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merged changes in axi

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This commit is contained in:
Alex Forencich 2023-03-30 00:13:02 -07:00
commit 047b1a4cec
2 changed files with 6 additions and 1 deletions
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6
fpga/lib/axi/rtl/axi_vfifo.v
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@ -415,10 +415,14 @@ for (n = 0; n < AXI_CH; n = n + 1) begin : axi_ch
// control sync
(* shreg_extract = "no" *)
reg ch_cfg_enable_sync_1_reg = 1'b0, ch_cfg_enable_sync_2_reg = 1'b0;
(* shreg_extract = "no" *)
reg ch_cfg_reset_sync_1_reg = 1'b0, ch_cfg_reset_sync_2_reg = 1'b0;
always @(posedge ch_clk) begin
ch_cfg_enable_sync_1_reg <= cfg_enable_reg;
ch_cfg_enable_sync_2_reg <= ch_cfg_enable_sync_1_reg;
ch_cfg_reset_sync_1_reg <= cfg_reset_reg;
ch_cfg_reset_sync_2_reg <= ch_cfg_reset_sync_1_reg;
end
// status sync
@ -535,7 +539,7 @@ for (n = 0; n < AXI_CH; n = n + 1) begin : axi_ch
.cfg_fifo_base_addr(cfg_fifo_base_addr_reg[AXI_ADDR_WIDTH*n +: AXI_ADDR_WIDTH]),
.cfg_fifo_size_mask(cfg_fifo_size_mask_reg),
.cfg_enable(ch_cfg_enable_sync_2_reg),
.cfg_reset(cfg_reset_reg),
.cfg_reset(ch_cfg_reset_sync_2_reg),
/*
* Status

1
fpga/lib/axi/syn/vivado/axi_vfifo.tcl
View File

@ -49,6 +49,7 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == axi_vfifo || REF_NAME =
# control
constrain_sync_chain $inst "cfg_enable_reg_reg" "axi_ch[*].ch_cfg_enable_sync_1_reg_reg" "axi_ch[*].ch_cfg_enable_sync_2_reg_reg"
constrain_sync_chain $inst "cfg_reset_reg_reg" "axi_ch[*].ch_cfg_reset_sync_1_reg_reg" "axi_ch[*].ch_cfg_reset_sync_2_reg_reg"
set sync_ffs [get_cells "$inst/cfg_fifo_base_addr_reg_reg[*] $inst/axi_ch[*].axi_vfifo_raw_inst/fifo_base_addr_reg_reg[*]"]