From 38915fb5330cb8270b454afc0140a94489dc56db Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 30 Mar 2023 00:12:13 -0700 Subject: [PATCH] Fix reset CDC in AXI VFIFO Signed-off-by: Alex Forencich --- rtl/axi_vfifo.v | 6 +++++- syn/vivado/axi_vfifo.tcl | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/rtl/axi_vfifo.v b/rtl/axi_vfifo.v index e8ae9fd5d..af0a781f8 100644 --- a/rtl/axi_vfifo.v +++ b/rtl/axi_vfifo.v @@ -415,10 +415,14 @@ for (n = 0; n < AXI_CH; n = n + 1) begin : axi_ch // control sync (* shreg_extract = "no" *) reg ch_cfg_enable_sync_1_reg = 1'b0, ch_cfg_enable_sync_2_reg = 1'b0; + (* shreg_extract = "no" *) + reg ch_cfg_reset_sync_1_reg = 1'b0, ch_cfg_reset_sync_2_reg = 1'b0; always @(posedge ch_clk) begin ch_cfg_enable_sync_1_reg <= cfg_enable_reg; ch_cfg_enable_sync_2_reg <= ch_cfg_enable_sync_1_reg; + ch_cfg_reset_sync_1_reg <= cfg_reset_reg; + ch_cfg_reset_sync_2_reg <= ch_cfg_reset_sync_1_reg; end // status sync @@ -535,7 +539,7 @@ for (n = 0; n < AXI_CH; n = n + 1) begin : axi_ch .cfg_fifo_base_addr(cfg_fifo_base_addr_reg[AXI_ADDR_WIDTH*n +: AXI_ADDR_WIDTH]), .cfg_fifo_size_mask(cfg_fifo_size_mask_reg), .cfg_enable(ch_cfg_enable_sync_2_reg), - .cfg_reset(cfg_reset_reg), + .cfg_reset(ch_cfg_reset_sync_2_reg), /* * Status diff --git a/syn/vivado/axi_vfifo.tcl b/syn/vivado/axi_vfifo.tcl index a93297b34..a3a062334 100644 --- a/syn/vivado/axi_vfifo.tcl +++ b/syn/vivado/axi_vfifo.tcl @@ -49,6 +49,7 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == axi_vfifo || REF_NAME = # control constrain_sync_chain $inst "cfg_enable_reg_reg" "axi_ch[*].ch_cfg_enable_sync_1_reg_reg" "axi_ch[*].ch_cfg_enable_sync_2_reg_reg" + constrain_sync_chain $inst "cfg_reset_reg_reg" "axi_ch[*].ch_cfg_reset_sync_1_reg_reg" "axi_ch[*].ch_cfg_reset_sync_2_reg_reg" set sync_ffs [get_cells "$inst/cfg_fifo_base_addr_reg_reg[*] $inst/axi_ch[*].axi_vfifo_raw_inst/fifo_base_addr_reg_reg[*]"]