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README.md
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README.md
@ -9,11 +9,12 @@ a high performance datapath, 10G/25G Ethernet, PCI express gen 3, a custom,
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high performance, tightly-integrated PCIe DMA engine, many (1000+) transmit,
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high performance, tightly-integrated PCIe DMA engine, many (1000+) transmit,
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receive, completion, and event queues, MSI interrupts, multiple interfaces,
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receive, completion, and event queues, MSI interrupts, multiple interfaces,
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multiple ports per interface, per-port transmit scheduling including high
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multiple ports per interface, per-port transmit scheduling including high
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precision TDMA, checksum offloading, and native IEEE 1588 PTP timestamping.
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precision TDMA, flow hashing, RSS, checksum offloading, and native IEEE 1588
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A Linux driver is included that integrates with the Linux networking stack.
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PTP timestamping. A Linux driver is included that integrates with the Linux
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Development and debugging is facilitated by an extensive simulation framwork
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networking stack. Development and debugging is facilitated by an extensive
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that covers the entire system from a simulation model of the driver and PCI
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simulation framework that covers the entire system from a simulation model of
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express interface on one side to the Ethernet interfaces on the other side.
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the driver and PCI express interface on one side to the Ethernet interfaces on
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the other side.
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Corundum has several unique architectural features. First, transmit, receive,
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Corundum has several unique architectural features. First, transmit, receive,
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completion, and event queue states are stored efficiently in block RAM or
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completion, and event queue states are stored efficiently in block RAM or
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@ -24,7 +25,7 @@ extremely fine-grained control over packet transmission. Coupled with PTP time
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synchronization, this enables high precision TDMA.
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synchronization, this enables high precision TDMA.
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Corundum currently supports Xilinx Ultrascale and Ultrascale Plus series
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Corundum currently supports Xilinx Ultrascale and Ultrascale Plus series
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devices. Desgins are included for the following FPGA boards:
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devices. Designs are included for the following FPGA boards:
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* Alpha Data ADM-PCIE-9V3 (Xilinx Virtex Ultrascale Plus XCVU3P)
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* Alpha Data ADM-PCIE-9V3 (Xilinx Virtex Ultrascale Plus XCVU3P)
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* Exablaze ExaNIC X10 (Xilinx Kintex Ultrascale XCKU035)
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* Exablaze ExaNIC X10 (Xilinx Kintex Ultrascale XCKU035)
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@ -88,6 +89,11 @@ Receive engine. Manages receive descriptor dequeue and fetch via DMA, packet
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reception, data writeback via DMA, and completion enqueue and writeback via
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reception, data writeback via DMA, and completion enqueue and writeback via
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DMA. Handles PTP timestamps for inclusion in completion records.
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DMA. Handles PTP timestamps for inclusion in completion records.
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#### rx_hash module
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Receive hash computation module. Extracts IP addresses and ports from packet
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headers and computes 32 bit Toeplitz flow hash.
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#### tdma_ber_ch module
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#### tdma_ber_ch module
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TDMA bit error ratio test channel module. Controls PRBS logic in Ethernet PHY
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TDMA bit error ratio test channel module. Controls PRBS logic in Ethernet PHY
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@ -140,6 +146,7 @@ packets.
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queue_manager.v : Queue manager
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queue_manager.v : Queue manager
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rx_checksum.v : Receive checksum offload
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rx_checksum.v : Receive checksum offload
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rx_engine.v : Receive engine
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rx_engine.v : Receive engine
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rx_hash.v : Receive hashing module
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tdma_ber_ch.v : TDMA BER channel
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tdma_ber_ch.v : TDMA BER channel
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tdma_ber.v : TDMA BER
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tdma_ber.v : TDMA BER
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tdma_scheduler.v : TDMA scheduler
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tdma_scheduler.v : TDMA scheduler
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