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fpga/common: Update port timing constraints to not mark ASYNC_REG on the first flip flop in the status sync chains for better placement flexibility

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-04-06 14:34:22 -07:00
parent c273b7f4ad
commit 04ede2e535
1 changed files with 1 additions and 1 deletions
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fpga/common/syn/vivado/mqnic_port.tcl
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@ -33,7 +33,7 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == mqnic_port || REF_NAME
puts "Inserting timing constraints for mqnic_port instance $inst"
proc constrain_slow_sync {inst driver args} {
set sync_ffs [get_cells -hier [concat $driver $args] -filter "PARENT == $inst"]
set sync_ffs [get_cells -hier $args -filter "PARENT == $inst"]
if {[llength $sync_ffs]} {
set_property ASYNC_REG TRUE $sync_ffs