From 04ede2e535bb1d2f29cdc822287f6fb33147eaaa Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 6 Apr 2023 14:34:22 -0700 Subject: [PATCH] fpga/common: Update port timing constraints to not mark ASYNC_REG on the first flip flop in the status sync chains for better placement flexibility Signed-off-by: Alex Forencich --- fpga/common/syn/vivado/mqnic_port.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/common/syn/vivado/mqnic_port.tcl b/fpga/common/syn/vivado/mqnic_port.tcl index 5b51cc91e..06bfd1451 100644 --- a/fpga/common/syn/vivado/mqnic_port.tcl +++ b/fpga/common/syn/vivado/mqnic_port.tcl @@ -33,7 +33,7 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == mqnic_port || REF_NAME puts "Inserting timing constraints for mqnic_port instance $inst" proc constrain_slow_sync {inst driver args} { - set sync_ffs [get_cells -hier [concat $driver $args] -filter "PARENT == $inst"] + set sync_ffs [get_cells -hier $args -filter "PARENT == $inst"] if {[llength $sync_ffs]} { set_property ASYNC_REG TRUE $sync_ffs