FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity

Update readme

Browse Source
This commit is contained in:
Alex Forencich 2014-11-05 16:19:00 -08:00
parent af0dce33b1
commit 0507fd4ca9
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README
View File

@ -1,2 +1,2 @@
Verilog ethernet components Verilog AXI Stream components