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Critical path optimization

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This commit is contained in:
Alex Forencich 2019-06-28 17:28:12 -07:00
parent 4afbd71f1f
commit 0515d354e3
1 changed files with 13 additions and 2 deletions
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15
rtl/pcie_us_axi_dma_rd.v
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@ -245,6 +245,7 @@ reg [AXI_ADDR_WIDTH-1:0] axi_addr_reg = {AXI_ADDR_WIDTH{1'b0}}, axi_addr_next;
reg axi_addr_valid_reg = 1'b0, axi_addr_valid_next; reg axi_addr_valid_reg = 1'b0, axi_addr_valid_next;
reg [9:0] op_dword_count_reg = 10'd0, op_dword_count_next; reg [9:0] op_dword_count_reg = 10'd0, op_dword_count_next;
reg [12:0] op_count_reg = 13'd0, op_count_next; reg [12:0] op_count_reg = 13'd0, op_count_next;
reg op_count_leq_axi_max_burst_reg = 1'b0, op_count_leq_axi_max_burst_next;
reg [12:0] tr_count_reg = 13'd0, tr_count_next; reg [12:0] tr_count_reg = 13'd0, tr_count_next;
reg [CYCLE_COUNT_WIDTH-1:0] input_cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, input_cycle_count_next; reg [CYCLE_COUNT_WIDTH-1:0] input_cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, input_cycle_count_next;
reg [CYCLE_COUNT_WIDTH-1:0] output_cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, output_cycle_count_next; reg [CYCLE_COUNT_WIDTH-1:0] output_cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, output_cycle_count_next;
@ -562,6 +563,7 @@ always @* begin
axi_addr_next = axi_addr_reg; axi_addr_next = axi_addr_reg;
axi_addr_valid_next = axi_addr_valid_reg; axi_addr_valid_next = axi_addr_valid_reg;
op_count_next = op_count_reg; op_count_next = op_count_reg;
op_count_leq_axi_max_burst_next = op_count_leq_axi_max_burst_reg;
tr_count_next = tr_count_reg; tr_count_next = tr_count_reg;
op_dword_count_next = op_dword_count_reg; op_dword_count_next = op_dword_count_reg;
input_cycle_count_next = input_cycle_count_reg; input_cycle_count_next = input_cycle_count_reg;
@ -648,6 +650,8 @@ always @* begin
first_cycle_offset_next = axi_addr_next[OFFSET_WIDTH-1:0]; first_cycle_offset_next = axi_addr_next[OFFSET_WIDTH-1:0];
first_cycle_next = 1'b1; first_cycle_next = 1'b1;
op_count_leq_axi_max_burst_next = op_count_next <= AXI_MAX_BURST_SIZE-axi_addr_next[1:0];
if (active_tags[pcie_tag_next] && error_code_next == RC_ERROR_NORMAL_TERMINATION) begin if (active_tags[pcie_tag_next] && error_code_next == RC_ERROR_NORMAL_TERMINATION) begin
// no error // no error
axi_addr_valid_next = !final_cpl_next; axi_addr_valid_next = !final_cpl_next;
@ -767,6 +771,8 @@ always @* begin
first_cycle_offset_next = axi_addr_next[OFFSET_WIDTH-1:0]; first_cycle_offset_next = axi_addr_next[OFFSET_WIDTH-1:0];
first_cycle_next = 1'b1; first_cycle_next = 1'b1;
op_count_leq_axi_max_burst_next = op_count_next <= AXI_MAX_BURST_SIZE-axi_addr_next[1:0];
if (active_tags[pcie_tag_next] && error_code_reg == RC_ERROR_NORMAL_TERMINATION) begin if (active_tags[pcie_tag_next] && error_code_reg == RC_ERROR_NORMAL_TERMINATION) begin
// no error // no error
axi_addr_valid_next = !final_cpl_next; axi_addr_valid_next = !final_cpl_next;
@ -825,7 +831,7 @@ always @* begin
if (s_axis_rc_tready && s_axis_rc_tvalid) begin if (s_axis_rc_tready && s_axis_rc_tvalid) begin
transfer_in_save = 1'b1; transfer_in_save = 1'b1;
if (op_count_reg <= AXI_MAX_BURST_SIZE-axi_addr_reg[1:0]) begin if (op_count_leq_axi_max_burst_reg) begin
// packet smaller than max burst size // packet smaller than max burst size
if (axi_addr_reg[12] != axi_addr_plus_op_count[12]) begin if (axi_addr_reg[12] != axi_addr_plus_op_count[12]) begin
// crosses 4k boundary // crosses 4k boundary
@ -862,6 +868,8 @@ always @* begin
axi_addr_next = axi_addr_reg + tr_count_next; axi_addr_next = axi_addr_reg + tr_count_next;
op_count_next = op_count_reg - tr_count_next; op_count_next = op_count_reg - tr_count_next;
op_count_leq_axi_max_burst_next = op_count_next <= AXI_MAX_BURST_SIZE-axi_addr_next[1:0];
input_active_next = input_cycle_count_next != 0; input_active_next = input_cycle_count_next != 0;
input_cycle_count_next = input_cycle_count_next - 1; input_cycle_count_next = input_cycle_count_next - 1;
s_axis_rc_tready_next = m_axi_wready_int_early && input_active_next && bubble_cycle_reg && (!last_cycle_next || op_count_next == 0 || !m_axi_awvalid || m_axi_awready); s_axis_rc_tready_next = m_axi_wready_int_early && input_active_next && bubble_cycle_reg && (!last_cycle_next || op_count_next == 0 || !m_axi_awvalid || m_axi_awready);
@ -908,7 +916,7 @@ always @* begin
tlp_state_next = TLP_STATE_TRANSFER; tlp_state_next = TLP_STATE_TRANSFER;
end else if (op_count_reg != 0) begin end else if (op_count_reg != 0) begin
// current transfer done, but operation not finished yet // current transfer done, but operation not finished yet
if (op_count_reg <= AXI_MAX_BURST_SIZE-axi_addr_reg[1:0]) begin if (op_count_leq_axi_max_burst_reg) begin
// packet smaller than max burst size // packet smaller than max burst size
if (axi_addr_reg[12] != axi_addr_plus_op_count[12]) begin if (axi_addr_reg[12] != axi_addr_plus_op_count[12]) begin
// crosses 4k boundary // crosses 4k boundary
@ -947,6 +955,8 @@ always @* begin
axi_addr_next = axi_addr_reg + tr_count_next; axi_addr_next = axi_addr_reg + tr_count_next;
op_count_next = op_count_reg - tr_count_next; op_count_next = op_count_reg - tr_count_next;
op_count_leq_axi_max_burst_next = op_count_next <= AXI_MAX_BURST_SIZE-axi_addr_next[1:0];
// enqueue status FIFO entry for write completion // enqueue status FIFO entry for write completion
status_fifo_we = 1'b1; status_fifo_we = 1'b1;
status_fifo_wr_tag = tag_table_tag[pcie_tag_reg]; status_fifo_wr_tag = tag_table_tag[pcie_tag_reg];
@ -1090,6 +1100,7 @@ always @(posedge clk) begin
error_code_reg <= error_code_next; error_code_reg <= error_code_next;
axi_addr_reg <= axi_addr_next; axi_addr_reg <= axi_addr_next;
op_count_reg <= op_count_next; op_count_reg <= op_count_next;
op_count_leq_axi_max_burst_reg <= op_count_leq_axi_max_burst_next;
tr_count_reg <= tr_count_next; tr_count_reg <= tr_count_next;
op_dword_count_reg <= op_dword_count_next; op_dword_count_reg <= op_dword_count_next;
input_cycle_count_reg <= input_cycle_count_next; input_cycle_count_reg <= input_cycle_count_next;