diff --git a/fpga/lib/eth/README.md b/fpga/lib/eth/README.md index b7f6e64aa..0ade5cedf 100644 --- a/fpga/lib/eth/README.md +++ b/fpga/lib/eth/README.md @@ -46,7 +46,7 @@ following boards: * Exablaze ExaNIC X10 (Xilinx Kintex UltraScale XCKU035) * Exablaze ExaNIC X25 (Xilinx Kintex UltraScale+ XCKU3P) * HiTech Global HTG-9200 (Xilinx UltraScale+ XCVU9P) -* HiTech Global HTG-V6HXT-100GIG-565 (Xilinx Virtex 6 XC6VHX565T) +* HiTech Global HTG-640 (HTG-V6HXT-100GIG-565) (Xilinx Virtex 6 XC6VHX565T) * Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P) * Xilinx KC705 (Xilinx Kintex 7 XC7K325T) * Xilinx ML605 (Xilinx Virtex 6 XC6VLX240T) diff --git a/fpga/lib/eth/example/520N_MX/fpga_10g/common/quartus_pro.mk b/fpga/lib/eth/example/520N_MX/fpga_10g/common/quartus_pro.mk index 1fc1b6fe8..f7e9cea62 100644 --- a/fpga/lib/eth/example/520N_MX/fpga_10g/common/quartus_pro.mk +++ b/fpga/lib/eth/example/520N_MX/fpga_10g/common/quartus_pro.mk @@ -39,7 +39,7 @@ CONFIG ?= config.mk -include ../$(CONFIG) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) IP_FILES_REL = $(patsubst %, ../%, $(IP_FILES)) IP_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_FILES))) @@ -48,13 +48,15 @@ IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) IP_TCL_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_TCL_FILES))) IP_TCL_FILES_IP_INT = $(patsubst %.tcl, ip/%.ip, $(notdir $(IP_TCL_FILES))) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) + ifdef QSF_FILES - QSF_FILES_REL = $(patsubst %, ../%, $(QSF_FILES)) + QSF_FILES_REL = $(foreach p,$(QSF_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else QSF_FILES_REL = ../$(FPGA_TOP).qsf endif -SDC_FILES_REL = $(patsubst %, ../%, $(SDC_FILES)) +SDC_FILES_REL = $(foreach p,$(SDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ASSIGNMENT_FILES = $(FPGA_TOP).qpf $(FPGA_TOP).qsf @@ -72,15 +74,16 @@ fpga: $(FPGA_TOP).sof quartus: $(FPGA_TOP).qpf quartus $(FPGA_TOP).qpf -tmpclean: +tmpclean:: -rm -rf defines.v -rm -rf *.rpt *.summary *.done *.smsg *.chg smart.log *.htm *.eqn *.pin *.qsf *.qpf *.sld *.txt *.qws *.stp -rm -rf ip db qdb incremental_db reconfig_mif tmp-clearbox synth_dumps .qsys_edit + -rm -rf create_project.tcl update_config.tcl update_ip_*.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.sof *.pof *.jdi *.jic *.map -distclean: clean +distclean:: clean -rm -rf rev syn: smart.log output_files/$(PROJECT).syn.rpt @@ -113,7 +116,8 @@ endef $(foreach l,$(IP_FILES_REL) $(IP_TCL_FILES_REL),$(eval $(call COPY_IP_RULE,$(l)))) define TCL_IP_GEN_RULE -$(patsubst %.tcl, %.ip, $(1)): $(1) +$(patsubst %.tcl,%.ip,$(1)): $(1) + cd ip && rm -f $(patsubst %.tcl,%,$(notdir $(1))).{qpf,qsf} cd ip && qsys-script --script=$(notdir $(1)) endef $(foreach l,$(IP_TCL_FILES_INT),$(eval $(call TCL_IP_GEN_RULE,$(l)))) @@ -149,25 +153,30 @@ smart.log: $(ASSIGNMENT_FILES) # Project initialization ################################################################### -$(ASSIGNMENT_FILES): $(QSF_FILES_REL) $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT) - rm -f $(FPGA_TOP).qsf - quartus_sh --prepare -f $(FPGA_FAMILY) -d $(FPGA_DEVICE) -t $(FPGA_TOP) $(FPGA_TOP) - echo >> $(FPGA_TOP).qsf - echo >> $(FPGA_TOP).qsf - echo "# Source files" >> $(FPGA_TOP).qsf +create_project.tcl: Makefile $(QSF_FILES_REL) | $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT) + rm -f update_config.tcl + echo "project_new $(FPGA_TOP) -overwrite" > $@ + echo "set_global_assignment -name FAMILY \"$(FPGA_FAMILY)\"" >> $@ + echo "set_global_assignment -name DEVICE \"$(FPGA_DEVICE)\"" >> $@ for x in $(SYN_FILES_REL) $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT); do \ case $${x##*.} in \ - v|V) echo set_global_assignment -name VERILOG_FILE $$x >> $(FPGA_TOP).qsf ;;\ - vhd|VHD) echo set_global_assignment -name VHDL_FILE $$x >> $(FPGA_TOP).qsf ;;\ - qip|QIP) echo set_global_assignment -name QIP_FILE $$x >> $(FPGA_TOP).qsf ;;\ - ip|IP) echo set_global_assignment -name IP_FILE $$x >> $(FPGA_TOP).qsf ;;\ - *) echo set_global_assignment -name SOURCE_FILE $$x >> $(FPGA_TOP).qsf ;;\ + v|V) echo set_global_assignment -name VERILOG_FILE "$$x" >> $@ ;;\ + vhd|VHD) echo set_global_assignment -name VHDL_FILE "$$x" >> $@ ;;\ + qip|QIP) echo set_global_assignment -name QIP_FILE "$$x" >> $@ ;;\ + ip|IP) echo set_global_assignment -name IP_FILE "$$x" >> $@ ;;\ + *) echo set_global_assignment -name SOURCE_FILE "$$x" >> $@ ;;\ esac; \ done - echo >> $(FPGA_TOP).qsf - echo "# SDC files" >> $(FPGA_TOP).qsf - for x in $(SDC_FILES_REL); do echo set_global_assignment -name SDC_FILE $$x >> $(FPGA_TOP).qsf; done - for x in $(QSF_FILES_REL); do printf "\n#\n# Included QSF file $$x\n#\n" >> $(FPGA_TOP).qsf; cat $$x >> $(FPGA_TOP).qsf; done + for x in $(SDC_FILES_REL); do echo set_global_assignment -name SDC_FILE "$$x" >> $@; done + for x in $(QSF_FILES_REL); do echo source "$$x" >> $@; done + +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) + echo "project_open $(FPGA_TOP)" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo source "$$x" >> $@; done + +$(ASSIGNMENT_FILES): create_project.tcl update_config.tcl + for x in $?; do quartus_sh -t "$$x"; done + touch -c $(ASSIGNMENT_FILES) syn.chg: $(STAMP) syn.chg diff --git a/fpga/lib/eth/example/520N_MX/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/520N_MX/fpga_10g/tb/fpga_core/test_fpga_core.py index ef7224c09..df2b0cc67 100644 --- a/fpga/lib/eth/example/520N_MX/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/520N_MX/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -48,195 +48,47 @@ class TB: cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) # Ethernet - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_1, 6.4, units="ns").start()) - self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1, dut.qsfp0_rx_clk_1, dut.qsfp0_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_1, 6.4, units="ns").start()) - self.qsfp0_1_sink = XgmiiSink(dut.qsfp0_txd_1, dut.qsfp0_txc_1, dut.qsfp0_tx_clk_1, dut.qsfp0_tx_rst_1) + self.qsfp_source = [] + self.qsfp_sink = [] - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_2, 6.4, units="ns").start()) - self.qsfp0_2_source = XgmiiSource(dut.qsfp0_rxd_2, dut.qsfp0_rxc_2, dut.qsfp0_rx_clk_2, dut.qsfp0_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_2, 6.4, units="ns").start()) - self.qsfp0_2_sink = XgmiiSink(dut.qsfp0_txd_2, dut.qsfp0_txc_2, dut.qsfp0_tx_clk_2, dut.qsfp0_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_3, 6.4, units="ns").start()) - self.qsfp0_3_source = XgmiiSource(dut.qsfp0_rxd_3, dut.qsfp0_rxc_3, dut.qsfp0_rx_clk_3, dut.qsfp0_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_3, 6.4, units="ns").start()) - self.qsfp0_3_sink = XgmiiSink(dut.qsfp0_txd_3, dut.qsfp0_txc_3, dut.qsfp0_tx_clk_3, dut.qsfp0_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_4, 6.4, units="ns").start()) - self.qsfp0_4_source = XgmiiSource(dut.qsfp0_rxd_4, dut.qsfp0_rxc_4, dut.qsfp0_rx_clk_4, dut.qsfp0_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_4, 6.4, units="ns").start()) - self.qsfp0_4_sink = XgmiiSink(dut.qsfp0_txd_4, dut.qsfp0_txc_4, dut.qsfp0_tx_clk_4, dut.qsfp0_tx_rst_4) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_1, 6.4, units="ns").start()) - self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_1, 6.4, units="ns").start()) - self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_2, 6.4, units="ns").start()) - self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_2, 6.4, units="ns").start()) - self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_3, 6.4, units="ns").start()) - self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_3, 6.4, units="ns").start()) - self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_4, 6.4, units="ns").start()) - self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 6.4, units="ns").start()) - self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4) - - cocotb.start_soon(Clock(dut.qsfp2_rx_clk_1, 6.4, units="ns").start()) - self.qsfp2_1_source = XgmiiSource(dut.qsfp2_rxd_1, dut.qsfp2_rxc_1, dut.qsfp2_rx_clk_1, dut.qsfp2_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp2_tx_clk_1, 6.4, units="ns").start()) - self.qsfp2_1_sink = XgmiiSink(dut.qsfp2_txd_1, dut.qsfp2_txc_1, dut.qsfp2_tx_clk_1, dut.qsfp2_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp2_rx_clk_2, 6.4, units="ns").start()) - self.qsfp2_2_source = XgmiiSource(dut.qsfp2_rxd_2, dut.qsfp2_rxc_2, dut.qsfp2_rx_clk_2, dut.qsfp2_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp2_tx_clk_2, 6.4, units="ns").start()) - self.qsfp2_2_sink = XgmiiSink(dut.qsfp2_txd_2, dut.qsfp2_txc_2, dut.qsfp2_tx_clk_2, dut.qsfp2_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp2_rx_clk_3, 6.4, units="ns").start()) - self.qsfp2_3_source = XgmiiSource(dut.qsfp2_rxd_3, dut.qsfp2_rxc_3, dut.qsfp2_rx_clk_3, dut.qsfp2_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp2_tx_clk_3, 6.4, units="ns").start()) - self.qsfp2_3_sink = XgmiiSink(dut.qsfp2_txd_3, dut.qsfp2_txc_3, dut.qsfp2_tx_clk_3, dut.qsfp2_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp2_rx_clk_4, 6.4, units="ns").start()) - self.qsfp2_4_source = XgmiiSource(dut.qsfp2_rxd_4, dut.qsfp2_rxc_4, dut.qsfp2_rx_clk_4, dut.qsfp2_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp2_tx_clk_4, 6.4, units="ns").start()) - self.qsfp2_4_sink = XgmiiSink(dut.qsfp2_txd_4, dut.qsfp2_txc_4, dut.qsfp2_tx_clk_4, dut.qsfp2_tx_rst_4) - - cocotb.start_soon(Clock(dut.qsfp3_rx_clk_1, 6.4, units="ns").start()) - self.qsfp3_1_source = XgmiiSource(dut.qsfp3_rxd_1, dut.qsfp3_rxc_1, dut.qsfp3_rx_clk_1, dut.qsfp3_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp3_tx_clk_1, 6.4, units="ns").start()) - self.qsfp3_1_sink = XgmiiSink(dut.qsfp3_txd_1, dut.qsfp3_txc_1, dut.qsfp3_tx_clk_1, dut.qsfp3_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp3_rx_clk_2, 6.4, units="ns").start()) - self.qsfp3_2_source = XgmiiSource(dut.qsfp3_rxd_2, dut.qsfp3_rxc_2, dut.qsfp3_rx_clk_2, dut.qsfp3_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp3_tx_clk_2, 6.4, units="ns").start()) - self.qsfp3_2_sink = XgmiiSink(dut.qsfp3_txd_2, dut.qsfp3_txc_2, dut.qsfp3_tx_clk_2, dut.qsfp3_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp3_rx_clk_3, 6.4, units="ns").start()) - self.qsfp3_3_source = XgmiiSource(dut.qsfp3_rxd_3, dut.qsfp3_rxc_3, dut.qsfp3_rx_clk_3, dut.qsfp3_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp3_tx_clk_3, 6.4, units="ns").start()) - self.qsfp3_3_sink = XgmiiSink(dut.qsfp3_txd_3, dut.qsfp3_txc_3, dut.qsfp3_tx_clk_3, dut.qsfp3_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp3_rx_clk_4, 6.4, units="ns").start()) - self.qsfp3_4_source = XgmiiSource(dut.qsfp3_rxd_4, dut.qsfp3_rxc_4, dut.qsfp3_rx_clk_4, dut.qsfp3_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp3_tx_clk_4, 6.4, units="ns").start()) - self.qsfp3_4_sink = XgmiiSink(dut.qsfp3_txd_4, dut.qsfp3_txc_4, dut.qsfp3_tx_clk_4, dut.qsfp3_tx_rst_4) + for x in range(4): + sources = [] + sinks = [] + for y in range(1, 5): + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_rx_clk_{y}"), 6.4, units="ns").start()) + source = XgmiiSource(getattr(dut, f"qsfp{x}_rxd_{y}"), getattr(dut, f"qsfp{x}_rxc_{y}"), getattr(dut, f"qsfp{x}_rx_clk_{y}"), getattr(dut, f"qsfp{x}_rx_rst_{y}")) + sources.append(source) + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_tx_clk_{y}"), 6.4, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"qsfp{x}_txd_{y}"), getattr(dut, f"qsfp{x}_txc_{y}"), getattr(dut, f"qsfp{x}_tx_clk_{y}"), getattr(dut, f"qsfp{x}_tx_rst_{y}")) + sinks.append(sink) + self.qsfp_source.append(sources) + self.qsfp_sink.append(sinks) async def init(self): self.dut.rst.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_4.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) - self.dut.qsfp2_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp2_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp2_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp2_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp2_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp2_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp2_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp2_tx_rst_4.setimmediatevalue(0) - self.dut.qsfp3_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp3_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp3_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp3_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp3_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp3_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp3_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp3_tx_rst_4.setimmediatevalue(0) + for x in range(4): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(0) + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(0) for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 1 - self.dut.qsfp0_rx_rst_1.value = 1 - self.dut.qsfp0_tx_rst_1.value = 1 - self.dut.qsfp0_rx_rst_2.value = 1 - self.dut.qsfp0_tx_rst_2.value = 1 - self.dut.qsfp0_rx_rst_3.value = 1 - self.dut.qsfp0_tx_rst_3.value = 1 - self.dut.qsfp0_rx_rst_4.value = 1 - self.dut.qsfp0_tx_rst_4.value = 1 - self.dut.qsfp1_rx_rst_1.value = 1 - self.dut.qsfp1_tx_rst_1.value = 1 - self.dut.qsfp1_rx_rst_2.value = 1 - self.dut.qsfp1_tx_rst_2.value = 1 - self.dut.qsfp1_rx_rst_3.value = 1 - self.dut.qsfp1_tx_rst_3.value = 1 - self.dut.qsfp1_rx_rst_4.value = 1 - self.dut.qsfp1_tx_rst_4.value = 1 - self.dut.qsfp2_rx_rst_1.value = 1 - self.dut.qsfp2_tx_rst_1.value = 1 - self.dut.qsfp2_rx_rst_2.value = 1 - self.dut.qsfp2_tx_rst_2.value = 1 - self.dut.qsfp2_rx_rst_3.value = 1 - self.dut.qsfp2_tx_rst_3.value = 1 - self.dut.qsfp2_rx_rst_4.value = 1 - self.dut.qsfp2_tx_rst_4.value = 1 - self.dut.qsfp3_rx_rst_1.value = 1 - self.dut.qsfp3_tx_rst_1.value = 1 - self.dut.qsfp3_rx_rst_2.value = 1 - self.dut.qsfp3_tx_rst_2.value = 1 - self.dut.qsfp3_rx_rst_3.value = 1 - self.dut.qsfp3_tx_rst_3.value = 1 - self.dut.qsfp3_rx_rst_4.value = 1 - self.dut.qsfp3_tx_rst_4.value = 1 + for x in range(4): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").value = 1 + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").value = 1 for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 0 - self.dut.qsfp0_rx_rst_1.value = 0 - self.dut.qsfp0_tx_rst_1.value = 0 - self.dut.qsfp0_rx_rst_2.value = 0 - self.dut.qsfp0_tx_rst_2.value = 0 - self.dut.qsfp0_rx_rst_3.value = 0 - self.dut.qsfp0_tx_rst_3.value = 0 - self.dut.qsfp0_rx_rst_4.value = 0 - self.dut.qsfp0_tx_rst_4.value = 0 - self.dut.qsfp1_rx_rst_1.value = 0 - self.dut.qsfp1_tx_rst_1.value = 0 - self.dut.qsfp1_rx_rst_2.value = 0 - self.dut.qsfp1_tx_rst_2.value = 0 - self.dut.qsfp1_rx_rst_3.value = 0 - self.dut.qsfp1_tx_rst_3.value = 0 - self.dut.qsfp1_rx_rst_4.value = 0 - self.dut.qsfp1_tx_rst_4.value = 0 - self.dut.qsfp2_rx_rst_1.value = 0 - self.dut.qsfp2_tx_rst_1.value = 0 - self.dut.qsfp2_rx_rst_2.value = 0 - self.dut.qsfp2_tx_rst_2.value = 0 - self.dut.qsfp2_rx_rst_3.value = 0 - self.dut.qsfp2_tx_rst_3.value = 0 - self.dut.qsfp2_rx_rst_4.value = 0 - self.dut.qsfp2_tx_rst_4.value = 0 - self.dut.qsfp3_rx_rst_1.value = 0 - self.dut.qsfp3_tx_rst_1.value = 0 - self.dut.qsfp3_rx_rst_2.value = 0 - self.dut.qsfp3_tx_rst_2.value = 0 - self.dut.qsfp3_rx_rst_3.value = 0 - self.dut.qsfp3_tx_rst_3.value = 0 - self.dut.qsfp3_rx_rst_4.value = 0 - self.dut.qsfp3_tx_rst_4.value = 0 + for x in range(4): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").value = 0 + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").value = 0 @cocotb.test() @@ -256,11 +108,11 @@ async def run_test(dut): test_frame = XgmiiFrame.from_payload(test_pkt.build()) - await tb.qsfp0_1_source.send(test_frame) + await tb.qsfp_source[0][0].send(test_frame) tb.log.info("receive ARP request") - rx_frame = await tb.qsfp0_1_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -288,11 +140,11 @@ async def run_test(dut): resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - await tb.qsfp0_1_source.send(resp_frame) + await tb.qsfp_source[0][0].send(resp_frame) tb.log.info("receive UDP packet") - rx_frame = await tb.qsfp0_1_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/README.md b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/README.md deleted file mode 100644 index 10a48174c..000000000 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/README.md +++ /dev/null @@ -1,30 +0,0 @@ -# Verilog Ethernet ADM-PCIE-9V3 Example Design - -## Introduction - -This example design targets the Alpha Data ADM-PCIE-9V3 FPGA board. - -The design by default listens to UDP port 1234 at IP address 192.168.1.128 and -will echo back any packets received. The design will also respond correctly -to ARP requests. - -* FPGA: xcvu3p-ffvc1517-2-i -* PHY: 10G BASE-R PHY IP core and internal GTY transceiver - -## How to build - -Run make to build. Ensure that the Xilinx Vivado toolchain components are -in PATH. - -## How to test - -Run make program to program the ADM-PCIE-9V3 board with Vivado. Then run - - netcat -u 192.168.1.128 1234 - -to open a UDP connection to port 1234. Any text entered into netcat will be -echoed back after pressing enter. - -It is also possible to use hping to test the design by running - - hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/fpga.xdc b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/fpga.xdc deleted file mode 100644 index 5718ae810..000000000 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/fpga.xdc +++ /dev/null @@ -1,206 +0,0 @@ -# XDC constraints for the ADM-PCIE-9V3 -# part: xcvu3p-ffvc1517-2-i - -# General configuration -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] -set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] -set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design] -set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] - -# 300 MHz system clock -set_property -dict {LOC AP26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_p] -set_property -dict {LOC AP27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_n] -create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p] - -# LEDs -set_property -dict {LOC AT27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[0]}] -set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[1]}] -set_property -dict {LOC AU23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_r}] -set_property -dict {LOC AH24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {front_led[0]}] -set_property -dict {LOC AJ23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {front_led[1]}] - -set_false_path -to [get_ports {user_led_g[*] user_led_r front_led[*]}] -set_output_delay 0 [get_ports {user_led_g[*] user_led_r front_led[*]}] - -# Switches -set_property -dict {LOC AV27 IOSTANDARD LVCMOS18} [get_ports {user_sw[0]}] -set_property -dict {LOC AW27 IOSTANDARD LVCMOS18} [get_ports {user_sw[1]}] - -set_false_path -from [get_ports {user_sw[*]}] -set_input_delay 0 [get_ports {user_sw[*]}] - -# GPIO -#set_property -dict {LOC G30 IOSTANDARD LVCMOS18} [get_ports gpio_p[0]] -#set_property -dict {LOC F30 IOSTANDARD LVCMOS18} [get_ports gpio_n[0]] -#set_property -dict {LOC J31 IOSTANDARD LVCMOS18} [get_ports gpio_p[1]] -#set_property -dict {LOC H31 IOSTANDARD LVCMOS18} [get_ports gpio_n[1]] - -# QSFP28 Interfaces -set_property -dict {LOC G38 } [get_ports qsfp_0_rx_0_p] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC G39 } [get_ports qsfp_0_rx_0_n] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC F35 } [get_ports qsfp_0_tx_0_p] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC F36 } [get_ports qsfp_0_tx_0_n] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC E38 } [get_ports qsfp_0_rx_1_p] ;# MGTYRXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC E39 } [get_ports qsfp_0_rx_1_n] ;# MGTYRXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC D35 } [get_ports qsfp_0_tx_1_p] ;# MGTYTXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC D36 } [get_ports qsfp_0_tx_1_n] ;# MGTYTXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC C38 } [get_ports qsfp_0_rx_2_p] ;# MGTYRXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC C39 } [get_ports qsfp_0_rx_2_n] ;# MGTYRXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC C33 } [get_ports qsfp_0_tx_2_p] ;# MGTYTXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC C34 } [get_ports qsfp_0_tx_2_n] ;# MGTYTXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC B36 } [get_ports qsfp_0_rx_3_p] ;# MGTYRXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC B37 } [get_ports qsfp_0_rx_3_n] ;# MGTYRXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC A33 } [get_ports qsfp_0_tx_3_p] ;# MGTYTXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC A34 } [get_ports qsfp_0_tx_3_n] ;# MGTYTXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 -set_property -dict {LOC N33 } [get_ports qsfp_0_mgt_refclk_p] ;# MGTREFCLK0P_128 from ? -set_property -dict {LOC N34 } [get_ports qsfp_0_mgt_refclk_n] ;# MGTREFCLK0N_128 from ? -set_property -dict {LOC F29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_0_modprs_l] -set_property -dict {LOC D31 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_0_sel_l] - -# 161.1328125 MHz MGT reference clock -create_clock -period 6.206 -name qsfp_0_mgt_refclk [get_ports qsfp_0_mgt_refclk_p] - -set_property -dict {LOC R38 } [get_ports qsfp_1_rx_0_p] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC R39 } [get_ports qsfp_1_rx_0_n] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC P35 } [get_ports qsfp_1_tx_0_p] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC P36 } [get_ports qsfp_1_tx_0_n] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC N38 } [get_ports qsfp_1_rx_1_p] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC N39 } [get_ports qsfp_1_rx_1_n] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC M35 } [get_ports qsfp_1_tx_1_p] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC M36 } [get_ports qsfp_1_tx_1_n] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC L38 } [get_ports qsfp_1_rx_2_p] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC L39 } [get_ports qsfp_1_rx_2_n] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC K35 } [get_ports qsfp_1_tx_2_p] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC K36 } [get_ports qsfp_1_tx_2_n] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC J38 } [get_ports qsfp_1_rx_3_p] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC J39 } [get_ports qsfp_1_rx_3_n] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC H35 } [get_ports qsfp_1_tx_3_p] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC H36 } [get_ports qsfp_1_tx_3_n] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC U33 } [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_127 from ? -set_property -dict {LOC U34 } [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_127 from ? -set_property -dict {LOC F33 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_1_modprs_l] -set_property -dict {LOC D30 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_1_sel_l] - -# 161.1328125 MHz MGT reference clock -create_clock -period 6.206 -name qsfp_1_mgt_refclk [get_ports qsfp_1_mgt_refclk_p] - -set_property -dict {LOC B29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_reset_l] -set_property -dict {LOC C29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_int_l] -#set_property -dict {LOC A28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports qsfp_i2c_scl] -#set_property -dict {LOC A29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports qsfp_i2c_sda] - -set_false_path -to [get_ports {qsfp_0_sel_l qsfp_1_sel_l qsfp_reset_l}] -set_output_delay 0 [get_ports {qsfp_0_sel_l qsfp_1_sel_l qsfp_reset_l}] -set_false_path -from [get_ports {qsfp_0_modprs_l qsfp_1_modprs_l qsfp_int_l}] -set_input_delay 0 [get_ports {qsfp_0_modprs_l qsfp_1_modprs_l qsfp_int_l}] - -#set_false_path -to [get_ports {qsfp_i2c_sda qsfp_i2c_scl}] -#set_output_delay 0 [get_ports {qsfp_i2c_sda qsfp_i2c_scl}] -#set_false_path -from [get_ports {qsfp_i2c_sda qsfp_i2c_scl}] -#set_input_delay 0 [get_ports {qsfp_i2c_sda qsfp_i2c_scl}] - -# I2C interface -#set_property -dict {LOC AT25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_scl] -#set_property -dict {LOC AT26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_sda] -#set_property -dict {LOC AP23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_wp] - -#set_false_path -to [get_ports {eeprom_i2c_sda eeprom_i2c_scl eeprom_wp}] -#set_output_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl eeprom_wp}] -#set_false_path -from [get_ports {eeprom_i2c_sda eeprom_i2c_scl}] -#set_input_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}] - -# PCIe Interface -#set_property -dict {LOC J2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC J1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC H5 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC H4 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC L2 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC L1 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC K5 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC K4 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC N2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC N1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC M5 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC M4 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC R2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC R1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC P5 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC P4 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC U2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC U1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC T5 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC T4 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC W2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC W1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC V5 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC V4 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AA2 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AA1 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AB5 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AB4 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AC2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AC1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AD5 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AD4 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AE2 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AE1 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AF5 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AF4 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AG2 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AG1 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AH5 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AH4 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AJ2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AJ1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AK5 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AK4 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AM5 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AM4 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AP5 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AP4 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AT5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AT4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AU2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AU1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AU7 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AU6 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AV4 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AV3 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AW7 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AW6 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AA7 } [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_226 -#set_property -dict {LOC AA6 } [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_226 -#set_property -dict {LOC AJ7 } [get_ports pcie_refclk_2_p] ;# MGTREFCLK0P_224 -#set_property -dict {LOC AJ6 } [get_ports pcie_refclk_2_n] ;# MGTREFCLK0N_224 -#set_property -dict {LOC AJ31 IOSTANDARD LVCMOS18 PULLUP true} [get_ports perst_0] -#set_property -dict {LOC AH29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports perst_1] - -# 100 MHz MGT reference clock -#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p] -#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports pcie_refclk_2_p] - -#set_false_path -from [get_ports {perst_0}] -#set_input_delay 0 [get_ports {perst_0}] - -# QSPI flash -#set_property -dict {LOC AF30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}] -#set_property -dict {LOC AG30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}] -#set_property -dict {LOC AF28 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[2]}] -#set_property -dict {LOC AG28 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[3]}] -#set_property -dict {LOC AV30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_cs}] - -#set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}] -#set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}] -#set_false_path -from [get_ports {qspi_1_dq}] -#set_input_delay 0 [get_ports {qspi_1_dq}] diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v deleted file mode 100644 index f8152c851..000000000 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v +++ /dev/null @@ -1,796 +0,0 @@ -/* - -Copyright (c) 2014-2021 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA top-level module - */ -module fpga ( - /* - * Clock: 300MHz LVDS - */ - input wire clk_300mhz_p, - input wire clk_300mhz_n, - - /* - * GPIO - */ - output wire [1:0] user_led_g, - output wire user_led_r, - output wire [1:0] front_led, - input wire [1:0] user_sw, - - /* - * Ethernet: QSFP28 - */ - output wire qsfp_0_tx_0_p, - output wire qsfp_0_tx_0_n, - input wire qsfp_0_rx_0_p, - input wire qsfp_0_rx_0_n, - output wire qsfp_0_tx_1_p, - output wire qsfp_0_tx_1_n, - input wire qsfp_0_rx_1_p, - input wire qsfp_0_rx_1_n, - output wire qsfp_0_tx_2_p, - output wire qsfp_0_tx_2_n, - input wire qsfp_0_rx_2_p, - input wire qsfp_0_rx_2_n, - output wire qsfp_0_tx_3_p, - output wire qsfp_0_tx_3_n, - input wire qsfp_0_rx_3_p, - input wire qsfp_0_rx_3_n, - input wire qsfp_0_mgt_refclk_p, - input wire qsfp_0_mgt_refclk_n, - input wire qsfp_0_modprs_l, - output wire qsfp_0_sel_l, - - output wire qsfp_1_tx_0_p, - output wire qsfp_1_tx_0_n, - input wire qsfp_1_rx_0_p, - input wire qsfp_1_rx_0_n, - output wire qsfp_1_tx_1_p, - output wire qsfp_1_tx_1_n, - input wire qsfp_1_rx_1_p, - input wire qsfp_1_rx_1_n, - output wire qsfp_1_tx_2_p, - output wire qsfp_1_tx_2_n, - input wire qsfp_1_rx_2_p, - input wire qsfp_1_rx_2_n, - output wire qsfp_1_tx_3_p, - output wire qsfp_1_tx_3_n, - input wire qsfp_1_rx_3_p, - input wire qsfp_1_rx_3_n, - input wire qsfp_1_mgt_refclk_p, - input wire qsfp_1_mgt_refclk_n, - input wire qsfp_1_modprs_l, - output wire qsfp_1_sel_l, - - output wire qsfp_reset_l, - input wire qsfp_int_l -); - -// Clock and reset - -wire clk_300mhz_ibufg; - -// Internal 125 MHz clock -wire clk_125mhz_mmcm_out; -wire clk_125mhz_int; -wire rst_125mhz_int; - -// Internal 156.25 MHz clock -wire clk_156mhz_int; -wire rst_156mhz_int; - -wire mmcm_rst = 1'b0; -wire mmcm_locked; -wire mmcm_clkfb; - -IBUFGDS #( - .DIFF_TERM("FALSE"), - .IBUF_LOW_PWR("FALSE") -) -clk_300mhz_ibufg_inst ( - .O (clk_300mhz_ibufg), - .I (clk_300mhz_p), - .IB (clk_300mhz_n) -); - -// MMCM instance -// 300 MHz in, 125 MHz out -// PFD range: 10 MHz to 500 MHz -// VCO range: 800 MHz to 1600 MHz -// M = 10, D = 3 sets Fvco = 1000 MHz (in range) -// Divide by 8 to get output frequency of 125 MHz -MMCME3_BASE #( - .BANDWIDTH("OPTIMIZED"), - .CLKOUT0_DIVIDE_F(8), - .CLKOUT0_DUTY_CYCLE(0.5), - .CLKOUT0_PHASE(0), - .CLKOUT1_DIVIDE(1), - .CLKOUT1_DUTY_CYCLE(0.5), - .CLKOUT1_PHASE(0), - .CLKOUT2_DIVIDE(1), - .CLKOUT2_DUTY_CYCLE(0.5), - .CLKOUT2_PHASE(0), - .CLKOUT3_DIVIDE(1), - .CLKOUT3_DUTY_CYCLE(0.5), - .CLKOUT3_PHASE(0), - .CLKOUT4_DIVIDE(1), - .CLKOUT4_DUTY_CYCLE(0.5), - .CLKOUT4_PHASE(0), - .CLKOUT5_DIVIDE(1), - .CLKOUT5_DUTY_CYCLE(0.5), - .CLKOUT5_PHASE(0), - .CLKOUT6_DIVIDE(1), - .CLKOUT6_DUTY_CYCLE(0.5), - .CLKOUT6_PHASE(0), - .CLKFBOUT_MULT_F(10), - .CLKFBOUT_PHASE(0), - .DIVCLK_DIVIDE(3), - .REF_JITTER1(0.010), - .CLKIN1_PERIOD(3.333), - .STARTUP_WAIT("FALSE"), - .CLKOUT4_CASCADE("FALSE") -) -clk_mmcm_inst ( - .CLKIN1(clk_300mhz_ibufg), - .CLKFBIN(mmcm_clkfb), - .RST(mmcm_rst), - .PWRDWN(1'b0), - .CLKOUT0(clk_125mhz_mmcm_out), - .CLKOUT0B(), - .CLKOUT1(), - .CLKOUT1B(), - .CLKOUT2(), - .CLKOUT2B(), - .CLKOUT3(), - .CLKOUT3B(), - .CLKOUT4(), - .CLKOUT5(), - .CLKOUT6(), - .CLKFBOUT(mmcm_clkfb), - .CLKFBOUTB(), - .LOCKED(mmcm_locked) -); - -BUFG -clk_125mhz_bufg_inst ( - .I(clk_125mhz_mmcm_out), - .O(clk_125mhz_int) -); - -sync_reset #( - .N(4) -) -sync_reset_125mhz_inst ( - .clk(clk_125mhz_int), - .rst(~mmcm_locked), - .out(rst_125mhz_int) -); - -// GPIO -wire [1:0] user_sw_int; - -debounce_switch #( - .WIDTH(2), - .N(4), - .RATE(125000) -) -debounce_switch_inst ( - .clk(clk_125mhz_int), - .rst(rst_125mhz_int), - .in({user_sw}), - .out({user_sw_int}) -); - -// XGMII 10G PHY - -assign qsfp_reset_l = 1'b1; - -// QSFP 0 -assign qsfp_0_sel_l = 1'b0; - -wire qsfp_0_tx_clk_0_int; -wire qsfp_0_tx_rst_0_int; -wire [63:0] qsfp_0_txd_0_int; -wire [7:0] qsfp_0_txc_0_int; -wire qsfp_0_rx_clk_0_int; -wire qsfp_0_rx_rst_0_int; -wire [63:0] qsfp_0_rxd_0_int; -wire [7:0] qsfp_0_rxc_0_int; -wire qsfp_0_tx_clk_1_int; -wire qsfp_0_tx_rst_1_int; -wire [63:0] qsfp_0_txd_1_int; -wire [7:0] qsfp_0_txc_1_int; -wire qsfp_0_rx_clk_1_int; -wire qsfp_0_rx_rst_1_int; -wire [63:0] qsfp_0_rxd_1_int; -wire [7:0] qsfp_0_rxc_1_int; -wire qsfp_0_tx_clk_2_int; -wire qsfp_0_tx_rst_2_int; -wire [63:0] qsfp_0_txd_2_int; -wire [7:0] qsfp_0_txc_2_int; -wire qsfp_0_rx_clk_2_int; -wire qsfp_0_rx_rst_2_int; -wire [63:0] qsfp_0_rxd_2_int; -wire [7:0] qsfp_0_rxc_2_int; -wire qsfp_0_tx_clk_3_int; -wire qsfp_0_tx_rst_3_int; -wire [63:0] qsfp_0_txd_3_int; -wire [7:0] qsfp_0_txc_3_int; -wire qsfp_0_rx_clk_3_int; -wire qsfp_0_rx_rst_3_int; -wire [63:0] qsfp_0_rxd_3_int; -wire [7:0] qsfp_0_rxc_3_int; - -assign clk_156mhz_int = qsfp_0_tx_clk_0_int; -assign rst_156mhz_int = qsfp_0_tx_rst_0_int; - -wire qsfp_0_rx_block_lock_0; -wire qsfp_0_rx_block_lock_1; -wire qsfp_0_rx_block_lock_2; -wire qsfp_0_rx_block_lock_3; - -wire qsfp_0_mgt_refclk; - -IBUFDS_GTE4 ibufds_gte4_qsfp_0_mgt_refclk_inst ( - .I (qsfp_0_mgt_refclk_p), - .IB (qsfp_0_mgt_refclk_n), - .CEB (1'b0), - .O (qsfp_0_mgt_refclk), - .ODIV2 () -); - -wire qsfp_0_qpll0lock; -wire qsfp_0_qpll0outclk; -wire qsfp_0_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_0_phy_0_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(qsfp_0_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_0_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_0_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_0_qpll0outrefclk), - - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), - - // Serial data - .xcvr_txp(qsfp_0_tx_0_p), - .xcvr_txn(qsfp_0_tx_0_n), - .xcvr_rxp(qsfp_0_rx_0_p), - .xcvr_rxn(qsfp_0_rx_0_n), - - // PHY connections - .phy_tx_clk(qsfp_0_tx_clk_0_int), - .phy_tx_rst(qsfp_0_tx_rst_0_int), - .phy_xgmii_txd(qsfp_0_txd_0_int), - .phy_xgmii_txc(qsfp_0_txc_0_int), - .phy_rx_clk(qsfp_0_rx_clk_0_int), - .phy_rx_rst(qsfp_0_rx_rst_0_int), - .phy_xgmii_rxd(qsfp_0_rxd_0_int), - .phy_xgmii_rxc(qsfp_0_rxc_0_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_0_rx_block_lock_0), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_0_phy_1_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_0_tx_1_p), - .xcvr_txn(qsfp_0_tx_1_n), - .xcvr_rxp(qsfp_0_rx_1_p), - .xcvr_rxn(qsfp_0_rx_1_n), - - // PHY connections - .phy_tx_clk(qsfp_0_tx_clk_1_int), - .phy_tx_rst(qsfp_0_tx_rst_1_int), - .phy_xgmii_txd(qsfp_0_txd_1_int), - .phy_xgmii_txc(qsfp_0_txc_1_int), - .phy_rx_clk(qsfp_0_rx_clk_1_int), - .phy_rx_rst(qsfp_0_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_0_rxd_1_int), - .phy_xgmii_rxc(qsfp_0_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_0_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_0_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_0_tx_2_p), - .xcvr_txn(qsfp_0_tx_2_n), - .xcvr_rxp(qsfp_0_rx_2_p), - .xcvr_rxn(qsfp_0_rx_2_n), - - // PHY connections - .phy_tx_clk(qsfp_0_tx_clk_2_int), - .phy_tx_rst(qsfp_0_tx_rst_2_int), - .phy_xgmii_txd(qsfp_0_txd_2_int), - .phy_xgmii_txc(qsfp_0_txc_2_int), - .phy_rx_clk(qsfp_0_rx_clk_2_int), - .phy_rx_rst(qsfp_0_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_0_rxd_2_int), - .phy_xgmii_rxc(qsfp_0_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_0_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_0_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_0_tx_3_p), - .xcvr_txn(qsfp_0_tx_3_n), - .xcvr_rxp(qsfp_0_rx_3_p), - .xcvr_rxn(qsfp_0_rx_3_n), - - // PHY connections - .phy_tx_clk(qsfp_0_tx_clk_3_int), - .phy_tx_rst(qsfp_0_tx_rst_3_int), - .phy_xgmii_txd(qsfp_0_txd_3_int), - .phy_xgmii_txc(qsfp_0_txc_3_int), - .phy_rx_clk(qsfp_0_rx_clk_3_int), - .phy_rx_rst(qsfp_0_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_0_rxd_3_int), - .phy_xgmii_rxc(qsfp_0_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_0_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -// QSFP 1 -assign qsfp_1_sel_l = 1'b0; - -wire qsfp_1_tx_clk_0_int; -wire qsfp_1_tx_rst_0_int; -wire [63:0] qsfp_1_txd_0_int; -wire [7:0] qsfp_1_txc_0_int; -wire qsfp_1_rx_clk_0_int; -wire qsfp_1_rx_rst_0_int; -wire [63:0] qsfp_1_rxd_0_int; -wire [7:0] qsfp_1_rxc_0_int; -wire qsfp_1_tx_clk_1_int; -wire qsfp_1_tx_rst_1_int; -wire [63:0] qsfp_1_txd_1_int; -wire [7:0] qsfp_1_txc_1_int; -wire qsfp_1_rx_clk_1_int; -wire qsfp_1_rx_rst_1_int; -wire [63:0] qsfp_1_rxd_1_int; -wire [7:0] qsfp_1_rxc_1_int; -wire qsfp_1_tx_clk_2_int; -wire qsfp_1_tx_rst_2_int; -wire [63:0] qsfp_1_txd_2_int; -wire [7:0] qsfp_1_txc_2_int; -wire qsfp_1_rx_clk_2_int; -wire qsfp_1_rx_rst_2_int; -wire [63:0] qsfp_1_rxd_2_int; -wire [7:0] qsfp_1_rxc_2_int; -wire qsfp_1_tx_clk_3_int; -wire qsfp_1_tx_rst_3_int; -wire [63:0] qsfp_1_txd_3_int; -wire [7:0] qsfp_1_txc_3_int; -wire qsfp_1_rx_clk_3_int; -wire qsfp_1_rx_rst_3_int; -wire [63:0] qsfp_1_rxd_3_int; -wire [7:0] qsfp_1_rxc_3_int; - -wire qsfp_1_rx_block_lock_0; -wire qsfp_1_rx_block_lock_1; -wire qsfp_1_rx_block_lock_2; -wire qsfp_1_rx_block_lock_3; - -wire qsfp_1_mgt_refclk; - -IBUFDS_GTE4 ibufds_gte4_qsfp_1_mgt_refclk_inst ( - .I (qsfp_1_mgt_refclk_p), - .IB (qsfp_1_mgt_refclk_n), - .CEB (1'b0), - .O (qsfp_1_mgt_refclk), - .ODIV2 () -); - -wire qsfp_1_qpll0lock; -wire qsfp_1_qpll0outclk; -wire qsfp_1_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp_1_phy_0_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(qsfp_1_mgt_refclk), - .xcvr_qpll0lock_out(qsfp_1_qpll0lock), - .xcvr_qpll0outclk_out(qsfp_1_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp_1_qpll0outrefclk), - - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), - - // Serial data - .xcvr_txp(qsfp_1_tx_0_p), - .xcvr_txn(qsfp_1_tx_0_n), - .xcvr_rxp(qsfp_1_rx_0_p), - .xcvr_rxn(qsfp_1_rx_0_n), - - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_0_int), - .phy_tx_rst(qsfp_1_tx_rst_0_int), - .phy_xgmii_txd(qsfp_1_txd_0_int), - .phy_xgmii_txc(qsfp_1_txc_0_int), - .phy_rx_clk(qsfp_1_rx_clk_0_int), - .phy_rx_rst(qsfp_1_rx_rst_0_int), - .phy_xgmii_rxd(qsfp_1_rxd_0_int), - .phy_xgmii_rxc(qsfp_1_rxc_0_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_0), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_1_phy_1_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_1_tx_1_p), - .xcvr_txn(qsfp_1_tx_1_n), - .xcvr_rxp(qsfp_1_rx_1_p), - .xcvr_rxn(qsfp_1_rx_1_n), - - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_1_int), - .phy_tx_rst(qsfp_1_tx_rst_1_int), - .phy_xgmii_txd(qsfp_1_txd_1_int), - .phy_xgmii_txc(qsfp_1_txc_1_int), - .phy_rx_clk(qsfp_1_rx_clk_1_int), - .phy_rx_rst(qsfp_1_rx_rst_1_int), - .phy_xgmii_rxd(qsfp_1_rxd_1_int), - .phy_xgmii_rxc(qsfp_1_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_1_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_1_tx_2_p), - .xcvr_txn(qsfp_1_tx_2_n), - .xcvr_rxp(qsfp_1_rx_2_p), - .xcvr_rxn(qsfp_1_rx_2_n), - - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_2_int), - .phy_tx_rst(qsfp_1_tx_rst_2_int), - .phy_xgmii_txd(qsfp_1_txd_2_int), - .phy_xgmii_txc(qsfp_1_txc_2_int), - .phy_rx_clk(qsfp_1_rx_clk_2_int), - .phy_rx_rst(qsfp_1_rx_rst_2_int), - .phy_xgmii_rxd(qsfp_1_rxd_2_int), - .phy_xgmii_rxc(qsfp_1_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp_1_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp_1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp_1_tx_3_p), - .xcvr_txn(qsfp_1_tx_3_n), - .xcvr_rxp(qsfp_1_rx_3_p), - .xcvr_rxn(qsfp_1_rx_3_n), - - // PHY connections - .phy_tx_clk(qsfp_1_tx_clk_3_int), - .phy_tx_rst(qsfp_1_tx_rst_3_int), - .phy_xgmii_txd(qsfp_1_txd_3_int), - .phy_xgmii_txc(qsfp_1_txc_3_int), - .phy_rx_clk(qsfp_1_rx_clk_3_int), - .phy_rx_rst(qsfp_1_rx_rst_3_int), - .phy_xgmii_rxd(qsfp_1_rxd_3_int), - .phy_xgmii_rxc(qsfp_1_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp_1_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -assign front_led[0] = qsfp_0_rx_block_lock_0; -assign front_led[1] = qsfp_1_rx_block_lock_0; - -fpga_core -core_inst ( - /* - * Clock: 156.25 MHz - * Synchronous reset - */ - .clk(clk_156mhz_int), - .rst(rst_156mhz_int), - /* - * GPIO - */ - .user_led_g(user_led_g), - .user_led_r(user_led_r), - //.front_led(front_led), - .user_sw(user_sw_int), - - /* - * Ethernet: QSFP28 - */ - .qsfp_0_tx_clk_0(qsfp_0_tx_clk_0_int), - .qsfp_0_tx_rst_0(qsfp_0_tx_rst_0_int), - .qsfp_0_txd_0(qsfp_0_txd_0_int), - .qsfp_0_txc_0(qsfp_0_txc_0_int), - .qsfp_0_rx_clk_0(qsfp_0_rx_clk_0_int), - .qsfp_0_rx_rst_0(qsfp_0_rx_rst_0_int), - .qsfp_0_rxd_0(qsfp_0_rxd_0_int), - .qsfp_0_rxc_0(qsfp_0_rxc_0_int), - .qsfp_0_tx_clk_1(qsfp_0_tx_clk_1_int), - .qsfp_0_tx_rst_1(qsfp_0_tx_rst_1_int), - .qsfp_0_txd_1(qsfp_0_txd_1_int), - .qsfp_0_txc_1(qsfp_0_txc_1_int), - .qsfp_0_rx_clk_1(qsfp_0_rx_clk_1_int), - .qsfp_0_rx_rst_1(qsfp_0_rx_rst_1_int), - .qsfp_0_rxd_1(qsfp_0_rxd_1_int), - .qsfp_0_rxc_1(qsfp_0_rxc_1_int), - .qsfp_0_tx_clk_2(qsfp_0_tx_clk_2_int), - .qsfp_0_tx_rst_2(qsfp_0_tx_rst_2_int), - .qsfp_0_txd_2(qsfp_0_txd_2_int), - .qsfp_0_txc_2(qsfp_0_txc_2_int), - .qsfp_0_rx_clk_2(qsfp_0_rx_clk_2_int), - .qsfp_0_rx_rst_2(qsfp_0_rx_rst_2_int), - .qsfp_0_rxd_2(qsfp_0_rxd_2_int), - .qsfp_0_rxc_2(qsfp_0_rxc_2_int), - .qsfp_0_tx_clk_3(qsfp_0_tx_clk_3_int), - .qsfp_0_tx_rst_3(qsfp_0_tx_rst_3_int), - .qsfp_0_txd_3(qsfp_0_txd_3_int), - .qsfp_0_txc_3(qsfp_0_txc_3_int), - .qsfp_0_rx_clk_3(qsfp_0_rx_clk_3_int), - .qsfp_0_rx_rst_3(qsfp_0_rx_rst_3_int), - .qsfp_0_rxd_3(qsfp_0_rxd_3_int), - .qsfp_0_rxc_3(qsfp_0_rxc_3_int), - .qsfp_1_tx_clk_0(qsfp_1_tx_clk_0_int), - .qsfp_1_tx_rst_0(qsfp_1_tx_rst_0_int), - .qsfp_1_txd_0(qsfp_1_txd_0_int), - .qsfp_1_txc_0(qsfp_1_txc_0_int), - .qsfp_1_rx_clk_0(qsfp_1_rx_clk_0_int), - .qsfp_1_rx_rst_0(qsfp_1_rx_rst_0_int), - .qsfp_1_rxd_0(qsfp_1_rxd_0_int), - .qsfp_1_rxc_0(qsfp_1_rxc_0_int), - .qsfp_1_tx_clk_1(qsfp_1_tx_clk_1_int), - .qsfp_1_tx_rst_1(qsfp_1_tx_rst_1_int), - .qsfp_1_txd_1(qsfp_1_txd_1_int), - .qsfp_1_txc_1(qsfp_1_txc_1_int), - .qsfp_1_rx_clk_1(qsfp_1_rx_clk_1_int), - .qsfp_1_rx_rst_1(qsfp_1_rx_rst_1_int), - .qsfp_1_rxd_1(qsfp_1_rxd_1_int), - .qsfp_1_rxc_1(qsfp_1_rxc_1_int), - .qsfp_1_tx_clk_2(qsfp_1_tx_clk_2_int), - .qsfp_1_tx_rst_2(qsfp_1_tx_rst_2_int), - .qsfp_1_txd_2(qsfp_1_txd_2_int), - .qsfp_1_txc_2(qsfp_1_txc_2_int), - .qsfp_1_rx_clk_2(qsfp_1_rx_clk_2_int), - .qsfp_1_rx_rst_2(qsfp_1_rx_rst_2_int), - .qsfp_1_rxd_2(qsfp_1_rxd_2_int), - .qsfp_1_rxc_2(qsfp_1_rxc_2_int), - .qsfp_1_tx_clk_3(qsfp_1_tx_clk_3_int), - .qsfp_1_tx_rst_3(qsfp_1_tx_rst_3_int), - .qsfp_1_txd_3(qsfp_1_txd_3_int), - .qsfp_1_txc_3(qsfp_1_txc_3_int), - .qsfp_1_rx_clk_3(qsfp_1_rx_clk_3_int), - .qsfp_1_rx_rst_3(qsfp_1_rx_rst_3_int), - .qsfp_1_rxd_3(qsfp_1_rxd_3_int), - .qsfp_1_rxc_3(qsfp_1_rxc_3_int) -); - -endmodule - -`resetall diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v deleted file mode 100644 index cf6f92802..000000000 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v +++ /dev/null @@ -1,665 +0,0 @@ -/* - -Copyright (c) 2014-2021 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA core logic - */ -module fpga_core # -( - parameter TARGET = "XILINX" -) -( - /* - * Clock: 156.25MHz - * Synchronous reset - */ - input wire clk, - input wire rst, - - /* - * GPIO - */ - output wire [1:0] user_led_g, - output wire user_led_r, - output wire [1:0] front_led, - input wire [1:0] user_sw, - - /* - * Ethernet: QSFP28 - */ - input wire qsfp_0_tx_clk_0, - input wire qsfp_0_tx_rst_0, - output wire [63:0] qsfp_0_txd_0, - output wire [7:0] qsfp_0_txc_0, - input wire qsfp_0_rx_clk_0, - input wire qsfp_0_rx_rst_0, - input wire [63:0] qsfp_0_rxd_0, - input wire [7:0] qsfp_0_rxc_0, - input wire qsfp_0_tx_clk_1, - input wire qsfp_0_tx_rst_1, - output wire [63:0] qsfp_0_txd_1, - output wire [7:0] qsfp_0_txc_1, - input wire qsfp_0_rx_clk_1, - input wire qsfp_0_rx_rst_1, - input wire [63:0] qsfp_0_rxd_1, - input wire [7:0] qsfp_0_rxc_1, - input wire qsfp_0_tx_clk_2, - input wire qsfp_0_tx_rst_2, - output wire [63:0] qsfp_0_txd_2, - output wire [7:0] qsfp_0_txc_2, - input wire qsfp_0_rx_clk_2, - input wire qsfp_0_rx_rst_2, - input wire [63:0] qsfp_0_rxd_2, - input wire [7:0] qsfp_0_rxc_2, - input wire qsfp_0_tx_clk_3, - input wire qsfp_0_tx_rst_3, - output wire [63:0] qsfp_0_txd_3, - output wire [7:0] qsfp_0_txc_3, - input wire qsfp_0_rx_clk_3, - input wire qsfp_0_rx_rst_3, - input wire [63:0] qsfp_0_rxd_3, - input wire [7:0] qsfp_0_rxc_3, - input wire qsfp_1_tx_clk_0, - input wire qsfp_1_tx_rst_0, - output wire [63:0] qsfp_1_txd_0, - output wire [7:0] qsfp_1_txc_0, - input wire qsfp_1_rx_clk_0, - input wire qsfp_1_rx_rst_0, - input wire [63:0] qsfp_1_rxd_0, - input wire [7:0] qsfp_1_rxc_0, - input wire qsfp_1_tx_clk_1, - input wire qsfp_1_tx_rst_1, - output wire [63:0] qsfp_1_txd_1, - output wire [7:0] qsfp_1_txc_1, - input wire qsfp_1_rx_clk_1, - input wire qsfp_1_rx_rst_1, - input wire [63:0] qsfp_1_rxd_1, - input wire [7:0] qsfp_1_rxc_1, - input wire qsfp_1_tx_clk_2, - input wire qsfp_1_tx_rst_2, - output wire [63:0] qsfp_1_txd_2, - output wire [7:0] qsfp_1_txc_2, - input wire qsfp_1_rx_clk_2, - input wire qsfp_1_rx_rst_2, - input wire [63:0] qsfp_1_rxd_2, - input wire [7:0] qsfp_1_rxc_2, - input wire qsfp_1_tx_clk_3, - input wire qsfp_1_tx_rst_3, - output wire [63:0] qsfp_1_txd_3, - output wire [7:0] qsfp_1_txc_3, - input wire qsfp_1_rx_clk_3, - input wire qsfp_1_rx_rst_3, - input wire [63:0] qsfp_1_rxd_3, - input wire [7:0] qsfp_1_rxc_3 -); - -// AXI between MAC and Ethernet modules -wire [63:0] rx_axis_tdata; -wire [7:0] rx_axis_tkeep; -wire rx_axis_tvalid; -wire rx_axis_tready; -wire rx_axis_tlast; -wire rx_axis_tuser; - -wire [63:0] tx_axis_tdata; -wire [7:0] tx_axis_tkeep; -wire tx_axis_tvalid; -wire tx_axis_tready; -wire tx_axis_tlast; -wire tx_axis_tuser; - -// Ethernet frame between Ethernet modules and UDP stack -wire rx_eth_hdr_ready; -wire rx_eth_hdr_valid; -wire [47:0] rx_eth_dest_mac; -wire [47:0] rx_eth_src_mac; -wire [15:0] rx_eth_type; -wire [63:0] rx_eth_payload_axis_tdata; -wire [7:0] rx_eth_payload_axis_tkeep; -wire rx_eth_payload_axis_tvalid; -wire rx_eth_payload_axis_tready; -wire rx_eth_payload_axis_tlast; -wire rx_eth_payload_axis_tuser; - -wire tx_eth_hdr_ready; -wire tx_eth_hdr_valid; -wire [47:0] tx_eth_dest_mac; -wire [47:0] tx_eth_src_mac; -wire [15:0] tx_eth_type; -wire [63:0] tx_eth_payload_axis_tdata; -wire [7:0] tx_eth_payload_axis_tkeep; -wire tx_eth_payload_axis_tvalid; -wire tx_eth_payload_axis_tready; -wire tx_eth_payload_axis_tlast; -wire tx_eth_payload_axis_tuser; - -// IP frame connections -wire rx_ip_hdr_valid; -wire rx_ip_hdr_ready; -wire [47:0] rx_ip_eth_dest_mac; -wire [47:0] rx_ip_eth_src_mac; -wire [15:0] rx_ip_eth_type; -wire [3:0] rx_ip_version; -wire [3:0] rx_ip_ihl; -wire [5:0] rx_ip_dscp; -wire [1:0] rx_ip_ecn; -wire [15:0] rx_ip_length; -wire [15:0] rx_ip_identification; -wire [2:0] rx_ip_flags; -wire [12:0] rx_ip_fragment_offset; -wire [7:0] rx_ip_ttl; -wire [7:0] rx_ip_protocol; -wire [15:0] rx_ip_header_checksum; -wire [31:0] rx_ip_source_ip; -wire [31:0] rx_ip_dest_ip; -wire [63:0] rx_ip_payload_axis_tdata; -wire [7:0] rx_ip_payload_axis_tkeep; -wire rx_ip_payload_axis_tvalid; -wire rx_ip_payload_axis_tready; -wire rx_ip_payload_axis_tlast; -wire rx_ip_payload_axis_tuser; - -wire tx_ip_hdr_valid; -wire tx_ip_hdr_ready; -wire [5:0] tx_ip_dscp; -wire [1:0] tx_ip_ecn; -wire [15:0] tx_ip_length; -wire [7:0] tx_ip_ttl; -wire [7:0] tx_ip_protocol; -wire [31:0] tx_ip_source_ip; -wire [31:0] tx_ip_dest_ip; -wire [63:0] tx_ip_payload_axis_tdata; -wire [7:0] tx_ip_payload_axis_tkeep; -wire tx_ip_payload_axis_tvalid; -wire tx_ip_payload_axis_tready; -wire tx_ip_payload_axis_tlast; -wire tx_ip_payload_axis_tuser; - -// UDP frame connections -wire rx_udp_hdr_valid; -wire rx_udp_hdr_ready; -wire [47:0] rx_udp_eth_dest_mac; -wire [47:0] rx_udp_eth_src_mac; -wire [15:0] rx_udp_eth_type; -wire [3:0] rx_udp_ip_version; -wire [3:0] rx_udp_ip_ihl; -wire [5:0] rx_udp_ip_dscp; -wire [1:0] rx_udp_ip_ecn; -wire [15:0] rx_udp_ip_length; -wire [15:0] rx_udp_ip_identification; -wire [2:0] rx_udp_ip_flags; -wire [12:0] rx_udp_ip_fragment_offset; -wire [7:0] rx_udp_ip_ttl; -wire [7:0] rx_udp_ip_protocol; -wire [15:0] rx_udp_ip_header_checksum; -wire [31:0] rx_udp_ip_source_ip; -wire [31:0] rx_udp_ip_dest_ip; -wire [15:0] rx_udp_source_port; -wire [15:0] rx_udp_dest_port; -wire [15:0] rx_udp_length; -wire [15:0] rx_udp_checksum; -wire [63:0] rx_udp_payload_axis_tdata; -wire [7:0] rx_udp_payload_axis_tkeep; -wire rx_udp_payload_axis_tvalid; -wire rx_udp_payload_axis_tready; -wire rx_udp_payload_axis_tlast; -wire rx_udp_payload_axis_tuser; - -wire tx_udp_hdr_valid; -wire tx_udp_hdr_ready; -wire [5:0] tx_udp_ip_dscp; -wire [1:0] tx_udp_ip_ecn; -wire [7:0] tx_udp_ip_ttl; -wire [31:0] tx_udp_ip_source_ip; -wire [31:0] tx_udp_ip_dest_ip; -wire [15:0] tx_udp_source_port; -wire [15:0] tx_udp_dest_port; -wire [15:0] tx_udp_length; -wire [15:0] tx_udp_checksum; -wire [63:0] tx_udp_payload_axis_tdata; -wire [7:0] tx_udp_payload_axis_tkeep; -wire tx_udp_payload_axis_tvalid; -wire tx_udp_payload_axis_tready; -wire tx_udp_payload_axis_tlast; -wire tx_udp_payload_axis_tuser; - -wire [63:0] rx_fifo_udp_payload_axis_tdata; -wire [7:0] rx_fifo_udp_payload_axis_tkeep; -wire rx_fifo_udp_payload_axis_tvalid; -wire rx_fifo_udp_payload_axis_tready; -wire rx_fifo_udp_payload_axis_tlast; -wire rx_fifo_udp_payload_axis_tuser; - -wire [63:0] tx_fifo_udp_payload_axis_tdata; -wire [7:0] tx_fifo_udp_payload_axis_tkeep; -wire tx_fifo_udp_payload_axis_tvalid; -wire tx_fifo_udp_payload_axis_tready; -wire tx_fifo_udp_payload_axis_tlast; -wire tx_fifo_udp_payload_axis_tuser; - -// Configuration -wire [47:0] local_mac = 48'h02_00_00_00_00_00; -wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128}; -wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1}; -wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0}; - -// IP ports not used -assign rx_ip_hdr_ready = 1; -assign rx_ip_payload_axis_tready = 1; - -assign tx_ip_hdr_valid = 0; -assign tx_ip_dscp = 0; -assign tx_ip_ecn = 0; -assign tx_ip_length = 0; -assign tx_ip_ttl = 0; -assign tx_ip_protocol = 0; -assign tx_ip_source_ip = 0; -assign tx_ip_dest_ip = 0; -assign tx_ip_payload_axis_tdata = 0; -assign tx_ip_payload_axis_tkeep = 0; -assign tx_ip_payload_axis_tvalid = 0; -assign tx_ip_payload_axis_tlast = 0; -assign tx_ip_payload_axis_tuser = 0; - -// Loop back UDP -wire match_cond = rx_udp_dest_port == 1234; -wire no_match = !match_cond; - -reg match_cond_reg = 0; -reg no_match_reg = 0; - -always @(posedge clk) begin - if (rst) begin - match_cond_reg <= 0; - no_match_reg <= 0; - end else begin - if (rx_udp_payload_axis_tvalid) begin - if ((!match_cond_reg && !no_match_reg) || - (rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin - match_cond_reg <= match_cond; - no_match_reg <= no_match; - end - end else begin - match_cond_reg <= 0; - no_match_reg <= 0; - end - end -end - -assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond; -assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match; -assign tx_udp_ip_dscp = 0; -assign tx_udp_ip_ecn = 0; -assign tx_udp_ip_ttl = 64; -assign tx_udp_ip_source_ip = local_ip; -assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip; -assign tx_udp_source_port = rx_udp_dest_port; -assign tx_udp_dest_port = rx_udp_source_port; -assign tx_udp_length = rx_udp_length; -assign tx_udp_checksum = 0; - -assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata; -assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep; -assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid; -assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready; -assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast; -assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser; - -assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata; -assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep; -assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg; -assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg; -assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast; -assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser; - -// Place first payload byte onto LEDs -reg valid_last = 0; -reg [7:0] led_reg = 0; - -always @(posedge clk) begin - if (rst) begin - led_reg <= 0; - end else begin - valid_last <= tx_udp_payload_axis_tvalid; - if (tx_udp_payload_axis_tvalid && !valid_last) begin - led_reg <= tx_udp_payload_axis_tdata; - end - end -end - -assign user_led_g = ~led_reg[1:0]; -assign user_led_r = 1'b1; -assign front_led = 2'b00; - -assign qsfp_0_txd_1 = 64'h0707070707070707; -assign qsfp_0_txc_1 = 8'hff; -assign qsfp_0_txd_2 = 64'h0707070707070707; -assign qsfp_0_txc_2 = 8'hff; -assign qsfp_0_txd_3 = 64'h0707070707070707; -assign qsfp_0_txc_3 = 8'hff; - -assign qsfp_1_txd_0 = 64'h0707070707070707; -assign qsfp_1_txc_0 = 8'hff; -assign qsfp_1_txd_1 = 64'h0707070707070707; -assign qsfp_1_txc_1 = 8'hff; -assign qsfp_1_txd_2 = 64'h0707070707070707; -assign qsfp_1_txc_2 = 8'hff; -assign qsfp_1_txd_3 = 64'h0707070707070707; -assign qsfp_1_txc_3 = 8'hff; - -eth_mac_10g_fifo #( - .ENABLE_PADDING(1), - .ENABLE_DIC(1), - .MIN_FRAME_LENGTH(64), - .TX_FIFO_DEPTH(4096), - .TX_FRAME_FIFO(1), - .RX_FIFO_DEPTH(4096), - .RX_FRAME_FIFO(1) -) -eth_mac_10g_fifo_inst ( - .rx_clk(qsfp_0_rx_clk_0), - .rx_rst(qsfp_0_rx_rst_0), - .tx_clk(qsfp_0_tx_clk_0), - .tx_rst(qsfp_0_tx_rst_0), - .logic_clk(clk), - .logic_rst(rst), - - .tx_axis_tdata(tx_axis_tdata), - .tx_axis_tkeep(tx_axis_tkeep), - .tx_axis_tvalid(tx_axis_tvalid), - .tx_axis_tready(tx_axis_tready), - .tx_axis_tlast(tx_axis_tlast), - .tx_axis_tuser(tx_axis_tuser), - - .rx_axis_tdata(rx_axis_tdata), - .rx_axis_tkeep(rx_axis_tkeep), - .rx_axis_tvalid(rx_axis_tvalid), - .rx_axis_tready(rx_axis_tready), - .rx_axis_tlast(rx_axis_tlast), - .rx_axis_tuser(rx_axis_tuser), - - .xgmii_rxd(qsfp_0_rxd_0), - .xgmii_rxc(qsfp_0_rxc_0), - .xgmii_txd(qsfp_0_txd_0), - .xgmii_txc(qsfp_0_txc_0), - - .tx_fifo_overflow(), - .tx_fifo_bad_frame(), - .tx_fifo_good_frame(), - .rx_error_bad_frame(), - .rx_error_bad_fcs(), - .rx_fifo_overflow(), - .rx_fifo_bad_frame(), - .rx_fifo_good_frame(), - - .ifg_delay(8'd12) -); - -eth_axis_rx #( - .DATA_WIDTH(64) -) -eth_axis_rx_inst ( - .clk(clk), - .rst(rst), - // AXI input - .s_axis_tdata(rx_axis_tdata), - .s_axis_tkeep(rx_axis_tkeep), - .s_axis_tvalid(rx_axis_tvalid), - .s_axis_tready(rx_axis_tready), - .s_axis_tlast(rx_axis_tlast), - .s_axis_tuser(rx_axis_tuser), - // Ethernet frame output - .m_eth_hdr_valid(rx_eth_hdr_valid), - .m_eth_hdr_ready(rx_eth_hdr_ready), - .m_eth_dest_mac(rx_eth_dest_mac), - .m_eth_src_mac(rx_eth_src_mac), - .m_eth_type(rx_eth_type), - .m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), - .m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep), - .m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), - .m_eth_payload_axis_tready(rx_eth_payload_axis_tready), - .m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), - .m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), - // Status signals - .busy(), - .error_header_early_termination() -); - -eth_axis_tx #( - .DATA_WIDTH(64) -) -eth_axis_tx_inst ( - .clk(clk), - .rst(rst), - // Ethernet frame input - .s_eth_hdr_valid(tx_eth_hdr_valid), - .s_eth_hdr_ready(tx_eth_hdr_ready), - .s_eth_dest_mac(tx_eth_dest_mac), - .s_eth_src_mac(tx_eth_src_mac), - .s_eth_type(tx_eth_type), - .s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), - .s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep), - .s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), - .s_eth_payload_axis_tready(tx_eth_payload_axis_tready), - .s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), - .s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), - // AXI output - .m_axis_tdata(tx_axis_tdata), - .m_axis_tkeep(tx_axis_tkeep), - .m_axis_tvalid(tx_axis_tvalid), - .m_axis_tready(tx_axis_tready), - .m_axis_tlast(tx_axis_tlast), - .m_axis_tuser(tx_axis_tuser), - // Status signals - .busy() -); - -udp_complete_64 -udp_complete_inst ( - .clk(clk), - .rst(rst), - // Ethernet frame input - .s_eth_hdr_valid(rx_eth_hdr_valid), - .s_eth_hdr_ready(rx_eth_hdr_ready), - .s_eth_dest_mac(rx_eth_dest_mac), - .s_eth_src_mac(rx_eth_src_mac), - .s_eth_type(rx_eth_type), - .s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), - .s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep), - .s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), - .s_eth_payload_axis_tready(rx_eth_payload_axis_tready), - .s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), - .s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), - // Ethernet frame output - .m_eth_hdr_valid(tx_eth_hdr_valid), - .m_eth_hdr_ready(tx_eth_hdr_ready), - .m_eth_dest_mac(tx_eth_dest_mac), - .m_eth_src_mac(tx_eth_src_mac), - .m_eth_type(tx_eth_type), - .m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), - .m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep), - .m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), - .m_eth_payload_axis_tready(tx_eth_payload_axis_tready), - .m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), - .m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), - // IP frame input - .s_ip_hdr_valid(tx_ip_hdr_valid), - .s_ip_hdr_ready(tx_ip_hdr_ready), - .s_ip_dscp(tx_ip_dscp), - .s_ip_ecn(tx_ip_ecn), - .s_ip_length(tx_ip_length), - .s_ip_ttl(tx_ip_ttl), - .s_ip_protocol(tx_ip_protocol), - .s_ip_source_ip(tx_ip_source_ip), - .s_ip_dest_ip(tx_ip_dest_ip), - .s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata), - .s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep), - .s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid), - .s_ip_payload_axis_tready(tx_ip_payload_axis_tready), - .s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast), - .s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser), - // IP frame output - .m_ip_hdr_valid(rx_ip_hdr_valid), - .m_ip_hdr_ready(rx_ip_hdr_ready), - .m_ip_eth_dest_mac(rx_ip_eth_dest_mac), - .m_ip_eth_src_mac(rx_ip_eth_src_mac), - .m_ip_eth_type(rx_ip_eth_type), - .m_ip_version(rx_ip_version), - .m_ip_ihl(rx_ip_ihl), - .m_ip_dscp(rx_ip_dscp), - .m_ip_ecn(rx_ip_ecn), - .m_ip_length(rx_ip_length), - .m_ip_identification(rx_ip_identification), - .m_ip_flags(rx_ip_flags), - .m_ip_fragment_offset(rx_ip_fragment_offset), - .m_ip_ttl(rx_ip_ttl), - .m_ip_protocol(rx_ip_protocol), - .m_ip_header_checksum(rx_ip_header_checksum), - .m_ip_source_ip(rx_ip_source_ip), - .m_ip_dest_ip(rx_ip_dest_ip), - .m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata), - .m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep), - .m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid), - .m_ip_payload_axis_tready(rx_ip_payload_axis_tready), - .m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast), - .m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser), - // UDP frame input - .s_udp_hdr_valid(tx_udp_hdr_valid), - .s_udp_hdr_ready(tx_udp_hdr_ready), - .s_udp_ip_dscp(tx_udp_ip_dscp), - .s_udp_ip_ecn(tx_udp_ip_ecn), - .s_udp_ip_ttl(tx_udp_ip_ttl), - .s_udp_ip_source_ip(tx_udp_ip_source_ip), - .s_udp_ip_dest_ip(tx_udp_ip_dest_ip), - .s_udp_source_port(tx_udp_source_port), - .s_udp_dest_port(tx_udp_dest_port), - .s_udp_length(tx_udp_length), - .s_udp_checksum(tx_udp_checksum), - .s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata), - .s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep), - .s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid), - .s_udp_payload_axis_tready(tx_udp_payload_axis_tready), - .s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast), - .s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser), - // UDP frame output - .m_udp_hdr_valid(rx_udp_hdr_valid), - .m_udp_hdr_ready(rx_udp_hdr_ready), - .m_udp_eth_dest_mac(rx_udp_eth_dest_mac), - .m_udp_eth_src_mac(rx_udp_eth_src_mac), - .m_udp_eth_type(rx_udp_eth_type), - .m_udp_ip_version(rx_udp_ip_version), - .m_udp_ip_ihl(rx_udp_ip_ihl), - .m_udp_ip_dscp(rx_udp_ip_dscp), - .m_udp_ip_ecn(rx_udp_ip_ecn), - .m_udp_ip_length(rx_udp_ip_length), - .m_udp_ip_identification(rx_udp_ip_identification), - .m_udp_ip_flags(rx_udp_ip_flags), - .m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset), - .m_udp_ip_ttl(rx_udp_ip_ttl), - .m_udp_ip_protocol(rx_udp_ip_protocol), - .m_udp_ip_header_checksum(rx_udp_ip_header_checksum), - .m_udp_ip_source_ip(rx_udp_ip_source_ip), - .m_udp_ip_dest_ip(rx_udp_ip_dest_ip), - .m_udp_source_port(rx_udp_source_port), - .m_udp_dest_port(rx_udp_dest_port), - .m_udp_length(rx_udp_length), - .m_udp_checksum(rx_udp_checksum), - .m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata), - .m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep), - .m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid), - .m_udp_payload_axis_tready(rx_udp_payload_axis_tready), - .m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast), - .m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser), - // Status signals - .ip_rx_busy(), - .ip_tx_busy(), - .udp_rx_busy(), - .udp_tx_busy(), - .ip_rx_error_header_early_termination(), - .ip_rx_error_payload_early_termination(), - .ip_rx_error_invalid_header(), - .ip_rx_error_invalid_checksum(), - .ip_tx_error_payload_early_termination(), - .ip_tx_error_arp_failed(), - .udp_rx_error_header_early_termination(), - .udp_rx_error_payload_early_termination(), - .udp_tx_error_payload_early_termination(), - // Configuration - .local_mac(local_mac), - .local_ip(local_ip), - .gateway_ip(gateway_ip), - .subnet_mask(subnet_mask), - .clear_arp_cache(1'b0) -); - -axis_fifo #( - .DEPTH(8192), - .DATA_WIDTH(64), - .KEEP_ENABLE(1), - .KEEP_WIDTH(8), - .ID_ENABLE(0), - .DEST_ENABLE(0), - .USER_ENABLE(1), - .USER_WIDTH(1), - .FRAME_FIFO(0) -) -udp_payload_fifo ( - .clk(clk), - .rst(rst), - - // AXI input - .s_axis_tdata(rx_fifo_udp_payload_axis_tdata), - .s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep), - .s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid), - .s_axis_tready(rx_fifo_udp_payload_axis_tready), - .s_axis_tlast(rx_fifo_udp_payload_axis_tlast), - .s_axis_tid(0), - .s_axis_tdest(0), - .s_axis_tuser(rx_fifo_udp_payload_axis_tuser), - - // AXI output - .m_axis_tdata(tx_fifo_udp_payload_axis_tdata), - .m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep), - .m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid), - .m_axis_tready(tx_fifo_udp_payload_axis_tready), - .m_axis_tlast(tx_fifo_udp_payload_axis_tlast), - .m_axis_tid(), - .m_axis_tdest(), - .m_axis_tuser(tx_fifo_udp_payload_axis_tuser), - - // Status - .status_overflow(), - .status_bad_frame(), - .status_good_frame() -); - -endmodule - -`resetall diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/test_fpga_core.py deleted file mode 100644 index 6d907a8c7..000000000 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/test_fpga_core.py +++ /dev/null @@ -1,289 +0,0 @@ -""" - -Copyright (c) 2020 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -""" - -import logging -import os - -from scapy.layers.l2 import Ether, ARP -from scapy.layers.inet import IP, UDP - -import cocotb_test.simulator - -import cocotb -from cocotb.log import SimLog -from cocotb.clock import Clock -from cocotb.triggers import RisingEdge - -from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink - - -class TB: - def __init__(self, dut): - self.dut = dut - - self.log = SimLog("cocotb.tb") - self.log.setLevel(logging.DEBUG) - - cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) - - # Ethernet - cocotb.start_soon(Clock(dut.qsfp_0_rx_clk_0, 6.4, units="ns").start()) - self.qsfp_0_0_source = XgmiiSource(dut.qsfp_0_rxd_0, dut.qsfp_0_rxc_0, dut.qsfp_0_rx_clk_0, dut.qsfp_0_rx_rst_0) - cocotb.start_soon(Clock(dut.qsfp_0_tx_clk_0, 6.4, units="ns").start()) - self.qsfp_0_0_sink = XgmiiSink(dut.qsfp_0_txd_0, dut.qsfp_0_txc_0, dut.qsfp_0_tx_clk_0, dut.qsfp_0_tx_rst_0) - - cocotb.start_soon(Clock(dut.qsfp_0_rx_clk_1, 6.4, units="ns").start()) - self.qsfp_0_1_source = XgmiiSource(dut.qsfp_0_rxd_1, dut.qsfp_0_rxc_1, dut.qsfp_0_rx_clk_1, dut.qsfp_0_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp_0_tx_clk_1, 6.4, units="ns").start()) - self.qsfp_0_1_sink = XgmiiSink(dut.qsfp_0_txd_1, dut.qsfp_0_txc_1, dut.qsfp_0_tx_clk_1, dut.qsfp_0_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp_0_rx_clk_2, 6.4, units="ns").start()) - self.qsfp_0_2_source = XgmiiSource(dut.qsfp_0_rxd_2, dut.qsfp_0_rxc_2, dut.qsfp_0_rx_clk_2, dut.qsfp_0_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp_0_tx_clk_2, 6.4, units="ns").start()) - self.qsfp_0_2_sink = XgmiiSink(dut.qsfp_0_txd_2, dut.qsfp_0_txc_2, dut.qsfp_0_tx_clk_2, dut.qsfp_0_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp_0_rx_clk_3, 6.4, units="ns").start()) - self.qsfp_0_3_source = XgmiiSource(dut.qsfp_0_rxd_3, dut.qsfp_0_rxc_3, dut.qsfp_0_rx_clk_3, dut.qsfp_0_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp_0_tx_clk_3, 6.4, units="ns").start()) - self.qsfp_0_3_sink = XgmiiSink(dut.qsfp_0_txd_3, dut.qsfp_0_txc_3, dut.qsfp_0_tx_clk_3, dut.qsfp_0_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_0, 6.4, units="ns").start()) - self.qsfp_1_0_source = XgmiiSource(dut.qsfp_1_rxd_0, dut.qsfp_1_rxc_0, dut.qsfp_1_rx_clk_0, dut.qsfp_1_rx_rst_0) - cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_0, 6.4, units="ns").start()) - self.qsfp_1_0_sink = XgmiiSink(dut.qsfp_1_txd_0, dut.qsfp_1_txc_0, dut.qsfp_1_tx_clk_0, dut.qsfp_1_tx_rst_0) - - cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_1, 6.4, units="ns").start()) - self.qsfp_1_1_source = XgmiiSource(dut.qsfp_1_rxd_1, dut.qsfp_1_rxc_1, dut.qsfp_1_rx_clk_1, dut.qsfp_1_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_1, 6.4, units="ns").start()) - self.qsfp_1_1_sink = XgmiiSink(dut.qsfp_1_txd_1, dut.qsfp_1_txc_1, dut.qsfp_1_tx_clk_1, dut.qsfp_1_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_2, 6.4, units="ns").start()) - self.qsfp_1_2_source = XgmiiSource(dut.qsfp_1_rxd_2, dut.qsfp_1_rxc_2, dut.qsfp_1_rx_clk_2, dut.qsfp_1_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_2, 6.4, units="ns").start()) - self.qsfp_1_2_sink = XgmiiSink(dut.qsfp_1_txd_2, dut.qsfp_1_txc_2, dut.qsfp_1_tx_clk_2, dut.qsfp_1_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_3, 6.4, units="ns").start()) - self.qsfp_1_3_source = XgmiiSource(dut.qsfp_1_rxd_3, dut.qsfp_1_rxc_3, dut.qsfp_1_rx_clk_3, dut.qsfp_1_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_3, 6.4, units="ns").start()) - self.qsfp_1_3_sink = XgmiiSink(dut.qsfp_1_txd_3, dut.qsfp_1_txc_3, dut.qsfp_1_tx_clk_3, dut.qsfp_1_tx_rst_3) - - dut.user_sw.setimmediatevalue(0) - - async def init(self): - - self.dut.rst.setimmediatevalue(0) - self.dut.qsfp_0_rx_rst_0.setimmediatevalue(0) - self.dut.qsfp_0_tx_rst_0.setimmediatevalue(0) - self.dut.qsfp_0_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp_0_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp_0_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp_0_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp_0_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp_0_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp_1_rx_rst_0.setimmediatevalue(0) - self.dut.qsfp_1_tx_rst_0.setimmediatevalue(0) - self.dut.qsfp_1_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp_1_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp_1_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp_1_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp_1_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp_1_tx_rst_3.setimmediatevalue(0) - - for k in range(10): - await RisingEdge(self.dut.clk) - - self.dut.rst.value = 1 - self.dut.qsfp_0_rx_rst_0.value = 1 - self.dut.qsfp_0_tx_rst_0.value = 1 - self.dut.qsfp_0_rx_rst_1.value = 1 - self.dut.qsfp_0_tx_rst_1.value = 1 - self.dut.qsfp_0_rx_rst_2.value = 1 - self.dut.qsfp_0_tx_rst_2.value = 1 - self.dut.qsfp_0_rx_rst_3.value = 1 - self.dut.qsfp_0_tx_rst_3.value = 1 - self.dut.qsfp_1_rx_rst_0.value = 1 - self.dut.qsfp_1_tx_rst_0.value = 1 - self.dut.qsfp_1_rx_rst_1.value = 1 - self.dut.qsfp_1_tx_rst_1.value = 1 - self.dut.qsfp_1_rx_rst_2.value = 1 - self.dut.qsfp_1_tx_rst_2.value = 1 - self.dut.qsfp_1_rx_rst_3.value = 1 - self.dut.qsfp_1_tx_rst_3.value = 1 - - for k in range(10): - await RisingEdge(self.dut.clk) - - self.dut.rst.value = 0 - self.dut.qsfp_0_rx_rst_0.value = 0 - self.dut.qsfp_0_tx_rst_0.value = 0 - self.dut.qsfp_0_rx_rst_1.value = 0 - self.dut.qsfp_0_tx_rst_1.value = 0 - self.dut.qsfp_0_rx_rst_2.value = 0 - self.dut.qsfp_0_tx_rst_2.value = 0 - self.dut.qsfp_0_rx_rst_3.value = 0 - self.dut.qsfp_0_tx_rst_3.value = 0 - self.dut.qsfp_1_rx_rst_0.value = 0 - self.dut.qsfp_1_tx_rst_0.value = 0 - self.dut.qsfp_1_rx_rst_1.value = 0 - self.dut.qsfp_1_tx_rst_1.value = 0 - self.dut.qsfp_1_rx_rst_2.value = 0 - self.dut.qsfp_1_tx_rst_2.value = 0 - self.dut.qsfp_1_rx_rst_3.value = 0 - self.dut.qsfp_1_tx_rst_3.value = 0 - - -@cocotb.test() -async def run_test(dut): - - tb = TB(dut) - - await tb.init() - - tb.log.info("test UDP RX packet") - - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00') - ip = IP(src='192.168.1.100', dst='192.168.1.128') - udp = UDP(sport=5678, dport=1234) - test_pkt = eth / ip / udp / payload - - test_frame = XgmiiFrame.from_payload(test_pkt.build()) - - await tb.qsfp_0_0_source.send(test_frame) - - tb.log.info("receive ARP request") - - rx_frame = await tb.qsfp_0_0_sink.recv() - - rx_pkt = Ether(bytes(rx_frame.get_payload())) - - tb.log.info("RX packet: %s", repr(rx_pkt)) - - assert rx_pkt.dst == 'ff:ff:ff:ff:ff:ff' - assert rx_pkt.src == test_pkt.dst - assert rx_pkt[ARP].hwtype == 1 - assert rx_pkt[ARP].ptype == 0x0800 - assert rx_pkt[ARP].hwlen == 6 - assert rx_pkt[ARP].plen == 4 - assert rx_pkt[ARP].op == 1 - assert rx_pkt[ARP].hwsrc == test_pkt.dst - assert rx_pkt[ARP].psrc == test_pkt[IP].dst - assert rx_pkt[ARP].hwdst == '00:00:00:00:00:00' - assert rx_pkt[ARP].pdst == test_pkt[IP].src - - tb.log.info("send ARP response") - - eth = Ether(src=test_pkt.src, dst=test_pkt.dst) - arp = ARP(hwtype=1, ptype=0x0800, hwlen=6, plen=4, op=2, - hwsrc=test_pkt.src, psrc=test_pkt[IP].src, - hwdst=test_pkt.dst, pdst=test_pkt[IP].dst) - resp_pkt = eth / arp - - resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - - await tb.qsfp_0_0_source.send(resp_frame) - - tb.log.info("receive UDP packet") - - rx_frame = await tb.qsfp_0_0_sink.recv() - - rx_pkt = Ether(bytes(rx_frame.get_payload())) - - tb.log.info("RX packet: %s", repr(rx_pkt)) - - assert rx_pkt.dst == test_pkt.src - assert rx_pkt.src == test_pkt.dst - assert rx_pkt[IP].dst == test_pkt[IP].src - assert rx_pkt[IP].src == test_pkt[IP].dst - assert rx_pkt[UDP].dport == test_pkt[UDP].sport - assert rx_pkt[UDP].sport == test_pkt[UDP].dport - assert rx_pkt[UDP].payload == test_pkt[UDP].payload - - await RisingEdge(dut.clk) - await RisingEdge(dut.clk) - - -# cocotb-test - -tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) -axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'lib', 'axis', 'rtl')) -eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) - - -def test_fpga_core(request): - dut = "fpga_core" - module = os.path.splitext(os.path.basename(__file__))[0] - toplevel = dut - - verilog_sources = [ - os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g_fifo.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), - os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "eth_axis_rx.v"), - os.path.join(eth_rtl_dir, "eth_axis_tx.v"), - os.path.join(eth_rtl_dir, "udp_complete_64.v"), - os.path.join(eth_rtl_dir, "udp_checksum_gen_64.v"), - os.path.join(eth_rtl_dir, "udp_64.v"), - os.path.join(eth_rtl_dir, "udp_ip_rx_64.v"), - os.path.join(eth_rtl_dir, "udp_ip_tx_64.v"), - os.path.join(eth_rtl_dir, "ip_complete_64.v"), - os.path.join(eth_rtl_dir, "ip_64.v"), - os.path.join(eth_rtl_dir, "ip_eth_rx_64.v"), - os.path.join(eth_rtl_dir, "ip_eth_tx_64.v"), - os.path.join(eth_rtl_dir, "ip_arb_mux.v"), - os.path.join(eth_rtl_dir, "arp.v"), - os.path.join(eth_rtl_dir, "arp_cache.v"), - os.path.join(eth_rtl_dir, "arp_eth_rx.v"), - os.path.join(eth_rtl_dir, "arp_eth_tx.v"), - os.path.join(eth_rtl_dir, "eth_arb_mux.v"), - os.path.join(axis_rtl_dir, "arbiter.v"), - os.path.join(axis_rtl_dir, "priority_encoder.v"), - os.path.join(axis_rtl_dir, "axis_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), - ] - - parameters = {} - - # parameters['A'] = val - - extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} - - sim_build = os.path.join(tests_dir, "sim_build", - request.node.name.replace('[', '-').replace(']', '')) - - cocotb_test.simulator.run( - python_search=[tests_dir], - verilog_sources=verilog_sources, - toplevel=toplevel, - module=module, - parameters=parameters, - sim_build=sim_build, - extra_env=extra_env, - ) diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/common/vivado.mk b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/common/vivado.mk index 21e6a5fed..1402e2382 100644 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/common/vivado.mk +++ b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/common/vivado.mk @@ -28,7 +28,7 @@ ################################################################### # phony targets -.PHONY: clean fpga +.PHONY: fpga vivado tmpclean clean distclean # prevent make from deleting intermediate files and reports .PRECIOUS: %.xpr %.bit %.mcs %.prm @@ -40,15 +40,16 @@ CONFIG ?= config.mk FPGA_TOP ?= fpga PROJECT ?= $(FPGA_TOP) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else - XDC_FILES_REL = $(FPGA_TOP).xdc + XDC_FILES_REL = $(PROJECT).xdc endif ################################################################### @@ -60,20 +61,20 @@ endif all: fpga -fpga: $(FPGA_TOP).bit +fpga: $(PROJECT).bit -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr -tmpclean: +tmpclean:: -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt -distclean: clean +distclean:: clean -rm -rf rev ################################################################### @@ -91,12 +92,17 @@ create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done -$(PROJECT).xpr: create_project.tcl +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) # synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr echo "open_project $(PROJECT).xpr" > run_synth.tcl echo "reset_run synth_1" >> run_synth.tcl echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga.xdc b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga.xdc index 5718ae810..526ed4a88 100644 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga.xdc +++ b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga.xdc @@ -193,6 +193,282 @@ set_input_delay 0 [get_ports {qsfp_0_modprs_l qsfp_1_modprs_l qsfp_int_l}] #set_false_path -from [get_ports {perst_0}] #set_input_delay 0 [get_ports {perst_0}] +# DDR4 C0 +# 5x K4A8G085WB-RC +#set_property -dict {LOC F9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +#set_property -dict {LOC G9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +#set_property -dict {LOC G11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +#set_property -dict {LOC D11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +#set_property -dict {LOC E12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +#set_property -dict {LOC G10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +#set_property -dict {LOC F10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +#set_property -dict {LOC J9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +#set_property -dict {LOC J8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +#set_property -dict {LOC F12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +#set_property -dict {LOC D9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +#set_property -dict {LOC H11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +#set_property -dict {LOC E8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +#set_property -dict {LOC J11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +#set_property -dict {LOC C9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +#set_property -dict {LOC B11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +#set_property -dict {LOC K12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +#set_property -dict {LOC H9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[17]}] +#set_property -dict {LOC F8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +#set_property -dict {LOC H8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +#set_property -dict {LOC D10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +#set_property -dict {LOC E11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +#set_property -dict {LOC B10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[0]}] +#set_property -dict {LOC C11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[1]}] +#set_property -dict {LOC A9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[2]}] +#set_property -dict {LOC H12 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t}] +#set_property -dict {LOC G12 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c}] +#set_property -dict {LOC B9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke}] +#set_property -dict {LOC E10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n}] +#set_property -dict {LOC C12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +#set_property -dict {LOC A10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt}] +#set_property -dict {LOC G7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +#set_property -dict {LOC F7 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] +#set_property -dict {LOC H7 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_alert_n}] +#set_property -dict {LOC J10 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_ten}] + +#set_property -dict {LOC L10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +#set_property -dict {LOC L9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +#set_property -dict {LOC N9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +#set_property -dict {LOC M9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +#set_property -dict {LOC M10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +#set_property -dict {LOC K11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +#set_property -dict {LOC M11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +#set_property -dict {LOC K10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +#set_property -dict {LOC L17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +#set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +#set_property -dict {LOC M15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +#set_property -dict {LOC M17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +#set_property -dict {LOC M14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +#set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +#set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +#set_property -dict {LOC N17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +#set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +#set_property -dict {LOC E16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +#set_property -dict {LOC F14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +#set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +#set_property -dict {LOC G16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +#set_property -dict {LOC F17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +#set_property -dict {LOC E15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +#set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +#set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +#set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +#set_property -dict {LOC B16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +#set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +#set_property -dict {LOC B17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +#set_property -dict {LOC B14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +#set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +#set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +#set_property -dict {LOC F18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +#set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +#set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +#set_property -dict {LOC D21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +#set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +#set_property -dict {LOC G19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +#set_property -dict {LOC E21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +#set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +#set_property -dict {LOC D18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +#set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +#set_property -dict {LOC A19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +#set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +#set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +#set_property -dict {LOC B19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +#set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +#set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +#set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +#set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +#set_property -dict {LOC H19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +#set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +#set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +#set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +#set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +#set_property -dict {LOC K18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +#set_property -dict {LOC L20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +#set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +#set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +#set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +#set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +#set_property -dict {LOC M22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +#set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +#set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +#set_property -dict {LOC H16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +#set_property -dict {LOC K15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +#set_property -dict {LOC J16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +#set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +#set_property -dict {LOC K13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +#set_property -dict {LOC L13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +#set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +#set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +#set_property -dict {LOC M12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +#set_property -dict {LOC L12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +#set_property -dict {LOC L15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +#set_property -dict {LOC L14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +#set_property -dict {LOC F13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +#set_property -dict {LOC E13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +#set_property -dict {LOC B15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +#set_property -dict {LOC A15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +#set_property -dict {LOC F22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +#set_property -dict {LOC E22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +#set_property -dict {LOC C21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +#set_property -dict {LOC B21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +#set_property -dict {LOC K21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +#set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +#set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +#set_property -dict {LOC K22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +#set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +#set_property -dict {LOC K16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +#set_property -dict {LOC N12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[0]}] +#set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[1]}] +#set_property -dict {LOC G15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[2]}] +#set_property -dict {LOC D14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[3]}] +#set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[4]}] +#set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[5]}] +#set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[6]}] +#set_property -dict {LOC N22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[7]}] +#set_property -dict {LOC J13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[8]}] + +# DDR4 C1 +# 5x K4A8G085WB-RC +#set_property -dict {LOC AN9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +#set_property -dict {LOC AM9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +#set_property -dict {LOC AP11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +#set_property -dict {LOC AU9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +#set_property -dict {LOC AT10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +#set_property -dict {LOC AL12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +#set_property -dict {LOC AM12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +#set_property -dict {LOC AM10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +#set_property -dict {LOC AL11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +#set_property -dict {LOC AP7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +#set_property -dict {LOC AR8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +#set_property -dict {LOC AL10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +#set_property -dict {LOC AP8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +#set_property -dict {LOC AK11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +#set_property -dict {LOC AP9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +#set_property -dict {LOC AV10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +#set_property -dict {LOC AT11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +#set_property -dict {LOC AL8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[17]}] +#set_property -dict {LOC AN11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +#set_property -dict {LOC AR9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +#set_property -dict {LOC AP12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +#set_property -dict {LOC AN10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +#set_property -dict {LOC AW13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[0]}] +#set_property -dict {LOC AU10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[1]}] +#set_property -dict {LOC AW11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[2]}] +#set_property -dict {LOC AM7 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}] +#set_property -dict {LOC AN7 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}] +#set_property -dict {LOC AU12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}] +#set_property -dict {LOC AT12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}] +#set_property -dict {LOC AV9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +#set_property -dict {LOC AR11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}] +#set_property -dict {LOC AM8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +#set_property -dict {LOC AN12 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] +#set_property -dict {LOC AR10 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}] +#set_property -dict {LOC AV11 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}] + +#set_property -dict {LOC AK9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +#set_property -dict {LOC AK10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +#set_property -dict {LOC AH10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +#set_property -dict {LOC AJ11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +#set_property -dict {LOC AJ9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +#set_property -dict {LOC AH12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +#set_property -dict {LOC AG10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +#set_property -dict {LOC AJ12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +#set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +#set_property -dict {LOC AN14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +#set_property -dict {LOC AL13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +#set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +#set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +#set_property -dict {LOC AM17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +#set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +#set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +#set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +#set_property -dict {LOC AP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +#set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +#set_property -dict {LOC AR14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +#set_property -dict {LOC AP17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +#set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +#set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +#set_property -dict {LOC AN15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +#set_property -dict {LOC AU15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +#set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +#set_property -dict {LOC AV15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +#set_property -dict {LOC AT16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +#set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +#set_property -dict {LOC AW17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +#set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +#set_property -dict {LOC AW18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +#set_property -dict {LOC AP19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +#set_property -dict {LOC AT20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +#set_property -dict {LOC AN21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +#set_property -dict {LOC AR19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +#set_property -dict {LOC AN20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +#set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +#set_property -dict {LOC AR20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +#set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +#set_property -dict {LOC AW19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +#set_property -dict {LOC AU22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +#set_property -dict {LOC AV19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +#set_property -dict {LOC AW22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +#set_property -dict {LOC AU18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +#set_property -dict {LOC AT22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +#set_property -dict {LOC AW21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +#set_property -dict {LOC AU19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +#set_property -dict {LOC AH19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +#set_property -dict {LOC AJ22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +#set_property -dict {LOC AF21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +#set_property -dict {LOC AH22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +#set_property -dict {LOC AF20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +#set_property -dict {LOC AJ19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +#set_property -dict {LOC AH21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +#set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +#set_property -dict {LOC AM19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +#set_property -dict {LOC AK20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +#set_property -dict {LOC AM22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +#set_property -dict {LOC AL22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +#set_property -dict {LOC AM20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +#set_property -dict {LOC AK19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +#set_property -dict {LOC AN19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +#set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +#set_property -dict {LOC AF15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +#set_property -dict {LOC AJ17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +#set_property -dict {LOC AH17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +#set_property -dict {LOC AJ14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +#set_property -dict {LOC AG15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +#set_property -dict {LOC AJ13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +#set_property -dict {LOC AG17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +#set_property -dict {LOC AJ16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +#set_property -dict {LOC AG9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +#set_property -dict {LOC AH9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +#set_property -dict {LOC AK16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +#set_property -dict {LOC AL16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +#set_property -dict {LOC AR13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +#set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +#set_property -dict {LOC AU17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +#set_property -dict {LOC AV17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +#set_property -dict {LOC AN22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +#set_property -dict {LOC AP22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +#set_property -dict {LOC AV22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +#set_property -dict {LOC AV21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +#set_property -dict {LOC AG20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +#set_property -dict {LOC AH20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +#set_property -dict {LOC AK21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +#set_property -dict {LOC AL21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +#set_property -dict {LOC AH16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +#set_property -dict {LOC AH15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +#set_property -dict {LOC AG12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] +#set_property -dict {LOC AK15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] +#set_property -dict {LOC AP16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] +#set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] +#set_property -dict {LOC AP21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] +#set_property -dict {LOC AU20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] +#set_property -dict {LOC AG19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] +#set_property -dict {LOC AL18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] +#set_property -dict {LOC AG14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}] + # QSPI flash #set_property -dict {LOC AF30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}] #set_property -dict {LOC AG30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}] diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile index 2f542a14d..54d446b2e 100644 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile +++ b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile @@ -58,6 +58,9 @@ XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES += ip/eth_xcvr_gt.tcl +# Configuration +CONFIG_TCL_FILES = ./config.tcl + include ../common/vivado.mk program: $(FPGA_TOP).bit diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl new file mode 100644 index 000000000..756e2b3a1 --- /dev/null +++ b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile similarity index 99% rename from fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile rename to fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile index 2f542a14d..54d446b2e 100644 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile +++ b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile @@ -58,6 +58,9 @@ XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES += ip/eth_xcvr_gt.tcl +# Configuration +CONFIG_TCL_FILES = ./config.tcl + include ../common/vivado.mk program: $(FPGA_TOP).bit diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl new file mode 100644 index 000000000..90aa4caeb --- /dev/null +++ b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py index 78e9eb932..423eb9f12 100644 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -48,109 +48,49 @@ class TB: cocotb.start_soon(Clock(dut.clk, 2.56, units="ns").start()) # Ethernet - cocotb.start_soon(Clock(dut.qsfp_0_rx_clk_0, 2.56, units="ns").start()) - self.qsfp_0_0_source = XgmiiSource(dut.qsfp_0_rxd_0, dut.qsfp_0_rxc_0, dut.qsfp_0_rx_clk_0, dut.qsfp_0_rx_rst_0) - cocotb.start_soon(Clock(dut.qsfp_0_tx_clk_0, 2.56, units="ns").start()) - self.qsfp_0_0_sink = XgmiiSink(dut.qsfp_0_txd_0, dut.qsfp_0_txc_0, dut.qsfp_0_tx_clk_0, dut.qsfp_0_tx_rst_0) + self.qsfp_source = [] + self.qsfp_sink = [] - cocotb.start_soon(Clock(dut.qsfp_0_rx_clk_1, 2.56, units="ns").start()) - self.qsfp_0_1_source = XgmiiSource(dut.qsfp_0_rxd_1, dut.qsfp_0_rxc_1, dut.qsfp_0_rx_clk_1, dut.qsfp_0_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp_0_tx_clk_1, 2.56, units="ns").start()) - self.qsfp_0_1_sink = XgmiiSink(dut.qsfp_0_txd_1, dut.qsfp_0_txc_1, dut.qsfp_0_tx_clk_1, dut.qsfp_0_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp_0_rx_clk_2, 2.56, units="ns").start()) - self.qsfp_0_2_source = XgmiiSource(dut.qsfp_0_rxd_2, dut.qsfp_0_rxc_2, dut.qsfp_0_rx_clk_2, dut.qsfp_0_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp_0_tx_clk_2, 2.56, units="ns").start()) - self.qsfp_0_2_sink = XgmiiSink(dut.qsfp_0_txd_2, dut.qsfp_0_txc_2, dut.qsfp_0_tx_clk_2, dut.qsfp_0_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp_0_rx_clk_3, 2.56, units="ns").start()) - self.qsfp_0_3_source = XgmiiSource(dut.qsfp_0_rxd_3, dut.qsfp_0_rxc_3, dut.qsfp_0_rx_clk_3, dut.qsfp_0_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp_0_tx_clk_3, 2.56, units="ns").start()) - self.qsfp_0_3_sink = XgmiiSink(dut.qsfp_0_txd_3, dut.qsfp_0_txc_3, dut.qsfp_0_tx_clk_3, dut.qsfp_0_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_0, 2.56, units="ns").start()) - self.qsfp_1_0_source = XgmiiSource(dut.qsfp_1_rxd_0, dut.qsfp_1_rxc_0, dut.qsfp_1_rx_clk_0, dut.qsfp_1_rx_rst_0) - cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_0, 2.56, units="ns").start()) - self.qsfp_1_0_sink = XgmiiSink(dut.qsfp_1_txd_0, dut.qsfp_1_txc_0, dut.qsfp_1_tx_clk_0, dut.qsfp_1_tx_rst_0) - - cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_1, 2.56, units="ns").start()) - self.qsfp_1_1_source = XgmiiSource(dut.qsfp_1_rxd_1, dut.qsfp_1_rxc_1, dut.qsfp_1_rx_clk_1, dut.qsfp_1_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_1, 2.56, units="ns").start()) - self.qsfp_1_1_sink = XgmiiSink(dut.qsfp_1_txd_1, dut.qsfp_1_txc_1, dut.qsfp_1_tx_clk_1, dut.qsfp_1_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_2, 2.56, units="ns").start()) - self.qsfp_1_2_source = XgmiiSource(dut.qsfp_1_rxd_2, dut.qsfp_1_rxc_2, dut.qsfp_1_rx_clk_2, dut.qsfp_1_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_2, 2.56, units="ns").start()) - self.qsfp_1_2_sink = XgmiiSink(dut.qsfp_1_txd_2, dut.qsfp_1_txc_2, dut.qsfp_1_tx_clk_2, dut.qsfp_1_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_3, 2.56, units="ns").start()) - self.qsfp_1_3_source = XgmiiSource(dut.qsfp_1_rxd_3, dut.qsfp_1_rxc_3, dut.qsfp_1_rx_clk_3, dut.qsfp_1_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_3, 2.56, units="ns").start()) - self.qsfp_1_3_sink = XgmiiSink(dut.qsfp_1_txd_3, dut.qsfp_1_txc_3, dut.qsfp_1_tx_clk_3, dut.qsfp_1_tx_rst_3) + for x in range(2): + sources = [] + sinks = [] + for y in range(4): + cocotb.start_soon(Clock(getattr(dut, f"qsfp_{x}_rx_clk_{y}"), 2.56, units="ns").start()) + source = XgmiiSource(getattr(dut, f"qsfp_{x}_rxd_{y}"), getattr(dut, f"qsfp_{x}_rxc_{y}"), getattr(dut, f"qsfp_{x}_rx_clk_{y}"), getattr(dut, f"qsfp_{x}_rx_rst_{y}")) + sources.append(source) + cocotb.start_soon(Clock(getattr(dut, f"qsfp_{x}_tx_clk_{y}"), 2.56, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"qsfp_{x}_txd_{y}"), getattr(dut, f"qsfp_{x}_txc_{y}"), getattr(dut, f"qsfp_{x}_tx_clk_{y}"), getattr(dut, f"qsfp_{x}_tx_rst_{y}")) + sinks.append(sink) + self.qsfp_source.append(sources) + self.qsfp_sink.append(sinks) dut.user_sw.setimmediatevalue(0) async def init(self): self.dut.rst.setimmediatevalue(0) - self.dut.qsfp_0_rx_rst_0.setimmediatevalue(0) - self.dut.qsfp_0_tx_rst_0.setimmediatevalue(0) - self.dut.qsfp_0_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp_0_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp_0_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp_0_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp_0_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp_0_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp_1_rx_rst_0.setimmediatevalue(0) - self.dut.qsfp_1_tx_rst_0.setimmediatevalue(0) - self.dut.qsfp_1_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp_1_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp_1_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp_1_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp_1_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp_1_tx_rst_3.setimmediatevalue(0) + for x in range(2): + for y in range(4): + getattr(self.dut, f"qsfp_{x}_rx_rst_{y}").setimmediatevalue(0) + getattr(self.dut, f"qsfp_{x}_tx_rst_{y}").setimmediatevalue(0) for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 1 - self.dut.qsfp_0_rx_rst_0.value = 1 - self.dut.qsfp_0_tx_rst_0.value = 1 - self.dut.qsfp_0_rx_rst_1.value = 1 - self.dut.qsfp_0_tx_rst_1.value = 1 - self.dut.qsfp_0_rx_rst_2.value = 1 - self.dut.qsfp_0_tx_rst_2.value = 1 - self.dut.qsfp_0_rx_rst_3.value = 1 - self.dut.qsfp_0_tx_rst_3.value = 1 - self.dut.qsfp_1_rx_rst_0.value = 1 - self.dut.qsfp_1_tx_rst_0.value = 1 - self.dut.qsfp_1_rx_rst_1.value = 1 - self.dut.qsfp_1_tx_rst_1.value = 1 - self.dut.qsfp_1_rx_rst_2.value = 1 - self.dut.qsfp_1_tx_rst_2.value = 1 - self.dut.qsfp_1_rx_rst_3.value = 1 - self.dut.qsfp_1_tx_rst_3.value = 1 + for x in range(2): + for y in range(4): + getattr(self.dut, f"qsfp_{x}_rx_rst_{y}").value = 1 + getattr(self.dut, f"qsfp_{x}_tx_rst_{y}").value = 1 for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 0 - self.dut.qsfp_0_rx_rst_0.value = 0 - self.dut.qsfp_0_tx_rst_0.value = 0 - self.dut.qsfp_0_rx_rst_1.value = 0 - self.dut.qsfp_0_tx_rst_1.value = 0 - self.dut.qsfp_0_rx_rst_2.value = 0 - self.dut.qsfp_0_tx_rst_2.value = 0 - self.dut.qsfp_0_rx_rst_3.value = 0 - self.dut.qsfp_0_tx_rst_3.value = 0 - self.dut.qsfp_1_rx_rst_0.value = 0 - self.dut.qsfp_1_tx_rst_0.value = 0 - self.dut.qsfp_1_rx_rst_1.value = 0 - self.dut.qsfp_1_tx_rst_1.value = 0 - self.dut.qsfp_1_rx_rst_2.value = 0 - self.dut.qsfp_1_tx_rst_2.value = 0 - self.dut.qsfp_1_rx_rst_3.value = 0 - self.dut.qsfp_1_tx_rst_3.value = 0 + for x in range(2): + for y in range(4): + getattr(self.dut, f"qsfp_{x}_rx_rst_{y}").value = 0 + getattr(self.dut, f"qsfp_{x}_tx_rst_{y}").value = 0 @cocotb.test() @@ -170,11 +110,11 @@ async def run_test(dut): test_frame = XgmiiFrame.from_payload(test_pkt.build()) - await tb.qsfp_0_0_source.send(test_frame) + await tb.qsfp_source[0][0].send(test_frame) tb.log.info("receive ARP request") - rx_frame = await tb.qsfp_0_0_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -202,11 +142,11 @@ async def run_test(dut): resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - await tb.qsfp_0_0_source.send(resp_frame) + await tb.qsfp_source[0][0].send(resp_frame) tb.log.info("receive UDP packet") - rx_frame = await tb.qsfp_0_0_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) diff --git a/fpga/lib/eth/example/AU200/fpga_10g/fpga.xdc b/fpga/lib/eth/example/AU200/fpga_10g/fpga.xdc deleted file mode 100644 index daba8a8f4..000000000 --- a/fpga/lib/eth/example/AU200/fpga_10g/fpga.xdc +++ /dev/null @@ -1,259 +0,0 @@ -# XDC constraints for the Xilinx Alveo U200 board -# part: xcu200-fsgd2104-2-e - -# General configuration -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design] -set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] -set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] -set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] - -set_operating_conditions -design_power_budget 160 - -# System clocks -# 300 MHz (DDR 0) -#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] -#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] -#create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p] - -# 300 MHz (DDR 1) -#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] -#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] -#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] - -# 300 MHz (DDR 2) -#set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] -#set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] -#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] - -# 300 MHz (DDR 3) -#set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] -#set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] -#create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p] - -# SI570 user clock -#set_property -dict {LOC AU19 IOSTANDARD LVDS} [get_ports clk_user_p] -#set_property -dict {LOC AV19 IOSTANDARD LVDS} [get_ports clk_user_n] -#create_clock -period 6.400 -name clk_user [get_ports clk_user_p] - -# LEDs -set_property -dict {LOC BC21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] -set_property -dict {LOC BB21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] -set_property -dict {LOC BA20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}] - -set_false_path -to [get_ports {led[*]}] -set_output_delay 0 [get_ports {led[*]}] - -# Reset button -set_property -dict {LOC AL20 IOSTANDARD LVCMOS12} [get_ports reset] - -set_false_path -from [get_ports {reset}] -set_input_delay 0 [get_ports {reset}] - -# DIP switches -set_property -dict {LOC AN22 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] -set_property -dict {LOC AM19 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] -set_property -dict {LOC AL19 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] -set_property -dict {LOC AP20 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] - -set_false_path -from [get_ports {sw[*]}] -set_input_delay 0 [get_ports {sw[*]}] - -# UART -set_property -dict {LOC BF18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd] -set_property -dict {LOC BB20 IOSTANDARD LVCMOS12} [get_ports uart_rxd] - -#set_false_path -to [get_ports {uart_txd}] -#set_output_delay 0 [get_ports {uart_txd}] -#set_false_path -from [get_ports {uart_rxd}] -#set_input_delay 0 [get_ports {uart_rxd}] - -# BMC -#set_property -dict {LOC AR20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[0]}] -#set_property -dict {LOC AM20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[1]}] -#set_property -dict {LOC AM21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[2]}] -#set_property -dict {LOC AN21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[3]}] -#set_property -dict {LOC BB19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_uart_txd}] -#set_property -dict {LOC BA19 IOSTANDARD LVCMOS12} [get_ports {msp_uart_rxd}] - -#set_false_path -to [get_ports {msp_uart_txd}] -#set_output_delay 0 [get_ports {msp_uart_txd}] -#set_false_path -from [get_ports {msp_gpio[*] msp_uart_rxd}] -#set_input_delay 0 [get_ports {msp_gpio[*] msp_uart_rxd}] - -# QSFP28 Interfaces -set_property -dict {LOC N4 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC N3 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC N9 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC N8 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M2 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M1 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M7 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M6 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L4 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L3 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L9 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L8 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K2 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K1 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K7 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K6 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13 -#set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14 -set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18 -set_property -dict {LOC K10 } [get_ports qsfp0_mgt_refclk_1_n] ;# MGTREFCLK1N_231 from U9.17 -set_property -dict {LOC BE16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_modsell] -set_property -dict {LOC BE17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl] -set_property -dict {LOC BE20 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_modprsl] -set_property -dict {LOC BE21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_intl] -set_property -dict {LOC BD18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode] -set_property -dict {LOC AT22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_refclk_reset] -set_property -dict {LOC AT20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[0]}] -set_property -dict {LOC AU22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[1]}] - -# 156.25 MHz MGT reference clock (from SI570) -#create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports qsfp0_mgt_refclk_0_p] - -# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) -#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] - -# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) -create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] - -set_false_path -to [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] -set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] -set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}] -set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}] - -set_property -dict {LOC U4 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC U3 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC U9 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC U8 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T2 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T1 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R4 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R3 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R9 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R8 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P2 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P1 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15 -#set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16 -set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18 -set_property -dict {LOC P10 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U12.17 -set_property -dict {LOC AY20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_modsell] -set_property -dict {LOC BC18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl] -set_property -dict {LOC BC19 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_modprsl] -set_property -dict {LOC AV21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_intl] -set_property -dict {LOC AV22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode] -set_property -dict {LOC AR21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_refclk_reset] -set_property -dict {LOC AR22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[0]}] -set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[1]}] - -# 156.25 MHz MGT reference clock (from SI570) -#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p] - -# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) -#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] - -# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) -create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] - -set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] -set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] -set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] -set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] - -# I2C interface -#set_property -dict {LOC BF19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset] -set_property -dict {LOC BF20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_scl] -set_property -dict {LOC BF17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_sda] - -set_false_path -to [get_ports {i2c_sda i2c_scl}] -set_output_delay 0 [get_ports {i2c_sda i2c_scl}] -set_false_path -from [get_ports {i2c_sda i2c_scl}] -set_input_delay 0 [get_ports {i2c_sda i2c_scl}] - -# PCIe Interface -#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AG9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AG8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AJ9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AJ8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AL4 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AL3 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AL9 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AL8 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AN4 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AN3 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AN9 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AN8 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AR4 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AR3 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AR9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AR8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AU4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AU3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AU9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AU8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AV7 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AV6 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AW4 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AW3 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BB5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BB4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BD5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BD4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BF5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BF4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AM11 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_226 -#set_property -dict {LOC AM10 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_226 -#set_property -dict {LOC BD21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n] - -# 100 MHz MGT reference clock -#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p] - -#set_false_path -from [get_ports {pcie_reset_n}] -#set_input_delay 0 [get_ports {pcie_reset_n}] diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/Makefile b/fpga/lib/eth/example/AU200/fpga_25g/Makefile similarity index 100% rename from fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/Makefile rename to fpga/lib/eth/example/AU200/fpga_25g/Makefile diff --git a/fpga/lib/eth/example/AU200/fpga_10g/README.md b/fpga/lib/eth/example/AU200/fpga_25g/README.md similarity index 100% rename from fpga/lib/eth/example/AU200/fpga_10g/README.md rename to fpga/lib/eth/example/AU200/fpga_25g/README.md diff --git a/fpga/lib/eth/example/AU200/fpga_10g/common/vivado.mk b/fpga/lib/eth/example/AU200/fpga_25g/common/vivado.mk similarity index 76% rename from fpga/lib/eth/example/AU200/fpga_10g/common/vivado.mk rename to fpga/lib/eth/example/AU200/fpga_25g/common/vivado.mk index 21e6a5fed..1402e2382 100644 --- a/fpga/lib/eth/example/AU200/fpga_10g/common/vivado.mk +++ b/fpga/lib/eth/example/AU200/fpga_25g/common/vivado.mk @@ -28,7 +28,7 @@ ################################################################### # phony targets -.PHONY: clean fpga +.PHONY: fpga vivado tmpclean clean distclean # prevent make from deleting intermediate files and reports .PRECIOUS: %.xpr %.bit %.mcs %.prm @@ -40,15 +40,16 @@ CONFIG ?= config.mk FPGA_TOP ?= fpga PROJECT ?= $(FPGA_TOP) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else - XDC_FILES_REL = $(FPGA_TOP).xdc + XDC_FILES_REL = $(PROJECT).xdc endif ################################################################### @@ -60,20 +61,20 @@ endif all: fpga -fpga: $(FPGA_TOP).bit +fpga: $(PROJECT).bit -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr -tmpclean: +tmpclean:: -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt -distclean: clean +distclean:: clean -rm -rf rev ################################################################### @@ -91,12 +92,17 @@ create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done -$(PROJECT).xpr: create_project.tcl +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) # synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr echo "open_project $(PROJECT).xpr" > run_synth.tcl echo "reset_run synth_1" >> run_synth.tcl echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl diff --git a/fpga/lib/eth/example/AU200/fpga_25g/fpga.xdc b/fpga/lib/eth/example/AU200/fpga_25g/fpga.xdc new file mode 100644 index 000000000..53665ef34 --- /dev/null +++ b/fpga/lib/eth/example/AU200/fpga_25g/fpga.xdc @@ -0,0 +1,848 @@ +# XDC constraints for the Xilinx Alveo U200 board +# part: xcu200-fsgd2104-2-e + +# General configuration +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] + +set_operating_conditions -design_power_budget 160 + +# System clocks +# 300 MHz (DDR 0) +#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] +#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] +#create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p] + +# 300 MHz (DDR 1) +#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] +#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] +#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] + +# 300 MHz (DDR 2) +#set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] +#set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] +#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] + +# 300 MHz (DDR 3) +#set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] +#set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] +#create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p] + +# SI570 user clock +#set_property -dict {LOC AU19 IOSTANDARD LVDS} [get_ports clk_user_p] +#set_property -dict {LOC AV19 IOSTANDARD LVDS} [get_ports clk_user_n] +#create_clock -period 6.400 -name clk_user [get_ports clk_user_p] + +# LEDs +set_property -dict {LOC BC21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] +set_property -dict {LOC BB21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] +set_property -dict {LOC BA20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}] + +set_false_path -to [get_ports {led[*]}] +set_output_delay 0 [get_ports {led[*]}] + +# Reset button +set_property -dict {LOC AL20 IOSTANDARD LVCMOS12} [get_ports reset] + +set_false_path -from [get_ports {reset}] +set_input_delay 0 [get_ports {reset}] + +# DIP switches +set_property -dict {LOC AN22 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] +set_property -dict {LOC AM19 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] +set_property -dict {LOC AL19 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] +set_property -dict {LOC AP20 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] + +set_false_path -from [get_ports {sw[*]}] +set_input_delay 0 [get_ports {sw[*]}] + +# UART +set_property -dict {LOC BF18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd] +set_property -dict {LOC BB20 IOSTANDARD LVCMOS12} [get_ports uart_rxd] + +#set_false_path -to [get_ports {uart_txd}] +#set_output_delay 0 [get_ports {uart_txd}] +#set_false_path -from [get_ports {uart_rxd}] +#set_input_delay 0 [get_ports {uart_rxd}] + +# BMC +#set_property -dict {LOC AR20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[0]}] +#set_property -dict {LOC AM20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[1]}] +#set_property -dict {LOC AM21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[2]}] +#set_property -dict {LOC AN21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[3]}] +#set_property -dict {LOC BB19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_uart_txd}] +#set_property -dict {LOC BA19 IOSTANDARD LVCMOS12} [get_ports {msp_uart_rxd}] + +#set_false_path -to [get_ports {msp_uart_txd}] +#set_output_delay 0 [get_ports {msp_uart_txd}] +#set_false_path -from [get_ports {msp_gpio[*] msp_uart_rxd}] +#set_input_delay 0 [get_ports {msp_gpio[*] msp_uart_rxd}] + +# QSFP28 Interfaces +set_property -dict {LOC N4 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N3 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N9 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N8 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M2 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M1 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M7 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M6 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L4 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L3 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L9 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L8 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K2 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K1 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K7 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K6 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13 +#set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14 +set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18 +set_property -dict {LOC K10 } [get_ports qsfp0_mgt_refclk_1_n] ;# MGTREFCLK1N_231 from U9.17 +set_property -dict {LOC BE16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_modsell] +set_property -dict {LOC BE17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl] +set_property -dict {LOC BE20 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_modprsl] +set_property -dict {LOC BE21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_intl] +set_property -dict {LOC BD18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode] +set_property -dict {LOC AT22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_refclk_reset] +set_property -dict {LOC AT20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[0]}] +set_property -dict {LOC AU22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[1]}] + +# 156.25 MHz MGT reference clock (from SI570) +#create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports qsfp0_mgt_refclk_0_p] + +# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) +#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] + +# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) +create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] + +set_false_path -to [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] +set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] +set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}] +set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}] + +set_property -dict {LOC U4 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U3 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U9 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U8 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T2 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T1 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R4 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R3 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R9 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R8 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P2 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P1 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +#set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15 +#set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16 +set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18 +set_property -dict {LOC P10 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U12.17 +set_property -dict {LOC AY20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_modsell] +set_property -dict {LOC BC18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl] +set_property -dict {LOC BC19 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_modprsl] +set_property -dict {LOC AV21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_intl] +set_property -dict {LOC AV22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode] +set_property -dict {LOC AR21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_refclk_reset] +set_property -dict {LOC AR22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[0]}] +set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[1]}] + +# 156.25 MHz MGT reference clock (from SI570) +#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p] + +# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) +#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] + +# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) +create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] + +set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] +set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] +set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] +set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] + +# I2C interface +#set_property -dict {LOC BF19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset] +set_property -dict {LOC BF20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_scl] +set_property -dict {LOC BF17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_sda] + +set_false_path -to [get_ports {i2c_sda i2c_scl}] +set_output_delay 0 [get_ports {i2c_sda i2c_scl}] +set_false_path -from [get_ports {i2c_sda i2c_scl}] +set_input_delay 0 [get_ports {i2c_sda i2c_scl}] + +# PCIe Interface +#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AG9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AG8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AJ9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AJ8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AL4 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AL3 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AL9 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AL8 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AN4 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AN3 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AN9 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AN8 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR4 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR3 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AV7 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AV6 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AW4 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AW3 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BB5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BB4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BD5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BD4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BF5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BF4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AM11 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_226 +#set_property -dict {LOC AM10 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_226 +#set_property -dict {LOC BD21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n] + +# 100 MHz MGT reference clock +#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p] + +#set_false_path -from [get_ports {pcie_reset_n}] +#set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 C0 +#set_property -dict {LOC AT36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +#set_property -dict {LOC AV36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +#set_property -dict {LOC AV37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +#set_property -dict {LOC AW35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +#set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +#set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +#set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +#set_property -dict {LOC BA40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +#set_property -dict {LOC BA37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +#set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +#set_property -dict {LOC AR35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +#set_property -dict {LOC BA39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +#set_property -dict {LOC BB40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +#set_property -dict {LOC AN36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +#set_property -dict {LOC AP35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +#set_property -dict {LOC AP36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +#set_property -dict {LOC AR36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +#set_property -dict {LOC AT35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +#set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +#set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +#set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +#set_property -dict {LOC AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[0]}] +#set_property -dict {LOC AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[0]}] +#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[1]}] +#set_property -dict {LOC AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[1]}] +#set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}] +#set_property -dict {LOC BC40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}] +#set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}] +#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}] +#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}] +#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}] +#set_property -dict {LOC BB39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +#set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}] +#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}] +#set_property -dict {LOC AU36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +#set_property -dict {LOC AU31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] + +#set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +#set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +#set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +#set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +#set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +#set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +#set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +#set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +#set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +#set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +#set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +#set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +#set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +#set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +#set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +#set_property -dict {LOC BF29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +#set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +#set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +#set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +#set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +#set_property -dict {LOC BC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +#set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +#set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +#set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +#set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +#set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +#set_property -dict {LOC AV34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +#set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +#set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +#set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +#set_property -dict {LOC BA35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +#set_property -dict {LOC BA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +#set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +#set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +#set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +#set_property -dict {LOC AT32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +#set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +#set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +#set_property -dict {LOC AR31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +#set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +#set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +#set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +#set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +#set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +#set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +#set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +#set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +#set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +#set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +#set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +#set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +#set_property -dict {LOC AV29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +#set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +#set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +#set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +#set_property -dict {LOC BD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +#set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +#set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +#set_property -dict {LOC BD35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +#set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +#set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +#set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +#set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +#set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +#set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +#set_property -dict {LOC BF43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +#set_property -dict {LOC BF42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +#set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +#set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +#set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +#set_property -dict {LOC BF41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +#set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +#set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +#set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +#set_property -dict {LOC BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +#set_property -dict {LOC BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +#set_property -dict {LOC BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +#set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +#set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +#set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +#set_property -dict {LOC BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +#set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +#set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +#set_property -dict {LOC AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +#set_property -dict {LOC AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +#set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +#set_property -dict {LOC BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +#set_property -dict {LOC AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +#set_property -dict {LOC AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +#set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}] +#set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}] +#set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}] +#set_property -dict {LOC AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}] +#set_property -dict {LOC AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}] +#set_property -dict {LOC AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}] +#set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}] +#set_property -dict {LOC AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}] +#set_property -dict {LOC AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}] +#set_property -dict {LOC AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}] +#set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}] +#set_property -dict {LOC BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}] +#set_property -dict {LOC BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}] +#set_property -dict {LOC BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}] +#set_property -dict {LOC BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}] +#set_property -dict {LOC BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}] +#set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}] +#set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}] + +# DDR4 C1 +#set_property -dict {LOC AN24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +#set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +#set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +#set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +#set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +#set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +#set_property -dict {LOC AV24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +#set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +#set_property -dict {LOC AY25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +#set_property -dict {LOC BA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +#set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +#set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +#set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +#set_property -dict {LOC AL24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +#set_property -dict {LOC AL25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +#set_property -dict {LOC AM25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +#set_property -dict {LOC AN23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +#set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +#set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +#set_property -dict {LOC BC22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +#set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +#set_property -dict {LOC AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[0]}] +#set_property -dict {LOC AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[0]}] +#set_property -dict {LOC AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[1]}] +#set_property -dict {LOC AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[1]}] +#set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}] +#set_property -dict {LOC BB24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}] +#set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}] +#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}] +#set_property -dict {LOC AR23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}] +#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}] +#set_property -dict {LOC AW25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +#set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}] +#set_property -dict {LOC AP24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}] +#set_property -dict {LOC AT23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +#set_property -dict {LOC AR17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] + +#set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +#set_property -dict {LOC BD7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +#set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +#set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +#set_property -dict {LOC BD10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +#set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +#set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +#set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +#set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +#set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +#set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +#set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +#set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +#set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +#set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +#set_property -dict {LOC BA11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +#set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +#set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +#set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +#set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +#set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +#set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +#set_property -dict {LOC BA7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +#set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +#set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +#set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +#set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +#set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +#set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +#set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +#set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +#set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +#set_property -dict {LOC BE13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +#set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +#set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +#set_property -dict {LOC BD13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +#set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +#set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +#set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +#set_property -dict {LOC BF13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +#set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +#set_property -dict {LOC BA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +#set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +#set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +#set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +#set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +#set_property -dict {LOC BC11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +#set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +#set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +#set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +#set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +#set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +#set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +#set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +#set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +#set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +#set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +#set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +#set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +#set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +#set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +#set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +#set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +#set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +#set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +#set_property -dict {LOC BF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +#set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +#set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +#set_property -dict {LOC BD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +#set_property -dict {LOC BC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +#set_property -dict {LOC BF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +#set_property -dict {LOC BE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +#set_property -dict {LOC BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +#set_property -dict {LOC BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +#set_property -dict {LOC BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +#set_property -dict {LOC BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +#set_property -dict {LOC AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +#set_property -dict {LOC AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +#set_property -dict {LOC AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +#set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +#set_property -dict {LOC BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +#set_property -dict {LOC BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +#set_property -dict {LOC BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +#set_property -dict {LOC BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +#set_property -dict {LOC AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +#set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +#set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +#set_property -dict {LOC AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +#set_property -dict {LOC BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +#set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +#set_property -dict {LOC BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] +#set_property -dict {LOC BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] +#set_property -dict {LOC BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}] +#set_property -dict {LOC BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}] +#set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}] +#set_property -dict {LOC BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}] +#set_property -dict {LOC AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}] +#set_property -dict {LOC AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}] +#set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}] +#set_property -dict {LOC AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}] +#set_property -dict {LOC AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}] +#set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}] +#set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}] +#set_property -dict {LOC AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}] +#set_property -dict {LOC BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}] +#set_property -dict {LOC BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}] +#set_property -dict {LOC BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}] +#set_property -dict {LOC BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}] + +# DDR4 C2 +#set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +#set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +#set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +#set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +#set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +#set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +#set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +#set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +#set_property -dict {LOC A32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +#set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +#set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +#set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +#set_property -dict {LOC M30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +#set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +#set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +#set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +#set_property -dict {LOC K30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +#set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +#set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +#set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +#set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}] +#set_property -dict {LOC C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[0]}] +#set_property -dict {LOC B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[0]}] +#set_property -dict {LOC D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[1]}] +#set_property -dict {LOC D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[1]}] +#set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}] +#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}] +#set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}] +#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}] +#set_property -dict {LOC L30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}] +#set_property -dict {LOC K31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}] +#set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +#set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}] +#set_property -dict {LOC F34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}] +#set_property -dict {LOC M29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +#set_property -dict {LOC D36 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] + +#set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] +#set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] +#set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] +#set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] +#set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] +#set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] +#set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] +#set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] +#set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] +#set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] +#set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] +#set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] +#set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] +#set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] +#set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] +#set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] +#set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] +#set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] +#set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] +#set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] +#set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] +#set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] +#set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] +#set_property -dict {LOC F29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] +#set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] +#set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] +#set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] +#set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] +#set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] +#set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] +#set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] +#set_property -dict {LOC C28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] +#set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] +#set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] +#set_property -dict {LOC D38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] +#set_property -dict {LOC E35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] +#set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] +#set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] +#set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] +#set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] +#set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] +#set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] +#set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] +#set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] +#set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] +#set_property -dict {LOC M32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] +#set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] +#set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] +#set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] +#set_property -dict {LOC K35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] +#set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] +#set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] +#set_property -dict {LOC J34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] +#set_property -dict {LOC J33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] +#set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] +#set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] +#set_property -dict {LOC H36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] +#set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] +#set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] +#set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] +#set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] +#set_property -dict {LOC K38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] +#set_property -dict {LOC G35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] +#set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] +#set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] +#set_property -dict {LOC B37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] +#set_property -dict {LOC A37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] +#set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] +#set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] +#set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] +#set_property -dict {LOC A40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] +#set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] +#set_property -dict {LOC N26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] +#set_property -dict {LOC M26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] +#set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] +#set_property -dict {LOC P28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] +#set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] +#set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] +#set_property -dict {LOC M27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] +#set_property -dict {LOC L28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] +#set_property -dict {LOC D29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] +#set_property -dict {LOC D30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] +#set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] +#set_property -dict {LOC H27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] +#set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] +#set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] +#set_property -dict {LOC C29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] +#set_property -dict {LOC B29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] +#set_property -dict {LOC E39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] +#set_property -dict {LOC E40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] +#set_property -dict {LOC G37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] +#set_property -dict {LOC F37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] +#set_property -dict {LOC N31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}] +#set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}] +#set_property -dict {LOC T30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}] +#set_property -dict {LOC R31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}] +#set_property -dict {LOC L35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}] +#set_property -dict {LOC L36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}] +#set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}] +#set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}] +#set_property -dict {LOC J38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}] +#set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}] +#set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}] +#set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}] +#set_property -dict {LOC B39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}] +#set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}] +#set_property -dict {LOC C37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}] +#set_property -dict {LOC C38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}] + +# DDR4 C3 +#set_property -dict {LOC K15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}] +#set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}] +#set_property -dict {LOC F14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}] +#set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}] +#set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}] +#set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}] +#set_property -dict {LOC B14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}] +#set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}] +#set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}] +#set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}] +#set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}] +#set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}] +#set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}] +#set_property -dict {LOC K16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}] +#set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}] +#set_property -dict {LOC E15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}] +#set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}] +#set_property -dict {LOC J15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}] +#set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}] +#set_property -dict {LOC D13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}] +#set_property -dict {LOC J13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}] +#set_property -dict {LOC L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[0]}] +#set_property -dict {LOC L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[0]}] +#set_property -dict {LOC G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[1]}] +#set_property -dict {LOC G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[1]}] +#set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}] +#set_property -dict {LOC L15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}] +#set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}] +#set_property -dict {LOC D16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}] +#set_property -dict {LOC M14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}] +#set_property -dict {LOC M13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}] +#set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}] +#set_property -dict {LOC C16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}] +#set_property -dict {LOC E16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}] +#set_property -dict {LOC J14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}] +#set_property -dict {LOC D21 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}] + +#set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}] +#set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}] +#set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}] +#set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}] +#set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}] +#set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}] +#set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}] +#set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}] +#set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}] +#set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}] +#set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}] +#set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}] +#set_property -dict {LOC L24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}] +#set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}] +#set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}] +#set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}] +#set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}] +#set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}] +#set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}] +#set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}] +#set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}] +#set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}] +#set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}] +#set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}] +#set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}] +#set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}] +#set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}] +#set_property -dict {LOC R17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}] +#set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}] +#set_property -dict {LOC T20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}] +#set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}] +#set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}] +#set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}] +#set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}] +#set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}] +#set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}] +#set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}] +#set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}] +#set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}] +#set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}] +#set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}] +#set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}] +#set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}] +#set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}] +#set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}] +#set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}] +#set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}] +#set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}] +#set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}] +#set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}] +#set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}] +#set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}] +#set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}] +#set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}] +#set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}] +#set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}] +#set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}] +#set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}] +#set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}] +#set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}] +#set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}] +#set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}] +#set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}] +#set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}] +#set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}] +#set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}] +#set_property -dict {LOC N13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}] +#set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}] +#set_property -dict {LOC T15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}] +#set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}] +#set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}] +#set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}] +#set_property -dict {LOC T22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}] +#set_property -dict {LOC R22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}] +#set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}] +#set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}] +#set_property -dict {LOC J21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}] +#set_property -dict {LOC H21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}] +#set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}] +#set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}] +#set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}] +#set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}] +#set_property -dict {LOC K18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}] +#set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}] +#set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}] +#set_property -dict {LOC P18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}] +#set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}] +#set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}] +#set_property -dict {LOC A25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}] +#set_property -dict {LOC A24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}] +#set_property -dict {LOC D24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}] +#set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}] +#set_property -dict {LOC C17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}] +#set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}] +#set_property -dict {LOC B19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}] +#set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}] +#set_property -dict {LOC F18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}] +#set_property -dict {LOC F17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}] +#set_property -dict {LOC H19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}] +#set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}] +#set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}] +#set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}] +#set_property -dict {LOC H23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}] +#set_property -dict {LOC H22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}] +#set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}] +#set_property -dict {LOC P15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}] +#set_property -dict {LOC T13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}] +#set_property -dict {LOC R13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}] diff --git a/fpga/lib/eth/example/AU200/fpga_10g/fpga/Makefile b/fpga/lib/eth/example/AU200/fpga_25g/fpga/Makefile similarity index 99% rename from fpga/lib/eth/example/AU200/fpga_10g/fpga/Makefile rename to fpga/lib/eth/example/AU200/fpga_25g/fpga/Makefile index 14b9a0249..632b41026 100644 --- a/fpga/lib/eth/example/AU200/fpga_10g/fpga/Makefile +++ b/fpga/lib/eth/example/AU200/fpga_25g/fpga/Makefile @@ -59,6 +59,9 @@ XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES += ip/eth_xcvr_gt.tcl +# Configuration +CONFIG_TCL_FILES = ./config.tcl + include ../common/vivado.mk program: $(FPGA_TOP).bit diff --git a/fpga/lib/eth/example/AU200/fpga_25g/fpga/config.tcl b/fpga/lib/eth/example/AU200/fpga_25g/fpga/config.tcl new file mode 100644 index 000000000..756e2b3a1 --- /dev/null +++ b/fpga/lib/eth/example/AU200/fpga_25g/fpga/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/AU200/fpga_25g/fpga_10g/Makefile b/fpga/lib/eth/example/AU200/fpga_25g/fpga_10g/Makefile new file mode 100644 index 000000000..632b41026 --- /dev/null +++ b/fpga/lib/eth/example/AU200/fpga_25g/fpga_10g/Makefile @@ -0,0 +1,114 @@ + +# FPGA settings +FPGA_PART = xcu200-fsgd2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/debounce_switch.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete_64.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v +SYN_FILES += lib/eth/rtl/udp_64.v +SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v +SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v +SYN_FILES += lib/eth/rtl/ip_complete_64.v +SYN_FILES += lib/eth/rtl/ip_64.v +SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v +SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl + +# IP +IP_TCL_FILES += ip/eth_xcvr_gt.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%.mcs %.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + diff --git a/fpga/lib/eth/example/AU200/fpga_25g/fpga_10g/config.tcl b/fpga/lib/eth/example/AU200/fpga_25g/fpga_10g/config.tcl new file mode 100644 index 000000000..90aa4caeb --- /dev/null +++ b/fpga/lib/eth/example/AU200/fpga_25g/fpga_10g/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/lib/eth/example/AU200/fpga_25g/ip/eth_xcvr_gt.tcl similarity index 100% rename from fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/ip/eth_xcvr_gt.tcl rename to fpga/lib/eth/example/AU200/fpga_25g/ip/eth_xcvr_gt.tcl diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/lib/eth b/fpga/lib/eth/example/AU200/fpga_25g/lib/eth similarity index 100% rename from fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/lib/eth rename to fpga/lib/eth/example/AU200/fpga_25g/lib/eth diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/rtl/debounce_switch.v b/fpga/lib/eth/example/AU200/fpga_25g/rtl/debounce_switch.v similarity index 100% rename from fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/rtl/debounce_switch.v rename to fpga/lib/eth/example/AU200/fpga_25g/rtl/debounce_switch.v diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/fpga/lib/eth/example/AU200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v similarity index 100% rename from fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/rtl/eth_xcvr_phy_wrapper.v rename to fpga/lib/eth/example/AU200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v diff --git a/fpga/lib/eth/example/AU200/fpga_10g/rtl/fpga.v b/fpga/lib/eth/example/AU200/fpga_25g/rtl/fpga.v similarity index 100% rename from fpga/lib/eth/example/AU200/fpga_10g/rtl/fpga.v rename to fpga/lib/eth/example/AU200/fpga_25g/rtl/fpga.v diff --git a/fpga/lib/eth/example/AU200/fpga_10g/rtl/fpga_core.v b/fpga/lib/eth/example/AU200/fpga_25g/rtl/fpga_core.v similarity index 100% rename from fpga/lib/eth/example/AU200/fpga_10g/rtl/fpga_core.v rename to fpga/lib/eth/example/AU200/fpga_25g/rtl/fpga_core.v diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/rtl/sync_signal.v b/fpga/lib/eth/example/AU200/fpga_25g/rtl/sync_signal.v similarity index 100% rename from fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/rtl/sync_signal.v rename to fpga/lib/eth/example/AU200/fpga_25g/rtl/sync_signal.v diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/AU200/fpga_25g/tb/fpga_core/Makefile similarity index 100% rename from fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/Makefile rename to fpga/lib/eth/example/AU200/fpga_25g/tb/fpga_core/Makefile diff --git a/fpga/lib/eth/example/AU200/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py similarity index 53% rename from fpga/lib/eth/example/AU200/fpga_10g/tb/fpga_core/test_fpga_core.py rename to fpga/lib/eth/example/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py index 6f609015c..d90e185ee 100644 --- a/fpga/lib/eth/example/AU200/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -45,112 +45,52 @@ class TB: self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) - cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) + cocotb.start_soon(Clock(dut.clk, 2.56, units="ns").start()) # Ethernet - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_1, 6.4, units="ns").start()) - self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1, dut.qsfp0_rx_clk_1, dut.qsfp0_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_1, 6.4, units="ns").start()) - self.qsfp0_1_sink = XgmiiSink(dut.qsfp0_txd_1, dut.qsfp0_txc_1, dut.qsfp0_tx_clk_1, dut.qsfp0_tx_rst_1) + self.qsfp_source = [] + self.qsfp_sink = [] - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_2, 6.4, units="ns").start()) - self.qsfp0_2_source = XgmiiSource(dut.qsfp0_rxd_2, dut.qsfp0_rxc_2, dut.qsfp0_rx_clk_2, dut.qsfp0_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_2, 6.4, units="ns").start()) - self.qsfp0_2_sink = XgmiiSink(dut.qsfp0_txd_2, dut.qsfp0_txc_2, dut.qsfp0_tx_clk_2, dut.qsfp0_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_3, 6.4, units="ns").start()) - self.qsfp0_3_source = XgmiiSource(dut.qsfp0_rxd_3, dut.qsfp0_rxc_3, dut.qsfp0_rx_clk_3, dut.qsfp0_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_3, 6.4, units="ns").start()) - self.qsfp0_3_sink = XgmiiSink(dut.qsfp0_txd_3, dut.qsfp0_txc_3, dut.qsfp0_tx_clk_3, dut.qsfp0_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_4, 6.4, units="ns").start()) - self.qsfp0_4_source = XgmiiSource(dut.qsfp0_rxd_4, dut.qsfp0_rxc_4, dut.qsfp0_rx_clk_4, dut.qsfp0_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_4, 6.4, units="ns").start()) - self.qsfp0_4_sink = XgmiiSink(dut.qsfp0_txd_4, dut.qsfp0_txc_4, dut.qsfp0_tx_clk_4, dut.qsfp0_tx_rst_4) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_1, 6.4, units="ns").start()) - self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_1, 6.4, units="ns").start()) - self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_2, 6.4, units="ns").start()) - self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_2, 6.4, units="ns").start()) - self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_3, 6.4, units="ns").start()) - self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_3, 6.4, units="ns").start()) - self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_4, 6.4, units="ns").start()) - self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 6.4, units="ns").start()) - self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4) + for x in range(2): + sources = [] + sinks = [] + for y in range(1, 5): + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_rx_clk_{y}"), 2.56, units="ns").start()) + source = XgmiiSource(getattr(dut, f"qsfp{x}_rxd_{y}"), getattr(dut, f"qsfp{x}_rxc_{y}"), getattr(dut, f"qsfp{x}_rx_clk_{y}"), getattr(dut, f"qsfp{x}_rx_rst_{y}")) + sources.append(source) + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_tx_clk_{y}"), 2.56, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"qsfp{x}_txd_{y}"), getattr(dut, f"qsfp{x}_txc_{y}"), getattr(dut, f"qsfp{x}_tx_clk_{y}"), getattr(dut, f"qsfp{x}_tx_rst_{y}")) + sinks.append(sink) + self.qsfp_source.append(sources) + self.qsfp_sink.append(sinks) dut.sw.setimmediatevalue(0) async def init(self): self.dut.rst.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_4.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) + for x in range(2): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(0) + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(0) for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 1 - self.dut.qsfp0_rx_rst_1.value = 1 - self.dut.qsfp0_tx_rst_1.value = 1 - self.dut.qsfp0_rx_rst_2.value = 1 - self.dut.qsfp0_tx_rst_2.value = 1 - self.dut.qsfp0_rx_rst_3.value = 1 - self.dut.qsfp0_tx_rst_3.value = 1 - self.dut.qsfp0_rx_rst_4.value = 1 - self.dut.qsfp0_tx_rst_4.value = 1 - self.dut.qsfp1_rx_rst_1.value = 1 - self.dut.qsfp1_tx_rst_1.value = 1 - self.dut.qsfp1_rx_rst_2.value = 1 - self.dut.qsfp1_tx_rst_2.value = 1 - self.dut.qsfp1_rx_rst_3.value = 1 - self.dut.qsfp1_tx_rst_3.value = 1 - self.dut.qsfp1_rx_rst_4.value = 1 - self.dut.qsfp1_tx_rst_4.value = 1 + for x in range(2): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").value = 1 + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").value = 1 for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 0 - self.dut.qsfp0_rx_rst_1.value = 0 - self.dut.qsfp0_tx_rst_1.value = 0 - self.dut.qsfp0_rx_rst_2.value = 0 - self.dut.qsfp0_tx_rst_2.value = 0 - self.dut.qsfp0_rx_rst_3.value = 0 - self.dut.qsfp0_tx_rst_3.value = 0 - self.dut.qsfp0_rx_rst_4.value = 0 - self.dut.qsfp0_tx_rst_4.value = 0 - self.dut.qsfp1_rx_rst_1.value = 0 - self.dut.qsfp1_tx_rst_1.value = 0 - self.dut.qsfp1_rx_rst_2.value = 0 - self.dut.qsfp1_tx_rst_2.value = 0 - self.dut.qsfp1_rx_rst_3.value = 0 - self.dut.qsfp1_tx_rst_3.value = 0 - self.dut.qsfp1_rx_rst_4.value = 0 - self.dut.qsfp1_tx_rst_4.value = 0 + for x in range(2): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").value = 0 + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").value = 0 @cocotb.test() @@ -170,11 +110,11 @@ async def run_test(dut): test_frame = XgmiiFrame.from_payload(test_pkt.build()) - await tb.qsfp0_1_source.send(test_frame) + await tb.qsfp_source[0][0].send(test_frame) tb.log.info("receive ARP request") - rx_frame = await tb.qsfp0_1_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -202,11 +142,11 @@ async def run_test(dut): resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - await tb.qsfp0_1_source.send(resp_frame) + await tb.qsfp_source[0][0].send(resp_frame) tb.log.info("receive UDP packet") - rx_frame = await tb.qsfp0_1_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) diff --git a/fpga/lib/eth/example/AU250/fpga_10g/fpga.xdc b/fpga/lib/eth/example/AU250/fpga_10g/fpga.xdc deleted file mode 100644 index c60f13e00..000000000 --- a/fpga/lib/eth/example/AU250/fpga_10g/fpga.xdc +++ /dev/null @@ -1,259 +0,0 @@ -# XDC constraints for the Xilinx Alveo U250 board -# part: xcu250-figd2104-2-e - -# General configuration -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design] -set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] -set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] -set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] - -set_operating_conditions -design_power_budget 160 - -# System clocks -# 300 MHz (DDR 0) -#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] -#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] -#create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p] - -# 300 MHz (DDR 1) -#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] -#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] -#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] - -# 300 MHz (DDR 2) -#set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] -#set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] -#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] - -# 300 MHz (DDR 3) -#set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] -#set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] -#create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p] - -# SI570 user clock -#set_property -dict {LOC AU19 IOSTANDARD LVDS} [get_ports clk_user_p] -#set_property -dict {LOC AV19 IOSTANDARD LVDS} [get_ports clk_user_n] -#create_clock -period 6.400 -name clk_user [get_ports clk_user_p] - -# LEDs -set_property -dict {LOC BC21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] -set_property -dict {LOC BB21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] -set_property -dict {LOC BA20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}] - -set_false_path -to [get_ports {led[*]}] -set_output_delay 0 [get_ports {led[*]}] - -# Reset button -set_property -dict {LOC AL20 IOSTANDARD LVCMOS12} [get_ports reset] - -set_false_path -from [get_ports {reset}] -set_input_delay 0 [get_ports {reset}] - -# DIP switches -set_property -dict {LOC AN22 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] -set_property -dict {LOC AM19 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] -set_property -dict {LOC AL19 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] -set_property -dict {LOC AP20 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] - -set_false_path -from [get_ports {sw[*]}] -set_input_delay 0 [get_ports {sw[*]}] - -# UART -set_property -dict {LOC BF18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd] -set_property -dict {LOC BB20 IOSTANDARD LVCMOS12} [get_ports uart_rxd] - -#set_false_path -to [get_ports {uart_txd}] -#set_output_delay 0 [get_ports {uart_txd}] -#set_false_path -from [get_ports {uart_rxd}] -#set_input_delay 0 [get_ports {uart_rxd}] - -# BMC -#set_property -dict {LOC AR20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[0]}] -#set_property -dict {LOC AM20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[1]}] -#set_property -dict {LOC AM21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[2]}] -#set_property -dict {LOC AN21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[3]}] -#set_property -dict {LOC BB19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_uart_txd}] -#set_property -dict {LOC BA19 IOSTANDARD LVCMOS12} [get_ports {msp_uart_rxd}] - -#set_false_path -to [get_ports {msp_uart_txd}] -#set_output_delay 0 [get_ports {msp_uart_txd}] -#set_false_path -from [get_ports {msp_gpio[*] msp_uart_rxd}] -#set_input_delay 0 [get_ports {msp_gpio[*] msp_uart_rxd}] - -# QSFP28 Interfaces -set_property -dict {LOC N4 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC N3 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC N9 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC N8 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC M2 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC M1 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC M7 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC M6 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC L4 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC L3 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC L9 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC L8 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC K2 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC K1 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC K7 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC K6 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13 -#set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14 -set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18 -set_property -dict {LOC K10 } [get_ports qsfp0_mgt_refclk_1_n] ;# MGTREFCLK1N_231 from U9.17 -set_property -dict {LOC BE16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_modsell] -set_property -dict {LOC BE17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl] -set_property -dict {LOC BE20 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_modprsl] -set_property -dict {LOC BE21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_intl] -set_property -dict {LOC BD18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode] -set_property -dict {LOC AT22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_refclk_reset] -set_property -dict {LOC AT20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[0]}] -set_property -dict {LOC AU22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[1]}] - -# 156.25 MHz MGT reference clock (from SI570) -#create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports qsfp0_mgt_refclk_0_p] - -# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) -#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] - -# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) -create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] - -set_false_path -to [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] -set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] -set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}] -set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}] - -set_property -dict {LOC U4 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC U3 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC U9 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC U8 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC T2 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC T1 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC R4 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC R3 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC R9 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC R8 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC P2 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC P1 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC P7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC P6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 -#set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15 -#set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16 -set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18 -set_property -dict {LOC P10 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U12.17 -set_property -dict {LOC AY20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_modsell] -set_property -dict {LOC BC18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl] -set_property -dict {LOC BC19 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_modprsl] -set_property -dict {LOC AV21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_intl] -set_property -dict {LOC AV22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode] -set_property -dict {LOC AR21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_refclk_reset] -set_property -dict {LOC AR22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[0]}] -set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[1]}] - -# 156.25 MHz MGT reference clock (from SI570) -#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p] - -# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) -#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] - -# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) -create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] - -set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] -set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] -set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] -set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] - -# I2C interface -#set_property -dict {LOC BF19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset] -set_property -dict {LOC BF20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_scl] -set_property -dict {LOC BF17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_sda] - -set_false_path -to [get_ports {i2c_sda i2c_scl}] -set_output_delay 0 [get_ports {i2c_sda i2c_scl}] -set_false_path -from [get_ports {i2c_sda i2c_scl}] -set_input_delay 0 [get_ports {i2c_sda i2c_scl}] - -# PCIe Interface -#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AG9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AG8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AJ9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AJ8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AL4 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AL3 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AL9 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AL8 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AN4 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AN3 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AN9 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AN8 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AR4 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AR3 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AR9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AR8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AU4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AU3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AU9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AU8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4 -#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4 -#set_property -dict {LOC AV7 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4 -#set_property -dict {LOC AV6 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4 -#set_property -dict {LOC AW4 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4 -#set_property -dict {LOC AW3 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4 -#set_property -dict {LOC BB5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4 -#set_property -dict {LOC BB4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4 -#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4 -#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4 -#set_property -dict {LOC BD5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4 -#set_property -dict {LOC BD4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4 -#set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4 -#set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4 -#set_property -dict {LOC BF5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4 -#set_property -dict {LOC BF4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4 -#set_property -dict {LOC AM11 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_226 -#set_property -dict {LOC AM10 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_226 -#set_property -dict {LOC BD21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n] - -# 100 MHz MGT reference clock -#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p] - -#set_false_path -from [get_ports {pcie_reset_n}] -#set_input_delay 0 [get_ports {pcie_reset_n}] diff --git a/fpga/lib/eth/example/AU250/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/AU250/fpga_10g/tb/fpga_core/test_fpga_core.py deleted file mode 100644 index 6f609015c..000000000 --- a/fpga/lib/eth/example/AU250/fpga_10g/tb/fpga_core/test_fpga_core.py +++ /dev/null @@ -1,289 +0,0 @@ -""" - -Copyright (c) 2020 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -""" - -import logging -import os - -from scapy.layers.l2 import Ether, ARP -from scapy.layers.inet import IP, UDP - -import cocotb_test.simulator - -import cocotb -from cocotb.log import SimLog -from cocotb.clock import Clock -from cocotb.triggers import RisingEdge - -from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink - - -class TB: - def __init__(self, dut): - self.dut = dut - - self.log = SimLog("cocotb.tb") - self.log.setLevel(logging.DEBUG) - - cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) - - # Ethernet - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_1, 6.4, units="ns").start()) - self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1, dut.qsfp0_rx_clk_1, dut.qsfp0_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_1, 6.4, units="ns").start()) - self.qsfp0_1_sink = XgmiiSink(dut.qsfp0_txd_1, dut.qsfp0_txc_1, dut.qsfp0_tx_clk_1, dut.qsfp0_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_2, 6.4, units="ns").start()) - self.qsfp0_2_source = XgmiiSource(dut.qsfp0_rxd_2, dut.qsfp0_rxc_2, dut.qsfp0_rx_clk_2, dut.qsfp0_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_2, 6.4, units="ns").start()) - self.qsfp0_2_sink = XgmiiSink(dut.qsfp0_txd_2, dut.qsfp0_txc_2, dut.qsfp0_tx_clk_2, dut.qsfp0_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_3, 6.4, units="ns").start()) - self.qsfp0_3_source = XgmiiSource(dut.qsfp0_rxd_3, dut.qsfp0_rxc_3, dut.qsfp0_rx_clk_3, dut.qsfp0_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_3, 6.4, units="ns").start()) - self.qsfp0_3_sink = XgmiiSink(dut.qsfp0_txd_3, dut.qsfp0_txc_3, dut.qsfp0_tx_clk_3, dut.qsfp0_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_4, 6.4, units="ns").start()) - self.qsfp0_4_source = XgmiiSource(dut.qsfp0_rxd_4, dut.qsfp0_rxc_4, dut.qsfp0_rx_clk_4, dut.qsfp0_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_4, 6.4, units="ns").start()) - self.qsfp0_4_sink = XgmiiSink(dut.qsfp0_txd_4, dut.qsfp0_txc_4, dut.qsfp0_tx_clk_4, dut.qsfp0_tx_rst_4) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_1, 6.4, units="ns").start()) - self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_1, 6.4, units="ns").start()) - self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_2, 6.4, units="ns").start()) - self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_2, 6.4, units="ns").start()) - self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_3, 6.4, units="ns").start()) - self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_3, 6.4, units="ns").start()) - self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_4, 6.4, units="ns").start()) - self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 6.4, units="ns").start()) - self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4) - - dut.sw.setimmediatevalue(0) - - async def init(self): - - self.dut.rst.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_4.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) - - for k in range(10): - await RisingEdge(self.dut.clk) - - self.dut.rst.value = 1 - self.dut.qsfp0_rx_rst_1.value = 1 - self.dut.qsfp0_tx_rst_1.value = 1 - self.dut.qsfp0_rx_rst_2.value = 1 - self.dut.qsfp0_tx_rst_2.value = 1 - self.dut.qsfp0_rx_rst_3.value = 1 - self.dut.qsfp0_tx_rst_3.value = 1 - self.dut.qsfp0_rx_rst_4.value = 1 - self.dut.qsfp0_tx_rst_4.value = 1 - self.dut.qsfp1_rx_rst_1.value = 1 - self.dut.qsfp1_tx_rst_1.value = 1 - self.dut.qsfp1_rx_rst_2.value = 1 - self.dut.qsfp1_tx_rst_2.value = 1 - self.dut.qsfp1_rx_rst_3.value = 1 - self.dut.qsfp1_tx_rst_3.value = 1 - self.dut.qsfp1_rx_rst_4.value = 1 - self.dut.qsfp1_tx_rst_4.value = 1 - - for k in range(10): - await RisingEdge(self.dut.clk) - - self.dut.rst.value = 0 - self.dut.qsfp0_rx_rst_1.value = 0 - self.dut.qsfp0_tx_rst_1.value = 0 - self.dut.qsfp0_rx_rst_2.value = 0 - self.dut.qsfp0_tx_rst_2.value = 0 - self.dut.qsfp0_rx_rst_3.value = 0 - self.dut.qsfp0_tx_rst_3.value = 0 - self.dut.qsfp0_rx_rst_4.value = 0 - self.dut.qsfp0_tx_rst_4.value = 0 - self.dut.qsfp1_rx_rst_1.value = 0 - self.dut.qsfp1_tx_rst_1.value = 0 - self.dut.qsfp1_rx_rst_2.value = 0 - self.dut.qsfp1_tx_rst_2.value = 0 - self.dut.qsfp1_rx_rst_3.value = 0 - self.dut.qsfp1_tx_rst_3.value = 0 - self.dut.qsfp1_rx_rst_4.value = 0 - self.dut.qsfp1_tx_rst_4.value = 0 - - -@cocotb.test() -async def run_test(dut): - - tb = TB(dut) - - await tb.init() - - tb.log.info("test UDP RX packet") - - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00') - ip = IP(src='192.168.1.100', dst='192.168.1.128') - udp = UDP(sport=5678, dport=1234) - test_pkt = eth / ip / udp / payload - - test_frame = XgmiiFrame.from_payload(test_pkt.build()) - - await tb.qsfp0_1_source.send(test_frame) - - tb.log.info("receive ARP request") - - rx_frame = await tb.qsfp0_1_sink.recv() - - rx_pkt = Ether(bytes(rx_frame.get_payload())) - - tb.log.info("RX packet: %s", repr(rx_pkt)) - - assert rx_pkt.dst == 'ff:ff:ff:ff:ff:ff' - assert rx_pkt.src == test_pkt.dst - assert rx_pkt[ARP].hwtype == 1 - assert rx_pkt[ARP].ptype == 0x0800 - assert rx_pkt[ARP].hwlen == 6 - assert rx_pkt[ARP].plen == 4 - assert rx_pkt[ARP].op == 1 - assert rx_pkt[ARP].hwsrc == test_pkt.dst - assert rx_pkt[ARP].psrc == test_pkt[IP].dst - assert rx_pkt[ARP].hwdst == '00:00:00:00:00:00' - assert rx_pkt[ARP].pdst == test_pkt[IP].src - - tb.log.info("send ARP response") - - eth = Ether(src=test_pkt.src, dst=test_pkt.dst) - arp = ARP(hwtype=1, ptype=0x0800, hwlen=6, plen=4, op=2, - hwsrc=test_pkt.src, psrc=test_pkt[IP].src, - hwdst=test_pkt.dst, pdst=test_pkt[IP].dst) - resp_pkt = eth / arp - - resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - - await tb.qsfp0_1_source.send(resp_frame) - - tb.log.info("receive UDP packet") - - rx_frame = await tb.qsfp0_1_sink.recv() - - rx_pkt = Ether(bytes(rx_frame.get_payload())) - - tb.log.info("RX packet: %s", repr(rx_pkt)) - - assert rx_pkt.dst == test_pkt.src - assert rx_pkt.src == test_pkt.dst - assert rx_pkt[IP].dst == test_pkt[IP].src - assert rx_pkt[IP].src == test_pkt[IP].dst - assert rx_pkt[UDP].dport == test_pkt[UDP].sport - assert rx_pkt[UDP].sport == test_pkt[UDP].dport - assert rx_pkt[UDP].payload == test_pkt[UDP].payload - - await RisingEdge(dut.clk) - await RisingEdge(dut.clk) - - -# cocotb-test - -tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) -axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'lib', 'axis', 'rtl')) -eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) - - -def test_fpga_core(request): - dut = "fpga_core" - module = os.path.splitext(os.path.basename(__file__))[0] - toplevel = dut - - verilog_sources = [ - os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g_fifo.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), - os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "eth_axis_rx.v"), - os.path.join(eth_rtl_dir, "eth_axis_tx.v"), - os.path.join(eth_rtl_dir, "udp_complete_64.v"), - os.path.join(eth_rtl_dir, "udp_checksum_gen_64.v"), - os.path.join(eth_rtl_dir, "udp_64.v"), - os.path.join(eth_rtl_dir, "udp_ip_rx_64.v"), - os.path.join(eth_rtl_dir, "udp_ip_tx_64.v"), - os.path.join(eth_rtl_dir, "ip_complete_64.v"), - os.path.join(eth_rtl_dir, "ip_64.v"), - os.path.join(eth_rtl_dir, "ip_eth_rx_64.v"), - os.path.join(eth_rtl_dir, "ip_eth_tx_64.v"), - os.path.join(eth_rtl_dir, "ip_arb_mux.v"), - os.path.join(eth_rtl_dir, "arp.v"), - os.path.join(eth_rtl_dir, "arp_cache.v"), - os.path.join(eth_rtl_dir, "arp_eth_rx.v"), - os.path.join(eth_rtl_dir, "arp_eth_tx.v"), - os.path.join(eth_rtl_dir, "eth_arb_mux.v"), - os.path.join(axis_rtl_dir, "arbiter.v"), - os.path.join(axis_rtl_dir, "priority_encoder.v"), - os.path.join(axis_rtl_dir, "axis_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), - ] - - parameters = {} - - # parameters['A'] = val - - extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} - - sim_build = os.path.join(tests_dir, "sim_build", - request.node.name.replace('[', '-').replace(']', '')) - - cocotb_test.simulator.run( - python_search=[tests_dir], - verilog_sources=verilog_sources, - toplevel=toplevel, - module=module, - parameters=parameters, - sim_build=sim_build, - extra_env=extra_env, - ) diff --git a/fpga/lib/eth/example/AU200/fpga_10g/Makefile b/fpga/lib/eth/example/AU250/fpga_25g/Makefile similarity index 100% rename from fpga/lib/eth/example/AU200/fpga_10g/Makefile rename to fpga/lib/eth/example/AU250/fpga_25g/Makefile diff --git a/fpga/lib/eth/example/AU250/fpga_10g/README.md b/fpga/lib/eth/example/AU250/fpga_25g/README.md similarity index 100% rename from fpga/lib/eth/example/AU250/fpga_10g/README.md rename to fpga/lib/eth/example/AU250/fpga_25g/README.md diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/common/vivado.mk b/fpga/lib/eth/example/AU250/fpga_25g/common/vivado.mk similarity index 76% rename from fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/common/vivado.mk rename to fpga/lib/eth/example/AU250/fpga_25g/common/vivado.mk index 21e6a5fed..1402e2382 100644 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/common/vivado.mk +++ b/fpga/lib/eth/example/AU250/fpga_25g/common/vivado.mk @@ -28,7 +28,7 @@ ################################################################### # phony targets -.PHONY: clean fpga +.PHONY: fpga vivado tmpclean clean distclean # prevent make from deleting intermediate files and reports .PRECIOUS: %.xpr %.bit %.mcs %.prm @@ -40,15 +40,16 @@ CONFIG ?= config.mk FPGA_TOP ?= fpga PROJECT ?= $(FPGA_TOP) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else - XDC_FILES_REL = $(FPGA_TOP).xdc + XDC_FILES_REL = $(PROJECT).xdc endif ################################################################### @@ -60,20 +61,20 @@ endif all: fpga -fpga: $(FPGA_TOP).bit +fpga: $(PROJECT).bit -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr -tmpclean: +tmpclean:: -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt -distclean: clean +distclean:: clean -rm -rf rev ################################################################### @@ -91,12 +92,17 @@ create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done -$(PROJECT).xpr: create_project.tcl +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) # synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr echo "open_project $(PROJECT).xpr" > run_synth.tcl echo "reset_run synth_1" >> run_synth.tcl echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl diff --git a/fpga/lib/eth/example/AU250/fpga_25g/fpga.xdc b/fpga/lib/eth/example/AU250/fpga_25g/fpga.xdc new file mode 100644 index 000000000..2d006125a --- /dev/null +++ b/fpga/lib/eth/example/AU250/fpga_25g/fpga.xdc @@ -0,0 +1,848 @@ +# XDC constraints for the Xilinx Alveo U250 board +# part: xcu250-figd2104-2-e + +# General configuration +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] + +set_operating_conditions -design_power_budget 160 + +# System clocks +# 300 MHz (DDR 0) +#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] +#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] +#create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p] + +# 300 MHz (DDR 1) +#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] +#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] +#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] + +# 300 MHz (DDR 2) +#set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] +#set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] +#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] + +# 300 MHz (DDR 3) +#set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] +#set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] +#create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p] + +# SI570 user clock +#set_property -dict {LOC AU19 IOSTANDARD LVDS} [get_ports clk_user_p] +#set_property -dict {LOC AV19 IOSTANDARD LVDS} [get_ports clk_user_n] +#create_clock -period 6.400 -name clk_user [get_ports clk_user_p] + +# LEDs +set_property -dict {LOC BC21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] +set_property -dict {LOC BB21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] +set_property -dict {LOC BA20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}] + +set_false_path -to [get_ports {led[*]}] +set_output_delay 0 [get_ports {led[*]}] + +# Reset button +set_property -dict {LOC AL20 IOSTANDARD LVCMOS12} [get_ports reset] + +set_false_path -from [get_ports {reset}] +set_input_delay 0 [get_ports {reset}] + +# DIP switches +set_property -dict {LOC AN22 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] +set_property -dict {LOC AM19 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] +set_property -dict {LOC AL19 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] +set_property -dict {LOC AP20 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] + +set_false_path -from [get_ports {sw[*]}] +set_input_delay 0 [get_ports {sw[*]}] + +# UART +set_property -dict {LOC BF18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd] +set_property -dict {LOC BB20 IOSTANDARD LVCMOS12} [get_ports uart_rxd] + +#set_false_path -to [get_ports {uart_txd}] +#set_output_delay 0 [get_ports {uart_txd}] +#set_false_path -from [get_ports {uart_rxd}] +#set_input_delay 0 [get_ports {uart_rxd}] + +# BMC +#set_property -dict {LOC AR20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[0]}] +#set_property -dict {LOC AM20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[1]}] +#set_property -dict {LOC AM21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[2]}] +#set_property -dict {LOC AN21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[3]}] +#set_property -dict {LOC BB19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_uart_txd}] +#set_property -dict {LOC BA19 IOSTANDARD LVCMOS12} [get_ports {msp_uart_rxd}] + +#set_false_path -to [get_ports {msp_uart_txd}] +#set_output_delay 0 [get_ports {msp_uart_txd}] +#set_false_path -from [get_ports {msp_gpio[*] msp_uart_rxd}] +#set_input_delay 0 [get_ports {msp_gpio[*] msp_uart_rxd}] + +# QSFP28 Interfaces +set_property -dict {LOC N4 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC N3 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC N9 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC N8 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC M2 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC M1 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC M7 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC M6 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC L4 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC L3 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC L9 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC L8 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC K2 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC K1 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC K7 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC K6 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +#set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13 +#set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14 +set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18 +set_property -dict {LOC K10 } [get_ports qsfp0_mgt_refclk_1_n] ;# MGTREFCLK1N_231 from U9.17 +set_property -dict {LOC BE16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_modsell] +set_property -dict {LOC BE17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl] +set_property -dict {LOC BE20 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_modprsl] +set_property -dict {LOC BE21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_intl] +set_property -dict {LOC BD18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode] +set_property -dict {LOC AT22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_refclk_reset] +set_property -dict {LOC AT20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[0]}] +set_property -dict {LOC AU22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[1]}] + +# 156.25 MHz MGT reference clock (from SI570) +#create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports qsfp0_mgt_refclk_0_p] + +# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) +#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] + +# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) +create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] + +set_false_path -to [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] +set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] +set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}] +set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}] + +set_property -dict {LOC U4 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC U3 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC U9 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC U8 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC T2 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC T1 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC R4 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC R3 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC R9 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC R8 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC P2 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC P1 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC P7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 +set_property -dict {LOC P6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 +#set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15 +#set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16 +set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18 +set_property -dict {LOC P10 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U12.17 +set_property -dict {LOC AY20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_modsell] +set_property -dict {LOC BC18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl] +set_property -dict {LOC BC19 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_modprsl] +set_property -dict {LOC AV21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_intl] +set_property -dict {LOC AV22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode] +set_property -dict {LOC AR21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_refclk_reset] +set_property -dict {LOC AR22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[0]}] +set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[1]}] + +# 156.25 MHz MGT reference clock (from SI570) +#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p] + +# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) +#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] + +# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) +create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] + +set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] +set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] +set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] +set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] + +# I2C interface +#set_property -dict {LOC BF19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset] +set_property -dict {LOC BF20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_scl] +set_property -dict {LOC BF17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_sda] + +set_false_path -to [get_ports {i2c_sda i2c_scl}] +set_output_delay 0 [get_ports {i2c_sda i2c_scl}] +set_false_path -from [get_ports {i2c_sda i2c_scl}] +set_input_delay 0 [get_ports {i2c_sda i2c_scl}] + +# PCIe Interface +#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AG9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AG8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AJ9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AJ8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AL4 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AL3 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AL9 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AL8 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AN4 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AN3 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AN9 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AN8 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AR4 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AR3 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AR9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AR8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AU4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AU3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AU9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AU8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4 +#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4 +#set_property -dict {LOC AV7 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4 +#set_property -dict {LOC AV6 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4 +#set_property -dict {LOC AW4 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4 +#set_property -dict {LOC AW3 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4 +#set_property -dict {LOC BB5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4 +#set_property -dict {LOC BB4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4 +#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4 +#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4 +#set_property -dict {LOC BD5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4 +#set_property -dict {LOC BD4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4 +#set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4 +#set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4 +#set_property -dict {LOC BF5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4 +#set_property -dict {LOC BF4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4 +#set_property -dict {LOC AM11 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_226 +#set_property -dict {LOC AM10 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_226 +#set_property -dict {LOC BD21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n] + +# 100 MHz MGT reference clock +#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p] + +#set_false_path -from [get_ports {pcie_reset_n}] +#set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 C0 +#set_property -dict {LOC AT36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +#set_property -dict {LOC AV36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +#set_property -dict {LOC AV37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +#set_property -dict {LOC AW35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +#set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +#set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +#set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +#set_property -dict {LOC BA40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +#set_property -dict {LOC BA37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +#set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +#set_property -dict {LOC AR35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +#set_property -dict {LOC BA39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +#set_property -dict {LOC BB40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +#set_property -dict {LOC AN36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +#set_property -dict {LOC AP35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +#set_property -dict {LOC AP36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +#set_property -dict {LOC AR36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +#set_property -dict {LOC AT35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +#set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +#set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +#set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +#set_property -dict {LOC AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[0]}] +#set_property -dict {LOC AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[0]}] +#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[1]}] +#set_property -dict {LOC AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[1]}] +#set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}] +#set_property -dict {LOC BC40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}] +#set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}] +#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}] +#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}] +#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}] +#set_property -dict {LOC BB39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +#set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}] +#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}] +#set_property -dict {LOC AU36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +#set_property -dict {LOC AU31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] + +#set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +#set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +#set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +#set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +#set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +#set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +#set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +#set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +#set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +#set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +#set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +#set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +#set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +#set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +#set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +#set_property -dict {LOC BF29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +#set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +#set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +#set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +#set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +#set_property -dict {LOC BC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +#set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +#set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +#set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +#set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +#set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +#set_property -dict {LOC AV34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +#set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +#set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +#set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +#set_property -dict {LOC BA35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +#set_property -dict {LOC BA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +#set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +#set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +#set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +#set_property -dict {LOC AT32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +#set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +#set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +#set_property -dict {LOC AR31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +#set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +#set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +#set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +#set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +#set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +#set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +#set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +#set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +#set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +#set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +#set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +#set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +#set_property -dict {LOC AV29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +#set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +#set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +#set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +#set_property -dict {LOC BD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +#set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +#set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +#set_property -dict {LOC BD35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +#set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +#set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +#set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +#set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +#set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +#set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +#set_property -dict {LOC BF43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +#set_property -dict {LOC BF42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +#set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +#set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +#set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +#set_property -dict {LOC BF41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +#set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +#set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +#set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +#set_property -dict {LOC BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +#set_property -dict {LOC BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +#set_property -dict {LOC BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +#set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +#set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +#set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +#set_property -dict {LOC BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +#set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +#set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +#set_property -dict {LOC AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +#set_property -dict {LOC AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +#set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +#set_property -dict {LOC BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +#set_property -dict {LOC AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +#set_property -dict {LOC AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +#set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}] +#set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}] +#set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}] +#set_property -dict {LOC AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}] +#set_property -dict {LOC AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}] +#set_property -dict {LOC AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}] +#set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}] +#set_property -dict {LOC AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}] +#set_property -dict {LOC AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}] +#set_property -dict {LOC AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}] +#set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}] +#set_property -dict {LOC BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}] +#set_property -dict {LOC BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}] +#set_property -dict {LOC BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}] +#set_property -dict {LOC BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}] +#set_property -dict {LOC BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}] +#set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}] +#set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}] + +# DDR4 C1 +#set_property -dict {LOC AN24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +#set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +#set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +#set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +#set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +#set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +#set_property -dict {LOC AV24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +#set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +#set_property -dict {LOC AY25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +#set_property -dict {LOC BA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +#set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +#set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +#set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +#set_property -dict {LOC AL24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +#set_property -dict {LOC AL25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +#set_property -dict {LOC AM25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +#set_property -dict {LOC AN23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +#set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +#set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +#set_property -dict {LOC BC22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +#set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +#set_property -dict {LOC AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[0]}] +#set_property -dict {LOC AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[0]}] +#set_property -dict {LOC AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[1]}] +#set_property -dict {LOC AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[1]}] +#set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}] +#set_property -dict {LOC BB24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}] +#set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}] +#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}] +#set_property -dict {LOC AR23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}] +#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}] +#set_property -dict {LOC AW25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +#set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}] +#set_property -dict {LOC AP24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}] +#set_property -dict {LOC AT23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +#set_property -dict {LOC AR17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] + +#set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +#set_property -dict {LOC BD7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +#set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +#set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +#set_property -dict {LOC BD10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +#set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +#set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +#set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +#set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +#set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +#set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +#set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +#set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +#set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +#set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +#set_property -dict {LOC BA11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +#set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +#set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +#set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +#set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +#set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +#set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +#set_property -dict {LOC BA7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +#set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +#set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +#set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +#set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +#set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +#set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +#set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +#set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +#set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +#set_property -dict {LOC BE13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +#set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +#set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +#set_property -dict {LOC BD13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +#set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +#set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +#set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +#set_property -dict {LOC BF13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +#set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +#set_property -dict {LOC BA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +#set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +#set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +#set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +#set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +#set_property -dict {LOC BC11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +#set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +#set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +#set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +#set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +#set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +#set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +#set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +#set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +#set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +#set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +#set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +#set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +#set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +#set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +#set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +#set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +#set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +#set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +#set_property -dict {LOC BF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +#set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +#set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +#set_property -dict {LOC BD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +#set_property -dict {LOC BC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +#set_property -dict {LOC BF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +#set_property -dict {LOC BE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +#set_property -dict {LOC BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +#set_property -dict {LOC BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +#set_property -dict {LOC BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +#set_property -dict {LOC BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +#set_property -dict {LOC AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +#set_property -dict {LOC AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +#set_property -dict {LOC AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +#set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +#set_property -dict {LOC BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +#set_property -dict {LOC BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +#set_property -dict {LOC BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +#set_property -dict {LOC BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +#set_property -dict {LOC AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +#set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +#set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +#set_property -dict {LOC AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +#set_property -dict {LOC BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +#set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +#set_property -dict {LOC BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] +#set_property -dict {LOC BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] +#set_property -dict {LOC BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}] +#set_property -dict {LOC BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}] +#set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}] +#set_property -dict {LOC BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}] +#set_property -dict {LOC AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}] +#set_property -dict {LOC AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}] +#set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}] +#set_property -dict {LOC AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}] +#set_property -dict {LOC AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}] +#set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}] +#set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}] +#set_property -dict {LOC AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}] +#set_property -dict {LOC BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}] +#set_property -dict {LOC BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}] +#set_property -dict {LOC BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}] +#set_property -dict {LOC BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}] + +# DDR4 C2 +#set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +#set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +#set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +#set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +#set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +#set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +#set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +#set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +#set_property -dict {LOC A32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +#set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +#set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +#set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +#set_property -dict {LOC M30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +#set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +#set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +#set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +#set_property -dict {LOC K30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +#set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +#set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +#set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +#set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}] +#set_property -dict {LOC C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[0]}] +#set_property -dict {LOC B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[0]}] +#set_property -dict {LOC D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[1]}] +#set_property -dict {LOC D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[1]}] +#set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}] +#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}] +#set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}] +#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}] +#set_property -dict {LOC L30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}] +#set_property -dict {LOC K31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}] +#set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +#set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}] +#set_property -dict {LOC F34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}] +#set_property -dict {LOC M29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +#set_property -dict {LOC D36 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] + +#set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] +#set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] +#set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] +#set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] +#set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] +#set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] +#set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] +#set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] +#set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] +#set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] +#set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] +#set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] +#set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] +#set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] +#set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] +#set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] +#set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] +#set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] +#set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] +#set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] +#set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] +#set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] +#set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] +#set_property -dict {LOC F29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] +#set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] +#set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] +#set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] +#set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] +#set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] +#set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] +#set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] +#set_property -dict {LOC C28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] +#set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] +#set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] +#set_property -dict {LOC D38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] +#set_property -dict {LOC E35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] +#set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] +#set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] +#set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] +#set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] +#set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] +#set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] +#set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] +#set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] +#set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] +#set_property -dict {LOC M32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] +#set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] +#set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] +#set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] +#set_property -dict {LOC K35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] +#set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] +#set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] +#set_property -dict {LOC J34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] +#set_property -dict {LOC J33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] +#set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] +#set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] +#set_property -dict {LOC H36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] +#set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] +#set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] +#set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] +#set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] +#set_property -dict {LOC K38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] +#set_property -dict {LOC G35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] +#set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] +#set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] +#set_property -dict {LOC B37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] +#set_property -dict {LOC A37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] +#set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] +#set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] +#set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] +#set_property -dict {LOC A40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] +#set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] +#set_property -dict {LOC N26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] +#set_property -dict {LOC M26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] +#set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] +#set_property -dict {LOC P28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] +#set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] +#set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] +#set_property -dict {LOC M27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] +#set_property -dict {LOC L28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] +#set_property -dict {LOC D29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] +#set_property -dict {LOC D30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] +#set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] +#set_property -dict {LOC H27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] +#set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] +#set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] +#set_property -dict {LOC C29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] +#set_property -dict {LOC B29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] +#set_property -dict {LOC E39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] +#set_property -dict {LOC E40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] +#set_property -dict {LOC G37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] +#set_property -dict {LOC F37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] +#set_property -dict {LOC N31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}] +#set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}] +#set_property -dict {LOC T30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}] +#set_property -dict {LOC R31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}] +#set_property -dict {LOC L35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}] +#set_property -dict {LOC L36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}] +#set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}] +#set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}] +#set_property -dict {LOC J38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}] +#set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}] +#set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}] +#set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}] +#set_property -dict {LOC B39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}] +#set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}] +#set_property -dict {LOC C37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}] +#set_property -dict {LOC C38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}] + +# DDR4 C3 +#set_property -dict {LOC K15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}] +#set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}] +#set_property -dict {LOC F14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}] +#set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}] +#set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}] +#set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}] +#set_property -dict {LOC B14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}] +#set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}] +#set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}] +#set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}] +#set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}] +#set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}] +#set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}] +#set_property -dict {LOC K16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}] +#set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}] +#set_property -dict {LOC E15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}] +#set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}] +#set_property -dict {LOC J15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}] +#set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}] +#set_property -dict {LOC D13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}] +#set_property -dict {LOC J13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}] +#set_property -dict {LOC L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[0]}] +#set_property -dict {LOC L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[0]}] +#set_property -dict {LOC G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[1]}] +#set_property -dict {LOC G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[1]}] +#set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}] +#set_property -dict {LOC L15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}] +#set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}] +#set_property -dict {LOC D16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}] +#set_property -dict {LOC M14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}] +#set_property -dict {LOC M13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}] +#set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}] +#set_property -dict {LOC C16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}] +#set_property -dict {LOC E16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}] +#set_property -dict {LOC J14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}] +#set_property -dict {LOC D21 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}] + +#set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}] +#set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}] +#set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}] +#set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}] +#set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}] +#set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}] +#set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}] +#set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}] +#set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}] +#set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}] +#set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}] +#set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}] +#set_property -dict {LOC L24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}] +#set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}] +#set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}] +#set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}] +#set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}] +#set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}] +#set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}] +#set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}] +#set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}] +#set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}] +#set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}] +#set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}] +#set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}] +#set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}] +#set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}] +#set_property -dict {LOC R17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}] +#set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}] +#set_property -dict {LOC T20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}] +#set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}] +#set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}] +#set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}] +#set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}] +#set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}] +#set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}] +#set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}] +#set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}] +#set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}] +#set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}] +#set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}] +#set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}] +#set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}] +#set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}] +#set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}] +#set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}] +#set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}] +#set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}] +#set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}] +#set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}] +#set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}] +#set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}] +#set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}] +#set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}] +#set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}] +#set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}] +#set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}] +#set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}] +#set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}] +#set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}] +#set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}] +#set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}] +#set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}] +#set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}] +#set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}] +#set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}] +#set_property -dict {LOC N13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}] +#set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}] +#set_property -dict {LOC T15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}] +#set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}] +#set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}] +#set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}] +#set_property -dict {LOC T22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}] +#set_property -dict {LOC R22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}] +#set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}] +#set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}] +#set_property -dict {LOC J21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}] +#set_property -dict {LOC H21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}] +#set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}] +#set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}] +#set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}] +#set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}] +#set_property -dict {LOC K18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}] +#set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}] +#set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}] +#set_property -dict {LOC P18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}] +#set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}] +#set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}] +#set_property -dict {LOC A25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}] +#set_property -dict {LOC A24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}] +#set_property -dict {LOC D24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}] +#set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}] +#set_property -dict {LOC C17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}] +#set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}] +#set_property -dict {LOC B19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}] +#set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}] +#set_property -dict {LOC F18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}] +#set_property -dict {LOC F17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}] +#set_property -dict {LOC H19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}] +#set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}] +#set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}] +#set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}] +#set_property -dict {LOC H23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}] +#set_property -dict {LOC H22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}] +#set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}] +#set_property -dict {LOC P15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}] +#set_property -dict {LOC T13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}] +#set_property -dict {LOC R13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}] diff --git a/fpga/lib/eth/example/AU250/fpga_10g/fpga/Makefile b/fpga/lib/eth/example/AU250/fpga_25g/fpga/Makefile similarity index 99% rename from fpga/lib/eth/example/AU250/fpga_10g/fpga/Makefile rename to fpga/lib/eth/example/AU250/fpga_25g/fpga/Makefile index c165e710d..ae7c4ef1b 100644 --- a/fpga/lib/eth/example/AU250/fpga_10g/fpga/Makefile +++ b/fpga/lib/eth/example/AU250/fpga_25g/fpga/Makefile @@ -59,6 +59,9 @@ XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES += ip/eth_xcvr_gt.tcl +# Configuration +CONFIG_TCL_FILES = ./config.tcl + include ../common/vivado.mk program: $(FPGA_TOP).bit diff --git a/fpga/lib/eth/example/AU250/fpga_25g/fpga/config.tcl b/fpga/lib/eth/example/AU250/fpga_25g/fpga/config.tcl new file mode 100644 index 000000000..756e2b3a1 --- /dev/null +++ b/fpga/lib/eth/example/AU250/fpga_25g/fpga/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/AU250/fpga_25g/fpga_10g/Makefile b/fpga/lib/eth/example/AU250/fpga_25g/fpga_10g/Makefile new file mode 100644 index 000000000..ae7c4ef1b --- /dev/null +++ b/fpga/lib/eth/example/AU250/fpga_25g/fpga_10g/Makefile @@ -0,0 +1,114 @@ + +# FPGA settings +FPGA_PART = xcu250-figd2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/debounce_switch.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete_64.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v +SYN_FILES += lib/eth/rtl/udp_64.v +SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v +SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v +SYN_FILES += lib/eth/rtl/ip_complete_64.v +SYN_FILES += lib/eth/rtl/ip_64.v +SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v +SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl + +# IP +IP_TCL_FILES += ip/eth_xcvr_gt.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%.mcs %.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + diff --git a/fpga/lib/eth/example/AU250/fpga_25g/fpga_10g/config.tcl b/fpga/lib/eth/example/AU250/fpga_25g/fpga_10g/config.tcl new file mode 100644 index 000000000..90aa4caeb --- /dev/null +++ b/fpga/lib/eth/example/AU250/fpga_25g/fpga_10g/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/AU200/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/lib/eth/example/AU250/fpga_25g/ip/eth_xcvr_gt.tcl similarity index 100% rename from fpga/lib/eth/example/AU200/fpga_10g/ip/eth_xcvr_gt.tcl rename to fpga/lib/eth/example/AU250/fpga_25g/ip/eth_xcvr_gt.tcl diff --git a/fpga/lib/eth/example/AU200/fpga_10g/lib/eth b/fpga/lib/eth/example/AU250/fpga_25g/lib/eth similarity index 100% rename from fpga/lib/eth/example/AU200/fpga_10g/lib/eth rename to fpga/lib/eth/example/AU250/fpga_25g/lib/eth diff --git a/fpga/lib/eth/example/AU200/fpga_10g/rtl/debounce_switch.v b/fpga/lib/eth/example/AU250/fpga_25g/rtl/debounce_switch.v similarity index 100% rename from fpga/lib/eth/example/AU200/fpga_10g/rtl/debounce_switch.v rename to fpga/lib/eth/example/AU250/fpga_25g/rtl/debounce_switch.v diff --git a/fpga/lib/eth/example/AU200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/fpga/lib/eth/example/AU250/fpga_25g/rtl/eth_xcvr_phy_wrapper.v similarity index 100% rename from fpga/lib/eth/example/AU200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v rename to fpga/lib/eth/example/AU250/fpga_25g/rtl/eth_xcvr_phy_wrapper.v diff --git a/fpga/lib/eth/example/AU250/fpga_10g/rtl/fpga.v b/fpga/lib/eth/example/AU250/fpga_25g/rtl/fpga.v similarity index 100% rename from fpga/lib/eth/example/AU250/fpga_10g/rtl/fpga.v rename to fpga/lib/eth/example/AU250/fpga_25g/rtl/fpga.v diff --git a/fpga/lib/eth/example/AU250/fpga_10g/rtl/fpga_core.v b/fpga/lib/eth/example/AU250/fpga_25g/rtl/fpga_core.v similarity index 100% rename from fpga/lib/eth/example/AU250/fpga_10g/rtl/fpga_core.v rename to fpga/lib/eth/example/AU250/fpga_25g/rtl/fpga_core.v diff --git a/fpga/lib/eth/example/AU200/fpga_10g/rtl/sync_signal.v b/fpga/lib/eth/example/AU250/fpga_25g/rtl/sync_signal.v similarity index 100% rename from fpga/lib/eth/example/AU200/fpga_10g/rtl/sync_signal.v rename to fpga/lib/eth/example/AU250/fpga_25g/rtl/sync_signal.v diff --git a/fpga/lib/eth/example/AU200/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/AU250/fpga_25g/tb/fpga_core/Makefile similarity index 100% rename from fpga/lib/eth/example/AU200/fpga_10g/tb/fpga_core/Makefile rename to fpga/lib/eth/example/AU250/fpga_25g/tb/fpga_core/Makefile diff --git a/fpga/lib/eth/example/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py new file mode 100644 index 000000000..d90e185ee --- /dev/null +++ b/fpga/lib/eth/example/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -0,0 +1,229 @@ +""" + +Copyright (c) 2020 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +""" + +import logging +import os + +from scapy.layers.l2 import Ether, ARP +from scapy.layers.inet import IP, UDP + +import cocotb_test.simulator + +import cocotb +from cocotb.log import SimLog +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge + +from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = SimLog("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 2.56, units="ns").start()) + + # Ethernet + self.qsfp_source = [] + self.qsfp_sink = [] + + for x in range(2): + sources = [] + sinks = [] + for y in range(1, 5): + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_rx_clk_{y}"), 2.56, units="ns").start()) + source = XgmiiSource(getattr(dut, f"qsfp{x}_rxd_{y}"), getattr(dut, f"qsfp{x}_rxc_{y}"), getattr(dut, f"qsfp{x}_rx_clk_{y}"), getattr(dut, f"qsfp{x}_rx_rst_{y}")) + sources.append(source) + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_tx_clk_{y}"), 2.56, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"qsfp{x}_txd_{y}"), getattr(dut, f"qsfp{x}_txc_{y}"), getattr(dut, f"qsfp{x}_tx_clk_{y}"), getattr(dut, f"qsfp{x}_tx_rst_{y}")) + sinks.append(sink) + self.qsfp_source.append(sources) + self.qsfp_sink.append(sinks) + + dut.sw.setimmediatevalue(0) + + async def init(self): + + self.dut.rst.setimmediatevalue(0) + for x in range(2): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(0) + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(0) + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst.value = 1 + for x in range(2): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").value = 1 + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").value = 1 + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst.value = 0 + for x in range(2): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").value = 0 + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").value = 0 + + +@cocotb.test() +async def run_test(dut): + + tb = TB(dut) + + await tb.init() + + tb.log.info("test UDP RX packet") + + payload = bytes([x % 256 for x in range(256)]) + eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00') + ip = IP(src='192.168.1.100', dst='192.168.1.128') + udp = UDP(sport=5678, dport=1234) + test_pkt = eth / ip / udp / payload + + test_frame = XgmiiFrame.from_payload(test_pkt.build()) + + await tb.qsfp_source[0][0].send(test_frame) + + tb.log.info("receive ARP request") + + rx_frame = await tb.qsfp_sink[0][0].recv() + + rx_pkt = Ether(bytes(rx_frame.get_payload())) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + assert rx_pkt.dst == 'ff:ff:ff:ff:ff:ff' + assert rx_pkt.src == test_pkt.dst + assert rx_pkt[ARP].hwtype == 1 + assert rx_pkt[ARP].ptype == 0x0800 + assert rx_pkt[ARP].hwlen == 6 + assert rx_pkt[ARP].plen == 4 + assert rx_pkt[ARP].op == 1 + assert rx_pkt[ARP].hwsrc == test_pkt.dst + assert rx_pkt[ARP].psrc == test_pkt[IP].dst + assert rx_pkt[ARP].hwdst == '00:00:00:00:00:00' + assert rx_pkt[ARP].pdst == test_pkt[IP].src + + tb.log.info("send ARP response") + + eth = Ether(src=test_pkt.src, dst=test_pkt.dst) + arp = ARP(hwtype=1, ptype=0x0800, hwlen=6, plen=4, op=2, + hwsrc=test_pkt.src, psrc=test_pkt[IP].src, + hwdst=test_pkt.dst, pdst=test_pkt[IP].dst) + resp_pkt = eth / arp + + resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) + + await tb.qsfp_source[0][0].send(resp_frame) + + tb.log.info("receive UDP packet") + + rx_frame = await tb.qsfp_sink[0][0].recv() + + rx_pkt = Ether(bytes(rx_frame.get_payload())) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + assert rx_pkt.dst == test_pkt.src + assert rx_pkt.src == test_pkt.dst + assert rx_pkt[IP].dst == test_pkt[IP].src + assert rx_pkt[IP].src == test_pkt[IP].dst + assert rx_pkt[UDP].dport == test_pkt[UDP].sport + assert rx_pkt[UDP].sport == test_pkt[UDP].dport + assert rx_pkt[UDP].payload == test_pkt[UDP].payload + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'lib', 'axis', 'rtl')) +eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) + + +def test_fpga_core(request): + dut = "fpga_core" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, f"{dut}.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g_fifo.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), + os.path.join(eth_rtl_dir, "lfsr.v"), + os.path.join(eth_rtl_dir, "eth_axis_rx.v"), + os.path.join(eth_rtl_dir, "eth_axis_tx.v"), + os.path.join(eth_rtl_dir, "udp_complete_64.v"), + os.path.join(eth_rtl_dir, "udp_checksum_gen_64.v"), + os.path.join(eth_rtl_dir, "udp_64.v"), + os.path.join(eth_rtl_dir, "udp_ip_rx_64.v"), + os.path.join(eth_rtl_dir, "udp_ip_tx_64.v"), + os.path.join(eth_rtl_dir, "ip_complete_64.v"), + os.path.join(eth_rtl_dir, "ip_64.v"), + os.path.join(eth_rtl_dir, "ip_eth_rx_64.v"), + os.path.join(eth_rtl_dir, "ip_eth_tx_64.v"), + os.path.join(eth_rtl_dir, "ip_arb_mux.v"), + os.path.join(eth_rtl_dir, "arp.v"), + os.path.join(eth_rtl_dir, "arp_cache.v"), + os.path.join(eth_rtl_dir, "arp_eth_rx.v"), + os.path.join(eth_rtl_dir, "arp_eth_tx.v"), + os.path.join(eth_rtl_dir, "eth_arb_mux.v"), + os.path.join(axis_rtl_dir, "arbiter.v"), + os.path.join(axis_rtl_dir, "priority_encoder.v"), + os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + ] + + parameters = {} + + # parameters['A'] = val + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/fpga/lib/eth/example/AU280/fpga_10g/fpga.xdc b/fpga/lib/eth/example/AU280/fpga_10g/fpga.xdc deleted file mode 100644 index 1fef03977..000000000 --- a/fpga/lib/eth/example/AU280/fpga_10g/fpga.xdc +++ /dev/null @@ -1,214 +0,0 @@ -# XDC constraints for the Xilinx Alveo U280 board -# part: xcu280-fsvh2892-2L-e - -# General configuration -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design] -set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] -set_property CONFIG_MODE SPIx4 [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] -set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] -set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] -set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] - -set_operating_conditions -design_power_budget 160 - -# System clocks -# 100 MHz (DDR4) -#set_property -dict {LOC BJ43 IOSTANDARD LVDS} [get_ports clk_100mhz_0_p] -#set_property -dict {LOC BJ44 IOSTANDARD LVDS} [get_ports clk_100mhz_0_n] -#create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p] - -# 100 MHz (DDR4) -#set_property -dict {LOC BH6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p] -#set_property -dict {LOC BJ6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n] -#create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p] - -# 100 MHz -#set_property -dict {LOC G31 IOSTANDARD LVDS} [get_ports clk_100mhz_2_p] -#set_property -dict {LOC F31 IOSTANDARD LVDS} [get_ports clk_100mhz_2_n] -#create_clock -period 10 -name clk_100mhz_2 [get_ports clk_100mhz_2_p] - -# SI570 user clock -#set_property -dict {LOC G30 IOSTANDARD LVDS} [get_ports clk_si570_p] -#set_property -dict {LOC F30 IOSTANDARD LVDS} [get_ports clk_si570_n] -#create_clock -period 6.4 -name clk_si570 [get_ports clk_si570_p] - -# Reset button -set_property -dict {LOC L30 IOSTANDARD LVCMOS18} [get_ports reset] - -set_false_path -from [get_ports {reset}] -set_input_delay 0 [get_ports {reset}] - -# UART -#set_property -dict {LOC A28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports usb_uart_txd] -#set_property -dict {LOC B33 IOSTANDARD LVCMOS18} [get_ports usb_uart_rxd] - -#set_false_path -to [get_ports {uart_txd}] -#set_output_delay 0 [get_ports {uart_txd}] -#set_false_path -from [get_ports {uart_rxd}] -#set_input_delay 0 [get_ports {uart_rxd}] - -# HBM overtemp -set_property -dict {LOC D32 IOSTANDARD LVCMOS18} [get_ports hbm_cattrip] - -set_false_path -to [get_ports {hbm_cattrip}] -set_output_delay 0 [get_ports {hbm_cattrip}] - -# QSFP28 Interfaces -set_property -dict {LOC L53 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC L54 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC L48 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC L49 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC K51 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC K52 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC L44 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC L45 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC J53 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC J54 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC K46 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC K47 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC H51 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC H52 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC J48 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC J49 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 -#set_property -dict {LOC T42 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_134 from SI570 -#set_property -dict {LOC T43 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_134 from SI570 -set_property -dict {LOC R40 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_134 from SI546 -set_property -dict {LOC R41 } [get_ports qsfp0_mgt_refclk_1_n] ;# MGTREFCLK1N_134 from SI546 -set_property -dict {LOC H32 IOSTANDARD LVCMOS18} [get_ports qsfp0_refclk_oe_b] -set_property -dict {LOC G32 IOSTANDARD LVCMOS18} [get_ports qsfp0_refclk_fs] - -# 156.25 MHz MGT reference clock (from SI570) -#create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports qsfp0_mgt_refclk_0_p] - -# 156.25 MHz MGT reference clock (from SI546, fs = 0) -#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] - -# 161.1328125 MHz MGT reference clock (from SI546, fs = 1) -create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] - -set_false_path -to [get_ports {qsfp0_refclk_oe_b qsfp0_refclk_fs}] -set_output_delay 0 [get_ports {qsfp0_refclk_oe_b qsfp0_refclk_fs}] - -set_property -dict {LOC G53 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC G54 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC G48 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC G49 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC F51 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC F52 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC E48 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC E49 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC E53 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC E54 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC C48 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC C49 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC D51 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC D52 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC A49 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC A50 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 -#set_property -dict {LOC P42 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_135 from SI570 -#set_property -dict {LOC P43 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_135 from SI570 -set_property -dict {LOC M42 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_135 from SI546 -set_property -dict {LOC M43 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_135 from SI546 -set_property -dict {LOC H30 IOSTANDARD LVCMOS18} [get_ports qsfp1_refclk_oe_b] -set_property -dict {LOC G33 IOSTANDARD LVCMOS18} [get_ports qsfp1_refclk_fs] - -# 156.25 MHz MGT reference clock (from SI570) -#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p] - -# 156.25 MHz MGT reference clock (from SI546, fs = 0) -#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] - -# 161.1328125 MHz MGT reference clock (from SI546, fs = 1) -create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] - -set_false_path -to [get_ports {qsfp1_refclk_oe_b qsfp1_refclk_fs}] -set_output_delay 0 [get_ports {qsfp1_refclk_oe_b qsfp1_refclk_fs}] - -# PCIe Interface -#set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC AL11} [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC AL10} [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC AM4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC AM3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC AM9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC AM8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC AN6 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC AN5 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC AN11} [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC AN10} [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC AP9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC AP8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3 -#set_property -dict {LOC AP4 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AP3 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AR11} [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AR10} [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AR7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AR6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AT4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AT3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AT9 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AT8 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AU2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AU1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AU11} [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AU10} [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AV4 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AV3 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AU7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AU6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AW6 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AW5 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AV9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AV8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AW2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AW1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AW11} [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AW10} [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AY4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AY3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AY9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AY8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC BA6 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC BA5 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC BA11} [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC BA10} [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC BB9 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC BB8 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC BB4 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC BB3 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC BC11} [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC BC10} [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC BC7 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC BC6 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AL15} [get_ports pcie_refclk_0_p] ;# MGTREFCLK0P_227 (for x8 bifurcated lanes 0-7) -#set_property -dict {LOC AL14} [get_ports pcie_refclk_0_n] ;# MGTREFCLK0N_227 (for x8 bifurcated lanes 0-7) -#set_property -dict {LOC AK13} [get_ports pcie_refclk_2_p] ;# MGTREFCLK1P_227 (for async x8 bifurcated lanes 0-7) -#set_property -dict {LOC AK12} [get_ports pcie_refclk_2_n] ;# MGTREFCLK1N_227 (for async x8 bifurcated lanes 0-7) -#set_property -dict {LOC AR15} [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_225 (for x16 or x8 bifurcated lanes 8-16) -#set_property -dict {LOC AR14} [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_225 (for x16 or x8 bifurcated lanes 8-16) -#set_property -dict {LOC AP13} [get_ports pcie_refclk_3_p] ;# MGTREFCLK1P_225 (for async x16 or x8 bifurcated lanes 8-16) -#set_property -dict {LOC AP12} [get_ports pcie_refclk_3_n] ;# MGTREFCLK1N_225 (for async x16 or x8 bifurcated lanes 8-16) -#set_property -dict {LOC BH26 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n] - -# 100 MHz MGT reference clock -#create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p] -#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p] -#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports pcie_refclk_2_p] -#create_clock -period 10 -name pcie_mgt_refclk_3 [get_ports pcie_refclk_3_p] - -#set_false_path -from [get_ports {pcie_reset_n}] -#set_input_delay 0 [get_ports {pcie_reset_n}] diff --git a/fpga/lib/eth/example/AU250/fpga_10g/Makefile b/fpga/lib/eth/example/AU280/fpga_25g/Makefile similarity index 100% rename from fpga/lib/eth/example/AU250/fpga_10g/Makefile rename to fpga/lib/eth/example/AU280/fpga_25g/Makefile diff --git a/fpga/lib/eth/example/AU280/fpga_10g/README.md b/fpga/lib/eth/example/AU280/fpga_25g/README.md similarity index 100% rename from fpga/lib/eth/example/AU280/fpga_10g/README.md rename to fpga/lib/eth/example/AU280/fpga_25g/README.md diff --git a/fpga/lib/eth/example/AU250/fpga_10g/common/vivado.mk b/fpga/lib/eth/example/AU280/fpga_25g/common/vivado.mk similarity index 76% rename from fpga/lib/eth/example/AU250/fpga_10g/common/vivado.mk rename to fpga/lib/eth/example/AU280/fpga_25g/common/vivado.mk index 21e6a5fed..1402e2382 100644 --- a/fpga/lib/eth/example/AU250/fpga_10g/common/vivado.mk +++ b/fpga/lib/eth/example/AU280/fpga_25g/common/vivado.mk @@ -28,7 +28,7 @@ ################################################################### # phony targets -.PHONY: clean fpga +.PHONY: fpga vivado tmpclean clean distclean # prevent make from deleting intermediate files and reports .PRECIOUS: %.xpr %.bit %.mcs %.prm @@ -40,15 +40,16 @@ CONFIG ?= config.mk FPGA_TOP ?= fpga PROJECT ?= $(FPGA_TOP) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else - XDC_FILES_REL = $(FPGA_TOP).xdc + XDC_FILES_REL = $(PROJECT).xdc endif ################################################################### @@ -60,20 +61,20 @@ endif all: fpga -fpga: $(FPGA_TOP).bit +fpga: $(PROJECT).bit -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr -tmpclean: +tmpclean:: -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt -distclean: clean +distclean:: clean -rm -rf rev ################################################################### @@ -91,12 +92,17 @@ create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done -$(PROJECT).xpr: create_project.tcl +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) # synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr echo "open_project $(PROJECT).xpr" > run_synth.tcl echo "reset_run synth_1" >> run_synth.tcl echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl diff --git a/fpga/lib/eth/example/AU280/fpga_25g/fpga.xdc b/fpga/lib/eth/example/AU280/fpga_25g/fpga.xdc new file mode 100644 index 000000000..ff6be120e --- /dev/null +++ b/fpga/lib/eth/example/AU280/fpga_25g/fpga.xdc @@ -0,0 +1,495 @@ +# XDC constraints for the Xilinx Alveo U280 board +# part: xcu280-fsvh2892-2L-e + +# General configuration +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] + +set_operating_conditions -design_power_budget 160 + +# System clocks +# 100 MHz (DDR4) +#set_property -dict {LOC BJ43 IOSTANDARD LVDS} [get_ports clk_100mhz_0_p] +#set_property -dict {LOC BJ44 IOSTANDARD LVDS} [get_ports clk_100mhz_0_n] +#create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p] + +# 100 MHz (DDR4) +#set_property -dict {LOC BH6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p] +#set_property -dict {LOC BJ6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n] +#create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p] + +# 100 MHz +#set_property -dict {LOC G31 IOSTANDARD LVDS} [get_ports clk_100mhz_2_p] +#set_property -dict {LOC F31 IOSTANDARD LVDS} [get_ports clk_100mhz_2_n] +#create_clock -period 10 -name clk_100mhz_2 [get_ports clk_100mhz_2_p] + +# SI570 user clock +#set_property -dict {LOC G30 IOSTANDARD LVDS} [get_ports clk_si570_p] +#set_property -dict {LOC F30 IOSTANDARD LVDS} [get_ports clk_si570_n] +#create_clock -period 6.4 -name clk_si570 [get_ports clk_si570_p] + +# Reset button +set_property -dict {LOC L30 IOSTANDARD LVCMOS18} [get_ports reset] + +set_false_path -from [get_ports {reset}] +set_input_delay 0 [get_ports {reset}] + +# UART +#set_property -dict {LOC A28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports usb_uart_txd] +#set_property -dict {LOC B33 IOSTANDARD LVCMOS18} [get_ports usb_uart_rxd] + +#set_false_path -to [get_ports {uart_txd}] +#set_output_delay 0 [get_ports {uart_txd}] +#set_false_path -from [get_ports {uart_rxd}] +#set_input_delay 0 [get_ports {uart_rxd}] + +# HBM overtemp +set_property -dict {LOC D32 IOSTANDARD LVCMOS18} [get_ports hbm_cattrip] + +set_false_path -to [get_ports {hbm_cattrip}] +set_output_delay 0 [get_ports {hbm_cattrip}] + +# QSFP28 Interfaces +set_property -dict {LOC L53 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC L54 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC L48 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC L49 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC K51 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC K52 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC L44 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC L45 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC J53 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC J54 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC K46 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC K47 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC H51 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC H52 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC J48 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC J49 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 +#set_property -dict {LOC T42 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_134 from SI570 +#set_property -dict {LOC T43 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_134 from SI570 +set_property -dict {LOC R40 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_134 from SI546 +set_property -dict {LOC R41 } [get_ports qsfp0_mgt_refclk_1_n] ;# MGTREFCLK1N_134 from SI546 +set_property -dict {LOC H32 IOSTANDARD LVCMOS18} [get_ports qsfp0_refclk_oe_b] +set_property -dict {LOC G32 IOSTANDARD LVCMOS18} [get_ports qsfp0_refclk_fs] + +# 156.25 MHz MGT reference clock (from SI570) +#create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports qsfp0_mgt_refclk_0_p] + +# 156.25 MHz MGT reference clock (from SI546, fs = 0) +#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] + +# 161.1328125 MHz MGT reference clock (from SI546, fs = 1) +create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] + +set_false_path -to [get_ports {qsfp0_refclk_oe_b qsfp0_refclk_fs}] +set_output_delay 0 [get_ports {qsfp0_refclk_oe_b qsfp0_refclk_fs}] + +set_property -dict {LOC G53 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC G54 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC G48 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC G49 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC F51 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC F52 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC E48 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC E49 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC E53 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC E54 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC C48 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC C49 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC D51 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC D52 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC A49 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC A50 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 +#set_property -dict {LOC P42 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_135 from SI570 +#set_property -dict {LOC P43 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_135 from SI570 +set_property -dict {LOC M42 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_135 from SI546 +set_property -dict {LOC M43 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_135 from SI546 +set_property -dict {LOC H30 IOSTANDARD LVCMOS18} [get_ports qsfp1_refclk_oe_b] +set_property -dict {LOC G33 IOSTANDARD LVCMOS18} [get_ports qsfp1_refclk_fs] + +# 156.25 MHz MGT reference clock (from SI570) +#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p] + +# 156.25 MHz MGT reference clock (from SI546, fs = 0) +#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] + +# 161.1328125 MHz MGT reference clock (from SI546, fs = 1) +create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] + +set_false_path -to [get_ports {qsfp1_refclk_oe_b qsfp1_refclk_fs}] +set_output_delay 0 [get_ports {qsfp1_refclk_oe_b qsfp1_refclk_fs}] + +# PCIe Interface +#set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AL11} [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AL10} [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AM4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AM3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AM9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AM8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AN6 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AN5 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AN11} [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AN10} [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AP9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AP8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3 +#set_property -dict {LOC AP4 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AP3 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AR11} [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AR10} [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AR7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AR6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AT4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AT3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AT9 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AT8 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AU2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AU1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AU11} [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AU10} [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2 +#set_property -dict {LOC AV4 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AV3 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AU7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AU6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AW6 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AW5 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AV9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AV8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AW2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AW1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AW11} [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AW10} [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AY4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AY3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AY9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC AY8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 +#set_property -dict {LOC BA6 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BA5 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BA11} [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BA10} [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BB9 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BB8 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BB4 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BB3 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BC11} [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BC10} [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BC7 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC BC6 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 +#set_property -dict {LOC AL15} [get_ports pcie_refclk_0_p] ;# MGTREFCLK0P_227 (for x8 bifurcated lanes 0-7) +#set_property -dict {LOC AL14} [get_ports pcie_refclk_0_n] ;# MGTREFCLK0N_227 (for x8 bifurcated lanes 0-7) +#set_property -dict {LOC AK13} [get_ports pcie_refclk_2_p] ;# MGTREFCLK1P_227 (for async x8 bifurcated lanes 0-7) +#set_property -dict {LOC AK12} [get_ports pcie_refclk_2_n] ;# MGTREFCLK1N_227 (for async x8 bifurcated lanes 0-7) +#set_property -dict {LOC AR15} [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_225 (for x16 or x8 bifurcated lanes 8-16) +#set_property -dict {LOC AR14} [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_225 (for x16 or x8 bifurcated lanes 8-16) +#set_property -dict {LOC AP13} [get_ports pcie_refclk_3_p] ;# MGTREFCLK1P_225 (for async x16 or x8 bifurcated lanes 8-16) +#set_property -dict {LOC AP12} [get_ports pcie_refclk_3_n] ;# MGTREFCLK1N_225 (for async x16 or x8 bifurcated lanes 8-16) +#set_property -dict {LOC BH26 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n] + +# 100 MHz MGT reference clock +#create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p] +#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p] +#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports pcie_refclk_2_p] +#create_clock -period 10 -name pcie_mgt_refclk_3 [get_ports pcie_refclk_3_p] + +#set_false_path -from [get_ports {pcie_reset_n}] +#set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 C0 +#set_property -dict {LOC BF46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +#set_property -dict {LOC BG43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +#set_property -dict {LOC BK45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +#set_property -dict {LOC BF42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +#set_property -dict {LOC BL45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +#set_property -dict {LOC BF43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +#set_property -dict {LOC BG42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +#set_property -dict {LOC BL43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +#set_property -dict {LOC BK43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +#set_property -dict {LOC BM42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +#set_property -dict {LOC BG45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +#set_property -dict {LOC BD41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +#set_property -dict {LOC BL42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +#set_property -dict {LOC BE44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +#set_property -dict {LOC BE43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +#set_property -dict {LOC BL46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +#set_property -dict {LOC BH44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +#set_property -dict {LOC BH45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +#set_property -dict {LOC BM47 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +#set_property -dict {LOC BF41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +#set_property -dict {LOC BE41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +#set_property -dict {LOC BH46 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_t}] +#set_property -dict {LOC BJ46 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_c}] +#set_property -dict {LOC BH42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke}] +#set_property -dict {LOC BK46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n}] +#set_property -dict {LOC BH41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +#set_property -dict {LOC BG44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt}] +#set_property -dict {LOC BF45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +#set_property -dict {LOC BG33 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c0_reset_n}] + +#set_property -dict {LOC BN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +#set_property -dict {LOC BP32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +#set_property -dict {LOC BL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +#set_property -dict {LOC BM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +#set_property -dict {LOC BP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +#set_property -dict {LOC BP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +#set_property -dict {LOC BP31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +#set_property -dict {LOC BN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +#set_property -dict {LOC BJ31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +#set_property -dict {LOC BH31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +#set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +#set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +#set_property -dict {LOC BH29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +#set_property -dict {LOC BH30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +#set_property -dict {LOC BF31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +#set_property -dict {LOC BG32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +#set_property -dict {LOC BK31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +#set_property -dict {LOC BL31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +#set_property -dict {LOC BK33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +#set_property -dict {LOC BL33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +#set_property -dict {LOC BL32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +#set_property -dict {LOC BM33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +#set_property -dict {LOC BN34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +#set_property -dict {LOC BP34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +#set_property -dict {LOC BH34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +#set_property -dict {LOC BH35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +#set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +#set_property -dict {LOC BF36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +#set_property -dict {LOC BJ33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +#set_property -dict {LOC BJ34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +#set_property -dict {LOC BG34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +#set_property -dict {LOC BG35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +#set_property -dict {LOC BM52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +#set_property -dict {LOC BL53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +#set_property -dict {LOC BL52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +#set_property -dict {LOC BL51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +#set_property -dict {LOC BN50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +#set_property -dict {LOC BN51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +#set_property -dict {LOC BN49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +#set_property -dict {LOC BM48 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +#set_property -dict {LOC BE50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +#set_property -dict {LOC BE49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +#set_property -dict {LOC BE51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +#set_property -dict {LOC BD51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +#set_property -dict {LOC BF52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +#set_property -dict {LOC BF51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +#set_property -dict {LOC BG50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +#set_property -dict {LOC BF50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +#set_property -dict {LOC BH50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +#set_property -dict {LOC BJ51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +#set_property -dict {LOC BH51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +#set_property -dict {LOC BH49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +#set_property -dict {LOC BK50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +#set_property -dict {LOC BK51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +#set_property -dict {LOC BJ49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +#set_property -dict {LOC BJ48 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +#set_property -dict {LOC BN44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +#set_property -dict {LOC BN45 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +#set_property -dict {LOC BM44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +#set_property -dict {LOC BM45 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +#set_property -dict {LOC BP43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +#set_property -dict {LOC BP44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +#set_property -dict {LOC BN47 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +#set_property -dict {LOC BP47 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +#set_property -dict {LOC BG54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +#set_property -dict {LOC BG53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +#set_property -dict {LOC BE53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +#set_property -dict {LOC BE54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +#set_property -dict {LOC BH52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +#set_property -dict {LOC BG52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +#set_property -dict {LOC BK54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +#set_property -dict {LOC BK53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +#set_property -dict {LOC BN29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +#set_property -dict {LOC BN30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +#set_property -dict {LOC BM28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +#set_property -dict {LOC BM29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +#set_property -dict {LOC BJ29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +#set_property -dict {LOC BK30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +#set_property -dict {LOC BG29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +#set_property -dict {LOC BG30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +#set_property -dict {LOC BL35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +#set_property -dict {LOC BM35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +#set_property -dict {LOC BM34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +#set_property -dict {LOC BN35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +#set_property -dict {LOC BK34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +#set_property -dict {LOC BK35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +#set_property -dict {LOC BH32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +#set_property -dict {LOC BJ32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +#set_property -dict {LOC BM49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +#set_property -dict {LOC BM50 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +#set_property -dict {LOC BP48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}] +#set_property -dict {LOC BP49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}] +#set_property -dict {LOC BF47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}] +#set_property -dict {LOC BF48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}] +#set_property -dict {LOC BG48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}] +#set_property -dict {LOC BG49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}] +#set_property -dict {LOC BH47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}] +#set_property -dict {LOC BJ47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}] +#set_property -dict {LOC BK48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}] +#set_property -dict {LOC BK49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}] +#set_property -dict {LOC BN46 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}] +#set_property -dict {LOC BP46 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}] +#set_property -dict {LOC BN42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}] +#set_property -dict {LOC BP42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}] +#set_property -dict {LOC BH54 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}] +#set_property -dict {LOC BJ54 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}] +#set_property -dict {LOC BJ52 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}] +#set_property -dict {LOC BJ53 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}] + +# DDR4 C1 +#set_property -dict {LOC BF7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +#set_property -dict {LOC BK1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +#set_property -dict {LOC BF6 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +#set_property -dict {LOC BF5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +#set_property -dict {LOC BE3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +#set_property -dict {LOC BE6 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +#set_property -dict {LOC BE5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +#set_property -dict {LOC BG7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +#set_property -dict {LOC BJ1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +#set_property -dict {LOC BG2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +#set_property -dict {LOC BJ8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +#set_property -dict {LOC BE4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +#set_property -dict {LOC BL2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +#set_property -dict {LOC BK5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +#set_property -dict {LOC BK8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +#set_property -dict {LOC BJ4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +#set_property -dict {LOC BF8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +#set_property -dict {LOC BG8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +#set_property -dict {LOC BK4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +#set_property -dict {LOC BF3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +#set_property -dict {LOC BF2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +#set_property -dict {LOC BJ3 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_t}] +#set_property -dict {LOC BJ2 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_c}] +#set_property -dict {LOC BE1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}] +#set_property -dict {LOC BL3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}] +#set_property -dict {LOC BG3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +#set_property -dict {LOC BH2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}] +#set_property -dict {LOC BH1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +#set_property -dict {LOC BH12 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c1_reset_n}] + +#set_property -dict {LOC A11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +#set_property -dict {LOC A10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +#set_property -dict {LOC A9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +#set_property -dict {LOC A8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +#set_property -dict {LOC B12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +#set_property -dict {LOC B10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +#set_property -dict {LOC C12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +#set_property -dict {LOC B11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +#set_property -dict {LOC E11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +#set_property -dict {LOC D11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +#set_property -dict {LOC E12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +#set_property -dict {LOC F11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +#set_property -dict {LOC F10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +#set_property -dict {LOC E9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +#set_property -dict {LOC F9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +#set_property -dict {LOC G11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +#set_property -dict {LOC H12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +#set_property -dict {LOC G13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +#set_property -dict {LOC H13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +#set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +#set_property -dict {LOC J11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +#set_property -dict {LOC J12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +#set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +#set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +#set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +#set_property -dict {LOC C15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +#set_property -dict {LOC A15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +#set_property -dict {LOC B15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +#set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +#set_property -dict {LOC E14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +#set_property -dict {LOC F14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +#set_property -dict {LOC F13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +#set_property -dict {LOC BM3 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +#set_property -dict {LOC BM4 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +#set_property -dict {LOC BM5 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +#set_property -dict {LOC BL6 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +#set_property -dict {LOC BN4 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +#set_property -dict {LOC BN5 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +#set_property -dict {LOC BN6 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +#set_property -dict {LOC BN7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +#set_property -dict {LOC BJ9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +#set_property -dict {LOC BK9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +#set_property -dict {LOC BK10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +#set_property -dict {LOC BL10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +#set_property -dict {LOC BM9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +#set_property -dict {LOC BN9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +#set_property -dict {LOC BN10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +#set_property -dict {LOC BM10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +#set_property -dict {LOC BM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +#set_property -dict {LOC BM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +#set_property -dict {LOC BL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +#set_property -dict {LOC BM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +#set_property -dict {LOC BN12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +#set_property -dict {LOC BM12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +#set_property -dict {LOC BP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +#set_property -dict {LOC BP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +#set_property -dict {LOC BJ13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +#set_property -dict {LOC BJ12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +#set_property -dict {LOC BH15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +#set_property -dict {LOC BH14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +#set_property -dict {LOC BK14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +#set_property -dict {LOC BK15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +#set_property -dict {LOC BL12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +#set_property -dict {LOC BL13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +#set_property -dict {LOC BE9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +#set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +#set_property -dict {LOC BF10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +#set_property -dict {LOC BE11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +#set_property -dict {LOC BG13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +#set_property -dict {LOC BG12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +#set_property -dict {LOC BG9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +#set_property -dict {LOC BG10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +#set_property -dict {LOC B13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +#set_property -dict {LOC A13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +#set_property -dict {LOC C10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +#set_property -dict {LOC C9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +#set_property -dict {LOC D10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +#set_property -dict {LOC D9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +#set_property -dict {LOC H10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +#set_property -dict {LOC G10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +#set_property -dict {LOC H15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +#set_property -dict {LOC G15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +#set_property -dict {LOC K14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +#set_property -dict {LOC K13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +#set_property -dict {LOC D15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +#set_property -dict {LOC D14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +#set_property -dict {LOC E13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +#set_property -dict {LOC D12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +#set_property -dict {LOC BL7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +#set_property -dict {LOC BM7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +#set_property -dict {LOC BP7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] +#set_property -dict {LOC BP6 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] +#set_property -dict {LOC BL8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}] +#set_property -dict {LOC BM8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}] +#set_property -dict {LOC BP9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}] +#set_property -dict {LOC BP8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}] +#set_property -dict {LOC BN15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}] +#set_property -dict {LOC BN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}] +#set_property -dict {LOC BP12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}] +#set_property -dict {LOC BP11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}] +#set_property -dict {LOC BJ14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}] +#set_property -dict {LOC BK13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}] +#set_property -dict {LOC BJ11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}] +#set_property -dict {LOC BK11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}] +#set_property -dict {LOC BF12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}] +#set_property -dict {LOC BF11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}] +#set_property -dict {LOC BH10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}] +#set_property -dict {LOC BH9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}] diff --git a/fpga/lib/eth/example/AU280/fpga_10g/fpga/Makefile b/fpga/lib/eth/example/AU280/fpga_25g/fpga/Makefile similarity index 99% rename from fpga/lib/eth/example/AU280/fpga_10g/fpga/Makefile rename to fpga/lib/eth/example/AU280/fpga_25g/fpga/Makefile index cf7334d43..158a27cd0 100644 --- a/fpga/lib/eth/example/AU280/fpga_10g/fpga/Makefile +++ b/fpga/lib/eth/example/AU280/fpga_25g/fpga/Makefile @@ -58,6 +58,9 @@ XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES += ip/eth_xcvr_gt.tcl +# Configuration +CONFIG_TCL_FILES = ./config.tcl + include ../common/vivado.mk program: $(FPGA_TOP).bit diff --git a/fpga/lib/eth/example/AU280/fpga_25g/fpga/config.tcl b/fpga/lib/eth/example/AU280/fpga_25g/fpga/config.tcl new file mode 100644 index 000000000..756e2b3a1 --- /dev/null +++ b/fpga/lib/eth/example/AU280/fpga_25g/fpga/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/AU280/fpga_25g/fpga_10g/Makefile b/fpga/lib/eth/example/AU280/fpga_25g/fpga_10g/Makefile new file mode 100644 index 000000000..158a27cd0 --- /dev/null +++ b/fpga/lib/eth/example/AU280/fpga_25g/fpga_10g/Makefile @@ -0,0 +1,113 @@ + +# FPGA settings +FPGA_PART = xcu280-fsvh2892-2L-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete_64.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v +SYN_FILES += lib/eth/rtl/udp_64.v +SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v +SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v +SYN_FILES += lib/eth/rtl/ip_complete_64.v +SYN_FILES += lib/eth/rtl/ip_64.v +SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v +SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl + +# IP +IP_TCL_FILES += ip/eth_xcvr_gt.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%.mcs %.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + diff --git a/fpga/lib/eth/example/AU280/fpga_25g/fpga_10g/config.tcl b/fpga/lib/eth/example/AU280/fpga_25g/fpga_10g/config.tcl new file mode 100644 index 000000000..90aa4caeb --- /dev/null +++ b/fpga/lib/eth/example/AU280/fpga_25g/fpga_10g/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/AU250/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/lib/eth/example/AU280/fpga_25g/ip/eth_xcvr_gt.tcl similarity index 100% rename from fpga/lib/eth/example/AU250/fpga_10g/ip/eth_xcvr_gt.tcl rename to fpga/lib/eth/example/AU280/fpga_25g/ip/eth_xcvr_gt.tcl diff --git a/fpga/lib/eth/example/AU250/fpga_10g/lib/eth b/fpga/lib/eth/example/AU280/fpga_25g/lib/eth similarity index 100% rename from fpga/lib/eth/example/AU250/fpga_10g/lib/eth rename to fpga/lib/eth/example/AU280/fpga_25g/lib/eth diff --git a/fpga/lib/eth/example/AU250/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/fpga/lib/eth/example/AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v similarity index 100% rename from fpga/lib/eth/example/AU250/fpga_10g/rtl/eth_xcvr_phy_wrapper.v rename to fpga/lib/eth/example/AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v diff --git a/fpga/lib/eth/example/AU280/fpga_10g/rtl/fpga.v b/fpga/lib/eth/example/AU280/fpga_25g/rtl/fpga.v similarity index 100% rename from fpga/lib/eth/example/AU280/fpga_10g/rtl/fpga.v rename to fpga/lib/eth/example/AU280/fpga_25g/rtl/fpga.v diff --git a/fpga/lib/eth/example/AU280/fpga_10g/rtl/fpga_core.v b/fpga/lib/eth/example/AU280/fpga_25g/rtl/fpga_core.v similarity index 100% rename from fpga/lib/eth/example/AU280/fpga_10g/rtl/fpga_core.v rename to fpga/lib/eth/example/AU280/fpga_25g/rtl/fpga_core.v diff --git a/fpga/lib/eth/example/AU250/fpga_10g/rtl/sync_signal.v b/fpga/lib/eth/example/AU280/fpga_25g/rtl/sync_signal.v similarity index 100% rename from fpga/lib/eth/example/AU250/fpga_10g/rtl/sync_signal.v rename to fpga/lib/eth/example/AU280/fpga_25g/rtl/sync_signal.v diff --git a/fpga/lib/eth/example/AU250/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/AU280/fpga_25g/tb/fpga_core/Makefile similarity index 100% rename from fpga/lib/eth/example/AU250/fpga_10g/tb/fpga_core/Makefile rename to fpga/lib/eth/example/AU280/fpga_25g/tb/fpga_core/Makefile diff --git a/fpga/lib/eth/example/AU280/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py similarity index 52% rename from fpga/lib/eth/example/AU280/fpga_10g/tb/fpga_core/test_fpga_core.py rename to fpga/lib/eth/example/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py index 3884d768e..ef36bbec9 100644 --- a/fpga/lib/eth/example/AU280/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -45,110 +45,50 @@ class TB: self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) - cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) + cocotb.start_soon(Clock(dut.clk, 2.56, units="ns").start()) # Ethernet - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_1, 6.4, units="ns").start()) - self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1, dut.qsfp0_rx_clk_1, dut.qsfp0_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_1, 6.4, units="ns").start()) - self.qsfp0_1_sink = XgmiiSink(dut.qsfp0_txd_1, dut.qsfp0_txc_1, dut.qsfp0_tx_clk_1, dut.qsfp0_tx_rst_1) + self.qsfp_source = [] + self.qsfp_sink = [] - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_2, 6.4, units="ns").start()) - self.qsfp0_2_source = XgmiiSource(dut.qsfp0_rxd_2, dut.qsfp0_rxc_2, dut.qsfp0_rx_clk_2, dut.qsfp0_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_2, 6.4, units="ns").start()) - self.qsfp0_2_sink = XgmiiSink(dut.qsfp0_txd_2, dut.qsfp0_txc_2, dut.qsfp0_tx_clk_2, dut.qsfp0_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_3, 6.4, units="ns").start()) - self.qsfp0_3_source = XgmiiSource(dut.qsfp0_rxd_3, dut.qsfp0_rxc_3, dut.qsfp0_rx_clk_3, dut.qsfp0_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_3, 6.4, units="ns").start()) - self.qsfp0_3_sink = XgmiiSink(dut.qsfp0_txd_3, dut.qsfp0_txc_3, dut.qsfp0_tx_clk_3, dut.qsfp0_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_4, 6.4, units="ns").start()) - self.qsfp0_4_source = XgmiiSource(dut.qsfp0_rxd_4, dut.qsfp0_rxc_4, dut.qsfp0_rx_clk_4, dut.qsfp0_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_4, 6.4, units="ns").start()) - self.qsfp0_4_sink = XgmiiSink(dut.qsfp0_txd_4, dut.qsfp0_txc_4, dut.qsfp0_tx_clk_4, dut.qsfp0_tx_rst_4) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_1, 6.4, units="ns").start()) - self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_1, 6.4, units="ns").start()) - self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_2, 6.4, units="ns").start()) - self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_2, 6.4, units="ns").start()) - self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_3, 6.4, units="ns").start()) - self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_3, 6.4, units="ns").start()) - self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_4, 6.4, units="ns").start()) - self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 6.4, units="ns").start()) - self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4) + for x in range(2): + sources = [] + sinks = [] + for y in range(1, 5): + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_rx_clk_{y}"), 2.56, units="ns").start()) + source = XgmiiSource(getattr(dut, f"qsfp{x}_rxd_{y}"), getattr(dut, f"qsfp{x}_rxc_{y}"), getattr(dut, f"qsfp{x}_rx_clk_{y}"), getattr(dut, f"qsfp{x}_rx_rst_{y}")) + sources.append(source) + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_tx_clk_{y}"), 2.56, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"qsfp{x}_txd_{y}"), getattr(dut, f"qsfp{x}_txc_{y}"), getattr(dut, f"qsfp{x}_tx_clk_{y}"), getattr(dut, f"qsfp{x}_tx_rst_{y}")) + sinks.append(sink) + self.qsfp_source.append(sources) + self.qsfp_sink.append(sinks) async def init(self): self.dut.rst.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_4.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) + for x in range(2): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(0) + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(0) for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 1 - self.dut.qsfp0_rx_rst_1.value = 1 - self.dut.qsfp0_tx_rst_1.value = 1 - self.dut.qsfp0_rx_rst_2.value = 1 - self.dut.qsfp0_tx_rst_2.value = 1 - self.dut.qsfp0_rx_rst_3.value = 1 - self.dut.qsfp0_tx_rst_3.value = 1 - self.dut.qsfp0_rx_rst_4.value = 1 - self.dut.qsfp0_tx_rst_4.value = 1 - self.dut.qsfp1_rx_rst_1.value = 1 - self.dut.qsfp1_tx_rst_1.value = 1 - self.dut.qsfp1_rx_rst_2.value = 1 - self.dut.qsfp1_tx_rst_2.value = 1 - self.dut.qsfp1_rx_rst_3.value = 1 - self.dut.qsfp1_tx_rst_3.value = 1 - self.dut.qsfp1_rx_rst_4.value = 1 - self.dut.qsfp1_tx_rst_4.value = 1 + for x in range(2): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").value = 1 + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").value = 1 for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 0 - self.dut.qsfp0_rx_rst_1.value = 0 - self.dut.qsfp0_tx_rst_1.value = 0 - self.dut.qsfp0_rx_rst_2.value = 0 - self.dut.qsfp0_tx_rst_2.value = 0 - self.dut.qsfp0_rx_rst_3.value = 0 - self.dut.qsfp0_tx_rst_3.value = 0 - self.dut.qsfp0_rx_rst_4.value = 0 - self.dut.qsfp0_tx_rst_4.value = 0 - self.dut.qsfp1_rx_rst_1.value = 0 - self.dut.qsfp1_tx_rst_1.value = 0 - self.dut.qsfp1_rx_rst_2.value = 0 - self.dut.qsfp1_tx_rst_2.value = 0 - self.dut.qsfp1_rx_rst_3.value = 0 - self.dut.qsfp1_tx_rst_3.value = 0 - self.dut.qsfp1_rx_rst_4.value = 0 - self.dut.qsfp1_tx_rst_4.value = 0 + for x in range(2): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").value = 0 + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").value = 0 @cocotb.test() @@ -168,11 +108,11 @@ async def run_test(dut): test_frame = XgmiiFrame.from_payload(test_pkt.build()) - await tb.qsfp0_1_source.send(test_frame) + await tb.qsfp_source[0][0].send(test_frame) tb.log.info("receive ARP request") - rx_frame = await tb.qsfp0_1_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -200,11 +140,11 @@ async def run_test(dut): resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - await tb.qsfp0_1_source.send(resp_frame) + await tb.qsfp_source[0][0].send(resp_frame) tb.log.info("receive UDP packet") - rx_frame = await tb.qsfp0_1_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) diff --git a/fpga/lib/eth/example/AU50/fpga_10g/common/vivado.mk b/fpga/lib/eth/example/AU50/fpga_10g/common/vivado.mk deleted file mode 100644 index 21e6a5fed..000000000 --- a/fpga/lib/eth/example/AU50/fpga_10g/common/vivado.mk +++ /dev/null @@ -1,131 +0,0 @@ -################################################################### -# -# Xilinx Vivado FPGA Makefile -# -# Copyright (c) 2016 Alex Forencich -# -################################################################### -# -# Parameters: -# FPGA_TOP - Top module name -# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) -# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) -# SYN_FILES - space-separated list of source files -# INC_FILES - space-separated list of include files -# XDC_FILES - space-separated list of timing constraint files -# XCI_FILES - space-separated list of IP XCI files -# -# Example: -# -# FPGA_TOP = fpga -# FPGA_FAMILY = VirtexUltrascale -# FPGA_DEVICE = xcvu095-ffva2104-2-e -# SYN_FILES = rtl/fpga.v -# XDC_FILES = fpga.xdc -# XCI_FILES = ip/pcspma.xci -# include ../common/vivado.mk -# -################################################################### - -# phony targets -.PHONY: clean fpga - -# prevent make from deleting intermediate files and reports -.PRECIOUS: %.xpr %.bit %.mcs %.prm -.SECONDARY: - -CONFIG ?= config.mk --include ../$(CONFIG) - -FPGA_TOP ?= fpga -PROJECT ?= $(FPGA_TOP) - -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) - -ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) -else - XDC_FILES_REL = $(FPGA_TOP).xdc -endif - -################################################################### -# Main Targets -# -# all: build everything -# clean: remove output files and project files -################################################################### - -all: fpga - -fpga: $(FPGA_TOP).bit - -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr - -tmpclean: - -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl - -clean: tmpclean - -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl - -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt - -distclean: clean - -rm -rf rev - -################################################################### -# Target implementations -################################################################### - -# Vivado project file -create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) - rm -rf defines.v - touch defines.v - for x in $(DEFS); do echo '`define' $$x >> defines.v; done - echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ - echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ - echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ - echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ - for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done - for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done - -$(PROJECT).xpr: create_project.tcl - vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) - -# synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) - echo "open_project $(PROJECT).xpr" > run_synth.tcl - echo "reset_run synth_1" >> run_synth.tcl - echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl - echo "wait_on_run synth_1" >> run_synth.tcl - vivado -nojournal -nolog -mode batch -source run_synth.tcl - -# implementation run -$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp - echo "open_project $(PROJECT).xpr" > run_impl.tcl - echo "reset_run impl_1" >> run_impl.tcl - echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl - echo "wait_on_run impl_1" >> run_impl.tcl - echo "open_run impl_1" >> run_impl.tcl - echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl - echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl - vivado -nojournal -nolog -mode batch -source run_impl.tcl - -# bit file -$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp - echo "open_project $(PROJECT).xpr" > generate_bit.tcl - echo "open_run impl_1" >> generate_bit.tcl - echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl - echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl - vivado -nojournal -nolog -mode batch -source generate_bit.tcl - ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi - mkdir -p rev - COUNT=100; \ - while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ - do COUNT=$$((COUNT+1)); done; \ - cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/lib/eth/example/AU280/fpga_10g/Makefile b/fpga/lib/eth/example/AU50/fpga_25g/Makefile similarity index 100% rename from fpga/lib/eth/example/AU280/fpga_10g/Makefile rename to fpga/lib/eth/example/AU50/fpga_25g/Makefile diff --git a/fpga/lib/eth/example/AU50/fpga_10g/README.md b/fpga/lib/eth/example/AU50/fpga_25g/README.md similarity index 100% rename from fpga/lib/eth/example/AU50/fpga_10g/README.md rename to fpga/lib/eth/example/AU50/fpga_25g/README.md diff --git a/fpga/lib/eth/example/AU280/fpga_10g/common/vivado.mk b/fpga/lib/eth/example/AU50/fpga_25g/common/vivado.mk similarity index 76% rename from fpga/lib/eth/example/AU280/fpga_10g/common/vivado.mk rename to fpga/lib/eth/example/AU50/fpga_25g/common/vivado.mk index 21e6a5fed..1402e2382 100644 --- a/fpga/lib/eth/example/AU280/fpga_10g/common/vivado.mk +++ b/fpga/lib/eth/example/AU50/fpga_25g/common/vivado.mk @@ -28,7 +28,7 @@ ################################################################### # phony targets -.PHONY: clean fpga +.PHONY: fpga vivado tmpclean clean distclean # prevent make from deleting intermediate files and reports .PRECIOUS: %.xpr %.bit %.mcs %.prm @@ -40,15 +40,16 @@ CONFIG ?= config.mk FPGA_TOP ?= fpga PROJECT ?= $(FPGA_TOP) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else - XDC_FILES_REL = $(FPGA_TOP).xdc + XDC_FILES_REL = $(PROJECT).xdc endif ################################################################### @@ -60,20 +61,20 @@ endif all: fpga -fpga: $(FPGA_TOP).bit +fpga: $(PROJECT).bit -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr -tmpclean: +tmpclean:: -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt -distclean: clean +distclean:: clean -rm -rf rev ################################################################### @@ -91,12 +92,17 @@ create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done -$(PROJECT).xpr: create_project.tcl +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) # synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr echo "open_project $(PROJECT).xpr" > run_synth.tcl echo "reset_run synth_1" >> run_synth.tcl echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl diff --git a/fpga/lib/eth/example/AU50/fpga_10g/fpga.xdc b/fpga/lib/eth/example/AU50/fpga_25g/fpga.xdc similarity index 99% rename from fpga/lib/eth/example/AU50/fpga_10g/fpga.xdc rename to fpga/lib/eth/example/AU50/fpga_25g/fpga.xdc index e46f255f4..5d3515481 100644 --- a/fpga/lib/eth/example/AU50/fpga_10g/fpga.xdc +++ b/fpga/lib/eth/example/AU50/fpga_25g/fpga.xdc @@ -13,6 +13,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] set_operating_conditions -design_power_budget 63 diff --git a/fpga/lib/eth/example/AU50/fpga_10g/fpga/Makefile b/fpga/lib/eth/example/AU50/fpga_25g/fpga/Makefile similarity index 99% rename from fpga/lib/eth/example/AU50/fpga_10g/fpga/Makefile rename to fpga/lib/eth/example/AU50/fpga_25g/fpga/Makefile index 44a2685d7..0bf97979b 100644 --- a/fpga/lib/eth/example/AU50/fpga_10g/fpga/Makefile +++ b/fpga/lib/eth/example/AU50/fpga_25g/fpga/Makefile @@ -58,6 +58,9 @@ XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES += ip/eth_xcvr_gt.tcl +# Configuration +CONFIG_TCL_FILES = ./config.tcl + include ../common/vivado.mk program: $(FPGA_TOP).bit diff --git a/fpga/lib/eth/example/AU50/fpga_25g/fpga/config.tcl b/fpga/lib/eth/example/AU50/fpga_25g/fpga/config.tcl new file mode 100644 index 000000000..756e2b3a1 --- /dev/null +++ b/fpga/lib/eth/example/AU50/fpga_25g/fpga/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/AU50/fpga_25g/fpga_10g/Makefile b/fpga/lib/eth/example/AU50/fpga_25g/fpga_10g/Makefile new file mode 100644 index 000000000..0bf97979b --- /dev/null +++ b/fpga/lib/eth/example/AU50/fpga_25g/fpga_10g/Makefile @@ -0,0 +1,113 @@ + +# FPGA settings +FPGA_PART = xcu50-fsvh2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete_64.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v +SYN_FILES += lib/eth/rtl/udp_64.v +SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v +SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v +SYN_FILES += lib/eth/rtl/ip_complete_64.v +SYN_FILES += lib/eth/rtl/ip_64.v +SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v +SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl + +# IP +IP_TCL_FILES += ip/eth_xcvr_gt.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%.mcs %.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + diff --git a/fpga/lib/eth/example/AU50/fpga_25g/fpga_10g/config.tcl b/fpga/lib/eth/example/AU50/fpga_25g/fpga_10g/config.tcl new file mode 100644 index 000000000..90aa4caeb --- /dev/null +++ b/fpga/lib/eth/example/AU50/fpga_25g/fpga_10g/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/AU280/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/lib/eth/example/AU50/fpga_25g/ip/eth_xcvr_gt.tcl similarity index 100% rename from fpga/lib/eth/example/AU280/fpga_10g/ip/eth_xcvr_gt.tcl rename to fpga/lib/eth/example/AU50/fpga_25g/ip/eth_xcvr_gt.tcl diff --git a/fpga/lib/eth/example/AU280/fpga_10g/lib/eth b/fpga/lib/eth/example/AU50/fpga_25g/lib/eth similarity index 100% rename from fpga/lib/eth/example/AU280/fpga_10g/lib/eth rename to fpga/lib/eth/example/AU50/fpga_25g/lib/eth diff --git a/fpga/lib/eth/example/AU280/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/fpga/lib/eth/example/AU50/fpga_25g/rtl/eth_xcvr_phy_wrapper.v similarity index 100% rename from fpga/lib/eth/example/AU280/fpga_10g/rtl/eth_xcvr_phy_wrapper.v rename to fpga/lib/eth/example/AU50/fpga_25g/rtl/eth_xcvr_phy_wrapper.v diff --git a/fpga/lib/eth/example/AU50/fpga_10g/rtl/fpga.v b/fpga/lib/eth/example/AU50/fpga_25g/rtl/fpga.v similarity index 100% rename from fpga/lib/eth/example/AU50/fpga_10g/rtl/fpga.v rename to fpga/lib/eth/example/AU50/fpga_25g/rtl/fpga.v diff --git a/fpga/lib/eth/example/AU50/fpga_10g/rtl/fpga_core.v b/fpga/lib/eth/example/AU50/fpga_25g/rtl/fpga_core.v similarity index 100% rename from fpga/lib/eth/example/AU50/fpga_10g/rtl/fpga_core.v rename to fpga/lib/eth/example/AU50/fpga_25g/rtl/fpga_core.v diff --git a/fpga/lib/eth/example/AU280/fpga_10g/rtl/sync_signal.v b/fpga/lib/eth/example/AU50/fpga_25g/rtl/sync_signal.v similarity index 100% rename from fpga/lib/eth/example/AU280/fpga_10g/rtl/sync_signal.v rename to fpga/lib/eth/example/AU50/fpga_25g/rtl/sync_signal.v diff --git a/fpga/lib/eth/example/AU280/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/AU50/fpga_25g/tb/fpga_core/Makefile similarity index 100% rename from fpga/lib/eth/example/AU280/fpga_10g/tb/fpga_core/Makefile rename to fpga/lib/eth/example/AU50/fpga_25g/tb/fpga_core/Makefile diff --git a/fpga/lib/eth/example/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py new file mode 100644 index 000000000..73fa052a2 --- /dev/null +++ b/fpga/lib/eth/example/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -0,0 +1,219 @@ +""" + +Copyright (c) 2020 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +""" + +import logging +import os + +from scapy.layers.l2 import Ether, ARP +from scapy.layers.inet import IP, UDP + +import cocotb_test.simulator + +import cocotb +from cocotb.log import SimLog +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge + +from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = SimLog("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 2.56, units="ns").start()) + + # Ethernet + self.qsfp_source = [] + self.qsfp_sink = [] + + for y in range(1, 5): + cocotb.start_soon(Clock(getattr(dut, f"qsfp_rx_clk_{y}"), 2.56, units="ns").start()) + source = XgmiiSource(getattr(dut, f"qsfp_rxd_{y}"), getattr(dut, f"qsfp_rxc_{y}"), getattr(dut, f"qsfp_rx_clk_{y}"), getattr(dut, f"qsfp_rx_rst_{y}")) + self.qsfp_source.append(source) + cocotb.start_soon(Clock(getattr(dut, f"qsfp_tx_clk_{y}"), 2.56, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"qsfp_txd_{y}"), getattr(dut, f"qsfp_txc_{y}"), getattr(dut, f"qsfp_tx_clk_{y}"), getattr(dut, f"qsfp_tx_rst_{y}")) + self.qsfp_sink.append(sink) + + async def init(self): + + self.dut.rst.setimmediatevalue(0) + for y in range(1, 5): + getattr(self.dut, f"qsfp_rx_rst_{y}").setimmediatevalue(0) + getattr(self.dut, f"qsfp_tx_rst_{y}").setimmediatevalue(0) + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst.value = 1 + for y in range(1, 5): + getattr(self.dut, f"qsfp_rx_rst_{y}").value = 1 + getattr(self.dut, f"qsfp_tx_rst_{y}").value = 1 + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst.value = 0 + for y in range(1, 5): + getattr(self.dut, f"qsfp_rx_rst_{y}").value = 0 + getattr(self.dut, f"qsfp_tx_rst_{y}").value = 0 + + +@cocotb.test() +async def run_test(dut): + + tb = TB(dut) + + await tb.init() + + tb.log.info("test UDP RX packet") + + payload = bytes([x % 256 for x in range(256)]) + eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00') + ip = IP(src='192.168.1.100', dst='192.168.1.128') + udp = UDP(sport=5678, dport=1234) + test_pkt = eth / ip / udp / payload + + test_frame = XgmiiFrame.from_payload(test_pkt.build()) + + await tb.qsfp_source[0].send(test_frame) + + tb.log.info("receive ARP request") + + rx_frame = await tb.qsfp_sink[0].recv() + + rx_pkt = Ether(bytes(rx_frame.get_payload())) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + assert rx_pkt.dst == 'ff:ff:ff:ff:ff:ff' + assert rx_pkt.src == test_pkt.dst + assert rx_pkt[ARP].hwtype == 1 + assert rx_pkt[ARP].ptype == 0x0800 + assert rx_pkt[ARP].hwlen == 6 + assert rx_pkt[ARP].plen == 4 + assert rx_pkt[ARP].op == 1 + assert rx_pkt[ARP].hwsrc == test_pkt.dst + assert rx_pkt[ARP].psrc == test_pkt[IP].dst + assert rx_pkt[ARP].hwdst == '00:00:00:00:00:00' + assert rx_pkt[ARP].pdst == test_pkt[IP].src + + tb.log.info("send ARP response") + + eth = Ether(src=test_pkt.src, dst=test_pkt.dst) + arp = ARP(hwtype=1, ptype=0x0800, hwlen=6, plen=4, op=2, + hwsrc=test_pkt.src, psrc=test_pkt[IP].src, + hwdst=test_pkt.dst, pdst=test_pkt[IP].dst) + resp_pkt = eth / arp + + resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) + + await tb.qsfp_source[0].send(resp_frame) + + tb.log.info("receive UDP packet") + + rx_frame = await tb.qsfp_sink[0].recv() + + rx_pkt = Ether(bytes(rx_frame.get_payload())) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + assert rx_pkt.dst == test_pkt.src + assert rx_pkt.src == test_pkt.dst + assert rx_pkt[IP].dst == test_pkt[IP].src + assert rx_pkt[IP].src == test_pkt[IP].dst + assert rx_pkt[UDP].dport == test_pkt[UDP].sport + assert rx_pkt[UDP].sport == test_pkt[UDP].dport + assert rx_pkt[UDP].payload == test_pkt[UDP].payload + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'lib', 'axis', 'rtl')) +eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) + + +def test_fpga_core(request): + dut = "fpga_core" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, f"{dut}.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g_fifo.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), + os.path.join(eth_rtl_dir, "lfsr.v"), + os.path.join(eth_rtl_dir, "eth_axis_rx.v"), + os.path.join(eth_rtl_dir, "eth_axis_tx.v"), + os.path.join(eth_rtl_dir, "udp_complete_64.v"), + os.path.join(eth_rtl_dir, "udp_checksum_gen_64.v"), + os.path.join(eth_rtl_dir, "udp_64.v"), + os.path.join(eth_rtl_dir, "udp_ip_rx_64.v"), + os.path.join(eth_rtl_dir, "udp_ip_tx_64.v"), + os.path.join(eth_rtl_dir, "ip_complete_64.v"), + os.path.join(eth_rtl_dir, "ip_64.v"), + os.path.join(eth_rtl_dir, "ip_eth_rx_64.v"), + os.path.join(eth_rtl_dir, "ip_eth_tx_64.v"), + os.path.join(eth_rtl_dir, "ip_arb_mux.v"), + os.path.join(eth_rtl_dir, "arp.v"), + os.path.join(eth_rtl_dir, "arp_cache.v"), + os.path.join(eth_rtl_dir, "arp_eth_rx.v"), + os.path.join(eth_rtl_dir, "arp_eth_tx.v"), + os.path.join(eth_rtl_dir, "eth_arb_mux.v"), + os.path.join(axis_rtl_dir, "arbiter.v"), + os.path.join(axis_rtl_dir, "priority_encoder.v"), + os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + ] + + parameters = {} + + # parameters['A'] = val + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/fpga/lib/eth/example/Arty/fpga/common/vivado.mk b/fpga/lib/eth/example/Arty/fpga/common/vivado.mk index 21e6a5fed..1402e2382 100644 --- a/fpga/lib/eth/example/Arty/fpga/common/vivado.mk +++ b/fpga/lib/eth/example/Arty/fpga/common/vivado.mk @@ -28,7 +28,7 @@ ################################################################### # phony targets -.PHONY: clean fpga +.PHONY: fpga vivado tmpclean clean distclean # prevent make from deleting intermediate files and reports .PRECIOUS: %.xpr %.bit %.mcs %.prm @@ -40,15 +40,16 @@ CONFIG ?= config.mk FPGA_TOP ?= fpga PROJECT ?= $(FPGA_TOP) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else - XDC_FILES_REL = $(FPGA_TOP).xdc + XDC_FILES_REL = $(PROJECT).xdc endif ################################################################### @@ -60,20 +61,20 @@ endif all: fpga -fpga: $(FPGA_TOP).bit +fpga: $(PROJECT).bit -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr -tmpclean: +tmpclean:: -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt -distclean: clean +distclean:: clean -rm -rf rev ################################################################### @@ -91,12 +92,17 @@ create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done -$(PROJECT).xpr: create_project.tcl +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) # synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr echo "open_project $(PROJECT).xpr" > run_synth.tcl echo "reset_run synth_1" >> run_synth.tcl echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl diff --git a/fpga/lib/eth/example/Arty/fpga/fpga.xdc b/fpga/lib/eth/example/Arty/fpga/fpga.xdc index 6c23386f2..f26c74dba 100644 --- a/fpga/lib/eth/example/Arty/fpga/fpga.xdc +++ b/fpga/lib/eth/example/Arty/fpga/fpga.xdc @@ -2,11 +2,11 @@ # part: xc7a35t-csg324-1 # General configuration -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 3.3 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] # 100 MHz clock set_property -dict {LOC E3 IOSTANDARD LVCMOS33} [get_ports clk] diff --git a/fpga/lib/eth/example/DE5-Net/fpga/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/DE5-Net/fpga/tb/fpga_core/test_fpga_core.py index 95b1238af..b2ec8a162 100644 --- a/fpga/lib/eth/example/DE5-Net/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/DE5-Net/fpga/tb/fpga_core/test_fpga_core.py @@ -48,17 +48,14 @@ class TB: cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) # Ethernet - self.sfp_a_source = XgmiiSource(dut.sfp_a_rxd, dut.sfp_a_rxc, dut.clk, dut.rst) - self.sfp_a_sink = XgmiiSink(dut.sfp_a_txd, dut.sfp_a_txc, dut.clk, dut.rst) + self.sfp_source = [] + self.sfp_sink = [] - self.sfp_b_source = XgmiiSource(dut.sfp_b_rxd, dut.sfp_b_rxc, dut.clk, dut.rst) - self.sfp_b_sink = XgmiiSink(dut.sfp_b_txd, dut.sfp_b_txc, dut.clk, dut.rst) - - self.sfp_c_source = XgmiiSource(dut.sfp_c_rxd, dut.sfp_c_rxc, dut.clk, dut.rst) - self.sfp_c_sink = XgmiiSink(dut.sfp_c_txd, dut.sfp_c_txc, dut.clk, dut.rst) - - self.sfp_d_source = XgmiiSource(dut.sfp_d_rxd, dut.sfp_d_rxc, dut.clk, dut.rst) - self.sfp_d_sink = XgmiiSink(dut.sfp_d_txd, dut.sfp_d_txc, dut.clk, dut.rst) + for x in "abcd": + source = XgmiiSource(getattr(dut, f"sfp_{x}_rxd"), getattr(dut, f"sfp_{x}_rxc"), dut.clk, dut.rst) + self.sfp_source.append(source) + sink = XgmiiSink(getattr(dut, f"sfp_{x}_txd"), getattr(dut, f"sfp_{x}_txc"), dut.clk, dut.rst) + self.sfp_sink.append(sink) dut.btn.setimmediatevalue(0) dut.sw.setimmediatevalue(0) @@ -95,11 +92,11 @@ async def run_test(dut): test_frame = XgmiiFrame.from_payload(test_pkt.build()) - await tb.sfp_a_source.send(test_frame) + await tb.sfp_source[0].send(test_frame) tb.log.info("receive ARP request") - rx_frame = await tb.sfp_a_sink.recv() + rx_frame = await tb.sfp_sink[0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -127,11 +124,11 @@ async def run_test(dut): resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - await tb.sfp_a_source.send(resp_frame) + await tb.sfp_source[0].send(resp_frame) tb.log.info("receive UDP packet") - rx_frame = await tb.sfp_a_sink.recv() + rx_frame = await tb.sfp_sink[0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) diff --git a/fpga/lib/eth/example/ExaNIC_X10/fpga/common/vivado.mk b/fpga/lib/eth/example/ExaNIC_X10/fpga/common/vivado.mk index 21e6a5fed..1402e2382 100644 --- a/fpga/lib/eth/example/ExaNIC_X10/fpga/common/vivado.mk +++ b/fpga/lib/eth/example/ExaNIC_X10/fpga/common/vivado.mk @@ -28,7 +28,7 @@ ################################################################### # phony targets -.PHONY: clean fpga +.PHONY: fpga vivado tmpclean clean distclean # prevent make from deleting intermediate files and reports .PRECIOUS: %.xpr %.bit %.mcs %.prm @@ -40,15 +40,16 @@ CONFIG ?= config.mk FPGA_TOP ?= fpga PROJECT ?= $(FPGA_TOP) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else - XDC_FILES_REL = $(FPGA_TOP).xdc + XDC_FILES_REL = $(PROJECT).xdc endif ################################################################### @@ -60,20 +61,20 @@ endif all: fpga -fpga: $(FPGA_TOP).bit +fpga: $(PROJECT).bit -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr -tmpclean: +tmpclean:: -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt -distclean: clean +distclean:: clean -rm -rf rev ################################################################### @@ -91,12 +92,17 @@ create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done -$(PROJECT).xpr: create_project.tcl +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) # synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr echo "open_project $(PROJECT).xpr" > run_synth.tcl echo "reset_run synth_1" >> run_synth.tcl echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl diff --git a/fpga/lib/eth/example/ExaNIC_X10/fpga/fpga.xdc b/fpga/lib/eth/example/ExaNIC_X10/fpga/fpga.xdc index f3c5ef2b0..59392e654 100644 --- a/fpga/lib/eth/example/ExaNIC_X10/fpga/fpga.xdc +++ b/fpga/lib/eth/example/ExaNIC_X10/fpga/fpga.xdc @@ -2,13 +2,14 @@ # part: xcku035-fbva676-2-e # General configuration -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] -set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type2 [current_design] -set_property CONFIG_MODE BPI16 [current_design] +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] +set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type2 [current_design] +set_property CONFIG_MODE BPI16 [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # 100 MHz system clock set_property -dict {LOC D18 IOSTANDARD LVDS} [get_ports clk_100mhz_p] diff --git a/fpga/lib/eth/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py index d4370edac..ea6269f55 100644 --- a/fpga/lib/eth/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py @@ -48,41 +48,39 @@ class TB: cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) # Ethernet - cocotb.start_soon(Clock(dut.sfp_1_rx_clk, 6.4, units="ns").start()) - self.sfp_1_source = XgmiiSource(dut.sfp_1_rxd, dut.sfp_1_rxc, dut.sfp_1_rx_clk, dut.sfp_1_rx_rst) - cocotb.start_soon(Clock(dut.sfp_1_tx_clk, 6.4, units="ns").start()) - self.sfp_1_sink = XgmiiSink(dut.sfp_1_txd, dut.sfp_1_txc, dut.sfp_1_tx_clk, dut.sfp_1_tx_rst) + self.sfp_source = [] + self.sfp_sink = [] - cocotb.start_soon(Clock(dut.sfp_2_rx_clk, 6.4, units="ns").start()) - self.sfp_2_source = XgmiiSource(dut.sfp_2_rxd, dut.sfp_2_rxc, dut.sfp_2_rx_clk, dut.sfp_2_rx_rst) - cocotb.start_soon(Clock(dut.sfp_2_tx_clk, 6.4, units="ns").start()) - self.sfp_2_sink = XgmiiSink(dut.sfp_2_txd, dut.sfp_2_txc, dut.sfp_2_tx_clk, dut.sfp_2_tx_rst) + for y in range(1, 3): + cocotb.start_soon(Clock(getattr(dut, f"sfp_{y}_rx_clk"), 6.4, units="ns").start()) + source = XgmiiSource(getattr(dut, f"sfp_{y}_rxd"), getattr(dut, f"sfp_{y}_rxc"), getattr(dut, f"sfp_{y}_rx_clk"), getattr(dut, f"sfp_{y}_rx_rst")) + self.sfp_source.append(source) + cocotb.start_soon(Clock(getattr(dut, f"sfp_{y}_tx_clk"), 6.4, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"sfp_{y}_txd"), getattr(dut, f"sfp_{y}_txc"), getattr(dut, f"sfp_{y}_tx_clk"), getattr(dut, f"sfp_{y}_tx_rst")) + self.sfp_sink.append(sink) async def init(self): self.dut.rst.setimmediatevalue(0) - self.dut.sfp_1_rx_rst.setimmediatevalue(0) - self.dut.sfp_1_tx_rst.setimmediatevalue(0) - self.dut.sfp_2_rx_rst.setimmediatevalue(0) - self.dut.sfp_2_tx_rst.setimmediatevalue(0) + for y in range(1, 3): + getattr(self.dut, f"sfp_{y}_rx_rst").setimmediatevalue(0) + getattr(self.dut, f"sfp_{y}_tx_rst").setimmediatevalue(0) for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 1 - self.dut.sfp_1_rx_rst.value = 1 - self.dut.sfp_1_tx_rst.value = 1 - self.dut.sfp_2_rx_rst.value = 1 - self.dut.sfp_2_tx_rst.value = 1 + for y in range(1, 3): + getattr(self.dut, f"sfp_{y}_rx_rst").value = 1 + getattr(self.dut, f"sfp_{y}_tx_rst").value = 1 for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 0 - self.dut.sfp_1_rx_rst.value = 0 - self.dut.sfp_1_tx_rst.value = 0 - self.dut.sfp_2_rx_rst.value = 0 - self.dut.sfp_2_tx_rst.value = 0 + for y in range(1, 3): + getattr(self.dut, f"sfp_{y}_rx_rst").value = 0 + getattr(self.dut, f"sfp_{y}_tx_rst").value = 0 @cocotb.test() @@ -102,11 +100,11 @@ async def run_test(dut): test_frame = XgmiiFrame.from_payload(test_pkt.build()) - await tb.sfp_1_source.send(test_frame) + await tb.sfp_source[0].send(test_frame) tb.log.info("receive ARP request") - rx_frame = await tb.sfp_1_sink.recv() + rx_frame = await tb.sfp_sink[0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -134,11 +132,11 @@ async def run_test(dut): resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - await tb.sfp_1_source.send(resp_frame) + await tb.sfp_source[0].send(resp_frame) tb.log.info("receive UDP packet") - rx_frame = await tb.sfp_1_sink.recv() + rx_frame = await tb.sfp_sink[0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/common/vivado.mk b/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/common/vivado.mk deleted file mode 100644 index 21e6a5fed..000000000 --- a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/common/vivado.mk +++ /dev/null @@ -1,131 +0,0 @@ -################################################################### -# -# Xilinx Vivado FPGA Makefile -# -# Copyright (c) 2016 Alex Forencich -# -################################################################### -# -# Parameters: -# FPGA_TOP - Top module name -# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) -# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) -# SYN_FILES - space-separated list of source files -# INC_FILES - space-separated list of include files -# XDC_FILES - space-separated list of timing constraint files -# XCI_FILES - space-separated list of IP XCI files -# -# Example: -# -# FPGA_TOP = fpga -# FPGA_FAMILY = VirtexUltrascale -# FPGA_DEVICE = xcvu095-ffva2104-2-e -# SYN_FILES = rtl/fpga.v -# XDC_FILES = fpga.xdc -# XCI_FILES = ip/pcspma.xci -# include ../common/vivado.mk -# -################################################################### - -# phony targets -.PHONY: clean fpga - -# prevent make from deleting intermediate files and reports -.PRECIOUS: %.xpr %.bit %.mcs %.prm -.SECONDARY: - -CONFIG ?= config.mk --include ../$(CONFIG) - -FPGA_TOP ?= fpga -PROJECT ?= $(FPGA_TOP) - -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) - -ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) -else - XDC_FILES_REL = $(FPGA_TOP).xdc -endif - -################################################################### -# Main Targets -# -# all: build everything -# clean: remove output files and project files -################################################################### - -all: fpga - -fpga: $(FPGA_TOP).bit - -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr - -tmpclean: - -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl - -clean: tmpclean - -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl - -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt - -distclean: clean - -rm -rf rev - -################################################################### -# Target implementations -################################################################### - -# Vivado project file -create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) - rm -rf defines.v - touch defines.v - for x in $(DEFS); do echo '`define' $$x >> defines.v; done - echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ - echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ - echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ - echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ - for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done - for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done - -$(PROJECT).xpr: create_project.tcl - vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) - -# synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) - echo "open_project $(PROJECT).xpr" > run_synth.tcl - echo "reset_run synth_1" >> run_synth.tcl - echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl - echo "wait_on_run synth_1" >> run_synth.tcl - vivado -nojournal -nolog -mode batch -source run_synth.tcl - -# implementation run -$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp - echo "open_project $(PROJECT).xpr" > run_impl.tcl - echo "reset_run impl_1" >> run_impl.tcl - echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl - echo "wait_on_run impl_1" >> run_impl.tcl - echo "open_run impl_1" >> run_impl.tcl - echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl - echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl - vivado -nojournal -nolog -mode batch -source run_impl.tcl - -# bit file -$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp - echo "open_project $(PROJECT).xpr" > generate_bit.tcl - echo "open_run impl_1" >> generate_bit.tcl - echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl - echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl - vivado -nojournal -nolog -mode batch -source generate_bit.tcl - ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi - mkdir -p rev - COUNT=100; \ - while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ - do COUNT=$$((COUNT+1)); done; \ - cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/lib/eth/example/AU50/fpga_10g/Makefile b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/Makefile similarity index 100% rename from fpga/lib/eth/example/AU50/fpga_10g/Makefile rename to fpga/lib/eth/example/ExaNIC_X25/fpga_25g/Makefile diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/README.md b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/README.md similarity index 100% rename from fpga/lib/eth/example/ExaNIC_X25/fpga_10g/README.md rename to fpga/lib/eth/example/ExaNIC_X25/fpga_25g/README.md diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/common/vivado.mk b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/common/vivado.mk new file mode 100644 index 000000000..1402e2382 --- /dev/null +++ b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/common/vivado.mk @@ -0,0 +1,137 @@ +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - space-separated list of source files +# INC_FILES - space-separated list of include files +# XDC_FILES - space-separated list of timing constraint files +# XCI_FILES - space-separated list of IP XCI files +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: fpga vivado tmpclean clean distclean + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include ../$(CONFIG) + +FPGA_TOP ?= fpga +PROJECT ?= $(FPGA_TOP) + +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) + +ifdef XDC_FILES + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +else + XDC_FILES_REL = $(PROJECT).xdc +endif + +################################################################### +# Main Targets +# +# all: build everything +# clean: remove output files and project files +################################################################### + +all: fpga + +fpga: $(PROJECT).bit + +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr + +tmpclean:: + -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean:: tmpclean + -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt + +distclean:: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file +create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ + echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ + echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ + echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ + for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl + vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) + +# synthesis run +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr + echo "open_project $(PROJECT).xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp + echo "open_project $(PROJECT).xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + echo "open_run impl_1" >> run_impl.tcl + echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl + echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# bit file +$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp + echo "open_project $(PROJECT).xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl + echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi + mkdir -p rev + COUNT=100; \ + while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/fpga.xdc b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/fpga.xdc similarity index 100% rename from fpga/lib/eth/example/ExaNIC_X25/fpga_10g/fpga.xdc rename to fpga/lib/eth/example/ExaNIC_X25/fpga_25g/fpga.xdc diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/fpga/Makefile b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/fpga/Makefile similarity index 99% rename from fpga/lib/eth/example/ExaNIC_X25/fpga_10g/fpga/Makefile rename to fpga/lib/eth/example/ExaNIC_X25/fpga_25g/fpga/Makefile index ab32e45dc..ccd409e06 100644 --- a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/fpga/Makefile +++ b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/fpga/Makefile @@ -57,6 +57,9 @@ XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES = ip/eth_xcvr_gt.tcl +# Configuration +CONFIG_TCL_FILES = ./config.tcl + include ../common/vivado.mk program: $(FPGA_TOP).bit diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/fpga/config.tcl b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/fpga/config.tcl new file mode 100644 index 000000000..756e2b3a1 --- /dev/null +++ b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/fpga/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/fpga_10g/Makefile b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/fpga_10g/Makefile new file mode 100644 index 000000000..ccd409e06 --- /dev/null +++ b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/fpga_10g/Makefile @@ -0,0 +1,113 @@ + +# FPGA settings +FPGA_PART = xcku3p-ffvb676-2-e +FPGA_TOP = fpga +FPGA_ARCH = kintexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete_64.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v +SYN_FILES += lib/eth/rtl/udp_64.v +SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v +SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v +SYN_FILES += lib/eth/rtl/ip_complete_64.v +SYN_FILES += lib/eth/rtl/ip_64.v +SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v +SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl + +# IP +IP_TCL_FILES = ip/eth_xcvr_gt.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%.mcs %.prm: %.bit + echo "write_cfgmem -force -format mcs -size 32 -interface BPIx16 -loadbit {up 0x00800000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s29gl256p-bpi-x16}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.BPI_RS_PINS {24:23} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/fpga_10g/config.tcl b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/fpga_10g/config.tcl new file mode 100644 index 000000000..90aa4caeb --- /dev/null +++ b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/fpga_10g/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/ip/eth_xcvr_gt.tcl similarity index 100% rename from fpga/lib/eth/example/ExaNIC_X25/fpga_10g/ip/eth_xcvr_gt.tcl rename to fpga/lib/eth/example/ExaNIC_X25/fpga_25g/ip/eth_xcvr_gt.tcl diff --git a/fpga/lib/eth/example/AU50/fpga_10g/lib/eth b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/lib/eth similarity index 100% rename from fpga/lib/eth/example/AU50/fpga_10g/lib/eth rename to fpga/lib/eth/example/ExaNIC_X25/fpga_25g/lib/eth diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/rtl/eth_xcvr_phy_wrapper.v similarity index 100% rename from fpga/lib/eth/example/ExaNIC_X25/fpga_10g/rtl/eth_xcvr_phy_wrapper.v rename to fpga/lib/eth/example/ExaNIC_X25/fpga_25g/rtl/eth_xcvr_phy_wrapper.v diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/rtl/fpga.v b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/rtl/fpga.v similarity index 100% rename from fpga/lib/eth/example/ExaNIC_X25/fpga_10g/rtl/fpga.v rename to fpga/lib/eth/example/ExaNIC_X25/fpga_25g/rtl/fpga.v diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/rtl/fpga_core.v b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/rtl/fpga_core.v similarity index 100% rename from fpga/lib/eth/example/ExaNIC_X25/fpga_10g/rtl/fpga_core.v rename to fpga/lib/eth/example/ExaNIC_X25/fpga_25g/rtl/fpga_core.v diff --git a/fpga/lib/eth/example/AU50/fpga_10g/rtl/sync_signal.v b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/rtl/sync_signal.v similarity index 100% rename from fpga/lib/eth/example/AU50/fpga_10g/rtl/sync_signal.v rename to fpga/lib/eth/example/ExaNIC_X25/fpga_25g/rtl/sync_signal.v diff --git a/fpga/lib/eth/example/AU50/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile similarity index 100% rename from fpga/lib/eth/example/AU50/fpga_10g/tb/fpga_core/Makefile rename to fpga/lib/eth/example/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py new file mode 100644 index 000000000..16c91df3b --- /dev/null +++ b/fpga/lib/eth/example/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -0,0 +1,219 @@ +""" + +Copyright (c) 2020 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +""" + +import logging +import os + +from scapy.layers.l2 import Ether, ARP +from scapy.layers.inet import IP, UDP + +import cocotb_test.simulator + +import cocotb +from cocotb.log import SimLog +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge + +from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = SimLog("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 2.56, units="ns").start()) + + # Ethernet + self.sfp_source = [] + self.sfp_sink = [] + + for y in range(1, 3): + cocotb.start_soon(Clock(getattr(dut, f"sfp_{y}_rx_clk"), 2.56, units="ns").start()) + source = XgmiiSource(getattr(dut, f"sfp_{y}_rxd"), getattr(dut, f"sfp_{y}_rxc"), getattr(dut, f"sfp_{y}_rx_clk"), getattr(dut, f"sfp_{y}_rx_rst")) + self.sfp_source.append(source) + cocotb.start_soon(Clock(getattr(dut, f"sfp_{y}_tx_clk"), 2.56, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"sfp_{y}_txd"), getattr(dut, f"sfp_{y}_txc"), getattr(dut, f"sfp_{y}_tx_clk"), getattr(dut, f"sfp_{y}_tx_rst")) + self.sfp_sink.append(sink) + + async def init(self): + + self.dut.rst.setimmediatevalue(0) + for y in range(1, 3): + getattr(self.dut, f"sfp_{y}_rx_rst").setimmediatevalue(0) + getattr(self.dut, f"sfp_{y}_tx_rst").setimmediatevalue(0) + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst.value = 1 + for y in range(1, 3): + getattr(self.dut, f"sfp_{y}_rx_rst").value = 1 + getattr(self.dut, f"sfp_{y}_tx_rst").value = 1 + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst.value = 0 + for y in range(1, 3): + getattr(self.dut, f"sfp_{y}_rx_rst").value = 0 + getattr(self.dut, f"sfp_{y}_tx_rst").value = 0 + + +@cocotb.test() +async def run_test(dut): + + tb = TB(dut) + + await tb.init() + + tb.log.info("test UDP RX packet") + + payload = bytes([x % 256 for x in range(256)]) + eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00') + ip = IP(src='192.168.1.100', dst='192.168.1.128') + udp = UDP(sport=5678, dport=1234) + test_pkt = eth / ip / udp / payload + + test_frame = XgmiiFrame.from_payload(test_pkt.build()) + + await tb.sfp_source[0].send(test_frame) + + tb.log.info("receive ARP request") + + rx_frame = await tb.sfp_sink[0].recv() + + rx_pkt = Ether(bytes(rx_frame.get_payload())) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + assert rx_pkt.dst == 'ff:ff:ff:ff:ff:ff' + assert rx_pkt.src == test_pkt.dst + assert rx_pkt[ARP].hwtype == 1 + assert rx_pkt[ARP].ptype == 0x0800 + assert rx_pkt[ARP].hwlen == 6 + assert rx_pkt[ARP].plen == 4 + assert rx_pkt[ARP].op == 1 + assert rx_pkt[ARP].hwsrc == test_pkt.dst + assert rx_pkt[ARP].psrc == test_pkt[IP].dst + assert rx_pkt[ARP].hwdst == '00:00:00:00:00:00' + assert rx_pkt[ARP].pdst == test_pkt[IP].src + + tb.log.info("send ARP response") + + eth = Ether(src=test_pkt.src, dst=test_pkt.dst) + arp = ARP(hwtype=1, ptype=0x0800, hwlen=6, plen=4, op=2, + hwsrc=test_pkt.src, psrc=test_pkt[IP].src, + hwdst=test_pkt.dst, pdst=test_pkt[IP].dst) + resp_pkt = eth / arp + + resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) + + await tb.sfp_source[0].send(resp_frame) + + tb.log.info("receive UDP packet") + + rx_frame = await tb.sfp_sink[0].recv() + + rx_pkt = Ether(bytes(rx_frame.get_payload())) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + assert rx_pkt.dst == test_pkt.src + assert rx_pkt.src == test_pkt.dst + assert rx_pkt[IP].dst == test_pkt[IP].src + assert rx_pkt[IP].src == test_pkt[IP].dst + assert rx_pkt[UDP].dport == test_pkt[UDP].sport + assert rx_pkt[UDP].sport == test_pkt[UDP].dport + assert rx_pkt[UDP].payload == test_pkt[UDP].payload + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'lib', 'axis', 'rtl')) +eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) + + +def test_fpga_core(request): + dut = "fpga_core" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, f"{dut}.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g_fifo.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), + os.path.join(eth_rtl_dir, "lfsr.v"), + os.path.join(eth_rtl_dir, "eth_axis_rx.v"), + os.path.join(eth_rtl_dir, "eth_axis_tx.v"), + os.path.join(eth_rtl_dir, "udp_complete_64.v"), + os.path.join(eth_rtl_dir, "udp_checksum_gen_64.v"), + os.path.join(eth_rtl_dir, "udp_64.v"), + os.path.join(eth_rtl_dir, "udp_ip_rx_64.v"), + os.path.join(eth_rtl_dir, "udp_ip_tx_64.v"), + os.path.join(eth_rtl_dir, "ip_complete_64.v"), + os.path.join(eth_rtl_dir, "ip_64.v"), + os.path.join(eth_rtl_dir, "ip_eth_rx_64.v"), + os.path.join(eth_rtl_dir, "ip_eth_tx_64.v"), + os.path.join(eth_rtl_dir, "ip_arb_mux.v"), + os.path.join(eth_rtl_dir, "arp.v"), + os.path.join(eth_rtl_dir, "arp_cache.v"), + os.path.join(eth_rtl_dir, "arp_eth_rx.v"), + os.path.join(eth_rtl_dir, "arp_eth_tx.v"), + os.path.join(eth_rtl_dir, "eth_arb_mux.v"), + os.path.join(axis_rtl_dir, "arbiter.v"), + os.path.join(axis_rtl_dir, "priority_encoder.v"), + os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + ] + + parameters = {} + + # parameters['A'] = val + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/fpga/lib/eth/example/HXT100G/fpga/Makefile b/fpga/lib/eth/example/HTG640/fpga/Makefile similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga/Makefile rename to fpga/lib/eth/example/HTG640/fpga/Makefile diff --git a/fpga/lib/eth/example/HXT100G/fpga/README.md b/fpga/lib/eth/example/HTG640/fpga/README.md similarity index 77% rename from fpga/lib/eth/example/HXT100G/fpga/README.md rename to fpga/lib/eth/example/HTG640/fpga/README.md index 2a46b7101..b66a59bf5 100644 --- a/fpga/lib/eth/example/HXT100G/fpga/README.md +++ b/fpga/lib/eth/example/HTG640/fpga/README.md @@ -1,8 +1,8 @@ -# Verilog Ethernet HXT100G Example Design +# Verilog Ethernet HTG-640 Example Design ## Introduction -This example design targets the HiTech Global HXT100G FPGA board. +This example design targets the HiTech Global HTG-640 (HTG-V6HXT-100GIG-565) FPGA board. The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly @@ -18,7 +18,7 @@ in PATH. ## How to test -Run make program to program the HXT100G board with the Xilinx Impact software. +Run make program to program the HTG-640 board with the Xilinx Impact software. Then run netcat -u 192.168.1.128 1234 diff --git a/fpga/lib/eth/example/HXT100G/fpga/common/xilinx.mk b/fpga/lib/eth/example/HTG640/fpga/common/xilinx.mk similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga/common/xilinx.mk rename to fpga/lib/eth/example/HTG640/fpga/common/xilinx.mk diff --git a/fpga/lib/eth/example/HXT100G/fpga/coregen/Makefile b/fpga/lib/eth/example/HTG640/fpga/coregen/Makefile similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga/coregen/Makefile rename to fpga/lib/eth/example/HTG640/fpga/coregen/Makefile diff --git a/fpga/lib/eth/example/HXT100G/fpga/coregen/coregen.cgp b/fpga/lib/eth/example/HTG640/fpga/coregen/coregen.cgp similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga/coregen/coregen.cgp rename to fpga/lib/eth/example/HTG640/fpga/coregen/coregen.cgp diff --git a/fpga/lib/eth/example/HXT100G/fpga/coregen/ten_gig_eth_pcs_pma_v2_6.xco b/fpga/lib/eth/example/HTG640/fpga/coregen/ten_gig_eth_pcs_pma_v2_6.xco similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga/coregen/ten_gig_eth_pcs_pma_v2_6.xco rename to fpga/lib/eth/example/HTG640/fpga/coregen/ten_gig_eth_pcs_pma_v2_6.xco diff --git a/fpga/lib/eth/example/HXT100G/fpga/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco b/fpga/lib/eth/example/HTG640/fpga/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco rename to fpga/lib/eth/example/HTG640/fpga/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco diff --git a/fpga/lib/eth/example/HXT100G/fpga/fpga.ucf b/fpga/lib/eth/example/HTG640/fpga/fpga.ucf similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga/fpga.ucf rename to fpga/lib/eth/example/HTG640/fpga/fpga.ucf diff --git a/fpga/lib/eth/example/HXT100G/fpga/fpga/Makefile b/fpga/lib/eth/example/HTG640/fpga/fpga/Makefile similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga/fpga/Makefile rename to fpga/lib/eth/example/HTG640/fpga/fpga/Makefile diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/lib/eth b/fpga/lib/eth/example/HTG640/fpga/lib/eth similarity index 100% rename from fpga/lib/eth/example/ExaNIC_X25/fpga_10g/lib/eth rename to fpga/lib/eth/example/HTG640/fpga/lib/eth diff --git a/fpga/lib/eth/example/HXT100G/fpga/rtl/debounce_switch.v b/fpga/lib/eth/example/HTG640/fpga/rtl/debounce_switch.v similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga/rtl/debounce_switch.v rename to fpga/lib/eth/example/HTG640/fpga/rtl/debounce_switch.v diff --git a/fpga/lib/eth/example/HXT100G/fpga/rtl/eth_gth_phy_quad.v b/fpga/lib/eth/example/HTG640/fpga/rtl/eth_gth_phy_quad.v similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga/rtl/eth_gth_phy_quad.v rename to fpga/lib/eth/example/HTG640/fpga/rtl/eth_gth_phy_quad.v diff --git a/fpga/lib/eth/example/HXT100G/fpga/rtl/fpga.v b/fpga/lib/eth/example/HTG640/fpga/rtl/fpga.v similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga/rtl/fpga.v rename to fpga/lib/eth/example/HTG640/fpga/rtl/fpga.v diff --git a/fpga/lib/eth/example/HXT100G/fpga/rtl/fpga_core.v b/fpga/lib/eth/example/HTG640/fpga/rtl/fpga_core.v similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga/rtl/fpga_core.v rename to fpga/lib/eth/example/HTG640/fpga/rtl/fpga_core.v diff --git a/fpga/lib/eth/example/HXT100G/fpga/rtl/gth_i2c_init.v b/fpga/lib/eth/example/HTG640/fpga/rtl/gth_i2c_init.v similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga/rtl/gth_i2c_init.v rename to fpga/lib/eth/example/HTG640/fpga/rtl/gth_i2c_init.v diff --git a/fpga/lib/eth/example/HXT100G/fpga/rtl/i2c_master.v b/fpga/lib/eth/example/HTG640/fpga/rtl/i2c_master.v similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga/rtl/i2c_master.v rename to fpga/lib/eth/example/HTG640/fpga/rtl/i2c_master.v diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/rtl/sync_signal.v b/fpga/lib/eth/example/HTG640/fpga/rtl/sync_signal.v similarity index 100% rename from fpga/lib/eth/example/ExaNIC_X25/fpga_10g/rtl/sync_signal.v rename to fpga/lib/eth/example/HTG640/fpga/rtl/sync_signal.v diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/HTG640/fpga/tb/fpga_core/Makefile similarity index 100% rename from fpga/lib/eth/example/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile rename to fpga/lib/eth/example/HTG640/fpga/tb/fpga_core/Makefile diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/HTG640/fpga/tb/fpga_core/test_fpga_core.py similarity index 81% rename from fpga/lib/eth/example/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py rename to fpga/lib/eth/example/HTG640/fpga/tb/fpga_core/test_fpga_core.py index d4370edac..4f841d926 100644 --- a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/HTG640/fpga/tb/fpga_core/test_fpga_core.py @@ -48,41 +48,46 @@ class TB: cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) # Ethernet - cocotb.start_soon(Clock(dut.sfp_1_rx_clk, 6.4, units="ns").start()) - self.sfp_1_source = XgmiiSource(dut.sfp_1_rxd, dut.sfp_1_rxc, dut.sfp_1_rx_clk, dut.sfp_1_rx_rst) - cocotb.start_soon(Clock(dut.sfp_1_tx_clk, 6.4, units="ns").start()) - self.sfp_1_sink = XgmiiSink(dut.sfp_1_txd, dut.sfp_1_txc, dut.sfp_1_tx_clk, dut.sfp_1_tx_rst) + self.eth_r_source = [] + self.eth_r_sink = [] - cocotb.start_soon(Clock(dut.sfp_2_rx_clk, 6.4, units="ns").start()) - self.sfp_2_source = XgmiiSource(dut.sfp_2_rxd, dut.sfp_2_rxc, dut.sfp_2_rx_clk, dut.sfp_2_rx_rst) - cocotb.start_soon(Clock(dut.sfp_2_tx_clk, 6.4, units="ns").start()) - self.sfp_2_sink = XgmiiSink(dut.sfp_2_txd, dut.sfp_2_txc, dut.sfp_2_tx_clk, dut.sfp_2_tx_rst) + for x in range(12): + source = XgmiiSource(getattr(dut, f"eth_r{x}_rxd"), getattr(dut, f"eth_r{x}_rxc"), dut.clk, dut.rst) + self.eth_r_source.append(source) + sink = XgmiiSink(getattr(dut, f"eth_r{x}_txd"), getattr(dut, f"eth_r{x}_txc"), dut.clk, dut.rst) + self.eth_r_sink.append(sink) + + self.eth_l_source = [] + self.eth_l_sink = [] + + for x in range(12): + source = XgmiiSource(getattr(dut, f"eth_l{x}_rxd"), getattr(dut, f"eth_l{x}_rxc"), dut.clk, dut.rst) + self.eth_l_source.append(source) + sink = XgmiiSink(getattr(dut, f"eth_l{x}_txd"), getattr(dut, f"eth_l{x}_txc"), dut.clk, dut.rst) + self.eth_l_sink.append(sink) + + dut.sw.setimmediatevalue(0) + dut.jp.setimmediatevalue(0) + dut.uart_suspend.setimmediatevalue(0) + dut.uart_dtr.setimmediatevalue(0) + dut.uart_txd.setimmediatevalue(0) + dut.uart_rts.setimmediatevalue(0) + dut.amh_right_mdio_i.setimmediatevalue(0) + dut.amh_left_mdio_i.setimmediatevalue(0) async def init(self): self.dut.rst.setimmediatevalue(0) - self.dut.sfp_1_rx_rst.setimmediatevalue(0) - self.dut.sfp_1_tx_rst.setimmediatevalue(0) - self.dut.sfp_2_rx_rst.setimmediatevalue(0) - self.dut.sfp_2_tx_rst.setimmediatevalue(0) for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 1 - self.dut.sfp_1_rx_rst.value = 1 - self.dut.sfp_1_tx_rst.value = 1 - self.dut.sfp_2_rx_rst.value = 1 - self.dut.sfp_2_tx_rst.value = 1 for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 0 - self.dut.sfp_1_rx_rst.value = 0 - self.dut.sfp_1_tx_rst.value = 0 - self.dut.sfp_2_rx_rst.value = 0 - self.dut.sfp_2_tx_rst.value = 0 @cocotb.test() @@ -102,11 +107,11 @@ async def run_test(dut): test_frame = XgmiiFrame.from_payload(test_pkt.build()) - await tb.sfp_1_source.send(test_frame) + await tb.eth_l_source[0].send(test_frame) tb.log.info("receive ARP request") - rx_frame = await tb.sfp_1_sink.recv() + rx_frame = await tb.eth_l_sink[0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -134,11 +139,11 @@ async def run_test(dut): resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - await tb.sfp_1_source.send(resp_frame) + await tb.eth_l_source[0].send(resp_frame) tb.log.info("receive UDP packet") - rx_frame = await tb.sfp_1_sink.recv() + rx_frame = await tb.eth_l_sink[0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/Makefile b/fpga/lib/eth/example/HTG640/fpga_cxpt16/Makefile similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga_cxpt16/Makefile rename to fpga/lib/eth/example/HTG640/fpga_cxpt16/Makefile diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/README.md b/fpga/lib/eth/example/HTG640/fpga_cxpt16/README.md similarity index 87% rename from fpga/lib/eth/example/HXT100G/fpga_cxpt16/README.md rename to fpga/lib/eth/example/HTG640/fpga_cxpt16/README.md index c31e812af..806220684 100644 --- a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/README.md +++ b/fpga/lib/eth/example/HTG640/fpga_cxpt16/README.md @@ -1,8 +1,8 @@ -# Verilog Ethernet HXT100G Crosspoint Switch Design +# Verilog Ethernet HTG-640 Crosspoint Switch Design ## Introduction -This design targets the HiTech Global HXT100G FPGA board. +This design targets the HiTech Global HTG-640 (HTG-V6HXT-100GIG-565) FPGA board. The design forms a 16x16 crosspoint switch for 10G Ethernet. It is capable of connecting any output port to any input port based on configuration frames diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/common/xilinx.mk b/fpga/lib/eth/example/HTG640/fpga_cxpt16/common/xilinx.mk similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga_cxpt16/common/xilinx.mk rename to fpga/lib/eth/example/HTG640/fpga_cxpt16/common/xilinx.mk diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/coregen/Makefile b/fpga/lib/eth/example/HTG640/fpga_cxpt16/coregen/Makefile similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga_cxpt16/coregen/Makefile rename to fpga/lib/eth/example/HTG640/fpga_cxpt16/coregen/Makefile diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/coregen/coregen.cgp b/fpga/lib/eth/example/HTG640/fpga_cxpt16/coregen/coregen.cgp similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga_cxpt16/coregen/coregen.cgp rename to fpga/lib/eth/example/HTG640/fpga_cxpt16/coregen/coregen.cgp diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6.xco b/fpga/lib/eth/example/HTG640/fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6.xco similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6.xco rename to fpga/lib/eth/example/HTG640/fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6.xco diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco b/fpga/lib/eth/example/HTG640/fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco rename to fpga/lib/eth/example/HTG640/fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/fpga.ucf b/fpga/lib/eth/example/HTG640/fpga_cxpt16/fpga.ucf similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga_cxpt16/fpga.ucf rename to fpga/lib/eth/example/HTG640/fpga_cxpt16/fpga.ucf diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/fpga/Makefile b/fpga/lib/eth/example/HTG640/fpga_cxpt16/fpga/Makefile similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga_cxpt16/fpga/Makefile rename to fpga/lib/eth/example/HTG640/fpga_cxpt16/fpga/Makefile diff --git a/fpga/lib/eth/example/HTG9200/fpga_10g/lib/eth b/fpga/lib/eth/example/HTG640/fpga_cxpt16/lib/eth similarity index 100% rename from fpga/lib/eth/example/HTG9200/fpga_10g/lib/eth rename to fpga/lib/eth/example/HTG640/fpga_cxpt16/lib/eth diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/rtl/debounce_switch.v b/fpga/lib/eth/example/HTG640/fpga_cxpt16/rtl/debounce_switch.v similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga_cxpt16/rtl/debounce_switch.v rename to fpga/lib/eth/example/HTG640/fpga_cxpt16/rtl/debounce_switch.v diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/rtl/eth_gth_phy_quad.v b/fpga/lib/eth/example/HTG640/fpga_cxpt16/rtl/eth_gth_phy_quad.v similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga_cxpt16/rtl/eth_gth_phy_quad.v rename to fpga/lib/eth/example/HTG640/fpga_cxpt16/rtl/eth_gth_phy_quad.v diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/rtl/fpga.v b/fpga/lib/eth/example/HTG640/fpga_cxpt16/rtl/fpga.v similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga_cxpt16/rtl/fpga.v rename to fpga/lib/eth/example/HTG640/fpga_cxpt16/rtl/fpga.v diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/rtl/fpga_core.v b/fpga/lib/eth/example/HTG640/fpga_cxpt16/rtl/fpga_core.v similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga_cxpt16/rtl/fpga_core.v rename to fpga/lib/eth/example/HTG640/fpga_cxpt16/rtl/fpga_core.v diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/rtl/gth_i2c_init.v b/fpga/lib/eth/example/HTG640/fpga_cxpt16/rtl/gth_i2c_init.v similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga_cxpt16/rtl/gth_i2c_init.v rename to fpga/lib/eth/example/HTG640/fpga_cxpt16/rtl/gth_i2c_init.v diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/rtl/i2c_master.v b/fpga/lib/eth/example/HTG640/fpga_cxpt16/rtl/i2c_master.v similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga_cxpt16/rtl/i2c_master.v rename to fpga/lib/eth/example/HTG640/fpga_cxpt16/rtl/i2c_master.v diff --git a/fpga/lib/eth/example/HXT100G/fpga/rtl/sync_signal.v b/fpga/lib/eth/example/HTG640/fpga_cxpt16/rtl/sync_signal.v similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga/rtl/sync_signal.v rename to fpga/lib/eth/example/HTG640/fpga_cxpt16/rtl/sync_signal.v diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/tb/fpga_core/Makefile b/fpga/lib/eth/example/HTG640/fpga_cxpt16/tb/fpga_core/Makefile similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga_cxpt16/tb/fpga_core/Makefile rename to fpga/lib/eth/example/HTG640/fpga_cxpt16/tb/fpga_core/Makefile diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/HTG640/fpga_cxpt16/tb/fpga_core/test_fpga_core.py similarity index 52% rename from fpga/lib/eth/example/HXT100G/fpga_cxpt16/tb/fpga_core/test_fpga_core.py rename to fpga/lib/eth/example/HTG640/fpga_cxpt16/tb/fpga_core/test_fpga_core.py index 7f3e94ed8..6ff9520d4 100644 --- a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/HTG640/fpga_cxpt16/tb/fpga_core/test_fpga_core.py @@ -47,77 +47,23 @@ class TB: cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) # Ethernet - self.eth_r0_source = XgmiiSource(dut.eth_r0_rxd, dut.eth_r0_rxc, dut.clk, dut.rst) - self.eth_r0_sink = XgmiiSink(dut.eth_r0_txd, dut.eth_r0_txc, dut.clk, dut.rst) + self.eth_r_source = [] + self.eth_r_sink = [] - self.eth_r1_source = XgmiiSource(dut.eth_r1_rxd, dut.eth_r1_rxc, dut.clk, dut.rst) - self.eth_r1_sink = XgmiiSink(dut.eth_r1_txd, dut.eth_r1_txc, dut.clk, dut.rst) + for x in range(12): + source = XgmiiSource(getattr(dut, f"eth_r{x}_rxd"), getattr(dut, f"eth_r{x}_rxc"), dut.clk, dut.rst) + self.eth_r_source.append(source) + sink = XgmiiSink(getattr(dut, f"eth_r{x}_txd"), getattr(dut, f"eth_r{x}_txc"), dut.clk, dut.rst) + self.eth_r_sink.append(sink) - self.eth_r2_source = XgmiiSource(dut.eth_r2_rxd, dut.eth_r2_rxc, dut.clk, dut.rst) - self.eth_r2_sink = XgmiiSink(dut.eth_r2_txd, dut.eth_r2_txc, dut.clk, dut.rst) + self.eth_l_source = [] + self.eth_l_sink = [] - self.eth_r3_source = XgmiiSource(dut.eth_r3_rxd, dut.eth_r3_rxc, dut.clk, dut.rst) - self.eth_r3_sink = XgmiiSink(dut.eth_r3_txd, dut.eth_r3_txc, dut.clk, dut.rst) - - self.eth_r4_source = XgmiiSource(dut.eth_r4_rxd, dut.eth_r4_rxc, dut.clk, dut.rst) - self.eth_r4_sink = XgmiiSink(dut.eth_r4_txd, dut.eth_r4_txc, dut.clk, dut.rst) - - self.eth_r5_source = XgmiiSource(dut.eth_r5_rxd, dut.eth_r5_rxc, dut.clk, dut.rst) - self.eth_r5_sink = XgmiiSink(dut.eth_r5_txd, dut.eth_r5_txc, dut.clk, dut.rst) - - self.eth_r6_source = XgmiiSource(dut.eth_r6_rxd, dut.eth_r6_rxc, dut.clk, dut.rst) - self.eth_r6_sink = XgmiiSink(dut.eth_r6_txd, dut.eth_r6_txc, dut.clk, dut.rst) - - self.eth_r7_source = XgmiiSource(dut.eth_r7_rxd, dut.eth_r7_rxc, dut.clk, dut.rst) - self.eth_r7_sink = XgmiiSink(dut.eth_r7_txd, dut.eth_r7_txc, dut.clk, dut.rst) - - self.eth_r8_source = XgmiiSource(dut.eth_r8_rxd, dut.eth_r8_rxc, dut.clk, dut.rst) - self.eth_r8_sink = XgmiiSink(dut.eth_r8_txd, dut.eth_r8_txc, dut.clk, dut.rst) - - self.eth_r9_source = XgmiiSource(dut.eth_r9_rxd, dut.eth_r9_rxc, dut.clk, dut.rst) - self.eth_r9_sink = XgmiiSink(dut.eth_r9_txd, dut.eth_r9_txc, dut.clk, dut.rst) - - self.eth_r10_source = XgmiiSource(dut.eth_r10_rxd, dut.eth_r10_rxc, dut.clk, dut.rst) - self.eth_r10_sink = XgmiiSink(dut.eth_r10_txd, dut.eth_r10_txc, dut.clk, dut.rst) - - self.eth_r11_source = XgmiiSource(dut.eth_r11_rxd, dut.eth_r11_rxc, dut.clk, dut.rst) - self.eth_r11_sink = XgmiiSink(dut.eth_r11_txd, dut.eth_r11_txc, dut.clk, dut.rst) - - self.eth_l0_source = XgmiiSource(dut.eth_l0_rxd, dut.eth_l0_rxc, dut.clk, dut.rst) - self.eth_l0_sink = XgmiiSink(dut.eth_l0_txd, dut.eth_l0_txc, dut.clk, dut.rst) - - self.eth_l1_source = XgmiiSource(dut.eth_l1_rxd, dut.eth_l1_rxc, dut.clk, dut.rst) - self.eth_l1_sink = XgmiiSink(dut.eth_l1_txd, dut.eth_l1_txc, dut.clk, dut.rst) - - self.eth_l2_source = XgmiiSource(dut.eth_l2_rxd, dut.eth_l2_rxc, dut.clk, dut.rst) - self.eth_l2_sink = XgmiiSink(dut.eth_l2_txd, dut.eth_l2_txc, dut.clk, dut.rst) - - self.eth_l3_source = XgmiiSource(dut.eth_l3_rxd, dut.eth_l3_rxc, dut.clk, dut.rst) - self.eth_l3_sink = XgmiiSink(dut.eth_l3_txd, dut.eth_l3_txc, dut.clk, dut.rst) - - self.eth_l4_source = XgmiiSource(dut.eth_l4_rxd, dut.eth_l4_rxc, dut.clk, dut.rst) - self.eth_l4_sink = XgmiiSink(dut.eth_l4_txd, dut.eth_l4_txc, dut.clk, dut.rst) - - self.eth_l5_source = XgmiiSource(dut.eth_l5_rxd, dut.eth_l5_rxc, dut.clk, dut.rst) - self.eth_l5_sink = XgmiiSink(dut.eth_l5_txd, dut.eth_l5_txc, dut.clk, dut.rst) - - self.eth_l6_source = XgmiiSource(dut.eth_l6_rxd, dut.eth_l6_rxc, dut.clk, dut.rst) - self.eth_l6_sink = XgmiiSink(dut.eth_l6_txd, dut.eth_l6_txc, dut.clk, dut.rst) - - self.eth_l7_source = XgmiiSource(dut.eth_l7_rxd, dut.eth_l7_rxc, dut.clk, dut.rst) - self.eth_l7_sink = XgmiiSink(dut.eth_l7_txd, dut.eth_l7_txc, dut.clk, dut.rst) - - self.eth_l8_source = XgmiiSource(dut.eth_l8_rxd, dut.eth_l8_rxc, dut.clk, dut.rst) - self.eth_l8_sink = XgmiiSink(dut.eth_l8_txd, dut.eth_l8_txc, dut.clk, dut.rst) - - self.eth_l9_source = XgmiiSource(dut.eth_l9_rxd, dut.eth_l9_rxc, dut.clk, dut.rst) - self.eth_l9_sink = XgmiiSink(dut.eth_l9_txd, dut.eth_l9_txc, dut.clk, dut.rst) - - self.eth_l10_source = XgmiiSource(dut.eth_l10_rxd, dut.eth_l10_rxc, dut.clk, dut.rst) - self.eth_l10_sink = XgmiiSink(dut.eth_l10_txd, dut.eth_l10_txc, dut.clk, dut.rst) - - self.eth_l11_source = XgmiiSource(dut.eth_l11_rxd, dut.eth_l11_rxc, dut.clk, dut.rst) - self.eth_l11_sink = XgmiiSink(dut.eth_l11_txd, dut.eth_l11_txc, dut.clk, dut.rst) + for x in range(12): + source = XgmiiSource(getattr(dut, f"eth_l{x}_rxd"), getattr(dut, f"eth_l{x}_rxc"), dut.clk, dut.rst) + self.eth_l_source.append(source) + sink = XgmiiSink(getattr(dut, f"eth_l{x}_txd"), getattr(dut, f"eth_l{x}_txc"), dut.clk, dut.rst) + self.eth_l_sink.append(sink) dut.sw.setimmediatevalue(0) dut.jp.setimmediatevalue(0) @@ -158,9 +104,9 @@ async def run_test(dut): test_frame = XgmiiFrame.from_payload(test_pkt.build()) - await tb.eth_l0_source.send(test_frame) + await tb.eth_l_source[0].send(test_frame) - rx_frame = await tb.eth_l0_sink.recv() + rx_frame = await tb.eth_l_sink[0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -176,7 +122,7 @@ async def run_test(dut): test_frame = XgmiiFrame.from_payload(test_pkt.build()) - await tb.eth_l11_source.send(test_frame) + await tb.eth_l_source[11].send(test_frame) await Timer(400, 'ns') @@ -188,9 +134,9 @@ async def run_test(dut): test_frame = XgmiiFrame.from_payload(test_pkt.build()) - await tb.eth_l0_source.send(test_frame) + await tb.eth_l_source[0].send(test_frame) - rx_frame = await tb.eth_r7_sink.recv() + rx_frame = await tb.eth_r_sink[7].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) diff --git a/fpga/lib/eth/example/HTG9200/fpga_10g/common/vivado.mk b/fpga/lib/eth/example/HTG9200/fpga_10g/common/vivado.mk deleted file mode 100644 index 21e6a5fed..000000000 --- a/fpga/lib/eth/example/HTG9200/fpga_10g/common/vivado.mk +++ /dev/null @@ -1,131 +0,0 @@ -################################################################### -# -# Xilinx Vivado FPGA Makefile -# -# Copyright (c) 2016 Alex Forencich -# -################################################################### -# -# Parameters: -# FPGA_TOP - Top module name -# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) -# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) -# SYN_FILES - space-separated list of source files -# INC_FILES - space-separated list of include files -# XDC_FILES - space-separated list of timing constraint files -# XCI_FILES - space-separated list of IP XCI files -# -# Example: -# -# FPGA_TOP = fpga -# FPGA_FAMILY = VirtexUltrascale -# FPGA_DEVICE = xcvu095-ffva2104-2-e -# SYN_FILES = rtl/fpga.v -# XDC_FILES = fpga.xdc -# XCI_FILES = ip/pcspma.xci -# include ../common/vivado.mk -# -################################################################### - -# phony targets -.PHONY: clean fpga - -# prevent make from deleting intermediate files and reports -.PRECIOUS: %.xpr %.bit %.mcs %.prm -.SECONDARY: - -CONFIG ?= config.mk --include ../$(CONFIG) - -FPGA_TOP ?= fpga -PROJECT ?= $(FPGA_TOP) - -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) - -ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) -else - XDC_FILES_REL = $(FPGA_TOP).xdc -endif - -################################################################### -# Main Targets -# -# all: build everything -# clean: remove output files and project files -################################################################### - -all: fpga - -fpga: $(FPGA_TOP).bit - -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr - -tmpclean: - -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl - -clean: tmpclean - -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl - -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt - -distclean: clean - -rm -rf rev - -################################################################### -# Target implementations -################################################################### - -# Vivado project file -create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) - rm -rf defines.v - touch defines.v - for x in $(DEFS); do echo '`define' $$x >> defines.v; done - echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ - echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ - echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ - echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ - for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done - for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done - -$(PROJECT).xpr: create_project.tcl - vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) - -# synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) - echo "open_project $(PROJECT).xpr" > run_synth.tcl - echo "reset_run synth_1" >> run_synth.tcl - echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl - echo "wait_on_run synth_1" >> run_synth.tcl - vivado -nojournal -nolog -mode batch -source run_synth.tcl - -# implementation run -$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp - echo "open_project $(PROJECT).xpr" > run_impl.tcl - echo "reset_run impl_1" >> run_impl.tcl - echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl - echo "wait_on_run impl_1" >> run_impl.tcl - echo "open_run impl_1" >> run_impl.tcl - echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl - echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl - vivado -nojournal -nolog -mode batch -source run_impl.tcl - -# bit file -$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp - echo "open_project $(PROJECT).xpr" > generate_bit.tcl - echo "open_run impl_1" >> generate_bit.tcl - echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl - echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl - vivado -nojournal -nolog -mode batch -source generate_bit.tcl - ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi - mkdir -p rev - COUNT=100; \ - while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ - do COUNT=$$((COUNT+1)); done; \ - cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/lib/eth/example/HTG9200/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/HTG9200/fpga_10g/tb/fpga_core/test_fpga_core.py deleted file mode 100644 index 0a109c8be..000000000 --- a/fpga/lib/eth/example/HTG9200/fpga_10g/tb/fpga_core/test_fpga_core.py +++ /dev/null @@ -1,601 +0,0 @@ -""" - -Copyright (c) 2020 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -""" - -import logging -import os - -from scapy.layers.l2 import Ether, ARP -from scapy.layers.inet import IP, UDP - -import cocotb_test.simulator - -import cocotb -from cocotb.log import SimLog -from cocotb.clock import Clock -from cocotb.triggers import RisingEdge - -from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink - - -class TB: - def __init__(self, dut): - self.dut = dut - - self.log = SimLog("cocotb.tb") - self.log.setLevel(logging.DEBUG) - - cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) - - dut.btn.setimmediatevalue(0) - dut.sw.setimmediatevalue(0) - - dut.uart_txd.setimmediatevalue(1) - dut.uart_rts.setimmediatevalue(1) - - # Ethernet - cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_1, 6.4, units="ns").start()) - self.qsfp_1_1_source = XgmiiSource(dut.qsfp_1_rxd_1, dut.qsfp_1_rxc_1, dut.qsfp_1_rx_clk_1, dut.qsfp_1_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_1, 6.4, units="ns").start()) - self.qsfp_1_1_sink = XgmiiSink(dut.qsfp_1_txd_1, dut.qsfp_1_txc_1, dut.qsfp_1_tx_clk_1, dut.qsfp_1_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_2, 6.4, units="ns").start()) - self.qsfp_1_2_source = XgmiiSource(dut.qsfp_1_rxd_2, dut.qsfp_1_rxc_2, dut.qsfp_1_rx_clk_2, dut.qsfp_1_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_2, 6.4, units="ns").start()) - self.qsfp_1_2_sink = XgmiiSink(dut.qsfp_1_txd_2, dut.qsfp_1_txc_2, dut.qsfp_1_tx_clk_2, dut.qsfp_1_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_3, 6.4, units="ns").start()) - self.qsfp_1_3_source = XgmiiSource(dut.qsfp_1_rxd_3, dut.qsfp_1_rxc_3, dut.qsfp_1_rx_clk_3, dut.qsfp_1_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_3, 6.4, units="ns").start()) - self.qsfp_1_3_sink = XgmiiSink(dut.qsfp_1_txd_3, dut.qsfp_1_txc_3, dut.qsfp_1_tx_clk_3, dut.qsfp_1_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_4, 6.4, units="ns").start()) - self.qsfp_1_4_source = XgmiiSource(dut.qsfp_1_rxd_4, dut.qsfp_1_rxc_4, dut.qsfp_1_rx_clk_4, dut.qsfp_1_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_4, 6.4, units="ns").start()) - self.qsfp_1_4_sink = XgmiiSink(dut.qsfp_1_txd_4, dut.qsfp_1_txc_4, dut.qsfp_1_tx_clk_4, dut.qsfp_1_tx_rst_4) - - cocotb.start_soon(Clock(dut.qsfp_2_rx_clk_1, 6.4, units="ns").start()) - self.qsfp_2_1_source = XgmiiSource(dut.qsfp_2_rxd_1, dut.qsfp_2_rxc_1, dut.qsfp_2_rx_clk_1, dut.qsfp_2_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp_2_tx_clk_1, 6.4, units="ns").start()) - self.qsfp_2_1_sink = XgmiiSink(dut.qsfp_2_txd_1, dut.qsfp_2_txc_1, dut.qsfp_2_tx_clk_1, dut.qsfp_2_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp_2_rx_clk_2, 6.4, units="ns").start()) - self.qsfp_2_2_source = XgmiiSource(dut.qsfp_2_rxd_2, dut.qsfp_2_rxc_2, dut.qsfp_2_rx_clk_2, dut.qsfp_2_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp_2_tx_clk_2, 6.4, units="ns").start()) - self.qsfp_2_2_sink = XgmiiSink(dut.qsfp_2_txd_2, dut.qsfp_2_txc_2, dut.qsfp_2_tx_clk_2, dut.qsfp_2_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp_2_rx_clk_3, 6.4, units="ns").start()) - self.qsfp_2_3_source = XgmiiSource(dut.qsfp_2_rxd_3, dut.qsfp_2_rxc_3, dut.qsfp_2_rx_clk_3, dut.qsfp_2_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp_2_tx_clk_3, 6.4, units="ns").start()) - self.qsfp_2_3_sink = XgmiiSink(dut.qsfp_2_txd_3, dut.qsfp_2_txc_3, dut.qsfp_2_tx_clk_3, dut.qsfp_2_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp_2_rx_clk_4, 6.4, units="ns").start()) - self.qsfp_2_4_source = XgmiiSource(dut.qsfp_2_rxd_4, dut.qsfp_2_rxc_4, dut.qsfp_2_rx_clk_4, dut.qsfp_2_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp_2_tx_clk_4, 6.4, units="ns").start()) - self.qsfp_2_4_sink = XgmiiSink(dut.qsfp_2_txd_4, dut.qsfp_2_txc_4, dut.qsfp_2_tx_clk_4, dut.qsfp_2_tx_rst_4) - - cocotb.start_soon(Clock(dut.qsfp_3_rx_clk_1, 6.4, units="ns").start()) - self.qsfp_3_1_source = XgmiiSource(dut.qsfp_3_rxd_1, dut.qsfp_3_rxc_1, dut.qsfp_3_rx_clk_1, dut.qsfp_3_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp_3_tx_clk_1, 6.4, units="ns").start()) - self.qsfp_3_1_sink = XgmiiSink(dut.qsfp_3_txd_1, dut.qsfp_3_txc_1, dut.qsfp_3_tx_clk_1, dut.qsfp_3_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp_3_rx_clk_2, 6.4, units="ns").start()) - self.qsfp_3_2_source = XgmiiSource(dut.qsfp_3_rxd_2, dut.qsfp_3_rxc_2, dut.qsfp_3_rx_clk_2, dut.qsfp_3_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp_3_tx_clk_2, 6.4, units="ns").start()) - self.qsfp_3_2_sink = XgmiiSink(dut.qsfp_3_txd_2, dut.qsfp_3_txc_2, dut.qsfp_3_tx_clk_2, dut.qsfp_3_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp_3_rx_clk_3, 6.4, units="ns").start()) - self.qsfp_3_3_source = XgmiiSource(dut.qsfp_3_rxd_3, dut.qsfp_3_rxc_3, dut.qsfp_3_rx_clk_3, dut.qsfp_3_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp_3_tx_clk_3, 6.4, units="ns").start()) - self.qsfp_3_3_sink = XgmiiSink(dut.qsfp_3_txd_3, dut.qsfp_3_txc_3, dut.qsfp_3_tx_clk_3, dut.qsfp_3_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp_3_rx_clk_4, 6.4, units="ns").start()) - self.qsfp_3_4_source = XgmiiSource(dut.qsfp_3_rxd_4, dut.qsfp_3_rxc_4, dut.qsfp_3_rx_clk_4, dut.qsfp_3_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp_3_tx_clk_4, 6.4, units="ns").start()) - self.qsfp_3_4_sink = XgmiiSink(dut.qsfp_3_txd_4, dut.qsfp_3_txc_4, dut.qsfp_3_tx_clk_4, dut.qsfp_3_tx_rst_4) - - cocotb.start_soon(Clock(dut.qsfp_4_rx_clk_1, 6.4, units="ns").start()) - self.qsfp_4_1_source = XgmiiSource(dut.qsfp_4_rxd_1, dut.qsfp_4_rxc_1, dut.qsfp_4_rx_clk_1, dut.qsfp_4_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp_4_tx_clk_1, 6.4, units="ns").start()) - self.qsfp_4_1_sink = XgmiiSink(dut.qsfp_4_txd_1, dut.qsfp_4_txc_1, dut.qsfp_4_tx_clk_1, dut.qsfp_4_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp_4_rx_clk_2, 6.4, units="ns").start()) - self.qsfp_4_2_source = XgmiiSource(dut.qsfp_4_rxd_2, dut.qsfp_4_rxc_2, dut.qsfp_4_rx_clk_2, dut.qsfp_4_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp_4_tx_clk_2, 6.4, units="ns").start()) - self.qsfp_4_2_sink = XgmiiSink(dut.qsfp_4_txd_2, dut.qsfp_4_txc_2, dut.qsfp_4_tx_clk_2, dut.qsfp_4_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp_4_rx_clk_3, 6.4, units="ns").start()) - self.qsfp_4_3_source = XgmiiSource(dut.qsfp_4_rxd_3, dut.qsfp_4_rxc_3, dut.qsfp_4_rx_clk_3, dut.qsfp_4_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp_4_tx_clk_3, 6.4, units="ns").start()) - self.qsfp_4_3_sink = XgmiiSink(dut.qsfp_4_txd_3, dut.qsfp_4_txc_3, dut.qsfp_4_tx_clk_3, dut.qsfp_4_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp_4_rx_clk_4, 6.4, units="ns").start()) - self.qsfp_4_4_source = XgmiiSource(dut.qsfp_4_rxd_4, dut.qsfp_4_rxc_4, dut.qsfp_4_rx_clk_4, dut.qsfp_4_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp_4_tx_clk_4, 6.4, units="ns").start()) - self.qsfp_4_4_sink = XgmiiSink(dut.qsfp_4_txd_4, dut.qsfp_4_txc_4, dut.qsfp_4_tx_clk_4, dut.qsfp_4_tx_rst_4) - - cocotb.start_soon(Clock(dut.qsfp_5_rx_clk_1, 6.4, units="ns").start()) - self.qsfp_5_1_source = XgmiiSource(dut.qsfp_5_rxd_1, dut.qsfp_5_rxc_1, dut.qsfp_5_rx_clk_1, dut.qsfp_5_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp_5_tx_clk_1, 6.4, units="ns").start()) - self.qsfp_5_1_sink = XgmiiSink(dut.qsfp_5_txd_1, dut.qsfp_5_txc_1, dut.qsfp_5_tx_clk_1, dut.qsfp_5_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp_5_rx_clk_2, 6.4, units="ns").start()) - self.qsfp_5_2_source = XgmiiSource(dut.qsfp_5_rxd_2, dut.qsfp_5_rxc_2, dut.qsfp_5_rx_clk_2, dut.qsfp_5_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp_5_tx_clk_2, 6.4, units="ns").start()) - self.qsfp_5_2_sink = XgmiiSink(dut.qsfp_5_txd_2, dut.qsfp_5_txc_2, dut.qsfp_5_tx_clk_2, dut.qsfp_5_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp_5_rx_clk_3, 6.4, units="ns").start()) - self.qsfp_5_3_source = XgmiiSource(dut.qsfp_5_rxd_3, dut.qsfp_5_rxc_3, dut.qsfp_5_rx_clk_3, dut.qsfp_5_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp_5_tx_clk_3, 6.4, units="ns").start()) - self.qsfp_5_3_sink = XgmiiSink(dut.qsfp_5_txd_3, dut.qsfp_5_txc_3, dut.qsfp_5_tx_clk_3, dut.qsfp_5_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp_5_rx_clk_4, 6.4, units="ns").start()) - self.qsfp_5_4_source = XgmiiSource(dut.qsfp_5_rxd_4, dut.qsfp_5_rxc_4, dut.qsfp_5_rx_clk_4, dut.qsfp_5_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp_5_tx_clk_4, 6.4, units="ns").start()) - self.qsfp_5_4_sink = XgmiiSink(dut.qsfp_5_txd_4, dut.qsfp_5_txc_4, dut.qsfp_5_tx_clk_4, dut.qsfp_5_tx_rst_4) - - cocotb.start_soon(Clock(dut.qsfp_6_rx_clk_1, 6.4, units="ns").start()) - self.qsfp_6_1_source = XgmiiSource(dut.qsfp_6_rxd_1, dut.qsfp_6_rxc_1, dut.qsfp_6_rx_clk_1, dut.qsfp_6_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp_6_tx_clk_1, 6.4, units="ns").start()) - self.qsfp_6_1_sink = XgmiiSink(dut.qsfp_6_txd_1, dut.qsfp_6_txc_1, dut.qsfp_6_tx_clk_1, dut.qsfp_6_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp_6_rx_clk_2, 6.4, units="ns").start()) - self.qsfp_6_2_source = XgmiiSource(dut.qsfp_6_rxd_2, dut.qsfp_6_rxc_2, dut.qsfp_6_rx_clk_2, dut.qsfp_6_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp_6_tx_clk_2, 6.4, units="ns").start()) - self.qsfp_6_2_sink = XgmiiSink(dut.qsfp_6_txd_2, dut.qsfp_6_txc_2, dut.qsfp_6_tx_clk_2, dut.qsfp_6_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp_6_rx_clk_3, 6.4, units="ns").start()) - self.qsfp_6_3_source = XgmiiSource(dut.qsfp_6_rxd_3, dut.qsfp_6_rxc_3, dut.qsfp_6_rx_clk_3, dut.qsfp_6_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp_6_tx_clk_3, 6.4, units="ns").start()) - self.qsfp_6_3_sink = XgmiiSink(dut.qsfp_6_txd_3, dut.qsfp_6_txc_3, dut.qsfp_6_tx_clk_3, dut.qsfp_6_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp_6_rx_clk_4, 6.4, units="ns").start()) - self.qsfp_6_4_source = XgmiiSource(dut.qsfp_6_rxd_4, dut.qsfp_6_rxc_4, dut.qsfp_6_rx_clk_4, dut.qsfp_6_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp_6_tx_clk_4, 6.4, units="ns").start()) - self.qsfp_6_4_sink = XgmiiSink(dut.qsfp_6_txd_4, dut.qsfp_6_txc_4, dut.qsfp_6_tx_clk_4, dut.qsfp_6_tx_rst_4) - - cocotb.start_soon(Clock(dut.qsfp_7_rx_clk_1, 6.4, units="ns").start()) - self.qsfp_7_1_source = XgmiiSource(dut.qsfp_7_rxd_1, dut.qsfp_7_rxc_1, dut.qsfp_7_rx_clk_1, dut.qsfp_7_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp_7_tx_clk_1, 6.4, units="ns").start()) - self.qsfp_7_1_sink = XgmiiSink(dut.qsfp_7_txd_1, dut.qsfp_7_txc_1, dut.qsfp_7_tx_clk_1, dut.qsfp_7_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp_7_rx_clk_2, 6.4, units="ns").start()) - self.qsfp_7_2_source = XgmiiSource(dut.qsfp_7_rxd_2, dut.qsfp_7_rxc_2, dut.qsfp_7_rx_clk_2, dut.qsfp_7_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp_7_tx_clk_2, 6.4, units="ns").start()) - self.qsfp_7_2_sink = XgmiiSink(dut.qsfp_7_txd_2, dut.qsfp_7_txc_2, dut.qsfp_7_tx_clk_2, dut.qsfp_7_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp_7_rx_clk_3, 6.4, units="ns").start()) - self.qsfp_7_3_source = XgmiiSource(dut.qsfp_7_rxd_3, dut.qsfp_7_rxc_3, dut.qsfp_7_rx_clk_3, dut.qsfp_7_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp_7_tx_clk_3, 6.4, units="ns").start()) - self.qsfp_7_3_sink = XgmiiSink(dut.qsfp_7_txd_3, dut.qsfp_7_txc_3, dut.qsfp_7_tx_clk_3, dut.qsfp_7_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp_7_rx_clk_4, 6.4, units="ns").start()) - self.qsfp_7_4_source = XgmiiSource(dut.qsfp_7_rxd_4, dut.qsfp_7_rxc_4, dut.qsfp_7_rx_clk_4, dut.qsfp_7_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp_7_tx_clk_4, 6.4, units="ns").start()) - self.qsfp_7_4_sink = XgmiiSink(dut.qsfp_7_txd_4, dut.qsfp_7_txc_4, dut.qsfp_7_tx_clk_4, dut.qsfp_7_tx_rst_4) - - cocotb.start_soon(Clock(dut.qsfp_8_rx_clk_1, 6.4, units="ns").start()) - self.qsfp_8_1_source = XgmiiSource(dut.qsfp_8_rxd_1, dut.qsfp_8_rxc_1, dut.qsfp_8_rx_clk_1, dut.qsfp_8_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp_8_tx_clk_1, 6.4, units="ns").start()) - self.qsfp_8_1_sink = XgmiiSink(dut.qsfp_8_txd_1, dut.qsfp_8_txc_1, dut.qsfp_8_tx_clk_1, dut.qsfp_8_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp_8_rx_clk_2, 6.4, units="ns").start()) - self.qsfp_8_2_source = XgmiiSource(dut.qsfp_8_rxd_2, dut.qsfp_8_rxc_2, dut.qsfp_8_rx_clk_2, dut.qsfp_8_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp_8_tx_clk_2, 6.4, units="ns").start()) - self.qsfp_8_2_sink = XgmiiSink(dut.qsfp_8_txd_2, dut.qsfp_8_txc_2, dut.qsfp_8_tx_clk_2, dut.qsfp_8_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp_8_rx_clk_3, 6.4, units="ns").start()) - self.qsfp_8_3_source = XgmiiSource(dut.qsfp_8_rxd_3, dut.qsfp_8_rxc_3, dut.qsfp_8_rx_clk_3, dut.qsfp_8_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp_8_tx_clk_3, 6.4, units="ns").start()) - self.qsfp_8_3_sink = XgmiiSink(dut.qsfp_8_txd_3, dut.qsfp_8_txc_3, dut.qsfp_8_tx_clk_3, dut.qsfp_8_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp_8_rx_clk_4, 6.4, units="ns").start()) - self.qsfp_8_4_source = XgmiiSource(dut.qsfp_8_rxd_4, dut.qsfp_8_rxc_4, dut.qsfp_8_rx_clk_4, dut.qsfp_8_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp_8_tx_clk_4, 6.4, units="ns").start()) - self.qsfp_8_4_sink = XgmiiSink(dut.qsfp_8_txd_4, dut.qsfp_8_txc_4, dut.qsfp_8_tx_clk_4, dut.qsfp_8_tx_rst_4) - - cocotb.start_soon(Clock(dut.qsfp_9_rx_clk_1, 6.4, units="ns").start()) - self.qsfp_9_1_source = XgmiiSource(dut.qsfp_9_rxd_1, dut.qsfp_9_rxc_1, dut.qsfp_9_rx_clk_1, dut.qsfp_9_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp_9_tx_clk_1, 6.4, units="ns").start()) - self.qsfp_9_1_sink = XgmiiSink(dut.qsfp_9_txd_1, dut.qsfp_9_txc_1, dut.qsfp_9_tx_clk_1, dut.qsfp_9_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp_9_rx_clk_2, 6.4, units="ns").start()) - self.qsfp_9_2_source = XgmiiSource(dut.qsfp_9_rxd_2, dut.qsfp_9_rxc_2, dut.qsfp_9_rx_clk_2, dut.qsfp_9_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp_9_tx_clk_2, 6.4, units="ns").start()) - self.qsfp_9_2_sink = XgmiiSink(dut.qsfp_9_txd_2, dut.qsfp_9_txc_2, dut.qsfp_9_tx_clk_2, dut.qsfp_9_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp_9_rx_clk_3, 6.4, units="ns").start()) - self.qsfp_9_3_source = XgmiiSource(dut.qsfp_9_rxd_3, dut.qsfp_9_rxc_3, dut.qsfp_9_rx_clk_3, dut.qsfp_9_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp_9_tx_clk_3, 6.4, units="ns").start()) - self.qsfp_9_3_sink = XgmiiSink(dut.qsfp_9_txd_3, dut.qsfp_9_txc_3, dut.qsfp_9_tx_clk_3, dut.qsfp_9_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp_9_rx_clk_4, 6.4, units="ns").start()) - self.qsfp_9_4_source = XgmiiSource(dut.qsfp_9_rxd_4, dut.qsfp_9_rxc_4, dut.qsfp_9_rx_clk_4, dut.qsfp_9_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp_9_tx_clk_4, 6.4, units="ns").start()) - self.qsfp_9_4_sink = XgmiiSink(dut.qsfp_9_txd_4, dut.qsfp_9_txc_4, dut.qsfp_9_tx_clk_4, dut.qsfp_9_tx_rst_4) - - async def init(self): - - self.dut.rst.setimmediatevalue(0) - self.dut.qsfp_1_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp_1_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp_1_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp_1_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp_1_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp_1_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp_1_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp_1_tx_rst_4.setimmediatevalue(0) - self.dut.qsfp_2_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp_2_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp_2_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp_2_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp_2_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp_2_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp_2_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp_2_tx_rst_4.setimmediatevalue(0) - self.dut.qsfp_3_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp_3_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp_3_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp_3_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp_3_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp_3_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp_3_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp_3_tx_rst_4.setimmediatevalue(0) - self.dut.qsfp_4_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp_4_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp_4_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp_4_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp_4_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp_4_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp_4_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp_4_tx_rst_4.setimmediatevalue(0) - self.dut.qsfp_5_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp_5_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp_5_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp_5_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp_5_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp_5_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp_5_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp_5_tx_rst_4.setimmediatevalue(0) - self.dut.qsfp_6_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp_6_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp_6_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp_6_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp_6_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp_6_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp_6_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp_6_tx_rst_4.setimmediatevalue(0) - self.dut.qsfp_7_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp_7_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp_7_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp_7_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp_7_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp_7_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp_7_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp_7_tx_rst_4.setimmediatevalue(0) - self.dut.qsfp_8_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp_8_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp_8_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp_8_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp_8_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp_8_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp_8_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp_8_tx_rst_4.setimmediatevalue(0) - self.dut.qsfp_9_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp_9_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp_9_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp_9_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp_9_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp_9_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp_9_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp_9_tx_rst_4.setimmediatevalue(0) - - for k in range(10): - await RisingEdge(self.dut.clk) - - self.dut.rst.value = 1 - self.dut.qsfp_1_rx_rst_1.value = 1 - self.dut.qsfp_1_tx_rst_1.value = 1 - self.dut.qsfp_1_rx_rst_2.value = 1 - self.dut.qsfp_1_tx_rst_2.value = 1 - self.dut.qsfp_1_rx_rst_3.value = 1 - self.dut.qsfp_1_tx_rst_3.value = 1 - self.dut.qsfp_1_rx_rst_4.value = 1 - self.dut.qsfp_1_tx_rst_4.value = 1 - self.dut.qsfp_2_rx_rst_1.value = 1 - self.dut.qsfp_2_tx_rst_1.value = 1 - self.dut.qsfp_2_rx_rst_2.value = 1 - self.dut.qsfp_2_tx_rst_2.value = 1 - self.dut.qsfp_2_rx_rst_3.value = 1 - self.dut.qsfp_2_tx_rst_3.value = 1 - self.dut.qsfp_2_rx_rst_4.value = 1 - self.dut.qsfp_2_tx_rst_4.value = 1 - self.dut.qsfp_3_rx_rst_1.value = 1 - self.dut.qsfp_3_tx_rst_1.value = 1 - self.dut.qsfp_3_rx_rst_2.value = 1 - self.dut.qsfp_3_tx_rst_2.value = 1 - self.dut.qsfp_3_rx_rst_3.value = 1 - self.dut.qsfp_3_tx_rst_3.value = 1 - self.dut.qsfp_3_rx_rst_4.value = 1 - self.dut.qsfp_3_tx_rst_4.value = 1 - self.dut.qsfp_4_rx_rst_1.value = 1 - self.dut.qsfp_4_tx_rst_1.value = 1 - self.dut.qsfp_4_rx_rst_2.value = 1 - self.dut.qsfp_4_tx_rst_2.value = 1 - self.dut.qsfp_4_rx_rst_3.value = 1 - self.dut.qsfp_4_tx_rst_3.value = 1 - self.dut.qsfp_4_rx_rst_4.value = 1 - self.dut.qsfp_4_tx_rst_4.value = 1 - self.dut.qsfp_5_rx_rst_1.value = 1 - self.dut.qsfp_5_tx_rst_1.value = 1 - self.dut.qsfp_5_rx_rst_2.value = 1 - self.dut.qsfp_5_tx_rst_2.value = 1 - self.dut.qsfp_5_rx_rst_3.value = 1 - self.dut.qsfp_5_tx_rst_3.value = 1 - self.dut.qsfp_5_rx_rst_4.value = 1 - self.dut.qsfp_5_tx_rst_4.value = 1 - self.dut.qsfp_6_rx_rst_1.value = 1 - self.dut.qsfp_6_tx_rst_1.value = 1 - self.dut.qsfp_6_rx_rst_2.value = 1 - self.dut.qsfp_6_tx_rst_2.value = 1 - self.dut.qsfp_6_rx_rst_3.value = 1 - self.dut.qsfp_6_tx_rst_3.value = 1 - self.dut.qsfp_6_rx_rst_4.value = 1 - self.dut.qsfp_6_tx_rst_4.value = 1 - self.dut.qsfp_7_rx_rst_1.value = 1 - self.dut.qsfp_7_tx_rst_1.value = 1 - self.dut.qsfp_7_rx_rst_2.value = 1 - self.dut.qsfp_7_tx_rst_2.value = 1 - self.dut.qsfp_7_rx_rst_3.value = 1 - self.dut.qsfp_7_tx_rst_3.value = 1 - self.dut.qsfp_7_rx_rst_4.value = 1 - self.dut.qsfp_7_tx_rst_4.value = 1 - self.dut.qsfp_8_rx_rst_1.value = 1 - self.dut.qsfp_8_tx_rst_1.value = 1 - self.dut.qsfp_8_rx_rst_2.value = 1 - self.dut.qsfp_8_tx_rst_2.value = 1 - self.dut.qsfp_8_rx_rst_3.value = 1 - self.dut.qsfp_8_tx_rst_3.value = 1 - self.dut.qsfp_8_rx_rst_4.value = 1 - self.dut.qsfp_8_tx_rst_4.value = 1 - self.dut.qsfp_9_rx_rst_1.value = 1 - self.dut.qsfp_9_tx_rst_1.value = 1 - self.dut.qsfp_9_rx_rst_2.value = 1 - self.dut.qsfp_9_tx_rst_2.value = 1 - self.dut.qsfp_9_rx_rst_3.value = 1 - self.dut.qsfp_9_tx_rst_3.value = 1 - self.dut.qsfp_9_rx_rst_4.value = 1 - self.dut.qsfp_9_tx_rst_4.value = 1 - - for k in range(10): - await RisingEdge(self.dut.clk) - - self.dut.rst.value = 0 - self.dut.qsfp_1_rx_rst_1.value = 0 - self.dut.qsfp_1_tx_rst_1.value = 0 - self.dut.qsfp_1_rx_rst_2.value = 0 - self.dut.qsfp_1_tx_rst_2.value = 0 - self.dut.qsfp_1_rx_rst_3.value = 0 - self.dut.qsfp_1_tx_rst_3.value = 0 - self.dut.qsfp_1_rx_rst_4.value = 0 - self.dut.qsfp_1_tx_rst_4.value = 0 - self.dut.qsfp_2_rx_rst_1.value = 0 - self.dut.qsfp_2_tx_rst_1.value = 0 - self.dut.qsfp_2_rx_rst_2.value = 0 - self.dut.qsfp_2_tx_rst_2.value = 0 - self.dut.qsfp_2_rx_rst_3.value = 0 - self.dut.qsfp_2_tx_rst_3.value = 0 - self.dut.qsfp_2_rx_rst_4.value = 0 - self.dut.qsfp_2_tx_rst_4.value = 0 - self.dut.qsfp_3_rx_rst_1.value = 0 - self.dut.qsfp_3_tx_rst_1.value = 0 - self.dut.qsfp_3_rx_rst_2.value = 0 - self.dut.qsfp_3_tx_rst_2.value = 0 - self.dut.qsfp_3_rx_rst_3.value = 0 - self.dut.qsfp_3_tx_rst_3.value = 0 - self.dut.qsfp_3_rx_rst_4.value = 0 - self.dut.qsfp_3_tx_rst_4.value = 0 - self.dut.qsfp_4_rx_rst_1.value = 0 - self.dut.qsfp_4_tx_rst_1.value = 0 - self.dut.qsfp_4_rx_rst_2.value = 0 - self.dut.qsfp_4_tx_rst_2.value = 0 - self.dut.qsfp_4_rx_rst_3.value = 0 - self.dut.qsfp_4_tx_rst_3.value = 0 - self.dut.qsfp_4_rx_rst_4.value = 0 - self.dut.qsfp_4_tx_rst_4.value = 0 - self.dut.qsfp_5_rx_rst_1.value = 0 - self.dut.qsfp_5_tx_rst_1.value = 0 - self.dut.qsfp_5_rx_rst_2.value = 0 - self.dut.qsfp_5_tx_rst_2.value = 0 - self.dut.qsfp_5_rx_rst_3.value = 0 - self.dut.qsfp_5_tx_rst_3.value = 0 - self.dut.qsfp_5_rx_rst_4.value = 0 - self.dut.qsfp_5_tx_rst_4.value = 0 - self.dut.qsfp_6_rx_rst_1.value = 0 - self.dut.qsfp_6_tx_rst_1.value = 0 - self.dut.qsfp_6_rx_rst_2.value = 0 - self.dut.qsfp_6_tx_rst_2.value = 0 - self.dut.qsfp_6_rx_rst_3.value = 0 - self.dut.qsfp_6_tx_rst_3.value = 0 - self.dut.qsfp_6_rx_rst_4.value = 0 - self.dut.qsfp_6_tx_rst_4.value = 0 - self.dut.qsfp_7_rx_rst_1.value = 0 - self.dut.qsfp_7_tx_rst_1.value = 0 - self.dut.qsfp_7_rx_rst_2.value = 0 - self.dut.qsfp_7_tx_rst_2.value = 0 - self.dut.qsfp_7_rx_rst_3.value = 0 - self.dut.qsfp_7_tx_rst_3.value = 0 - self.dut.qsfp_7_rx_rst_4.value = 0 - self.dut.qsfp_7_tx_rst_4.value = 0 - self.dut.qsfp_8_rx_rst_1.value = 0 - self.dut.qsfp_8_tx_rst_1.value = 0 - self.dut.qsfp_8_rx_rst_2.value = 0 - self.dut.qsfp_8_tx_rst_2.value = 0 - self.dut.qsfp_8_rx_rst_3.value = 0 - self.dut.qsfp_8_tx_rst_3.value = 0 - self.dut.qsfp_8_rx_rst_4.value = 0 - self.dut.qsfp_8_tx_rst_4.value = 0 - self.dut.qsfp_9_rx_rst_1.value = 0 - self.dut.qsfp_9_tx_rst_1.value = 0 - self.dut.qsfp_9_rx_rst_2.value = 0 - self.dut.qsfp_9_tx_rst_2.value = 0 - self.dut.qsfp_9_rx_rst_3.value = 0 - self.dut.qsfp_9_tx_rst_3.value = 0 - self.dut.qsfp_9_rx_rst_4.value = 0 - self.dut.qsfp_9_tx_rst_4.value = 0 - - -@cocotb.test() -async def run_test(dut): - - tb = TB(dut) - - await tb.init() - - tb.log.info("test UDP RX packet") - - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00') - ip = IP(src='192.168.1.100', dst='192.168.1.128') - udp = UDP(sport=5678, dport=1234) - test_pkt = eth / ip / udp / payload - - test_frame = XgmiiFrame.from_payload(test_pkt.build()) - - await tb.qsfp_1_1_source.send(test_frame) - - tb.log.info("receive ARP request") - - rx_frame = await tb.qsfp_1_1_sink.recv() - - rx_pkt = Ether(bytes(rx_frame.get_payload())) - - tb.log.info("RX packet: %s", repr(rx_pkt)) - - assert rx_pkt.dst == 'ff:ff:ff:ff:ff:ff' - assert rx_pkt.src == test_pkt.dst - assert rx_pkt[ARP].hwtype == 1 - assert rx_pkt[ARP].ptype == 0x0800 - assert rx_pkt[ARP].hwlen == 6 - assert rx_pkt[ARP].plen == 4 - assert rx_pkt[ARP].op == 1 - assert rx_pkt[ARP].hwsrc == test_pkt.dst - assert rx_pkt[ARP].psrc == test_pkt[IP].dst - assert rx_pkt[ARP].hwdst == '00:00:00:00:00:00' - assert rx_pkt[ARP].pdst == test_pkt[IP].src - - tb.log.info("send ARP response") - - eth = Ether(src=test_pkt.src, dst=test_pkt.dst) - arp = ARP(hwtype=1, ptype=0x0800, hwlen=6, plen=4, op=2, - hwsrc=test_pkt.src, psrc=test_pkt[IP].src, - hwdst=test_pkt.dst, pdst=test_pkt[IP].dst) - resp_pkt = eth / arp - - resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - - await tb.qsfp_1_1_source.send(resp_frame) - - tb.log.info("receive UDP packet") - - rx_frame = await tb.qsfp_1_1_sink.recv() - - rx_pkt = Ether(bytes(rx_frame.get_payload())) - - tb.log.info("RX packet: %s", repr(rx_pkt)) - - assert rx_pkt.dst == test_pkt.src - assert rx_pkt.src == test_pkt.dst - assert rx_pkt[IP].dst == test_pkt[IP].src - assert rx_pkt[IP].src == test_pkt[IP].dst - assert rx_pkt[UDP].dport == test_pkt[UDP].sport - assert rx_pkt[UDP].sport == test_pkt[UDP].dport - assert rx_pkt[UDP].payload == test_pkt[UDP].payload - - await RisingEdge(dut.clk) - await RisingEdge(dut.clk) - - -# cocotb-test - -tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) -axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'lib', 'axis', 'rtl')) -eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) - - -def test_fpga_core(request): - dut = "fpga_core" - module = os.path.splitext(os.path.basename(__file__))[0] - toplevel = dut - - verilog_sources = [ - os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g_fifo.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), - os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "eth_axis_rx.v"), - os.path.join(eth_rtl_dir, "eth_axis_tx.v"), - os.path.join(eth_rtl_dir, "udp_complete_64.v"), - os.path.join(eth_rtl_dir, "udp_checksum_gen_64.v"), - os.path.join(eth_rtl_dir, "udp_64.v"), - os.path.join(eth_rtl_dir, "udp_ip_rx_64.v"), - os.path.join(eth_rtl_dir, "udp_ip_tx_64.v"), - os.path.join(eth_rtl_dir, "ip_complete_64.v"), - os.path.join(eth_rtl_dir, "ip_64.v"), - os.path.join(eth_rtl_dir, "ip_eth_rx_64.v"), - os.path.join(eth_rtl_dir, "ip_eth_tx_64.v"), - os.path.join(eth_rtl_dir, "ip_arb_mux.v"), - os.path.join(eth_rtl_dir, "arp.v"), - os.path.join(eth_rtl_dir, "arp_cache.v"), - os.path.join(eth_rtl_dir, "arp_eth_rx.v"), - os.path.join(eth_rtl_dir, "arp_eth_tx.v"), - os.path.join(eth_rtl_dir, "eth_arb_mux.v"), - os.path.join(axis_rtl_dir, "arbiter.v"), - os.path.join(axis_rtl_dir, "priority_encoder.v"), - os.path.join(axis_rtl_dir, "axis_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), - ] - - parameters = {} - - # parameters['A'] = val - - extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} - - sim_build = os.path.join(tests_dir, "sim_build", - request.node.name.replace('[', '-').replace(']', '')) - - cocotb_test.simulator.run( - python_search=[tests_dir], - verilog_sources=verilog_sources, - toplevel=toplevel, - module=module, - parameters=parameters, - sim_build=sim_build, - extra_env=extra_env, - ) diff --git a/fpga/lib/eth/example/HTG9200/fpga_10g/README.md b/fpga/lib/eth/example/HTG9200/fpga_25g/README.md similarity index 100% rename from fpga/lib/eth/example/HTG9200/fpga_10g/README.md rename to fpga/lib/eth/example/HTG9200/fpga_25g/README.md diff --git a/fpga/lib/eth/example/HTG9200/fpga_25g/common/vivado.mk b/fpga/lib/eth/example/HTG9200/fpga_25g/common/vivado.mk new file mode 100644 index 000000000..1402e2382 --- /dev/null +++ b/fpga/lib/eth/example/HTG9200/fpga_25g/common/vivado.mk @@ -0,0 +1,137 @@ +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - space-separated list of source files +# INC_FILES - space-separated list of include files +# XDC_FILES - space-separated list of timing constraint files +# XCI_FILES - space-separated list of IP XCI files +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: fpga vivado tmpclean clean distclean + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include ../$(CONFIG) + +FPGA_TOP ?= fpga +PROJECT ?= $(FPGA_TOP) + +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) + +ifdef XDC_FILES + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +else + XDC_FILES_REL = $(PROJECT).xdc +endif + +################################################################### +# Main Targets +# +# all: build everything +# clean: remove output files and project files +################################################################### + +all: fpga + +fpga: $(PROJECT).bit + +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr + +tmpclean:: + -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean:: tmpclean + -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt + +distclean:: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file +create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ + echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ + echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ + echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ + for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl + vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) + +# synthesis run +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr + echo "open_project $(PROJECT).xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp + echo "open_project $(PROJECT).xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + echo "open_run impl_1" >> run_impl.tcl + echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl + echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# bit file +$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp + echo "open_project $(PROJECT).xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl + echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi + mkdir -p rev + COUNT=100; \ + while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/lib/eth/example/HTG9200/fpga_10g/fpga.xdc b/fpga/lib/eth/example/HTG9200/fpga_25g/fpga.xdc similarity index 67% rename from fpga/lib/eth/example/HTG9200/fpga_10g/fpga.xdc rename to fpga/lib/eth/example/HTG9200/fpga_25g/fpga.xdc index 12d0e5110..cca216957 100644 --- a/fpga/lib/eth/example/HTG9200/fpga_10g/fpga.xdc +++ b/fpga/lib/eth/example/HTG9200/fpga_25g/fpga.xdc @@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # System clocks # DDR4 clocks from U5 (200 MHz) @@ -30,16 +31,21 @@ create_clock -period 5.000 -name ref_clk [get_ports ref_clk_p] #create_clock -period 12.5 -name emc_clk [get_ports emc_clk] # PLL control -# set_property -dict {LOC L24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_fdec}] -# set_property -dict {LOC K25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_finc}] -# set_property -dict {LOC K23 IOSTANDARD LVCMOS18} [get_ports {clk_gty2_intr_n}] +set_property -dict {LOC L24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_fdec}] +set_property -dict {LOC K25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_finc}] +set_property -dict {LOC K23 IOSTANDARD LVCMOS18} [get_ports {clk_gty2_intr_n}] set_property -dict {LOC L25 IOSTANDARD LVCMOS18} [get_ports {clk_gty2_lol_n}] -# set_property -dict {LOC L23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_oe_n}] -# set_property -dict {LOC L22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_sync_n}] -# set_property -dict {LOC K22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_rst_n}] +set_property -dict {LOC L23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_oe_n}] +set_property -dict {LOC L22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_sync_n}] +set_property -dict {LOC K22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_rst_n}] -# set_property -dict {LOC BE20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_sd_oe}] -# set_property -dict {LOC BD20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_out0_sel_i2cb}] +#set_property -dict {LOC BE20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_sd_oe}] +#set_property -dict {LOC BD20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_out0_sel_i2cb}] + +set_false_path -to [get_ports {clk_gty2_fdec clk_gty2_finc clk_gty2_oe_n clk_gty2_sync_n clk_gty2_rst_n}] +set_output_delay 0 [get_ports {clk_gty2_fdec clk_gty2_finc clk_gty2_oe_n clk_gty2_sync_n clk_gty2_rst_n}] +set_false_path -from [get_ports {clk_gty2_intr_n clk_gty2_lol_n}] +set_input_delay 0 [get_ports {clk_gty2_intr_n clk_gty2_lol_n}] # LEDs set_property -dict {LOC BA24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}] @@ -51,10 +57,16 @@ set_property -dict {LOC BD25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports { set_property -dict {LOC BC26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[6]}] set_property -dict {LOC BC27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[7]}] +set_false_path -to [get_ports {led[*]}] +set_output_delay 0 [get_ports {led[*]}] + # Push buttons set_property -dict {LOC B31 IOSTANDARD LVCMOS12} [get_ports {btn[0]}] set_property -dict {LOC C31 IOSTANDARD LVCMOS12} [get_ports {btn[1]}] +set_false_path -from [get_ports {btn[*]}] +set_input_delay 0 [get_ports {btn[*]}] + # DIP switches set_property -dict {LOC P33 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] set_property -dict {LOC K34 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] @@ -65,15 +77,21 @@ set_property -dict {LOC D36 IOSTANDARD LVCMOS12} [get_ports {sw[5]}] set_property -dict {LOC E37 IOSTANDARD LVCMOS12} [get_ports {sw[6]}] set_property -dict {LOC F38 IOSTANDARD LVCMOS12} [get_ports {sw[7]}] +set_false_path -from [get_ports {sw[*]}] +set_input_delay 0 [get_ports {sw[*]}] + # GPIO -# set_property -dict {LOC AY25 IOSTANDARD LVCMOS18} [get_ports {gpio[0]}] -# set_property -dict {LOC AW25 IOSTANDARD LVCMOS18} [get_ports {gpio[1]}] -# set_property -dict {LOC AU26 IOSTANDARD LVCMOS18} [get_ports {gpio[2]}] -# set_property -dict {LOC BD26 IOSTANDARD LVCMOS18} [get_ports {gpio[3]}] -# set_property -dict {LOC BE27 IOSTANDARD LVCMOS18} [get_ports {gpio[4]}] -# set_property -dict {LOC BE26 IOSTANDARD LVCMOS18} [get_ports {gpio[5]}] -# set_property -dict {LOC AU25 IOSTANDARD LVCMOS18} [get_ports {gpio[6]}] -# set_property -dict {LOC AR26 IOSTANDARD LVCMOS18} [get_ports {gpio[7]}] +#set_property -dict {LOC AY25 IOSTANDARD LVCMOS18} [get_ports {gpio[0]}] +#set_property -dict {LOC AW25 IOSTANDARD LVCMOS18} [get_ports {gpio[1]}] +#set_property -dict {LOC AU26 IOSTANDARD LVCMOS18} [get_ports {gpio[2]}] +#set_property -dict {LOC BD26 IOSTANDARD LVCMOS18} [get_ports {gpio[3]}] +#set_property -dict {LOC BE27 IOSTANDARD LVCMOS18} [get_ports {gpio[4]}] +#set_property -dict {LOC BE26 IOSTANDARD LVCMOS18} [get_ports {gpio[5]}] +#set_property -dict {LOC AU25 IOSTANDARD LVCMOS18} [get_ports {gpio[6]}] +#set_property -dict {LOC AR26 IOSTANDARD LVCMOS18} [get_ports {gpio[7]}] + +#set_false_path -to [get_ports {gpio[*]}] +#set_output_delay 0 [get_ports {gpio[*]}] # UART set_property -dict {LOC BB27 IOSTANDARD LVCMOS18} [get_ports uart_txd] @@ -82,22 +100,37 @@ set_property -dict {LOC BC28 IOSTANDARD LVCMOS18} [get_ports uart_rts] set_property -dict {LOC AY28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_cts] set_property -dict {LOC AY26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rst_n] set_property -dict {LOC BB26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_suspend_n] -# set_property -dict {LOC AW28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[0]}] -# set_property -dict {LOC AV28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[1]}] -# set_property -dict {LOC AV27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[2]}] -# set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[3]}] +#set_property -dict {LOC AW28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[0]}] +#set_property -dict {LOC AV28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[1]}] +#set_property -dict {LOC AV27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[2]}] +#set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[3]}] + +set_false_path -to [get_ports {uart_rxd uart_cts uart_rst_n uart_suspend_n}] +set_output_delay 0 [get_ports {uart_rxd uart_cts uart_rst_n uart_suspend_n}] +set_false_path -from [get_ports {uart_txd uart_rts}] +set_input_delay 0 [get_ports {uart_txd uart_rts}] # I2C set_property -dict {LOC BB21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_scl] set_property -dict {LOC BC21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_sda] set_property -dict {LOC BF20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_rst_n] +set_false_path -to [get_ports {i2c_main_sda i2c_main_scl i2c_main_rst_n}] +set_output_delay 0 [get_ports {i2c_main_sda i2c_main_scl i2c_main_rst_n}] +set_false_path -from [get_ports {i2c_main_sda i2c_main_scl}] +set_input_delay 0 [get_ports {i2c_main_sda i2c_main_scl}] + # QSPI flash -# set_property -dict {LOC AM26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[0]}] -# set_property -dict {LOC AN26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[1]}] -# set_property -dict {LOC AL25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[2]}] -# set_property -dict {LOC AM25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[3]}] -# set_property -dict {LOC BF27 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_cs_n}] +#set_property -dict {LOC AM26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[0]}] +#set_property -dict {LOC AN26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[1]}] +#set_property -dict {LOC AL25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[2]}] +#set_property -dict {LOC AM25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[3]}] +#set_property -dict {LOC BF27 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_cs_n}] + +#set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}] +#set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}] +#set_false_path -from [get_ports {qspi_1_dq}] +#set_input_delay 0 [get_ports {qspi_1_dq}] # DDR4 A # set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[0]}] @@ -731,346 +764,325 @@ create_clock -period 6.206 -name qsfp_9_mgt_refclk [get_ports qsfp_9_mgt_refclk_ # 161.1328125 MHz MGT reference clock #create_clock -period 6.206 -name ff_mgt_refclk [get_ports ff_mgt_refclk_p] -# FMC+ -# set_property -dict {LOC BA15 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[0]}] ;# CC -# set_property -dict {LOC BA14 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[0]}] ;# CC -# set_property -dict {LOC AY13 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[1]}] ;# CC -# set_property -dict {LOC BA13 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[1]}] ;# CC -# set_property -dict {LOC AL15 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[2]}] -# set_property -dict {LOC AM15 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[2]}] -# set_property -dict {LOC AN14 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[3]}] -# set_property -dict {LOC AN13 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[3]}] -# set_property -dict {LOC AL14 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[4]}] -# set_property -dict {LOC AM14 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[4]}] -# set_property -dict {LOC AP13 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[5]}] -# set_property -dict {LOC AR13 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[5]}] -# set_property -dict {LOC AP15 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[6]}] -# set_property -dict {LOC AP14 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[6]}] -# set_property -dict {LOC AU16 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[7]}] -# set_property -dict {LOC AV16 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[7]}] -# set_property -dict {LOC AR16 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[8]}] -# set_property -dict {LOC AR15 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[8]}] -# set_property -dict {LOC AT15 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[9]}] -# set_property -dict {LOC AU15 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[9]}] -# set_property -dict {LOC AU14 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[10]}] -# set_property -dict {LOC AV14 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[10]}] -# set_property -dict {LOC BD15 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[11]}] -# set_property -dict {LOC BD14 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[11]}] -# set_property -dict {LOC AY12 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[12]}] -# set_property -dict {LOC AY11 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[12]}] -# set_property -dict {LOC BA12 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[13]}] -# set_property -dict {LOC BB12 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[13]}] -# set_property -dict {LOC BB15 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[14]}] -# set_property -dict {LOC BB14 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[14]}] -# set_property -dict {LOC BF14 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[15]}] -# set_property -dict {LOC BF13 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[15]}] -# set_property -dict {LOC BD16 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[16]}] -# set_property -dict {LOC BE16 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[16]}] -# set_property -dict {LOC AT20 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[17]}] ;# CC -# set_property -dict {LOC AU20 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[17]}] ;# CC -# set_property -dict {LOC AV19 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[18]}] ;# CC -# set_property -dict {LOC AW19 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[18]}] ;# CC -# set_property -dict {LOC AR17 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[19]}] -# set_property -dict {LOC AT17 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[19]}] -# set_property -dict {LOC AN18 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[20]}] -# set_property -dict {LOC AN17 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[20]}] -# set_property -dict {LOC AW20 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[21]}] -# set_property -dict {LOC AY20 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[21]}] -# set_property -dict {LOC AT19 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[22]}] -# set_property -dict {LOC AU19 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[22]}] -# set_property -dict {LOC AL17 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[23]}] -# set_property -dict {LOC AM17 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[23]}] -# set_property -dict {LOC AY17 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[24]}] -# set_property -dict {LOC BA17 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[24]}] -# set_property -dict {LOC AY18 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[25]}] -# set_property -dict {LOC BA18 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[25]}] -# set_property -dict {LOC AP20 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[26]}] -# set_property -dict {LOC AP20 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[26]}] -# set_property -dict {LOC AN19 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[27]}] -# set_property -dict {LOC AP19 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[27]}] -# set_property -dict {LOC BB17 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[28]}] -# set_property -dict {LOC BC17 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[28]}] -# set_property -dict {LOC BB19 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[29]}] -# set_property -dict {LOC BC18 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[29]}] -# set_property -dict {LOC BD18 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[30]}] -# set_property -dict {LOC BE18 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[30]}] -# set_property -dict {LOC BC19 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[31]}] -# set_property -dict {LOC BD19 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[31]}] -# set_property -dict {LOC BF19 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[32]}] -# set_property -dict {LOC BF18 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[32]}] -# set_property -dict {LOC BE17 IOSTANDARD LVCMOS18} [get_ports {fmc_la_p[33]}] -# set_property -dict {LOC BF17 IOSTANDARD LVCMOS18} [get_ports {fmc_la_n[33]}] +# FMC+ J9 +#set_property -dict {LOC BA15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[0]}] ;# J9.G9 LA00_P_CC +#set_property -dict {LOC BA14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[0]}] ;# J9.G10 LA00_N_CC +#set_property -dict {LOC AY13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[1]}] ;# J9.D8 LA01_P_CC +#set_property -dict {LOC BA13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[1]}] ;# J9.D9 LA01_N_CC +#set_property -dict {LOC AL15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[2]}] ;# J9.H7 LA02_P +#set_property -dict {LOC AM15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[2]}] ;# J9.H8 LA02_N +#set_property -dict {LOC AN14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[3]}] ;# J9.G12 LA03_P +#set_property -dict {LOC AN13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[3]}] ;# J9.G13 LA03_N +#set_property -dict {LOC AL14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[4]}] ;# J9.H10 LA04_P +#set_property -dict {LOC AM14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[4]}] ;# J9.H11 LA04_N +#set_property -dict {LOC AP13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[5]}] ;# J9.D11 LA05_P +#set_property -dict {LOC AR13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[5]}] ;# J9.D12 LA05_N +#set_property -dict {LOC AP15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[6]}] ;# J9.C10 LA06_P +#set_property -dict {LOC AP14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[6]}] ;# J9.C11 LA06_N +#set_property -dict {LOC AU16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[7]}] ;# J9.H13 LA07_P +#set_property -dict {LOC AV16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[7]}] ;# J9.H14 LA07_N +#set_property -dict {LOC AR16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[8]}] ;# J9.G12 LA08_P +#set_property -dict {LOC AR15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[8]}] ;# J9.G13 LA08_N +#set_property -dict {LOC AT15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[9]}] ;# J9.D14 LA09_P +#set_property -dict {LOC AU15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[9]}] ;# J9.D15 LA09_N +#set_property -dict {LOC AU14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[10]}] ;# J9.C14 LA10_P +#set_property -dict {LOC AV14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[10]}] ;# J9.C15 LA10_N +#set_property -dict {LOC BD15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[11]}] ;# J9.H16 LA11_P +#set_property -dict {LOC BD14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[11]}] ;# J9.H17 LA11_N +#set_property -dict {LOC AY12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[12]}] ;# J9.G15 LA12_P +#set_property -dict {LOC AY11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[12]}] ;# J9.G16 LA12_N +#set_property -dict {LOC BA12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[13]}] ;# J9.D17 LA13_P +#set_property -dict {LOC BB12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[13]}] ;# J9.D18 LA13_N +#set_property -dict {LOC BB15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[14]}] ;# J9.C18 LA14_P +#set_property -dict {LOC BB14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[14]}] ;# J9.C19 LA14_N +#set_property -dict {LOC BF14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[15]}] ;# J9.H19 LA15_P +#set_property -dict {LOC BF13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[15]}] ;# J9.H20 LA15_N +#set_property -dict {LOC BD16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[16]}] ;# J9.G18 LA16_P +#set_property -dict {LOC BE16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[16]}] ;# J9.G19 LA16_N +#set_property -dict {LOC AT20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[17]}] ;# J9.D20 LA17_P_CC +#set_property -dict {LOC AU20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[17]}] ;# J9.D21 LA17_N_CC +#set_property -dict {LOC AV19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[18]}] ;# J9.C22 LA18_P_CC +#set_property -dict {LOC AW19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[18]}] ;# J9.C23 LA18_N_CC +#set_property -dict {LOC AR17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[19]}] ;# J9.H22 LA19_P +#set_property -dict {LOC AT17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[19]}] ;# J9.H23 LA19_N +#set_property -dict {LOC AN18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[20]}] ;# J9.G21 LA20_P +#set_property -dict {LOC AN17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[20]}] ;# J9.G22 LA20_N +#set_property -dict {LOC AW20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[21]}] ;# J9.H25 LA21_P +#set_property -dict {LOC AY20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[21]}] ;# J9.H26 LA21_N +#set_property -dict {LOC AT19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[22]}] ;# J9.G24 LA22_P +#set_property -dict {LOC AU19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[22]}] ;# J9.G25 LA22_N +#set_property -dict {LOC AL17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[23]}] ;# J9.D23 LA23_P +#set_property -dict {LOC AM17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[23]}] ;# J9.D24 LA23_N +#set_property -dict {LOC AY17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[24]}] ;# J9.H28 LA24_P +#set_property -dict {LOC BA17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[24]}] ;# J9.H29 LA24_N +#set_property -dict {LOC AY18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[25]}] ;# J9.G27 LA25_P +#set_property -dict {LOC BA18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[25]}] ;# J9.G28 LA25_N +#set_property -dict {LOC AP20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[26]}] ;# J9.D26 LA26_P +#set_property -dict {LOC AP20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[26]}] ;# J9.D27 LA26_N +#set_property -dict {LOC AN19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[27]}] ;# J9.C26 LA27_P +#set_property -dict {LOC AP19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[27]}] ;# J9.C27 LA27_N +#set_property -dict {LOC BB17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[28]}] ;# J9.H31 LA28_P +#set_property -dict {LOC BC17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[28]}] ;# J9.H32 LA28_N +#set_property -dict {LOC BB19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[29]}] ;# J9.G30 LA29_P +#set_property -dict {LOC BC18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[29]}] ;# J9.G31 LA29_N +#set_property -dict {LOC BD18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[30]}] ;# J9.H34 LA30_P +#set_property -dict {LOC BE18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[30]}] ;# J9.H35 LA30_N +#set_property -dict {LOC BC19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[31]}] ;# J9.G33 LA31_P +#set_property -dict {LOC BD19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[31]}] ;# J9.G34 LA31_N +#set_property -dict {LOC BF19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[32]}] ;# J9.H37 LA32_P +#set_property -dict {LOC BF18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[32]}] ;# J9.H38 LA32_N +#set_property -dict {LOC BE17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[33]}] ;# J9.G36 LA33_P +#set_property -dict {LOC BF17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[33]}] ;# J9.G37 LA33_N -# set_property -dict {LOC G14 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[0]}] ;# CC -# set_property -dict {LOC F14 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[0]}] ;# CC -# set_property -dict {LOC G15 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[1]}] ;# CC -# set_property -dict {LOC F15 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[1]}] ;# CC -# set_property -dict {LOC A14 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[2]}] -# set_property -dict {LOC A13 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[2]}] -# set_property -dict {LOC B17 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[3]}] -# set_property -dict {LOC A17 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[3]}] -# set_property -dict {LOC C16 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[4]}] -# set_property -dict {LOC B16 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[4]}] -# set_property -dict {LOC B15 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[5]}] -# set_property -dict {LOC A15 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[5]}] -# set_property -dict {LOC G17 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[6]}] -# set_property -dict {LOC G16 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[6]}] -# set_property -dict {LOC D13 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[7]}] -# set_property -dict {LOC C13 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[7]}] -# set_property -dict {LOC E15 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[8]}] -# set_property -dict {LOC D15 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[8]}] -# set_property -dict {LOC E16 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[9]}] -# set_property -dict {LOC D16 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[9]}] -# set_property -dict {LOC R16 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[10]}] -# set_property -dict {LOC P16 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[10]}] -# set_property -dict {LOC L13 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[11]}] -# set_property -dict {LOC K13 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[11]}] -# set_property -dict {LOC H17 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[12]}] -# set_property -dict {LOC H16 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[12]}] -# set_property -dict {LOC J13 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[13]}] -# set_property -dict {LOC H13 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[13]}] -# set_property -dict {LOC P14 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[14]}] -# set_property -dict {LOC N14 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[14]}] -# set_property -dict {LOC N16 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[15]}] -# set_property -dict {LOC M16 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[15]}] -# set_property -dict {LOC M14 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[16]}] -# set_property -dict {LOC L14 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[16]}] -# set_property -dict {LOC J14 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[17]}] ;# CC -# set_property -dict {LOC H14 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[17]}] ;# CC -# set_property -dict {LOC J16 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[18]}] ;# CC -# set_property -dict {LOC J15 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[18]}] ;# CC -# set_property -dict {LOC F13 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[19]}] -# set_property -dict {LOC E13 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[19]}] -# set_property -dict {LOC K16 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[20]}] -# set_property -dict {LOC K15 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[20]}] -# set_property -dict {LOC C14 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[21]}] -# set_property -dict {LOC B14 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[21]}] -# set_property -dict {LOC R15 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[22]}] -# set_property -dict {LOC P15 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[22]}] -# set_property -dict {LOC P13 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_p[23]}] -# set_property -dict {LOC N13 IOSTANDARD LVCMOS18} [get_ports {fmc_ha_n[23]}] +#set_property -dict {LOC G14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[0]}] ;# J9.F4 HA00_P_CC +#set_property -dict {LOC F14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[0]}] ;# J9.F5 HA00_N_CC +#set_property -dict {LOC G15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[1]}] ;# J9.E2 HA01_P_CC +#set_property -dict {LOC F15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[1]}] ;# J9.E3 HA01_N_CC +#set_property -dict {LOC A14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[2]}] ;# J9.K7 HA02_P +#set_property -dict {LOC A13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[2]}] ;# J9.K8 HA02_N +#set_property -dict {LOC B17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[3]}] ;# J9.J6 HA03_P +#set_property -dict {LOC A17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[3]}] ;# J9.J7 HA03_N +#set_property -dict {LOC C16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[4]}] ;# J9.F7 HA04_P +#set_property -dict {LOC B16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[4]}] ;# J9.F8 HA04_N +#set_property -dict {LOC B15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[5]}] ;# J9.E6 HA05_P +#set_property -dict {LOC A15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[5]}] ;# J9.E7 HA05_N +#set_property -dict {LOC G17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[6]}] ;# J9.K10 HA06_P +#set_property -dict {LOC G16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[6]}] ;# J9.K11 HA06_N +#set_property -dict {LOC D13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[7]}] ;# J9.J9 HA07_P +#set_property -dict {LOC C13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[7]}] ;# J9.J10 HA07_N +#set_property -dict {LOC E15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[8]}] ;# J9.F10 HA08_P +#set_property -dict {LOC D15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[8]}] ;# J9.F11 HA08_N +#set_property -dict {LOC E16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[9]}] ;# J9.E9 HA09_P +#set_property -dict {LOC D16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[9]}] ;# J9.E10 HA09_N +#set_property -dict {LOC R16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[10]}] ;# J9.K13 HA10_P +#set_property -dict {LOC P16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[10]}] ;# J9.K14 HA10_N +#set_property -dict {LOC L13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[11]}] ;# J9.J12 HA11_P +#set_property -dict {LOC K13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[11]}] ;# J9.J13 HA11_N +#set_property -dict {LOC H17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[12]}] ;# J9.F13 HA12_P +#set_property -dict {LOC H16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[12]}] ;# J9.F14 HA12_N +#set_property -dict {LOC J13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[13]}] ;# J9.E12 HA13_P +#set_property -dict {LOC H13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[13]}] ;# J9.E13 HA13_N +#set_property -dict {LOC P14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[14]}] ;# J9.J15 HA14_P +#set_property -dict {LOC N14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[14]}] ;# J9.J16 HA14_N +#set_property -dict {LOC N16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[15]}] ;# J9.F14 HA15_P +#set_property -dict {LOC M16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[15]}] ;# J9.F16 HA15_N +#set_property -dict {LOC M14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[16]}] ;# J9.E15 HA16_P +#set_property -dict {LOC L14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[16]}] ;# J9.E16 HA16_N +#set_property -dict {LOC J14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[17]}] ;# J9.K16 HA17_P_CC +#set_property -dict {LOC H14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[17]}] ;# J9.K17 HA17_N_CC +#set_property -dict {LOC J16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[18]}] ;# J9.J18 HA18_P_CC +#set_property -dict {LOC J15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[18]}] ;# J9.J19 HA18_N_CC +#set_property -dict {LOC F13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[19]}] ;# J9.F19 HA19_P +#set_property -dict {LOC E13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[19]}] ;# J9.F20 HA19_N +#set_property -dict {LOC K16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[20]}] ;# J9.E18 HA20_P +#set_property -dict {LOC K15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[20]}] ;# J9.E19 HA20_N +#set_property -dict {LOC C14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[21]}] ;# J9.K19 HA21_P +#set_property -dict {LOC B14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[21]}] ;# J9.K20 HA21_N +#set_property -dict {LOC R15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[22]}] ;# J9.J21 HA22_P +#set_property -dict {LOC P15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[22]}] ;# J9.J22 HA22_N +#set_property -dict {LOC P13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[23]}] ;# J9.K22 HA23_P +#set_property -dict {LOC N13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[23]}] ;# J9.K23 HA23_N -# set_property -dict {LOC H19 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[0]}] ;# CC -# set_property -dict {LOC H18 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[0]}] ;# CC -# set_property -dict {LOC D18 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[1]}] -# set_property -dict {LOC C18 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[1]}] -# set_property -dict {LOC D19 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[2]}] -# set_property -dict {LOC C19 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[2]}] -# set_property -dict {LOC B20 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[3]}] -# set_property -dict {LOC A20 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[3]}] -# set_property -dict {LOC F18 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[4]}] -# set_property -dict {LOC F17 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[4]}] -# set_property -dict {LOC E18 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[5]}] -# set_property -dict {LOC E17 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[5]}] -# set_property -dict {LOC J20 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[6]}] ;# CC -# set_property -dict {LOC J19 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[6]}] ;# CC -# set_property -dict {LOC F20 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[7]}] -# set_property -dict {LOC F19 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[7]}] -# set_property -dict {LOC J21 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[8]}] -# set_property -dict {LOC H21 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[8]}] -# set_property -dict {LOC G20 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[9]}] -# set_property -dict {LOC G19 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[9]}] -# set_property -dict {LOC P19 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[10]}] -# set_property -dict {LOC N19 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[10]}] -# set_property -dict {LOC L17 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[11]}] -# set_property -dict {LOC K17 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[11]}] -# set_property -dict {LOC L19 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[12]}] -# set_property -dict {LOC L18 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[12]}] -# set_property -dict {LOC N17 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[13]}] -# set_property -dict {LOC M17 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[13]}] -# set_property -dict {LOC N21 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[14]}] -# set_property -dict {LOC M21 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[14]}] -# set_property -dict {LOC R20 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[15]}] -# set_property -dict {LOC P20 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[15]}] -# set_property -dict {LOC L20 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[16]}] -# set_property -dict {LOC K20 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[16]}] -# set_property -dict {LOC K18 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[17]}] ;# CC -# set_property -dict {LOC J18 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[17]}] ;# CC -# set_property -dict {LOC C21 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[18]}] -# set_property -dict {LOC B21 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[18]}] -# set_property -dict {LOC E21 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[19]}] -# set_property -dict {LOC E20 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[19]}] -# set_property -dict {LOC B19 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[20]}] -# set_property -dict {LOC A19 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[20]}] -# set_property -dict {LOC D21 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_p[21]}] -# set_property -dict {LOC D20 IOSTANDARD LVCMOS18} [get_ports {fmc_hb_n[21]}] +#set_property -dict {LOC H19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[0]}] ;# J9.K25 HB00_P_CC +#set_property -dict {LOC H18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[0]}] ;# J9.K26 HB00_N_CC +#set_property -dict {LOC D18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[1]}] ;# J9.J24 HB01_P +#set_property -dict {LOC C18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[1]}] ;# J9.J25 HB01_N +#set_property -dict {LOC D19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[2]}] ;# J9.F22 HB02_P +#set_property -dict {LOC C19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[2]}] ;# J9.F23 HB02_N +#set_property -dict {LOC B20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[3]}] ;# J9.E21 HB03_P +#set_property -dict {LOC A20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[3]}] ;# J9.E22 HB03_N +#set_property -dict {LOC F18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[4]}] ;# J9.F25 HB04_P +#set_property -dict {LOC F17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[4]}] ;# J9.F26 HB04_N +#set_property -dict {LOC E18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[5]}] ;# J9.E24 HB05_P +#set_property -dict {LOC E17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[5]}] ;# J9.E25 HB05_N +#set_property -dict {LOC J20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[6]}] ;# J9.K28 HB06_P_CC +#set_property -dict {LOC J19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[6]}] ;# J9.K29 HB06_N_CC +#set_property -dict {LOC F20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[7]}] ;# J9.J27 HB07_P +#set_property -dict {LOC F19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[7]}] ;# J9.J28 HB07_N +#set_property -dict {LOC J21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[8]}] ;# J9.F28 HB08_P +#set_property -dict {LOC H21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[8]}] ;# J9.F29 HB08_N +#set_property -dict {LOC G20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[9]}] ;# J9.E27 HB09_P +#set_property -dict {LOC G19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[9]}] ;# J9.E28 HB09_N +#set_property -dict {LOC P19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[10]}] ;# J9.K31 HB10_P +#set_property -dict {LOC N19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[10]}] ;# J9.K32 HB10_N +#set_property -dict {LOC L17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[11]}] ;# J9.J30 HB11_P +#set_property -dict {LOC K17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[11]}] ;# J9.J31 HB11_N +#set_property -dict {LOC L19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[12]}] ;# J9.F31 HB12_P +#set_property -dict {LOC L18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[12]}] ;# J9.F32 HB12_N +#set_property -dict {LOC N17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[13]}] ;# J9.E30 HB13_P +#set_property -dict {LOC M17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[13]}] ;# J9.E31 HB13_N +#set_property -dict {LOC N21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[14]}] ;# J9.K34 HB14_P +#set_property -dict {LOC M21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[14]}] ;# J9.K35 HB14_N +#set_property -dict {LOC R20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[15]}] ;# J9.J33 HB15_P +#set_property -dict {LOC P20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[15]}] ;# J9.J34 HB15_N +#set_property -dict {LOC L20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[16]}] ;# J9.F34 HB16_P +#set_property -dict {LOC K20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[16]}] ;# J9.F35 HB16_N +#set_property -dict {LOC K18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[17]}] ;# J9.K37 HB17_P_CC +#set_property -dict {LOC J18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[17]}] ;# J9.K38 HB17_N_CC +#set_property -dict {LOC C21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[18]}] ;# J9.J36 HB18_P +#set_property -dict {LOC B21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[18]}] ;# J9.J37 HB18_N +#set_property -dict {LOC E21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[19]}] ;# J9.E33 HB19_P +#set_property -dict {LOC E20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[19]}] ;# J9.E34 HB19_N +#set_property -dict {LOC B19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[20]}] ;# J9.F37 HB20_P +#set_property -dict {LOC A19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[20]}] ;# J9.F38 HB20_N +#set_property -dict {LOC D21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[21]}] ;# J9.E36 HB21_P +#set_property -dict {LOC D20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[21]}] ;# J9.E37 HB21_N -# set_property -dict {LOC AW14 IOSTANDARD LVCMOS18} [get_ports {fmc_clk0_m2c_p}] -# set_property -dict {LOC AW13 IOSTANDARD LVCMOS18} [get_ports {fmc_clk0_m2c_n}] -# set_property -dict {LOC AV18 IOSTANDARD LVCMOS18} [get_ports {fmc_clk1_m2c_p}] -# set_property -dict {LOC AW18 IOSTANDARD LVCMOS18} [get_ports {fmc_clk1_m2c_n}] +#set_property -dict {LOC AW14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk0_m2c_p}] ;# J9.H4 CLK0_M2C_P +#set_property -dict {LOC AW13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk0_m2c_n}] ;# J9.H5 CLK0_M2C_N +#set_property -dict {LOC AV18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk1_m2c_p}] ;# J9.G2 CLK1_M2C_P +#set_property -dict {LOC AW18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk1_m2c_n}] ;# J9.G3 CLK1_M2C_N -# set_property -dict {LOC G25 IOSTANDARD LVCMOS18} [get_ports {fmc_user_def0_p}] -# set_property -dict {LOC G24 IOSTANDARD LVCMOS18} [get_ports {fmc_user_def0_n}] -# set_property -dict {LOC J24 IOSTANDARD LVCMOS18} [get_ports {fmc_sync_m2c_p}] -# set_property -dict {LOC H24 IOSTANDARD LVCMOS18} [get_ports {fmc_sync_m2c_n}] -# set_property -dict {LOC F24 IOSTANDARD LVCMOS18} [get_ports {fmc_refclk_m2c_p}] -# set_property -dict {LOC F23 IOSTANDARD LVCMOS18} [get_ports {fmc_refclk_m2c_n}] -# set_property -dict {LOC E23 IOSTANDARD LVCMOS18} [get_ports {fmc_sync_c2m_p}] -# set_property -dict {LOC E22 IOSTANDARD LVCMOS18} [get_ports {fmc_sync_c2m_n}] +#set_property -dict {LOC G25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_user_def0_p}] ;# J9.L32 USER_DEF0_P +#set_property -dict {LOC G24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_user_def0_n}] ;# J9.L33 USER_DEF0_N +#set_property -dict {LOC F24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_refclk_m2c_p}] ;# J9.L24 REFCLK_M2C_P +#set_property -dict {LOC F23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_refclk_m2c_n}] ;# J9.L25 REFCLK_M2C_N +#set_property -dict {LOC E23 IOSTANDARD LVDS } [get_ports {fmc_sync_c2m_p}] ;# J9.L16 SYNC_C2M_P +#set_property -dict {LOC E22 IOSTANDARD LVDS } [get_ports {fmc_sync_c2m_n}] ;# J9.L17 SYNC_C2M_N +#set_property -dict {LOC J24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_sync_m2c_p}] ;# J9.L28 SYNC_M2C_P +#set_property -dict {LOC H24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_sync_m2c_n}] ;# J9.L29 SYNC_M2C_N -# set_property -dict {LOC AV23 IOSTANDARD LVCMOS18} [get_ports {fmc_pg_m2c}] -# set_property -dict {LOC AW23 IOSTANDARD LVCMOS18} [get_ports {fmc_prsnt_m2c_l}] -# set_property -dict {LOC BC23 IOSTANDARD LVCMOS18} [get_ports {hspc_prsnt_m2c_l}] +#set_property -dict {LOC AV23 IOSTANDARD LVCMOS18} [get_ports {fmc_pg_m2c}] ;# J9.F1 PG_M2C +#set_property -dict {LOC AW23 IOSTANDARD LVCMOS18} [get_ports {fmc_prsnt_m2c_l}] ;# J9.H2 PRSNT_M2C_L +#set_property -dict {LOC BC23 IOSTANDARD LVCMOS18} [get_ports {fmc_hspc_prsnt_m2c_l}] ;# J9.Z1 HSPC_PRSNT_M2C_L -#set_property -dict {LOC AA9 } [get_ports {fmc_dp_c2m_p[3]}] ;# MGTYTXP0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -#set_property -dict {LOC AA8 } [get_ports {fmc_dp_c2m_n[3]}] ;# MGTYTXN0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -#set_property -dict {LOC AA4 } [get_ports {fmc_dp_m2c_p[3]}] ;# MGTYRXP0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -#set_property -dict {LOC AA3 } [get_ports {fmc_dp_m2c_n[3]}] ;# MGTYRXN0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -#set_property -dict {LOC Y7 } [get_ports {fmc_dp_c2m_p[0]}] ;# MGTYTXP1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -#set_property -dict {LOC Y6 } [get_ports {fmc_dp_c2m_n[0]}] ;# MGTYTXN1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -#set_property -dict {LOC Y2 } [get_ports {fmc_dp_m2c_p[0]}] ;# MGTYRXP1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -#set_property -dict {LOC Y1 } [get_ports {fmc_dp_m2c_n[0]}] ;# MGTYRXN1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -#set_property -dict {LOC W9 } [get_ports {fmc_dp_c2m_p[2]}] ;# MGTYTXP2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -#set_property -dict {LOC W8 } [get_ports {fmc_dp_c2m_n[2]}] ;# MGTYTXN2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -#set_property -dict {LOC W4 } [get_ports {fmc_dp_m2c_p[2]}] ;# MGTYRXP2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -#set_property -dict {LOC W3 } [get_ports {fmc_dp_m2c_n[2]}] ;# MGTYRXN2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -#set_property -dict {LOC V7 } [get_ports {fmc_dp_c2m_p[1]}] ;# MGTYTXP3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 -#set_property -dict {LOC V6 } [get_ports {fmc_dp_c2m_n[1]}] ;# MGTYTXN3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 -#set_property -dict {LOC V2 } [get_ports {fmc_dp_m2c_p[1]}] ;# MGTYRXP3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 -#set_property -dict {LOC V1 } [get_ports {fmc_dp_m2c_n[1]}] ;# MGTYRXN3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 -#set_property -dict {LOC Y11 } [get_ports fmc_mgt_refclk_1_0_p] ;# MGTREFCLK0P_229 from J9.D4 GBTCLK0_M2C_P -#set_property -dict {LOC Y10 } [get_ports fmc_mgt_refclk_1_0_n] ;# MGTREFCLK0N_229 from J9.D5 GBTCLK0_M2C_N -#set_property -dict {LOC V11 } [get_ports fmc_mgt_refclk_1_1_p] ;# MGTREFCLK1P_229 from U27.14 OUT3 -#set_property -dict {LOC V10 } [get_ports fmc_mgt_refclk_1_1_n] ;# MGTREFCLK1N_229 from U27.13 OUT3B +#set_property -dict {LOC Y7 } [get_ports {fmc_dp_c2m_p[0]}] ;# MGTYTXP1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C2 DP0_C2M_P +#set_property -dict {LOC Y6 } [get_ports {fmc_dp_c2m_n[0]}] ;# MGTYTXN1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C3 DP0_C2M_N +#set_property -dict {LOC Y2 } [get_ports {fmc_dp_m2c_p[0]}] ;# MGTYRXP1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C6 DP0_M2C_P +#set_property -dict {LOC Y1 } [get_ports {fmc_dp_m2c_n[0]}] ;# MGTYRXN1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C7 DP0_M2C_N +#set_property -dict {LOC V7 } [get_ports {fmc_dp_c2m_p[1]}] ;# MGTYTXP3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A22 DP1_C2M_P +#set_property -dict {LOC V6 } [get_ports {fmc_dp_c2m_n[1]}] ;# MGTYTXN3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A23 DP1_C2M_N +#set_property -dict {LOC V2 } [get_ports {fmc_dp_m2c_p[1]}] ;# MGTYRXP3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A2 DP1_M2C_P +#set_property -dict {LOC V1 } [get_ports {fmc_dp_m2c_n[1]}] ;# MGTYRXN3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A3 DP1_M2C_N +#set_property -dict {LOC W9 } [get_ports {fmc_dp_c2m_p[2]}] ;# MGTYTXP2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A26 DP2_C2M_P +#set_property -dict {LOC W8 } [get_ports {fmc_dp_c2m_n[2]}] ;# MGTYTXN2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A27 DP2_C2M_N +#set_property -dict {LOC W4 } [get_ports {fmc_dp_m2c_p[2]}] ;# MGTYRXP2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A6 DP2_M2C_P +#set_property -dict {LOC W3 } [get_ports {fmc_dp_m2c_n[2]}] ;# MGTYRXN2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A7 DP2_M2C_N +#set_property -dict {LOC AA9 } [get_ports {fmc_dp_c2m_p[3]}] ;# MGTYTXP0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A30 DP3_C2M_P +#set_property -dict {LOC AA8 } [get_ports {fmc_dp_c2m_n[3]}] ;# MGTYTXN0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A31 DP3_C2M_N +#set_property -dict {LOC AA4 } [get_ports {fmc_dp_m2c_p[3]}] ;# MGTYRXP0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A10 DP3_M2C_P +#set_property -dict {LOC AA3 } [get_ports {fmc_dp_m2c_n[3]}] ;# MGTYRXN0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A11 DP3_M2C_N +#set_property -dict {LOC Y11 } [get_ports fmc_mgt_refclk_0_0_p] ;# MGTREFCLK0P_229 from J9.D4 GBTCLK0_M2C_P +#set_property -dict {LOC Y10 } [get_ports fmc_mgt_refclk_0_0_n] ;# MGTREFCLK0N_229 from J9.D5 GBTCLK0_M2C_N +#set_property -dict {LOC V11 } [get_ports fmc_mgt_refclk_0_1_p] ;# MGTREFCLK1P_229 from U27.14 OUT3 +#set_property -dict {LOC V10 } [get_ports fmc_mgt_refclk_0_1_n] ;# MGTREFCLK1N_229 from U27.13 OUT3B -# 156.25 MHz MGT reference clock +# reference clock +#create_clock -period 6.400 -name fmc_mgt_refclk_0_0 [get_ports fmc_mgt_refclk_0_0_p] +#create_clock -period 6.400 -name fmc_mgt_refclk_0_1 [get_ports fmc_mgt_refclk_0_1_p] + +#set_property -dict {LOC AC9 } [get_ports {fmc_dp_c2m_p[4]}] ;# MGTYTXP2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A34 DP4_C2M_P +#set_property -dict {LOC AC8 } [get_ports {fmc_dp_c2m_n[4]}] ;# MGTYTXN2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A35 DP4_C2M_N +#set_property -dict {LOC AC4 } [get_ports {fmc_dp_m2c_p[4]}] ;# MGTYRXP2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A14 DP4_M2C_P +#set_property -dict {LOC AC3 } [get_ports {fmc_dp_m2c_n[4]}] ;# MGTYRXN2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A15 DP4_M2C_N +#set_property -dict {LOC AE9 } [get_ports {fmc_dp_c2m_p[5]}] ;# MGTYTXP0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A38 DP5_C2M_P +#set_property -dict {LOC AE8 } [get_ports {fmc_dp_c2m_n[5]}] ;# MGTYTXN0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A39 DP5_C2M_N +#set_property -dict {LOC AE4 } [get_ports {fmc_dp_m2c_p[5]}] ;# MGTYRXP0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A18 DP5_M2C_P +#set_property -dict {LOC AE3 } [get_ports {fmc_dp_m2c_n[5]}] ;# MGTYRXN0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A19 DP5_M2C_N +#set_property -dict {LOC AD7 } [get_ports {fmc_dp_c2m_p[6]}] ;# MGTYTXP1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B36 DP6_C2M_P +#set_property -dict {LOC AD6 } [get_ports {fmc_dp_c2m_n[6]}] ;# MGTYTXN1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B37 DP6_C2M_N +#set_property -dict {LOC AD2 } [get_ports {fmc_dp_m2c_p[6]}] ;# MGTYRXP1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B16 DP6_M2C_P +#set_property -dict {LOC AD1 } [get_ports {fmc_dp_m2c_n[6]}] ;# MGTYRXN1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B17 DP6_M2C_N +#set_property -dict {LOC AB7 } [get_ports {fmc_dp_c2m_p[7]}] ;# MGTYTXP3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B32 DP7_C2M_P +#set_property -dict {LOC AB6 } [get_ports {fmc_dp_c2m_n[7]}] ;# MGTYTXN3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B33 DP7_C2M_N +#set_property -dict {LOC AB2 } [get_ports {fmc_dp_m2c_p[7]}] ;# MGTYRXP3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B12 DP7_M2C_P +#set_property -dict {LOC AB1 } [get_ports {fmc_dp_m2c_n[7]}] ;# MGTYRXN3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B13 DP7_M2C_N +#set_property -dict {LOC AD11} [get_ports fmc_mgt_refclk_1_0_p] ;# MGTREFCLK0P_228 from J9.B20 GBTCLK1_M2C_P +#set_property -dict {LOC AD10} [get_ports fmc_mgt_refclk_1_0_n] ;# MGTREFCLK0N_228 from J9.B21 GBTCLK1_M2C_N + +# reference clock #create_clock -period 6.400 -name fmc_mgt_refclk_1_0 [get_ports fmc_mgt_refclk_1_0_p] -#create_clock -period 6.400 -name fmc_mgt_refclk_1_1 [get_ports fmc_mgt_refclk_1_1_p] -# 161.1328125 MHz MGT reference clock -#create_clock -period 6.206 -name fmc_mgt_refclk_1_0 [get_ports fmc_mgt_refclk_1_0_p] -#create_clock -period 6.206 -name fmc_mgt_refclk_1_1 [get_ports fmc_mgt_refclk_1_1_p] +#set_property -dict {LOC L9 } [get_ports {fmc_dp_c2m_p[8]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B28 DP8_C2M_P +#set_property -dict {LOC L8 } [get_ports {fmc_dp_c2m_n[8]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B29 DP8_C2M_N +#set_property -dict {LOC L4 } [get_ports {fmc_dp_m2c_p[8]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B8 DP8_M2C_P +#set_property -dict {LOC L3 } [get_ports {fmc_dp_m2c_n[8]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B9 DP8_M2C_N +#set_property -dict {LOC K7 } [get_ports {fmc_dp_c2m_p[9]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B24 DP9_C2M_P +#set_property -dict {LOC K6 } [get_ports {fmc_dp_c2m_n[9]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B25 DP9_C2M_N +#set_property -dict {LOC K2 } [get_ports {fmc_dp_m2c_p[9]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B4 DP9_M2C_P +#set_property -dict {LOC K1 } [get_ports {fmc_dp_m2c_n[9]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B5 DP9_M2C_N +#set_property -dict {LOC M7 } [get_ports {fmc_dp_c2m_p[10]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Z24 DP10_C2M_P +#set_property -dict {LOC M6 } [get_ports {fmc_dp_c2m_n[10]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Z25 DP10_C2M_N +#set_property -dict {LOC M2 } [get_ports {fmc_dp_m2c_p[10]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Y10 DP10_M2C_P +#set_property -dict {LOC M1 } [get_ports {fmc_dp_m2c_n[10]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Y11 DP10_M2C_N +#set_property -dict {LOC N9 } [get_ports {fmc_dp_c2m_p[11]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Y26 DP11_C2M_P +#set_property -dict {LOC N8 } [get_ports {fmc_dp_c2m_n[11]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Y27 DP11_C2M_N +#set_property -dict {LOC N4 } [get_ports {fmc_dp_m2c_p[11]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Z12 DP11_M2C_P +#set_property -dict {LOC N3 } [get_ports {fmc_dp_m2c_n[11]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Z13 DP11_M2C_N +#set_property -dict {LOC M11 } [get_ports fmc_mgt_refclk_2_0_p] ;# MGTREFCLK0P_231 from J9.L12 GBTCLK2_M2C_P +#set_property -dict {LOC M10 } [get_ports fmc_mgt_refclk_2_0_n] ;# MGTREFCLK0N_231 from J9.L13 GBTCLK2_M2C_N +#set_property -dict {LOC K11 } [get_ports fmc_mgt_refclk_2_1_p] ;# MGTREFCLK1P_231 from U27.17 OUT2 +#set_property -dict {LOC K10 } [get_ports fmc_mgt_refclk_2_1_n] ;# MGTREFCLK1N_231 from U27.16 OUT2B -#set_property -dict {LOC AE9 } [get_ports {fmc_dp_c2m_p[5]}] ;# MGTYTXP0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 -#set_property -dict {LOC AE8 } [get_ports {fmc_dp_c2m_n[5]}] ;# MGTYTXN0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 -#set_property -dict {LOC AE4 } [get_ports {fmc_dp_m2c_p[5]}] ;# MGTYRXP0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 -#set_property -dict {LOC AE3 } [get_ports {fmc_dp_m2c_n[5]}] ;# MGTYRXN0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 -#set_property -dict {LOC AD7 } [get_ports {fmc_dp_c2m_p[6]}] ;# MGTYTXP1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 -#set_property -dict {LOC AD6 } [get_ports {fmc_dp_c2m_n[6]}] ;# MGTYTXN1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 -#set_property -dict {LOC AD2 } [get_ports {fmc_dp_m2c_p[6]}] ;# MGTYRXP1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 -#set_property -dict {LOC AD1 } [get_ports {fmc_dp_m2c_n[6]}] ;# MGTYRXN1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 -#set_property -dict {LOC AC9 } [get_ports {fmc_dp_c2m_p[4]}] ;# MGTYTXP2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 -#set_property -dict {LOC AC8 } [get_ports {fmc_dp_c2m_n[4]}] ;# MGTYTXN2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 -#set_property -dict {LOC AC4 } [get_ports {fmc_dp_m2c_p[4]}] ;# MGTYRXP2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 -#set_property -dict {LOC AC3 } [get_ports {fmc_dp_m2c_n[4]}] ;# MGTYRXN2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 -#set_property -dict {LOC AB7 } [get_ports {fmc_dp_c2m_p[7]}] ;# MGTYTXP3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 -#set_property -dict {LOC AB6 } [get_ports {fmc_dp_c2m_n[7]}] ;# MGTYTXN3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 -#set_property -dict {LOC AB2 } [get_ports {fmc_dp_m2c_p[7]}] ;# MGTYRXP3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 -#set_property -dict {LOC AB1 } [get_ports {fmc_dp_m2c_n[7]}] ;# MGTYRXN3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 -#set_property -dict {LOC AD11} [get_ports fmc_mgt_refclk_2_0_p] ;# MGTREFCLK0P_228 from J9.B20 GBTCLK1_M2C_P -#set_property -dict {LOC AD10} [get_ports fmc_mgt_refclk_2_0_n] ;# MGTREFCLK0N_228 from J9.B21 GBTCLK1_M2C_N - -# 156.25 MHz MGT reference clock +# reference clock #create_clock -period 6.400 -name fmc_mgt_refclk_2_0 [get_ports fmc_mgt_refclk_2_0_p] +#create_clock -period 6.400 -name fmc_mgt_refclk_2_1 [get_ports fmc_mgt_refclk_2_1_p] -# 161.1328125 MHz MGT reference clock -#create_clock -period 6.206 -name fmc_mgt_refclk_2_0 [get_ports fmc_mgt_refclk_2_0_p] +#set_property -dict {LOC P7 } [get_ports {fmc_dp_c2m_p[12]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Z28 DP12_C2M_P +#set_property -dict {LOC P6 } [get_ports {fmc_dp_c2m_n[12]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Z29 DP12_C2M_N +#set_property -dict {LOC P2 } [get_ports {fmc_dp_m2c_p[12]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Y14 DP12_M2C_P +#set_property -dict {LOC P1 } [get_ports {fmc_dp_m2c_n[12]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Y15 DP12_M2C_N +#set_property -dict {LOC R9 } [get_ports {fmc_dp_c2m_p[13]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Y30 DP13_C2M_P +#set_property -dict {LOC R8 } [get_ports {fmc_dp_c2m_n[13]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Y31 DP13_C2M_N +#set_property -dict {LOC R4 } [get_ports {fmc_dp_m2c_p[13]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Z16 DP13_M2C_P +#set_property -dict {LOC R3 } [get_ports {fmc_dp_m2c_n[13]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Z17 DP13_M2C_N +#set_property -dict {LOC T7 } [get_ports {fmc_dp_c2m_p[14]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.M18 DP14_C2M_P +#set_property -dict {LOC T6 } [get_ports {fmc_dp_c2m_n[14]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.M19 DP14_C2M_N +#set_property -dict {LOC T2 } [get_ports {fmc_dp_m2c_p[14]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.Y18 DP14_M2C_P +#set_property -dict {LOC T1 } [get_ports {fmc_dp_m2c_n[14]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.Y19 DP14_M2C_N +#set_property -dict {LOC U9 } [get_ports {fmc_dp_c2m_p[15]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.M22 DP15_C2M_P +#set_property -dict {LOC U8 } [get_ports {fmc_dp_c2m_n[15]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.M23 DP15_C2M_N +#set_property -dict {LOC U4 } [get_ports {fmc_dp_m2c_p[15]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.Y22 DP15_M2C_P +#set_property -dict {LOC U3 } [get_ports {fmc_dp_m2c_n[15]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.Y23 DP15_M2C_N +#set_property -dict {LOC T11 } [get_ports fmc_mgt_refclk_3_0_p] ;# MGTREFCLK0P_230 from J9.L8 GBTCLK3_M2C_P +#set_property -dict {LOC T10 } [get_ports fmc_mgt_refclk_3_0_n] ;# MGTREFCLK0N_230 from J9.L9 GBTCLK3_M2C_N -#set_property -dict {LOC N9 } [get_ports {fmc_dp_c2m_p[11]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC N8 } [get_ports {fmc_dp_c2m_n[11]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC N4 } [get_ports {fmc_dp_m2c_p[11]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC N3 } [get_ports {fmc_dp_m2c_n[11]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC M7 } [get_ports {fmc_dp_c2m_p[10]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC M6 } [get_ports {fmc_dp_c2m_n[10]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC M2 } [get_ports {fmc_dp_m2c_p[10]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC M1 } [get_ports {fmc_dp_m2c_n[10]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC L9 } [get_ports {fmc_dp_c2m_p[8]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC L8 } [get_ports {fmc_dp_c2m_n[8]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC L4 } [get_ports {fmc_dp_m2c_p[8]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC L3 } [get_ports {fmc_dp_m2c_n[8]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC K7 } [get_ports {fmc_dp_c2m_p[9]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC K6 } [get_ports {fmc_dp_c2m_n[9]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC K2 } [get_ports {fmc_dp_m2c_p[9]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC K1 } [get_ports {fmc_dp_m2c_n[9]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC M11 } [get_ports fmc_mgt_refclk_3_0_p] ;# MGTREFCLK0P_231 from J9.L12 GBTCLK2_M2C_P -#set_property -dict {LOC M10 } [get_ports fmc_mgt_refclk_3_0_n] ;# MGTREFCLK0N_231 from J9.L13 GBTCLK2_M2C_N -#set_property -dict {LOC K11 } [get_ports fmc_mgt_refclk_3_1_p] ;# MGTREFCLK1P_231 from U27.17 OUT2 -#set_property -dict {LOC K10 } [get_ports fmc_mgt_refclk_3_1_n] ;# MGTREFCLK1N_231 from U27.16 OUT2B - -# 156.25 MHz MGT reference clock +# reference clock #create_clock -period 6.400 -name fmc_mgt_refclk_3_0 [get_ports fmc_mgt_refclk_3_0_p] -#create_clock -period 6.400 -name fmc_mgt_refclk_3_1 [get_ports fmc_mgt_refclk_3_1_p] -# 161.1328125 MHz MGT reference clock -#create_clock -period 6.206 -name fmc_mgt_refclk_3_0 [get_ports fmc_mgt_refclk_3_0_p] -#create_clock -period 6.206 -name fmc_mgt_refclk_3_1 [get_ports fmc_mgt_refclk_3_1_p] +#set_property -dict {LOC AF7 } [get_ports {fmc_dp_c2m_p[16]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.M26 DP16_C2M_P +#set_property -dict {LOC AF6 } [get_ports {fmc_dp_c2m_n[16]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.M27 DP16_C2M_N +#set_property -dict {LOC AF2 } [get_ports {fmc_dp_m2c_p[16]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.Z32 DP16_M2C_P +#set_property -dict {LOC AF1 } [get_ports {fmc_dp_m2c_n[16]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.Z33 DP16_M2C_N +#set_property -dict {LOC AG9 } [get_ports {fmc_dp_c2m_p[17]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.M30 DP17_C2M_P +#set_property -dict {LOC AG8 } [get_ports {fmc_dp_c2m_n[17]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.M31 DP17_C2M_N +#set_property -dict {LOC AG4 } [get_ports {fmc_dp_m2c_p[17]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.Y34 DP17_M2C_P +#set_property -dict {LOC AG3 } [get_ports {fmc_dp_m2c_n[17]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.Y35 DP17_M2C_N +#set_property -dict {LOC AH7 } [get_ports {fmc_dp_c2m_p[18]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.M34 DP18_C2M_P +#set_property -dict {LOC AH6 } [get_ports {fmc_dp_c2m_n[18]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.M35 DP18_C2M_N +#set_property -dict {LOC AH2 } [get_ports {fmc_dp_m2c_p[18]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.Z36 DP18_M2C_P +#set_property -dict {LOC AH1 } [get_ports {fmc_dp_m2c_n[18]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.Z37 DP18_M2C_N +#set_property -dict {LOC AJ9 } [get_ports {fmc_dp_c2m_p[19]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.M38 DP19_C2M_P +#set_property -dict {LOC AJ8 } [get_ports {fmc_dp_c2m_n[19]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.M39 DP19_C2M_N +#set_property -dict {LOC AJ4 } [get_ports {fmc_dp_m2c_p[19]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.Y38 DP19_M2C_P +#set_property -dict {LOC AJ3 } [get_ports {fmc_dp_m2c_n[19]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.Y39 DP19_M2C_N +#set_property -dict {LOC AH11} [get_ports fmc_mgt_refclk_4_0_p] ;# MGTREFCLK0P_227 from J9.L4 GBTCLK4_M2C_P +#set_property -dict {LOC AH10} [get_ports fmc_mgt_refclk_4_0_n] ;# MGTREFCLK0N_227 from J9.L5 GBTCLK4_M2C_N +#set_property -dict {LOC AF11} [get_ports fmc_mgt_refclk_4_1_p] ;# MGTREFCLK1P_227 from U27.11 OUT4 +#set_property -dict {LOC AF10} [get_ports fmc_mgt_refclk_4_1_n] ;# MGTREFCLK1N_227 from U27.12 OUT4B -#set_property -dict {LOC U9 } [get_ports {fmc_dp_c2m_p[15]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC U8 } [get_ports {fmc_dp_c2m_n[15]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC U4 } [get_ports {fmc_dp_m2c_p[15]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC U3 } [get_ports {fmc_dp_m2c_n[15]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC T7 } [get_ports {fmc_dp_c2m_p[14]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC T6 } [get_ports {fmc_dp_c2m_n[14]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC T2 } [get_ports {fmc_dp_m2c_p[14]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC T1 } [get_ports {fmc_dp_m2c_n[14]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC R9 } [get_ports {fmc_dp_c2m_p[13]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC R8 } [get_ports {fmc_dp_c2m_n[13]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC R4 } [get_ports {fmc_dp_m2c_p[13]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC R3 } [get_ports {fmc_dp_m2c_n[13]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC P7 } [get_ports {fmc_dp_c2m_p[12]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC P6 } [get_ports {fmc_dp_c2m_n[12]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC P2 } [get_ports {fmc_dp_m2c_p[12]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC P1 } [get_ports {fmc_dp_m2c_n[12]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC T11 } [get_ports fmc_mgt_refclk_4_0_p] ;# MGTREFCLK0P_230 from J9.L8 GBTCLK3_M2C_P -#set_property -dict {LOC T10 } [get_ports fmc_mgt_refclk_4_0_n] ;# MGTREFCLK0N_230 from J9.L9 GBTCLK3_M2C_N - -# 156.25 MHz MGT reference clock +# reference clock #create_clock -period 6.400 -name fmc_mgt_refclk_4_0 [get_ports fmc_mgt_refclk_4_0_p] +#create_clock -period 6.400 -name fmc_mgt_refclk_4_1 [get_ports fmc_mgt_refclk_4_1_p] -# 161.1328125 MHz MGT reference clock -#create_clock -period 6.206 -name fmc_mgt_refclk_4_0 [get_ports fmc_mgt_refclk_4_0_p] +#set_property -dict {LOC J9 } [get_ports {fmc_dp_c2m_p[20]}] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.Z8 DP20_C2M_P +#set_property -dict {LOC J8 } [get_ports {fmc_dp_c2m_n[20]}] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.Z9 DP20_C2M_N +#set_property -dict {LOC J4 } [get_ports {fmc_dp_m2c_p[20]}] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.M14 DP20_M2C_P +#set_property -dict {LOC J3 } [get_ports {fmc_dp_m2c_n[20]}] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.M15 DP20_M2C_N +#set_property -dict {LOC H7 } [get_ports {fmc_dp_c2m_p[21]}] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.Y6 DP21_C2M_P +#set_property -dict {LOC H6 } [get_ports {fmc_dp_c2m_n[21]}] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.Y7 DP21_C2M_N +#set_property -dict {LOC H2 } [get_ports {fmc_dp_m2c_p[21]}] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.M10 DP21_M2C_P +#set_property -dict {LOC H1 } [get_ports {fmc_dp_m2c_n[21]}] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.M11 DP21_M2C_N +#set_property -dict {LOC G9 } [get_ports {fmc_dp_c2m_p[22]}] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.Z4 DP22_C2M_P +#set_property -dict {LOC G8 } [get_ports {fmc_dp_c2m_n[22]}] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.Z5 DP22_C2M_N +#set_property -dict {LOC G4 } [get_ports {fmc_dp_m2c_p[22]}] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.M6 DP22_M2C_P +#set_property -dict {LOC G3 } [get_ports {fmc_dp_m2c_n[22]}] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.M7 DP22_M2C_N +#set_property -dict {LOC F7 } [get_ports {fmc_dp_c2m_p[23]}] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.Y2 DP23_C2M_P +#set_property -dict {LOC F6 } [get_ports {fmc_dp_c2m_n[23]}] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.Y3 DP23_C2M_N +#set_property -dict {LOC F2 } [get_ports {fmc_dp_m2c_p[23]}] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.M2 DP23_M2C_P +#set_property -dict {LOC F1 } [get_ports {fmc_dp_m2c_n[23]}] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.M3 DP23_M2C_N +#set_property -dict {LOC H11 } [get_ports fmc_mgt_refclk_5_0_p] ;# MGTREFCLK0P_232 from J9.Z20 GBTCLK5_M2C_P +#set_property -dict {LOC H10 } [get_ports fmc_mgt_refclk_5_0_n] ;# MGTREFCLK0N_232 from J9.Z21 GBTCLK5_M2C_N -#set_property -dict {LOC AJ9 } [get_ports {fmc_dp_c2m_p[19]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AJ8 } [get_ports {fmc_dp_c2m_n[19]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AJ4 } [get_ports {fmc_dp_m2c_p[19]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AJ3 } [get_ports {fmc_dp_m2c_n[19]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AH7 } [get_ports {fmc_dp_c2m_p[18]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AH6 } [get_ports {fmc_dp_c2m_n[18]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AH2 } [get_ports {fmc_dp_m2c_p[18]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AH1 } [get_ports {fmc_dp_m2c_n[18]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AG9 } [get_ports {fmc_dp_c2m_p[17]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AG8 } [get_ports {fmc_dp_c2m_n[17]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AG4 } [get_ports {fmc_dp_m2c_p[17]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AG3 } [get_ports {fmc_dp_m2c_n[17]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AF7 } [get_ports {fmc_dp_c2m_p[16]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AF6 } [get_ports {fmc_dp_c2m_n[16]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AF2 } [get_ports {fmc_dp_m2c_p[16]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AF1 } [get_ports {fmc_dp_m2c_n[16]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AH11} [get_ports fmc_mgt_refclk_5_0_p] ;# MGTREFCLK0P_227 from J9.L4 GBTCLK4_M2C_P -#set_property -dict {LOC AH10} [get_ports fmc_mgt_refclk_5_0_n] ;# MGTREFCLK0N_227 from J9.L5 GBTCLK4_M2C_N -#set_property -dict {LOC AF11} [get_ports fmc_mgt_refclk_5_1_p] ;# MGTREFCLK1P_227 from U27.11 OUT4 -#set_property -dict {LOC AF10} [get_ports fmc_mgt_refclk_5_1_n] ;# MGTREFCLK1N_227 from U27.12 OUT4B - -# 156.25 MHz MGT reference clock +# reference clock #create_clock -period 6.400 -name fmc_mgt_refclk_5_0 [get_ports fmc_mgt_refclk_5_0_p] -#create_clock -period 6.400 -name fmc_mgt_refclk_5_1 [get_ports fmc_mgt_refclk_5_1_p] - -# 161.1328125 MHz MGT reference clock -#create_clock -period 6.206 -name fmc_mgt_refclk_5_0 [get_ports fmc_mgt_refclk_5_0_p] -#create_clock -period 6.206 -name fmc_mgt_refclk_5_1 [get_ports fmc_mgt_refclk_5_1_p] - -#set_property -dict {LOC J9 } [get_ports {fmc_dp_c2m_p[20]}] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC J8 } [get_ports {fmc_dp_c2m_n[20]}] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC J4 } [get_ports {fmc_dp_m2c_p[20]}] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC J3 } [get_ports {fmc_dp_m2c_n[20]}] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC H7 } [get_ports {fmc_dp_c2m_p[21]}] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC H6 } [get_ports {fmc_dp_c2m_n[21]}] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC H2 } [get_ports {fmc_dp_m2c_p[21]}] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC H1 } [get_ports {fmc_dp_m2c_n[21]}] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC G9 } [get_ports {fmc_dp_c2m_p[22]}] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC G8 } [get_ports {fmc_dp_c2m_n[22]}] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC G4 } [get_ports {fmc_dp_m2c_p[22]}] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC G3 } [get_ports {fmc_dp_m2c_n[22]}] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC F7 } [get_ports {fmc_dp_c2m_p[23]}] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC F6 } [get_ports {fmc_dp_c2m_n[23]}] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC F2 } [get_ports {fmc_dp_m2c_p[23]}] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC F1 } [get_ports {fmc_dp_m2c_n[23]}] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC H11 } [get_ports fmc_mgt_refclk_6_0_p] ;# MGTREFCLK0P_232 from J9.Z20 GBTCLK5_M2C_P -#set_property -dict {LOC H10 } [get_ports fmc_mgt_refclk_6_0_n] ;# MGTREFCLK0N_232 from J9.Z21 GBTCLK5_M2C_N - -# 156.25 MHz MGT reference clock -#create_clock -period 6.400 -name fmc_mgt_refclk_6_0 [get_ports fmc_mgt_refclk_6_0_p] - -# 161.1328125 MHz MGT reference clock -#create_clock -period 6.206 -name fmc_mgt_refclk_6_0 [get_ports fmc_mgt_refclk_6_0_p] diff --git a/fpga/lib/eth/example/HTG9200/fpga_10g/fpga/Makefile b/fpga/lib/eth/example/HTG9200/fpga_25g/fpga/Makefile similarity index 98% rename from fpga/lib/eth/example/HTG9200/fpga_10g/fpga/Makefile rename to fpga/lib/eth/example/HTG9200/fpga_25g/fpga/Makefile index b09408332..578e97b42 100644 --- a/fpga/lib/eth/example/HTG9200/fpga_10g/fpga/Makefile +++ b/fpga/lib/eth/example/HTG9200/fpga_25g/fpga/Makefile @@ -11,7 +11,7 @@ SYN_FILES += rtl/eth_xcvr_phy_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/i2c_master.v -SYN_FILES += rtl/si5341_i2c_init.v +SYN_FILES += pll/si5341_i2c_init.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v @@ -60,6 +60,9 @@ XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES += ip/eth_xcvr_gt.tcl +# Configuration +CONFIG_TCL_FILES = ./config.tcl + include ../common/vivado.mk program: $(FPGA_TOP).bit diff --git a/fpga/lib/eth/example/HTG9200/fpga_25g/fpga/config.tcl b/fpga/lib/eth/example/HTG9200/fpga_25g/fpga/config.tcl new file mode 100644 index 000000000..756e2b3a1 --- /dev/null +++ b/fpga/lib/eth/example/HTG9200/fpga_25g/fpga/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/HTG9200/fpga_25g/fpga_10g/Makefile b/fpga/lib/eth/example/HTG9200/fpga_25g/fpga_10g/Makefile new file mode 100644 index 000000000..578e97b42 --- /dev/null +++ b/fpga/lib/eth/example/HTG9200/fpga_25g/fpga_10g/Makefile @@ -0,0 +1,115 @@ + +# FPGA settings +FPGA_PART = xcvu9p-flgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/debounce_switch.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/i2c_master.v +SYN_FILES += pll/si5341_i2c_init.v +SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete_64.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v +SYN_FILES += lib/eth/rtl/udp_64.v +SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v +SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v +SYN_FILES += lib/eth/rtl/ip_complete_64.v +SYN_FILES += lib/eth/rtl/ip_64.v +SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v +SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl + +# IP +IP_TCL_FILES += ip/eth_xcvr_gt.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + diff --git a/fpga/lib/eth/example/HTG9200/fpga_25g/fpga_10g/config.tcl b/fpga/lib/eth/example/HTG9200/fpga_25g/fpga_10g/config.tcl new file mode 100644 index 000000000..90aa4caeb --- /dev/null +++ b/fpga/lib/eth/example/HTG9200/fpga_25g/fpga_10g/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/AU50/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/lib/eth/example/HTG9200/fpga_25g/ip/eth_xcvr_gt.tcl similarity index 100% rename from fpga/lib/eth/example/AU50/fpga_10g/ip/eth_xcvr_gt.tcl rename to fpga/lib/eth/example/HTG9200/fpga_25g/ip/eth_xcvr_gt.tcl diff --git a/fpga/lib/eth/example/HXT100G/fpga/lib/eth b/fpga/lib/eth/example/HTG9200/fpga_25g/lib/eth similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga/lib/eth rename to fpga/lib/eth/example/HTG9200/fpga_25g/lib/eth diff --git a/fpga/lib/eth/example/HTG9200/fpga_10g/rtl/Si5341-RevD-fpga-161-osc-Registers.txt b/fpga/lib/eth/example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161-Registers.txt similarity index 82% rename from fpga/lib/eth/example/HTG9200/fpga_10g/rtl/Si5341-RevD-fpga-161-osc-Registers.txt rename to fpga/lib/eth/example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161-Registers.txt index 72552fc74..a999c1d0b 100644 --- a/fpga/lib/eth/example/HTG9200/fpga_10g/rtl/Si5341-RevD-fpga-161-osc-Registers.txt +++ b/fpga/lib/eth/example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161-Registers.txt @@ -1,12 +1,12 @@ # Si534x/7x/8x/9x Registers Script # # Part: Si5341 -# Project File: C:\Users\Alex\Documents\Si5341-RevD-fpga-161-osc-Project.slabtimeproj -# Design ID: fpga +# Project File: X:\Projects\verilog-ethernet\example\HTG9200\fpga_25g\pll\HTG9200_161-9k2_161.slabtimeproj +# Design ID: 9k2_161 # Includes Pre/Post Download Control Register Writes: Yes # Die Revision: B1 -# Creator: ClockBuilder Pro v3.1 [2021-01-18] -# Created On: 2021-03-14 17:21:45 GMT-07:00 +# Creator: ClockBuilder Pro v4.1 [2021-09-22] +# Created On: 2023-07-19 01:51:06 GMT-07:00 Address,Data # # Start configuration preamble @@ -30,7 +30,7 @@ Address,Data 0x0008,0x00 0x000B,0x74 0x0017,0xD0 -0x0018,0xFC +0x0018,0xFF 0x0021,0x0B 0x0022,0x00 0x002B,0x02 @@ -69,35 +69,35 @@ Address,Data 0x0112,0x02 0x0113,0x09 0x0114,0x3B -0x0115,0x2C +0x0115,0x29 0x0117,0x06 0x0118,0x09 0x0119,0x3B -0x011A,0x29 +0x011A,0x28 0x011C,0x06 0x011D,0x09 0x011E,0x3B -0x011F,0x29 +0x011F,0x28 0x0121,0x06 0x0122,0x09 0x0123,0x3B -0x0124,0x2A +0x0124,0x28 0x0126,0x06 0x0127,0x09 0x0128,0x3B -0x0129,0x2A +0x0129,0x28 0x012B,0x06 0x012C,0x09 0x012D,0x3B -0x012E,0x2B +0x012E,0x28 0x0130,0x06 0x0131,0x09 0x0132,0x3B -0x0133,0x2B +0x0133,0x28 0x013A,0x06 0x013B,0x09 0x013C,0x3B -0x013D,0x2B +0x013D,0x28 0x013F,0x00 0x0140,0x00 0x0141,0x40 @@ -182,13 +182,13 @@ Address,Data 0x0268,0x00 0x0269,0x00 0x026A,0x00 -0x026B,0x66 -0x026C,0x70 -0x026D,0x67 -0x026E,0x61 -0x026F,0x00 -0x0270,0x00 -0x0271,0x00 +0x026B,0x39 +0x026C,0x6B +0x026D,0x32 +0x026E,0x5F +0x026F,0x31 +0x0270,0x36 +0x0271,0x31 0x0272,0x00 0x0302,0x00 0x0303,0x00 @@ -203,9 +203,9 @@ Address,Data 0x030C,0x00 0x030D,0x00 0x030E,0x00 -0x030F,0x00 -0x0310,0x80 -0x0311,0x14 +0x030F,0x10 +0x0310,0x42 +0x0311,0x08 0x0312,0x00 0x0313,0x00 0x0314,0x00 @@ -215,35 +215,35 @@ Address,Data 0x0318,0x00 0x0319,0x00 0x031A,0x00 -0x031B,0x80 -0x031C,0x14 +0x031B,0x00 +0x031C,0x00 0x031D,0x00 0x031E,0x00 0x031F,0x00 0x0320,0x00 -0x0321,0x80 +0x0321,0x00 0x0322,0x00 0x0323,0x00 0x0324,0x00 0x0325,0x00 -0x0326,0x80 -0x0327,0x14 +0x0326,0x00 +0x0327,0x00 0x0328,0x00 0x0329,0x00 0x032A,0x00 0x032B,0x00 -0x032C,0x80 +0x032C,0x00 0x032D,0x00 0x032E,0x00 0x032F,0x00 -0x0330,0x10 -0x0331,0x42 -0x0332,0x08 +0x0330,0x00 +0x0331,0x00 +0x0332,0x00 0x0333,0x00 0x0334,0x00 0x0335,0x00 0x0336,0x00 -0x0337,0x80 +0x0337,0x00 0x0338,0x00 0x0339,0x1F 0x033B,0x00 @@ -391,16 +391,16 @@ Address,Data 0x094F,0x02 0x095E,0x00 0x0A02,0x00 -0x0A03,0x1F -0x0A04,0x0F -0x0A05,0x1F +0x0A03,0x03 +0x0A04,0x01 +0x0A05,0x03 0x0A14,0x00 0x0A1A,0x00 0x0A20,0x00 0x0A26,0x00 0x0A2C,0x00 0x0B44,0x0F -0x0B4A,0x00 +0x0B4A,0x1C 0x0B57,0xA5 0x0B58,0x00 # End configuration registers diff --git a/fpga/lib/eth/example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161.slabtimeproj b/fpga/lib/eth/example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161.slabtimeproj new file mode 100644 index 000000000..dcb40c415 Binary files /dev/null and b/fpga/lib/eth/example/HTG9200/fpga_25g/pll/HTG9200_161-9k2_161.slabtimeproj differ diff --git a/fpga/lib/eth/example/HTG9200/fpga_10g/rtl/si5341_i2c_init.py b/fpga/lib/eth/example/HTG9200/fpga_25g/pll/si5341_i2c_init.py similarity index 89% rename from fpga/lib/eth/example/HTG9200/fpga_10g/rtl/si5341_i2c_init.py rename to fpga/lib/eth/example/HTG9200/fpga_25g/pll/si5341_i2c_init.py index f564d1256..6f28b1ffe 100755 --- a/fpga/lib/eth/example/HTG9200/fpga_10g/rtl/si5341_i2c_init.py +++ b/fpga/lib/eth/example/HTG9200/fpga_25g/pll/si5341_i2c_init.py @@ -1,62 +1,18 @@ #!/usr/bin/env python """ -Generates an I2C init module for an Si5341 PLL chip +Generates an I2C init module for multiple chips """ -import argparse from jinja2 import Template -def main(): - parser = argparse.ArgumentParser(description=__doc__.strip()) - parser.add_argument('-r', '--regs', type=str, help="register list") - parser.add_argument('-n', '--name', type=str, help="module name") - parser.add_argument('-o', '--output', type=str, help="output file name") - - args = parser.parse_args() - - try: - generate(**args.__dict__) - except IOError as ex: - print(ex) - exit(1) - - -def generate(regs=None, name=None, output=None): - if regs is None: - raise Exception("Register list not specified") - - if name is None: - name = "si5341_i2c_init" - - if output is None: - output = name + ".v" - - print(f"Generating Si5341 I2C init module {name}...") - +def si5341_cmds(regs, dev_addr=0x77): cur_page = None cur_addr = None - dev_addr = 0x77 - i = 0 - cmds = "" + cmds = [] - cmds += " // Initial delay\n" - cmds += f" init_data[{i}] = 9'b000010110; // delay 30 ms\n" - i += 1 - cmds += " // Set muxes to select Si5341\n" - cmds += f" init_data[{i}] = {{2'b01, 7'h70}};\n" - i += 1 - cmds += f" init_data[{i}] = {{1'b1, 8'h00}};\n" - i += 1 - cmds += f" init_data[{i}] = 9'b001000001; // I2C stop\n" - i += 1 - cmds += f" init_data[{i}] = {{2'b01, 7'h71}};\n" - i += 1 - cmds += f" init_data[{i}] = {{1'b1, 8'h04}};\n" - i += 1 - cmds += f" init_data[{i}] = 9'b001000001; // I2C stop\n" - i += 1 + print(f"Reading register list file '{regs}'...") with open(regs, "r") as f: for line in f: @@ -64,11 +20,10 @@ def generate(regs=None, name=None, output=None): if not line or line == "Address,Data": continue if line[0] == '#': - cmds += f" // {line[1:].strip()}\n" + cmds.append(f"// {line[1:].strip()}") if line.startswith("# Delay"): - cmds += f" init_data[{i}] = 9'b000011010; // delay 300 ms\n" - i += 1 + cmds.append("9'b000011010; // delay 300 ms") cur_addr = None continue @@ -79,30 +34,69 @@ def generate(regs=None, name=None, output=None): data = int(d[1], 0) if page != cur_page: - cmds += f" init_data[{i}] = {{2'b01, 7'h{dev_addr:02x}}};\n" - i += 1 - cmds += f" init_data[{i}] = {{1'b1, 8'h01}};\n" - i += 1 - cmds += f" init_data[{i}] = {{1'b1, 8'h{page:02x}}}; // set page {page:#04x}\n" - i += 1 + cmds.append(f"{{2'b01, 7'h{dev_addr:02x}}};") + cmds.append("{1'b1, 8'h01};") + cmds.append(f"{{1'b1, 8'h{page:02x}}}; // set page {page:#04x}") cur_page = page cur_addr = None if addr != cur_addr: - cmds += f" init_data[{i}] = {{2'b01, 7'h{dev_addr:02x}}};\n" - i += 1 - cmds += f" init_data[{i}] = {{1'b1, 8'h{addr & 0xff:02x}}};\n" - i += 1 + cmds.append(f"{{2'b01, 7'h{dev_addr:02x}}};") + cmds.append(f"{{1'b1, 8'h{addr & 0xff:02x}}};") cur_addr = addr - cmds += f" init_data[{i}] = {{1'b1, 8'h{data:02x}}}; // write {data:#04x} to {addr:#06x}\n" - i += 1 + cmds.append(f"{{1'b1, 8'h{data:02x}}}; // write {data:#04x} to {addr:#06x}") cur_addr += 1 - cmds += f" init_data[{i}] = 9'd0; // end\n" - i += 1 + return cmds - cmd_count = i + +def mux_cmds(val, dev_addr): + cmds = [] + cmds.append(f"{{2'b01, 7'h{dev_addr:02x}}};") + cmds.append(f"{{1'b1, 8'h{val:02x}}};") + cmds.append("9'b001000001; // I2C stop") + return cmds + + +def main(): + cmds = [] + + cmds.append("// Initial delay") + cmds.append("9'b000010110; // delay 30 ms") + + # Si5341 on HTG 9200 + cmds.append("// Set muxes to select U48 Si5341 on HTG-9200") + cmds.extend(mux_cmds(0x00, 0x70)) + cmds.extend(mux_cmds(0x04, 0x71)) + + cmds.extend(si5341_cmds("HTG9200_161-9k2_161-Registers.txt", 0x77)) + generate(cmds) + + +def generate(cmds=None, name=None, output=None): + if cmds is None: + raise Exception("Command list is required") + + if name is None: + name = "si5341_i2c_init" + + if output is None: + output = name + ".v" + + print(f"Generating Si5341 I2C init module {name}...") + + cmds.append("9'd0; // end") + + cmd_str = "" + cmd_count = 0 + + for cmd in cmds: + if cmd.startswith('//'): + cmd_str += f" {cmd}\n" + else: + cmd_str += f" init_data[{cmd_count}] = {cmd}\n" + cmd_count += 1 t = Template(u"""/* @@ -248,7 +242,7 @@ localparam INIT_DATA_LEN = {{cmd_count}}; reg [8:0] init_data [INIT_DATA_LEN-1:0]; initial begin -{{cmds-}} +{{cmd_str-}} end localparam [3:0] @@ -591,7 +585,7 @@ endmodule with open(output, 'w') as f: f.write(t.render( - cmds=cmds, + cmd_str=cmd_str, cmd_count=cmd_count, name=name )) diff --git a/fpga/lib/eth/example/HTG9200/fpga_10g/rtl/si5341_i2c_init.v b/fpga/lib/eth/example/HTG9200/fpga_25g/pll/si5341_i2c_init.v similarity index 95% rename from fpga/lib/eth/example/HTG9200/fpga_10g/rtl/si5341_i2c_init.v rename to fpga/lib/eth/example/HTG9200/fpga_25g/pll/si5341_i2c_init.v index f3dd9a34b..7a29b977c 100644 --- a/fpga/lib/eth/example/HTG9200/fpga_10g/rtl/si5341_i2c_init.v +++ b/fpga/lib/eth/example/HTG9200/fpga_25g/pll/si5341_i2c_init.v @@ -144,7 +144,7 @@ reg [8:0] init_data [INIT_DATA_LEN-1:0]; initial begin // Initial delay init_data[0] = 9'b000010110; // delay 30 ms - // Set muxes to select Si5341 + // Set muxes to select U48 Si5341 on HTG-9200 init_data[1] = {2'b01, 7'h70}; init_data[2] = {1'b1, 8'h00}; init_data[3] = 9'b001000001; // I2C stop @@ -154,12 +154,12 @@ initial begin // Si534x/7x/8x/9x Registers Script // // Part: Si5341 - // Project File: C:\Users\Alex\Documents\Si5341-RevD-fpga-161-osc-Project.slabtimeproj - // Design ID: fpga + // Project File: X:\Projects\verilog-ethernet\example\HTG9200\fpga_25g\pll\HTG9200_161-9k2_161.slabtimeproj + // Design ID: 9k2_161 // Includes Pre/Post Download Control Register Writes: Yes // Die Revision: B1 - // Creator: ClockBuilder Pro v3.1 [2021-01-18] - // Created On: 2021-03-14 17:21:45 GMT-07:00 + // Creator: ClockBuilder Pro v4.1 [2021-09-22] + // Created On: 2023-07-19 01:51:06 GMT-07:00 // // Start configuration preamble init_data[7] = {2'b01, 7'h77}; @@ -214,7 +214,7 @@ initial begin init_data[47] = {2'b01, 7'h77}; init_data[48] = {1'b1, 8'h17}; init_data[49] = {1'b1, 8'hd0}; // write 0xd0 to 0x0017 - init_data[50] = {1'b1, 8'hfc}; // write 0xfc to 0x0018 + init_data[50] = {1'b1, 8'hff}; // write 0xff to 0x0018 init_data[51] = {2'b01, 7'h77}; init_data[52] = {1'b1, 8'h21}; init_data[53] = {1'b1, 8'h0b}; // write 0x0b to 0x0021 @@ -272,49 +272,49 @@ initial begin init_data[105] = {1'b1, 8'h02}; // write 0x02 to 0x0112 init_data[106] = {1'b1, 8'h09}; // write 0x09 to 0x0113 init_data[107] = {1'b1, 8'h3b}; // write 0x3b to 0x0114 - init_data[108] = {1'b1, 8'h2c}; // write 0x2c to 0x0115 + init_data[108] = {1'b1, 8'h29}; // write 0x29 to 0x0115 init_data[109] = {2'b01, 7'h77}; init_data[110] = {1'b1, 8'h17}; init_data[111] = {1'b1, 8'h06}; // write 0x06 to 0x0117 init_data[112] = {1'b1, 8'h09}; // write 0x09 to 0x0118 init_data[113] = {1'b1, 8'h3b}; // write 0x3b to 0x0119 - init_data[114] = {1'b1, 8'h29}; // write 0x29 to 0x011a + init_data[114] = {1'b1, 8'h28}; // write 0x28 to 0x011a init_data[115] = {2'b01, 7'h77}; init_data[116] = {1'b1, 8'h1c}; init_data[117] = {1'b1, 8'h06}; // write 0x06 to 0x011c init_data[118] = {1'b1, 8'h09}; // write 0x09 to 0x011d init_data[119] = {1'b1, 8'h3b}; // write 0x3b to 0x011e - init_data[120] = {1'b1, 8'h29}; // write 0x29 to 0x011f + init_data[120] = {1'b1, 8'h28}; // write 0x28 to 0x011f init_data[121] = {2'b01, 7'h77}; init_data[122] = {1'b1, 8'h21}; init_data[123] = {1'b1, 8'h06}; // write 0x06 to 0x0121 init_data[124] = {1'b1, 8'h09}; // write 0x09 to 0x0122 init_data[125] = {1'b1, 8'h3b}; // write 0x3b to 0x0123 - init_data[126] = {1'b1, 8'h2a}; // write 0x2a to 0x0124 + init_data[126] = {1'b1, 8'h28}; // write 0x28 to 0x0124 init_data[127] = {2'b01, 7'h77}; init_data[128] = {1'b1, 8'h26}; init_data[129] = {1'b1, 8'h06}; // write 0x06 to 0x0126 init_data[130] = {1'b1, 8'h09}; // write 0x09 to 0x0127 init_data[131] = {1'b1, 8'h3b}; // write 0x3b to 0x0128 - init_data[132] = {1'b1, 8'h2a}; // write 0x2a to 0x0129 + init_data[132] = {1'b1, 8'h28}; // write 0x28 to 0x0129 init_data[133] = {2'b01, 7'h77}; init_data[134] = {1'b1, 8'h2b}; init_data[135] = {1'b1, 8'h06}; // write 0x06 to 0x012b init_data[136] = {1'b1, 8'h09}; // write 0x09 to 0x012c init_data[137] = {1'b1, 8'h3b}; // write 0x3b to 0x012d - init_data[138] = {1'b1, 8'h2b}; // write 0x2b to 0x012e + init_data[138] = {1'b1, 8'h28}; // write 0x28 to 0x012e init_data[139] = {2'b01, 7'h77}; init_data[140] = {1'b1, 8'h30}; init_data[141] = {1'b1, 8'h06}; // write 0x06 to 0x0130 init_data[142] = {1'b1, 8'h09}; // write 0x09 to 0x0131 init_data[143] = {1'b1, 8'h3b}; // write 0x3b to 0x0132 - init_data[144] = {1'b1, 8'h2b}; // write 0x2b to 0x0133 + init_data[144] = {1'b1, 8'h28}; // write 0x28 to 0x0133 init_data[145] = {2'b01, 7'h77}; init_data[146] = {1'b1, 8'h3a}; init_data[147] = {1'b1, 8'h06}; // write 0x06 to 0x013a init_data[148] = {1'b1, 8'h09}; // write 0x09 to 0x013b init_data[149] = {1'b1, 8'h3b}; // write 0x3b to 0x013c - init_data[150] = {1'b1, 8'h2b}; // write 0x2b to 0x013d + init_data[150] = {1'b1, 8'h28}; // write 0x28 to 0x013d init_data[151] = {2'b01, 7'h77}; init_data[152] = {1'b1, 8'h3f}; init_data[153] = {1'b1, 8'h00}; // write 0x00 to 0x013f @@ -414,13 +414,13 @@ initial begin init_data[247] = {1'b1, 8'h00}; // write 0x00 to 0x0268 init_data[248] = {1'b1, 8'h00}; // write 0x00 to 0x0269 init_data[249] = {1'b1, 8'h00}; // write 0x00 to 0x026a - init_data[250] = {1'b1, 8'h66}; // write 0x66 to 0x026b - init_data[251] = {1'b1, 8'h70}; // write 0x70 to 0x026c - init_data[252] = {1'b1, 8'h67}; // write 0x67 to 0x026d - init_data[253] = {1'b1, 8'h61}; // write 0x61 to 0x026e - init_data[254] = {1'b1, 8'h00}; // write 0x00 to 0x026f - init_data[255] = {1'b1, 8'h00}; // write 0x00 to 0x0270 - init_data[256] = {1'b1, 8'h00}; // write 0x00 to 0x0271 + init_data[250] = {1'b1, 8'h39}; // write 0x39 to 0x026b + init_data[251] = {1'b1, 8'h6b}; // write 0x6b to 0x026c + init_data[252] = {1'b1, 8'h32}; // write 0x32 to 0x026d + init_data[253] = {1'b1, 8'h5f}; // write 0x5f to 0x026e + init_data[254] = {1'b1, 8'h31}; // write 0x31 to 0x026f + init_data[255] = {1'b1, 8'h36}; // write 0x36 to 0x0270 + init_data[256] = {1'b1, 8'h31}; // write 0x31 to 0x0271 init_data[257] = {1'b1, 8'h00}; // write 0x00 to 0x0272 init_data[258] = {2'b01, 7'h77}; init_data[259] = {1'b1, 8'h01}; @@ -440,9 +440,9 @@ initial begin init_data[273] = {1'b1, 8'h00}; // write 0x00 to 0x030c init_data[274] = {1'b1, 8'h00}; // write 0x00 to 0x030d init_data[275] = {1'b1, 8'h00}; // write 0x00 to 0x030e - init_data[276] = {1'b1, 8'h00}; // write 0x00 to 0x030f - init_data[277] = {1'b1, 8'h80}; // write 0x80 to 0x0310 - init_data[278] = {1'b1, 8'h14}; // write 0x14 to 0x0311 + init_data[276] = {1'b1, 8'h10}; // write 0x10 to 0x030f + init_data[277] = {1'b1, 8'h42}; // write 0x42 to 0x0310 + init_data[278] = {1'b1, 8'h08}; // write 0x08 to 0x0311 init_data[279] = {1'b1, 8'h00}; // write 0x00 to 0x0312 init_data[280] = {1'b1, 8'h00}; // write 0x00 to 0x0313 init_data[281] = {1'b1, 8'h00}; // write 0x00 to 0x0314 @@ -452,35 +452,35 @@ initial begin init_data[285] = {1'b1, 8'h00}; // write 0x00 to 0x0318 init_data[286] = {1'b1, 8'h00}; // write 0x00 to 0x0319 init_data[287] = {1'b1, 8'h00}; // write 0x00 to 0x031a - init_data[288] = {1'b1, 8'h80}; // write 0x80 to 0x031b - init_data[289] = {1'b1, 8'h14}; // write 0x14 to 0x031c + init_data[288] = {1'b1, 8'h00}; // write 0x00 to 0x031b + init_data[289] = {1'b1, 8'h00}; // write 0x00 to 0x031c init_data[290] = {1'b1, 8'h00}; // write 0x00 to 0x031d init_data[291] = {1'b1, 8'h00}; // write 0x00 to 0x031e init_data[292] = {1'b1, 8'h00}; // write 0x00 to 0x031f init_data[293] = {1'b1, 8'h00}; // write 0x00 to 0x0320 - init_data[294] = {1'b1, 8'h80}; // write 0x80 to 0x0321 + init_data[294] = {1'b1, 8'h00}; // write 0x00 to 0x0321 init_data[295] = {1'b1, 8'h00}; // write 0x00 to 0x0322 init_data[296] = {1'b1, 8'h00}; // write 0x00 to 0x0323 init_data[297] = {1'b1, 8'h00}; // write 0x00 to 0x0324 init_data[298] = {1'b1, 8'h00}; // write 0x00 to 0x0325 - init_data[299] = {1'b1, 8'h80}; // write 0x80 to 0x0326 - init_data[300] = {1'b1, 8'h14}; // write 0x14 to 0x0327 + init_data[299] = {1'b1, 8'h00}; // write 0x00 to 0x0326 + init_data[300] = {1'b1, 8'h00}; // write 0x00 to 0x0327 init_data[301] = {1'b1, 8'h00}; // write 0x00 to 0x0328 init_data[302] = {1'b1, 8'h00}; // write 0x00 to 0x0329 init_data[303] = {1'b1, 8'h00}; // write 0x00 to 0x032a init_data[304] = {1'b1, 8'h00}; // write 0x00 to 0x032b - init_data[305] = {1'b1, 8'h80}; // write 0x80 to 0x032c + init_data[305] = {1'b1, 8'h00}; // write 0x00 to 0x032c init_data[306] = {1'b1, 8'h00}; // write 0x00 to 0x032d init_data[307] = {1'b1, 8'h00}; // write 0x00 to 0x032e init_data[308] = {1'b1, 8'h00}; // write 0x00 to 0x032f - init_data[309] = {1'b1, 8'h10}; // write 0x10 to 0x0330 - init_data[310] = {1'b1, 8'h42}; // write 0x42 to 0x0331 - init_data[311] = {1'b1, 8'h08}; // write 0x08 to 0x0332 + init_data[309] = {1'b1, 8'h00}; // write 0x00 to 0x0330 + init_data[310] = {1'b1, 8'h00}; // write 0x00 to 0x0331 + init_data[311] = {1'b1, 8'h00}; // write 0x00 to 0x0332 init_data[312] = {1'b1, 8'h00}; // write 0x00 to 0x0333 init_data[313] = {1'b1, 8'h00}; // write 0x00 to 0x0334 init_data[314] = {1'b1, 8'h00}; // write 0x00 to 0x0335 init_data[315] = {1'b1, 8'h00}; // write 0x00 to 0x0336 - init_data[316] = {1'b1, 8'h80}; // write 0x80 to 0x0337 + init_data[316] = {1'b1, 8'h00}; // write 0x00 to 0x0337 init_data[317] = {1'b1, 8'h00}; // write 0x00 to 0x0338 init_data[318] = {1'b1, 8'h1f}; // write 0x1f to 0x0339 init_data[319] = {2'b01, 7'h77}; @@ -655,9 +655,9 @@ initial begin init_data[488] = {2'b01, 7'h77}; init_data[489] = {1'b1, 8'h02}; init_data[490] = {1'b1, 8'h00}; // write 0x00 to 0x0a02 - init_data[491] = {1'b1, 8'h1f}; // write 0x1f to 0x0a03 - init_data[492] = {1'b1, 8'h0f}; // write 0x0f to 0x0a04 - init_data[493] = {1'b1, 8'h1f}; // write 0x1f to 0x0a05 + init_data[491] = {1'b1, 8'h03}; // write 0x03 to 0x0a03 + init_data[492] = {1'b1, 8'h01}; // write 0x01 to 0x0a04 + init_data[493] = {1'b1, 8'h03}; // write 0x03 to 0x0a05 init_data[494] = {2'b01, 7'h77}; init_data[495] = {1'b1, 8'h14}; init_data[496] = {1'b1, 8'h00}; // write 0x00 to 0x0a14 @@ -681,7 +681,7 @@ initial begin init_data[514] = {1'b1, 8'h0f}; // write 0x0f to 0x0b44 init_data[515] = {2'b01, 7'h77}; init_data[516] = {1'b1, 8'h4a}; - init_data[517] = {1'b1, 8'h00}; // write 0x00 to 0x0b4a + init_data[517] = {1'b1, 8'h1c}; // write 0x1c to 0x0b4a init_data[518] = {2'b01, 7'h77}; init_data[519] = {1'b1, 8'h57}; init_data[520] = {1'b1, 8'ha5}; // write 0xa5 to 0x0b57 diff --git a/fpga/lib/eth/example/HTG9200/fpga_10g/rtl/debounce_switch.v b/fpga/lib/eth/example/HTG9200/fpga_25g/rtl/debounce_switch.v similarity index 100% rename from fpga/lib/eth/example/HTG9200/fpga_10g/rtl/debounce_switch.v rename to fpga/lib/eth/example/HTG9200/fpga_25g/rtl/debounce_switch.v diff --git a/fpga/lib/eth/example/AU50/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/fpga/lib/eth/example/HTG9200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v similarity index 100% rename from fpga/lib/eth/example/AU50/fpga_10g/rtl/eth_xcvr_phy_wrapper.v rename to fpga/lib/eth/example/HTG9200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v diff --git a/fpga/lib/eth/example/HTG9200/fpga_10g/rtl/fpga.v b/fpga/lib/eth/example/HTG9200/fpga_25g/rtl/fpga.v similarity index 99% rename from fpga/lib/eth/example/HTG9200/fpga_10g/rtl/fpga.v rename to fpga/lib/eth/example/HTG9200/fpga_25g/rtl/fpga.v index d05252be8..70be6b273 100644 --- a/fpga/lib/eth/example/HTG9200/fpga_10g/rtl/fpga.v +++ b/fpga/lib/eth/example/HTG9200/fpga_25g/rtl/fpga.v @@ -38,7 +38,13 @@ module fpga ( input wire ref_clk_p, input wire ref_clk_n, + output wire clk_gty2_fdec, + output wire clk_gty2_finc, + input wire clk_gty2_intr_n, input wire clk_gty2_lol_n, + output wire clk_gty2_oe_n, + output wire clk_gty2_sync_n, + output wire clk_gty2_rst_n, /* * GPIO @@ -373,6 +379,12 @@ si5341_i2c_init_inst ( .start(1'b1) ); +assign clk_gty2_fdec = 1'b0; +assign clk_gty2_finc = 1'b0; +assign clk_gty2_oe_n = 1'b0; +assign clk_gty2_sync_n = 1'b1; +assign clk_gty2_rst_n = btn[0]; + // XGMII 10G PHY wire qsfp_reset = rst_125mhz_int || si5341_i2c_busy || !clk_gty2_lol_n; diff --git a/fpga/lib/eth/example/HTG9200/fpga_10g/rtl/fpga_core.v b/fpga/lib/eth/example/HTG9200/fpga_25g/rtl/fpga_core.v similarity index 100% rename from fpga/lib/eth/example/HTG9200/fpga_10g/rtl/fpga_core.v rename to fpga/lib/eth/example/HTG9200/fpga_25g/rtl/fpga_core.v diff --git a/fpga/lib/eth/example/HTG9200/fpga_10g/rtl/i2c_master.v b/fpga/lib/eth/example/HTG9200/fpga_25g/rtl/i2c_master.v similarity index 100% rename from fpga/lib/eth/example/HTG9200/fpga_10g/rtl/i2c_master.v rename to fpga/lib/eth/example/HTG9200/fpga_25g/rtl/i2c_master.v diff --git a/fpga/lib/eth/example/HTG9200/fpga_10g/rtl/sync_signal.v b/fpga/lib/eth/example/HTG9200/fpga_25g/rtl/sync_signal.v similarity index 100% rename from fpga/lib/eth/example/HTG9200/fpga_10g/rtl/sync_signal.v rename to fpga/lib/eth/example/HTG9200/fpga_25g/rtl/sync_signal.v diff --git a/fpga/lib/eth/example/HTG9200/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/HTG9200/fpga_25g/tb/fpga_core/Makefile similarity index 100% rename from fpga/lib/eth/example/HTG9200/fpga_10g/tb/fpga_core/Makefile rename to fpga/lib/eth/example/HTG9200/fpga_25g/tb/fpga_core/Makefile diff --git a/fpga/lib/eth/example/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/HTG9200/fpga_25g/tb/fpga_core/test_fpga_core.py similarity index 68% rename from fpga/lib/eth/example/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py rename to fpga/lib/eth/example/HTG9200/fpga_25g/tb/fpga_core/test_fpga_core.py index 95d86a84c..035693d12 100644 --- a/fpga/lib/eth/example/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/HTG9200/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -45,66 +45,56 @@ class TB: self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) - cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) + cocotb.start_soon(Clock(dut.clk, 2.56, units="ns").start()) + + dut.btn.setimmediatevalue(0) + dut.sw.setimmediatevalue(0) + + dut.uart_txd.setimmediatevalue(1) + dut.uart_rts.setimmediatevalue(1) # Ethernet - cocotb.start_soon(Clock(dut.qsfp_rx_clk_1, 6.4, units="ns").start()) - self.qsfp_1_source = XgmiiSource(dut.qsfp_rxd_1, dut.qsfp_rxc_1, dut.qsfp_rx_clk_1, dut.qsfp_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp_tx_clk_1, 6.4, units="ns").start()) - self.qsfp_1_sink = XgmiiSink(dut.qsfp_txd_1, dut.qsfp_txc_1, dut.qsfp_tx_clk_1, dut.qsfp_tx_rst_1) + self.qsfp_source = [] + self.qsfp_sink = [] - cocotb.start_soon(Clock(dut.qsfp_rx_clk_2, 6.4, units="ns").start()) - self.qsfp_2_source = XgmiiSource(dut.qsfp_rxd_2, dut.qsfp_rxc_2, dut.qsfp_rx_clk_2, dut.qsfp_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp_tx_clk_2, 6.4, units="ns").start()) - self.qsfp_2_sink = XgmiiSink(dut.qsfp_txd_2, dut.qsfp_txc_2, dut.qsfp_tx_clk_2, dut.qsfp_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp_rx_clk_3, 6.4, units="ns").start()) - self.qsfp_3_source = XgmiiSource(dut.qsfp_rxd_3, dut.qsfp_rxc_3, dut.qsfp_rx_clk_3, dut.qsfp_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp_tx_clk_3, 6.4, units="ns").start()) - self.qsfp_3_sink = XgmiiSink(dut.qsfp_txd_3, dut.qsfp_txc_3, dut.qsfp_tx_clk_3, dut.qsfp_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp_rx_clk_4, 6.4, units="ns").start()) - self.qsfp_4_source = XgmiiSource(dut.qsfp_rxd_4, dut.qsfp_rxc_4, dut.qsfp_rx_clk_4, dut.qsfp_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp_tx_clk_4, 6.4, units="ns").start()) - self.qsfp_4_sink = XgmiiSink(dut.qsfp_txd_4, dut.qsfp_txc_4, dut.qsfp_tx_clk_4, dut.qsfp_tx_rst_4) + for x in range(1, 10): + sources = [] + sinks = [] + for y in range(1, 5): + cocotb.start_soon(Clock(getattr(dut, f"qsfp_{x}_rx_clk_{y}"), 2.56, units="ns").start()) + source = XgmiiSource(getattr(dut, f"qsfp_{x}_rxd_{y}"), getattr(dut, f"qsfp_{x}_rxc_{y}"), getattr(dut, f"qsfp_{x}_rx_clk_{y}"), getattr(dut, f"qsfp_{x}_rx_rst_{y}")) + sources.append(source) + cocotb.start_soon(Clock(getattr(dut, f"qsfp_{x}_tx_clk_{y}"), 2.56, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"qsfp_{x}_txd_{y}"), getattr(dut, f"qsfp_{x}_txc_{y}"), getattr(dut, f"qsfp_{x}_tx_clk_{y}"), getattr(dut, f"qsfp_{x}_tx_rst_{y}")) + sinks.append(sink) + self.qsfp_source.append(sources) + self.qsfp_sink.append(sinks) async def init(self): self.dut.rst.setimmediatevalue(0) - self.dut.qsfp_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp_tx_rst_4.setimmediatevalue(0) + for x in range(1, 10): + for y in range(1, 5): + getattr(self.dut, f"qsfp_{x}_rx_rst_{y}").setimmediatevalue(0) + getattr(self.dut, f"qsfp_{x}_tx_rst_{y}").setimmediatevalue(0) for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 1 - self.dut.qsfp_rx_rst_1.value = 1 - self.dut.qsfp_tx_rst_1.value = 1 - self.dut.qsfp_rx_rst_2.value = 1 - self.dut.qsfp_tx_rst_2.value = 1 - self.dut.qsfp_rx_rst_3.value = 1 - self.dut.qsfp_tx_rst_3.value = 1 - self.dut.qsfp_rx_rst_4.value = 1 - self.dut.qsfp_tx_rst_4.value = 1 + for x in range(1, 10): + for y in range(1, 5): + getattr(self.dut, f"qsfp_{x}_rx_rst_{y}").value = 1 + getattr(self.dut, f"qsfp_{x}_tx_rst_{y}").value = 1 for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 0 - self.dut.qsfp_rx_rst_1.value = 0 - self.dut.qsfp_tx_rst_1.value = 0 - self.dut.qsfp_rx_rst_2.value = 0 - self.dut.qsfp_tx_rst_2.value = 0 - self.dut.qsfp_rx_rst_3.value = 0 - self.dut.qsfp_tx_rst_3.value = 0 - self.dut.qsfp_rx_rst_4.value = 0 - self.dut.qsfp_tx_rst_4.value = 0 + for x in range(1, 10): + for y in range(1, 5): + getattr(self.dut, f"qsfp_{x}_rx_rst_{y}").value = 0 + getattr(self.dut, f"qsfp_{x}_tx_rst_{y}").value = 0 @cocotb.test() @@ -124,11 +114,11 @@ async def run_test(dut): test_frame = XgmiiFrame.from_payload(test_pkt.build()) - await tb.qsfp_1_source.send(test_frame) + await tb.qsfp_source[0][0].send(test_frame) tb.log.info("receive ARP request") - rx_frame = await tb.qsfp_1_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -156,11 +146,11 @@ async def run_test(dut): resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - await tb.qsfp_1_source.send(resp_frame) + await tb.qsfp_source[0][0].send(resp_frame) tb.log.info("receive UDP packet") - rx_frame = await tb.qsfp_1_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) diff --git a/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/README.md b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/README.md new file mode 100644 index 000000000..7c285603e --- /dev/null +++ b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/README.md @@ -0,0 +1,28 @@ +# Verilog Ethernet HTG-9200 + HTG 6x QSFP28 FMC+ Example Design + +## Introduction + +This example design targets the HiTech Global HTG-9200 FPGA board with the HiTech Global HTG-FMC-X6QSFP28 FMC+ board installed on J9. + +The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. + +The design is configured to run all 15 QSFP28 modules synchronous to the GTY reference oscillator (U47) on the HTG-9200. This is done by forwarding the MGT reference clock for QSFP1 through the FPGA to the SYNC_C2M pins on the FMC+, which is connected as a reference input to the Si5341 PLL (U7) on the FMC+. + +* FPGA: xcvu9p-flgb2104-2-e +* PHY: 10G BASE-R PHY IP core and internal GTY transceiver + +## How to build + +Run make to build. Ensure that the Xilinx Vivado toolchain components are in PATH. + +## How to test + +Run make program to program the HTG-9200 board with Vivado. Then run + + netcat -u 192.168.1.128 1234 + +to open a UDP connection to port 1234. Any text entered into netcat will be echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 diff --git a/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/common/vivado.mk b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/common/vivado.mk new file mode 100644 index 000000000..1402e2382 --- /dev/null +++ b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/common/vivado.mk @@ -0,0 +1,137 @@ +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - space-separated list of source files +# INC_FILES - space-separated list of include files +# XDC_FILES - space-separated list of timing constraint files +# XCI_FILES - space-separated list of IP XCI files +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: fpga vivado tmpclean clean distclean + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include ../$(CONFIG) + +FPGA_TOP ?= fpga +PROJECT ?= $(FPGA_TOP) + +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) + +ifdef XDC_FILES + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +else + XDC_FILES_REL = $(PROJECT).xdc +endif + +################################################################### +# Main Targets +# +# all: build everything +# clean: remove output files and project files +################################################################### + +all: fpga + +fpga: $(PROJECT).bit + +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr + +tmpclean:: + -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean:: tmpclean + -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt + +distclean:: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file +create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ + echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ + echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ + echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ + for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl + vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) + +# synthesis run +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr + echo "open_project $(PROJECT).xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp + echo "open_project $(PROJECT).xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + echo "open_run impl_1" >> run_impl.tcl + echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl + echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# bit file +$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp + echo "open_project $(PROJECT).xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl + echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi + mkdir -p rev + COUNT=100; \ + while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga.xdc b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga.xdc new file mode 100644 index 000000000..e07da2558 --- /dev/null +++ b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga.xdc @@ -0,0 +1,1088 @@ +# XDC constraints for the HiTech Global HTG-9200 board +# part: xcvu9p-flgb2104-2-e + +# General configuration +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] + +# System clocks +# DDR4 clocks from U5 (200 MHz) +#set_property -dict {LOC C36 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_a_p] +#set_property -dict {LOC C37 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_a_n] +#create_clock -period 5.000 -name sys_clk_ddr4_a [get_ports sys_clk_ddr4_a_p] + +#set_property -dict {LOC BA34 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_b_p] +#set_property -dict {LOC BB34 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_b_n] +#create_clock -period 5.000 -name sys_clk_ddr4_b [get_ports sys_clk_ddr4_b_p] + +# refclk from U24 (200 MHz) +set_property -dict {LOC AV26 IOSTANDARD LVDS} [get_ports ref_clk_p] +set_property -dict {LOC AW26 IOSTANDARD LVDS} [get_ports ref_clk_n] +create_clock -period 5.000 -name ref_clk [get_ports ref_clk_p] + +# 80 MHz EMCCLK +#set_property -dict {LOC AL27 IOSTANDARD LVCMOS18} [get_ports emc_clk] +#create_clock -period 12.5 -name emc_clk [get_ports emc_clk] + +# PLL control +set_property -dict {LOC L24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_fdec}] +set_property -dict {LOC K25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_finc}] +set_property -dict {LOC K23 IOSTANDARD LVCMOS18} [get_ports {clk_gty2_intr_n}] +set_property -dict {LOC L25 IOSTANDARD LVCMOS18} [get_ports {clk_gty2_lol_n}] +set_property -dict {LOC L23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_oe_n}] +set_property -dict {LOC L22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_sync_n}] +set_property -dict {LOC K22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_rst_n}] + +#set_property -dict {LOC BE20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_sd_oe}] +#set_property -dict {LOC BD20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_out0_sel_i2cb}] + +set_false_path -to [get_ports {clk_gty2_fdec clk_gty2_finc clk_gty2_oe_n clk_gty2_sync_n clk_gty2_rst_n}] +set_output_delay 0 [get_ports {clk_gty2_fdec clk_gty2_finc clk_gty2_oe_n clk_gty2_sync_n clk_gty2_rst_n}] +set_false_path -from [get_ports {clk_gty2_intr_n clk_gty2_lol_n}] +set_input_delay 0 [get_ports {clk_gty2_intr_n clk_gty2_lol_n}] + +# LEDs +set_property -dict {LOC BA24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}] +set_property -dict {LOC BB24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}] +set_property -dict {LOC BC24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[2]}] +set_property -dict {LOC BD24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[3]}] +set_property -dict {LOC AP25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[4]}] +set_property -dict {LOC BD25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[5]}] +set_property -dict {LOC BC26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[6]}] +set_property -dict {LOC BC27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[7]}] + +set_false_path -to [get_ports {led[*]}] +set_output_delay 0 [get_ports {led[*]}] + +# Push buttons +set_property -dict {LOC B31 IOSTANDARD LVCMOS12} [get_ports {btn[0]}] +set_property -dict {LOC C31 IOSTANDARD LVCMOS12} [get_ports {btn[1]}] + +set_false_path -from [get_ports {btn[*]}] +set_input_delay 0 [get_ports {btn[*]}] + +# DIP switches +set_property -dict {LOC P33 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] +set_property -dict {LOC K34 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] +set_property -dict {LOC E35 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] +set_property -dict {LOC H38 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] +set_property -dict {LOC D35 IOSTANDARD LVCMOS12} [get_ports {sw[4]}] +set_property -dict {LOC D36 IOSTANDARD LVCMOS12} [get_ports {sw[5]}] +set_property -dict {LOC E37 IOSTANDARD LVCMOS12} [get_ports {sw[6]}] +set_property -dict {LOC F38 IOSTANDARD LVCMOS12} [get_ports {sw[7]}] + +set_false_path -from [get_ports {sw[*]}] +set_input_delay 0 [get_ports {sw[*]}] + +# GPIO +#set_property -dict {LOC AY25 IOSTANDARD LVCMOS18} [get_ports {gpio[0]}] +#set_property -dict {LOC AW25 IOSTANDARD LVCMOS18} [get_ports {gpio[1]}] +#set_property -dict {LOC AU26 IOSTANDARD LVCMOS18} [get_ports {gpio[2]}] +#set_property -dict {LOC BD26 IOSTANDARD LVCMOS18} [get_ports {gpio[3]}] +#set_property -dict {LOC BE27 IOSTANDARD LVCMOS18} [get_ports {gpio[4]}] +#set_property -dict {LOC BE26 IOSTANDARD LVCMOS18} [get_ports {gpio[5]}] +#set_property -dict {LOC AU25 IOSTANDARD LVCMOS18} [get_ports {gpio[6]}] +#set_property -dict {LOC AR26 IOSTANDARD LVCMOS18} [get_ports {gpio[7]}] + +#set_false_path -to [get_ports {gpio[*]}] +#set_output_delay 0 [get_ports {gpio[*]}] + +# UART +set_property -dict {LOC BB27 IOSTANDARD LVCMOS18} [get_ports uart_txd] +set_property -dict {LOC AY27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rxd] +set_property -dict {LOC BC28 IOSTANDARD LVCMOS18} [get_ports uart_rts] +set_property -dict {LOC AY28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_cts] +set_property -dict {LOC AY26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rst_n] +set_property -dict {LOC BB26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_suspend_n] +#set_property -dict {LOC AW28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[0]}] +#set_property -dict {LOC AV28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[1]}] +#set_property -dict {LOC AV27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[2]}] +#set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[3]}] + +set_false_path -to [get_ports {uart_rxd uart_cts uart_rst_n uart_suspend_n}] +set_output_delay 0 [get_ports {uart_rxd uart_cts uart_rst_n uart_suspend_n}] +set_false_path -from [get_ports {uart_txd uart_rts}] +set_input_delay 0 [get_ports {uart_txd uart_rts}] + +# I2C +set_property -dict {LOC BB21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_scl] +set_property -dict {LOC BC21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_sda] +set_property -dict {LOC BF20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_rst_n] + +set_false_path -to [get_ports {i2c_main_sda i2c_main_scl i2c_main_rst_n}] +set_output_delay 0 [get_ports {i2c_main_sda i2c_main_scl i2c_main_rst_n}] +set_false_path -from [get_ports {i2c_main_sda i2c_main_scl}] +set_input_delay 0 [get_ports {i2c_main_sda i2c_main_scl}] + +# QSPI flash +#set_property -dict {LOC AM26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[0]}] +#set_property -dict {LOC AN26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[1]}] +#set_property -dict {LOC AL25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[2]}] +#set_property -dict {LOC AM25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[3]}] +#set_property -dict {LOC BF27 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_cs_n}] + +#set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}] +#set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}] +#set_false_path -from [get_ports {qspi_1_dq}] +#set_input_delay 0 [get_ports {qspi_1_dq}] + +# DDR4 A +# set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[0]}] +# set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[1]}] +# set_property -dict {LOC D34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[2]}] +# set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[3]}] +# set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[4]}] +# set_property -dict {LOC D38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[5]}] +# set_property -dict {LOC A39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[6]}] +# set_property -dict {LOC C38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[7]}] +# set_property -dict {LOC B39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[8]}] +# set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[9]}] +# set_property -dict {LOC A10 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[10]}] +# set_property -dict {LOC D39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[11]}] +# set_property -dict {LOC C34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[12]}] +# set_property -dict {LOC A38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[13]}] +# set_property -dict {LOC A40 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[14]}] +# set_property -dict {LOC E36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[15]}] +# set_property -dict {LOC E38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[16]}] + +# set_property -dict {LOC B34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_act_n}] +# set_property -dict {LOC A37 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_alert_n}] + +# set_property -dict {LOC C39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_ba[0]}] +# set_property -dict {LOC E39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_ba[1]}] +# set_property -dict {LOC B40 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_bg[0]}] + +# set_property -dict {LOC D40 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_cke}] +# set_property -dict {LOC A32 IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_a_ck_t}] +# set_property -dict {LOC A33 IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_a_ck_c}] +# set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_cs_n}] + +# set_property -dict {LOC N28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[0]}] +# set_property -dict {LOC N26 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[1]}] +# set_property -dict {LOC R27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[2]}] +# set_property -dict {LOC P26 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[3]}] +# set_property -dict {LOC P28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[4]}] +# set_property -dict {LOC R26 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[5]}] +# set_property -dict {LOC T27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[6]}] +# set_property -dict {LOC T26 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[7]}] +# set_property -dict {LOC H29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[8]}] +# set_property -dict {LOC G27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[9]}] +# set_property -dict {LOC D28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[10]}] +# set_property -dict {LOC F27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[11]}] +# set_property -dict {LOC G29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[12]}] +# set_property -dict {LOC G26 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[13]}] +# set_property -dict {LOC E28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[14]}] +# set_property -dict {LOC E27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[15]}] +# set_property -dict {LOC H28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[16]}] +# set_property -dict {LOC L27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[17]}] +# set_property -dict {LOC J28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[18]}] +# set_property -dict {LOC H27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[19]}] +# set_property -dict {LOC J29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[20]}] +# set_property -dict {LOC M27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[21]}] +# set_property -dict {LOC K28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[22]}] +# set_property -dict {LOC J28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[23]}] +# set_property -dict {LOC E30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[24]}] +# set_property -dict {LOC B29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[25]}] +# set_property -dict {LOC A29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[26]}] +# set_property -dict {LOC C29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[27]}] +# set_property -dict {LOC D30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[28]}] +# set_property -dict {LOC B30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[29]}] +# set_property -dict {LOC A30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[30]}] +# set_property -dict {LOC D29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[31]}] +# set_property -dict {LOC T32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[32]}] +# set_property -dict {LOC T33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[33]}] +# set_property -dict {LOC U31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[34]}] +# set_property -dict {LOC U32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[35]}] +# set_property -dict {LOC V31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[36]}] +# set_property -dict {LOC R33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[37]}] +# set_property -dict {LOC U30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[38]}] +# set_property -dict {LOC T30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[39]}] +# set_property -dict {LOC F32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[40]}] +# set_property -dict {LOC E33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[41]}] +# set_property -dict {LOC E32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[42]}] +# set_property -dict {LOC F33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[43]}] +# set_property -dict {LOC G31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[44]}] +# set_property -dict {LOC H32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[45]}] +# set_property -dict {LOC H31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[46]}] +# set_property -dict {LOC G32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[47]}] +# set_property -dict {LOC R32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[48]}] +# set_property -dict {LOC P32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[49]}] +# set_property -dict {LOC R31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[50]}] +# set_property -dict {LOC N32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[51]}] +# set_property -dict {LOC N31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[52]}] +# set_property -dict {LOC N34 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[53]}] +# set_property -dict {LOC P31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[54]}] +# set_property -dict {LOC N33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[55]}] +# set_property -dict {LOC L30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[56]}] +# set_property -dict {LOC K32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[57]}] +# set_property -dict {LOC M30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[58]}] +# set_property -dict {LOC K33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[59]}] +# set_property -dict {LOC J31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[60]}] +# set_property -dict {LOC L33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[61]}] +# set_property -dict {LOC K31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[62]}] +# set_property -dict {LOC L32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[63]}] +# set_property -dict {LOC J35 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[64]}] +# set_property -dict {LOC G34 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[65]}] +# set_property -dict {LOC G37 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[66]}] +# set_property -dict {LOC H34 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[67]}] +# set_property -dict {LOC J36 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[68]}] +# set_property -dict {LOC F35 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[69]}] +# set_property -dict {LOC F37 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[70]}] +# set_property -dict {LOC F34 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[71]}] + +# set_property -dict {LOC P29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[0]}] +# set_property -dict {LOC N29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[0]}] +# set_property -dict {LOC F28 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[1]}] +# set_property -dict {LOC F29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[1]}] +# set_property -dict {LOC K26 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[2]}] +# set_property -dict {LOC K27 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[2]}] +# set_property -dict {LOC A27 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[3]}] +# set_property -dict {LOC A28 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[3]}] +# set_property -dict {LOC V32 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[4]}] +# set_property -dict {LOC V33 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[4]}] +# set_property -dict {LOC J33 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[5]}] +# set_property -dict {LOC H33 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[5]}] +# set_property -dict {LOC M34 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[6]}] +# set_property -dict {LOC L34 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[6]}] +# set_property -dict {LOC K30 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[7]}] +# set_property -dict {LOC J30 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[7]}] +# set_property -dict {LOC H36 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[8]}] +# set_property -dict {LOC G36 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[8]}] + +# set_property -dict {LOC T28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[0]}] +# set_property -dict {LOC J26 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[1]}] +# set_property -dict {LOC M29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[2]}] +# set_property -dict {LOC C27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[3]}] +# set_property -dict {LOC U34 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[4]}] +# set_property -dict {LOC G30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[5]}] +# set_property -dict {LOC R30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[6]}] +# set_property -dict {LOC M31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[7]}] +# set_property -dict {LOC H37 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[8]}] + +# set_property -dict {LOC A34 IOSTANDARD LVCMOS12} [get_ports {ddr4_a_odt}] +# set_property -dict {LOC E40 IOSTANDARD LVCMOS12} [get_ports {ddr4_a_rst_n}] +# set_property -dict {LOC D31 IOSTANDARD LVCMOS12} [get_ports {ddr4_a_par}] +# set_property -dict {LOC B37 IOSTANDARD LVCMOS12} [get_ports {ddr4_a_ten}] + +# DDR4 B +# set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[0]}] +# set_property -dict {LOC BA35 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[1]}] +# set_property -dict {LOC AV34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[2]}] +# set_property -dict {LOC BD34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[3]}] +# set_property -dict {LOC BC34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[4]}] +# set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[5]}] +# set_property -dict {LOC BE37 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[6]}] +# set_property -dict {LOC BF38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[7]}] +# set_property -dict {LOC BF37 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[8]}] +# set_property -dict {LOC AW34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[9]}] +# set_property -dict {LOC BD35 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[10]}] +# set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[11]}] +# set_property -dict {LOC BD36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[12]}] +# set_property -dict {LOC BE38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[13]}] +# set_property -dict {LOC BB36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[14]}] +# set_property -dict {LOC BF40 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[15]}] +# set_property -dict {LOC BE40 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[16]}] + +# set_property -dict {LOC BF35 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_act_n}] +# set_property -dict {LOC BD39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_alert_n}] + +# set_property -dict {LOC BB38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_ba[0]}] +# set_property -dict {LOC BD40 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_ba[1]}] +# set_property -dict {LOC BC36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_bg[0]}] + +# set_property -dict {LOC BB35 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_cke}] +# set_property -dict {LOC BB37 IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_b_ck_t}] +# set_property -dict {LOC BC37 IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_b_ck_c}] +# set_property -dict {LOC BE36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_cs_n}] + +# set_property -dict {LOC AP29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[0]}] +# set_property -dict {LOC AR30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[1]}] +# set_property -dict {LOC AN29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[2]}] +# set_property -dict {LOC AP30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[3]}] +# set_property -dict {LOC AL29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[4]}] +# set_property -dict {LOC AN31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[5]}] +# set_property -dict {LOC AL30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[6]}] +# set_property -dict {LOC AM31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[7]}] +# set_property -dict {LOC AT29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[8]}] +# set_property -dict {LOC AU32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[9]}] +# set_property -dict {LOC AU30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[10]}] +# set_property -dict {LOC AV31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[11]}] +# set_property -dict {LOC AT30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[12]}] +# set_property -dict {LOC AW31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[13]}] +# set_property -dict {LOC AU31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[14]}] +# set_property -dict {LOC AV32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[15]}] +# set_property -dict {LOC BB30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[16]}] +# set_property -dict {LOC AY32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[17]}] +# set_property -dict {LOC BA30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[18]}] +# set_property -dict {LOC AY30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[19]}] +# set_property -dict {LOC BA29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[20]}] +# set_property -dict {LOC AY31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[21]}] +# set_property -dict {LOC BB29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[22]}] +# set_property -dict {LOC BB31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[23]}] +# set_property -dict {LOC BF30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[24]}] +# set_property -dict {LOC BE32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[25]}] +# set_property -dict {LOC BD29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[26]}] +# set_property -dict {LOC BD33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[27]}] +# set_property -dict {LOC BE30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[28]}] +# set_property -dict {LOC BE33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[29]}] +# set_property -dict {LOC BC29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[30]}] +# set_property -dict {LOC BE31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[31]}] +# set_property -dict {LOC Y33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[32]}] +# set_property -dict {LOC W30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[33]}] +# set_property -dict {LOC W34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[34]}] +# set_property -dict {LOC Y32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[35]}] +# set_property -dict {LOC AA34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[36]}] +# set_property -dict {LOC Y30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[37]}] +# set_property -dict {LOC AB34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[38]}] +# set_property -dict {LOC W33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[39]}] +# set_property -dict {LOC AJ31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[40]}] +# set_property -dict {LOC AG30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[41]}] +# set_property -dict {LOC AJ28 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[42]}] +# set_property -dict {LOC AK28 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[43]}] +# set_property -dict {LOC AK31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[44]}] +# set_property -dict {LOC AG29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[45]}] +# set_property -dict {LOC AJ30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[46]}] +# set_property -dict {LOC AJ29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[47]}] +# set_property -dict {LOC AC32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[48]}] +# set_property -dict {LOC AE33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[49]}] +# set_property -dict {LOC AC33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[50]}] +# set_property -dict {LOC AD34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[51]}] +# set_property -dict {LOC AC34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[52]}] +# set_property -dict {LOC AD33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[53]}] +# set_property -dict {LOC AE30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[54]}] +# set_property -dict {LOC AF30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[55]}] +# set_property -dict {LOC AF34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[56]}] +# set_property -dict {LOC AJ33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[57]}] +# set_property -dict {LOC AH33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[58]}] +# set_property -dict {LOC AG32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[59]}] +# set_property -dict {LOC AF33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[60]}] +# set_property -dict {LOC AG31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[61]}] +# set_property -dict {LOC AF32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[62]}] +# set_property -dict {LOC AG34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[63]}] +# set_property -dict {LOC AN34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[64]}] +# set_property -dict {LOC AL34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[65]}] +# set_property -dict {LOC AP34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[66]}] +# set_property -dict {LOC AM32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[67]}] +# set_property -dict {LOC AR33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[68]}] +# set_property -dict {LOC AL32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[69]}] +# set_property -dict {LOC AP33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[70]}] +# set_property -dict {LOC AM34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[71]}] + +# set_property -dict {LOC AM29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[0]}] +# set_property -dict {LOC AM30 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[0]}] +# set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[1]}] +# set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[1]}] +# set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[2]}] +# set_property -dict {LOC BB32 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[2]}] +# set_property -dict {LOC BD30 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[3]}] +# set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[3]}] +# set_property -dict {LOC W31 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[4]}] +# set_property -dict {LOC Y31 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[4]}] +# set_property -dict {LOC AH28 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[5]}] +# set_property -dict {LOC AH29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[5]}] +# set_property -dict {LOC AC31 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[6]}] +# set_property -dict {LOC AD31 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[6]}] +# set_property -dict {LOC AH31 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[7]}] +# set_property -dict {LOC AH32 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[7]}] +# set_property -dict {LOC AN32 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[8]}] +# set_property -dict {LOC AN33 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[8]}] + +# set_property -dict {LOC AP31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[0]}] +# set_property -dict {LOC AW29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[1]}] +# set_property -dict {LOC BC31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[2]}] +# set_property -dict {LOC BF32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[3]}] +# set_property -dict {LOC AA32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[4]}] +# set_property -dict {LOC AJ27 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[5]}] +# set_property -dict {LOC AE31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[6]}] +# set_property -dict {LOC AH34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[7]}] +# set_property -dict {LOC AT33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[8]}] + +# set_property -dict {LOC BE35 IOSTANDARD LVCMOS12} [get_ports {ddr4_b_odt}] +# set_property -dict {LOC AY36 IOSTANDARD LVCMOS12} [get_ports {ddr4_b_rst_n}] +# set_property -dict {LOC AV33 IOSTANDARD LVCMOS12} [get_ports {ddr4_b_par}] +# set_property -dict {LOC BF39 IOSTANDARD LVCMOS12} [get_ports {ddr4_b_ten}] + +# QSFP28 Interfaces + +# QSFP 1 +set_property -dict {LOC G40 } [get_ports {qsfp_1_tx_p[1]}] ;# MGTYTXP0_133 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC G41 } [get_ports {qsfp_1_tx_n[1]}] ;# MGTYTXN0_133 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC J45 } [get_ports {qsfp_1_rx_p[1]}] ;# MGTYRXP0_133 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC J46 } [get_ports {qsfp_1_rx_n[1]}] ;# MGTYRXN0_133 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC E42 } [get_ports {qsfp_1_tx_p[2]}] ;# MGTYTXP1_133 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC E43 } [get_ports {qsfp_1_tx_n[2]}] ;# MGTYTXN1_133 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC H43 } [get_ports {qsfp_1_rx_p[2]}] ;# MGTYRXP1_133 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC H44 } [get_ports {qsfp_1_rx_n[2]}] ;# MGTYRXN1_133 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC C42 } [get_ports {qsfp_1_tx_p[0]}] ;# MGTYTXP2_133 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC C43 } [get_ports {qsfp_1_tx_n[0]}] ;# MGTYTXN2_133 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC F45 } [get_ports {qsfp_1_rx_p[0]}] ;# MGTYRXP2_133 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC F46 } [get_ports {qsfp_1_rx_n[0]}] ;# MGTYRXN2_133 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC A42 } [get_ports {qsfp_1_tx_p[3]}] ;# MGTYTXP3_133 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC A43 } [get_ports {qsfp_1_tx_n[3]}] ;# MGTYTXN3_133 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC D45 } [get_ports {qsfp_1_rx_p[3]}] ;# MGTYRXP3_133 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC D46 } [get_ports {qsfp_1_rx_n[3]}] ;# MGTYRXN3_133 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC K38 } [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK1P_133 from U48.28 OUT1_P +set_property -dict {LOC K39 } [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK1N_133 from U48.27 OUT1_N +set_property -dict {LOC BB20 IOSTANDARD LVCMOS18} [get_ports qsfp_1_resetl] +set_property -dict {LOC BE21 IOSTANDARD LVCMOS18} [get_ports qsfp_1_modprsl] +set_property -dict {LOC BA20 IOSTANDARD LVCMOS18} [get_ports qsfp_1_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_1_mgt_refclk [get_ports qsfp_1_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_1_mgt_refclk [get_ports qsfp_1_mgt_refclk_p] + +# QSFP 2 +set_property -dict {LOC N40 } [get_ports {qsfp_2_tx_p[1]}] ;# MGTYTXP0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC N41 } [get_ports {qsfp_2_tx_n[1]}] ;# MGTYTXN0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC N45 } [get_ports {qsfp_2_rx_p[1]}] ;# MGTYRXP0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC N46 } [get_ports {qsfp_2_rx_n[1]}] ;# MGTYRXN0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M38 } [get_ports {qsfp_2_tx_p[2]}] ;# MGTYTXP1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M39 } [get_ports {qsfp_2_tx_n[2]}] ;# MGTYTXN1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M43 } [get_ports {qsfp_2_rx_p[2]}] ;# MGTYRXP1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M44 } [get_ports {qsfp_2_rx_n[2]}] ;# MGTYRXN1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L40 } [get_ports {qsfp_2_tx_p[0]}] ;# MGTYTXP2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L41 } [get_ports {qsfp_2_tx_n[0]}] ;# MGTYTXN2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L45 } [get_ports {qsfp_2_rx_p[0]}] ;# MGTYRXP2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L46 } [get_ports {qsfp_2_rx_n[0]}] ;# MGTYRXN2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC J40 } [get_ports {qsfp_2_tx_p[3]}] ;# MGTYTXP3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC J41 } [get_ports {qsfp_2_tx_n[3]}] ;# MGTYTXN3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC K43 } [get_ports {qsfp_2_rx_p[3]}] ;# MGTYRXP3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC K44 } [get_ports {qsfp_2_rx_n[3]}] ;# MGTYRXN3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC R36 } [get_ports qsfp_2_mgt_refclk_p] ;# MGTREFCLK0P_132 from U48.35 OUT3_P +set_property -dict {LOC R37 } [get_ports qsfp_2_mgt_refclk_n] ;# MGTREFCLK0N_132 from U48.34 OUT3_N +set_property -dict {LOC BE22 IOSTANDARD LVCMOS18} [get_ports qsfp_2_resetl] +set_property -dict {LOC BD21 IOSTANDARD LVCMOS18} [get_ports qsfp_2_modprsl] +set_property -dict {LOC BF22 IOSTANDARD LVCMOS18} [get_ports qsfp_2_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_2_mgt_refclk [get_ports qsfp_2_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_2_mgt_refclk [get_ports qsfp_2_mgt_refclk_p] + +# QSFP 3 +set_property -dict {LOC U40 } [get_ports {qsfp_3_tx_p[1]}] ;# MGTYTXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC U41 } [get_ports {qsfp_3_tx_n[1]}] ;# MGTYTXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC U45 } [get_ports {qsfp_3_rx_p[1]}] ;# MGTYRXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC U46 } [get_ports {qsfp_3_rx_n[1]}] ;# MGTYRXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC T38 } [get_ports {qsfp_3_tx_p[2]}] ;# MGTYTXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC T39 } [get_ports {qsfp_3_tx_n[2]}] ;# MGTYTXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC T43 } [get_ports {qsfp_3_rx_p[2]}] ;# MGTYRXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC T44 } [get_ports {qsfp_3_rx_n[2]}] ;# MGTYRXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC R40 } [get_ports {qsfp_3_tx_p[0]}] ;# MGTYTXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC R41 } [get_ports {qsfp_3_tx_n[0]}] ;# MGTYTXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC R45 } [get_ports {qsfp_3_rx_p[0]}] ;# MGTYRXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC R46 } [get_ports {qsfp_3_rx_n[0]}] ;# MGTYRXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC P38 } [get_ports {qsfp_3_tx_p[3]}] ;# MGTYTXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC P39 } [get_ports {qsfp_3_tx_n[3]}] ;# MGTYTXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC P43 } [get_ports {qsfp_3_rx_p[3]}] ;# MGTYRXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC P44 } [get_ports {qsfp_3_rx_n[3]}] ;# MGTYRXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC W36 } [get_ports qsfp_3_mgt_refclk_p] ;# MGTREFCLK0P_131 from U48.38 OUT4_P +set_property -dict {LOC W37 } [get_ports qsfp_3_mgt_refclk_n] ;# MGTREFCLK0N_131 from U48.37 OUT4_N +set_property -dict {LOC AY23 IOSTANDARD LVCMOS18} [get_ports qsfp_3_resetl] +set_property -dict {LOC AY22 IOSTANDARD LVCMOS18} [get_ports qsfp_3_modprsl] +set_property -dict {LOC BA22 IOSTANDARD LVCMOS18} [get_ports qsfp_3_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_3_mgt_refclk [get_ports qsfp_3_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_3_mgt_refclk [get_ports qsfp_3_mgt_refclk_p] + +# QSFP 4 +set_property -dict {LOC AA40} [get_ports {qsfp_4_tx_p[1]}] ;# MGTYTXP0_130 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AA41} [get_ports {qsfp_4_tx_n[1]}] ;# MGTYTXN0_130 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AA45} [get_ports {qsfp_4_rx_p[1]}] ;# MGTYRXP0_130 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AA46} [get_ports {qsfp_4_rx_n[1]}] ;# MGTYRXN0_130 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y38 } [get_ports {qsfp_4_tx_p[2]}] ;# MGTYTXP1_130 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y39 } [get_ports {qsfp_4_tx_n[2]}] ;# MGTYTXN1_130 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y43 } [get_ports {qsfp_4_rx_p[2]}] ;# MGTYRXP1_130 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y44 } [get_ports {qsfp_4_rx_n[2]}] ;# MGTYRXN1_130 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W40 } [get_ports {qsfp_4_tx_p[0]}] ;# MGTYTXP2_130 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W41 } [get_ports {qsfp_4_tx_n[0]}] ;# MGTYTXN2_130 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W45 } [get_ports {qsfp_4_rx_p[0]}] ;# MGTYRXP2_130 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W46 } [get_ports {qsfp_4_rx_n[0]}] ;# MGTYRXN2_130 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V38 } [get_ports {qsfp_4_tx_p[3]}] ;# MGTYTXP3_130 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V39 } [get_ports {qsfp_4_tx_n[3]}] ;# MGTYTXN3_130 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V43 } [get_ports {qsfp_4_rx_p[3]}] ;# MGTYRXP3_130 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V44 } [get_ports {qsfp_4_rx_n[3]}] ;# MGTYRXN3_130 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AC36} [get_ports qsfp_4_mgt_refclk_p] ;# MGTREFCLK0P_130 from U48.42 OUT5_P +set_property -dict {LOC AC37} [get_ports qsfp_4_mgt_refclk_n] ;# MGTREFCLK0N_130 from U48.41 OUT5_N +set_property -dict {LOC BC22 IOSTANDARD LVCMOS18} [get_ports qsfp_4_resetl] +set_property -dict {LOC BB22 IOSTANDARD LVCMOS18} [get_ports qsfp_4_modprsl] +set_property -dict {LOC BA23 IOSTANDARD LVCMOS18} [get_ports qsfp_4_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_4_mgt_refclk [get_ports qsfp_4_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_4_mgt_refclk [get_ports qsfp_4_mgt_refclk_p] + +# QSFP 5 +set_property -dict {LOC AE40} [get_ports {qsfp_5_tx_p[1]}] ;# MGTYTXP0_129 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AE41} [get_ports {qsfp_5_tx_n[1]}] ;# MGTYTXN0_129 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AE45} [get_ports {qsfp_5_rx_p[1]}] ;# MGTYRXP0_129 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AE46} [get_ports {qsfp_5_rx_n[1]}] ;# MGTYRXN0_129 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AD38} [get_ports {qsfp_5_tx_p[2]}] ;# MGTYTXP1_129 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AD39} [get_ports {qsfp_5_tx_n[2]}] ;# MGTYTXN1_129 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AD43} [get_ports {qsfp_5_rx_p[2]}] ;# MGTYRXP1_129 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AD44} [get_ports {qsfp_5_rx_n[2]}] ;# MGTYRXN1_129 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AC40} [get_ports {qsfp_5_tx_p[3]}] ;# MGTYTXP2_129 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AC41} [get_ports {qsfp_5_tx_n[3]}] ;# MGTYTXN2_129 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AC45} [get_ports {qsfp_5_rx_p[3]}] ;# MGTYRXP2_129 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AC46} [get_ports {qsfp_5_rx_n[3]}] ;# MGTYRXN2_129 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AB38} [get_ports {qsfp_5_tx_p[0]}] ;# MGTYTXP3_129 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AB39} [get_ports {qsfp_5_tx_n[0]}] ;# MGTYTXN3_129 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AB43} [get_ports {qsfp_5_rx_p[0]}] ;# MGTYRXP3_129 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AB44} [get_ports {qsfp_5_rx_n[0]}] ;# MGTYRXN3_129 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AG36} [get_ports qsfp_5_mgt_refclk_p] ;# MGTREFCLK0P_129 from U48.24 OUT0_P +set_property -dict {LOC AG37} [get_ports qsfp_5_mgt_refclk_n] ;# MGTREFCLK0N_129 from U48.23 OUT0_N +set_property -dict {LOC BD23 IOSTANDARD LVCMOS18} [get_ports qsfp_5_resetl] +set_property -dict {LOC BE23 IOSTANDARD LVCMOS18} [get_ports qsfp_5_modprsl] +set_property -dict {LOC BF23 IOSTANDARD LVCMOS18} [get_ports qsfp_5_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_5_mgt_refclk [get_ports qsfp_5_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_5_mgt_refclk [get_ports qsfp_5_mgt_refclk_p] + +# QSFP 6 +set_property -dict {LOC AJ40} [get_ports {qsfp_6_tx_p[1]}] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AJ41} [get_ports {qsfp_6_tx_n[1]}] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AJ45} [get_ports {qsfp_6_rx_p[1]}] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AJ46} [get_ports {qsfp_6_rx_n[1]}] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH38} [get_ports {qsfp_6_tx_p[2]}] ;# MGTYTXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH39} [get_ports {qsfp_6_tx_n[2]}] ;# MGTYTXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH43} [get_ports {qsfp_6_rx_p[2]}] ;# MGTYRXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH44} [get_ports {qsfp_6_rx_n[2]}] ;# MGTYRXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG40} [get_ports {qsfp_6_tx_p[0]}] ;# MGTYTXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG41} [get_ports {qsfp_6_tx_n[0]}] ;# MGTYTXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG45} [get_ports {qsfp_6_rx_p[0]}] ;# MGTYRXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG46} [get_ports {qsfp_6_rx_n[0]}] ;# MGTYRXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AF38} [get_ports {qsfp_6_tx_p[3]}] ;# MGTYTXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AF39} [get_ports {qsfp_6_tx_n[3]}] ;# MGTYTXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AF43} [get_ports {qsfp_6_rx_p[3]}] ;# MGTYRXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AF44} [get_ports {qsfp_6_rx_n[3]}] ;# MGTYRXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AL36} [get_ports qsfp_6_mgt_refclk_p] ;# MGTREFCLK0P_128 from U48.59 OUT9_P +set_property -dict {LOC AL37} [get_ports qsfp_6_mgt_refclk_n] ;# MGTREFCLK0N_128 from U48.58 OUT9_N +set_property -dict {LOC AW24 IOSTANDARD LVCMOS18} [get_ports qsfp_6_resetl] +set_property -dict {LOC AR23 IOSTANDARD LVCMOS18} [get_ports qsfp_6_modprsl] +set_property -dict {LOC AV24 IOSTANDARD LVCMOS18} [get_ports qsfp_6_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_6_mgt_refclk [get_ports qsfp_6_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_6_mgt_refclk [get_ports qsfp_6_mgt_refclk_p] + +# QSFP 7 +set_property -dict {LOC AN40} [get_ports {qsfp_7_tx_p[1]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AN41} [get_ports {qsfp_7_tx_n[1]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AN45} [get_ports {qsfp_7_rx_p[1]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AN46} [get_ports {qsfp_7_rx_n[1]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM38} [get_ports {qsfp_7_tx_p[2]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM39} [get_ports {qsfp_7_tx_n[2]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM43} [get_ports {qsfp_7_rx_p[2]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM44} [get_ports {qsfp_7_rx_n[2]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL40} [get_ports {qsfp_7_tx_p[0]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL41} [get_ports {qsfp_7_tx_n[0]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL45} [get_ports {qsfp_7_rx_p[0]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL46} [get_ports {qsfp_7_rx_n[0]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK38} [get_ports {qsfp_7_tx_p[3]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK39} [get_ports {qsfp_7_tx_n[3]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK43} [get_ports {qsfp_7_rx_p[3]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK44} [get_ports {qsfp_7_rx_n[3]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AR36} [get_ports qsfp_7_mgt_refclk_p] ;# MGTREFCLK0P_127 from U48.54 OUT8_P +set_property -dict {LOC AR37} [get_ports qsfp_7_mgt_refclk_n] ;# MGTREFCLK0N_127 from U48.53 OUT8_N +set_property -dict {LOC AU24 IOSTANDARD LVCMOS18} [get_ports qsfp_7_resetl] +set_property -dict {LOC AN23 IOSTANDARD LVCMOS18} [get_ports qsfp_7_modprsl] +set_property -dict {LOC AT24 IOSTANDARD LVCMOS18} [get_ports qsfp_7_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_7_mgt_refclk [get_ports qsfp_7_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_7_mgt_refclk [get_ports qsfp_7_mgt_refclk_p] + +# QSFP 8 +set_property -dict {LOC AU40} [get_ports {qsfp_8_tx_p[1]}] ;# MGTYTXP0_126 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AU41} [get_ports {qsfp_8_tx_n[1]}] ;# MGTYTXN0_126 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AU45} [get_ports {qsfp_8_rx_p[1]}] ;# MGTYRXP0_126 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AU46} [get_ports {qsfp_8_rx_n[1]}] ;# MGTYRXN0_126 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT38} [get_ports {qsfp_8_tx_p[2]}] ;# MGTYTXP1_126 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT39} [get_ports {qsfp_8_tx_n[2]}] ;# MGTYTXN1_126 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT43} [get_ports {qsfp_8_rx_p[2]}] ;# MGTYRXP1_126 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT44} [get_ports {qsfp_8_rx_n[2]}] ;# MGTYRXN1_126 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR40} [get_ports {qsfp_8_tx_p[0]}] ;# MGTYTXP2_126 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR41} [get_ports {qsfp_8_tx_n[0]}] ;# MGTYTXN2_126 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR45} [get_ports {qsfp_8_rx_p[0]}] ;# MGTYRXP2_126 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR46} [get_ports {qsfp_8_rx_n[0]}] ;# MGTYRXN2_126 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AP38} [get_ports {qsfp_8_tx_p[3]}] ;# MGTYTXP3_126 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AP39} [get_ports {qsfp_8_tx_n[3]}] ;# MGTYTXN3_126 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AP43} [get_ports {qsfp_8_rx_p[3]}] ;# MGTYRXP3_126 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AP44} [get_ports {qsfp_8_rx_n[3]}] ;# MGTYRXN3_126 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AV38} [get_ports qsfp_8_mgt_refclk_p] ;# MGTREFCLK0P_126 from U48.45 OUT6_P +set_property -dict {LOC AV39} [get_ports qsfp_8_mgt_refclk_n] ;# MGTREFCLK0N_126 from U48.44 OUT6_N +set_property -dict {LOC AN24 IOSTANDARD LVCMOS18} [get_ports qsfp_8_resetl] +set_property -dict {LOC AP24 IOSTANDARD LVCMOS18} [get_ports qsfp_8_modprsl] +set_property -dict {LOC AP23 IOSTANDARD LVCMOS18} [get_ports qsfp_8_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_8_mgt_refclk [get_ports qsfp_8_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_8_mgt_refclk [get_ports qsfp_8_mgt_refclk_p] + +# QSFP 9 +set_property -dict {LOC BF42} [get_ports {qsfp_9_tx_p[1]}] ;# MGTYTXP0_125 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BF43} [get_ports {qsfp_9_tx_n[1]}] ;# MGTYTXN0_125 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BC45} [get_ports {qsfp_9_rx_p[1]}] ;# MGTYRXP0_125 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BC46} [get_ports {qsfp_9_rx_n[1]}] ;# MGTYRXN0_125 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BD42} [get_ports {qsfp_9_tx_p[2]}] ;# MGTYTXP1_125 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BD43} [get_ports {qsfp_9_tx_n[2]}] ;# MGTYTXN1_125 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BA45} [get_ports {qsfp_9_rx_p[2]}] ;# MGTYRXP1_125 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BA46} [get_ports {qsfp_9_rx_n[2]}] ;# MGTYRXN1_125 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BB42} [get_ports {qsfp_9_tx_p[0]}] ;# MGTYTXP2_125 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BB43} [get_ports {qsfp_9_tx_n[0]}] ;# MGTYTXN2_125 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW45} [get_ports {qsfp_9_rx_p[0]}] ;# MGTYRXP2_125 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW46} [get_ports {qsfp_9_rx_n[0]}] ;# MGTYRXN2_125 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW40} [get_ports {qsfp_9_tx_p[3]}] ;# MGTYTXP3_125 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW41} [get_ports {qsfp_9_tx_n[3]}] ;# MGTYTXN3_125 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AV43} [get_ports {qsfp_9_rx_p[3]}] ;# MGTYRXP3_125 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AV44} [get_ports {qsfp_9_rx_n[3]}] ;# MGTYRXN3_125 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BA40} [get_ports qsfp_9_mgt_refclk_p] ;# MGTREFCLK0P_125 from U48.51 OUT7_P +set_property -dict {LOC BA41} [get_ports qsfp_9_mgt_refclk_n] ;# MGTREFCLK0N_125 from U48.50 OUT7_N +set_property -dict {LOC AM24 IOSTANDARD LVCMOS18} [get_ports qsfp_9_resetl] +set_property -dict {LOC AM22 IOSTANDARD LVCMOS18} [get_ports qsfp_9_modprsl] +set_property -dict {LOC AL24 IOSTANDARD LVCMOS18} [get_ports qsfp_9_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_9_mgt_refclk [get_ports qsfp_9_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_9_mgt_refclk [get_ports qsfp_9_mgt_refclk_p] + +# SMA (GTY) +#set_property -dict {LOC E9 } [get_ports {sma_tx_p[0]}] ;# MGTYTXP0_233 GTYE4_CHANNEL_X1Y56 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC E8 } [get_ports {sma_tx_n[0]}] ;# MGTYTXN0_233 GTYE4_CHANNEL_X1Y56 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC E4 } [get_ports {sma_rx_p[0]}] ;# MGTYRXP0_233 GTYE4_CHANNEL_X1Y56 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC E3 } [get_ports {sma_rx_n[0]}] ;# MGTYRXN0_233 GTYE4_CHANNEL_X1Y56 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC D7 } [get_ports {sma_tx_p[1]}] ;# MGTYTXP1_233 GTYE4_CHANNEL_X1Y57 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC D6 } [get_ports {sma_tx_n[1]}] ;# MGTYTXN1_233 GTYE4_CHANNEL_X1Y57 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC D2 } [get_ports {sma_rx_p[1]}] ;# MGTYRXP1_233 GTYE4_CHANNEL_X1Y57 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC D1 } [get_ports {sma_rx_n[1]}] ;# MGTYRXN1_233 GTYE4_CHANNEL_X1Y57 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC C9 } [get_ports {sma_tx_p[2]}] ;# MGTYTXP2_233 GTYE4_CHANNEL_X1Y58 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC C8 } [get_ports {sma_tx_n[2]}] ;# MGTYTXN2_233 GTYE4_CHANNEL_X1Y58 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC C4 } [get_ports {sma_rx_p[2]}] ;# MGTYRXP2_233 GTYE4_CHANNEL_X1Y58 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC C3 } [get_ports {sma_rx_n[2]}] ;# MGTYRXN2_233 GTYE4_CHANNEL_X1Y58 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC A9 } [get_ports {sma_tx_p[3]}] ;# MGTYTXP3_233 GTYE4_CHANNEL_X1Y59 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC A8 } [get_ports {sma_tx_n[3]}] ;# MGTYTXN3_233 GTYE4_CHANNEL_X1Y59 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC A5 } [get_ports {sma_rx_p[3]}] ;# MGTYRXP3_233 GTYE4_CHANNEL_X1Y59 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC A4 } [get_ports {sma_rx_n[3]}] ;# MGTYRXN3_233 GTYE4_CHANNEL_X1Y59 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC D11 } [get_ports sma_mgt_refclk_p] ;# MGTREFCLK0P_233 from X20 SMA CLKP +#set_property -dict {LOC D10 } [get_ports sma_mgt_refclk_n] ;# MGTREFCLK0N_233 from X19 SMA CLKN + +# 156.25 MHz MGT reference clock +#create_clock -period 6.400 -name sma_mgt_refclk [get_ports sma_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +#create_clock -period 6.206 -name sma_mgt_refclk [get_ports sma_mgt_refclk_p] + +# FireFly +#set_property -dict {LOC BF5 } [get_ports {ff_tx_p[0]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BF4 } [get_ports {ff_tx_n[0]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BC2 } [get_ports {ff_rx_p[0]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BC1 } [get_ports {ff_rx_n[0]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BD5 } [get_ports {ff_tx_p[2]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BD4 } [get_ports {ff_tx_n[2]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BA2 } [get_ports {ff_rx_p[2]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BA1 } [get_ports {ff_rx_n[2]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BB5 } [get_ports {ff_tx_p[1]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BB4 } [get_ports {ff_tx_n[1]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AW4 } [get_ports {ff_rx_p[1]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AW3 } [get_ports {ff_rx_n[1]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AV7 } [get_ports {ff_tx_p[3]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AV6 } [get_ports {ff_tx_n[3]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AV2 } [get_ports {ff_rx_p[3]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AV1 } [get_ports {ff_rx_n[3]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AU9 } [get_ports {ff_tx_p[5]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU8 } [get_ports {ff_tx_n[5]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU4 } [get_ports {ff_rx_p[5]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU3 } [get_ports {ff_rx_n[5]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT7 } [get_ports {ff_tx_p[7]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT6 } [get_ports {ff_tx_n[7]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT2 } [get_ports {ff_rx_p[7]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT1 } [get_ports {ff_rx_n[7]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR9 } [get_ports {ff_tx_p[4]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR8 } [get_ports {ff_tx_n[4]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR4 } [get_ports {ff_rx_p[4]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR3 } [get_ports {ff_rx_n[4]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP7 } [get_ports {ff_tx_p[6]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP6 } [get_ports {ff_tx_n[6]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP2 } [get_ports {ff_rx_p[6]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP1 } [get_ports {ff_rx_n[6]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AN9 } [get_ports {ff_tx_p[11]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AN8 } [get_ports {ff_tx_n[11]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AN4 } [get_ports {ff_rx_p[11]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AN3 } [get_ports {ff_rx_n[11]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AM7 } [get_ports {ff_tx_p[9]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AM6 } [get_ports {ff_tx_n[9]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AM2 } [get_ports {ff_rx_p[9]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AM1 } [get_ports {ff_rx_n[9]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AL9 } [get_ports {ff_tx_p[10]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AL8 } [get_ports {ff_tx_n[10]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AL4 } [get_ports {ff_rx_p[10]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AL3 } [get_ports {ff_rx_n[10]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AK7 } [get_ports {ff_tx_p[8]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AK6 } [get_ports {ff_tx_n[8]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AK2 } [get_ports {ff_rx_p[8]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AK1 } [get_ports {ff_rx_n[8]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AP11} [get_ports ff_mgt_refclk_p] ;# MGTREFCLK1P_225 from U48.31 OUT2_P +#set_property -dict {LOC AP10} [get_ports ff_mgt_refclk_n] ;# MGTREFCLK1N_225 from U48.30 OUT2_N +#set_property -dict {LOC M22 IOSTANDARD LVCMOS18} [get_ports ff_tx_int_l] +#set_property -dict {LOC P21 IOSTANDARD LVCMOS18} [get_ports ff_tx_gpio] +#set_property -dict {LOC N23 IOSTANDARD LVCMOS18} [get_ports ff_tx_prsnt_l] +#set_property -dict {LOC N22 IOSTANDARD LVCMOS18} [get_ports ff_rx_int_l] +#set_property -dict {LOC R21 IOSTANDARD LVCMOS18} [get_ports ff_rx_gpio] +#set_property -dict {LOC P23 IOSTANDARD LVCMOS18} [get_ports ff_rx_prsnt_l] + +# 100 MHz MGT reference clock +#create_clock -period 10.000 -name ff_mgt_refclk [get_ports ff_mgt_refclk_p] + +# 156.25 MHz MGT reference clock +#create_clock -period 6.400 -name ff_mgt_refclk [get_ports ff_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +#create_clock -period 6.206 -name ff_mgt_refclk [get_ports ff_mgt_refclk_p] + +# FMC+ J9 +set_property -dict {LOC BA15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_lpmode] ;# J9.G9 LA00_P_CC +set_property -dict {LOC BA14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_resetl] ;# J9.G10 LA00_N_CC +set_property -dict {LOC AY13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_modprsl] ;# J9.D8 LA01_P_CC +set_property -dict {LOC BA13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_intl] ;# J9.D9 LA01_N_CC +set_property -dict {LOC AL15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_modsell] ;# J9.H7 LA02_P +set_property -dict {LOC AM15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_modprsl] ;# J9.H8 LA02_N +set_property -dict {LOC AN14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_intl] ;# J9.G12 LA03_P +set_property -dict {LOC AN13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_modsell] ;# J9.G13 LA03_N +set_property -dict {LOC AL14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_6_lpmode] ;# J9.H10 LA04_P +set_property -dict {LOC AM14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_resetl] ;# J9.H11 LA04_N +set_property -dict {LOC AP13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_modsell] ;# J9.D11 LA05_P +set_property -dict {LOC AR13 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_intl] ;# J9.D12 LA05_N +set_property -dict {LOC AP15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_1_resetl] ;# J9.C10 LA06_P +set_property -dict {LOC AP14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_lpmode] ;# J9.C11 LA06_N +set_property -dict {LOC AU16 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_modprsl] ;# J9.H13 LA07_P +set_property -dict {LOC AV16 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_modsell] ;# J9.H14 LA07_N +set_property -dict {LOC AR16 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_lpmode] ;# J9.G12 LA08_P +set_property -dict {LOC AR15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_intl] ;# J9.G13 LA08_N +set_property -dict {LOC AT15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_modprsl] ;# J9.D14 LA09_P +set_property -dict {LOC AU15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_modsell] ;# J9.D15 LA09_N +set_property -dict {LOC AU14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_2_resetl] ;# J9.C14 LA10_P +set_property -dict {LOC AV14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_lpmode] ;# J9.C15 LA10_N +set_property -dict {LOC BD15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_intl] ;# J9.H16 LA11_P +set_property -dict {LOC BD14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_modprsl] ;# J9.H17 LA11_N +set_property -dict {LOC AY12 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_4_resetl] ;# J9.G15 LA12_P +set_property -dict {LOC AY11 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_5_lpmode] ;# J9.G16 LA12_N +set_property -dict {LOC BA12 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_intl] ;# J9.D17 LA13_P +set_property -dict {LOC BB12 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_modprsl] ;# J9.D18 LA13_N +set_property -dict {LOC BB15 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_modsell] ;# J9.C18 LA14_P +set_property -dict {LOC BB14 IOSTANDARD LVCMOS18} [get_ports fmc_qsfp_3_resetl] ;# J9.C19 LA14_N +set_property -dict {LOC BF14 IOSTANDARD LVCMOS18} [get_ports fmc_clk_finc] ;# J9.H19 LA15_P +set_property -dict {LOC BF13 IOSTANDARD LVCMOS18} [get_ports fmc_clk_fdec] ;# J9.H20 LA15_N +set_property -dict {LOC BD16 IOSTANDARD LVCMOS18} [get_ports fmc_clk_rst_n] ;# J9.G18 LA16_P +set_property -dict {LOC BE16 IOSTANDARD LVCMOS18} [get_ports fmc_clk_lol_n] ;# J9.G19 LA16_N +set_property -dict {LOC AT20 IOSTANDARD LVCMOS18} [get_ports fmc_clk_sync_n] ;# J9.D20 LA17_P_CC +set_property -dict {LOC AU20 IOSTANDARD LVCMOS18} [get_ports fmc_clk_intr_n] ;# J9.D21 LA17_N_CC +#set_property -dict {LOC AV19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[18]}] ;# J9.C22 LA18_P_CC +#set_property -dict {LOC AW19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[18]}] ;# J9.C23 LA18_N_CC +#set_property -dict {LOC AR17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[19]}] ;# J9.H22 LA19_P +#set_property -dict {LOC AT17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[19]}] ;# J9.H23 LA19_N +#set_property -dict {LOC AN18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[20]}] ;# J9.G21 LA20_P +#set_property -dict {LOC AN17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[20]}] ;# J9.G22 LA20_N +#set_property -dict {LOC AW20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[21]}] ;# J9.H25 LA21_P +#set_property -dict {LOC AY20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[21]}] ;# J9.H26 LA21_N +#set_property -dict {LOC AT19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[22]}] ;# J9.G24 LA22_P +#set_property -dict {LOC AU19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[22]}] ;# J9.G25 LA22_N +#set_property -dict {LOC AL17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[23]}] ;# J9.D23 LA23_P +#set_property -dict {LOC AM17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[23]}] ;# J9.D24 LA23_N +#set_property -dict {LOC AY17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[24]}] ;# J9.H28 LA24_P +#set_property -dict {LOC BA17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[24]}] ;# J9.H29 LA24_N +#set_property -dict {LOC AY18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[25]}] ;# J9.G27 LA25_P +#set_property -dict {LOC BA18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[25]}] ;# J9.G28 LA25_N +#set_property -dict {LOC AP20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[26]}] ;# J9.D26 LA26_P +#set_property -dict {LOC AP20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[26]}] ;# J9.D27 LA26_N +#set_property -dict {LOC AN19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[27]}] ;# J9.C26 LA27_P +#set_property -dict {LOC AP19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[27]}] ;# J9.C27 LA27_N +#set_property -dict {LOC BB17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[28]}] ;# J9.H31 LA28_P +#set_property -dict {LOC BC17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[28]}] ;# J9.H32 LA28_N +#set_property -dict {LOC BB19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[29]}] ;# J9.G30 LA29_P +#set_property -dict {LOC BC18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[29]}] ;# J9.G31 LA29_N +#set_property -dict {LOC BD18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[30]}] ;# J9.H34 LA30_P +#set_property -dict {LOC BE18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[30]}] ;# J9.H35 LA30_N +#set_property -dict {LOC BC19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[31]}] ;# J9.G33 LA31_P +#set_property -dict {LOC BD19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[31]}] ;# J9.G34 LA31_N +#set_property -dict {LOC BF19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[32]}] ;# J9.H37 LA32_P +#set_property -dict {LOC BF18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[32]}] ;# J9.H38 LA32_N +#set_property -dict {LOC BE17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[33]}] ;# J9.G36 LA33_P +#set_property -dict {LOC BF17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[33]}] ;# J9.G37 LA33_N + +#set_property -dict {LOC G14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[0]}] ;# J9.F4 HA00_P_CC +#set_property -dict {LOC F14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[0]}] ;# J9.F5 HA00_N_CC +#set_property -dict {LOC G15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[1]}] ;# J9.E2 HA01_P_CC +#set_property -dict {LOC F15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[1]}] ;# J9.E3 HA01_N_CC +#set_property -dict {LOC A14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[2]}] ;# J9.K7 HA02_P +#set_property -dict {LOC A13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[2]}] ;# J9.K8 HA02_N +#set_property -dict {LOC B17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[3]}] ;# J9.J6 HA03_P +#set_property -dict {LOC A17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[3]}] ;# J9.J7 HA03_N +#set_property -dict {LOC C16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[4]}] ;# J9.F7 HA04_P +#set_property -dict {LOC B16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[4]}] ;# J9.F8 HA04_N +#set_property -dict {LOC B15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[5]}] ;# J9.E6 HA05_P +#set_property -dict {LOC A15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[5]}] ;# J9.E7 HA05_N +#set_property -dict {LOC G17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[6]}] ;# J9.K10 HA06_P +#set_property -dict {LOC G16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[6]}] ;# J9.K11 HA06_N +#set_property -dict {LOC D13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[7]}] ;# J9.J9 HA07_P +#set_property -dict {LOC C13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[7]}] ;# J9.J10 HA07_N +#set_property -dict {LOC E15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[8]}] ;# J9.F10 HA08_P +#set_property -dict {LOC D15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[8]}] ;# J9.F11 HA08_N +#set_property -dict {LOC E16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[9]}] ;# J9.E9 HA09_P +#set_property -dict {LOC D16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[9]}] ;# J9.E10 HA09_N +#set_property -dict {LOC R16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[10]}] ;# J9.K13 HA10_P +#set_property -dict {LOC P16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[10]}] ;# J9.K14 HA10_N +#set_property -dict {LOC L13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[11]}] ;# J9.J12 HA11_P +#set_property -dict {LOC K13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[11]}] ;# J9.J13 HA11_N +#set_property -dict {LOC H17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[12]}] ;# J9.F13 HA12_P +#set_property -dict {LOC H16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[12]}] ;# J9.F14 HA12_N +#set_property -dict {LOC J13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[13]}] ;# J9.E12 HA13_P +#set_property -dict {LOC H13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[13]}] ;# J9.E13 HA13_N +#set_property -dict {LOC P14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[14]}] ;# J9.J15 HA14_P +#set_property -dict {LOC N14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[14]}] ;# J9.J16 HA14_N +#set_property -dict {LOC N16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[15]}] ;# J9.F14 HA15_P +#set_property -dict {LOC M16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[15]}] ;# J9.F16 HA15_N +#set_property -dict {LOC M14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[16]}] ;# J9.E15 HA16_P +#set_property -dict {LOC L14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[16]}] ;# J9.E16 HA16_N +#set_property -dict {LOC J14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[17]}] ;# J9.K16 HA17_P_CC +#set_property -dict {LOC H14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[17]}] ;# J9.K17 HA17_N_CC +#set_property -dict {LOC J16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[18]}] ;# J9.J18 HA18_P_CC +#set_property -dict {LOC J15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[18]}] ;# J9.J19 HA18_N_CC +#set_property -dict {LOC F13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[19]}] ;# J9.F19 HA19_P +#set_property -dict {LOC E13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[19]}] ;# J9.F20 HA19_N +#set_property -dict {LOC K16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[20]}] ;# J9.E18 HA20_P +#set_property -dict {LOC K15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[20]}] ;# J9.E19 HA20_N +#set_property -dict {LOC C14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[21]}] ;# J9.K19 HA21_P +#set_property -dict {LOC B14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[21]}] ;# J9.K20 HA21_N +#set_property -dict {LOC R15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[22]}] ;# J9.J21 HA22_P +#set_property -dict {LOC P15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[22]}] ;# J9.J22 HA22_N +#set_property -dict {LOC P13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[23]}] ;# J9.K22 HA23_P +#set_property -dict {LOC N13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[23]}] ;# J9.K23 HA23_N + +#set_property -dict {LOC H19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[0]}] ;# J9.K25 HB00_P_CC +#set_property -dict {LOC H18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[0]}] ;# J9.K26 HB00_N_CC +#set_property -dict {LOC D18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[1]}] ;# J9.J24 HB01_P +#set_property -dict {LOC C18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[1]}] ;# J9.J25 HB01_N +#set_property -dict {LOC D19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[2]}] ;# J9.F22 HB02_P +#set_property -dict {LOC C19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[2]}] ;# J9.F23 HB02_N +#set_property -dict {LOC B20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[3]}] ;# J9.E21 HB03_P +#set_property -dict {LOC A20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[3]}] ;# J9.E22 HB03_N +#set_property -dict {LOC F18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[4]}] ;# J9.F25 HB04_P +#set_property -dict {LOC F17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[4]}] ;# J9.F26 HB04_N +#set_property -dict {LOC E18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[5]}] ;# J9.E24 HB05_P +#set_property -dict {LOC E17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[5]}] ;# J9.E25 HB05_N +#set_property -dict {LOC J20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[6]}] ;# J9.K28 HB06_P_CC +#set_property -dict {LOC J19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[6]}] ;# J9.K29 HB06_N_CC +#set_property -dict {LOC F20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[7]}] ;# J9.J27 HB07_P +#set_property -dict {LOC F19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[7]}] ;# J9.J28 HB07_N +#set_property -dict {LOC J21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[8]}] ;# J9.F28 HB08_P +#set_property -dict {LOC H21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[8]}] ;# J9.F29 HB08_N +#set_property -dict {LOC G20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[9]}] ;# J9.E27 HB09_P +#set_property -dict {LOC G19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[9]}] ;# J9.E28 HB09_N +#set_property -dict {LOC P19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[10]}] ;# J9.K31 HB10_P +#set_property -dict {LOC N19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[10]}] ;# J9.K32 HB10_N +#set_property -dict {LOC L17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[11]}] ;# J9.J30 HB11_P +#set_property -dict {LOC K17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[11]}] ;# J9.J31 HB11_N +#set_property -dict {LOC L19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[12]}] ;# J9.F31 HB12_P +#set_property -dict {LOC L18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[12]}] ;# J9.F32 HB12_N +#set_property -dict {LOC N17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[13]}] ;# J9.E30 HB13_P +#set_property -dict {LOC M17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[13]}] ;# J9.E31 HB13_N +#set_property -dict {LOC N21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[14]}] ;# J9.K34 HB14_P +#set_property -dict {LOC M21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[14]}] ;# J9.K35 HB14_N +#set_property -dict {LOC R20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[15]}] ;# J9.J33 HB15_P +#set_property -dict {LOC P20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[15]}] ;# J9.J34 HB15_N +#set_property -dict {LOC L20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[16]}] ;# J9.F34 HB16_P +#set_property -dict {LOC K20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[16]}] ;# J9.F35 HB16_N +#set_property -dict {LOC K18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[17]}] ;# J9.K37 HB17_P_CC +#set_property -dict {LOC J18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[17]}] ;# J9.K38 HB17_N_CC +#set_property -dict {LOC C21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[18]}] ;# J9.J36 HB18_P +#set_property -dict {LOC B21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[18]}] ;# J9.J37 HB18_N +#set_property -dict {LOC E21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[19]}] ;# J9.E33 HB19_P +#set_property -dict {LOC E20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[19]}] ;# J9.E34 HB19_N +#set_property -dict {LOC B19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[20]}] ;# J9.F37 HB20_P +#set_property -dict {LOC A19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[20]}] ;# J9.F38 HB20_N +#set_property -dict {LOC D21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[21]}] ;# J9.E36 HB21_P +#set_property -dict {LOC D20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[21]}] ;# J9.E37 HB21_N + +#set_property -dict {LOC AW14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk0_m2c_p}] ;# J9.H4 CLK0_M2C_P +#set_property -dict {LOC AW13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk0_m2c_n}] ;# J9.H5 CLK0_M2C_N +#set_property -dict {LOC AV18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk1_m2c_p}] ;# J9.G2 CLK1_M2C_P +#set_property -dict {LOC AW18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk1_m2c_n}] ;# J9.G3 CLK1_M2C_N + +#set_property -dict {LOC G25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_user_def0_p}] ;# J9.L32 USER_DEF0_P +#set_property -dict {LOC G24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_user_def0_n}] ;# J9.L33 USER_DEF0_N +#set_property -dict {LOC F24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_refclk_m2c_p}] ;# J9.L24 REFCLK_M2C_P +#set_property -dict {LOC F23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_refclk_m2c_n}] ;# J9.L25 REFCLK_M2C_N +set_property -dict {LOC E23 IOSTANDARD LVDS } [get_ports {fmc_sync_c2m_p}] ;# J9.L16 SYNC_C2M_P +set_property -dict {LOC E22 IOSTANDARD LVDS } [get_ports {fmc_sync_c2m_n}] ;# J9.L17 SYNC_C2M_N +#set_property -dict {LOC J24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_sync_m2c_p}] ;# J9.L28 SYNC_M2C_P +#set_property -dict {LOC H24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_sync_m2c_n}] ;# J9.L29 SYNC_M2C_N + +#set_property -dict {LOC AV23 IOSTANDARD LVCMOS18} [get_ports {fmc_pg_m2c}] ;# J9.F1 PG_M2C +#set_property -dict {LOC AW23 IOSTANDARD LVCMOS18} [get_ports {fmc_prsnt_m2c_l}] ;# J9.H2 PRSNT_M2C_L +#set_property -dict {LOC BC23 IOSTANDARD LVCMOS18} [get_ports {fmc_hspc_prsnt_m2c_l}] ;# J9.Z1 HSPC_PRSNT_M2C_L + +set_property -dict {LOC Y7 } [get_ports {fmc_qsfp_1_tx_p[0]}] ;# MGTYTXP1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C2 DP0_C2M_P +set_property -dict {LOC Y6 } [get_ports {fmc_qsfp_1_tx_n[0]}] ;# MGTYTXN1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C3 DP0_C2M_N +set_property -dict {LOC Y2 } [get_ports {fmc_qsfp_1_rx_p[0]}] ;# MGTYRXP1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C6 DP0_M2C_P +set_property -dict {LOC Y1 } [get_ports {fmc_qsfp_1_rx_n[0]}] ;# MGTYRXN1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C7 DP0_M2C_N +set_property -dict {LOC V7 } [get_ports {fmc_qsfp_1_tx_p[2]}] ;# MGTYTXP3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A22 DP1_C2M_P +set_property -dict {LOC V6 } [get_ports {fmc_qsfp_1_tx_n[2]}] ;# MGTYTXN3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A23 DP1_C2M_N +set_property -dict {LOC V2 } [get_ports {fmc_qsfp_1_rx_p[2]}] ;# MGTYRXP3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A2 DP1_M2C_P +set_property -dict {LOC V1 } [get_ports {fmc_qsfp_1_rx_n[2]}] ;# MGTYRXN3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A3 DP1_M2C_N +set_property -dict {LOC W9 } [get_ports {fmc_qsfp_1_tx_p[1]}] ;# MGTYTXP2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A26 DP2_C2M_P +set_property -dict {LOC W8 } [get_ports {fmc_qsfp_1_tx_n[1]}] ;# MGTYTXN2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A27 DP2_C2M_N +set_property -dict {LOC W4 } [get_ports {fmc_qsfp_1_rx_p[1]}] ;# MGTYRXP2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A6 DP2_M2C_P +set_property -dict {LOC W3 } [get_ports {fmc_qsfp_1_rx_n[1]}] ;# MGTYRXN2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A7 DP2_M2C_N +set_property -dict {LOC AA9 } [get_ports {fmc_qsfp_1_tx_p[3]}] ;# MGTYTXP0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A30 DP3_C2M_P +set_property -dict {LOC AA8 } [get_ports {fmc_qsfp_1_tx_n[3]}] ;# MGTYTXN0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A31 DP3_C2M_N +set_property -dict {LOC AA4 } [get_ports {fmc_qsfp_1_rx_p[3]}] ;# MGTYRXP0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A10 DP3_M2C_P +set_property -dict {LOC AA3 } [get_ports {fmc_qsfp_1_rx_n[3]}] ;# MGTYRXN0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A11 DP3_M2C_N +set_property -dict {LOC Y11 } [get_ports fmc_qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_229 from J9.D4 GBTCLK0_M2C_P +set_property -dict {LOC Y10 } [get_ports fmc_qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_229 from J9.D5 GBTCLK0_M2C_N +#set_property -dict {LOC V11 } [get_ports fmc_mgt_refclk_0_1_p] ;# MGTREFCLK1P_229 from U27.14 OUT3 +#set_property -dict {LOC V10 } [get_ports fmc_mgt_refclk_0_1_n] ;# MGTREFCLK1N_229 from U27.13 OUT3B + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_1_mgt_refclk [get_ports fmc_qsfp_1_mgt_refclk_p] +#create_clock -period 6.206 -name fmc_mgt_refclk_0_1 [get_ports fmc_mgt_refclk_0_1_p] + +set_property -dict {LOC AC9 } [get_ports {fmc_qsfp_6_tx_p[1]}] ;# MGTYTXP2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A34 DP4_C2M_P +set_property -dict {LOC AC8 } [get_ports {fmc_qsfp_6_tx_n[1]}] ;# MGTYTXN2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A35 DP4_C2M_N +set_property -dict {LOC AC4 } [get_ports {fmc_qsfp_6_rx_p[1]}] ;# MGTYRXP2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A14 DP4_M2C_P +set_property -dict {LOC AC3 } [get_ports {fmc_qsfp_6_rx_n[1]}] ;# MGTYRXN2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A15 DP4_M2C_N +set_property -dict {LOC AE9 } [get_ports {fmc_qsfp_6_tx_p[0]}] ;# MGTYTXP0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A38 DP5_C2M_P +set_property -dict {LOC AE8 } [get_ports {fmc_qsfp_6_tx_n[0]}] ;# MGTYTXN0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A39 DP5_C2M_N +set_property -dict {LOC AE4 } [get_ports {fmc_qsfp_6_rx_p[0]}] ;# MGTYRXP0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A18 DP5_M2C_P +set_property -dict {LOC AE3 } [get_ports {fmc_qsfp_6_rx_n[0]}] ;# MGTYRXN0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A19 DP5_M2C_N +set_property -dict {LOC AD7 } [get_ports {fmc_qsfp_6_tx_p[2]}] ;# MGTYTXP1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B36 DP6_C2M_P +set_property -dict {LOC AD6 } [get_ports {fmc_qsfp_6_tx_n[2]}] ;# MGTYTXN1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B37 DP6_C2M_N +set_property -dict {LOC AD2 } [get_ports {fmc_qsfp_6_rx_p[2]}] ;# MGTYRXP1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B16 DP6_M2C_P +set_property -dict {LOC AD1 } [get_ports {fmc_qsfp_6_rx_n[2]}] ;# MGTYRXN1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B17 DP6_M2C_N +set_property -dict {LOC AB7 } [get_ports {fmc_qsfp_6_tx_p[3]}] ;# MGTYTXP3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B32 DP7_C2M_P +set_property -dict {LOC AB6 } [get_ports {fmc_qsfp_6_tx_n[3]}] ;# MGTYTXN3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B33 DP7_C2M_N +set_property -dict {LOC AB2 } [get_ports {fmc_qsfp_6_rx_p[3]}] ;# MGTYRXP3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B12 DP7_M2C_P +set_property -dict {LOC AB1 } [get_ports {fmc_qsfp_6_rx_n[3]}] ;# MGTYRXN3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B13 DP7_M2C_N +set_property -dict {LOC AD11} [get_ports fmc_qsfp_6_mgt_refclk_p] ;# MGTREFCLK0P_228 from J9.B20 GBTCLK1_M2C_P +set_property -dict {LOC AD10} [get_ports fmc_qsfp_6_mgt_refclk_n] ;# MGTREFCLK0N_228 from J9.B21 GBTCLK1_M2C_N + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_6_mgt_refclk [get_ports fmc_qsfp_6_mgt_refclk_p] + +set_property -dict {LOC L9 } [get_ports {fmc_qsfp_4_tx_p[3]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B28 DP8_C2M_P +set_property -dict {LOC L8 } [get_ports {fmc_qsfp_4_tx_n[3]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B29 DP8_C2M_N +set_property -dict {LOC L4 } [get_ports {fmc_qsfp_4_rx_p[3]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B8 DP8_M2C_P +set_property -dict {LOC L3 } [get_ports {fmc_qsfp_4_rx_n[3]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B9 DP8_M2C_N +set_property -dict {LOC K7 } [get_ports {fmc_qsfp_4_tx_p[2]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B24 DP9_C2M_P +set_property -dict {LOC K6 } [get_ports {fmc_qsfp_4_tx_n[2]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B25 DP9_C2M_N +set_property -dict {LOC K2 } [get_ports {fmc_qsfp_4_rx_p[2]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B4 DP9_M2C_P +set_property -dict {LOC K1 } [get_ports {fmc_qsfp_4_rx_n[2]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B5 DP9_M2C_N +set_property -dict {LOC M7 } [get_ports {fmc_qsfp_4_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Z24 DP10_C2M_P +set_property -dict {LOC M6 } [get_ports {fmc_qsfp_4_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Z25 DP10_C2M_N +set_property -dict {LOC M2 } [get_ports {fmc_qsfp_4_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Y10 DP10_M2C_P +set_property -dict {LOC M1 } [get_ports {fmc_qsfp_4_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Y11 DP10_M2C_N +set_property -dict {LOC N9 } [get_ports {fmc_qsfp_4_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Y26 DP11_C2M_P +set_property -dict {LOC N8 } [get_ports {fmc_qsfp_4_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Y27 DP11_C2M_N +set_property -dict {LOC N4 } [get_ports {fmc_qsfp_4_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Z12 DP11_M2C_P +set_property -dict {LOC N3 } [get_ports {fmc_qsfp_4_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Z13 DP11_M2C_N +set_property -dict {LOC M11 } [get_ports fmc_qsfp_4_mgt_refclk_p] ;# MGTREFCLK0P_231 from J9.L12 GBTCLK2_M2C_P +set_property -dict {LOC M10 } [get_ports fmc_qsfp_4_mgt_refclk_n] ;# MGTREFCLK0N_231 from J9.L13 GBTCLK2_M2C_N +#set_property -dict {LOC K11 } [get_ports fmc_mgt_refclk_2_1_p] ;# MGTREFCLK1P_231 from U27.17 OUT2 +#set_property -dict {LOC K10 } [get_ports fmc_mgt_refclk_2_1_n] ;# MGTREFCLK1N_231 from U27.16 OUT2B + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_4_mgt_refclk [get_ports fmc_qsfp_4_mgt_refclk_p] +#create_clock -period 6.206 -name fmc_mgt_refclk_2_1 [get_ports fmc_mgt_refclk_2_1_p] + +set_property -dict {LOC P7 } [get_ports {fmc_qsfp_3_tx_p[2]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Z28 DP12_C2M_P +set_property -dict {LOC P6 } [get_ports {fmc_qsfp_3_tx_n[2]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Z29 DP12_C2M_N +set_property -dict {LOC P2 } [get_ports {fmc_qsfp_3_rx_p[2]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Y14 DP12_M2C_P +set_property -dict {LOC P1 } [get_ports {fmc_qsfp_3_rx_n[2]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Y15 DP12_M2C_N +set_property -dict {LOC R9 } [get_ports {fmc_qsfp_3_tx_p[3]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Y30 DP13_C2M_P +set_property -dict {LOC R8 } [get_ports {fmc_qsfp_3_tx_n[3]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Y31 DP13_C2M_N +set_property -dict {LOC R4 } [get_ports {fmc_qsfp_3_rx_p[3]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Z16 DP13_M2C_P +set_property -dict {LOC R3 } [get_ports {fmc_qsfp_3_rx_n[3]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Z17 DP13_M2C_N +set_property -dict {LOC T7 } [get_ports {fmc_qsfp_3_tx_p[1]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.M18 DP14_C2M_P +set_property -dict {LOC T6 } [get_ports {fmc_qsfp_3_tx_n[1]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.M19 DP14_C2M_N +set_property -dict {LOC T2 } [get_ports {fmc_qsfp_3_rx_p[1]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.Y18 DP14_M2C_P +set_property -dict {LOC T1 } [get_ports {fmc_qsfp_3_rx_n[1]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.Y19 DP14_M2C_N +set_property -dict {LOC U9 } [get_ports {fmc_qsfp_3_tx_p[0]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.M22 DP15_C2M_P +set_property -dict {LOC U8 } [get_ports {fmc_qsfp_3_tx_n[0]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.M23 DP15_C2M_N +set_property -dict {LOC U4 } [get_ports {fmc_qsfp_3_rx_p[0]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.Y22 DP15_M2C_P +set_property -dict {LOC U3 } [get_ports {fmc_qsfp_3_rx_n[0]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.Y23 DP15_M2C_N +set_property -dict {LOC T11 } [get_ports fmc_qsfp_3_mgt_refclk_p] ;# MGTREFCLK0P_230 from J9.L8 GBTCLK3_M2C_P +set_property -dict {LOC T10 } [get_ports fmc_qsfp_3_mgt_refclk_n] ;# MGTREFCLK0N_230 from J9.L9 GBTCLK3_M2C_N + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_3_mgt_refclk [get_ports fmc_qsfp_3_mgt_refclk_p] + +set_property -dict {LOC AF7 } [get_ports {fmc_qsfp_5_tx_p[3]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.M26 DP16_C2M_P +set_property -dict {LOC AF6 } [get_ports {fmc_qsfp_5_tx_n[3]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.M27 DP16_C2M_N +set_property -dict {LOC AF2 } [get_ports {fmc_qsfp_5_rx_p[3]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.Z32 DP16_M2C_P +set_property -dict {LOC AF1 } [get_ports {fmc_qsfp_5_rx_n[3]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.Z33 DP16_M2C_N +set_property -dict {LOC AG9 } [get_ports {fmc_qsfp_5_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.M30 DP17_C2M_P +set_property -dict {LOC AG8 } [get_ports {fmc_qsfp_5_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.M31 DP17_C2M_N +set_property -dict {LOC AG4 } [get_ports {fmc_qsfp_5_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.Y34 DP17_M2C_P +set_property -dict {LOC AG3 } [get_ports {fmc_qsfp_5_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.Y35 DP17_M2C_N +set_property -dict {LOC AH7 } [get_ports {fmc_qsfp_5_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.M34 DP18_C2M_P +set_property -dict {LOC AH6 } [get_ports {fmc_qsfp_5_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.M35 DP18_C2M_N +set_property -dict {LOC AH2 } [get_ports {fmc_qsfp_5_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.Z36 DP18_M2C_P +set_property -dict {LOC AH1 } [get_ports {fmc_qsfp_5_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.Z37 DP18_M2C_N +set_property -dict {LOC AJ9 } [get_ports {fmc_qsfp_5_tx_p[0]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.M38 DP19_C2M_P +set_property -dict {LOC AJ8 } [get_ports {fmc_qsfp_5_tx_n[0]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.M39 DP19_C2M_N +set_property -dict {LOC AJ4 } [get_ports {fmc_qsfp_5_rx_p[0]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.Y38 DP19_M2C_P +set_property -dict {LOC AJ3 } [get_ports {fmc_qsfp_5_rx_n[0]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.Y39 DP19_M2C_N +set_property -dict {LOC AH11} [get_ports fmc_qsfp_5_mgt_refclk_p] ;# MGTREFCLK0P_227 from J9.L4 GBTCLK4_M2C_P +set_property -dict {LOC AH10} [get_ports fmc_qsfp_5_mgt_refclk_n] ;# MGTREFCLK0N_227 from J9.L5 GBTCLK4_M2C_N +#set_property -dict {LOC AF11} [get_ports fmc_mgt_refclk_4_1_p] ;# MGTREFCLK1P_227 from U27.11 OUT4 +#set_property -dict {LOC AF10} [get_ports fmc_mgt_refclk_4_1_n] ;# MGTREFCLK1N_227 from U27.12 OUT4B + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_5_mgt_refclk [get_ports fmc_qsfp_5_mgt_refclk_p] +#create_clock -period 6.206 -name fmc_mgt_refclk_4_1 [get_ports fmc_mgt_refclk_4_1_p] + +set_property -dict {LOC J9 } [get_ports {fmc_qsfp_2_tx_p[3]}] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.Z8 DP20_C2M_P +set_property -dict {LOC J8 } [get_ports {fmc_qsfp_2_tx_n[3]}] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.Z9 DP20_C2M_N +set_property -dict {LOC J4 } [get_ports {fmc_qsfp_2_rx_p[3]}] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.M14 DP20_M2C_P +set_property -dict {LOC J3 } [get_ports {fmc_qsfp_2_rx_n[3]}] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.M15 DP20_M2C_N +set_property -dict {LOC H7 } [get_ports {fmc_qsfp_2_tx_p[2]}] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.Y6 DP21_C2M_P +set_property -dict {LOC H6 } [get_ports {fmc_qsfp_2_tx_n[2]}] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.Y7 DP21_C2M_N +set_property -dict {LOC H2 } [get_ports {fmc_qsfp_2_rx_p[2]}] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.M10 DP21_M2C_P +set_property -dict {LOC H1 } [get_ports {fmc_qsfp_2_rx_n[2]}] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.M11 DP21_M2C_N +set_property -dict {LOC G9 } [get_ports {fmc_qsfp_2_tx_p[0]}] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.Z4 DP22_C2M_P +set_property -dict {LOC G8 } [get_ports {fmc_qsfp_2_tx_n[0]}] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.Z5 DP22_C2M_N +set_property -dict {LOC G4 } [get_ports {fmc_qsfp_2_rx_p[0]}] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.M6 DP22_M2C_P +set_property -dict {LOC G3 } [get_ports {fmc_qsfp_2_rx_n[0]}] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.M7 DP22_M2C_N +set_property -dict {LOC F7 } [get_ports {fmc_qsfp_2_tx_p[1]}] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.Y2 DP23_C2M_P +set_property -dict {LOC F6 } [get_ports {fmc_qsfp_2_tx_n[1]}] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.Y3 DP23_C2M_N +set_property -dict {LOC F2 } [get_ports {fmc_qsfp_2_rx_p[1]}] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.M2 DP23_M2C_P +set_property -dict {LOC F1 } [get_ports {fmc_qsfp_2_rx_n[1]}] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.M3 DP23_M2C_N +set_property -dict {LOC H11 } [get_ports fmc_qsfp_2_mgt_refclk_p] ;# MGTREFCLK0P_232 from J9.Z20 GBTCLK5_M2C_P +set_property -dict {LOC H10 } [get_ports fmc_qsfp_2_mgt_refclk_n] ;# MGTREFCLK0N_232 from J9.Z21 GBTCLK5_M2C_N + +# reference clock +create_clock -period 6.206 -name fmc_qsfp_2_mgt_refclk [get_ports fmc_qsfp_2_mgt_refclk_p] diff --git a/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga/Makefile b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga/Makefile new file mode 100644 index 000000000..578e97b42 --- /dev/null +++ b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga/Makefile @@ -0,0 +1,115 @@ + +# FPGA settings +FPGA_PART = xcvu9p-flgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/debounce_switch.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/i2c_master.v +SYN_FILES += pll/si5341_i2c_init.v +SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete_64.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v +SYN_FILES += lib/eth/rtl/udp_64.v +SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v +SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v +SYN_FILES += lib/eth/rtl/ip_complete_64.v +SYN_FILES += lib/eth/rtl/ip_64.v +SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v +SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl + +# IP +IP_TCL_FILES += ip/eth_xcvr_gt.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + diff --git a/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga/config.tcl b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga/config.tcl new file mode 100644 index 000000000..756e2b3a1 --- /dev/null +++ b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile new file mode 100644 index 000000000..578e97b42 --- /dev/null +++ b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile @@ -0,0 +1,115 @@ + +# FPGA settings +FPGA_PART = xcvu9p-flgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/debounce_switch.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/i2c_master.v +SYN_FILES += pll/si5341_i2c_init.v +SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete_64.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v +SYN_FILES += lib/eth/rtl/udp_64.v +SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v +SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v +SYN_FILES += lib/eth/rtl/ip_complete_64.v +SYN_FILES += lib/eth/rtl/ip_64.v +SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v +SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl + +# IP +IP_TCL_FILES += ip/eth_xcvr_gt.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + diff --git a/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga_10g/config.tcl b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga_10g/config.tcl new file mode 100644 index 000000000..90aa4caeb --- /dev/null +++ b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga_10g/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/HTG9200/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/ip/eth_xcvr_gt.tcl similarity index 100% rename from fpga/lib/eth/example/HTG9200/fpga_10g/ip/eth_xcvr_gt.tcl rename to fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/ip/eth_xcvr_gt.tcl diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/lib/eth b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/lib/eth similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga_cxpt16/lib/eth rename to fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/lib/eth diff --git a/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_161-9k2_161-Registers.txt b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_161-9k2_161-Registers.txt new file mode 100644 index 000000000..bd345341b --- /dev/null +++ b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_161-9k2_161-Registers.txt @@ -0,0 +1,412 @@ +# Si534x/7x/8x/9x Registers Script +# +# Part: Si5341 +# Project File: X:\Projects\verilog-ethernet\example\HTG9200\fpga_25g\pll\HTG9200_161-9k2_161.slabtimeproj +# Design ID: 9k2_161 +# Includes Pre/Post Download Control Register Writes: Yes +# Die Revision: B1 +# Creator: ClockBuilder Pro v4.1 [2021-09-22] +# Created On: 2023-07-19 01:38:53 GMT-07:00 +Address,Data +# +# Start configuration preamble +0x0B24,0xC0 +0x0B25,0x00 +# Rev D stuck divider fix +0x0502,0x01 +0x0505,0x03 +0x0957,0x17 +0x0B4E,0x1A +# End configuration preamble +# +# Delay 300 msec +# Delay is worst case time for device to complete any calibration +# that is running due to device state change previous to this script +# being processed. +# +# Start configuration registers +0x0006,0x00 +0x0007,0x00 +0x0008,0x00 +0x000B,0x74 +0x0017,0xD0 +0x0018,0xFF +0x0021,0x0B +0x0022,0x00 +0x002B,0x02 +0x002C,0x33 +0x002D,0x05 +0x002E,0xAE +0x002F,0x00 +0x0030,0xAE +0x0031,0x00 +0x0032,0x00 +0x0033,0x00 +0x0034,0x00 +0x0035,0x00 +0x0036,0xAE +0x0037,0x00 +0x0038,0xAE +0x0039,0x00 +0x003A,0x00 +0x003B,0x00 +0x003C,0x00 +0x003D,0x00 +0x0041,0x07 +0x0042,0x07 +0x0043,0x00 +0x0044,0x00 +0x009E,0x00 +0x0102,0x01 +0x0108,0x06 +0x0109,0x09 +0x010A,0x3B +0x010B,0x28 +0x010D,0x06 +0x010E,0x09 +0x010F,0x3B +0x0110,0x28 +0x0112,0x02 +0x0113,0x09 +0x0114,0x3B +0x0115,0x29 +0x0117,0x06 +0x0118,0x09 +0x0119,0x3B +0x011A,0x28 +0x011C,0x06 +0x011D,0x09 +0x011E,0x3B +0x011F,0x28 +0x0121,0x06 +0x0122,0x09 +0x0123,0x3B +0x0124,0x28 +0x0126,0x06 +0x0127,0x09 +0x0128,0x3B +0x0129,0x28 +0x012B,0x06 +0x012C,0x09 +0x012D,0x3B +0x012E,0x28 +0x0130,0x06 +0x0131,0x09 +0x0132,0x3B +0x0133,0x28 +0x013A,0x06 +0x013B,0x09 +0x013C,0x3B +0x013D,0x28 +0x013F,0x00 +0x0140,0x00 +0x0141,0x40 +0x0206,0x00 +0x0208,0x02 +0x0209,0x00 +0x020A,0x00 +0x020B,0x00 +0x020C,0x00 +0x020D,0x00 +0x020E,0x01 +0x020F,0x00 +0x0210,0x00 +0x0211,0x00 +0x0212,0x02 +0x0213,0x00 +0x0214,0x00 +0x0215,0x00 +0x0216,0x00 +0x0217,0x00 +0x0218,0x01 +0x0219,0x00 +0x021A,0x00 +0x021B,0x00 +0x021C,0x00 +0x021D,0x00 +0x021E,0x00 +0x021F,0x00 +0x0220,0x00 +0x0221,0x00 +0x0222,0x00 +0x0223,0x00 +0x0224,0x00 +0x0225,0x00 +0x0226,0x00 +0x0227,0x00 +0x0228,0x00 +0x0229,0x00 +0x022A,0x00 +0x022B,0x00 +0x022C,0x00 +0x022D,0x00 +0x022E,0x00 +0x022F,0x00 +0x0235,0x00 +0x0236,0x00 +0x0237,0x00 +0x0238,0x90 +0x0239,0x54 +0x023A,0x00 +0x023B,0x00 +0x023C,0x00 +0x023D,0x00 +0x023E,0x80 +0x024A,0x00 +0x024B,0x00 +0x024C,0x00 +0x024D,0x00 +0x024E,0x00 +0x024F,0x00 +0x0250,0x03 +0x0251,0x00 +0x0252,0x00 +0x0253,0x00 +0x0254,0x00 +0x0255,0x00 +0x0256,0x00 +0x0257,0x00 +0x0258,0x00 +0x0259,0x00 +0x025A,0x00 +0x025B,0x00 +0x025C,0x00 +0x025D,0x00 +0x025E,0x00 +0x025F,0x00 +0x0260,0x00 +0x0261,0x00 +0x0262,0x00 +0x0263,0x00 +0x0264,0x00 +0x0268,0x00 +0x0269,0x00 +0x026A,0x00 +0x026B,0x39 +0x026C,0x6B +0x026D,0x32 +0x026E,0x5F +0x026F,0x31 +0x0270,0x36 +0x0271,0x31 +0x0272,0x00 +0x0302,0x00 +0x0303,0x00 +0x0304,0x00 +0x0305,0x80 +0x0306,0x14 +0x0307,0x00 +0x0308,0x00 +0x0309,0x00 +0x030A,0x00 +0x030B,0x80 +0x030C,0x00 +0x030D,0x00 +0x030E,0x00 +0x030F,0x10 +0x0310,0x42 +0x0311,0x08 +0x0312,0x00 +0x0313,0x00 +0x0314,0x00 +0x0315,0x00 +0x0316,0x80 +0x0317,0x00 +0x0318,0x00 +0x0319,0x00 +0x031A,0x00 +0x031B,0x00 +0x031C,0x00 +0x031D,0x00 +0x031E,0x00 +0x031F,0x00 +0x0320,0x00 +0x0321,0x00 +0x0322,0x00 +0x0323,0x00 +0x0324,0x00 +0x0325,0x00 +0x0326,0x00 +0x0327,0x00 +0x0328,0x00 +0x0329,0x00 +0x032A,0x00 +0x032B,0x00 +0x032C,0x00 +0x032D,0x00 +0x032E,0x00 +0x032F,0x00 +0x0330,0x00 +0x0331,0x00 +0x0332,0x00 +0x0333,0x00 +0x0334,0x00 +0x0335,0x00 +0x0336,0x00 +0x0337,0x00 +0x0338,0x00 +0x0339,0x1F +0x033B,0x00 +0x033C,0x00 +0x033D,0x00 +0x033E,0x00 +0x033F,0x00 +0x0340,0x00 +0x0341,0x00 +0x0342,0x00 +0x0343,0x00 +0x0344,0x00 +0x0345,0x00 +0x0346,0x00 +0x0347,0x00 +0x0348,0x00 +0x0349,0x00 +0x034A,0x00 +0x034B,0x00 +0x034C,0x00 +0x034D,0x00 +0x034E,0x00 +0x034F,0x00 +0x0350,0x00 +0x0351,0x00 +0x0352,0x00 +0x0353,0x00 +0x0354,0x00 +0x0355,0x00 +0x0356,0x00 +0x0357,0x00 +0x0358,0x00 +0x0359,0x00 +0x035A,0x00 +0x035B,0x00 +0x035C,0x00 +0x035D,0x00 +0x035E,0x00 +0x035F,0x00 +0x0360,0x00 +0x0361,0x00 +0x0362,0x00 +0x0802,0x00 +0x0803,0x00 +0x0804,0x00 +0x0805,0x00 +0x0806,0x00 +0x0807,0x00 +0x0808,0x00 +0x0809,0x00 +0x080A,0x00 +0x080B,0x00 +0x080C,0x00 +0x080D,0x00 +0x080E,0x00 +0x080F,0x00 +0x0810,0x00 +0x0811,0x00 +0x0812,0x00 +0x0813,0x00 +0x0814,0x00 +0x0815,0x00 +0x0816,0x00 +0x0817,0x00 +0x0818,0x00 +0x0819,0x00 +0x081A,0x00 +0x081B,0x00 +0x081C,0x00 +0x081D,0x00 +0x081E,0x00 +0x081F,0x00 +0x0820,0x00 +0x0821,0x00 +0x0822,0x00 +0x0823,0x00 +0x0824,0x00 +0x0825,0x00 +0x0826,0x00 +0x0827,0x00 +0x0828,0x00 +0x0829,0x00 +0x082A,0x00 +0x082B,0x00 +0x082C,0x00 +0x082D,0x00 +0x082E,0x00 +0x082F,0x00 +0x0830,0x00 +0x0831,0x00 +0x0832,0x00 +0x0833,0x00 +0x0834,0x00 +0x0835,0x00 +0x0836,0x00 +0x0837,0x00 +0x0838,0x00 +0x0839,0x00 +0x083A,0x00 +0x083B,0x00 +0x083C,0x00 +0x083D,0x00 +0x083E,0x00 +0x083F,0x00 +0x0840,0x00 +0x0841,0x00 +0x0842,0x00 +0x0843,0x00 +0x0844,0x00 +0x0845,0x00 +0x0846,0x00 +0x0847,0x00 +0x0848,0x00 +0x0849,0x00 +0x084A,0x00 +0x084B,0x00 +0x084C,0x00 +0x084D,0x00 +0x084E,0x00 +0x084F,0x00 +0x0850,0x00 +0x0851,0x00 +0x0852,0x00 +0x0853,0x00 +0x0854,0x00 +0x0855,0x00 +0x0856,0x00 +0x0857,0x00 +0x0858,0x00 +0x0859,0x00 +0x085A,0x00 +0x085B,0x00 +0x085C,0x00 +0x085D,0x00 +0x085E,0x00 +0x085F,0x00 +0x0860,0x00 +0x0861,0x00 +0x090E,0x00 +0x091C,0x04 +0x0943,0x00 +0x0949,0x03 +0x094A,0x30 +0x094E,0x49 +0x094F,0x02 +0x095E,0x00 +0x0A02,0x00 +0x0A03,0x03 +0x0A04,0x01 +0x0A05,0x03 +0x0A14,0x00 +0x0A1A,0x00 +0x0A20,0x00 +0x0A26,0x00 +0x0A2C,0x00 +0x0B44,0x0F +0x0B4A,0x1C +0x0B57,0xA5 +0x0B58,0x00 +# End configuration registers +# +# Start configuration postamble +0x001C,0x01 +0x0B24,0xC3 +0x0B25,0x02 +# End configuration postamble diff --git a/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_161-9k2_161.slabtimeproj b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_161-9k2_161.slabtimeproj new file mode 100644 index 000000000..2d660f8f6 Binary files /dev/null and b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_161-9k2_161.slabtimeproj differ diff --git a/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161-Registers.txt b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161-Registers.txt new file mode 100644 index 000000000..ac46ab6da --- /dev/null +++ b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161-Registers.txt @@ -0,0 +1,412 @@ +# Si534x/7x/8x/9x Registers Script +# +# Part: Si5341 +# Project File: X:\Projects\verilog-ethernet\example\HTG9200\fpga_fmc_htg_6qsfp_25g\pll\HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj +# Design ID: HTG6Q161 +# Includes Pre/Post Download Control Register Writes: Yes +# Die Revision: B1 +# Creator: ClockBuilder Pro v4.1 [2021-09-22] +# Created On: 2023-07-19 01:56:52 GMT-07:00 +Address,Data +# +# Start configuration preamble +0x0B24,0xC0 +0x0B25,0x00 +# Rev D stuck divider fix +0x0502,0x01 +0x0505,0x03 +0x0957,0x17 +0x0B4E,0x1A +# End configuration preamble +# +# Delay 300 msec +# Delay is worst case time for device to complete any calibration +# that is running due to device state change previous to this script +# being processed. +# +# Start configuration registers +0x0006,0x00 +0x0007,0x00 +0x0008,0x00 +0x000B,0x74 +0x0017,0xD0 +0x0018,0xFF +0x0021,0x0D +0x0022,0x00 +0x002B,0x02 +0x002C,0x34 +0x002D,0x10 +0x002E,0x00 +0x002F,0x00 +0x0030,0x00 +0x0031,0x00 +0x0032,0xA8 +0x0033,0x00 +0x0034,0x00 +0x0035,0x00 +0x0036,0x00 +0x0037,0x00 +0x0038,0x00 +0x0039,0x00 +0x003A,0xA8 +0x003B,0x00 +0x003C,0x00 +0x003D,0x00 +0x0041,0x00 +0x0042,0x00 +0x0043,0x07 +0x0044,0x00 +0x009E,0x00 +0x0102,0x01 +0x0108,0x06 +0x0109,0x09 +0x010A,0x33 +0x010B,0x08 +0x010D,0x06 +0x010E,0x09 +0x010F,0x33 +0x0110,0x08 +0x0112,0x06 +0x0113,0x09 +0x0114,0x33 +0x0115,0x08 +0x0117,0x06 +0x0118,0x09 +0x0119,0x33 +0x011A,0x08 +0x011C,0x06 +0x011D,0x09 +0x011E,0x33 +0x011F,0x08 +0x0121,0x06 +0x0122,0x09 +0x0123,0x33 +0x0124,0x08 +0x0126,0x06 +0x0127,0x09 +0x0128,0x33 +0x0129,0x08 +0x012B,0x06 +0x012C,0x09 +0x012D,0x33 +0x012E,0x08 +0x0130,0x06 +0x0131,0x09 +0x0132,0x33 +0x0133,0x08 +0x013A,0x01 +0x013B,0x09 +0x013C,0x3B +0x013D,0x28 +0x013F,0x00 +0x0140,0x00 +0x0141,0x40 +0x0206,0x00 +0x0208,0x00 +0x0209,0x00 +0x020A,0x00 +0x020B,0x00 +0x020C,0x00 +0x020D,0x00 +0x020E,0x00 +0x020F,0x00 +0x0210,0x00 +0x0211,0x00 +0x0212,0x00 +0x0213,0x00 +0x0214,0x00 +0x0215,0x00 +0x0216,0x00 +0x0217,0x00 +0x0218,0x00 +0x0219,0x00 +0x021A,0x00 +0x021B,0x00 +0x021C,0x02 +0x021D,0x00 +0x021E,0x00 +0x021F,0x00 +0x0220,0x00 +0x0221,0x00 +0x0222,0x01 +0x0223,0x00 +0x0224,0x00 +0x0225,0x00 +0x0226,0x00 +0x0227,0x00 +0x0228,0x00 +0x0229,0x00 +0x022A,0x00 +0x022B,0x00 +0x022C,0x00 +0x022D,0x00 +0x022E,0x00 +0x022F,0x00 +0x0235,0x00 +0x0236,0x00 +0x0237,0x00 +0x0238,0x00 +0x0239,0x52 +0x023A,0x00 +0x023B,0x00 +0x023C,0x00 +0x023D,0x00 +0x023E,0x80 +0x024A,0x00 +0x024B,0x00 +0x024C,0x00 +0x024D,0x00 +0x024E,0x00 +0x024F,0x00 +0x0250,0x00 +0x0251,0x00 +0x0252,0x00 +0x0253,0x00 +0x0254,0x00 +0x0255,0x00 +0x0256,0x00 +0x0257,0x00 +0x0258,0x00 +0x0259,0x00 +0x025A,0x00 +0x025B,0x00 +0x025C,0x00 +0x025D,0x00 +0x025E,0x00 +0x025F,0x00 +0x0260,0x00 +0x0261,0x00 +0x0262,0x00 +0x0263,0x00 +0x0264,0x00 +0x0268,0x00 +0x0269,0x00 +0x026A,0x00 +0x026B,0x48 +0x026C,0x54 +0x026D,0x47 +0x026E,0x36 +0x026F,0x51 +0x0270,0x31 +0x0271,0x36 +0x0272,0x31 +0x0302,0x00 +0x0303,0x00 +0x0304,0x00 +0x0305,0x80 +0x0306,0x14 +0x0307,0x00 +0x0308,0x00 +0x0309,0x00 +0x030A,0x00 +0x030B,0x80 +0x030C,0x00 +0x030D,0x00 +0x030E,0x00 +0x030F,0x00 +0x0310,0x00 +0x0311,0x00 +0x0312,0x00 +0x0313,0x00 +0x0314,0x00 +0x0315,0x00 +0x0316,0x00 +0x0317,0x00 +0x0318,0x00 +0x0319,0x00 +0x031A,0x00 +0x031B,0x00 +0x031C,0x00 +0x031D,0x00 +0x031E,0x00 +0x031F,0x00 +0x0320,0x00 +0x0321,0x00 +0x0322,0x00 +0x0323,0x00 +0x0324,0x00 +0x0325,0x00 +0x0326,0x00 +0x0327,0x00 +0x0328,0x00 +0x0329,0x00 +0x032A,0x00 +0x032B,0x00 +0x032C,0x00 +0x032D,0x00 +0x032E,0x00 +0x032F,0x00 +0x0330,0x00 +0x0331,0x00 +0x0332,0x00 +0x0333,0x00 +0x0334,0x00 +0x0335,0x00 +0x0336,0x00 +0x0337,0x00 +0x0338,0x00 +0x0339,0x1F +0x033B,0x00 +0x033C,0x00 +0x033D,0x00 +0x033E,0x00 +0x033F,0x00 +0x0340,0x00 +0x0341,0x00 +0x0342,0x00 +0x0343,0x00 +0x0344,0x00 +0x0345,0x00 +0x0346,0x00 +0x0347,0x00 +0x0348,0x00 +0x0349,0x00 +0x034A,0x00 +0x034B,0x00 +0x034C,0x00 +0x034D,0x00 +0x034E,0x00 +0x034F,0x00 +0x0350,0x00 +0x0351,0x00 +0x0352,0x00 +0x0353,0x00 +0x0354,0x00 +0x0355,0x00 +0x0356,0x00 +0x0357,0x00 +0x0358,0x00 +0x0359,0x00 +0x035A,0x00 +0x035B,0x00 +0x035C,0x00 +0x035D,0x00 +0x035E,0x00 +0x035F,0x00 +0x0360,0x00 +0x0361,0x00 +0x0362,0x00 +0x0802,0x00 +0x0803,0x00 +0x0804,0x00 +0x0805,0x00 +0x0806,0x00 +0x0807,0x00 +0x0808,0x00 +0x0809,0x00 +0x080A,0x00 +0x080B,0x00 +0x080C,0x00 +0x080D,0x00 +0x080E,0x00 +0x080F,0x00 +0x0810,0x00 +0x0811,0x00 +0x0812,0x00 +0x0813,0x00 +0x0814,0x00 +0x0815,0x00 +0x0816,0x00 +0x0817,0x00 +0x0818,0x00 +0x0819,0x00 +0x081A,0x00 +0x081B,0x00 +0x081C,0x00 +0x081D,0x00 +0x081E,0x00 +0x081F,0x00 +0x0820,0x00 +0x0821,0x00 +0x0822,0x00 +0x0823,0x00 +0x0824,0x00 +0x0825,0x00 +0x0826,0x00 +0x0827,0x00 +0x0828,0x00 +0x0829,0x00 +0x082A,0x00 +0x082B,0x00 +0x082C,0x00 +0x082D,0x00 +0x082E,0x00 +0x082F,0x00 +0x0830,0x00 +0x0831,0x00 +0x0832,0x00 +0x0833,0x00 +0x0834,0x00 +0x0835,0x00 +0x0836,0x00 +0x0837,0x00 +0x0838,0x00 +0x0839,0x00 +0x083A,0x00 +0x083B,0x00 +0x083C,0x00 +0x083D,0x00 +0x083E,0x00 +0x083F,0x00 +0x0840,0x00 +0x0841,0x00 +0x0842,0x00 +0x0843,0x00 +0x0844,0x00 +0x0845,0x00 +0x0846,0x00 +0x0847,0x00 +0x0848,0x00 +0x0849,0x00 +0x084A,0x00 +0x084B,0x00 +0x084C,0x00 +0x084D,0x00 +0x084E,0x00 +0x084F,0x00 +0x0850,0x00 +0x0851,0x00 +0x0852,0x00 +0x0853,0x00 +0x0854,0x00 +0x0855,0x00 +0x0856,0x00 +0x0857,0x00 +0x0858,0x00 +0x0859,0x00 +0x085A,0x00 +0x085B,0x00 +0x085C,0x00 +0x085D,0x00 +0x085E,0x00 +0x085F,0x00 +0x0860,0x00 +0x0861,0x00 +0x090E,0x00 +0x091C,0x04 +0x0943,0x00 +0x0949,0x04 +0x094A,0x40 +0x094E,0x49 +0x094F,0x02 +0x095E,0x00 +0x0A02,0x00 +0x0A03,0x01 +0x0A04,0x01 +0x0A05,0x01 +0x0A14,0x00 +0x0A1A,0x00 +0x0A20,0x00 +0x0A26,0x00 +0x0A2C,0x00 +0x0B44,0x0F +0x0B4A,0x1E +0x0B57,0xA0 +0x0B58,0x00 +# End configuration registers +# +# Start configuration postamble +0x001C,0x01 +0x0B24,0xC3 +0x0B25,0x02 +# End configuration postamble diff --git a/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj new file mode 100644 index 000000000..3af140b28 Binary files /dev/null and b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj differ diff --git a/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.py b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.py new file mode 100755 index 000000000..beb65f0aa --- /dev/null +++ b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.py @@ -0,0 +1,606 @@ +#!/usr/bin/env python +""" +Generates an I2C init module for multiple chips +""" + +from jinja2 import Template + + +def si5341_cmds(regs, dev_addr=0x77): + cur_page = None + cur_addr = None + + cmds = [] + + print(f"Reading register list file '{regs}'...") + + with open(regs, "r") as f: + for line in f: + line = line.strip() + if not line or line == "Address,Data": + continue + if line[0] == '#': + cmds.append(f"// {line[1:].strip()}") + + if line.startswith("# Delay"): + cmds.append("9'b000011010; // delay 300 ms") + cur_addr = None + + continue + + d = line.split(",") + addr = int(d[0], 0) + page = (addr >> 8) & 0xff + data = int(d[1], 0) + + if page != cur_page: + cmds.append(f"{{2'b01, 7'h{dev_addr:02x}}};") + cmds.append("{1'b1, 8'h01};") + cmds.append(f"{{1'b1, 8'h{page:02x}}}; // set page {page:#04x}") + cur_page = page + cur_addr = None + + if addr != cur_addr: + cmds.append(f"{{2'b01, 7'h{dev_addr:02x}}};") + cmds.append(f"{{1'b1, 8'h{addr & 0xff:02x}}};") + cur_addr = addr + + cmds.append(f"{{1'b1, 8'h{data:02x}}}; // write {data:#04x} to {addr:#06x}") + cur_addr += 1 + + return cmds + + +def mux_cmds(val, dev_addr): + cmds = [] + cmds.append(f"{{2'b01, 7'h{dev_addr:02x}}};") + cmds.append(f"{{1'b1, 8'h{val:02x}}};") + cmds.append("9'b001000001; // I2C stop") + return cmds + + +def main(): + cmds = [] + + cmds.append("// Initial delay") + cmds.append("9'b000010110; // delay 30 ms") + + # Si5341 on HTG 9200 + cmds.append("// Set muxes to select U48 Si5341 on HTG-9200") + cmds.extend(mux_cmds(0x00, 0x70)) + cmds.extend(mux_cmds(0x04, 0x71)) + + cmds.extend(si5341_cmds("HTG9200_161-9k2_161-Registers.txt", 0x77)) + + # Si5341 on FMC+ + cmds.append("// Set muxes to select U7 Si5341 on HTG-FMC-x6-QSFP28") + cmds.extend(mux_cmds(0x00, 0x70)) + cmds.extend(mux_cmds(0x02, 0x71)) + + cmds.extend(si5341_cmds("HTG9200_HTG_FMC_6QSFP_161-HTG6Q161-Registers.txt", 0x77)) + + generate(cmds) + + +def generate(cmds=None, name=None, output=None): + if cmds is None: + raise Exception("Command list is required") + + if name is None: + name = "si5341_i2c_init" + + if output is None: + output = name + ".v" + + print(f"Generating Si5341 I2C init module {name}...") + + cmds.append("9'd0; // end") + + cmd_str = "" + cmd_count = 0 + + for cmd in cmds: + if cmd.startswith('//'): + cmd_str += f" {cmd}\n" + else: + cmd_str += f" init_data[{cmd_count}] = {cmd}\n" + cmd_count += 1 + + t = Template(u"""/* + +Copyright (c) 2015-2021 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * {{name}} + */ +module {{name}} ( + input wire clk, + input wire rst, + + /* + * I2C master interface + */ + output wire [6:0] m_axis_cmd_address, + output wire m_axis_cmd_start, + output wire m_axis_cmd_read, + output wire m_axis_cmd_write, + output wire m_axis_cmd_write_multiple, + output wire m_axis_cmd_stop, + output wire m_axis_cmd_valid, + input wire m_axis_cmd_ready, + + output wire [7:0] m_axis_data_tdata, + output wire m_axis_data_tvalid, + input wire m_axis_data_tready, + output wire m_axis_data_tlast, + + /* + * Status + */ + output wire busy, + + /* + * Configuration + */ + input wire start +); + +/* + +Generic module for I2C bus initialization. Good for use when multiple devices +on an I2C bus must be initialized on system start without intervention of a +general-purpose processor. + +Copy this file and change init_data and INIT_DATA_LEN as needed. + +This module can be used in two modes: simple device initialization, or multiple +device initialization. In multiple device mode, the same initialization sequence +can be performed on multiple different device addresses. + +To use single device mode, only use the start write to address and write data commands. +The module will generate the I2C commands in sequential order. Terminate the list +with a 0 entry. + +To use the multiple device mode, use the start data and start address block commands +to set up lists of initialization data and device addresses. The module enters +multiple device mode upon seeing a start data block command. The module stores the +offset of the start of the data block and then skips ahead until it reaches a start +address block command. The module will store the offset to the address block and +read the first address in the block. Then it will jump back to the data block +and execute it, substituting the stored address for each current address write +command. Upon reaching the start address block command, the module will read out the +next address and start again at the top of the data block. If the module encounters +a start data block command while looking for an address, then it will store a new data +offset and then look for a start address block command. Terminate the list with a 0 +entry. Normal address commands will operate normally inside a data block. + +Commands: + +00 0000000 : stop +00 0000001 : exit multiple device mode +00 0000011 : start write to current address +00 0001000 : start address block +00 0001001 : start data block +00 001dddd : delay 2**(16+d) cycles +00 1000001 : send I2C stop +01 aaaaaaa : start write to address +1 dddddddd : write 8-bit data + +Examples + +write 0x11223344 to register 0x0004 on device at 0x50 + +01 1010000 start write to 0x50 +1 00000000 write address 0x0004 +1 00000100 +1 00010001 write data 0x11223344 +1 00100010 +1 00110011 +1 01000100 +0 00000000 stop + +write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53 + +00 0001001 start data block +00 0000011 start write to current address +1 00000000 write address 0x0004 +1 00000100 +1 00010001 write data 0x11223344 +1 00100010 +1 00110011 +1 01000100 +00 0001000 start address block +01 1010000 address 0x50 +01 1010001 address 0x51 +01 1010010 address 0x52 +01 1010011 address 0x53 +00 0000000 stop + +*/ + +// init_data ROM +localparam INIT_DATA_LEN = {{cmd_count}}; + +reg [8:0] init_data [INIT_DATA_LEN-1:0]; + +initial begin +{{cmd_str-}} +end + +localparam [3:0] + STATE_IDLE = 3'd0, + STATE_RUN = 3'd1, + STATE_TABLE_1 = 3'd2, + STATE_TABLE_2 = 3'd3, + STATE_TABLE_3 = 3'd4; + +reg [4:0] state_reg = STATE_IDLE, state_next; + +parameter AW = $clog2(INIT_DATA_LEN); + +reg [8:0] init_data_reg = 9'd0; + +reg [AW-1:0] address_reg = {AW{1'b0}}, address_next; +reg [AW-1:0] address_ptr_reg = {AW{1'b0}}, address_ptr_next; +reg [AW-1:0] data_ptr_reg = {AW{1'b0}}, data_ptr_next; + +reg [6:0] cur_address_reg = 7'd0, cur_address_next; + +reg [31:0] delay_counter_reg = 32'd0, delay_counter_next; + +reg [6:0] m_axis_cmd_address_reg = 7'd0, m_axis_cmd_address_next; +reg m_axis_cmd_start_reg = 1'b0, m_axis_cmd_start_next; +reg m_axis_cmd_write_reg = 1'b0, m_axis_cmd_write_next; +reg m_axis_cmd_stop_reg = 1'b0, m_axis_cmd_stop_next; +reg m_axis_cmd_valid_reg = 1'b0, m_axis_cmd_valid_next; + +reg [7:0] m_axis_data_tdata_reg = 8'd0, m_axis_data_tdata_next; +reg m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next; + +reg start_flag_reg = 1'b0, start_flag_next; + +reg busy_reg = 1'b0; + +assign m_axis_cmd_address = m_axis_cmd_address_reg; +assign m_axis_cmd_start = m_axis_cmd_start_reg; +assign m_axis_cmd_read = 1'b0; +assign m_axis_cmd_write = m_axis_cmd_write_reg; +assign m_axis_cmd_write_multiple = 1'b0; +assign m_axis_cmd_stop = m_axis_cmd_stop_reg; +assign m_axis_cmd_valid = m_axis_cmd_valid_reg; + +assign m_axis_data_tdata = m_axis_data_tdata_reg; +assign m_axis_data_tvalid = m_axis_data_tvalid_reg; +assign m_axis_data_tlast = 1'b1; + +assign busy = busy_reg; + +always @* begin + state_next = STATE_IDLE; + + address_next = address_reg; + address_ptr_next = address_ptr_reg; + data_ptr_next = data_ptr_reg; + + cur_address_next = cur_address_reg; + + delay_counter_next = delay_counter_reg; + + m_axis_cmd_address_next = m_axis_cmd_address_reg; + m_axis_cmd_start_next = m_axis_cmd_start_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready); + m_axis_cmd_write_next = m_axis_cmd_write_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready); + m_axis_cmd_stop_next = m_axis_cmd_stop_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready); + m_axis_cmd_valid_next = m_axis_cmd_valid_reg & ~m_axis_cmd_ready; + + m_axis_data_tdata_next = m_axis_data_tdata_reg; + m_axis_data_tvalid_next = m_axis_data_tvalid_reg & ~m_axis_data_tready; + + start_flag_next = start_flag_reg; + + if (m_axis_cmd_valid | m_axis_data_tvalid) begin + // wait for output registers to clear + state_next = state_reg; + end else if (delay_counter_reg != 0) begin + // delay + delay_counter_next = delay_counter_reg - 1; + state_next = state_reg; + end else begin + case (state_reg) + STATE_IDLE: begin + // wait for start signal + if (~start_flag_reg & start) begin + address_next = {AW{1'b0}}; + start_flag_next = 1'b1; + state_next = STATE_RUN; + end else begin + state_next = STATE_IDLE; + end + end + STATE_RUN: begin + // process commands + if (init_data_reg[8] == 1'b1) begin + // write data + m_axis_cmd_write_next = 1'b1; + m_axis_cmd_stop_next = 1'b0; + m_axis_cmd_valid_next = 1'b1; + + m_axis_data_tdata_next = init_data_reg[7:0]; + m_axis_data_tvalid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg[8:7] == 2'b01) begin + // write address + m_axis_cmd_address_next = init_data_reg[6:0]; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg[8:4] == 5'b00001) begin + // delay + delay_counter_next = 32'd1 << (init_data_reg[3:0]+16); + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg == 9'b001000001) begin + // send stop + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_RUN; + end + end + STATE_TABLE_1: begin + // find address table start + if (init_data_reg == 9'b000001000) begin + // address table start + address_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_2; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end + end + STATE_TABLE_2: begin + // find next address + if (init_data_reg[8:7] == 2'b01) begin + // write address command + // store address and move to data table + cur_address_next = init_data_reg[6:0]; + address_ptr_next = address_reg + 1; + address_next = data_ptr_reg; + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'd1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_2; + end + end + STATE_TABLE_3: begin + // process data table with selected address + if (init_data_reg[8] == 1'b1) begin + // write data + m_axis_cmd_write_next = 1'b1; + m_axis_cmd_stop_next = 1'b0; + m_axis_cmd_valid_next = 1'b1; + + m_axis_data_tdata_next = init_data_reg[7:0]; + m_axis_data_tvalid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg[8:7] == 2'b01) begin + // write address + m_axis_cmd_address_next = init_data_reg[6:0]; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000000011) begin + // write current address + m_axis_cmd_address_next = cur_address_reg; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b001000001) begin + // send stop + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'b000001000) begin + // address table start + address_next = address_ptr_reg; + state_next = STATE_TABLE_2; + end else if (init_data_reg == 9'd1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_3; + end + end + endcase + end +end + +always @(posedge clk) begin + state_reg <= state_next; + + // read init_data ROM + init_data_reg <= init_data[address_next]; + + address_reg <= address_next; + address_ptr_reg <= address_ptr_next; + data_ptr_reg <= data_ptr_next; + + cur_address_reg <= cur_address_next; + + delay_counter_reg <= delay_counter_next; + + m_axis_cmd_address_reg <= m_axis_cmd_address_next; + m_axis_cmd_start_reg <= m_axis_cmd_start_next; + m_axis_cmd_write_reg <= m_axis_cmd_write_next; + m_axis_cmd_stop_reg <= m_axis_cmd_stop_next; + m_axis_cmd_valid_reg <= m_axis_cmd_valid_next; + + m_axis_data_tdata_reg <= m_axis_data_tdata_next; + m_axis_data_tvalid_reg <= m_axis_data_tvalid_next; + + start_flag_reg <= start & start_flag_next; + + busy_reg <= (state_reg != STATE_IDLE); + + if (rst) begin + state_reg <= STATE_IDLE; + + init_data_reg <= 9'd0; + + address_reg <= {AW{1'b0}}; + address_ptr_reg <= {AW{1'b0}}; + data_ptr_reg <= {AW{1'b0}}; + + cur_address_reg <= 7'd0; + + delay_counter_reg <= 32'd0; + + m_axis_cmd_valid_reg <= 1'b0; + + m_axis_data_tvalid_reg <= 1'b0; + + start_flag_reg <= 1'b0; + + busy_reg <= 1'b0; + end +end + +endmodule + +`resetall + +""") + + print(f"Writing file '{output}'...") + + with open(output, 'w') as f: + f.write(t.render( + cmd_str=cmd_str, + cmd_count=cmd_count, + name=name + )) + f.flush() + + print("Done") + + +if __name__ == "__main__": + main() diff --git a/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.v b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.v new file mode 100644 index 000000000..f67fd21fa --- /dev/null +++ b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.v @@ -0,0 +1,1600 @@ +/* + +Copyright (c) 2015-2021 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * si5341_i2c_init + */ +module si5341_i2c_init ( + input wire clk, + input wire rst, + + /* + * I2C master interface + */ + output wire [6:0] m_axis_cmd_address, + output wire m_axis_cmd_start, + output wire m_axis_cmd_read, + output wire m_axis_cmd_write, + output wire m_axis_cmd_write_multiple, + output wire m_axis_cmd_stop, + output wire m_axis_cmd_valid, + input wire m_axis_cmd_ready, + + output wire [7:0] m_axis_data_tdata, + output wire m_axis_data_tvalid, + input wire m_axis_data_tready, + output wire m_axis_data_tlast, + + /* + * Status + */ + output wire busy, + + /* + * Configuration + */ + input wire start +); + +/* + +Generic module for I2C bus initialization. Good for use when multiple devices +on an I2C bus must be initialized on system start without intervention of a +general-purpose processor. + +Copy this file and change init_data and INIT_DATA_LEN as needed. + +This module can be used in two modes: simple device initialization, or multiple +device initialization. In multiple device mode, the same initialization sequence +can be performed on multiple different device addresses. + +To use single device mode, only use the start write to address and write data commands. +The module will generate the I2C commands in sequential order. Terminate the list +with a 0 entry. + +To use the multiple device mode, use the start data and start address block commands +to set up lists of initialization data and device addresses. The module enters +multiple device mode upon seeing a start data block command. The module stores the +offset of the start of the data block and then skips ahead until it reaches a start +address block command. The module will store the offset to the address block and +read the first address in the block. Then it will jump back to the data block +and execute it, substituting the stored address for each current address write +command. Upon reaching the start address block command, the module will read out the +next address and start again at the top of the data block. If the module encounters +a start data block command while looking for an address, then it will store a new data +offset and then look for a start address block command. Terminate the list with a 0 +entry. Normal address commands will operate normally inside a data block. + +Commands: + +00 0000000 : stop +00 0000001 : exit multiple device mode +00 0000011 : start write to current address +00 0001000 : start address block +00 0001001 : start data block +00 001dddd : delay 2**(16+d) cycles +00 1000001 : send I2C stop +01 aaaaaaa : start write to address +1 dddddddd : write 8-bit data + +Examples + +write 0x11223344 to register 0x0004 on device at 0x50 + +01 1010000 start write to 0x50 +1 00000000 write address 0x0004 +1 00000100 +1 00010001 write data 0x11223344 +1 00100010 +1 00110011 +1 01000100 +0 00000000 stop + +write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53 + +00 0001001 start data block +00 0000011 start write to current address +1 00000000 write address 0x0004 +1 00000100 +1 00010001 write data 0x11223344 +1 00100010 +1 00110011 +1 01000100 +00 0001000 start address block +01 1010000 address 0x50 +01 1010001 address 0x51 +01 1010010 address 0x52 +01 1010011 address 0x53 +00 0000000 stop + +*/ + +// init_data ROM +localparam INIT_DATA_LEN = 1070; + +reg [8:0] init_data [INIT_DATA_LEN-1:0]; + +initial begin + // Initial delay + init_data[0] = 9'b000010110; // delay 30 ms + // Set muxes to select U48 Si5341 on HTG-9200 + init_data[1] = {2'b01, 7'h70}; + init_data[2] = {1'b1, 8'h00}; + init_data[3] = 9'b001000001; // I2C stop + init_data[4] = {2'b01, 7'h71}; + init_data[5] = {1'b1, 8'h04}; + init_data[6] = 9'b001000001; // I2C stop + // Si534x/7x/8x/9x Registers Script + // + // Part: Si5341 + // Project File: X:\Projects\verilog-ethernet\example\HTG9200\fpga_25g\pll\HTG9200_161-9k2_161.slabtimeproj + // Design ID: 9k2_161 + // Includes Pre/Post Download Control Register Writes: Yes + // Die Revision: B1 + // Creator: ClockBuilder Pro v4.1 [2021-09-22] + // Created On: 2023-07-19 01:38:53 GMT-07:00 + // + // Start configuration preamble + init_data[7] = {2'b01, 7'h77}; + init_data[8] = {1'b1, 8'h01}; + init_data[9] = {1'b1, 8'h0b}; // set page 0x0b + init_data[10] = {2'b01, 7'h77}; + init_data[11] = {1'b1, 8'h24}; + init_data[12] = {1'b1, 8'hc0}; // write 0xc0 to 0x0b24 + init_data[13] = {1'b1, 8'h00}; // write 0x00 to 0x0b25 + // Rev D stuck divider fix + init_data[14] = {2'b01, 7'h77}; + init_data[15] = {1'b1, 8'h01}; + init_data[16] = {1'b1, 8'h05}; // set page 0x05 + init_data[17] = {2'b01, 7'h77}; + init_data[18] = {1'b1, 8'h02}; + init_data[19] = {1'b1, 8'h01}; // write 0x01 to 0x0502 + init_data[20] = {2'b01, 7'h77}; + init_data[21] = {1'b1, 8'h05}; + init_data[22] = {1'b1, 8'h03}; // write 0x03 to 0x0505 + init_data[23] = {2'b01, 7'h77}; + init_data[24] = {1'b1, 8'h01}; + init_data[25] = {1'b1, 8'h09}; // set page 0x09 + init_data[26] = {2'b01, 7'h77}; + init_data[27] = {1'b1, 8'h57}; + init_data[28] = {1'b1, 8'h17}; // write 0x17 to 0x0957 + init_data[29] = {2'b01, 7'h77}; + init_data[30] = {1'b1, 8'h01}; + init_data[31] = {1'b1, 8'h0b}; // set page 0x0b + init_data[32] = {2'b01, 7'h77}; + init_data[33] = {1'b1, 8'h4e}; + init_data[34] = {1'b1, 8'h1a}; // write 0x1a to 0x0b4e + // End configuration preamble + // + // Delay 300 msec + init_data[35] = 9'b000011010; // delay 300 ms + // Delay is worst case time for device to complete any calibration + // that is running due to device state change previous to this script + // being processed. + // + // Start configuration registers + init_data[36] = {2'b01, 7'h77}; + init_data[37] = {1'b1, 8'h01}; + init_data[38] = {1'b1, 8'h00}; // set page 0x00 + init_data[39] = {2'b01, 7'h77}; + init_data[40] = {1'b1, 8'h06}; + init_data[41] = {1'b1, 8'h00}; // write 0x00 to 0x0006 + init_data[42] = {1'b1, 8'h00}; // write 0x00 to 0x0007 + init_data[43] = {1'b1, 8'h00}; // write 0x00 to 0x0008 + init_data[44] = {2'b01, 7'h77}; + init_data[45] = {1'b1, 8'h0b}; + init_data[46] = {1'b1, 8'h74}; // write 0x74 to 0x000b + init_data[47] = {2'b01, 7'h77}; + init_data[48] = {1'b1, 8'h17}; + init_data[49] = {1'b1, 8'hd0}; // write 0xd0 to 0x0017 + init_data[50] = {1'b1, 8'hff}; // write 0xff to 0x0018 + init_data[51] = {2'b01, 7'h77}; + init_data[52] = {1'b1, 8'h21}; + init_data[53] = {1'b1, 8'h0b}; // write 0x0b to 0x0021 + init_data[54] = {1'b1, 8'h00}; // write 0x00 to 0x0022 + init_data[55] = {2'b01, 7'h77}; + init_data[56] = {1'b1, 8'h2b}; + init_data[57] = {1'b1, 8'h02}; // write 0x02 to 0x002b + init_data[58] = {1'b1, 8'h33}; // write 0x33 to 0x002c + init_data[59] = {1'b1, 8'h05}; // write 0x05 to 0x002d + init_data[60] = {1'b1, 8'hae}; // write 0xae to 0x002e + init_data[61] = {1'b1, 8'h00}; // write 0x00 to 0x002f + init_data[62] = {1'b1, 8'hae}; // write 0xae to 0x0030 + init_data[63] = {1'b1, 8'h00}; // write 0x00 to 0x0031 + init_data[64] = {1'b1, 8'h00}; // write 0x00 to 0x0032 + init_data[65] = {1'b1, 8'h00}; // write 0x00 to 0x0033 + init_data[66] = {1'b1, 8'h00}; // write 0x00 to 0x0034 + init_data[67] = {1'b1, 8'h00}; // write 0x00 to 0x0035 + init_data[68] = {1'b1, 8'hae}; // write 0xae to 0x0036 + init_data[69] = {1'b1, 8'h00}; // write 0x00 to 0x0037 + init_data[70] = {1'b1, 8'hae}; // write 0xae to 0x0038 + init_data[71] = {1'b1, 8'h00}; // write 0x00 to 0x0039 + init_data[72] = {1'b1, 8'h00}; // write 0x00 to 0x003a + init_data[73] = {1'b1, 8'h00}; // write 0x00 to 0x003b + init_data[74] = {1'b1, 8'h00}; // write 0x00 to 0x003c + init_data[75] = {1'b1, 8'h00}; // write 0x00 to 0x003d + init_data[76] = {2'b01, 7'h77}; + init_data[77] = {1'b1, 8'h41}; + init_data[78] = {1'b1, 8'h07}; // write 0x07 to 0x0041 + init_data[79] = {1'b1, 8'h07}; // write 0x07 to 0x0042 + init_data[80] = {1'b1, 8'h00}; // write 0x00 to 0x0043 + init_data[81] = {1'b1, 8'h00}; // write 0x00 to 0x0044 + init_data[82] = {2'b01, 7'h77}; + init_data[83] = {1'b1, 8'h9e}; + init_data[84] = {1'b1, 8'h00}; // write 0x00 to 0x009e + init_data[85] = {2'b01, 7'h77}; + init_data[86] = {1'b1, 8'h01}; + init_data[87] = {1'b1, 8'h01}; // set page 0x01 + init_data[88] = {2'b01, 7'h77}; + init_data[89] = {1'b1, 8'h02}; + init_data[90] = {1'b1, 8'h01}; // write 0x01 to 0x0102 + init_data[91] = {2'b01, 7'h77}; + init_data[92] = {1'b1, 8'h08}; + init_data[93] = {1'b1, 8'h06}; // write 0x06 to 0x0108 + init_data[94] = {1'b1, 8'h09}; // write 0x09 to 0x0109 + init_data[95] = {1'b1, 8'h3b}; // write 0x3b to 0x010a + init_data[96] = {1'b1, 8'h28}; // write 0x28 to 0x010b + init_data[97] = {2'b01, 7'h77}; + init_data[98] = {1'b1, 8'h0d}; + init_data[99] = {1'b1, 8'h06}; // write 0x06 to 0x010d + init_data[100] = {1'b1, 8'h09}; // write 0x09 to 0x010e + init_data[101] = {1'b1, 8'h3b}; // write 0x3b to 0x010f + init_data[102] = {1'b1, 8'h28}; // write 0x28 to 0x0110 + init_data[103] = {2'b01, 7'h77}; + init_data[104] = {1'b1, 8'h12}; + init_data[105] = {1'b1, 8'h02}; // write 0x02 to 0x0112 + init_data[106] = {1'b1, 8'h09}; // write 0x09 to 0x0113 + init_data[107] = {1'b1, 8'h3b}; // write 0x3b to 0x0114 + init_data[108] = {1'b1, 8'h29}; // write 0x29 to 0x0115 + init_data[109] = {2'b01, 7'h77}; + init_data[110] = {1'b1, 8'h17}; + init_data[111] = {1'b1, 8'h06}; // write 0x06 to 0x0117 + init_data[112] = {1'b1, 8'h09}; // write 0x09 to 0x0118 + init_data[113] = {1'b1, 8'h3b}; // write 0x3b to 0x0119 + init_data[114] = {1'b1, 8'h28}; // write 0x28 to 0x011a + init_data[115] = {2'b01, 7'h77}; + init_data[116] = {1'b1, 8'h1c}; + init_data[117] = {1'b1, 8'h06}; // write 0x06 to 0x011c + init_data[118] = {1'b1, 8'h09}; // write 0x09 to 0x011d + init_data[119] = {1'b1, 8'h3b}; // write 0x3b to 0x011e + init_data[120] = {1'b1, 8'h28}; // write 0x28 to 0x011f + init_data[121] = {2'b01, 7'h77}; + init_data[122] = {1'b1, 8'h21}; + init_data[123] = {1'b1, 8'h06}; // write 0x06 to 0x0121 + init_data[124] = {1'b1, 8'h09}; // write 0x09 to 0x0122 + init_data[125] = {1'b1, 8'h3b}; // write 0x3b to 0x0123 + init_data[126] = {1'b1, 8'h28}; // write 0x28 to 0x0124 + init_data[127] = {2'b01, 7'h77}; + init_data[128] = {1'b1, 8'h26}; + init_data[129] = {1'b1, 8'h06}; // write 0x06 to 0x0126 + init_data[130] = {1'b1, 8'h09}; // write 0x09 to 0x0127 + init_data[131] = {1'b1, 8'h3b}; // write 0x3b to 0x0128 + init_data[132] = {1'b1, 8'h28}; // write 0x28 to 0x0129 + init_data[133] = {2'b01, 7'h77}; + init_data[134] = {1'b1, 8'h2b}; + init_data[135] = {1'b1, 8'h06}; // write 0x06 to 0x012b + init_data[136] = {1'b1, 8'h09}; // write 0x09 to 0x012c + init_data[137] = {1'b1, 8'h3b}; // write 0x3b to 0x012d + init_data[138] = {1'b1, 8'h28}; // write 0x28 to 0x012e + init_data[139] = {2'b01, 7'h77}; + init_data[140] = {1'b1, 8'h30}; + init_data[141] = {1'b1, 8'h06}; // write 0x06 to 0x0130 + init_data[142] = {1'b1, 8'h09}; // write 0x09 to 0x0131 + init_data[143] = {1'b1, 8'h3b}; // write 0x3b to 0x0132 + init_data[144] = {1'b1, 8'h28}; // write 0x28 to 0x0133 + init_data[145] = {2'b01, 7'h77}; + init_data[146] = {1'b1, 8'h3a}; + init_data[147] = {1'b1, 8'h06}; // write 0x06 to 0x013a + init_data[148] = {1'b1, 8'h09}; // write 0x09 to 0x013b + init_data[149] = {1'b1, 8'h3b}; // write 0x3b to 0x013c + init_data[150] = {1'b1, 8'h28}; // write 0x28 to 0x013d + init_data[151] = {2'b01, 7'h77}; + init_data[152] = {1'b1, 8'h3f}; + init_data[153] = {1'b1, 8'h00}; // write 0x00 to 0x013f + init_data[154] = {1'b1, 8'h00}; // write 0x00 to 0x0140 + init_data[155] = {1'b1, 8'h40}; // write 0x40 to 0x0141 + init_data[156] = {2'b01, 7'h77}; + init_data[157] = {1'b1, 8'h01}; + init_data[158] = {1'b1, 8'h02}; // set page 0x02 + init_data[159] = {2'b01, 7'h77}; + init_data[160] = {1'b1, 8'h06}; + init_data[161] = {1'b1, 8'h00}; // write 0x00 to 0x0206 + init_data[162] = {2'b01, 7'h77}; + init_data[163] = {1'b1, 8'h08}; + init_data[164] = {1'b1, 8'h02}; // write 0x02 to 0x0208 + init_data[165] = {1'b1, 8'h00}; // write 0x00 to 0x0209 + init_data[166] = {1'b1, 8'h00}; // write 0x00 to 0x020a + init_data[167] = {1'b1, 8'h00}; // write 0x00 to 0x020b + init_data[168] = {1'b1, 8'h00}; // write 0x00 to 0x020c + init_data[169] = {1'b1, 8'h00}; // write 0x00 to 0x020d + init_data[170] = {1'b1, 8'h01}; // write 0x01 to 0x020e + init_data[171] = {1'b1, 8'h00}; // write 0x00 to 0x020f + init_data[172] = {1'b1, 8'h00}; // write 0x00 to 0x0210 + init_data[173] = {1'b1, 8'h00}; // write 0x00 to 0x0211 + init_data[174] = {1'b1, 8'h02}; // write 0x02 to 0x0212 + init_data[175] = {1'b1, 8'h00}; // write 0x00 to 0x0213 + init_data[176] = {1'b1, 8'h00}; // write 0x00 to 0x0214 + init_data[177] = {1'b1, 8'h00}; // write 0x00 to 0x0215 + init_data[178] = {1'b1, 8'h00}; // write 0x00 to 0x0216 + init_data[179] = {1'b1, 8'h00}; // write 0x00 to 0x0217 + init_data[180] = {1'b1, 8'h01}; // write 0x01 to 0x0218 + init_data[181] = {1'b1, 8'h00}; // write 0x00 to 0x0219 + init_data[182] = {1'b1, 8'h00}; // write 0x00 to 0x021a + init_data[183] = {1'b1, 8'h00}; // write 0x00 to 0x021b + init_data[184] = {1'b1, 8'h00}; // write 0x00 to 0x021c + init_data[185] = {1'b1, 8'h00}; // write 0x00 to 0x021d + init_data[186] = {1'b1, 8'h00}; // write 0x00 to 0x021e + init_data[187] = {1'b1, 8'h00}; // write 0x00 to 0x021f + init_data[188] = {1'b1, 8'h00}; // write 0x00 to 0x0220 + init_data[189] = {1'b1, 8'h00}; // write 0x00 to 0x0221 + init_data[190] = {1'b1, 8'h00}; // write 0x00 to 0x0222 + init_data[191] = {1'b1, 8'h00}; // write 0x00 to 0x0223 + init_data[192] = {1'b1, 8'h00}; // write 0x00 to 0x0224 + init_data[193] = {1'b1, 8'h00}; // write 0x00 to 0x0225 + init_data[194] = {1'b1, 8'h00}; // write 0x00 to 0x0226 + init_data[195] = {1'b1, 8'h00}; // write 0x00 to 0x0227 + init_data[196] = {1'b1, 8'h00}; // write 0x00 to 0x0228 + init_data[197] = {1'b1, 8'h00}; // write 0x00 to 0x0229 + init_data[198] = {1'b1, 8'h00}; // write 0x00 to 0x022a + init_data[199] = {1'b1, 8'h00}; // write 0x00 to 0x022b + init_data[200] = {1'b1, 8'h00}; // write 0x00 to 0x022c + init_data[201] = {1'b1, 8'h00}; // write 0x00 to 0x022d + init_data[202] = {1'b1, 8'h00}; // write 0x00 to 0x022e + init_data[203] = {1'b1, 8'h00}; // write 0x00 to 0x022f + init_data[204] = {2'b01, 7'h77}; + init_data[205] = {1'b1, 8'h35}; + init_data[206] = {1'b1, 8'h00}; // write 0x00 to 0x0235 + init_data[207] = {1'b1, 8'h00}; // write 0x00 to 0x0236 + init_data[208] = {1'b1, 8'h00}; // write 0x00 to 0x0237 + init_data[209] = {1'b1, 8'h90}; // write 0x90 to 0x0238 + init_data[210] = {1'b1, 8'h54}; // write 0x54 to 0x0239 + init_data[211] = {1'b1, 8'h00}; // write 0x00 to 0x023a + init_data[212] = {1'b1, 8'h00}; // write 0x00 to 0x023b + init_data[213] = {1'b1, 8'h00}; // write 0x00 to 0x023c + init_data[214] = {1'b1, 8'h00}; // write 0x00 to 0x023d + init_data[215] = {1'b1, 8'h80}; // write 0x80 to 0x023e + init_data[216] = {2'b01, 7'h77}; + init_data[217] = {1'b1, 8'h4a}; + init_data[218] = {1'b1, 8'h00}; // write 0x00 to 0x024a + init_data[219] = {1'b1, 8'h00}; // write 0x00 to 0x024b + init_data[220] = {1'b1, 8'h00}; // write 0x00 to 0x024c + init_data[221] = {1'b1, 8'h00}; // write 0x00 to 0x024d + init_data[222] = {1'b1, 8'h00}; // write 0x00 to 0x024e + init_data[223] = {1'b1, 8'h00}; // write 0x00 to 0x024f + init_data[224] = {1'b1, 8'h03}; // write 0x03 to 0x0250 + init_data[225] = {1'b1, 8'h00}; // write 0x00 to 0x0251 + init_data[226] = {1'b1, 8'h00}; // write 0x00 to 0x0252 + init_data[227] = {1'b1, 8'h00}; // write 0x00 to 0x0253 + init_data[228] = {1'b1, 8'h00}; // write 0x00 to 0x0254 + init_data[229] = {1'b1, 8'h00}; // write 0x00 to 0x0255 + init_data[230] = {1'b1, 8'h00}; // write 0x00 to 0x0256 + init_data[231] = {1'b1, 8'h00}; // write 0x00 to 0x0257 + init_data[232] = {1'b1, 8'h00}; // write 0x00 to 0x0258 + init_data[233] = {1'b1, 8'h00}; // write 0x00 to 0x0259 + init_data[234] = {1'b1, 8'h00}; // write 0x00 to 0x025a + init_data[235] = {1'b1, 8'h00}; // write 0x00 to 0x025b + init_data[236] = {1'b1, 8'h00}; // write 0x00 to 0x025c + init_data[237] = {1'b1, 8'h00}; // write 0x00 to 0x025d + init_data[238] = {1'b1, 8'h00}; // write 0x00 to 0x025e + init_data[239] = {1'b1, 8'h00}; // write 0x00 to 0x025f + init_data[240] = {1'b1, 8'h00}; // write 0x00 to 0x0260 + init_data[241] = {1'b1, 8'h00}; // write 0x00 to 0x0261 + init_data[242] = {1'b1, 8'h00}; // write 0x00 to 0x0262 + init_data[243] = {1'b1, 8'h00}; // write 0x00 to 0x0263 + init_data[244] = {1'b1, 8'h00}; // write 0x00 to 0x0264 + init_data[245] = {2'b01, 7'h77}; + init_data[246] = {1'b1, 8'h68}; + init_data[247] = {1'b1, 8'h00}; // write 0x00 to 0x0268 + init_data[248] = {1'b1, 8'h00}; // write 0x00 to 0x0269 + init_data[249] = {1'b1, 8'h00}; // write 0x00 to 0x026a + init_data[250] = {1'b1, 8'h39}; // write 0x39 to 0x026b + init_data[251] = {1'b1, 8'h6b}; // write 0x6b to 0x026c + init_data[252] = {1'b1, 8'h32}; // write 0x32 to 0x026d + init_data[253] = {1'b1, 8'h5f}; // write 0x5f to 0x026e + init_data[254] = {1'b1, 8'h31}; // write 0x31 to 0x026f + init_data[255] = {1'b1, 8'h36}; // write 0x36 to 0x0270 + init_data[256] = {1'b1, 8'h31}; // write 0x31 to 0x0271 + init_data[257] = {1'b1, 8'h00}; // write 0x00 to 0x0272 + init_data[258] = {2'b01, 7'h77}; + init_data[259] = {1'b1, 8'h01}; + init_data[260] = {1'b1, 8'h03}; // set page 0x03 + init_data[261] = {2'b01, 7'h77}; + init_data[262] = {1'b1, 8'h02}; + init_data[263] = {1'b1, 8'h00}; // write 0x00 to 0x0302 + init_data[264] = {1'b1, 8'h00}; // write 0x00 to 0x0303 + init_data[265] = {1'b1, 8'h00}; // write 0x00 to 0x0304 + init_data[266] = {1'b1, 8'h80}; // write 0x80 to 0x0305 + init_data[267] = {1'b1, 8'h14}; // write 0x14 to 0x0306 + init_data[268] = {1'b1, 8'h00}; // write 0x00 to 0x0307 + init_data[269] = {1'b1, 8'h00}; // write 0x00 to 0x0308 + init_data[270] = {1'b1, 8'h00}; // write 0x00 to 0x0309 + init_data[271] = {1'b1, 8'h00}; // write 0x00 to 0x030a + init_data[272] = {1'b1, 8'h80}; // write 0x80 to 0x030b + init_data[273] = {1'b1, 8'h00}; // write 0x00 to 0x030c + init_data[274] = {1'b1, 8'h00}; // write 0x00 to 0x030d + init_data[275] = {1'b1, 8'h00}; // write 0x00 to 0x030e + init_data[276] = {1'b1, 8'h10}; // write 0x10 to 0x030f + init_data[277] = {1'b1, 8'h42}; // write 0x42 to 0x0310 + init_data[278] = {1'b1, 8'h08}; // write 0x08 to 0x0311 + init_data[279] = {1'b1, 8'h00}; // write 0x00 to 0x0312 + init_data[280] = {1'b1, 8'h00}; // write 0x00 to 0x0313 + init_data[281] = {1'b1, 8'h00}; // write 0x00 to 0x0314 + init_data[282] = {1'b1, 8'h00}; // write 0x00 to 0x0315 + init_data[283] = {1'b1, 8'h80}; // write 0x80 to 0x0316 + init_data[284] = {1'b1, 8'h00}; // write 0x00 to 0x0317 + init_data[285] = {1'b1, 8'h00}; // write 0x00 to 0x0318 + init_data[286] = {1'b1, 8'h00}; // write 0x00 to 0x0319 + init_data[287] = {1'b1, 8'h00}; // write 0x00 to 0x031a + init_data[288] = {1'b1, 8'h00}; // write 0x00 to 0x031b + init_data[289] = {1'b1, 8'h00}; // write 0x00 to 0x031c + init_data[290] = {1'b1, 8'h00}; // write 0x00 to 0x031d + init_data[291] = {1'b1, 8'h00}; // write 0x00 to 0x031e + init_data[292] = {1'b1, 8'h00}; // write 0x00 to 0x031f + init_data[293] = {1'b1, 8'h00}; // write 0x00 to 0x0320 + init_data[294] = {1'b1, 8'h00}; // write 0x00 to 0x0321 + init_data[295] = {1'b1, 8'h00}; // write 0x00 to 0x0322 + init_data[296] = {1'b1, 8'h00}; // write 0x00 to 0x0323 + init_data[297] = {1'b1, 8'h00}; // write 0x00 to 0x0324 + init_data[298] = {1'b1, 8'h00}; // write 0x00 to 0x0325 + init_data[299] = {1'b1, 8'h00}; // write 0x00 to 0x0326 + init_data[300] = {1'b1, 8'h00}; // write 0x00 to 0x0327 + init_data[301] = {1'b1, 8'h00}; // write 0x00 to 0x0328 + init_data[302] = {1'b1, 8'h00}; // write 0x00 to 0x0329 + init_data[303] = {1'b1, 8'h00}; // write 0x00 to 0x032a + init_data[304] = {1'b1, 8'h00}; // write 0x00 to 0x032b + init_data[305] = {1'b1, 8'h00}; // write 0x00 to 0x032c + init_data[306] = {1'b1, 8'h00}; // write 0x00 to 0x032d + init_data[307] = {1'b1, 8'h00}; // write 0x00 to 0x032e + init_data[308] = {1'b1, 8'h00}; // write 0x00 to 0x032f + init_data[309] = {1'b1, 8'h00}; // write 0x00 to 0x0330 + init_data[310] = {1'b1, 8'h00}; // write 0x00 to 0x0331 + init_data[311] = {1'b1, 8'h00}; // write 0x00 to 0x0332 + init_data[312] = {1'b1, 8'h00}; // write 0x00 to 0x0333 + init_data[313] = {1'b1, 8'h00}; // write 0x00 to 0x0334 + init_data[314] = {1'b1, 8'h00}; // write 0x00 to 0x0335 + init_data[315] = {1'b1, 8'h00}; // write 0x00 to 0x0336 + init_data[316] = {1'b1, 8'h00}; // write 0x00 to 0x0337 + init_data[317] = {1'b1, 8'h00}; // write 0x00 to 0x0338 + init_data[318] = {1'b1, 8'h1f}; // write 0x1f to 0x0339 + init_data[319] = {2'b01, 7'h77}; + init_data[320] = {1'b1, 8'h3b}; + init_data[321] = {1'b1, 8'h00}; // write 0x00 to 0x033b + init_data[322] = {1'b1, 8'h00}; // write 0x00 to 0x033c + init_data[323] = {1'b1, 8'h00}; // write 0x00 to 0x033d + init_data[324] = {1'b1, 8'h00}; // write 0x00 to 0x033e + init_data[325] = {1'b1, 8'h00}; // write 0x00 to 0x033f + init_data[326] = {1'b1, 8'h00}; // write 0x00 to 0x0340 + init_data[327] = {1'b1, 8'h00}; // write 0x00 to 0x0341 + init_data[328] = {1'b1, 8'h00}; // write 0x00 to 0x0342 + init_data[329] = {1'b1, 8'h00}; // write 0x00 to 0x0343 + init_data[330] = {1'b1, 8'h00}; // write 0x00 to 0x0344 + init_data[331] = {1'b1, 8'h00}; // write 0x00 to 0x0345 + init_data[332] = {1'b1, 8'h00}; // write 0x00 to 0x0346 + init_data[333] = {1'b1, 8'h00}; // write 0x00 to 0x0347 + init_data[334] = {1'b1, 8'h00}; // write 0x00 to 0x0348 + init_data[335] = {1'b1, 8'h00}; // write 0x00 to 0x0349 + init_data[336] = {1'b1, 8'h00}; // write 0x00 to 0x034a + init_data[337] = {1'b1, 8'h00}; // write 0x00 to 0x034b + init_data[338] = {1'b1, 8'h00}; // write 0x00 to 0x034c + init_data[339] = {1'b1, 8'h00}; // write 0x00 to 0x034d + init_data[340] = {1'b1, 8'h00}; // write 0x00 to 0x034e + init_data[341] = {1'b1, 8'h00}; // write 0x00 to 0x034f + init_data[342] = {1'b1, 8'h00}; // write 0x00 to 0x0350 + init_data[343] = {1'b1, 8'h00}; // write 0x00 to 0x0351 + init_data[344] = {1'b1, 8'h00}; // write 0x00 to 0x0352 + init_data[345] = {1'b1, 8'h00}; // write 0x00 to 0x0353 + init_data[346] = {1'b1, 8'h00}; // write 0x00 to 0x0354 + init_data[347] = {1'b1, 8'h00}; // write 0x00 to 0x0355 + init_data[348] = {1'b1, 8'h00}; // write 0x00 to 0x0356 + init_data[349] = {1'b1, 8'h00}; // write 0x00 to 0x0357 + init_data[350] = {1'b1, 8'h00}; // write 0x00 to 0x0358 + init_data[351] = {1'b1, 8'h00}; // write 0x00 to 0x0359 + init_data[352] = {1'b1, 8'h00}; // write 0x00 to 0x035a + init_data[353] = {1'b1, 8'h00}; // write 0x00 to 0x035b + init_data[354] = {1'b1, 8'h00}; // write 0x00 to 0x035c + init_data[355] = {1'b1, 8'h00}; // write 0x00 to 0x035d + init_data[356] = {1'b1, 8'h00}; // write 0x00 to 0x035e + init_data[357] = {1'b1, 8'h00}; // write 0x00 to 0x035f + init_data[358] = {1'b1, 8'h00}; // write 0x00 to 0x0360 + init_data[359] = {1'b1, 8'h00}; // write 0x00 to 0x0361 + init_data[360] = {1'b1, 8'h00}; // write 0x00 to 0x0362 + init_data[361] = {2'b01, 7'h77}; + init_data[362] = {1'b1, 8'h01}; + init_data[363] = {1'b1, 8'h08}; // set page 0x08 + init_data[364] = {2'b01, 7'h77}; + init_data[365] = {1'b1, 8'h02}; + init_data[366] = {1'b1, 8'h00}; // write 0x00 to 0x0802 + init_data[367] = {1'b1, 8'h00}; // write 0x00 to 0x0803 + init_data[368] = {1'b1, 8'h00}; // write 0x00 to 0x0804 + init_data[369] = {1'b1, 8'h00}; // write 0x00 to 0x0805 + init_data[370] = {1'b1, 8'h00}; // write 0x00 to 0x0806 + init_data[371] = {1'b1, 8'h00}; // write 0x00 to 0x0807 + init_data[372] = {1'b1, 8'h00}; // write 0x00 to 0x0808 + init_data[373] = {1'b1, 8'h00}; // write 0x00 to 0x0809 + init_data[374] = {1'b1, 8'h00}; // write 0x00 to 0x080a + init_data[375] = {1'b1, 8'h00}; // write 0x00 to 0x080b + init_data[376] = {1'b1, 8'h00}; // write 0x00 to 0x080c + init_data[377] = {1'b1, 8'h00}; // write 0x00 to 0x080d + init_data[378] = {1'b1, 8'h00}; // write 0x00 to 0x080e + init_data[379] = {1'b1, 8'h00}; // write 0x00 to 0x080f + init_data[380] = {1'b1, 8'h00}; // write 0x00 to 0x0810 + init_data[381] = {1'b1, 8'h00}; // write 0x00 to 0x0811 + init_data[382] = {1'b1, 8'h00}; // write 0x00 to 0x0812 + init_data[383] = {1'b1, 8'h00}; // write 0x00 to 0x0813 + init_data[384] = {1'b1, 8'h00}; // write 0x00 to 0x0814 + init_data[385] = {1'b1, 8'h00}; // write 0x00 to 0x0815 + init_data[386] = {1'b1, 8'h00}; // write 0x00 to 0x0816 + init_data[387] = {1'b1, 8'h00}; // write 0x00 to 0x0817 + init_data[388] = {1'b1, 8'h00}; // write 0x00 to 0x0818 + init_data[389] = {1'b1, 8'h00}; // write 0x00 to 0x0819 + init_data[390] = {1'b1, 8'h00}; // write 0x00 to 0x081a + init_data[391] = {1'b1, 8'h00}; // write 0x00 to 0x081b + init_data[392] = {1'b1, 8'h00}; // write 0x00 to 0x081c + init_data[393] = {1'b1, 8'h00}; // write 0x00 to 0x081d + init_data[394] = {1'b1, 8'h00}; // write 0x00 to 0x081e + init_data[395] = {1'b1, 8'h00}; // write 0x00 to 0x081f + init_data[396] = {1'b1, 8'h00}; // write 0x00 to 0x0820 + init_data[397] = {1'b1, 8'h00}; // write 0x00 to 0x0821 + init_data[398] = {1'b1, 8'h00}; // write 0x00 to 0x0822 + init_data[399] = {1'b1, 8'h00}; // write 0x00 to 0x0823 + init_data[400] = {1'b1, 8'h00}; // write 0x00 to 0x0824 + init_data[401] = {1'b1, 8'h00}; // write 0x00 to 0x0825 + init_data[402] = {1'b1, 8'h00}; // write 0x00 to 0x0826 + init_data[403] = {1'b1, 8'h00}; // write 0x00 to 0x0827 + init_data[404] = {1'b1, 8'h00}; // write 0x00 to 0x0828 + init_data[405] = {1'b1, 8'h00}; // write 0x00 to 0x0829 + init_data[406] = {1'b1, 8'h00}; // write 0x00 to 0x082a + init_data[407] = {1'b1, 8'h00}; // write 0x00 to 0x082b + init_data[408] = {1'b1, 8'h00}; // write 0x00 to 0x082c + init_data[409] = {1'b1, 8'h00}; // write 0x00 to 0x082d + init_data[410] = {1'b1, 8'h00}; // write 0x00 to 0x082e + init_data[411] = {1'b1, 8'h00}; // write 0x00 to 0x082f + init_data[412] = {1'b1, 8'h00}; // write 0x00 to 0x0830 + init_data[413] = {1'b1, 8'h00}; // write 0x00 to 0x0831 + init_data[414] = {1'b1, 8'h00}; // write 0x00 to 0x0832 + init_data[415] = {1'b1, 8'h00}; // write 0x00 to 0x0833 + init_data[416] = {1'b1, 8'h00}; // write 0x00 to 0x0834 + init_data[417] = {1'b1, 8'h00}; // write 0x00 to 0x0835 + init_data[418] = {1'b1, 8'h00}; // write 0x00 to 0x0836 + init_data[419] = {1'b1, 8'h00}; // write 0x00 to 0x0837 + init_data[420] = {1'b1, 8'h00}; // write 0x00 to 0x0838 + init_data[421] = {1'b1, 8'h00}; // write 0x00 to 0x0839 + init_data[422] = {1'b1, 8'h00}; // write 0x00 to 0x083a + init_data[423] = {1'b1, 8'h00}; // write 0x00 to 0x083b + init_data[424] = {1'b1, 8'h00}; // write 0x00 to 0x083c + init_data[425] = {1'b1, 8'h00}; // write 0x00 to 0x083d + init_data[426] = {1'b1, 8'h00}; // write 0x00 to 0x083e + init_data[427] = {1'b1, 8'h00}; // write 0x00 to 0x083f + init_data[428] = {1'b1, 8'h00}; // write 0x00 to 0x0840 + init_data[429] = {1'b1, 8'h00}; // write 0x00 to 0x0841 + init_data[430] = {1'b1, 8'h00}; // write 0x00 to 0x0842 + init_data[431] = {1'b1, 8'h00}; // write 0x00 to 0x0843 + init_data[432] = {1'b1, 8'h00}; // write 0x00 to 0x0844 + init_data[433] = {1'b1, 8'h00}; // write 0x00 to 0x0845 + init_data[434] = {1'b1, 8'h00}; // write 0x00 to 0x0846 + init_data[435] = {1'b1, 8'h00}; // write 0x00 to 0x0847 + init_data[436] = {1'b1, 8'h00}; // write 0x00 to 0x0848 + init_data[437] = {1'b1, 8'h00}; // write 0x00 to 0x0849 + init_data[438] = {1'b1, 8'h00}; // write 0x00 to 0x084a + init_data[439] = {1'b1, 8'h00}; // write 0x00 to 0x084b + init_data[440] = {1'b1, 8'h00}; // write 0x00 to 0x084c + init_data[441] = {1'b1, 8'h00}; // write 0x00 to 0x084d + init_data[442] = {1'b1, 8'h00}; // write 0x00 to 0x084e + init_data[443] = {1'b1, 8'h00}; // write 0x00 to 0x084f + init_data[444] = {1'b1, 8'h00}; // write 0x00 to 0x0850 + init_data[445] = {1'b1, 8'h00}; // write 0x00 to 0x0851 + init_data[446] = {1'b1, 8'h00}; // write 0x00 to 0x0852 + init_data[447] = {1'b1, 8'h00}; // write 0x00 to 0x0853 + init_data[448] = {1'b1, 8'h00}; // write 0x00 to 0x0854 + init_data[449] = {1'b1, 8'h00}; // write 0x00 to 0x0855 + init_data[450] = {1'b1, 8'h00}; // write 0x00 to 0x0856 + init_data[451] = {1'b1, 8'h00}; // write 0x00 to 0x0857 + init_data[452] = {1'b1, 8'h00}; // write 0x00 to 0x0858 + init_data[453] = {1'b1, 8'h00}; // write 0x00 to 0x0859 + init_data[454] = {1'b1, 8'h00}; // write 0x00 to 0x085a + init_data[455] = {1'b1, 8'h00}; // write 0x00 to 0x085b + init_data[456] = {1'b1, 8'h00}; // write 0x00 to 0x085c + init_data[457] = {1'b1, 8'h00}; // write 0x00 to 0x085d + init_data[458] = {1'b1, 8'h00}; // write 0x00 to 0x085e + init_data[459] = {1'b1, 8'h00}; // write 0x00 to 0x085f + init_data[460] = {1'b1, 8'h00}; // write 0x00 to 0x0860 + init_data[461] = {1'b1, 8'h00}; // write 0x00 to 0x0861 + init_data[462] = {2'b01, 7'h77}; + init_data[463] = {1'b1, 8'h01}; + init_data[464] = {1'b1, 8'h09}; // set page 0x09 + init_data[465] = {2'b01, 7'h77}; + init_data[466] = {1'b1, 8'h0e}; + init_data[467] = {1'b1, 8'h00}; // write 0x00 to 0x090e + init_data[468] = {2'b01, 7'h77}; + init_data[469] = {1'b1, 8'h1c}; + init_data[470] = {1'b1, 8'h04}; // write 0x04 to 0x091c + init_data[471] = {2'b01, 7'h77}; + init_data[472] = {1'b1, 8'h43}; + init_data[473] = {1'b1, 8'h00}; // write 0x00 to 0x0943 + init_data[474] = {2'b01, 7'h77}; + init_data[475] = {1'b1, 8'h49}; + init_data[476] = {1'b1, 8'h03}; // write 0x03 to 0x0949 + init_data[477] = {1'b1, 8'h30}; // write 0x30 to 0x094a + init_data[478] = {2'b01, 7'h77}; + init_data[479] = {1'b1, 8'h4e}; + init_data[480] = {1'b1, 8'h49}; // write 0x49 to 0x094e + init_data[481] = {1'b1, 8'h02}; // write 0x02 to 0x094f + init_data[482] = {2'b01, 7'h77}; + init_data[483] = {1'b1, 8'h5e}; + init_data[484] = {1'b1, 8'h00}; // write 0x00 to 0x095e + init_data[485] = {2'b01, 7'h77}; + init_data[486] = {1'b1, 8'h01}; + init_data[487] = {1'b1, 8'h0a}; // set page 0x0a + init_data[488] = {2'b01, 7'h77}; + init_data[489] = {1'b1, 8'h02}; + init_data[490] = {1'b1, 8'h00}; // write 0x00 to 0x0a02 + init_data[491] = {1'b1, 8'h03}; // write 0x03 to 0x0a03 + init_data[492] = {1'b1, 8'h01}; // write 0x01 to 0x0a04 + init_data[493] = {1'b1, 8'h03}; // write 0x03 to 0x0a05 + init_data[494] = {2'b01, 7'h77}; + init_data[495] = {1'b1, 8'h14}; + init_data[496] = {1'b1, 8'h00}; // write 0x00 to 0x0a14 + init_data[497] = {2'b01, 7'h77}; + init_data[498] = {1'b1, 8'h1a}; + init_data[499] = {1'b1, 8'h00}; // write 0x00 to 0x0a1a + init_data[500] = {2'b01, 7'h77}; + init_data[501] = {1'b1, 8'h20}; + init_data[502] = {1'b1, 8'h00}; // write 0x00 to 0x0a20 + init_data[503] = {2'b01, 7'h77}; + init_data[504] = {1'b1, 8'h26}; + init_data[505] = {1'b1, 8'h00}; // write 0x00 to 0x0a26 + init_data[506] = {2'b01, 7'h77}; + init_data[507] = {1'b1, 8'h2c}; + init_data[508] = {1'b1, 8'h00}; // write 0x00 to 0x0a2c + init_data[509] = {2'b01, 7'h77}; + init_data[510] = {1'b1, 8'h01}; + init_data[511] = {1'b1, 8'h0b}; // set page 0x0b + init_data[512] = {2'b01, 7'h77}; + init_data[513] = {1'b1, 8'h44}; + init_data[514] = {1'b1, 8'h0f}; // write 0x0f to 0x0b44 + init_data[515] = {2'b01, 7'h77}; + init_data[516] = {1'b1, 8'h4a}; + init_data[517] = {1'b1, 8'h1c}; // write 0x1c to 0x0b4a + init_data[518] = {2'b01, 7'h77}; + init_data[519] = {1'b1, 8'h57}; + init_data[520] = {1'b1, 8'ha5}; // write 0xa5 to 0x0b57 + init_data[521] = {1'b1, 8'h00}; // write 0x00 to 0x0b58 + // End configuration registers + // + // Start configuration postamble + init_data[522] = {2'b01, 7'h77}; + init_data[523] = {1'b1, 8'h01}; + init_data[524] = {1'b1, 8'h00}; // set page 0x00 + init_data[525] = {2'b01, 7'h77}; + init_data[526] = {1'b1, 8'h1c}; + init_data[527] = {1'b1, 8'h01}; // write 0x01 to 0x001c + init_data[528] = {2'b01, 7'h77}; + init_data[529] = {1'b1, 8'h01}; + init_data[530] = {1'b1, 8'h0b}; // set page 0x0b + init_data[531] = {2'b01, 7'h77}; + init_data[532] = {1'b1, 8'h24}; + init_data[533] = {1'b1, 8'hc3}; // write 0xc3 to 0x0b24 + init_data[534] = {1'b1, 8'h02}; // write 0x02 to 0x0b25 + // End configuration postamble + // Set muxes to select U7 Si5341 on HTG-FMC-x6-QSFP28 + init_data[535] = {2'b01, 7'h70}; + init_data[536] = {1'b1, 8'h00}; + init_data[537] = 9'b001000001; // I2C stop + init_data[538] = {2'b01, 7'h71}; + init_data[539] = {1'b1, 8'h02}; + init_data[540] = 9'b001000001; // I2C stop + // Si534x/7x/8x/9x Registers Script + // + // Part: Si5341 + // Project File: X:\Projects\verilog-ethernet\example\HTG9200\fpga_fmc_htg_6qsfp_25g\pll\HTG9200_HTG_FMC_6QSFP_161-HTG6Q161.slabtimeproj + // Design ID: HTG6Q161 + // Includes Pre/Post Download Control Register Writes: Yes + // Die Revision: B1 + // Creator: ClockBuilder Pro v4.1 [2021-09-22] + // Created On: 2023-07-19 01:56:52 GMT-07:00 + // + // Start configuration preamble + init_data[541] = {2'b01, 7'h77}; + init_data[542] = {1'b1, 8'h01}; + init_data[543] = {1'b1, 8'h0b}; // set page 0x0b + init_data[544] = {2'b01, 7'h77}; + init_data[545] = {1'b1, 8'h24}; + init_data[546] = {1'b1, 8'hc0}; // write 0xc0 to 0x0b24 + init_data[547] = {1'b1, 8'h00}; // write 0x00 to 0x0b25 + // Rev D stuck divider fix + init_data[548] = {2'b01, 7'h77}; + init_data[549] = {1'b1, 8'h01}; + init_data[550] = {1'b1, 8'h05}; // set page 0x05 + init_data[551] = {2'b01, 7'h77}; + init_data[552] = {1'b1, 8'h02}; + init_data[553] = {1'b1, 8'h01}; // write 0x01 to 0x0502 + init_data[554] = {2'b01, 7'h77}; + init_data[555] = {1'b1, 8'h05}; + init_data[556] = {1'b1, 8'h03}; // write 0x03 to 0x0505 + init_data[557] = {2'b01, 7'h77}; + init_data[558] = {1'b1, 8'h01}; + init_data[559] = {1'b1, 8'h09}; // set page 0x09 + init_data[560] = {2'b01, 7'h77}; + init_data[561] = {1'b1, 8'h57}; + init_data[562] = {1'b1, 8'h17}; // write 0x17 to 0x0957 + init_data[563] = {2'b01, 7'h77}; + init_data[564] = {1'b1, 8'h01}; + init_data[565] = {1'b1, 8'h0b}; // set page 0x0b + init_data[566] = {2'b01, 7'h77}; + init_data[567] = {1'b1, 8'h4e}; + init_data[568] = {1'b1, 8'h1a}; // write 0x1a to 0x0b4e + // End configuration preamble + // + // Delay 300 msec + init_data[569] = 9'b000011010; // delay 300 ms + // Delay is worst case time for device to complete any calibration + // that is running due to device state change previous to this script + // being processed. + // + // Start configuration registers + init_data[570] = {2'b01, 7'h77}; + init_data[571] = {1'b1, 8'h01}; + init_data[572] = {1'b1, 8'h00}; // set page 0x00 + init_data[573] = {2'b01, 7'h77}; + init_data[574] = {1'b1, 8'h06}; + init_data[575] = {1'b1, 8'h00}; // write 0x00 to 0x0006 + init_data[576] = {1'b1, 8'h00}; // write 0x00 to 0x0007 + init_data[577] = {1'b1, 8'h00}; // write 0x00 to 0x0008 + init_data[578] = {2'b01, 7'h77}; + init_data[579] = {1'b1, 8'h0b}; + init_data[580] = {1'b1, 8'h74}; // write 0x74 to 0x000b + init_data[581] = {2'b01, 7'h77}; + init_data[582] = {1'b1, 8'h17}; + init_data[583] = {1'b1, 8'hd0}; // write 0xd0 to 0x0017 + init_data[584] = {1'b1, 8'hff}; // write 0xff to 0x0018 + init_data[585] = {2'b01, 7'h77}; + init_data[586] = {1'b1, 8'h21}; + init_data[587] = {1'b1, 8'h0d}; // write 0x0d to 0x0021 + init_data[588] = {1'b1, 8'h00}; // write 0x00 to 0x0022 + init_data[589] = {2'b01, 7'h77}; + init_data[590] = {1'b1, 8'h2b}; + init_data[591] = {1'b1, 8'h02}; // write 0x02 to 0x002b + init_data[592] = {1'b1, 8'h34}; // write 0x34 to 0x002c + init_data[593] = {1'b1, 8'h10}; // write 0x10 to 0x002d + init_data[594] = {1'b1, 8'h00}; // write 0x00 to 0x002e + init_data[595] = {1'b1, 8'h00}; // write 0x00 to 0x002f + init_data[596] = {1'b1, 8'h00}; // write 0x00 to 0x0030 + init_data[597] = {1'b1, 8'h00}; // write 0x00 to 0x0031 + init_data[598] = {1'b1, 8'ha8}; // write 0xa8 to 0x0032 + init_data[599] = {1'b1, 8'h00}; // write 0x00 to 0x0033 + init_data[600] = {1'b1, 8'h00}; // write 0x00 to 0x0034 + init_data[601] = {1'b1, 8'h00}; // write 0x00 to 0x0035 + init_data[602] = {1'b1, 8'h00}; // write 0x00 to 0x0036 + init_data[603] = {1'b1, 8'h00}; // write 0x00 to 0x0037 + init_data[604] = {1'b1, 8'h00}; // write 0x00 to 0x0038 + init_data[605] = {1'b1, 8'h00}; // write 0x00 to 0x0039 + init_data[606] = {1'b1, 8'ha8}; // write 0xa8 to 0x003a + init_data[607] = {1'b1, 8'h00}; // write 0x00 to 0x003b + init_data[608] = {1'b1, 8'h00}; // write 0x00 to 0x003c + init_data[609] = {1'b1, 8'h00}; // write 0x00 to 0x003d + init_data[610] = {2'b01, 7'h77}; + init_data[611] = {1'b1, 8'h41}; + init_data[612] = {1'b1, 8'h00}; // write 0x00 to 0x0041 + init_data[613] = {1'b1, 8'h00}; // write 0x00 to 0x0042 + init_data[614] = {1'b1, 8'h07}; // write 0x07 to 0x0043 + init_data[615] = {1'b1, 8'h00}; // write 0x00 to 0x0044 + init_data[616] = {2'b01, 7'h77}; + init_data[617] = {1'b1, 8'h9e}; + init_data[618] = {1'b1, 8'h00}; // write 0x00 to 0x009e + init_data[619] = {2'b01, 7'h77}; + init_data[620] = {1'b1, 8'h01}; + init_data[621] = {1'b1, 8'h01}; // set page 0x01 + init_data[622] = {2'b01, 7'h77}; + init_data[623] = {1'b1, 8'h02}; + init_data[624] = {1'b1, 8'h01}; // write 0x01 to 0x0102 + init_data[625] = {2'b01, 7'h77}; + init_data[626] = {1'b1, 8'h08}; + init_data[627] = {1'b1, 8'h06}; // write 0x06 to 0x0108 + init_data[628] = {1'b1, 8'h09}; // write 0x09 to 0x0109 + init_data[629] = {1'b1, 8'h33}; // write 0x33 to 0x010a + init_data[630] = {1'b1, 8'h08}; // write 0x08 to 0x010b + init_data[631] = {2'b01, 7'h77}; + init_data[632] = {1'b1, 8'h0d}; + init_data[633] = {1'b1, 8'h06}; // write 0x06 to 0x010d + init_data[634] = {1'b1, 8'h09}; // write 0x09 to 0x010e + init_data[635] = {1'b1, 8'h33}; // write 0x33 to 0x010f + init_data[636] = {1'b1, 8'h08}; // write 0x08 to 0x0110 + init_data[637] = {2'b01, 7'h77}; + init_data[638] = {1'b1, 8'h12}; + init_data[639] = {1'b1, 8'h06}; // write 0x06 to 0x0112 + init_data[640] = {1'b1, 8'h09}; // write 0x09 to 0x0113 + init_data[641] = {1'b1, 8'h33}; // write 0x33 to 0x0114 + init_data[642] = {1'b1, 8'h08}; // write 0x08 to 0x0115 + init_data[643] = {2'b01, 7'h77}; + init_data[644] = {1'b1, 8'h17}; + init_data[645] = {1'b1, 8'h06}; // write 0x06 to 0x0117 + init_data[646] = {1'b1, 8'h09}; // write 0x09 to 0x0118 + init_data[647] = {1'b1, 8'h33}; // write 0x33 to 0x0119 + init_data[648] = {1'b1, 8'h08}; // write 0x08 to 0x011a + init_data[649] = {2'b01, 7'h77}; + init_data[650] = {1'b1, 8'h1c}; + init_data[651] = {1'b1, 8'h06}; // write 0x06 to 0x011c + init_data[652] = {1'b1, 8'h09}; // write 0x09 to 0x011d + init_data[653] = {1'b1, 8'h33}; // write 0x33 to 0x011e + init_data[654] = {1'b1, 8'h08}; // write 0x08 to 0x011f + init_data[655] = {2'b01, 7'h77}; + init_data[656] = {1'b1, 8'h21}; + init_data[657] = {1'b1, 8'h06}; // write 0x06 to 0x0121 + init_data[658] = {1'b1, 8'h09}; // write 0x09 to 0x0122 + init_data[659] = {1'b1, 8'h33}; // write 0x33 to 0x0123 + init_data[660] = {1'b1, 8'h08}; // write 0x08 to 0x0124 + init_data[661] = {2'b01, 7'h77}; + init_data[662] = {1'b1, 8'h26}; + init_data[663] = {1'b1, 8'h06}; // write 0x06 to 0x0126 + init_data[664] = {1'b1, 8'h09}; // write 0x09 to 0x0127 + init_data[665] = {1'b1, 8'h33}; // write 0x33 to 0x0128 + init_data[666] = {1'b1, 8'h08}; // write 0x08 to 0x0129 + init_data[667] = {2'b01, 7'h77}; + init_data[668] = {1'b1, 8'h2b}; + init_data[669] = {1'b1, 8'h06}; // write 0x06 to 0x012b + init_data[670] = {1'b1, 8'h09}; // write 0x09 to 0x012c + init_data[671] = {1'b1, 8'h33}; // write 0x33 to 0x012d + init_data[672] = {1'b1, 8'h08}; // write 0x08 to 0x012e + init_data[673] = {2'b01, 7'h77}; + init_data[674] = {1'b1, 8'h30}; + init_data[675] = {1'b1, 8'h06}; // write 0x06 to 0x0130 + init_data[676] = {1'b1, 8'h09}; // write 0x09 to 0x0131 + init_data[677] = {1'b1, 8'h33}; // write 0x33 to 0x0132 + init_data[678] = {1'b1, 8'h08}; // write 0x08 to 0x0133 + init_data[679] = {2'b01, 7'h77}; + init_data[680] = {1'b1, 8'h3a}; + init_data[681] = {1'b1, 8'h01}; // write 0x01 to 0x013a + init_data[682] = {1'b1, 8'h09}; // write 0x09 to 0x013b + init_data[683] = {1'b1, 8'h3b}; // write 0x3b to 0x013c + init_data[684] = {1'b1, 8'h28}; // write 0x28 to 0x013d + init_data[685] = {2'b01, 7'h77}; + init_data[686] = {1'b1, 8'h3f}; + init_data[687] = {1'b1, 8'h00}; // write 0x00 to 0x013f + init_data[688] = {1'b1, 8'h00}; // write 0x00 to 0x0140 + init_data[689] = {1'b1, 8'h40}; // write 0x40 to 0x0141 + init_data[690] = {2'b01, 7'h77}; + init_data[691] = {1'b1, 8'h01}; + init_data[692] = {1'b1, 8'h02}; // set page 0x02 + init_data[693] = {2'b01, 7'h77}; + init_data[694] = {1'b1, 8'h06}; + init_data[695] = {1'b1, 8'h00}; // write 0x00 to 0x0206 + init_data[696] = {2'b01, 7'h77}; + init_data[697] = {1'b1, 8'h08}; + init_data[698] = {1'b1, 8'h00}; // write 0x00 to 0x0208 + init_data[699] = {1'b1, 8'h00}; // write 0x00 to 0x0209 + init_data[700] = {1'b1, 8'h00}; // write 0x00 to 0x020a + init_data[701] = {1'b1, 8'h00}; // write 0x00 to 0x020b + init_data[702] = {1'b1, 8'h00}; // write 0x00 to 0x020c + init_data[703] = {1'b1, 8'h00}; // write 0x00 to 0x020d + init_data[704] = {1'b1, 8'h00}; // write 0x00 to 0x020e + init_data[705] = {1'b1, 8'h00}; // write 0x00 to 0x020f + init_data[706] = {1'b1, 8'h00}; // write 0x00 to 0x0210 + init_data[707] = {1'b1, 8'h00}; // write 0x00 to 0x0211 + init_data[708] = {1'b1, 8'h00}; // write 0x00 to 0x0212 + init_data[709] = {1'b1, 8'h00}; // write 0x00 to 0x0213 + init_data[710] = {1'b1, 8'h00}; // write 0x00 to 0x0214 + init_data[711] = {1'b1, 8'h00}; // write 0x00 to 0x0215 + init_data[712] = {1'b1, 8'h00}; // write 0x00 to 0x0216 + init_data[713] = {1'b1, 8'h00}; // write 0x00 to 0x0217 + init_data[714] = {1'b1, 8'h00}; // write 0x00 to 0x0218 + init_data[715] = {1'b1, 8'h00}; // write 0x00 to 0x0219 + init_data[716] = {1'b1, 8'h00}; // write 0x00 to 0x021a + init_data[717] = {1'b1, 8'h00}; // write 0x00 to 0x021b + init_data[718] = {1'b1, 8'h02}; // write 0x02 to 0x021c + init_data[719] = {1'b1, 8'h00}; // write 0x00 to 0x021d + init_data[720] = {1'b1, 8'h00}; // write 0x00 to 0x021e + init_data[721] = {1'b1, 8'h00}; // write 0x00 to 0x021f + init_data[722] = {1'b1, 8'h00}; // write 0x00 to 0x0220 + init_data[723] = {1'b1, 8'h00}; // write 0x00 to 0x0221 + init_data[724] = {1'b1, 8'h01}; // write 0x01 to 0x0222 + init_data[725] = {1'b1, 8'h00}; // write 0x00 to 0x0223 + init_data[726] = {1'b1, 8'h00}; // write 0x00 to 0x0224 + init_data[727] = {1'b1, 8'h00}; // write 0x00 to 0x0225 + init_data[728] = {1'b1, 8'h00}; // write 0x00 to 0x0226 + init_data[729] = {1'b1, 8'h00}; // write 0x00 to 0x0227 + init_data[730] = {1'b1, 8'h00}; // write 0x00 to 0x0228 + init_data[731] = {1'b1, 8'h00}; // write 0x00 to 0x0229 + init_data[732] = {1'b1, 8'h00}; // write 0x00 to 0x022a + init_data[733] = {1'b1, 8'h00}; // write 0x00 to 0x022b + init_data[734] = {1'b1, 8'h00}; // write 0x00 to 0x022c + init_data[735] = {1'b1, 8'h00}; // write 0x00 to 0x022d + init_data[736] = {1'b1, 8'h00}; // write 0x00 to 0x022e + init_data[737] = {1'b1, 8'h00}; // write 0x00 to 0x022f + init_data[738] = {2'b01, 7'h77}; + init_data[739] = {1'b1, 8'h35}; + init_data[740] = {1'b1, 8'h00}; // write 0x00 to 0x0235 + init_data[741] = {1'b1, 8'h00}; // write 0x00 to 0x0236 + init_data[742] = {1'b1, 8'h00}; // write 0x00 to 0x0237 + init_data[743] = {1'b1, 8'h00}; // write 0x00 to 0x0238 + init_data[744] = {1'b1, 8'h52}; // write 0x52 to 0x0239 + init_data[745] = {1'b1, 8'h00}; // write 0x00 to 0x023a + init_data[746] = {1'b1, 8'h00}; // write 0x00 to 0x023b + init_data[747] = {1'b1, 8'h00}; // write 0x00 to 0x023c + init_data[748] = {1'b1, 8'h00}; // write 0x00 to 0x023d + init_data[749] = {1'b1, 8'h80}; // write 0x80 to 0x023e + init_data[750] = {2'b01, 7'h77}; + init_data[751] = {1'b1, 8'h4a}; + init_data[752] = {1'b1, 8'h00}; // write 0x00 to 0x024a + init_data[753] = {1'b1, 8'h00}; // write 0x00 to 0x024b + init_data[754] = {1'b1, 8'h00}; // write 0x00 to 0x024c + init_data[755] = {1'b1, 8'h00}; // write 0x00 to 0x024d + init_data[756] = {1'b1, 8'h00}; // write 0x00 to 0x024e + init_data[757] = {1'b1, 8'h00}; // write 0x00 to 0x024f + init_data[758] = {1'b1, 8'h00}; // write 0x00 to 0x0250 + init_data[759] = {1'b1, 8'h00}; // write 0x00 to 0x0251 + init_data[760] = {1'b1, 8'h00}; // write 0x00 to 0x0252 + init_data[761] = {1'b1, 8'h00}; // write 0x00 to 0x0253 + init_data[762] = {1'b1, 8'h00}; // write 0x00 to 0x0254 + init_data[763] = {1'b1, 8'h00}; // write 0x00 to 0x0255 + init_data[764] = {1'b1, 8'h00}; // write 0x00 to 0x0256 + init_data[765] = {1'b1, 8'h00}; // write 0x00 to 0x0257 + init_data[766] = {1'b1, 8'h00}; // write 0x00 to 0x0258 + init_data[767] = {1'b1, 8'h00}; // write 0x00 to 0x0259 + init_data[768] = {1'b1, 8'h00}; // write 0x00 to 0x025a + init_data[769] = {1'b1, 8'h00}; // write 0x00 to 0x025b + init_data[770] = {1'b1, 8'h00}; // write 0x00 to 0x025c + init_data[771] = {1'b1, 8'h00}; // write 0x00 to 0x025d + init_data[772] = {1'b1, 8'h00}; // write 0x00 to 0x025e + init_data[773] = {1'b1, 8'h00}; // write 0x00 to 0x025f + init_data[774] = {1'b1, 8'h00}; // write 0x00 to 0x0260 + init_data[775] = {1'b1, 8'h00}; // write 0x00 to 0x0261 + init_data[776] = {1'b1, 8'h00}; // write 0x00 to 0x0262 + init_data[777] = {1'b1, 8'h00}; // write 0x00 to 0x0263 + init_data[778] = {1'b1, 8'h00}; // write 0x00 to 0x0264 + init_data[779] = {2'b01, 7'h77}; + init_data[780] = {1'b1, 8'h68}; + init_data[781] = {1'b1, 8'h00}; // write 0x00 to 0x0268 + init_data[782] = {1'b1, 8'h00}; // write 0x00 to 0x0269 + init_data[783] = {1'b1, 8'h00}; // write 0x00 to 0x026a + init_data[784] = {1'b1, 8'h48}; // write 0x48 to 0x026b + init_data[785] = {1'b1, 8'h54}; // write 0x54 to 0x026c + init_data[786] = {1'b1, 8'h47}; // write 0x47 to 0x026d + init_data[787] = {1'b1, 8'h36}; // write 0x36 to 0x026e + init_data[788] = {1'b1, 8'h51}; // write 0x51 to 0x026f + init_data[789] = {1'b1, 8'h31}; // write 0x31 to 0x0270 + init_data[790] = {1'b1, 8'h36}; // write 0x36 to 0x0271 + init_data[791] = {1'b1, 8'h31}; // write 0x31 to 0x0272 + init_data[792] = {2'b01, 7'h77}; + init_data[793] = {1'b1, 8'h01}; + init_data[794] = {1'b1, 8'h03}; // set page 0x03 + init_data[795] = {2'b01, 7'h77}; + init_data[796] = {1'b1, 8'h02}; + init_data[797] = {1'b1, 8'h00}; // write 0x00 to 0x0302 + init_data[798] = {1'b1, 8'h00}; // write 0x00 to 0x0303 + init_data[799] = {1'b1, 8'h00}; // write 0x00 to 0x0304 + init_data[800] = {1'b1, 8'h80}; // write 0x80 to 0x0305 + init_data[801] = {1'b1, 8'h14}; // write 0x14 to 0x0306 + init_data[802] = {1'b1, 8'h00}; // write 0x00 to 0x0307 + init_data[803] = {1'b1, 8'h00}; // write 0x00 to 0x0308 + init_data[804] = {1'b1, 8'h00}; // write 0x00 to 0x0309 + init_data[805] = {1'b1, 8'h00}; // write 0x00 to 0x030a + init_data[806] = {1'b1, 8'h80}; // write 0x80 to 0x030b + init_data[807] = {1'b1, 8'h00}; // write 0x00 to 0x030c + init_data[808] = {1'b1, 8'h00}; // write 0x00 to 0x030d + init_data[809] = {1'b1, 8'h00}; // write 0x00 to 0x030e + init_data[810] = {1'b1, 8'h00}; // write 0x00 to 0x030f + init_data[811] = {1'b1, 8'h00}; // write 0x00 to 0x0310 + init_data[812] = {1'b1, 8'h00}; // write 0x00 to 0x0311 + init_data[813] = {1'b1, 8'h00}; // write 0x00 to 0x0312 + init_data[814] = {1'b1, 8'h00}; // write 0x00 to 0x0313 + init_data[815] = {1'b1, 8'h00}; // write 0x00 to 0x0314 + init_data[816] = {1'b1, 8'h00}; // write 0x00 to 0x0315 + init_data[817] = {1'b1, 8'h00}; // write 0x00 to 0x0316 + init_data[818] = {1'b1, 8'h00}; // write 0x00 to 0x0317 + init_data[819] = {1'b1, 8'h00}; // write 0x00 to 0x0318 + init_data[820] = {1'b1, 8'h00}; // write 0x00 to 0x0319 + init_data[821] = {1'b1, 8'h00}; // write 0x00 to 0x031a + init_data[822] = {1'b1, 8'h00}; // write 0x00 to 0x031b + init_data[823] = {1'b1, 8'h00}; // write 0x00 to 0x031c + init_data[824] = {1'b1, 8'h00}; // write 0x00 to 0x031d + init_data[825] = {1'b1, 8'h00}; // write 0x00 to 0x031e + init_data[826] = {1'b1, 8'h00}; // write 0x00 to 0x031f + init_data[827] = {1'b1, 8'h00}; // write 0x00 to 0x0320 + init_data[828] = {1'b1, 8'h00}; // write 0x00 to 0x0321 + init_data[829] = {1'b1, 8'h00}; // write 0x00 to 0x0322 + init_data[830] = {1'b1, 8'h00}; // write 0x00 to 0x0323 + init_data[831] = {1'b1, 8'h00}; // write 0x00 to 0x0324 + init_data[832] = {1'b1, 8'h00}; // write 0x00 to 0x0325 + init_data[833] = {1'b1, 8'h00}; // write 0x00 to 0x0326 + init_data[834] = {1'b1, 8'h00}; // write 0x00 to 0x0327 + init_data[835] = {1'b1, 8'h00}; // write 0x00 to 0x0328 + init_data[836] = {1'b1, 8'h00}; // write 0x00 to 0x0329 + init_data[837] = {1'b1, 8'h00}; // write 0x00 to 0x032a + init_data[838] = {1'b1, 8'h00}; // write 0x00 to 0x032b + init_data[839] = {1'b1, 8'h00}; // write 0x00 to 0x032c + init_data[840] = {1'b1, 8'h00}; // write 0x00 to 0x032d + init_data[841] = {1'b1, 8'h00}; // write 0x00 to 0x032e + init_data[842] = {1'b1, 8'h00}; // write 0x00 to 0x032f + init_data[843] = {1'b1, 8'h00}; // write 0x00 to 0x0330 + init_data[844] = {1'b1, 8'h00}; // write 0x00 to 0x0331 + init_data[845] = {1'b1, 8'h00}; // write 0x00 to 0x0332 + init_data[846] = {1'b1, 8'h00}; // write 0x00 to 0x0333 + init_data[847] = {1'b1, 8'h00}; // write 0x00 to 0x0334 + init_data[848] = {1'b1, 8'h00}; // write 0x00 to 0x0335 + init_data[849] = {1'b1, 8'h00}; // write 0x00 to 0x0336 + init_data[850] = {1'b1, 8'h00}; // write 0x00 to 0x0337 + init_data[851] = {1'b1, 8'h00}; // write 0x00 to 0x0338 + init_data[852] = {1'b1, 8'h1f}; // write 0x1f to 0x0339 + init_data[853] = {2'b01, 7'h77}; + init_data[854] = {1'b1, 8'h3b}; + init_data[855] = {1'b1, 8'h00}; // write 0x00 to 0x033b + init_data[856] = {1'b1, 8'h00}; // write 0x00 to 0x033c + init_data[857] = {1'b1, 8'h00}; // write 0x00 to 0x033d + init_data[858] = {1'b1, 8'h00}; // write 0x00 to 0x033e + init_data[859] = {1'b1, 8'h00}; // write 0x00 to 0x033f + init_data[860] = {1'b1, 8'h00}; // write 0x00 to 0x0340 + init_data[861] = {1'b1, 8'h00}; // write 0x00 to 0x0341 + init_data[862] = {1'b1, 8'h00}; // write 0x00 to 0x0342 + init_data[863] = {1'b1, 8'h00}; // write 0x00 to 0x0343 + init_data[864] = {1'b1, 8'h00}; // write 0x00 to 0x0344 + init_data[865] = {1'b1, 8'h00}; // write 0x00 to 0x0345 + init_data[866] = {1'b1, 8'h00}; // write 0x00 to 0x0346 + init_data[867] = {1'b1, 8'h00}; // write 0x00 to 0x0347 + init_data[868] = {1'b1, 8'h00}; // write 0x00 to 0x0348 + init_data[869] = {1'b1, 8'h00}; // write 0x00 to 0x0349 + init_data[870] = {1'b1, 8'h00}; // write 0x00 to 0x034a + init_data[871] = {1'b1, 8'h00}; // write 0x00 to 0x034b + init_data[872] = {1'b1, 8'h00}; // write 0x00 to 0x034c + init_data[873] = {1'b1, 8'h00}; // write 0x00 to 0x034d + init_data[874] = {1'b1, 8'h00}; // write 0x00 to 0x034e + init_data[875] = {1'b1, 8'h00}; // write 0x00 to 0x034f + init_data[876] = {1'b1, 8'h00}; // write 0x00 to 0x0350 + init_data[877] = {1'b1, 8'h00}; // write 0x00 to 0x0351 + init_data[878] = {1'b1, 8'h00}; // write 0x00 to 0x0352 + init_data[879] = {1'b1, 8'h00}; // write 0x00 to 0x0353 + init_data[880] = {1'b1, 8'h00}; // write 0x00 to 0x0354 + init_data[881] = {1'b1, 8'h00}; // write 0x00 to 0x0355 + init_data[882] = {1'b1, 8'h00}; // write 0x00 to 0x0356 + init_data[883] = {1'b1, 8'h00}; // write 0x00 to 0x0357 + init_data[884] = {1'b1, 8'h00}; // write 0x00 to 0x0358 + init_data[885] = {1'b1, 8'h00}; // write 0x00 to 0x0359 + init_data[886] = {1'b1, 8'h00}; // write 0x00 to 0x035a + init_data[887] = {1'b1, 8'h00}; // write 0x00 to 0x035b + init_data[888] = {1'b1, 8'h00}; // write 0x00 to 0x035c + init_data[889] = {1'b1, 8'h00}; // write 0x00 to 0x035d + init_data[890] = {1'b1, 8'h00}; // write 0x00 to 0x035e + init_data[891] = {1'b1, 8'h00}; // write 0x00 to 0x035f + init_data[892] = {1'b1, 8'h00}; // write 0x00 to 0x0360 + init_data[893] = {1'b1, 8'h00}; // write 0x00 to 0x0361 + init_data[894] = {1'b1, 8'h00}; // write 0x00 to 0x0362 + init_data[895] = {2'b01, 7'h77}; + init_data[896] = {1'b1, 8'h01}; + init_data[897] = {1'b1, 8'h08}; // set page 0x08 + init_data[898] = {2'b01, 7'h77}; + init_data[899] = {1'b1, 8'h02}; + init_data[900] = {1'b1, 8'h00}; // write 0x00 to 0x0802 + init_data[901] = {1'b1, 8'h00}; // write 0x00 to 0x0803 + init_data[902] = {1'b1, 8'h00}; // write 0x00 to 0x0804 + init_data[903] = {1'b1, 8'h00}; // write 0x00 to 0x0805 + init_data[904] = {1'b1, 8'h00}; // write 0x00 to 0x0806 + init_data[905] = {1'b1, 8'h00}; // write 0x00 to 0x0807 + init_data[906] = {1'b1, 8'h00}; // write 0x00 to 0x0808 + init_data[907] = {1'b1, 8'h00}; // write 0x00 to 0x0809 + init_data[908] = {1'b1, 8'h00}; // write 0x00 to 0x080a + init_data[909] = {1'b1, 8'h00}; // write 0x00 to 0x080b + init_data[910] = {1'b1, 8'h00}; // write 0x00 to 0x080c + init_data[911] = {1'b1, 8'h00}; // write 0x00 to 0x080d + init_data[912] = {1'b1, 8'h00}; // write 0x00 to 0x080e + init_data[913] = {1'b1, 8'h00}; // write 0x00 to 0x080f + init_data[914] = {1'b1, 8'h00}; // write 0x00 to 0x0810 + init_data[915] = {1'b1, 8'h00}; // write 0x00 to 0x0811 + init_data[916] = {1'b1, 8'h00}; // write 0x00 to 0x0812 + init_data[917] = {1'b1, 8'h00}; // write 0x00 to 0x0813 + init_data[918] = {1'b1, 8'h00}; // write 0x00 to 0x0814 + init_data[919] = {1'b1, 8'h00}; // write 0x00 to 0x0815 + init_data[920] = {1'b1, 8'h00}; // write 0x00 to 0x0816 + init_data[921] = {1'b1, 8'h00}; // write 0x00 to 0x0817 + init_data[922] = {1'b1, 8'h00}; // write 0x00 to 0x0818 + init_data[923] = {1'b1, 8'h00}; // write 0x00 to 0x0819 + init_data[924] = {1'b1, 8'h00}; // write 0x00 to 0x081a + init_data[925] = {1'b1, 8'h00}; // write 0x00 to 0x081b + init_data[926] = {1'b1, 8'h00}; // write 0x00 to 0x081c + init_data[927] = {1'b1, 8'h00}; // write 0x00 to 0x081d + init_data[928] = {1'b1, 8'h00}; // write 0x00 to 0x081e + init_data[929] = {1'b1, 8'h00}; // write 0x00 to 0x081f + init_data[930] = {1'b1, 8'h00}; // write 0x00 to 0x0820 + init_data[931] = {1'b1, 8'h00}; // write 0x00 to 0x0821 + init_data[932] = {1'b1, 8'h00}; // write 0x00 to 0x0822 + init_data[933] = {1'b1, 8'h00}; // write 0x00 to 0x0823 + init_data[934] = {1'b1, 8'h00}; // write 0x00 to 0x0824 + init_data[935] = {1'b1, 8'h00}; // write 0x00 to 0x0825 + init_data[936] = {1'b1, 8'h00}; // write 0x00 to 0x0826 + init_data[937] = {1'b1, 8'h00}; // write 0x00 to 0x0827 + init_data[938] = {1'b1, 8'h00}; // write 0x00 to 0x0828 + init_data[939] = {1'b1, 8'h00}; // write 0x00 to 0x0829 + init_data[940] = {1'b1, 8'h00}; // write 0x00 to 0x082a + init_data[941] = {1'b1, 8'h00}; // write 0x00 to 0x082b + init_data[942] = {1'b1, 8'h00}; // write 0x00 to 0x082c + init_data[943] = {1'b1, 8'h00}; // write 0x00 to 0x082d + init_data[944] = {1'b1, 8'h00}; // write 0x00 to 0x082e + init_data[945] = {1'b1, 8'h00}; // write 0x00 to 0x082f + init_data[946] = {1'b1, 8'h00}; // write 0x00 to 0x0830 + init_data[947] = {1'b1, 8'h00}; // write 0x00 to 0x0831 + init_data[948] = {1'b1, 8'h00}; // write 0x00 to 0x0832 + init_data[949] = {1'b1, 8'h00}; // write 0x00 to 0x0833 + init_data[950] = {1'b1, 8'h00}; // write 0x00 to 0x0834 + init_data[951] = {1'b1, 8'h00}; // write 0x00 to 0x0835 + init_data[952] = {1'b1, 8'h00}; // write 0x00 to 0x0836 + init_data[953] = {1'b1, 8'h00}; // write 0x00 to 0x0837 + init_data[954] = {1'b1, 8'h00}; // write 0x00 to 0x0838 + init_data[955] = {1'b1, 8'h00}; // write 0x00 to 0x0839 + init_data[956] = {1'b1, 8'h00}; // write 0x00 to 0x083a + init_data[957] = {1'b1, 8'h00}; // write 0x00 to 0x083b + init_data[958] = {1'b1, 8'h00}; // write 0x00 to 0x083c + init_data[959] = {1'b1, 8'h00}; // write 0x00 to 0x083d + init_data[960] = {1'b1, 8'h00}; // write 0x00 to 0x083e + init_data[961] = {1'b1, 8'h00}; // write 0x00 to 0x083f + init_data[962] = {1'b1, 8'h00}; // write 0x00 to 0x0840 + init_data[963] = {1'b1, 8'h00}; // write 0x00 to 0x0841 + init_data[964] = {1'b1, 8'h00}; // write 0x00 to 0x0842 + init_data[965] = {1'b1, 8'h00}; // write 0x00 to 0x0843 + init_data[966] = {1'b1, 8'h00}; // write 0x00 to 0x0844 + init_data[967] = {1'b1, 8'h00}; // write 0x00 to 0x0845 + init_data[968] = {1'b1, 8'h00}; // write 0x00 to 0x0846 + init_data[969] = {1'b1, 8'h00}; // write 0x00 to 0x0847 + init_data[970] = {1'b1, 8'h00}; // write 0x00 to 0x0848 + init_data[971] = {1'b1, 8'h00}; // write 0x00 to 0x0849 + init_data[972] = {1'b1, 8'h00}; // write 0x00 to 0x084a + init_data[973] = {1'b1, 8'h00}; // write 0x00 to 0x084b + init_data[974] = {1'b1, 8'h00}; // write 0x00 to 0x084c + init_data[975] = {1'b1, 8'h00}; // write 0x00 to 0x084d + init_data[976] = {1'b1, 8'h00}; // write 0x00 to 0x084e + init_data[977] = {1'b1, 8'h00}; // write 0x00 to 0x084f + init_data[978] = {1'b1, 8'h00}; // write 0x00 to 0x0850 + init_data[979] = {1'b1, 8'h00}; // write 0x00 to 0x0851 + init_data[980] = {1'b1, 8'h00}; // write 0x00 to 0x0852 + init_data[981] = {1'b1, 8'h00}; // write 0x00 to 0x0853 + init_data[982] = {1'b1, 8'h00}; // write 0x00 to 0x0854 + init_data[983] = {1'b1, 8'h00}; // write 0x00 to 0x0855 + init_data[984] = {1'b1, 8'h00}; // write 0x00 to 0x0856 + init_data[985] = {1'b1, 8'h00}; // write 0x00 to 0x0857 + init_data[986] = {1'b1, 8'h00}; // write 0x00 to 0x0858 + init_data[987] = {1'b1, 8'h00}; // write 0x00 to 0x0859 + init_data[988] = {1'b1, 8'h00}; // write 0x00 to 0x085a + init_data[989] = {1'b1, 8'h00}; // write 0x00 to 0x085b + init_data[990] = {1'b1, 8'h00}; // write 0x00 to 0x085c + init_data[991] = {1'b1, 8'h00}; // write 0x00 to 0x085d + init_data[992] = {1'b1, 8'h00}; // write 0x00 to 0x085e + init_data[993] = {1'b1, 8'h00}; // write 0x00 to 0x085f + init_data[994] = {1'b1, 8'h00}; // write 0x00 to 0x0860 + init_data[995] = {1'b1, 8'h00}; // write 0x00 to 0x0861 + init_data[996] = {2'b01, 7'h77}; + init_data[997] = {1'b1, 8'h01}; + init_data[998] = {1'b1, 8'h09}; // set page 0x09 + init_data[999] = {2'b01, 7'h77}; + init_data[1000] = {1'b1, 8'h0e}; + init_data[1001] = {1'b1, 8'h00}; // write 0x00 to 0x090e + init_data[1002] = {2'b01, 7'h77}; + init_data[1003] = {1'b1, 8'h1c}; + init_data[1004] = {1'b1, 8'h04}; // write 0x04 to 0x091c + init_data[1005] = {2'b01, 7'h77}; + init_data[1006] = {1'b1, 8'h43}; + init_data[1007] = {1'b1, 8'h00}; // write 0x00 to 0x0943 + init_data[1008] = {2'b01, 7'h77}; + init_data[1009] = {1'b1, 8'h49}; + init_data[1010] = {1'b1, 8'h04}; // write 0x04 to 0x0949 + init_data[1011] = {1'b1, 8'h40}; // write 0x40 to 0x094a + init_data[1012] = {2'b01, 7'h77}; + init_data[1013] = {1'b1, 8'h4e}; + init_data[1014] = {1'b1, 8'h49}; // write 0x49 to 0x094e + init_data[1015] = {1'b1, 8'h02}; // write 0x02 to 0x094f + init_data[1016] = {2'b01, 7'h77}; + init_data[1017] = {1'b1, 8'h5e}; + init_data[1018] = {1'b1, 8'h00}; // write 0x00 to 0x095e + init_data[1019] = {2'b01, 7'h77}; + init_data[1020] = {1'b1, 8'h01}; + init_data[1021] = {1'b1, 8'h0a}; // set page 0x0a + init_data[1022] = {2'b01, 7'h77}; + init_data[1023] = {1'b1, 8'h02}; + init_data[1024] = {1'b1, 8'h00}; // write 0x00 to 0x0a02 + init_data[1025] = {1'b1, 8'h01}; // write 0x01 to 0x0a03 + init_data[1026] = {1'b1, 8'h01}; // write 0x01 to 0x0a04 + init_data[1027] = {1'b1, 8'h01}; // write 0x01 to 0x0a05 + init_data[1028] = {2'b01, 7'h77}; + init_data[1029] = {1'b1, 8'h14}; + init_data[1030] = {1'b1, 8'h00}; // write 0x00 to 0x0a14 + init_data[1031] = {2'b01, 7'h77}; + init_data[1032] = {1'b1, 8'h1a}; + init_data[1033] = {1'b1, 8'h00}; // write 0x00 to 0x0a1a + init_data[1034] = {2'b01, 7'h77}; + init_data[1035] = {1'b1, 8'h20}; + init_data[1036] = {1'b1, 8'h00}; // write 0x00 to 0x0a20 + init_data[1037] = {2'b01, 7'h77}; + init_data[1038] = {1'b1, 8'h26}; + init_data[1039] = {1'b1, 8'h00}; // write 0x00 to 0x0a26 + init_data[1040] = {2'b01, 7'h77}; + init_data[1041] = {1'b1, 8'h2c}; + init_data[1042] = {1'b1, 8'h00}; // write 0x00 to 0x0a2c + init_data[1043] = {2'b01, 7'h77}; + init_data[1044] = {1'b1, 8'h01}; + init_data[1045] = {1'b1, 8'h0b}; // set page 0x0b + init_data[1046] = {2'b01, 7'h77}; + init_data[1047] = {1'b1, 8'h44}; + init_data[1048] = {1'b1, 8'h0f}; // write 0x0f to 0x0b44 + init_data[1049] = {2'b01, 7'h77}; + init_data[1050] = {1'b1, 8'h4a}; + init_data[1051] = {1'b1, 8'h1e}; // write 0x1e to 0x0b4a + init_data[1052] = {2'b01, 7'h77}; + init_data[1053] = {1'b1, 8'h57}; + init_data[1054] = {1'b1, 8'ha0}; // write 0xa0 to 0x0b57 + init_data[1055] = {1'b1, 8'h00}; // write 0x00 to 0x0b58 + // End configuration registers + // + // Start configuration postamble + init_data[1056] = {2'b01, 7'h77}; + init_data[1057] = {1'b1, 8'h01}; + init_data[1058] = {1'b1, 8'h00}; // set page 0x00 + init_data[1059] = {2'b01, 7'h77}; + init_data[1060] = {1'b1, 8'h1c}; + init_data[1061] = {1'b1, 8'h01}; // write 0x01 to 0x001c + init_data[1062] = {2'b01, 7'h77}; + init_data[1063] = {1'b1, 8'h01}; + init_data[1064] = {1'b1, 8'h0b}; // set page 0x0b + init_data[1065] = {2'b01, 7'h77}; + init_data[1066] = {1'b1, 8'h24}; + init_data[1067] = {1'b1, 8'hc3}; // write 0xc3 to 0x0b24 + init_data[1068] = {1'b1, 8'h02}; // write 0x02 to 0x0b25 + // End configuration postamble + init_data[1069] = 9'd0; // end +end + +localparam [3:0] + STATE_IDLE = 3'd0, + STATE_RUN = 3'd1, + STATE_TABLE_1 = 3'd2, + STATE_TABLE_2 = 3'd3, + STATE_TABLE_3 = 3'd4; + +reg [4:0] state_reg = STATE_IDLE, state_next; + +parameter AW = $clog2(INIT_DATA_LEN); + +reg [8:0] init_data_reg = 9'd0; + +reg [AW-1:0] address_reg = {AW{1'b0}}, address_next; +reg [AW-1:0] address_ptr_reg = {AW{1'b0}}, address_ptr_next; +reg [AW-1:0] data_ptr_reg = {AW{1'b0}}, data_ptr_next; + +reg [6:0] cur_address_reg = 7'd0, cur_address_next; + +reg [31:0] delay_counter_reg = 32'd0, delay_counter_next; + +reg [6:0] m_axis_cmd_address_reg = 7'd0, m_axis_cmd_address_next; +reg m_axis_cmd_start_reg = 1'b0, m_axis_cmd_start_next; +reg m_axis_cmd_write_reg = 1'b0, m_axis_cmd_write_next; +reg m_axis_cmd_stop_reg = 1'b0, m_axis_cmd_stop_next; +reg m_axis_cmd_valid_reg = 1'b0, m_axis_cmd_valid_next; + +reg [7:0] m_axis_data_tdata_reg = 8'd0, m_axis_data_tdata_next; +reg m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next; + +reg start_flag_reg = 1'b0, start_flag_next; + +reg busy_reg = 1'b0; + +assign m_axis_cmd_address = m_axis_cmd_address_reg; +assign m_axis_cmd_start = m_axis_cmd_start_reg; +assign m_axis_cmd_read = 1'b0; +assign m_axis_cmd_write = m_axis_cmd_write_reg; +assign m_axis_cmd_write_multiple = 1'b0; +assign m_axis_cmd_stop = m_axis_cmd_stop_reg; +assign m_axis_cmd_valid = m_axis_cmd_valid_reg; + +assign m_axis_data_tdata = m_axis_data_tdata_reg; +assign m_axis_data_tvalid = m_axis_data_tvalid_reg; +assign m_axis_data_tlast = 1'b1; + +assign busy = busy_reg; + +always @* begin + state_next = STATE_IDLE; + + address_next = address_reg; + address_ptr_next = address_ptr_reg; + data_ptr_next = data_ptr_reg; + + cur_address_next = cur_address_reg; + + delay_counter_next = delay_counter_reg; + + m_axis_cmd_address_next = m_axis_cmd_address_reg; + m_axis_cmd_start_next = m_axis_cmd_start_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready); + m_axis_cmd_write_next = m_axis_cmd_write_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready); + m_axis_cmd_stop_next = m_axis_cmd_stop_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready); + m_axis_cmd_valid_next = m_axis_cmd_valid_reg & ~m_axis_cmd_ready; + + m_axis_data_tdata_next = m_axis_data_tdata_reg; + m_axis_data_tvalid_next = m_axis_data_tvalid_reg & ~m_axis_data_tready; + + start_flag_next = start_flag_reg; + + if (m_axis_cmd_valid | m_axis_data_tvalid) begin + // wait for output registers to clear + state_next = state_reg; + end else if (delay_counter_reg != 0) begin + // delay + delay_counter_next = delay_counter_reg - 1; + state_next = state_reg; + end else begin + case (state_reg) + STATE_IDLE: begin + // wait for start signal + if (~start_flag_reg & start) begin + address_next = {AW{1'b0}}; + start_flag_next = 1'b1; + state_next = STATE_RUN; + end else begin + state_next = STATE_IDLE; + end + end + STATE_RUN: begin + // process commands + if (init_data_reg[8] == 1'b1) begin + // write data + m_axis_cmd_write_next = 1'b1; + m_axis_cmd_stop_next = 1'b0; + m_axis_cmd_valid_next = 1'b1; + + m_axis_data_tdata_next = init_data_reg[7:0]; + m_axis_data_tvalid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg[8:7] == 2'b01) begin + // write address + m_axis_cmd_address_next = init_data_reg[6:0]; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg[8:4] == 5'b00001) begin + // delay + delay_counter_next = 32'd1 << (init_data_reg[3:0]+16); + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg == 9'b001000001) begin + // send stop + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_RUN; + end + end + STATE_TABLE_1: begin + // find address table start + if (init_data_reg == 9'b000001000) begin + // address table start + address_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_2; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end + end + STATE_TABLE_2: begin + // find next address + if (init_data_reg[8:7] == 2'b01) begin + // write address command + // store address and move to data table + cur_address_next = init_data_reg[6:0]; + address_ptr_next = address_reg + 1; + address_next = data_ptr_reg; + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'd1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_2; + end + end + STATE_TABLE_3: begin + // process data table with selected address + if (init_data_reg[8] == 1'b1) begin + // write data + m_axis_cmd_write_next = 1'b1; + m_axis_cmd_stop_next = 1'b0; + m_axis_cmd_valid_next = 1'b1; + + m_axis_data_tdata_next = init_data_reg[7:0]; + m_axis_data_tvalid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg[8:7] == 2'b01) begin + // write address + m_axis_cmd_address_next = init_data_reg[6:0]; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000000011) begin + // write current address + m_axis_cmd_address_next = cur_address_reg; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b001000001) begin + // send stop + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'b000001000) begin + // address table start + address_next = address_ptr_reg; + state_next = STATE_TABLE_2; + end else if (init_data_reg == 9'd1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_3; + end + end + endcase + end +end + +always @(posedge clk) begin + state_reg <= state_next; + + // read init_data ROM + init_data_reg <= init_data[address_next]; + + address_reg <= address_next; + address_ptr_reg <= address_ptr_next; + data_ptr_reg <= data_ptr_next; + + cur_address_reg <= cur_address_next; + + delay_counter_reg <= delay_counter_next; + + m_axis_cmd_address_reg <= m_axis_cmd_address_next; + m_axis_cmd_start_reg <= m_axis_cmd_start_next; + m_axis_cmd_write_reg <= m_axis_cmd_write_next; + m_axis_cmd_stop_reg <= m_axis_cmd_stop_next; + m_axis_cmd_valid_reg <= m_axis_cmd_valid_next; + + m_axis_data_tdata_reg <= m_axis_data_tdata_next; + m_axis_data_tvalid_reg <= m_axis_data_tvalid_next; + + start_flag_reg <= start & start_flag_next; + + busy_reg <= (state_reg != STATE_IDLE); + + if (rst) begin + state_reg <= STATE_IDLE; + + init_data_reg <= 9'd0; + + address_reg <= {AW{1'b0}}; + address_ptr_reg <= {AW{1'b0}}; + data_ptr_reg <= {AW{1'b0}}; + + cur_address_reg <= 7'd0; + + delay_counter_reg <= 32'd0; + + m_axis_cmd_valid_reg <= 1'b0; + + m_axis_data_tvalid_reg <= 1'b0; + + start_flag_reg <= 1'b0; + + busy_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/rtl/debounce_switch.v b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/debounce_switch.v similarity index 98% rename from fpga/lib/eth/example/VCU1525/fpga_10g/rtl/debounce_switch.v rename to fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/debounce_switch.v index 8e93a50c4..f63a5a2e9 100644 --- a/fpga/lib/eth/example/VCU1525/fpga_10g/rtl/debounce_switch.v +++ b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/debounce_switch.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2014-2018 Alex Forencich +Copyright (c) 2014-2017 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal diff --git a/fpga/lib/eth/example/HTG9200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v similarity index 100% rename from fpga/lib/eth/example/HTG9200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v rename to fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v diff --git a/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v new file mode 100644 index 000000000..637495b66 --- /dev/null +++ b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v @@ -0,0 +1,4676 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA top-level module + */ +module fpga ( + /* + * Clock: 200 MHz LVDS + */ + input wire ref_clk_p, + input wire ref_clk_n, + + output wire clk_gty2_fdec, + output wire clk_gty2_finc, + input wire clk_gty2_intr_n, + input wire clk_gty2_lol_n, + output wire clk_gty2_oe_n, + output wire clk_gty2_sync_n, + output wire clk_gty2_rst_n, + + /* + * GPIO + */ + input wire [1:0] btn, + input wire [7:0] sw, + output wire [7:0] led, + + /* + * I2C for board management + */ + inout wire i2c_main_scl, + inout wire i2c_main_sda, + output wire i2c_main_rst_n, + + /* + * UART: 115200 bps, 8N1 + */ + output wire uart_rxd, + input wire uart_txd, + input wire uart_rts, + output wire uart_cts, + output wire uart_rst_n, + output wire uart_suspend_n, + + /* + * Ethernet: QSFP28 + */ + output wire [3:0] qsfp_1_tx_p, + output wire [3:0] qsfp_1_tx_n, + input wire [3:0] qsfp_1_rx_p, + input wire [3:0] qsfp_1_rx_n, + input wire qsfp_1_mgt_refclk_p, + input wire qsfp_1_mgt_refclk_n, + output wire qsfp_1_resetl, + input wire qsfp_1_modprsl, + input wire qsfp_1_intl, + + output wire [3:0] qsfp_2_tx_p, + output wire [3:0] qsfp_2_tx_n, + input wire [3:0] qsfp_2_rx_p, + input wire [3:0] qsfp_2_rx_n, + input wire qsfp_2_mgt_refclk_p, + input wire qsfp_2_mgt_refclk_n, + output wire qsfp_2_resetl, + input wire qsfp_2_modprsl, + input wire qsfp_2_intl, + + output wire [3:0] qsfp_3_tx_p, + output wire [3:0] qsfp_3_tx_n, + input wire [3:0] qsfp_3_rx_p, + input wire [3:0] qsfp_3_rx_n, + input wire qsfp_3_mgt_refclk_p, + input wire qsfp_3_mgt_refclk_n, + output wire qsfp_3_resetl, + input wire qsfp_3_modprsl, + input wire qsfp_3_intl, + + output wire [3:0] qsfp_4_tx_p, + output wire [3:0] qsfp_4_tx_n, + input wire [3:0] qsfp_4_rx_p, + input wire [3:0] qsfp_4_rx_n, + input wire qsfp_4_mgt_refclk_p, + input wire qsfp_4_mgt_refclk_n, + output wire qsfp_4_resetl, + input wire qsfp_4_modprsl, + input wire qsfp_4_intl, + + output wire [3:0] qsfp_5_tx_p, + output wire [3:0] qsfp_5_tx_n, + input wire [3:0] qsfp_5_rx_p, + input wire [3:0] qsfp_5_rx_n, + input wire qsfp_5_mgt_refclk_p, + input wire qsfp_5_mgt_refclk_n, + output wire qsfp_5_resetl, + input wire qsfp_5_modprsl, + input wire qsfp_5_intl, + + output wire [3:0] qsfp_6_tx_p, + output wire [3:0] qsfp_6_tx_n, + input wire [3:0] qsfp_6_rx_p, + input wire [3:0] qsfp_6_rx_n, + input wire qsfp_6_mgt_refclk_p, + input wire qsfp_6_mgt_refclk_n, + output wire qsfp_6_resetl, + input wire qsfp_6_modprsl, + input wire qsfp_6_intl, + + output wire [3:0] qsfp_7_tx_p, + output wire [3:0] qsfp_7_tx_n, + input wire [3:0] qsfp_7_rx_p, + input wire [3:0] qsfp_7_rx_n, + input wire qsfp_7_mgt_refclk_p, + input wire qsfp_7_mgt_refclk_n, + output wire qsfp_7_resetl, + input wire qsfp_7_modprsl, + input wire qsfp_7_intl, + + output wire [3:0] qsfp_8_tx_p, + output wire [3:0] qsfp_8_tx_n, + input wire [3:0] qsfp_8_rx_p, + input wire [3:0] qsfp_8_rx_n, + input wire qsfp_8_mgt_refclk_p, + input wire qsfp_8_mgt_refclk_n, + output wire qsfp_8_resetl, + input wire qsfp_8_modprsl, + input wire qsfp_8_intl, + + output wire [3:0] qsfp_9_tx_p, + output wire [3:0] qsfp_9_tx_n, + input wire [3:0] qsfp_9_rx_p, + input wire [3:0] qsfp_9_rx_n, + input wire qsfp_9_mgt_refclk_p, + input wire qsfp_9_mgt_refclk_n, + output wire qsfp_9_resetl, + input wire qsfp_9_modprsl, + input wire qsfp_9_intl, + + /* + * Ethernet: QSFP28 via HTG 6x QSFP28 FMC+ adapter + */ + output wire [3:0] fmc_qsfp_1_tx_p, + output wire [3:0] fmc_qsfp_1_tx_n, + input wire [3:0] fmc_qsfp_1_rx_p, + input wire [3:0] fmc_qsfp_1_rx_n, + input wire fmc_qsfp_1_mgt_refclk_p, + input wire fmc_qsfp_1_mgt_refclk_n, + output wire fmc_qsfp_1_modsell, + output wire fmc_qsfp_1_resetl, + input wire fmc_qsfp_1_modprsl, + input wire fmc_qsfp_1_intl, + output wire fmc_qsfp_1_lpmode, + + output wire [3:0] fmc_qsfp_2_tx_p, + output wire [3:0] fmc_qsfp_2_tx_n, + input wire [3:0] fmc_qsfp_2_rx_p, + input wire [3:0] fmc_qsfp_2_rx_n, + input wire fmc_qsfp_2_mgt_refclk_p, + input wire fmc_qsfp_2_mgt_refclk_n, + output wire fmc_qsfp_2_modsell, + output wire fmc_qsfp_2_resetl, + input wire fmc_qsfp_2_modprsl, + input wire fmc_qsfp_2_intl, + output wire fmc_qsfp_2_lpmode, + + output wire [3:0] fmc_qsfp_3_tx_p, + output wire [3:0] fmc_qsfp_3_tx_n, + input wire [3:0] fmc_qsfp_3_rx_p, + input wire [3:0] fmc_qsfp_3_rx_n, + input wire fmc_qsfp_3_mgt_refclk_p, + input wire fmc_qsfp_3_mgt_refclk_n, + output wire fmc_qsfp_3_modsell, + output wire fmc_qsfp_3_resetl, + input wire fmc_qsfp_3_modprsl, + input wire fmc_qsfp_3_intl, + output wire fmc_qsfp_3_lpmode, + + output wire [3:0] fmc_qsfp_4_tx_p, + output wire [3:0] fmc_qsfp_4_tx_n, + input wire [3:0] fmc_qsfp_4_rx_p, + input wire [3:0] fmc_qsfp_4_rx_n, + input wire fmc_qsfp_4_mgt_refclk_p, + input wire fmc_qsfp_4_mgt_refclk_n, + output wire fmc_qsfp_4_modsell, + output wire fmc_qsfp_4_resetl, + input wire fmc_qsfp_4_modprsl, + input wire fmc_qsfp_4_intl, + output wire fmc_qsfp_4_lpmode, + + output wire [3:0] fmc_qsfp_5_tx_p, + output wire [3:0] fmc_qsfp_5_tx_n, + input wire [3:0] fmc_qsfp_5_rx_p, + input wire [3:0] fmc_qsfp_5_rx_n, + input wire fmc_qsfp_5_mgt_refclk_p, + input wire fmc_qsfp_5_mgt_refclk_n, + output wire fmc_qsfp_5_modsell, + output wire fmc_qsfp_5_resetl, + input wire fmc_qsfp_5_modprsl, + input wire fmc_qsfp_5_intl, + output wire fmc_qsfp_5_lpmode, + + output wire [3:0] fmc_qsfp_6_tx_p, + output wire [3:0] fmc_qsfp_6_tx_n, + input wire [3:0] fmc_qsfp_6_rx_p, + input wire [3:0] fmc_qsfp_6_rx_n, + input wire fmc_qsfp_6_mgt_refclk_p, + input wire fmc_qsfp_6_mgt_refclk_n, + output wire fmc_qsfp_6_modsell, + output wire fmc_qsfp_6_resetl, + input wire fmc_qsfp_6_modprsl, + input wire fmc_qsfp_6_intl, + output wire fmc_qsfp_6_lpmode, + + output wire fmc_clk_finc, + output wire fmc_clk_fdec, + output wire fmc_clk_rst_n, + input wire fmc_clk_lol_n, + output wire fmc_clk_sync_n, + input wire fmc_clk_intr_n, + + output wire fmc_sync_c2m_p, + output wire fmc_sync_c2m_n +); + +// Clock and reset + +wire ref_clk_ibufg; + +// Internal 125 MHz clock +wire clk_125mhz_mmcm_out; +wire clk_125mhz_int; +wire rst_125mhz_int; + +// Internal 156.25 MHz clock +wire clk_156mhz_int; +wire rst_156mhz_int; + +wire mmcm_rst = ~btn[0]; +wire mmcm_locked; +wire mmcm_clkfb; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +ref_clk_ibufg_inst ( + .O (ref_clk_ibufg), + .I (ref_clk_p), + .IB (ref_clk_n) +); + +// MMCM instance +// 200 MHz in, 125 MHz out +// PFD range: 10 MHz to 500 MHz +// VCO range: 800 MHz to 1600 MHz +// M = 5, D = 1 sets Fvco = 1000 MHz (in range) +// Divide by 8 to get output frequency of 125 MHz +MMCME4_BASE #( + .BANDWIDTH("OPTIMIZED"), + .CLKOUT0_DIVIDE_F(8), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + .CLKFBOUT_MULT_F(5), + .CLKFBOUT_PHASE(0), + .DIVCLK_DIVIDE(1), + .REF_JITTER1(0.010), + .CLKIN1_PERIOD(5.0), + .STARTUP_WAIT("FALSE"), + .CLKOUT4_CASCADE("FALSE") +) +clk_mmcm_inst ( + .CLKIN1(ref_clk_ibufg), + .CLKFBIN(mmcm_clkfb), + .RST(mmcm_rst), + .PWRDWN(1'b0), + .CLKOUT0(clk_125mhz_mmcm_out), + .CLKOUT0B(), + .CLKOUT1(), + .CLKOUT1B(), + .CLKOUT2(), + .CLKOUT2B(), + .CLKOUT3(), + .CLKOUT3B(), + .CLKOUT4(), + .CLKOUT5(), + .CLKOUT6(), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + .LOCKED(mmcm_locked) +); + +BUFG +clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int) +); + +sync_reset #( + .N(4) +) +sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .out(rst_125mhz_int) +); + +// GPIO +wire btn_int; +wire [7:0] sw_int; + +debounce_switch #( + .WIDTH(9), + .N(4), + .RATE(125000) +) +debounce_switch_inst ( + .clk(clk_125mhz_int), + .rst(rst_125mhz_int), + .in({btn[1], + sw}), + .out({btn_int, + sw_int}) +); + +wire uart_txd_int; +wire uart_rts_int; + +sync_signal #( + .WIDTH(2), + .N(2) +) +sync_signal_inst ( + .clk(clk_125mhz_int), + .in({uart_txd, uart_rts}), + .out({uart_txd_int, uart_rts_int}) +); + +wire i2c_scl_i; +wire i2c_scl_o; +wire i2c_scl_t; +wire i2c_sda_i; +wire i2c_sda_o; +wire i2c_sda_t; + +assign i2c_scl_i = i2c_main_scl; +assign i2c_main_scl = i2c_scl_t ? 1'bz : i2c_scl_o; +assign i2c_sda_i = i2c_main_sda; +assign i2c_main_sda = i2c_sda_t ? 1'bz : i2c_sda_o; +assign i2c_main_rst_n = 1'b1; + +// Si5341 init +wire [6:0] si5341_i2c_cmd_address; +wire si5341_i2c_cmd_start; +wire si5341_i2c_cmd_read; +wire si5341_i2c_cmd_write; +wire si5341_i2c_cmd_write_multiple; +wire si5341_i2c_cmd_stop; +wire si5341_i2c_cmd_valid; +wire si5341_i2c_cmd_ready; + +wire [7:0] si5341_i2c_data_tdata; +wire si5341_i2c_data_tvalid; +wire si5341_i2c_data_tready; +wire si5341_i2c_data_tlast; + +wire si5341_i2c_busy; + +i2c_master +si5341_i2c_master_inst ( + .clk(clk_125mhz_int), + .rst(rst_125mhz_int), + .s_axis_cmd_address(si5341_i2c_cmd_address), + .s_axis_cmd_start(si5341_i2c_cmd_start), + .s_axis_cmd_read(si5341_i2c_cmd_read), + .s_axis_cmd_write(si5341_i2c_cmd_write), + .s_axis_cmd_write_multiple(si5341_i2c_cmd_write_multiple), + .s_axis_cmd_stop(si5341_i2c_cmd_stop), + .s_axis_cmd_valid(si5341_i2c_cmd_valid), + .s_axis_cmd_ready(si5341_i2c_cmd_ready), + .s_axis_data_tdata(si5341_i2c_data_tdata), + .s_axis_data_tvalid(si5341_i2c_data_tvalid), + .s_axis_data_tready(si5341_i2c_data_tready), + .s_axis_data_tlast(si5341_i2c_data_tlast), + .m_axis_data_tdata(), + .m_axis_data_tvalid(), + .m_axis_data_tready(1'b1), + .m_axis_data_tlast(), + .scl_i(i2c_scl_i), + .scl_o(i2c_scl_o), + .scl_t(i2c_scl_t), + .sda_i(i2c_sda_i), + .sda_o(i2c_sda_o), + .sda_t(i2c_sda_t), + .busy(), + .bus_control(), + .bus_active(), + .missed_ack(), + .prescale(312), + .stop_on_idle(1) +); + +si5341_i2c_init +si5341_i2c_init_inst ( + .clk(clk_125mhz_int), + .rst(rst_125mhz_int), + .m_axis_cmd_address(si5341_i2c_cmd_address), + .m_axis_cmd_start(si5341_i2c_cmd_start), + .m_axis_cmd_read(si5341_i2c_cmd_read), + .m_axis_cmd_write(si5341_i2c_cmd_write), + .m_axis_cmd_write_multiple(si5341_i2c_cmd_write_multiple), + .m_axis_cmd_stop(si5341_i2c_cmd_stop), + .m_axis_cmd_valid(si5341_i2c_cmd_valid), + .m_axis_cmd_ready(si5341_i2c_cmd_ready), + .m_axis_data_tdata(si5341_i2c_data_tdata), + .m_axis_data_tvalid(si5341_i2c_data_tvalid), + .m_axis_data_tready(si5341_i2c_data_tready), + .m_axis_data_tlast(si5341_i2c_data_tlast), + .busy(si5341_i2c_busy), + .start(1'b1) +); + +assign clk_gty2_fdec = 1'b0; +assign clk_gty2_finc = 1'b0; +assign clk_gty2_oe_n = 1'b0; +assign clk_gty2_sync_n = 1'b1; +assign clk_gty2_rst_n = btn[0]; + +assign fmc_clk_finc = 1'b0; +assign fmc_clk_fdec = 1'b0; +assign fmc_clk_rst_n = btn[0]; +assign fmc_clk_sync_n = 1'b1; + +// XGMII 10G PHY +wire qsfp_reset = rst_125mhz_int || si5341_i2c_busy || !clk_gty2_lol_n; +wire fmc_qsfp_reset = rst_125mhz_int || si5341_i2c_busy || !fmc_clk_lol_n; + +// QSFP 1 +assign qsfp_1_resetl = 1'b1; + +wire qsfp_1_tx_clk_1_int; +wire qsfp_1_tx_rst_1_int; +wire [63:0] qsfp_1_txd_1_int; +wire [7:0] qsfp_1_txc_1_int; +wire qsfp_1_rx_clk_1_int; +wire qsfp_1_rx_rst_1_int; +wire [63:0] qsfp_1_rxd_1_int; +wire [7:0] qsfp_1_rxc_1_int; +wire qsfp_1_tx_clk_2_int; +wire qsfp_1_tx_rst_2_int; +wire [63:0] qsfp_1_txd_2_int; +wire [7:0] qsfp_1_txc_2_int; +wire qsfp_1_rx_clk_2_int; +wire qsfp_1_rx_rst_2_int; +wire [63:0] qsfp_1_rxd_2_int; +wire [7:0] qsfp_1_rxc_2_int; +wire qsfp_1_tx_clk_3_int; +wire qsfp_1_tx_rst_3_int; +wire [63:0] qsfp_1_txd_3_int; +wire [7:0] qsfp_1_txc_3_int; +wire qsfp_1_rx_clk_3_int; +wire qsfp_1_rx_rst_3_int; +wire [63:0] qsfp_1_rxd_3_int; +wire [7:0] qsfp_1_rxc_3_int; +wire qsfp_1_tx_clk_4_int; +wire qsfp_1_tx_rst_4_int; +wire [63:0] qsfp_1_txd_4_int; +wire [7:0] qsfp_1_txc_4_int; +wire qsfp_1_rx_clk_4_int; +wire qsfp_1_rx_rst_4_int; +wire [63:0] qsfp_1_rxd_4_int; +wire [7:0] qsfp_1_rxc_4_int; + +assign clk_156mhz_int = qsfp_1_tx_clk_1_int; +assign rst_156mhz_int = qsfp_1_tx_rst_1_int; + +wire qsfp_1_rx_block_lock_1; +wire qsfp_1_rx_block_lock_2; +wire qsfp_1_rx_block_lock_3; +wire qsfp_1_rx_block_lock_4; + +wire qsfp_1_gtpowergood; + +wire qsfp_1_mgt_refclk; +wire qsfp_1_mgt_refclk_int; +wire qsfp_1_mgt_refclk_bufg; + +IBUFDS_GTE4 ibufds_gte4_qsfp_1_mgt_refclk_inst ( + .I (qsfp_1_mgt_refclk_p), + .IB (qsfp_1_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_1_mgt_refclk), + .ODIV2 (qsfp_1_mgt_refclk_int) +); + +BUFG_GT bufg_gt_qsfp_1_mgt_refclk_inst ( + .CE (qsfp_1_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (qsfp_1_mgt_refclk_int), + .O (qsfp_1_mgt_refclk_bufg) +); + +// forward MGT ref clock to PLL on FMC+ board +OBUFDS obufds_fmc_refclk_inst ( + .I(qsfp_1_mgt_refclk_bufg), + .O(fmc_sync_c2m_p), + .OB(fmc_sync_c2m_n) +); + +wire qsfp_1_qpll0lock; +wire qsfp_1_qpll0outclk; +wire qsfp_1_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +qsfp_1_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(qsfp_1_gtpowergood), + + // PLL out + .xcvr_gtrefclk00_in(qsfp_1_mgt_refclk), + .xcvr_qpll0lock_out(qsfp_1_qpll0lock), + .xcvr_qpll0outclk_out(qsfp_1_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp_1_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp_1_tx_p[0]), + .xcvr_txn(qsfp_1_tx_n[0]), + .xcvr_rxp(qsfp_1_rx_p[0]), + .xcvr_rxn(qsfp_1_rx_n[0]), + + // PHY connections + .phy_tx_clk(qsfp_1_tx_clk_1_int), + .phy_tx_rst(qsfp_1_tx_rst_1_int), + .phy_xgmii_txd(qsfp_1_txd_1_int), + .phy_xgmii_txc(qsfp_1_txc_1_int), + .phy_rx_clk(qsfp_1_rx_clk_1_int), + .phy_rx_rst(qsfp_1_rx_rst_1_int), + .phy_xgmii_rxd(qsfp_1_rxd_1_int), + .phy_xgmii_rxc(qsfp_1_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_1_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_1_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_1_tx_p[1]), + .xcvr_txn(qsfp_1_tx_n[1]), + .xcvr_rxp(qsfp_1_rx_p[1]), + .xcvr_rxn(qsfp_1_rx_n[1]), + + // PHY connections + .phy_tx_clk(qsfp_1_tx_clk_2_int), + .phy_tx_rst(qsfp_1_tx_rst_2_int), + .phy_xgmii_txd(qsfp_1_txd_2_int), + .phy_xgmii_txc(qsfp_1_txc_2_int), + .phy_rx_clk(qsfp_1_rx_clk_2_int), + .phy_rx_rst(qsfp_1_rx_rst_2_int), + .phy_xgmii_rxd(qsfp_1_rxd_2_int), + .phy_xgmii_rxc(qsfp_1_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_1_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_1_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_1_tx_p[2]), + .xcvr_txn(qsfp_1_tx_n[2]), + .xcvr_rxp(qsfp_1_rx_p[2]), + .xcvr_rxn(qsfp_1_rx_n[2]), + + // PHY connections + .phy_tx_clk(qsfp_1_tx_clk_3_int), + .phy_tx_rst(qsfp_1_tx_rst_3_int), + .phy_xgmii_txd(qsfp_1_txd_3_int), + .phy_xgmii_txc(qsfp_1_txc_3_int), + .phy_rx_clk(qsfp_1_rx_clk_3_int), + .phy_rx_rst(qsfp_1_rx_rst_3_int), + .phy_xgmii_rxd(qsfp_1_rxd_3_int), + .phy_xgmii_rxc(qsfp_1_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_1_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_1_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_1_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_1_tx_p[3]), + .xcvr_txn(qsfp_1_tx_n[3]), + .xcvr_rxp(qsfp_1_rx_p[3]), + .xcvr_rxn(qsfp_1_rx_n[3]), + + // PHY connections + .phy_tx_clk(qsfp_1_tx_clk_4_int), + .phy_tx_rst(qsfp_1_tx_rst_4_int), + .phy_xgmii_txd(qsfp_1_txd_4_int), + .phy_xgmii_txc(qsfp_1_txc_4_int), + .phy_rx_clk(qsfp_1_rx_clk_4_int), + .phy_rx_rst(qsfp_1_rx_rst_4_int), + .phy_xgmii_rxd(qsfp_1_rxd_4_int), + .phy_xgmii_rxc(qsfp_1_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_1_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// QSFP 2 +assign qsfp_2_resetl = 1'b1; + +wire qsfp_2_tx_clk_1_int; +wire qsfp_2_tx_rst_1_int; +wire [63:0] qsfp_2_txd_1_int; +wire [7:0] qsfp_2_txc_1_int; +wire qsfp_2_rx_clk_1_int; +wire qsfp_2_rx_rst_1_int; +wire [63:0] qsfp_2_rxd_1_int; +wire [7:0] qsfp_2_rxc_1_int; +wire qsfp_2_tx_clk_2_int; +wire qsfp_2_tx_rst_2_int; +wire [63:0] qsfp_2_txd_2_int; +wire [7:0] qsfp_2_txc_2_int; +wire qsfp_2_rx_clk_2_int; +wire qsfp_2_rx_rst_2_int; +wire [63:0] qsfp_2_rxd_2_int; +wire [7:0] qsfp_2_rxc_2_int; +wire qsfp_2_tx_clk_3_int; +wire qsfp_2_tx_rst_3_int; +wire [63:0] qsfp_2_txd_3_int; +wire [7:0] qsfp_2_txc_3_int; +wire qsfp_2_rx_clk_3_int; +wire qsfp_2_rx_rst_3_int; +wire [63:0] qsfp_2_rxd_3_int; +wire [7:0] qsfp_2_rxc_3_int; +wire qsfp_2_tx_clk_4_int; +wire qsfp_2_tx_rst_4_int; +wire [63:0] qsfp_2_txd_4_int; +wire [7:0] qsfp_2_txc_4_int; +wire qsfp_2_rx_clk_4_int; +wire qsfp_2_rx_rst_4_int; +wire [63:0] qsfp_2_rxd_4_int; +wire [7:0] qsfp_2_rxc_4_int; + +wire qsfp_2_rx_block_lock_1; +wire qsfp_2_rx_block_lock_2; +wire qsfp_2_rx_block_lock_3; +wire qsfp_2_rx_block_lock_4; + +wire qsfp_2_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_qsfp_2_mgt_refclk_inst ( + .I (qsfp_2_mgt_refclk_p), + .IB (qsfp_2_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_2_mgt_refclk), + .ODIV2 () +); + +wire qsfp_2_qpll0lock; +wire qsfp_2_qpll0outclk; +wire qsfp_2_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +qsfp_2_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(qsfp_2_mgt_refclk), + .xcvr_qpll0lock_out(qsfp_2_qpll0lock), + .xcvr_qpll0outclk_out(qsfp_2_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp_2_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp_2_tx_p[0]), + .xcvr_txn(qsfp_2_tx_n[0]), + .xcvr_rxp(qsfp_2_rx_p[0]), + .xcvr_rxn(qsfp_2_rx_n[0]), + + // PHY connections + .phy_tx_clk(qsfp_2_tx_clk_1_int), + .phy_tx_rst(qsfp_2_tx_rst_1_int), + .phy_xgmii_txd(qsfp_2_txd_1_int), + .phy_xgmii_txc(qsfp_2_txc_1_int), + .phy_rx_clk(qsfp_2_rx_clk_1_int), + .phy_rx_rst(qsfp_2_rx_rst_1_int), + .phy_xgmii_rxd(qsfp_2_rxd_1_int), + .phy_xgmii_rxc(qsfp_2_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_2_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_2_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_2_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_2_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_2_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_2_tx_p[1]), + .xcvr_txn(qsfp_2_tx_n[1]), + .xcvr_rxp(qsfp_2_rx_p[1]), + .xcvr_rxn(qsfp_2_rx_n[1]), + + // PHY connections + .phy_tx_clk(qsfp_2_tx_clk_2_int), + .phy_tx_rst(qsfp_2_tx_rst_2_int), + .phy_xgmii_txd(qsfp_2_txd_2_int), + .phy_xgmii_txc(qsfp_2_txc_2_int), + .phy_rx_clk(qsfp_2_rx_clk_2_int), + .phy_rx_rst(qsfp_2_rx_rst_2_int), + .phy_xgmii_rxd(qsfp_2_rxd_2_int), + .phy_xgmii_rxc(qsfp_2_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_2_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_2_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_2_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_2_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_2_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_2_tx_p[2]), + .xcvr_txn(qsfp_2_tx_n[2]), + .xcvr_rxp(qsfp_2_rx_p[2]), + .xcvr_rxn(qsfp_2_rx_n[2]), + + // PHY connections + .phy_tx_clk(qsfp_2_tx_clk_3_int), + .phy_tx_rst(qsfp_2_tx_rst_3_int), + .phy_xgmii_txd(qsfp_2_txd_3_int), + .phy_xgmii_txc(qsfp_2_txc_3_int), + .phy_rx_clk(qsfp_2_rx_clk_3_int), + .phy_rx_rst(qsfp_2_rx_rst_3_int), + .phy_xgmii_rxd(qsfp_2_rxd_3_int), + .phy_xgmii_rxc(qsfp_2_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_2_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_2_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_2_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_2_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_2_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_2_tx_p[3]), + .xcvr_txn(qsfp_2_tx_n[3]), + .xcvr_rxp(qsfp_2_rx_p[3]), + .xcvr_rxn(qsfp_2_rx_n[3]), + + // PHY connections + .phy_tx_clk(qsfp_2_tx_clk_4_int), + .phy_tx_rst(qsfp_2_tx_rst_4_int), + .phy_xgmii_txd(qsfp_2_txd_4_int), + .phy_xgmii_txc(qsfp_2_txc_4_int), + .phy_rx_clk(qsfp_2_rx_clk_4_int), + .phy_rx_rst(qsfp_2_rx_rst_4_int), + .phy_xgmii_rxd(qsfp_2_rxd_4_int), + .phy_xgmii_rxc(qsfp_2_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_2_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// QSFP 3 +assign qsfp_3_resetl = 1'b1; + +wire qsfp_3_tx_clk_1_int; +wire qsfp_3_tx_rst_1_int; +wire [63:0] qsfp_3_txd_1_int; +wire [7:0] qsfp_3_txc_1_int; +wire qsfp_3_rx_clk_1_int; +wire qsfp_3_rx_rst_1_int; +wire [63:0] qsfp_3_rxd_1_int; +wire [7:0] qsfp_3_rxc_1_int; +wire qsfp_3_tx_clk_2_int; +wire qsfp_3_tx_rst_2_int; +wire [63:0] qsfp_3_txd_2_int; +wire [7:0] qsfp_3_txc_2_int; +wire qsfp_3_rx_clk_2_int; +wire qsfp_3_rx_rst_2_int; +wire [63:0] qsfp_3_rxd_2_int; +wire [7:0] qsfp_3_rxc_2_int; +wire qsfp_3_tx_clk_3_int; +wire qsfp_3_tx_rst_3_int; +wire [63:0] qsfp_3_txd_3_int; +wire [7:0] qsfp_3_txc_3_int; +wire qsfp_3_rx_clk_3_int; +wire qsfp_3_rx_rst_3_int; +wire [63:0] qsfp_3_rxd_3_int; +wire [7:0] qsfp_3_rxc_3_int; +wire qsfp_3_tx_clk_4_int; +wire qsfp_3_tx_rst_4_int; +wire [63:0] qsfp_3_txd_4_int; +wire [7:0] qsfp_3_txc_4_int; +wire qsfp_3_rx_clk_4_int; +wire qsfp_3_rx_rst_4_int; +wire [63:0] qsfp_3_rxd_4_int; +wire [7:0] qsfp_3_rxc_4_int; + +wire qsfp_3_rx_block_lock_1; +wire qsfp_3_rx_block_lock_2; +wire qsfp_3_rx_block_lock_3; +wire qsfp_3_rx_block_lock_4; + +wire qsfp_3_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_qsfp_3_mgt_refclk_inst ( + .I (qsfp_3_mgt_refclk_p), + .IB (qsfp_3_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_3_mgt_refclk), + .ODIV2 () +); + +wire qsfp_3_qpll0lock; +wire qsfp_3_qpll0outclk; +wire qsfp_3_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +qsfp_3_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(qsfp_3_mgt_refclk), + .xcvr_qpll0lock_out(qsfp_3_qpll0lock), + .xcvr_qpll0outclk_out(qsfp_3_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp_3_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp_3_tx_p[0]), + .xcvr_txn(qsfp_3_tx_n[0]), + .xcvr_rxp(qsfp_3_rx_p[0]), + .xcvr_rxn(qsfp_3_rx_n[0]), + + // PHY connections + .phy_tx_clk(qsfp_3_tx_clk_1_int), + .phy_tx_rst(qsfp_3_tx_rst_1_int), + .phy_xgmii_txd(qsfp_3_txd_1_int), + .phy_xgmii_txc(qsfp_3_txc_1_int), + .phy_rx_clk(qsfp_3_rx_clk_1_int), + .phy_rx_rst(qsfp_3_rx_rst_1_int), + .phy_xgmii_rxd(qsfp_3_rxd_1_int), + .phy_xgmii_rxc(qsfp_3_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_3_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_3_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_3_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_3_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_3_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_3_tx_p[1]), + .xcvr_txn(qsfp_3_tx_n[1]), + .xcvr_rxp(qsfp_3_rx_p[1]), + .xcvr_rxn(qsfp_3_rx_n[1]), + + // PHY connections + .phy_tx_clk(qsfp_3_tx_clk_2_int), + .phy_tx_rst(qsfp_3_tx_rst_2_int), + .phy_xgmii_txd(qsfp_3_txd_2_int), + .phy_xgmii_txc(qsfp_3_txc_2_int), + .phy_rx_clk(qsfp_3_rx_clk_2_int), + .phy_rx_rst(qsfp_3_rx_rst_2_int), + .phy_xgmii_rxd(qsfp_3_rxd_2_int), + .phy_xgmii_rxc(qsfp_3_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_3_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_3_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_3_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_3_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_3_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_3_tx_p[2]), + .xcvr_txn(qsfp_3_tx_n[2]), + .xcvr_rxp(qsfp_3_rx_p[2]), + .xcvr_rxn(qsfp_3_rx_n[2]), + + // PHY connections + .phy_tx_clk(qsfp_3_tx_clk_3_int), + .phy_tx_rst(qsfp_3_tx_rst_3_int), + .phy_xgmii_txd(qsfp_3_txd_3_int), + .phy_xgmii_txc(qsfp_3_txc_3_int), + .phy_rx_clk(qsfp_3_rx_clk_3_int), + .phy_rx_rst(qsfp_3_rx_rst_3_int), + .phy_xgmii_rxd(qsfp_3_rxd_3_int), + .phy_xgmii_rxc(qsfp_3_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_3_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_3_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_3_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_3_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_3_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_3_tx_p[3]), + .xcvr_txn(qsfp_3_tx_n[3]), + .xcvr_rxp(qsfp_3_rx_p[3]), + .xcvr_rxn(qsfp_3_rx_n[3]), + + // PHY connections + .phy_tx_clk(qsfp_3_tx_clk_4_int), + .phy_tx_rst(qsfp_3_tx_rst_4_int), + .phy_xgmii_txd(qsfp_3_txd_4_int), + .phy_xgmii_txc(qsfp_3_txc_4_int), + .phy_rx_clk(qsfp_3_rx_clk_4_int), + .phy_rx_rst(qsfp_3_rx_rst_4_int), + .phy_xgmii_rxd(qsfp_3_rxd_4_int), + .phy_xgmii_rxc(qsfp_3_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_3_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// QSFP 4 +assign qsfp_4_resetl = 1'b1; + +wire qsfp_4_tx_clk_1_int; +wire qsfp_4_tx_rst_1_int; +wire [63:0] qsfp_4_txd_1_int; +wire [7:0] qsfp_4_txc_1_int; +wire qsfp_4_rx_clk_1_int; +wire qsfp_4_rx_rst_1_int; +wire [63:0] qsfp_4_rxd_1_int; +wire [7:0] qsfp_4_rxc_1_int; +wire qsfp_4_tx_clk_2_int; +wire qsfp_4_tx_rst_2_int; +wire [63:0] qsfp_4_txd_2_int; +wire [7:0] qsfp_4_txc_2_int; +wire qsfp_4_rx_clk_2_int; +wire qsfp_4_rx_rst_2_int; +wire [63:0] qsfp_4_rxd_2_int; +wire [7:0] qsfp_4_rxc_2_int; +wire qsfp_4_tx_clk_3_int; +wire qsfp_4_tx_rst_3_int; +wire [63:0] qsfp_4_txd_3_int; +wire [7:0] qsfp_4_txc_3_int; +wire qsfp_4_rx_clk_3_int; +wire qsfp_4_rx_rst_3_int; +wire [63:0] qsfp_4_rxd_3_int; +wire [7:0] qsfp_4_rxc_3_int; +wire qsfp_4_tx_clk_4_int; +wire qsfp_4_tx_rst_4_int; +wire [63:0] qsfp_4_txd_4_int; +wire [7:0] qsfp_4_txc_4_int; +wire qsfp_4_rx_clk_4_int; +wire qsfp_4_rx_rst_4_int; +wire [63:0] qsfp_4_rxd_4_int; +wire [7:0] qsfp_4_rxc_4_int; + +wire qsfp_4_rx_block_lock_1; +wire qsfp_4_rx_block_lock_2; +wire qsfp_4_rx_block_lock_3; +wire qsfp_4_rx_block_lock_4; + +wire qsfp_4_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_qsfp_4_mgt_refclk_inst ( + .I (qsfp_4_mgt_refclk_p), + .IB (qsfp_4_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_4_mgt_refclk), + .ODIV2 () +); + +wire qsfp_4_qpll0lock; +wire qsfp_4_qpll0outclk; +wire qsfp_4_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +qsfp_4_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(qsfp_4_mgt_refclk), + .xcvr_qpll0lock_out(qsfp_4_qpll0lock), + .xcvr_qpll0outclk_out(qsfp_4_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp_4_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp_4_tx_p[0]), + .xcvr_txn(qsfp_4_tx_n[0]), + .xcvr_rxp(qsfp_4_rx_p[0]), + .xcvr_rxn(qsfp_4_rx_n[0]), + + // PHY connections + .phy_tx_clk(qsfp_4_tx_clk_1_int), + .phy_tx_rst(qsfp_4_tx_rst_1_int), + .phy_xgmii_txd(qsfp_4_txd_1_int), + .phy_xgmii_txc(qsfp_4_txc_1_int), + .phy_rx_clk(qsfp_4_rx_clk_1_int), + .phy_rx_rst(qsfp_4_rx_rst_1_int), + .phy_xgmii_rxd(qsfp_4_rxd_1_int), + .phy_xgmii_rxc(qsfp_4_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_4_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_4_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_4_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_4_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_4_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_4_tx_p[1]), + .xcvr_txn(qsfp_4_tx_n[1]), + .xcvr_rxp(qsfp_4_rx_p[1]), + .xcvr_rxn(qsfp_4_rx_n[1]), + + // PHY connections + .phy_tx_clk(qsfp_4_tx_clk_2_int), + .phy_tx_rst(qsfp_4_tx_rst_2_int), + .phy_xgmii_txd(qsfp_4_txd_2_int), + .phy_xgmii_txc(qsfp_4_txc_2_int), + .phy_rx_clk(qsfp_4_rx_clk_2_int), + .phy_rx_rst(qsfp_4_rx_rst_2_int), + .phy_xgmii_rxd(qsfp_4_rxd_2_int), + .phy_xgmii_rxc(qsfp_4_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_4_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_4_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_4_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_4_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_4_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_4_tx_p[2]), + .xcvr_txn(qsfp_4_tx_n[2]), + .xcvr_rxp(qsfp_4_rx_p[2]), + .xcvr_rxn(qsfp_4_rx_n[2]), + + // PHY connections + .phy_tx_clk(qsfp_4_tx_clk_3_int), + .phy_tx_rst(qsfp_4_tx_rst_3_int), + .phy_xgmii_txd(qsfp_4_txd_3_int), + .phy_xgmii_txc(qsfp_4_txc_3_int), + .phy_rx_clk(qsfp_4_rx_clk_3_int), + .phy_rx_rst(qsfp_4_rx_rst_3_int), + .phy_xgmii_rxd(qsfp_4_rxd_3_int), + .phy_xgmii_rxc(qsfp_4_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_4_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_4_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_4_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_4_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_4_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_4_tx_p[3]), + .xcvr_txn(qsfp_4_tx_n[3]), + .xcvr_rxp(qsfp_4_rx_p[3]), + .xcvr_rxn(qsfp_4_rx_n[3]), + + // PHY connections + .phy_tx_clk(qsfp_4_tx_clk_4_int), + .phy_tx_rst(qsfp_4_tx_rst_4_int), + .phy_xgmii_txd(qsfp_4_txd_4_int), + .phy_xgmii_txc(qsfp_4_txc_4_int), + .phy_rx_clk(qsfp_4_rx_clk_4_int), + .phy_rx_rst(qsfp_4_rx_rst_4_int), + .phy_xgmii_rxd(qsfp_4_rxd_4_int), + .phy_xgmii_rxc(qsfp_4_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_4_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// QSFP 5 +assign qsfp_5_resetl = 1'b1; + +wire qsfp_5_tx_clk_1_int; +wire qsfp_5_tx_rst_1_int; +wire [63:0] qsfp_5_txd_1_int; +wire [7:0] qsfp_5_txc_1_int; +wire qsfp_5_rx_clk_1_int; +wire qsfp_5_rx_rst_1_int; +wire [63:0] qsfp_5_rxd_1_int; +wire [7:0] qsfp_5_rxc_1_int; +wire qsfp_5_tx_clk_2_int; +wire qsfp_5_tx_rst_2_int; +wire [63:0] qsfp_5_txd_2_int; +wire [7:0] qsfp_5_txc_2_int; +wire qsfp_5_rx_clk_2_int; +wire qsfp_5_rx_rst_2_int; +wire [63:0] qsfp_5_rxd_2_int; +wire [7:0] qsfp_5_rxc_2_int; +wire qsfp_5_tx_clk_3_int; +wire qsfp_5_tx_rst_3_int; +wire [63:0] qsfp_5_txd_3_int; +wire [7:0] qsfp_5_txc_3_int; +wire qsfp_5_rx_clk_3_int; +wire qsfp_5_rx_rst_3_int; +wire [63:0] qsfp_5_rxd_3_int; +wire [7:0] qsfp_5_rxc_3_int; +wire qsfp_5_tx_clk_4_int; +wire qsfp_5_tx_rst_4_int; +wire [63:0] qsfp_5_txd_4_int; +wire [7:0] qsfp_5_txc_4_int; +wire qsfp_5_rx_clk_4_int; +wire qsfp_5_rx_rst_4_int; +wire [63:0] qsfp_5_rxd_4_int; +wire [7:0] qsfp_5_rxc_4_int; + +wire qsfp_5_rx_block_lock_1; +wire qsfp_5_rx_block_lock_2; +wire qsfp_5_rx_block_lock_3; +wire qsfp_5_rx_block_lock_4; + +wire qsfp_5_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_qsfp_5_mgt_refclk_inst ( + .I (qsfp_5_mgt_refclk_p), + .IB (qsfp_5_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_5_mgt_refclk), + .ODIV2 () +); + +wire qsfp_5_qpll0lock; +wire qsfp_5_qpll0outclk; +wire qsfp_5_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +qsfp_5_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(qsfp_5_mgt_refclk), + .xcvr_qpll0lock_out(qsfp_5_qpll0lock), + .xcvr_qpll0outclk_out(qsfp_5_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp_5_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp_5_tx_p[0]), + .xcvr_txn(qsfp_5_tx_n[0]), + .xcvr_rxp(qsfp_5_rx_p[0]), + .xcvr_rxn(qsfp_5_rx_n[0]), + + // PHY connections + .phy_tx_clk(qsfp_5_tx_clk_1_int), + .phy_tx_rst(qsfp_5_tx_rst_1_int), + .phy_xgmii_txd(qsfp_5_txd_1_int), + .phy_xgmii_txc(qsfp_5_txc_1_int), + .phy_rx_clk(qsfp_5_rx_clk_1_int), + .phy_rx_rst(qsfp_5_rx_rst_1_int), + .phy_xgmii_rxd(qsfp_5_rxd_1_int), + .phy_xgmii_rxc(qsfp_5_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_5_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_5_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_5_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_5_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_5_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_5_tx_p[1]), + .xcvr_txn(qsfp_5_tx_n[1]), + .xcvr_rxp(qsfp_5_rx_p[1]), + .xcvr_rxn(qsfp_5_rx_n[1]), + + // PHY connections + .phy_tx_clk(qsfp_5_tx_clk_2_int), + .phy_tx_rst(qsfp_5_tx_rst_2_int), + .phy_xgmii_txd(qsfp_5_txd_2_int), + .phy_xgmii_txc(qsfp_5_txc_2_int), + .phy_rx_clk(qsfp_5_rx_clk_2_int), + .phy_rx_rst(qsfp_5_rx_rst_2_int), + .phy_xgmii_rxd(qsfp_5_rxd_2_int), + .phy_xgmii_rxc(qsfp_5_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_5_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_5_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_5_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_5_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_5_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_5_tx_p[2]), + .xcvr_txn(qsfp_5_tx_n[2]), + .xcvr_rxp(qsfp_5_rx_p[2]), + .xcvr_rxn(qsfp_5_rx_n[2]), + + // PHY connections + .phy_tx_clk(qsfp_5_tx_clk_3_int), + .phy_tx_rst(qsfp_5_tx_rst_3_int), + .phy_xgmii_txd(qsfp_5_txd_3_int), + .phy_xgmii_txc(qsfp_5_txc_3_int), + .phy_rx_clk(qsfp_5_rx_clk_3_int), + .phy_rx_rst(qsfp_5_rx_rst_3_int), + .phy_xgmii_rxd(qsfp_5_rxd_3_int), + .phy_xgmii_rxc(qsfp_5_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_5_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_5_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_5_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_5_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_5_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_5_tx_p[3]), + .xcvr_txn(qsfp_5_tx_n[3]), + .xcvr_rxp(qsfp_5_rx_p[3]), + .xcvr_rxn(qsfp_5_rx_n[3]), + + // PHY connections + .phy_tx_clk(qsfp_5_tx_clk_4_int), + .phy_tx_rst(qsfp_5_tx_rst_4_int), + .phy_xgmii_txd(qsfp_5_txd_4_int), + .phy_xgmii_txc(qsfp_5_txc_4_int), + .phy_rx_clk(qsfp_5_rx_clk_4_int), + .phy_rx_rst(qsfp_5_rx_rst_4_int), + .phy_xgmii_rxd(qsfp_5_rxd_4_int), + .phy_xgmii_rxc(qsfp_5_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_5_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// QSFP 6 +assign qsfp_6_resetl = 1'b1; + +wire qsfp_6_tx_clk_1_int; +wire qsfp_6_tx_rst_1_int; +wire [63:0] qsfp_6_txd_1_int; +wire [7:0] qsfp_6_txc_1_int; +wire qsfp_6_rx_clk_1_int; +wire qsfp_6_rx_rst_1_int; +wire [63:0] qsfp_6_rxd_1_int; +wire [7:0] qsfp_6_rxc_1_int; +wire qsfp_6_tx_clk_2_int; +wire qsfp_6_tx_rst_2_int; +wire [63:0] qsfp_6_txd_2_int; +wire [7:0] qsfp_6_txc_2_int; +wire qsfp_6_rx_clk_2_int; +wire qsfp_6_rx_rst_2_int; +wire [63:0] qsfp_6_rxd_2_int; +wire [7:0] qsfp_6_rxc_2_int; +wire qsfp_6_tx_clk_3_int; +wire qsfp_6_tx_rst_3_int; +wire [63:0] qsfp_6_txd_3_int; +wire [7:0] qsfp_6_txc_3_int; +wire qsfp_6_rx_clk_3_int; +wire qsfp_6_rx_rst_3_int; +wire [63:0] qsfp_6_rxd_3_int; +wire [7:0] qsfp_6_rxc_3_int; +wire qsfp_6_tx_clk_4_int; +wire qsfp_6_tx_rst_4_int; +wire [63:0] qsfp_6_txd_4_int; +wire [7:0] qsfp_6_txc_4_int; +wire qsfp_6_rx_clk_4_int; +wire qsfp_6_rx_rst_4_int; +wire [63:0] qsfp_6_rxd_4_int; +wire [7:0] qsfp_6_rxc_4_int; + +wire qsfp_6_rx_block_lock_1; +wire qsfp_6_rx_block_lock_2; +wire qsfp_6_rx_block_lock_3; +wire qsfp_6_rx_block_lock_4; + +wire qsfp_6_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_qsfp_6_mgt_refclk_inst ( + .I (qsfp_6_mgt_refclk_p), + .IB (qsfp_6_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_6_mgt_refclk), + .ODIV2 () +); + +wire qsfp_6_qpll0lock; +wire qsfp_6_qpll0outclk; +wire qsfp_6_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +qsfp_6_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(qsfp_6_mgt_refclk), + .xcvr_qpll0lock_out(qsfp_6_qpll0lock), + .xcvr_qpll0outclk_out(qsfp_6_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp_6_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp_6_tx_p[0]), + .xcvr_txn(qsfp_6_tx_n[0]), + .xcvr_rxp(qsfp_6_rx_p[0]), + .xcvr_rxn(qsfp_6_rx_n[0]), + + // PHY connections + .phy_tx_clk(qsfp_6_tx_clk_1_int), + .phy_tx_rst(qsfp_6_tx_rst_1_int), + .phy_xgmii_txd(qsfp_6_txd_1_int), + .phy_xgmii_txc(qsfp_6_txc_1_int), + .phy_rx_clk(qsfp_6_rx_clk_1_int), + .phy_rx_rst(qsfp_6_rx_rst_1_int), + .phy_xgmii_rxd(qsfp_6_rxd_1_int), + .phy_xgmii_rxc(qsfp_6_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_6_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_6_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_6_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_6_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_6_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_6_tx_p[1]), + .xcvr_txn(qsfp_6_tx_n[1]), + .xcvr_rxp(qsfp_6_rx_p[1]), + .xcvr_rxn(qsfp_6_rx_n[1]), + + // PHY connections + .phy_tx_clk(qsfp_6_tx_clk_2_int), + .phy_tx_rst(qsfp_6_tx_rst_2_int), + .phy_xgmii_txd(qsfp_6_txd_2_int), + .phy_xgmii_txc(qsfp_6_txc_2_int), + .phy_rx_clk(qsfp_6_rx_clk_2_int), + .phy_rx_rst(qsfp_6_rx_rst_2_int), + .phy_xgmii_rxd(qsfp_6_rxd_2_int), + .phy_xgmii_rxc(qsfp_6_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_6_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_6_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_6_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_6_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_6_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_6_tx_p[2]), + .xcvr_txn(qsfp_6_tx_n[2]), + .xcvr_rxp(qsfp_6_rx_p[2]), + .xcvr_rxn(qsfp_6_rx_n[2]), + + // PHY connections + .phy_tx_clk(qsfp_6_tx_clk_3_int), + .phy_tx_rst(qsfp_6_tx_rst_3_int), + .phy_xgmii_txd(qsfp_6_txd_3_int), + .phy_xgmii_txc(qsfp_6_txc_3_int), + .phy_rx_clk(qsfp_6_rx_clk_3_int), + .phy_rx_rst(qsfp_6_rx_rst_3_int), + .phy_xgmii_rxd(qsfp_6_rxd_3_int), + .phy_xgmii_rxc(qsfp_6_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_6_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_6_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_6_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_6_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_6_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_6_tx_p[3]), + .xcvr_txn(qsfp_6_tx_n[3]), + .xcvr_rxp(qsfp_6_rx_p[3]), + .xcvr_rxn(qsfp_6_rx_n[3]), + + // PHY connections + .phy_tx_clk(qsfp_6_tx_clk_4_int), + .phy_tx_rst(qsfp_6_tx_rst_4_int), + .phy_xgmii_txd(qsfp_6_txd_4_int), + .phy_xgmii_txc(qsfp_6_txc_4_int), + .phy_rx_clk(qsfp_6_rx_clk_4_int), + .phy_rx_rst(qsfp_6_rx_rst_4_int), + .phy_xgmii_rxd(qsfp_6_rxd_4_int), + .phy_xgmii_rxc(qsfp_6_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_6_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// QSFP 7 +assign qsfp_7_resetl = 1'b1; + +wire qsfp_7_tx_clk_1_int; +wire qsfp_7_tx_rst_1_int; +wire [63:0] qsfp_7_txd_1_int; +wire [7:0] qsfp_7_txc_1_int; +wire qsfp_7_rx_clk_1_int; +wire qsfp_7_rx_rst_1_int; +wire [63:0] qsfp_7_rxd_1_int; +wire [7:0] qsfp_7_rxc_1_int; +wire qsfp_7_tx_clk_2_int; +wire qsfp_7_tx_rst_2_int; +wire [63:0] qsfp_7_txd_2_int; +wire [7:0] qsfp_7_txc_2_int; +wire qsfp_7_rx_clk_2_int; +wire qsfp_7_rx_rst_2_int; +wire [63:0] qsfp_7_rxd_2_int; +wire [7:0] qsfp_7_rxc_2_int; +wire qsfp_7_tx_clk_3_int; +wire qsfp_7_tx_rst_3_int; +wire [63:0] qsfp_7_txd_3_int; +wire [7:0] qsfp_7_txc_3_int; +wire qsfp_7_rx_clk_3_int; +wire qsfp_7_rx_rst_3_int; +wire [63:0] qsfp_7_rxd_3_int; +wire [7:0] qsfp_7_rxc_3_int; +wire qsfp_7_tx_clk_4_int; +wire qsfp_7_tx_rst_4_int; +wire [63:0] qsfp_7_txd_4_int; +wire [7:0] qsfp_7_txc_4_int; +wire qsfp_7_rx_clk_4_int; +wire qsfp_7_rx_rst_4_int; +wire [63:0] qsfp_7_rxd_4_int; +wire [7:0] qsfp_7_rxc_4_int; + +wire qsfp_7_rx_block_lock_1; +wire qsfp_7_rx_block_lock_2; +wire qsfp_7_rx_block_lock_3; +wire qsfp_7_rx_block_lock_4; + +wire qsfp_7_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_qsfp_7_mgt_refclk_inst ( + .I (qsfp_7_mgt_refclk_p), + .IB (qsfp_7_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_7_mgt_refclk), + .ODIV2 () +); + +wire qsfp_7_qpll0lock; +wire qsfp_7_qpll0outclk; +wire qsfp_7_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +qsfp_7_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(qsfp_7_mgt_refclk), + .xcvr_qpll0lock_out(qsfp_7_qpll0lock), + .xcvr_qpll0outclk_out(qsfp_7_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp_7_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp_7_tx_p[0]), + .xcvr_txn(qsfp_7_tx_n[0]), + .xcvr_rxp(qsfp_7_rx_p[0]), + .xcvr_rxn(qsfp_7_rx_n[0]), + + // PHY connections + .phy_tx_clk(qsfp_7_tx_clk_1_int), + .phy_tx_rst(qsfp_7_tx_rst_1_int), + .phy_xgmii_txd(qsfp_7_txd_1_int), + .phy_xgmii_txc(qsfp_7_txc_1_int), + .phy_rx_clk(qsfp_7_rx_clk_1_int), + .phy_rx_rst(qsfp_7_rx_rst_1_int), + .phy_xgmii_rxd(qsfp_7_rxd_1_int), + .phy_xgmii_rxc(qsfp_7_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_7_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_7_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_7_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_7_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_7_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_7_tx_p[1]), + .xcvr_txn(qsfp_7_tx_n[1]), + .xcvr_rxp(qsfp_7_rx_p[1]), + .xcvr_rxn(qsfp_7_rx_n[1]), + + // PHY connections + .phy_tx_clk(qsfp_7_tx_clk_2_int), + .phy_tx_rst(qsfp_7_tx_rst_2_int), + .phy_xgmii_txd(qsfp_7_txd_2_int), + .phy_xgmii_txc(qsfp_7_txc_2_int), + .phy_rx_clk(qsfp_7_rx_clk_2_int), + .phy_rx_rst(qsfp_7_rx_rst_2_int), + .phy_xgmii_rxd(qsfp_7_rxd_2_int), + .phy_xgmii_rxc(qsfp_7_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_7_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_7_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_7_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_7_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_7_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_7_tx_p[2]), + .xcvr_txn(qsfp_7_tx_n[2]), + .xcvr_rxp(qsfp_7_rx_p[2]), + .xcvr_rxn(qsfp_7_rx_n[2]), + + // PHY connections + .phy_tx_clk(qsfp_7_tx_clk_3_int), + .phy_tx_rst(qsfp_7_tx_rst_3_int), + .phy_xgmii_txd(qsfp_7_txd_3_int), + .phy_xgmii_txc(qsfp_7_txc_3_int), + .phy_rx_clk(qsfp_7_rx_clk_3_int), + .phy_rx_rst(qsfp_7_rx_rst_3_int), + .phy_xgmii_rxd(qsfp_7_rxd_3_int), + .phy_xgmii_rxc(qsfp_7_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_7_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_7_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_7_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_7_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_7_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_7_tx_p[3]), + .xcvr_txn(qsfp_7_tx_n[3]), + .xcvr_rxp(qsfp_7_rx_p[3]), + .xcvr_rxn(qsfp_7_rx_n[3]), + + // PHY connections + .phy_tx_clk(qsfp_7_tx_clk_4_int), + .phy_tx_rst(qsfp_7_tx_rst_4_int), + .phy_xgmii_txd(qsfp_7_txd_4_int), + .phy_xgmii_txc(qsfp_7_txc_4_int), + .phy_rx_clk(qsfp_7_rx_clk_4_int), + .phy_rx_rst(qsfp_7_rx_rst_4_int), + .phy_xgmii_rxd(qsfp_7_rxd_4_int), + .phy_xgmii_rxc(qsfp_7_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_7_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// QSFP 8 +assign qsfp_8_resetl = 1'b1; + +wire qsfp_8_tx_clk_1_int; +wire qsfp_8_tx_rst_1_int; +wire [63:0] qsfp_8_txd_1_int; +wire [7:0] qsfp_8_txc_1_int; +wire qsfp_8_rx_clk_1_int; +wire qsfp_8_rx_rst_1_int; +wire [63:0] qsfp_8_rxd_1_int; +wire [7:0] qsfp_8_rxc_1_int; +wire qsfp_8_tx_clk_2_int; +wire qsfp_8_tx_rst_2_int; +wire [63:0] qsfp_8_txd_2_int; +wire [7:0] qsfp_8_txc_2_int; +wire qsfp_8_rx_clk_2_int; +wire qsfp_8_rx_rst_2_int; +wire [63:0] qsfp_8_rxd_2_int; +wire [7:0] qsfp_8_rxc_2_int; +wire qsfp_8_tx_clk_3_int; +wire qsfp_8_tx_rst_3_int; +wire [63:0] qsfp_8_txd_3_int; +wire [7:0] qsfp_8_txc_3_int; +wire qsfp_8_rx_clk_3_int; +wire qsfp_8_rx_rst_3_int; +wire [63:0] qsfp_8_rxd_3_int; +wire [7:0] qsfp_8_rxc_3_int; +wire qsfp_8_tx_clk_4_int; +wire qsfp_8_tx_rst_4_int; +wire [63:0] qsfp_8_txd_4_int; +wire [7:0] qsfp_8_txc_4_int; +wire qsfp_8_rx_clk_4_int; +wire qsfp_8_rx_rst_4_int; +wire [63:0] qsfp_8_rxd_4_int; +wire [7:0] qsfp_8_rxc_4_int; + +wire qsfp_8_rx_block_lock_1; +wire qsfp_8_rx_block_lock_2; +wire qsfp_8_rx_block_lock_3; +wire qsfp_8_rx_block_lock_4; + +wire qsfp_8_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_qsfp_8_mgt_refclk_inst ( + .I (qsfp_8_mgt_refclk_p), + .IB (qsfp_8_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_8_mgt_refclk), + .ODIV2 () +); + +wire qsfp_8_qpll0lock; +wire qsfp_8_qpll0outclk; +wire qsfp_8_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +qsfp_8_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(qsfp_8_mgt_refclk), + .xcvr_qpll0lock_out(qsfp_8_qpll0lock), + .xcvr_qpll0outclk_out(qsfp_8_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp_8_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp_8_tx_p[0]), + .xcvr_txn(qsfp_8_tx_n[0]), + .xcvr_rxp(qsfp_8_rx_p[0]), + .xcvr_rxn(qsfp_8_rx_n[0]), + + // PHY connections + .phy_tx_clk(qsfp_8_tx_clk_1_int), + .phy_tx_rst(qsfp_8_tx_rst_1_int), + .phy_xgmii_txd(qsfp_8_txd_1_int), + .phy_xgmii_txc(qsfp_8_txc_1_int), + .phy_rx_clk(qsfp_8_rx_clk_1_int), + .phy_rx_rst(qsfp_8_rx_rst_1_int), + .phy_xgmii_rxd(qsfp_8_rxd_1_int), + .phy_xgmii_rxc(qsfp_8_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_8_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_8_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_8_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_8_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_8_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_8_tx_p[1]), + .xcvr_txn(qsfp_8_tx_n[1]), + .xcvr_rxp(qsfp_8_rx_p[1]), + .xcvr_rxn(qsfp_8_rx_n[1]), + + // PHY connections + .phy_tx_clk(qsfp_8_tx_clk_2_int), + .phy_tx_rst(qsfp_8_tx_rst_2_int), + .phy_xgmii_txd(qsfp_8_txd_2_int), + .phy_xgmii_txc(qsfp_8_txc_2_int), + .phy_rx_clk(qsfp_8_rx_clk_2_int), + .phy_rx_rst(qsfp_8_rx_rst_2_int), + .phy_xgmii_rxd(qsfp_8_rxd_2_int), + .phy_xgmii_rxc(qsfp_8_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_8_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_8_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_8_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_8_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_8_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_8_tx_p[2]), + .xcvr_txn(qsfp_8_tx_n[2]), + .xcvr_rxp(qsfp_8_rx_p[2]), + .xcvr_rxn(qsfp_8_rx_n[2]), + + // PHY connections + .phy_tx_clk(qsfp_8_tx_clk_3_int), + .phy_tx_rst(qsfp_8_tx_rst_3_int), + .phy_xgmii_txd(qsfp_8_txd_3_int), + .phy_xgmii_txc(qsfp_8_txc_3_int), + .phy_rx_clk(qsfp_8_rx_clk_3_int), + .phy_rx_rst(qsfp_8_rx_rst_3_int), + .phy_xgmii_rxd(qsfp_8_rxd_3_int), + .phy_xgmii_rxc(qsfp_8_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_8_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_8_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_8_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_8_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_8_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_8_tx_p[3]), + .xcvr_txn(qsfp_8_tx_n[3]), + .xcvr_rxp(qsfp_8_rx_p[3]), + .xcvr_rxn(qsfp_8_rx_n[3]), + + // PHY connections + .phy_tx_clk(qsfp_8_tx_clk_4_int), + .phy_tx_rst(qsfp_8_tx_rst_4_int), + .phy_xgmii_txd(qsfp_8_txd_4_int), + .phy_xgmii_txc(qsfp_8_txc_4_int), + .phy_rx_clk(qsfp_8_rx_clk_4_int), + .phy_rx_rst(qsfp_8_rx_rst_4_int), + .phy_xgmii_rxd(qsfp_8_rxd_4_int), + .phy_xgmii_rxc(qsfp_8_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_8_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// QSFP 9 +assign qsfp_9_resetl = 1'b1; + +wire qsfp_9_tx_clk_1_int; +wire qsfp_9_tx_rst_1_int; +wire [63:0] qsfp_9_txd_1_int; +wire [7:0] qsfp_9_txc_1_int; +wire qsfp_9_rx_clk_1_int; +wire qsfp_9_rx_rst_1_int; +wire [63:0] qsfp_9_rxd_1_int; +wire [7:0] qsfp_9_rxc_1_int; +wire qsfp_9_tx_clk_2_int; +wire qsfp_9_tx_rst_2_int; +wire [63:0] qsfp_9_txd_2_int; +wire [7:0] qsfp_9_txc_2_int; +wire qsfp_9_rx_clk_2_int; +wire qsfp_9_rx_rst_2_int; +wire [63:0] qsfp_9_rxd_2_int; +wire [7:0] qsfp_9_rxc_2_int; +wire qsfp_9_tx_clk_3_int; +wire qsfp_9_tx_rst_3_int; +wire [63:0] qsfp_9_txd_3_int; +wire [7:0] qsfp_9_txc_3_int; +wire qsfp_9_rx_clk_3_int; +wire qsfp_9_rx_rst_3_int; +wire [63:0] qsfp_9_rxd_3_int; +wire [7:0] qsfp_9_rxc_3_int; +wire qsfp_9_tx_clk_4_int; +wire qsfp_9_tx_rst_4_int; +wire [63:0] qsfp_9_txd_4_int; +wire [7:0] qsfp_9_txc_4_int; +wire qsfp_9_rx_clk_4_int; +wire qsfp_9_rx_rst_4_int; +wire [63:0] qsfp_9_rxd_4_int; +wire [7:0] qsfp_9_rxc_4_int; + +wire qsfp_9_rx_block_lock_1; +wire qsfp_9_rx_block_lock_2; +wire qsfp_9_rx_block_lock_3; +wire qsfp_9_rx_block_lock_4; + +wire qsfp_9_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_qsfp_9_mgt_refclk_inst ( + .I (qsfp_9_mgt_refclk_p), + .IB (qsfp_9_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_9_mgt_refclk), + .ODIV2 () +); + +wire qsfp_9_qpll0lock; +wire qsfp_9_qpll0outclk; +wire qsfp_9_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +qsfp_9_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(qsfp_9_mgt_refclk), + .xcvr_qpll0lock_out(qsfp_9_qpll0lock), + .xcvr_qpll0outclk_out(qsfp_9_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp_9_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp_9_tx_p[0]), + .xcvr_txn(qsfp_9_tx_n[0]), + .xcvr_rxp(qsfp_9_rx_p[0]), + .xcvr_rxn(qsfp_9_rx_n[0]), + + // PHY connections + .phy_tx_clk(qsfp_9_tx_clk_1_int), + .phy_tx_rst(qsfp_9_tx_rst_1_int), + .phy_xgmii_txd(qsfp_9_txd_1_int), + .phy_xgmii_txc(qsfp_9_txc_1_int), + .phy_rx_clk(qsfp_9_rx_clk_1_int), + .phy_rx_rst(qsfp_9_rx_rst_1_int), + .phy_xgmii_rxd(qsfp_9_rxd_1_int), + .phy_xgmii_rxc(qsfp_9_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_9_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_9_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_9_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_9_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_9_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_9_tx_p[1]), + .xcvr_txn(qsfp_9_tx_n[1]), + .xcvr_rxp(qsfp_9_rx_p[1]), + .xcvr_rxn(qsfp_9_rx_n[1]), + + // PHY connections + .phy_tx_clk(qsfp_9_tx_clk_2_int), + .phy_tx_rst(qsfp_9_tx_rst_2_int), + .phy_xgmii_txd(qsfp_9_txd_2_int), + .phy_xgmii_txc(qsfp_9_txc_2_int), + .phy_rx_clk(qsfp_9_rx_clk_2_int), + .phy_rx_rst(qsfp_9_rx_rst_2_int), + .phy_xgmii_rxd(qsfp_9_rxd_2_int), + .phy_xgmii_rxc(qsfp_9_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_9_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_9_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_9_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_9_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_9_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_9_tx_p[2]), + .xcvr_txn(qsfp_9_tx_n[2]), + .xcvr_rxp(qsfp_9_rx_p[2]), + .xcvr_rxn(qsfp_9_rx_n[2]), + + // PHY connections + .phy_tx_clk(qsfp_9_tx_clk_3_int), + .phy_tx_rst(qsfp_9_tx_rst_3_int), + .phy_xgmii_txd(qsfp_9_txd_3_int), + .phy_xgmii_txc(qsfp_9_txc_3_int), + .phy_rx_clk(qsfp_9_rx_clk_3_int), + .phy_rx_rst(qsfp_9_rx_rst_3_int), + .phy_xgmii_rxd(qsfp_9_rxd_3_int), + .phy_xgmii_rxc(qsfp_9_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_9_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +qsfp_9_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp_9_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp_9_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp_9_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp_9_tx_p[3]), + .xcvr_txn(qsfp_9_tx_n[3]), + .xcvr_rxp(qsfp_9_rx_p[3]), + .xcvr_rxn(qsfp_9_rx_n[3]), + + // PHY connections + .phy_tx_clk(qsfp_9_tx_clk_4_int), + .phy_tx_rst(qsfp_9_tx_rst_4_int), + .phy_xgmii_txd(qsfp_9_txd_4_int), + .phy_xgmii_txc(qsfp_9_txc_4_int), + .phy_rx_clk(qsfp_9_rx_clk_4_int), + .phy_rx_rst(qsfp_9_rx_rst_4_int), + .phy_xgmii_rxd(qsfp_9_rxd_4_int), + .phy_xgmii_rxc(qsfp_9_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp_9_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// FMC QSFP 1 +assign fmc_qsfp_1_modsell = 1'b1; +assign fmc_qsfp_1_resetl = 1'b1; +assign fmc_qsfp_1_lpmode = 1'b0; + +wire fmc_qsfp_1_tx_clk_1_int; +wire fmc_qsfp_1_tx_rst_1_int; +wire [63:0] fmc_qsfp_1_txd_1_int; +wire [7:0] fmc_qsfp_1_txc_1_int; +wire fmc_qsfp_1_rx_clk_1_int; +wire fmc_qsfp_1_rx_rst_1_int; +wire [63:0] fmc_qsfp_1_rxd_1_int; +wire [7:0] fmc_qsfp_1_rxc_1_int; +wire fmc_qsfp_1_tx_clk_2_int; +wire fmc_qsfp_1_tx_rst_2_int; +wire [63:0] fmc_qsfp_1_txd_2_int; +wire [7:0] fmc_qsfp_1_txc_2_int; +wire fmc_qsfp_1_rx_clk_2_int; +wire fmc_qsfp_1_rx_rst_2_int; +wire [63:0] fmc_qsfp_1_rxd_2_int; +wire [7:0] fmc_qsfp_1_rxc_2_int; +wire fmc_qsfp_1_tx_clk_3_int; +wire fmc_qsfp_1_tx_rst_3_int; +wire [63:0] fmc_qsfp_1_txd_3_int; +wire [7:0] fmc_qsfp_1_txc_3_int; +wire fmc_qsfp_1_rx_clk_3_int; +wire fmc_qsfp_1_rx_rst_3_int; +wire [63:0] fmc_qsfp_1_rxd_3_int; +wire [7:0] fmc_qsfp_1_rxc_3_int; +wire fmc_qsfp_1_tx_clk_4_int; +wire fmc_qsfp_1_tx_rst_4_int; +wire [63:0] fmc_qsfp_1_txd_4_int; +wire [7:0] fmc_qsfp_1_txc_4_int; +wire fmc_qsfp_1_rx_clk_4_int; +wire fmc_qsfp_1_rx_rst_4_int; +wire [63:0] fmc_qsfp_1_rxd_4_int; +wire [7:0] fmc_qsfp_1_rxc_4_int; + +wire fmc_qsfp_1_rx_block_lock_1; +wire fmc_qsfp_1_rx_block_lock_2; +wire fmc_qsfp_1_rx_block_lock_3; +wire fmc_qsfp_1_rx_block_lock_4; + +wire fmc_qsfp_1_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_fmc_qsfp_1_mgt_refclk_inst ( + .I (fmc_qsfp_1_mgt_refclk_p), + .IB (fmc_qsfp_1_mgt_refclk_n), + .CEB (1'b0), + .O (fmc_qsfp_1_mgt_refclk), + .ODIV2 () +); + +wire fmc_qsfp_1_qpll0lock; +wire fmc_qsfp_1_qpll0outclk; +wire fmc_qsfp_1_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +fmc_qsfp_1_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(fmc_qsfp_1_mgt_refclk), + .xcvr_qpll0lock_out(fmc_qsfp_1_qpll0lock), + .xcvr_qpll0outclk_out(fmc_qsfp_1_qpll0outclk), + .xcvr_qpll0outrefclk_out(fmc_qsfp_1_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(fmc_qsfp_1_tx_p[0]), + .xcvr_txn(fmc_qsfp_1_tx_n[0]), + .xcvr_rxp(fmc_qsfp_1_rx_p[0]), + .xcvr_rxn(fmc_qsfp_1_rx_n[0]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_1_tx_clk_1_int), + .phy_tx_rst(fmc_qsfp_1_tx_rst_1_int), + .phy_xgmii_txd(fmc_qsfp_1_txd_1_int), + .phy_xgmii_txc(fmc_qsfp_1_txc_1_int), + .phy_rx_clk(fmc_qsfp_1_rx_clk_1_int), + .phy_rx_rst(fmc_qsfp_1_rx_rst_1_int), + .phy_xgmii_rxd(fmc_qsfp_1_rxd_1_int), + .phy_xgmii_rxc(fmc_qsfp_1_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_1_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_1_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_1_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_1_tx_p[1]), + .xcvr_txn(fmc_qsfp_1_tx_n[1]), + .xcvr_rxp(fmc_qsfp_1_rx_p[1]), + .xcvr_rxn(fmc_qsfp_1_rx_n[1]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_1_tx_clk_2_int), + .phy_tx_rst(fmc_qsfp_1_tx_rst_2_int), + .phy_xgmii_txd(fmc_qsfp_1_txd_2_int), + .phy_xgmii_txc(fmc_qsfp_1_txc_2_int), + .phy_rx_clk(fmc_qsfp_1_rx_clk_2_int), + .phy_rx_rst(fmc_qsfp_1_rx_rst_2_int), + .phy_xgmii_rxd(fmc_qsfp_1_rxd_2_int), + .phy_xgmii_rxc(fmc_qsfp_1_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_1_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_1_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_1_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_1_tx_p[2]), + .xcvr_txn(fmc_qsfp_1_tx_n[2]), + .xcvr_rxp(fmc_qsfp_1_rx_p[2]), + .xcvr_rxn(fmc_qsfp_1_rx_n[2]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_1_tx_clk_3_int), + .phy_tx_rst(fmc_qsfp_1_tx_rst_3_int), + .phy_xgmii_txd(fmc_qsfp_1_txd_3_int), + .phy_xgmii_txc(fmc_qsfp_1_txc_3_int), + .phy_rx_clk(fmc_qsfp_1_rx_clk_3_int), + .phy_rx_rst(fmc_qsfp_1_rx_rst_3_int), + .phy_xgmii_rxd(fmc_qsfp_1_rxd_3_int), + .phy_xgmii_rxc(fmc_qsfp_1_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_1_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_1_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_1_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_1_tx_p[3]), + .xcvr_txn(fmc_qsfp_1_tx_n[3]), + .xcvr_rxp(fmc_qsfp_1_rx_p[3]), + .xcvr_rxn(fmc_qsfp_1_rx_n[3]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_1_tx_clk_4_int), + .phy_tx_rst(fmc_qsfp_1_tx_rst_4_int), + .phy_xgmii_txd(fmc_qsfp_1_txd_4_int), + .phy_xgmii_txc(fmc_qsfp_1_txc_4_int), + .phy_rx_clk(fmc_qsfp_1_rx_clk_4_int), + .phy_rx_rst(fmc_qsfp_1_rx_rst_4_int), + .phy_xgmii_rxd(fmc_qsfp_1_rxd_4_int), + .phy_xgmii_rxc(fmc_qsfp_1_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_1_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// FMC QSFP 2 +assign fmc_qsfp_2_modsell = 1'b1; +assign fmc_qsfp_2_resetl = 1'b1; +assign fmc_qsfp_2_lpmode = 1'b0; + +wire fmc_qsfp_2_tx_clk_1_int; +wire fmc_qsfp_2_tx_rst_1_int; +wire [63:0] fmc_qsfp_2_txd_1_int; +wire [7:0] fmc_qsfp_2_txc_1_int; +wire fmc_qsfp_2_rx_clk_1_int; +wire fmc_qsfp_2_rx_rst_1_int; +wire [63:0] fmc_qsfp_2_rxd_1_int; +wire [7:0] fmc_qsfp_2_rxc_1_int; +wire fmc_qsfp_2_tx_clk_2_int; +wire fmc_qsfp_2_tx_rst_2_int; +wire [63:0] fmc_qsfp_2_txd_2_int; +wire [7:0] fmc_qsfp_2_txc_2_int; +wire fmc_qsfp_2_rx_clk_2_int; +wire fmc_qsfp_2_rx_rst_2_int; +wire [63:0] fmc_qsfp_2_rxd_2_int; +wire [7:0] fmc_qsfp_2_rxc_2_int; +wire fmc_qsfp_2_tx_clk_3_int; +wire fmc_qsfp_2_tx_rst_3_int; +wire [63:0] fmc_qsfp_2_txd_3_int; +wire [7:0] fmc_qsfp_2_txc_3_int; +wire fmc_qsfp_2_rx_clk_3_int; +wire fmc_qsfp_2_rx_rst_3_int; +wire [63:0] fmc_qsfp_2_rxd_3_int; +wire [7:0] fmc_qsfp_2_rxc_3_int; +wire fmc_qsfp_2_tx_clk_4_int; +wire fmc_qsfp_2_tx_rst_4_int; +wire [63:0] fmc_qsfp_2_txd_4_int; +wire [7:0] fmc_qsfp_2_txc_4_int; +wire fmc_qsfp_2_rx_clk_4_int; +wire fmc_qsfp_2_rx_rst_4_int; +wire [63:0] fmc_qsfp_2_rxd_4_int; +wire [7:0] fmc_qsfp_2_rxc_4_int; + +wire fmc_qsfp_2_rx_block_lock_1; +wire fmc_qsfp_2_rx_block_lock_2; +wire fmc_qsfp_2_rx_block_lock_3; +wire fmc_qsfp_2_rx_block_lock_4; + +wire fmc_qsfp_2_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_fmc_qsfp_2_mgt_refclk_inst ( + .I (fmc_qsfp_2_mgt_refclk_p), + .IB (fmc_qsfp_2_mgt_refclk_n), + .CEB (1'b0), + .O (fmc_qsfp_2_mgt_refclk), + .ODIV2 () +); + +wire fmc_qsfp_2_qpll0lock; +wire fmc_qsfp_2_qpll0outclk; +wire fmc_qsfp_2_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +fmc_qsfp_2_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(fmc_qsfp_2_mgt_refclk), + .xcvr_qpll0lock_out(fmc_qsfp_2_qpll0lock), + .xcvr_qpll0outclk_out(fmc_qsfp_2_qpll0outclk), + .xcvr_qpll0outrefclk_out(fmc_qsfp_2_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(fmc_qsfp_2_tx_p[0]), + .xcvr_txn(fmc_qsfp_2_tx_n[0]), + .xcvr_rxp(fmc_qsfp_2_rx_p[0]), + .xcvr_rxn(fmc_qsfp_2_rx_n[0]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_2_tx_clk_1_int), + .phy_tx_rst(fmc_qsfp_2_tx_rst_1_int), + .phy_xgmii_txd(fmc_qsfp_2_txd_1_int), + .phy_xgmii_txc(fmc_qsfp_2_txc_1_int), + .phy_rx_clk(fmc_qsfp_2_rx_clk_1_int), + .phy_rx_rst(fmc_qsfp_2_rx_rst_1_int), + .phy_xgmii_rxd(fmc_qsfp_2_rxd_1_int), + .phy_xgmii_rxc(fmc_qsfp_2_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_2_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_2_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_2_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_2_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_2_tx_p[1]), + .xcvr_txn(fmc_qsfp_2_tx_n[1]), + .xcvr_rxp(fmc_qsfp_2_rx_p[1]), + .xcvr_rxn(fmc_qsfp_2_rx_n[1]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_2_tx_clk_2_int), + .phy_tx_rst(fmc_qsfp_2_tx_rst_2_int), + .phy_xgmii_txd(fmc_qsfp_2_txd_2_int), + .phy_xgmii_txc(fmc_qsfp_2_txc_2_int), + .phy_rx_clk(fmc_qsfp_2_rx_clk_2_int), + .phy_rx_rst(fmc_qsfp_2_rx_rst_2_int), + .phy_xgmii_rxd(fmc_qsfp_2_rxd_2_int), + .phy_xgmii_rxc(fmc_qsfp_2_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_2_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_2_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_2_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_2_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_2_tx_p[2]), + .xcvr_txn(fmc_qsfp_2_tx_n[2]), + .xcvr_rxp(fmc_qsfp_2_rx_p[2]), + .xcvr_rxn(fmc_qsfp_2_rx_n[2]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_2_tx_clk_3_int), + .phy_tx_rst(fmc_qsfp_2_tx_rst_3_int), + .phy_xgmii_txd(fmc_qsfp_2_txd_3_int), + .phy_xgmii_txc(fmc_qsfp_2_txc_3_int), + .phy_rx_clk(fmc_qsfp_2_rx_clk_3_int), + .phy_rx_rst(fmc_qsfp_2_rx_rst_3_int), + .phy_xgmii_rxd(fmc_qsfp_2_rxd_3_int), + .phy_xgmii_rxc(fmc_qsfp_2_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_2_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_2_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_2_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_2_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_2_tx_p[3]), + .xcvr_txn(fmc_qsfp_2_tx_n[3]), + .xcvr_rxp(fmc_qsfp_2_rx_p[3]), + .xcvr_rxn(fmc_qsfp_2_rx_n[3]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_2_tx_clk_4_int), + .phy_tx_rst(fmc_qsfp_2_tx_rst_4_int), + .phy_xgmii_txd(fmc_qsfp_2_txd_4_int), + .phy_xgmii_txc(fmc_qsfp_2_txc_4_int), + .phy_rx_clk(fmc_qsfp_2_rx_clk_4_int), + .phy_rx_rst(fmc_qsfp_2_rx_rst_4_int), + .phy_xgmii_rxd(fmc_qsfp_2_rxd_4_int), + .phy_xgmii_rxc(fmc_qsfp_2_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_2_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// FMC QSFP 3 +assign fmc_qsfp_3_modsell = 1'b1; +assign fmc_qsfp_3_resetl = 1'b1; +assign fmc_qsfp_3_lpmode = 1'b0; + +wire fmc_qsfp_3_tx_clk_1_int; +wire fmc_qsfp_3_tx_rst_1_int; +wire [63:0] fmc_qsfp_3_txd_1_int; +wire [7:0] fmc_qsfp_3_txc_1_int; +wire fmc_qsfp_3_rx_clk_1_int; +wire fmc_qsfp_3_rx_rst_1_int; +wire [63:0] fmc_qsfp_3_rxd_1_int; +wire [7:0] fmc_qsfp_3_rxc_1_int; +wire fmc_qsfp_3_tx_clk_2_int; +wire fmc_qsfp_3_tx_rst_2_int; +wire [63:0] fmc_qsfp_3_txd_2_int; +wire [7:0] fmc_qsfp_3_txc_2_int; +wire fmc_qsfp_3_rx_clk_2_int; +wire fmc_qsfp_3_rx_rst_2_int; +wire [63:0] fmc_qsfp_3_rxd_2_int; +wire [7:0] fmc_qsfp_3_rxc_2_int; +wire fmc_qsfp_3_tx_clk_3_int; +wire fmc_qsfp_3_tx_rst_3_int; +wire [63:0] fmc_qsfp_3_txd_3_int; +wire [7:0] fmc_qsfp_3_txc_3_int; +wire fmc_qsfp_3_rx_clk_3_int; +wire fmc_qsfp_3_rx_rst_3_int; +wire [63:0] fmc_qsfp_3_rxd_3_int; +wire [7:0] fmc_qsfp_3_rxc_3_int; +wire fmc_qsfp_3_tx_clk_4_int; +wire fmc_qsfp_3_tx_rst_4_int; +wire [63:0] fmc_qsfp_3_txd_4_int; +wire [7:0] fmc_qsfp_3_txc_4_int; +wire fmc_qsfp_3_rx_clk_4_int; +wire fmc_qsfp_3_rx_rst_4_int; +wire [63:0] fmc_qsfp_3_rxd_4_int; +wire [7:0] fmc_qsfp_3_rxc_4_int; + +wire fmc_qsfp_3_rx_block_lock_1; +wire fmc_qsfp_3_rx_block_lock_2; +wire fmc_qsfp_3_rx_block_lock_3; +wire fmc_qsfp_3_rx_block_lock_4; + +wire fmc_qsfp_3_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_fmc_qsfp_3_mgt_refclk_inst ( + .I (fmc_qsfp_3_mgt_refclk_p), + .IB (fmc_qsfp_3_mgt_refclk_n), + .CEB (1'b0), + .O (fmc_qsfp_3_mgt_refclk), + .ODIV2 () +); + +wire fmc_qsfp_3_qpll0lock; +wire fmc_qsfp_3_qpll0outclk; +wire fmc_qsfp_3_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +fmc_qsfp_3_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(fmc_qsfp_3_mgt_refclk), + .xcvr_qpll0lock_out(fmc_qsfp_3_qpll0lock), + .xcvr_qpll0outclk_out(fmc_qsfp_3_qpll0outclk), + .xcvr_qpll0outrefclk_out(fmc_qsfp_3_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(fmc_qsfp_3_tx_p[0]), + .xcvr_txn(fmc_qsfp_3_tx_n[0]), + .xcvr_rxp(fmc_qsfp_3_rx_p[0]), + .xcvr_rxn(fmc_qsfp_3_rx_n[0]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_3_tx_clk_1_int), + .phy_tx_rst(fmc_qsfp_3_tx_rst_1_int), + .phy_xgmii_txd(fmc_qsfp_3_txd_1_int), + .phy_xgmii_txc(fmc_qsfp_3_txc_1_int), + .phy_rx_clk(fmc_qsfp_3_rx_clk_1_int), + .phy_rx_rst(fmc_qsfp_3_rx_rst_1_int), + .phy_xgmii_rxd(fmc_qsfp_3_rxd_1_int), + .phy_xgmii_rxc(fmc_qsfp_3_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_3_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_3_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_3_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_3_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_3_tx_p[1]), + .xcvr_txn(fmc_qsfp_3_tx_n[1]), + .xcvr_rxp(fmc_qsfp_3_rx_p[1]), + .xcvr_rxn(fmc_qsfp_3_rx_n[1]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_3_tx_clk_2_int), + .phy_tx_rst(fmc_qsfp_3_tx_rst_2_int), + .phy_xgmii_txd(fmc_qsfp_3_txd_2_int), + .phy_xgmii_txc(fmc_qsfp_3_txc_2_int), + .phy_rx_clk(fmc_qsfp_3_rx_clk_2_int), + .phy_rx_rst(fmc_qsfp_3_rx_rst_2_int), + .phy_xgmii_rxd(fmc_qsfp_3_rxd_2_int), + .phy_xgmii_rxc(fmc_qsfp_3_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_3_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_3_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_3_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_3_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_3_tx_p[2]), + .xcvr_txn(fmc_qsfp_3_tx_n[2]), + .xcvr_rxp(fmc_qsfp_3_rx_p[2]), + .xcvr_rxn(fmc_qsfp_3_rx_n[2]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_3_tx_clk_3_int), + .phy_tx_rst(fmc_qsfp_3_tx_rst_3_int), + .phy_xgmii_txd(fmc_qsfp_3_txd_3_int), + .phy_xgmii_txc(fmc_qsfp_3_txc_3_int), + .phy_rx_clk(fmc_qsfp_3_rx_clk_3_int), + .phy_rx_rst(fmc_qsfp_3_rx_rst_3_int), + .phy_xgmii_rxd(fmc_qsfp_3_rxd_3_int), + .phy_xgmii_rxc(fmc_qsfp_3_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_3_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_3_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_3_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_3_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_3_tx_p[3]), + .xcvr_txn(fmc_qsfp_3_tx_n[3]), + .xcvr_rxp(fmc_qsfp_3_rx_p[3]), + .xcvr_rxn(fmc_qsfp_3_rx_n[3]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_3_tx_clk_4_int), + .phy_tx_rst(fmc_qsfp_3_tx_rst_4_int), + .phy_xgmii_txd(fmc_qsfp_3_txd_4_int), + .phy_xgmii_txc(fmc_qsfp_3_txc_4_int), + .phy_rx_clk(fmc_qsfp_3_rx_clk_4_int), + .phy_rx_rst(fmc_qsfp_3_rx_rst_4_int), + .phy_xgmii_rxd(fmc_qsfp_3_rxd_4_int), + .phy_xgmii_rxc(fmc_qsfp_3_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_3_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// FMC QSFP 4 +assign fmc_qsfp_4_modsell = 1'b1; +assign fmc_qsfp_4_resetl = 1'b1; +assign fmc_qsfp_4_lpmode = 1'b0; + +wire fmc_qsfp_4_tx_clk_1_int; +wire fmc_qsfp_4_tx_rst_1_int; +wire [63:0] fmc_qsfp_4_txd_1_int; +wire [7:0] fmc_qsfp_4_txc_1_int; +wire fmc_qsfp_4_rx_clk_1_int; +wire fmc_qsfp_4_rx_rst_1_int; +wire [63:0] fmc_qsfp_4_rxd_1_int; +wire [7:0] fmc_qsfp_4_rxc_1_int; +wire fmc_qsfp_4_tx_clk_2_int; +wire fmc_qsfp_4_tx_rst_2_int; +wire [63:0] fmc_qsfp_4_txd_2_int; +wire [7:0] fmc_qsfp_4_txc_2_int; +wire fmc_qsfp_4_rx_clk_2_int; +wire fmc_qsfp_4_rx_rst_2_int; +wire [63:0] fmc_qsfp_4_rxd_2_int; +wire [7:0] fmc_qsfp_4_rxc_2_int; +wire fmc_qsfp_4_tx_clk_3_int; +wire fmc_qsfp_4_tx_rst_3_int; +wire [63:0] fmc_qsfp_4_txd_3_int; +wire [7:0] fmc_qsfp_4_txc_3_int; +wire fmc_qsfp_4_rx_clk_3_int; +wire fmc_qsfp_4_rx_rst_3_int; +wire [63:0] fmc_qsfp_4_rxd_3_int; +wire [7:0] fmc_qsfp_4_rxc_3_int; +wire fmc_qsfp_4_tx_clk_4_int; +wire fmc_qsfp_4_tx_rst_4_int; +wire [63:0] fmc_qsfp_4_txd_4_int; +wire [7:0] fmc_qsfp_4_txc_4_int; +wire fmc_qsfp_4_rx_clk_4_int; +wire fmc_qsfp_4_rx_rst_4_int; +wire [63:0] fmc_qsfp_4_rxd_4_int; +wire [7:0] fmc_qsfp_4_rxc_4_int; + +wire fmc_qsfp_4_rx_block_lock_1; +wire fmc_qsfp_4_rx_block_lock_2; +wire fmc_qsfp_4_rx_block_lock_3; +wire fmc_qsfp_4_rx_block_lock_4; + +wire fmc_qsfp_4_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_fmc_qsfp_4_mgt_refclk_inst ( + .I (fmc_qsfp_4_mgt_refclk_p), + .IB (fmc_qsfp_4_mgt_refclk_n), + .CEB (1'b0), + .O (fmc_qsfp_4_mgt_refclk), + .ODIV2 () +); + +wire fmc_qsfp_4_qpll0lock; +wire fmc_qsfp_4_qpll0outclk; +wire fmc_qsfp_4_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +fmc_qsfp_4_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(fmc_qsfp_4_mgt_refclk), + .xcvr_qpll0lock_out(fmc_qsfp_4_qpll0lock), + .xcvr_qpll0outclk_out(fmc_qsfp_4_qpll0outclk), + .xcvr_qpll0outrefclk_out(fmc_qsfp_4_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(fmc_qsfp_4_tx_p[0]), + .xcvr_txn(fmc_qsfp_4_tx_n[0]), + .xcvr_rxp(fmc_qsfp_4_rx_p[0]), + .xcvr_rxn(fmc_qsfp_4_rx_n[0]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_4_tx_clk_1_int), + .phy_tx_rst(fmc_qsfp_4_tx_rst_1_int), + .phy_xgmii_txd(fmc_qsfp_4_txd_1_int), + .phy_xgmii_txc(fmc_qsfp_4_txc_1_int), + .phy_rx_clk(fmc_qsfp_4_rx_clk_1_int), + .phy_rx_rst(fmc_qsfp_4_rx_rst_1_int), + .phy_xgmii_rxd(fmc_qsfp_4_rxd_1_int), + .phy_xgmii_rxc(fmc_qsfp_4_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_4_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_4_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_4_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_4_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_4_tx_p[1]), + .xcvr_txn(fmc_qsfp_4_tx_n[1]), + .xcvr_rxp(fmc_qsfp_4_rx_p[1]), + .xcvr_rxn(fmc_qsfp_4_rx_n[1]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_4_tx_clk_2_int), + .phy_tx_rst(fmc_qsfp_4_tx_rst_2_int), + .phy_xgmii_txd(fmc_qsfp_4_txd_2_int), + .phy_xgmii_txc(fmc_qsfp_4_txc_2_int), + .phy_rx_clk(fmc_qsfp_4_rx_clk_2_int), + .phy_rx_rst(fmc_qsfp_4_rx_rst_2_int), + .phy_xgmii_rxd(fmc_qsfp_4_rxd_2_int), + .phy_xgmii_rxc(fmc_qsfp_4_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_4_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_4_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_4_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_4_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_4_tx_p[2]), + .xcvr_txn(fmc_qsfp_4_tx_n[2]), + .xcvr_rxp(fmc_qsfp_4_rx_p[2]), + .xcvr_rxn(fmc_qsfp_4_rx_n[2]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_4_tx_clk_3_int), + .phy_tx_rst(fmc_qsfp_4_tx_rst_3_int), + .phy_xgmii_txd(fmc_qsfp_4_txd_3_int), + .phy_xgmii_txc(fmc_qsfp_4_txc_3_int), + .phy_rx_clk(fmc_qsfp_4_rx_clk_3_int), + .phy_rx_rst(fmc_qsfp_4_rx_rst_3_int), + .phy_xgmii_rxd(fmc_qsfp_4_rxd_3_int), + .phy_xgmii_rxc(fmc_qsfp_4_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_4_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_4_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_4_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_4_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_4_tx_p[3]), + .xcvr_txn(fmc_qsfp_4_tx_n[3]), + .xcvr_rxp(fmc_qsfp_4_rx_p[3]), + .xcvr_rxn(fmc_qsfp_4_rx_n[3]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_4_tx_clk_4_int), + .phy_tx_rst(fmc_qsfp_4_tx_rst_4_int), + .phy_xgmii_txd(fmc_qsfp_4_txd_4_int), + .phy_xgmii_txc(fmc_qsfp_4_txc_4_int), + .phy_rx_clk(fmc_qsfp_4_rx_clk_4_int), + .phy_rx_rst(fmc_qsfp_4_rx_rst_4_int), + .phy_xgmii_rxd(fmc_qsfp_4_rxd_4_int), + .phy_xgmii_rxc(fmc_qsfp_4_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_4_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// FMC QSFP 5 +assign fmc_qsfp_5_modsell = 1'b1; +assign fmc_qsfp_5_resetl = 1'b1; +assign fmc_qsfp_5_lpmode = 1'b0; + +wire fmc_qsfp_5_tx_clk_1_int; +wire fmc_qsfp_5_tx_rst_1_int; +wire [63:0] fmc_qsfp_5_txd_1_int; +wire [7:0] fmc_qsfp_5_txc_1_int; +wire fmc_qsfp_5_rx_clk_1_int; +wire fmc_qsfp_5_rx_rst_1_int; +wire [63:0] fmc_qsfp_5_rxd_1_int; +wire [7:0] fmc_qsfp_5_rxc_1_int; +wire fmc_qsfp_5_tx_clk_2_int; +wire fmc_qsfp_5_tx_rst_2_int; +wire [63:0] fmc_qsfp_5_txd_2_int; +wire [7:0] fmc_qsfp_5_txc_2_int; +wire fmc_qsfp_5_rx_clk_2_int; +wire fmc_qsfp_5_rx_rst_2_int; +wire [63:0] fmc_qsfp_5_rxd_2_int; +wire [7:0] fmc_qsfp_5_rxc_2_int; +wire fmc_qsfp_5_tx_clk_3_int; +wire fmc_qsfp_5_tx_rst_3_int; +wire [63:0] fmc_qsfp_5_txd_3_int; +wire [7:0] fmc_qsfp_5_txc_3_int; +wire fmc_qsfp_5_rx_clk_3_int; +wire fmc_qsfp_5_rx_rst_3_int; +wire [63:0] fmc_qsfp_5_rxd_3_int; +wire [7:0] fmc_qsfp_5_rxc_3_int; +wire fmc_qsfp_5_tx_clk_4_int; +wire fmc_qsfp_5_tx_rst_4_int; +wire [63:0] fmc_qsfp_5_txd_4_int; +wire [7:0] fmc_qsfp_5_txc_4_int; +wire fmc_qsfp_5_rx_clk_4_int; +wire fmc_qsfp_5_rx_rst_4_int; +wire [63:0] fmc_qsfp_5_rxd_4_int; +wire [7:0] fmc_qsfp_5_rxc_4_int; + +wire fmc_qsfp_5_rx_block_lock_1; +wire fmc_qsfp_5_rx_block_lock_2; +wire fmc_qsfp_5_rx_block_lock_3; +wire fmc_qsfp_5_rx_block_lock_4; + +wire fmc_qsfp_5_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_fmc_qsfp_5_mgt_refclk_inst ( + .I (fmc_qsfp_5_mgt_refclk_p), + .IB (fmc_qsfp_5_mgt_refclk_n), + .CEB (1'b0), + .O (fmc_qsfp_5_mgt_refclk), + .ODIV2 () +); + +wire fmc_qsfp_5_qpll0lock; +wire fmc_qsfp_5_qpll0outclk; +wire fmc_qsfp_5_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +fmc_qsfp_5_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(fmc_qsfp_5_mgt_refclk), + .xcvr_qpll0lock_out(fmc_qsfp_5_qpll0lock), + .xcvr_qpll0outclk_out(fmc_qsfp_5_qpll0outclk), + .xcvr_qpll0outrefclk_out(fmc_qsfp_5_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(fmc_qsfp_5_tx_p[0]), + .xcvr_txn(fmc_qsfp_5_tx_n[0]), + .xcvr_rxp(fmc_qsfp_5_rx_p[0]), + .xcvr_rxn(fmc_qsfp_5_rx_n[0]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_5_tx_clk_1_int), + .phy_tx_rst(fmc_qsfp_5_tx_rst_1_int), + .phy_xgmii_txd(fmc_qsfp_5_txd_1_int), + .phy_xgmii_txc(fmc_qsfp_5_txc_1_int), + .phy_rx_clk(fmc_qsfp_5_rx_clk_1_int), + .phy_rx_rst(fmc_qsfp_5_rx_rst_1_int), + .phy_xgmii_rxd(fmc_qsfp_5_rxd_1_int), + .phy_xgmii_rxc(fmc_qsfp_5_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_5_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_5_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_5_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_5_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_5_tx_p[1]), + .xcvr_txn(fmc_qsfp_5_tx_n[1]), + .xcvr_rxp(fmc_qsfp_5_rx_p[1]), + .xcvr_rxn(fmc_qsfp_5_rx_n[1]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_5_tx_clk_2_int), + .phy_tx_rst(fmc_qsfp_5_tx_rst_2_int), + .phy_xgmii_txd(fmc_qsfp_5_txd_2_int), + .phy_xgmii_txc(fmc_qsfp_5_txc_2_int), + .phy_rx_clk(fmc_qsfp_5_rx_clk_2_int), + .phy_rx_rst(fmc_qsfp_5_rx_rst_2_int), + .phy_xgmii_rxd(fmc_qsfp_5_rxd_2_int), + .phy_xgmii_rxc(fmc_qsfp_5_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_5_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_5_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_5_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_5_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_5_tx_p[2]), + .xcvr_txn(fmc_qsfp_5_tx_n[2]), + .xcvr_rxp(fmc_qsfp_5_rx_p[2]), + .xcvr_rxn(fmc_qsfp_5_rx_n[2]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_5_tx_clk_3_int), + .phy_tx_rst(fmc_qsfp_5_tx_rst_3_int), + .phy_xgmii_txd(fmc_qsfp_5_txd_3_int), + .phy_xgmii_txc(fmc_qsfp_5_txc_3_int), + .phy_rx_clk(fmc_qsfp_5_rx_clk_3_int), + .phy_rx_rst(fmc_qsfp_5_rx_rst_3_int), + .phy_xgmii_rxd(fmc_qsfp_5_rxd_3_int), + .phy_xgmii_rxc(fmc_qsfp_5_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_5_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_5_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_5_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_5_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_5_tx_p[3]), + .xcvr_txn(fmc_qsfp_5_tx_n[3]), + .xcvr_rxp(fmc_qsfp_5_rx_p[3]), + .xcvr_rxn(fmc_qsfp_5_rx_n[3]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_5_tx_clk_4_int), + .phy_tx_rst(fmc_qsfp_5_tx_rst_4_int), + .phy_xgmii_txd(fmc_qsfp_5_txd_4_int), + .phy_xgmii_txc(fmc_qsfp_5_txc_4_int), + .phy_rx_clk(fmc_qsfp_5_rx_clk_4_int), + .phy_rx_rst(fmc_qsfp_5_rx_rst_4_int), + .phy_xgmii_rxd(fmc_qsfp_5_rxd_4_int), + .phy_xgmii_rxc(fmc_qsfp_5_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_5_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// FMC QSFP 6 +assign fmc_qsfp_6_modsell = 1'b1; +assign fmc_qsfp_6_resetl = 1'b1; +assign fmc_qsfp_6_lpmode = 1'b0; + +wire fmc_qsfp_6_tx_clk_1_int; +wire fmc_qsfp_6_tx_rst_1_int; +wire [63:0] fmc_qsfp_6_txd_1_int; +wire [7:0] fmc_qsfp_6_txc_1_int; +wire fmc_qsfp_6_rx_clk_1_int; +wire fmc_qsfp_6_rx_rst_1_int; +wire [63:0] fmc_qsfp_6_rxd_1_int; +wire [7:0] fmc_qsfp_6_rxc_1_int; +wire fmc_qsfp_6_tx_clk_2_int; +wire fmc_qsfp_6_tx_rst_2_int; +wire [63:0] fmc_qsfp_6_txd_2_int; +wire [7:0] fmc_qsfp_6_txc_2_int; +wire fmc_qsfp_6_rx_clk_2_int; +wire fmc_qsfp_6_rx_rst_2_int; +wire [63:0] fmc_qsfp_6_rxd_2_int; +wire [7:0] fmc_qsfp_6_rxc_2_int; +wire fmc_qsfp_6_tx_clk_3_int; +wire fmc_qsfp_6_tx_rst_3_int; +wire [63:0] fmc_qsfp_6_txd_3_int; +wire [7:0] fmc_qsfp_6_txc_3_int; +wire fmc_qsfp_6_rx_clk_3_int; +wire fmc_qsfp_6_rx_rst_3_int; +wire [63:0] fmc_qsfp_6_rxd_3_int; +wire [7:0] fmc_qsfp_6_rxc_3_int; +wire fmc_qsfp_6_tx_clk_4_int; +wire fmc_qsfp_6_tx_rst_4_int; +wire [63:0] fmc_qsfp_6_txd_4_int; +wire [7:0] fmc_qsfp_6_txc_4_int; +wire fmc_qsfp_6_rx_clk_4_int; +wire fmc_qsfp_6_rx_rst_4_int; +wire [63:0] fmc_qsfp_6_rxd_4_int; +wire [7:0] fmc_qsfp_6_rxc_4_int; + +wire fmc_qsfp_6_rx_block_lock_1; +wire fmc_qsfp_6_rx_block_lock_2; +wire fmc_qsfp_6_rx_block_lock_3; +wire fmc_qsfp_6_rx_block_lock_4; + +wire fmc_qsfp_6_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_fmc_qsfp_6_mgt_refclk_inst ( + .I (fmc_qsfp_6_mgt_refclk_p), + .IB (fmc_qsfp_6_mgt_refclk_n), + .CEB (1'b0), + .O (fmc_qsfp_6_mgt_refclk), + .ODIV2 () +); + +wire fmc_qsfp_6_qpll0lock; +wire fmc_qsfp_6_qpll0outclk; +wire fmc_qsfp_6_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +fmc_qsfp_6_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(fmc_qsfp_6_mgt_refclk), + .xcvr_qpll0lock_out(fmc_qsfp_6_qpll0lock), + .xcvr_qpll0outclk_out(fmc_qsfp_6_qpll0outclk), + .xcvr_qpll0outrefclk_out(fmc_qsfp_6_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(fmc_qsfp_6_tx_p[0]), + .xcvr_txn(fmc_qsfp_6_tx_n[0]), + .xcvr_rxp(fmc_qsfp_6_rx_p[0]), + .xcvr_rxn(fmc_qsfp_6_rx_n[0]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_6_tx_clk_1_int), + .phy_tx_rst(fmc_qsfp_6_tx_rst_1_int), + .phy_xgmii_txd(fmc_qsfp_6_txd_1_int), + .phy_xgmii_txc(fmc_qsfp_6_txc_1_int), + .phy_rx_clk(fmc_qsfp_6_rx_clk_1_int), + .phy_rx_rst(fmc_qsfp_6_rx_rst_1_int), + .phy_xgmii_rxd(fmc_qsfp_6_rxd_1_int), + .phy_xgmii_rxc(fmc_qsfp_6_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_6_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_6_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_6_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_6_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_6_tx_p[1]), + .xcvr_txn(fmc_qsfp_6_tx_n[1]), + .xcvr_rxp(fmc_qsfp_6_rx_p[1]), + .xcvr_rxn(fmc_qsfp_6_rx_n[1]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_6_tx_clk_2_int), + .phy_tx_rst(fmc_qsfp_6_tx_rst_2_int), + .phy_xgmii_txd(fmc_qsfp_6_txd_2_int), + .phy_xgmii_txc(fmc_qsfp_6_txc_2_int), + .phy_rx_clk(fmc_qsfp_6_rx_clk_2_int), + .phy_rx_rst(fmc_qsfp_6_rx_rst_2_int), + .phy_xgmii_rxd(fmc_qsfp_6_rxd_2_int), + .phy_xgmii_rxc(fmc_qsfp_6_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_6_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_6_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_6_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_6_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_6_tx_p[2]), + .xcvr_txn(fmc_qsfp_6_tx_n[2]), + .xcvr_rxp(fmc_qsfp_6_rx_p[2]), + .xcvr_rxn(fmc_qsfp_6_rx_n[2]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_6_tx_clk_3_int), + .phy_tx_rst(fmc_qsfp_6_tx_rst_3_int), + .phy_xgmii_txd(fmc_qsfp_6_txd_3_int), + .phy_xgmii_txc(fmc_qsfp_6_txc_3_int), + .phy_rx_clk(fmc_qsfp_6_rx_clk_3_int), + .phy_rx_rst(fmc_qsfp_6_rx_rst_3_int), + .phy_xgmii_rxd(fmc_qsfp_6_rxd_3_int), + .phy_xgmii_rxc(fmc_qsfp_6_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmc_qsfp_6_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmc_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmc_qsfp_6_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmc_qsfp_6_qpll0outclk), + .xcvr_qpll0refclk_in(fmc_qsfp_6_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmc_qsfp_6_tx_p[3]), + .xcvr_txn(fmc_qsfp_6_tx_n[3]), + .xcvr_rxp(fmc_qsfp_6_rx_p[3]), + .xcvr_rxn(fmc_qsfp_6_rx_n[3]), + + // PHY connections + .phy_tx_clk(fmc_qsfp_6_tx_clk_4_int), + .phy_tx_rst(fmc_qsfp_6_tx_rst_4_int), + .phy_xgmii_txd(fmc_qsfp_6_txd_4_int), + .phy_xgmii_txc(fmc_qsfp_6_txc_4_int), + .phy_rx_clk(fmc_qsfp_6_rx_clk_4_int), + .phy_rx_rst(fmc_qsfp_6_rx_rst_4_int), + .phy_xgmii_rxd(fmc_qsfp_6_rxd_4_int), + .phy_xgmii_rxc(fmc_qsfp_6_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmc_qsfp_6_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +fpga_core +core_inst ( + /* + * Clock: 156MHz + * Synchronous reset + */ + .clk(clk_156mhz_int), + .rst(rst_156mhz_int), + /* + * GPIO + */ + .btn(btn_int), + .sw(sw_int), + .led(led), + /* + * UART: 115200 bps, 8N1 + */ + .uart_rxd(uart_rxd), + .uart_txd(uart_txd_int), + .uart_rts(uart_rts_int), + .uart_cts(uart_cts), + .uart_rst_n(uart_rst_n), + .uart_suspend_n(uart_suspend_n), + /* + * Ethernet: QSFP28 + */ + .qsfp_1_tx_clk_1(qsfp_1_tx_clk_1_int), + .qsfp_1_tx_rst_1(qsfp_1_tx_rst_1_int), + .qsfp_1_txd_1(qsfp_1_txd_1_int), + .qsfp_1_txc_1(qsfp_1_txc_1_int), + .qsfp_1_rx_clk_1(qsfp_1_rx_clk_1_int), + .qsfp_1_rx_rst_1(qsfp_1_rx_rst_1_int), + .qsfp_1_rxd_1(qsfp_1_rxd_1_int), + .qsfp_1_rxc_1(qsfp_1_rxc_1_int), + .qsfp_1_tx_clk_2(qsfp_1_tx_clk_2_int), + .qsfp_1_tx_rst_2(qsfp_1_tx_rst_2_int), + .qsfp_1_txd_2(qsfp_1_txd_2_int), + .qsfp_1_txc_2(qsfp_1_txc_2_int), + .qsfp_1_rx_clk_2(qsfp_1_rx_clk_2_int), + .qsfp_1_rx_rst_2(qsfp_1_rx_rst_2_int), + .qsfp_1_rxd_2(qsfp_1_rxd_2_int), + .qsfp_1_rxc_2(qsfp_1_rxc_2_int), + .qsfp_1_tx_clk_3(qsfp_1_tx_clk_3_int), + .qsfp_1_tx_rst_3(qsfp_1_tx_rst_3_int), + .qsfp_1_txd_3(qsfp_1_txd_3_int), + .qsfp_1_txc_3(qsfp_1_txc_3_int), + .qsfp_1_rx_clk_3(qsfp_1_rx_clk_3_int), + .qsfp_1_rx_rst_3(qsfp_1_rx_rst_3_int), + .qsfp_1_rxd_3(qsfp_1_rxd_3_int), + .qsfp_1_rxc_3(qsfp_1_rxc_3_int), + .qsfp_1_tx_clk_4(qsfp_1_tx_clk_4_int), + .qsfp_1_tx_rst_4(qsfp_1_tx_rst_4_int), + .qsfp_1_txd_4(qsfp_1_txd_4_int), + .qsfp_1_txc_4(qsfp_1_txc_4_int), + .qsfp_1_rx_clk_4(qsfp_1_rx_clk_4_int), + .qsfp_1_rx_rst_4(qsfp_1_rx_rst_4_int), + .qsfp_1_rxd_4(qsfp_1_rxd_4_int), + .qsfp_1_rxc_4(qsfp_1_rxc_4_int), + .qsfp_2_tx_clk_1(qsfp_2_tx_clk_1_int), + .qsfp_2_tx_rst_1(qsfp_2_tx_rst_1_int), + .qsfp_2_txd_1(qsfp_2_txd_1_int), + .qsfp_2_txc_1(qsfp_2_txc_1_int), + .qsfp_2_rx_clk_1(qsfp_2_rx_clk_1_int), + .qsfp_2_rx_rst_1(qsfp_2_rx_rst_1_int), + .qsfp_2_rxd_1(qsfp_2_rxd_1_int), + .qsfp_2_rxc_1(qsfp_2_rxc_1_int), + .qsfp_2_tx_clk_2(qsfp_2_tx_clk_2_int), + .qsfp_2_tx_rst_2(qsfp_2_tx_rst_2_int), + .qsfp_2_txd_2(qsfp_2_txd_2_int), + .qsfp_2_txc_2(qsfp_2_txc_2_int), + .qsfp_2_rx_clk_2(qsfp_2_rx_clk_2_int), + .qsfp_2_rx_rst_2(qsfp_2_rx_rst_2_int), + .qsfp_2_rxd_2(qsfp_2_rxd_2_int), + .qsfp_2_rxc_2(qsfp_2_rxc_2_int), + .qsfp_2_tx_clk_3(qsfp_2_tx_clk_3_int), + .qsfp_2_tx_rst_3(qsfp_2_tx_rst_3_int), + .qsfp_2_txd_3(qsfp_2_txd_3_int), + .qsfp_2_txc_3(qsfp_2_txc_3_int), + .qsfp_2_rx_clk_3(qsfp_2_rx_clk_3_int), + .qsfp_2_rx_rst_3(qsfp_2_rx_rst_3_int), + .qsfp_2_rxd_3(qsfp_2_rxd_3_int), + .qsfp_2_rxc_3(qsfp_2_rxc_3_int), + .qsfp_2_tx_clk_4(qsfp_2_tx_clk_4_int), + .qsfp_2_tx_rst_4(qsfp_2_tx_rst_4_int), + .qsfp_2_txd_4(qsfp_2_txd_4_int), + .qsfp_2_txc_4(qsfp_2_txc_4_int), + .qsfp_2_rx_clk_4(qsfp_2_rx_clk_4_int), + .qsfp_2_rx_rst_4(qsfp_2_rx_rst_4_int), + .qsfp_2_rxd_4(qsfp_2_rxd_4_int), + .qsfp_2_rxc_4(qsfp_2_rxc_4_int), + .qsfp_3_tx_clk_1(qsfp_3_tx_clk_1_int), + .qsfp_3_tx_rst_1(qsfp_3_tx_rst_1_int), + .qsfp_3_txd_1(qsfp_3_txd_1_int), + .qsfp_3_txc_1(qsfp_3_txc_1_int), + .qsfp_3_rx_clk_1(qsfp_3_rx_clk_1_int), + .qsfp_3_rx_rst_1(qsfp_3_rx_rst_1_int), + .qsfp_3_rxd_1(qsfp_3_rxd_1_int), + .qsfp_3_rxc_1(qsfp_3_rxc_1_int), + .qsfp_3_tx_clk_2(qsfp_3_tx_clk_2_int), + .qsfp_3_tx_rst_2(qsfp_3_tx_rst_2_int), + .qsfp_3_txd_2(qsfp_3_txd_2_int), + .qsfp_3_txc_2(qsfp_3_txc_2_int), + .qsfp_3_rx_clk_2(qsfp_3_rx_clk_2_int), + .qsfp_3_rx_rst_2(qsfp_3_rx_rst_2_int), + .qsfp_3_rxd_2(qsfp_3_rxd_2_int), + .qsfp_3_rxc_2(qsfp_3_rxc_2_int), + .qsfp_3_tx_clk_3(qsfp_3_tx_clk_3_int), + .qsfp_3_tx_rst_3(qsfp_3_tx_rst_3_int), + .qsfp_3_txd_3(qsfp_3_txd_3_int), + .qsfp_3_txc_3(qsfp_3_txc_3_int), + .qsfp_3_rx_clk_3(qsfp_3_rx_clk_3_int), + .qsfp_3_rx_rst_3(qsfp_3_rx_rst_3_int), + .qsfp_3_rxd_3(qsfp_3_rxd_3_int), + .qsfp_3_rxc_3(qsfp_3_rxc_3_int), + .qsfp_3_tx_clk_4(qsfp_3_tx_clk_4_int), + .qsfp_3_tx_rst_4(qsfp_3_tx_rst_4_int), + .qsfp_3_txd_4(qsfp_3_txd_4_int), + .qsfp_3_txc_4(qsfp_3_txc_4_int), + .qsfp_3_rx_clk_4(qsfp_3_rx_clk_4_int), + .qsfp_3_rx_rst_4(qsfp_3_rx_rst_4_int), + .qsfp_3_rxd_4(qsfp_3_rxd_4_int), + .qsfp_3_rxc_4(qsfp_3_rxc_4_int), + .qsfp_4_tx_clk_1(qsfp_4_tx_clk_1_int), + .qsfp_4_tx_rst_1(qsfp_4_tx_rst_1_int), + .qsfp_4_txd_1(qsfp_4_txd_1_int), + .qsfp_4_txc_1(qsfp_4_txc_1_int), + .qsfp_4_rx_clk_1(qsfp_4_rx_clk_1_int), + .qsfp_4_rx_rst_1(qsfp_4_rx_rst_1_int), + .qsfp_4_rxd_1(qsfp_4_rxd_1_int), + .qsfp_4_rxc_1(qsfp_4_rxc_1_int), + .qsfp_4_tx_clk_2(qsfp_4_tx_clk_2_int), + .qsfp_4_tx_rst_2(qsfp_4_tx_rst_2_int), + .qsfp_4_txd_2(qsfp_4_txd_2_int), + .qsfp_4_txc_2(qsfp_4_txc_2_int), + .qsfp_4_rx_clk_2(qsfp_4_rx_clk_2_int), + .qsfp_4_rx_rst_2(qsfp_4_rx_rst_2_int), + .qsfp_4_rxd_2(qsfp_4_rxd_2_int), + .qsfp_4_rxc_2(qsfp_4_rxc_2_int), + .qsfp_4_tx_clk_3(qsfp_4_tx_clk_3_int), + .qsfp_4_tx_rst_3(qsfp_4_tx_rst_3_int), + .qsfp_4_txd_3(qsfp_4_txd_3_int), + .qsfp_4_txc_3(qsfp_4_txc_3_int), + .qsfp_4_rx_clk_3(qsfp_4_rx_clk_3_int), + .qsfp_4_rx_rst_3(qsfp_4_rx_rst_3_int), + .qsfp_4_rxd_3(qsfp_4_rxd_3_int), + .qsfp_4_rxc_3(qsfp_4_rxc_3_int), + .qsfp_4_tx_clk_4(qsfp_4_tx_clk_4_int), + .qsfp_4_tx_rst_4(qsfp_4_tx_rst_4_int), + .qsfp_4_txd_4(qsfp_4_txd_4_int), + .qsfp_4_txc_4(qsfp_4_txc_4_int), + .qsfp_4_rx_clk_4(qsfp_4_rx_clk_4_int), + .qsfp_4_rx_rst_4(qsfp_4_rx_rst_4_int), + .qsfp_4_rxd_4(qsfp_4_rxd_4_int), + .qsfp_4_rxc_4(qsfp_4_rxc_4_int), + .qsfp_5_tx_clk_1(qsfp_5_tx_clk_1_int), + .qsfp_5_tx_rst_1(qsfp_5_tx_rst_1_int), + .qsfp_5_txd_1(qsfp_5_txd_1_int), + .qsfp_5_txc_1(qsfp_5_txc_1_int), + .qsfp_5_rx_clk_1(qsfp_5_rx_clk_1_int), + .qsfp_5_rx_rst_1(qsfp_5_rx_rst_1_int), + .qsfp_5_rxd_1(qsfp_5_rxd_1_int), + .qsfp_5_rxc_1(qsfp_5_rxc_1_int), + .qsfp_5_tx_clk_2(qsfp_5_tx_clk_2_int), + .qsfp_5_tx_rst_2(qsfp_5_tx_rst_2_int), + .qsfp_5_txd_2(qsfp_5_txd_2_int), + .qsfp_5_txc_2(qsfp_5_txc_2_int), + .qsfp_5_rx_clk_2(qsfp_5_rx_clk_2_int), + .qsfp_5_rx_rst_2(qsfp_5_rx_rst_2_int), + .qsfp_5_rxd_2(qsfp_5_rxd_2_int), + .qsfp_5_rxc_2(qsfp_5_rxc_2_int), + .qsfp_5_tx_clk_3(qsfp_5_tx_clk_3_int), + .qsfp_5_tx_rst_3(qsfp_5_tx_rst_3_int), + .qsfp_5_txd_3(qsfp_5_txd_3_int), + .qsfp_5_txc_3(qsfp_5_txc_3_int), + .qsfp_5_rx_clk_3(qsfp_5_rx_clk_3_int), + .qsfp_5_rx_rst_3(qsfp_5_rx_rst_3_int), + .qsfp_5_rxd_3(qsfp_5_rxd_3_int), + .qsfp_5_rxc_3(qsfp_5_rxc_3_int), + .qsfp_5_tx_clk_4(qsfp_5_tx_clk_4_int), + .qsfp_5_tx_rst_4(qsfp_5_tx_rst_4_int), + .qsfp_5_txd_4(qsfp_5_txd_4_int), + .qsfp_5_txc_4(qsfp_5_txc_4_int), + .qsfp_5_rx_clk_4(qsfp_5_rx_clk_4_int), + .qsfp_5_rx_rst_4(qsfp_5_rx_rst_4_int), + .qsfp_5_rxd_4(qsfp_5_rxd_4_int), + .qsfp_5_rxc_4(qsfp_5_rxc_4_int), + .qsfp_6_tx_clk_1(qsfp_6_tx_clk_1_int), + .qsfp_6_tx_rst_1(qsfp_6_tx_rst_1_int), + .qsfp_6_txd_1(qsfp_6_txd_1_int), + .qsfp_6_txc_1(qsfp_6_txc_1_int), + .qsfp_6_rx_clk_1(qsfp_6_rx_clk_1_int), + .qsfp_6_rx_rst_1(qsfp_6_rx_rst_1_int), + .qsfp_6_rxd_1(qsfp_6_rxd_1_int), + .qsfp_6_rxc_1(qsfp_6_rxc_1_int), + .qsfp_6_tx_clk_2(qsfp_6_tx_clk_2_int), + .qsfp_6_tx_rst_2(qsfp_6_tx_rst_2_int), + .qsfp_6_txd_2(qsfp_6_txd_2_int), + .qsfp_6_txc_2(qsfp_6_txc_2_int), + .qsfp_6_rx_clk_2(qsfp_6_rx_clk_2_int), + .qsfp_6_rx_rst_2(qsfp_6_rx_rst_2_int), + .qsfp_6_rxd_2(qsfp_6_rxd_2_int), + .qsfp_6_rxc_2(qsfp_6_rxc_2_int), + .qsfp_6_tx_clk_3(qsfp_6_tx_clk_3_int), + .qsfp_6_tx_rst_3(qsfp_6_tx_rst_3_int), + .qsfp_6_txd_3(qsfp_6_txd_3_int), + .qsfp_6_txc_3(qsfp_6_txc_3_int), + .qsfp_6_rx_clk_3(qsfp_6_rx_clk_3_int), + .qsfp_6_rx_rst_3(qsfp_6_rx_rst_3_int), + .qsfp_6_rxd_3(qsfp_6_rxd_3_int), + .qsfp_6_rxc_3(qsfp_6_rxc_3_int), + .qsfp_6_tx_clk_4(qsfp_6_tx_clk_4_int), + .qsfp_6_tx_rst_4(qsfp_6_tx_rst_4_int), + .qsfp_6_txd_4(qsfp_6_txd_4_int), + .qsfp_6_txc_4(qsfp_6_txc_4_int), + .qsfp_6_rx_clk_4(qsfp_6_rx_clk_4_int), + .qsfp_6_rx_rst_4(qsfp_6_rx_rst_4_int), + .qsfp_6_rxd_4(qsfp_6_rxd_4_int), + .qsfp_6_rxc_4(qsfp_6_rxc_4_int), + .qsfp_7_tx_clk_1(qsfp_7_tx_clk_1_int), + .qsfp_7_tx_rst_1(qsfp_7_tx_rst_1_int), + .qsfp_7_txd_1(qsfp_7_txd_1_int), + .qsfp_7_txc_1(qsfp_7_txc_1_int), + .qsfp_7_rx_clk_1(qsfp_7_rx_clk_1_int), + .qsfp_7_rx_rst_1(qsfp_7_rx_rst_1_int), + .qsfp_7_rxd_1(qsfp_7_rxd_1_int), + .qsfp_7_rxc_1(qsfp_7_rxc_1_int), + .qsfp_7_tx_clk_2(qsfp_7_tx_clk_2_int), + .qsfp_7_tx_rst_2(qsfp_7_tx_rst_2_int), + .qsfp_7_txd_2(qsfp_7_txd_2_int), + .qsfp_7_txc_2(qsfp_7_txc_2_int), + .qsfp_7_rx_clk_2(qsfp_7_rx_clk_2_int), + .qsfp_7_rx_rst_2(qsfp_7_rx_rst_2_int), + .qsfp_7_rxd_2(qsfp_7_rxd_2_int), + .qsfp_7_rxc_2(qsfp_7_rxc_2_int), + .qsfp_7_tx_clk_3(qsfp_7_tx_clk_3_int), + .qsfp_7_tx_rst_3(qsfp_7_tx_rst_3_int), + .qsfp_7_txd_3(qsfp_7_txd_3_int), + .qsfp_7_txc_3(qsfp_7_txc_3_int), + .qsfp_7_rx_clk_3(qsfp_7_rx_clk_3_int), + .qsfp_7_rx_rst_3(qsfp_7_rx_rst_3_int), + .qsfp_7_rxd_3(qsfp_7_rxd_3_int), + .qsfp_7_rxc_3(qsfp_7_rxc_3_int), + .qsfp_7_tx_clk_4(qsfp_7_tx_clk_4_int), + .qsfp_7_tx_rst_4(qsfp_7_tx_rst_4_int), + .qsfp_7_txd_4(qsfp_7_txd_4_int), + .qsfp_7_txc_4(qsfp_7_txc_4_int), + .qsfp_7_rx_clk_4(qsfp_7_rx_clk_4_int), + .qsfp_7_rx_rst_4(qsfp_7_rx_rst_4_int), + .qsfp_7_rxd_4(qsfp_7_rxd_4_int), + .qsfp_7_rxc_4(qsfp_7_rxc_4_int), + .qsfp_8_tx_clk_1(qsfp_8_tx_clk_1_int), + .qsfp_8_tx_rst_1(qsfp_8_tx_rst_1_int), + .qsfp_8_txd_1(qsfp_8_txd_1_int), + .qsfp_8_txc_1(qsfp_8_txc_1_int), + .qsfp_8_rx_clk_1(qsfp_8_rx_clk_1_int), + .qsfp_8_rx_rst_1(qsfp_8_rx_rst_1_int), + .qsfp_8_rxd_1(qsfp_8_rxd_1_int), + .qsfp_8_rxc_1(qsfp_8_rxc_1_int), + .qsfp_8_tx_clk_2(qsfp_8_tx_clk_2_int), + .qsfp_8_tx_rst_2(qsfp_8_tx_rst_2_int), + .qsfp_8_txd_2(qsfp_8_txd_2_int), + .qsfp_8_txc_2(qsfp_8_txc_2_int), + .qsfp_8_rx_clk_2(qsfp_8_rx_clk_2_int), + .qsfp_8_rx_rst_2(qsfp_8_rx_rst_2_int), + .qsfp_8_rxd_2(qsfp_8_rxd_2_int), + .qsfp_8_rxc_2(qsfp_8_rxc_2_int), + .qsfp_8_tx_clk_3(qsfp_8_tx_clk_3_int), + .qsfp_8_tx_rst_3(qsfp_8_tx_rst_3_int), + .qsfp_8_txd_3(qsfp_8_txd_3_int), + .qsfp_8_txc_3(qsfp_8_txc_3_int), + .qsfp_8_rx_clk_3(qsfp_8_rx_clk_3_int), + .qsfp_8_rx_rst_3(qsfp_8_rx_rst_3_int), + .qsfp_8_rxd_3(qsfp_8_rxd_3_int), + .qsfp_8_rxc_3(qsfp_8_rxc_3_int), + .qsfp_8_tx_clk_4(qsfp_8_tx_clk_4_int), + .qsfp_8_tx_rst_4(qsfp_8_tx_rst_4_int), + .qsfp_8_txd_4(qsfp_8_txd_4_int), + .qsfp_8_txc_4(qsfp_8_txc_4_int), + .qsfp_8_rx_clk_4(qsfp_8_rx_clk_4_int), + .qsfp_8_rx_rst_4(qsfp_8_rx_rst_4_int), + .qsfp_8_rxd_4(qsfp_8_rxd_4_int), + .qsfp_8_rxc_4(qsfp_8_rxc_4_int), + .qsfp_9_tx_clk_1(qsfp_9_tx_clk_1_int), + .qsfp_9_tx_rst_1(qsfp_9_tx_rst_1_int), + .qsfp_9_txd_1(qsfp_9_txd_1_int), + .qsfp_9_txc_1(qsfp_9_txc_1_int), + .qsfp_9_rx_clk_1(qsfp_9_rx_clk_1_int), + .qsfp_9_rx_rst_1(qsfp_9_rx_rst_1_int), + .qsfp_9_rxd_1(qsfp_9_rxd_1_int), + .qsfp_9_rxc_1(qsfp_9_rxc_1_int), + .qsfp_9_tx_clk_2(qsfp_9_tx_clk_2_int), + .qsfp_9_tx_rst_2(qsfp_9_tx_rst_2_int), + .qsfp_9_txd_2(qsfp_9_txd_2_int), + .qsfp_9_txc_2(qsfp_9_txc_2_int), + .qsfp_9_rx_clk_2(qsfp_9_rx_clk_2_int), + .qsfp_9_rx_rst_2(qsfp_9_rx_rst_2_int), + .qsfp_9_rxd_2(qsfp_9_rxd_2_int), + .qsfp_9_rxc_2(qsfp_9_rxc_2_int), + .qsfp_9_tx_clk_3(qsfp_9_tx_clk_3_int), + .qsfp_9_tx_rst_3(qsfp_9_tx_rst_3_int), + .qsfp_9_txd_3(qsfp_9_txd_3_int), + .qsfp_9_txc_3(qsfp_9_txc_3_int), + .qsfp_9_rx_clk_3(qsfp_9_rx_clk_3_int), + .qsfp_9_rx_rst_3(qsfp_9_rx_rst_3_int), + .qsfp_9_rxd_3(qsfp_9_rxd_3_int), + .qsfp_9_rxc_3(qsfp_9_rxc_3_int), + .qsfp_9_tx_clk_4(qsfp_9_tx_clk_4_int), + .qsfp_9_tx_rst_4(qsfp_9_tx_rst_4_int), + .qsfp_9_txd_4(qsfp_9_txd_4_int), + .qsfp_9_txc_4(qsfp_9_txc_4_int), + .qsfp_9_rx_clk_4(qsfp_9_rx_clk_4_int), + .qsfp_9_rx_rst_4(qsfp_9_rx_rst_4_int), + .qsfp_9_rxd_4(qsfp_9_rxd_4_int), + .qsfp_9_rxc_4(qsfp_9_rxc_4_int), + /* + * Ethernet: QSFP28 via HTG 6x QSFP28 FMC+ adapter + */ + .fmc_qsfp_1_tx_clk_1(fmc_qsfp_1_tx_clk_1_int), + .fmc_qsfp_1_tx_rst_1(fmc_qsfp_1_tx_rst_1_int), + .fmc_qsfp_1_txd_1(fmc_qsfp_1_txd_1_int), + .fmc_qsfp_1_txc_1(fmc_qsfp_1_txc_1_int), + .fmc_qsfp_1_rx_clk_1(fmc_qsfp_1_rx_clk_1_int), + .fmc_qsfp_1_rx_rst_1(fmc_qsfp_1_rx_rst_1_int), + .fmc_qsfp_1_rxd_1(fmc_qsfp_1_rxd_1_int), + .fmc_qsfp_1_rxc_1(fmc_qsfp_1_rxc_1_int), + .fmc_qsfp_1_tx_clk_2(fmc_qsfp_1_tx_clk_2_int), + .fmc_qsfp_1_tx_rst_2(fmc_qsfp_1_tx_rst_2_int), + .fmc_qsfp_1_txd_2(fmc_qsfp_1_txd_2_int), + .fmc_qsfp_1_txc_2(fmc_qsfp_1_txc_2_int), + .fmc_qsfp_1_rx_clk_2(fmc_qsfp_1_rx_clk_2_int), + .fmc_qsfp_1_rx_rst_2(fmc_qsfp_1_rx_rst_2_int), + .fmc_qsfp_1_rxd_2(fmc_qsfp_1_rxd_2_int), + .fmc_qsfp_1_rxc_2(fmc_qsfp_1_rxc_2_int), + .fmc_qsfp_1_tx_clk_3(fmc_qsfp_1_tx_clk_3_int), + .fmc_qsfp_1_tx_rst_3(fmc_qsfp_1_tx_rst_3_int), + .fmc_qsfp_1_txd_3(fmc_qsfp_1_txd_3_int), + .fmc_qsfp_1_txc_3(fmc_qsfp_1_txc_3_int), + .fmc_qsfp_1_rx_clk_3(fmc_qsfp_1_rx_clk_3_int), + .fmc_qsfp_1_rx_rst_3(fmc_qsfp_1_rx_rst_3_int), + .fmc_qsfp_1_rxd_3(fmc_qsfp_1_rxd_3_int), + .fmc_qsfp_1_rxc_3(fmc_qsfp_1_rxc_3_int), + .fmc_qsfp_1_tx_clk_4(fmc_qsfp_1_tx_clk_4_int), + .fmc_qsfp_1_tx_rst_4(fmc_qsfp_1_tx_rst_4_int), + .fmc_qsfp_1_txd_4(fmc_qsfp_1_txd_4_int), + .fmc_qsfp_1_txc_4(fmc_qsfp_1_txc_4_int), + .fmc_qsfp_1_rx_clk_4(fmc_qsfp_1_rx_clk_4_int), + .fmc_qsfp_1_rx_rst_4(fmc_qsfp_1_rx_rst_4_int), + .fmc_qsfp_1_rxd_4(fmc_qsfp_1_rxd_4_int), + .fmc_qsfp_1_rxc_4(fmc_qsfp_1_rxc_4_int), + .fmc_qsfp_2_tx_clk_1(fmc_qsfp_2_tx_clk_1_int), + .fmc_qsfp_2_tx_rst_1(fmc_qsfp_2_tx_rst_1_int), + .fmc_qsfp_2_txd_1(fmc_qsfp_2_txd_1_int), + .fmc_qsfp_2_txc_1(fmc_qsfp_2_txc_1_int), + .fmc_qsfp_2_rx_clk_1(fmc_qsfp_2_rx_clk_1_int), + .fmc_qsfp_2_rx_rst_1(fmc_qsfp_2_rx_rst_1_int), + .fmc_qsfp_2_rxd_1(fmc_qsfp_2_rxd_1_int), + .fmc_qsfp_2_rxc_1(fmc_qsfp_2_rxc_1_int), + .fmc_qsfp_2_tx_clk_2(fmc_qsfp_2_tx_clk_2_int), + .fmc_qsfp_2_tx_rst_2(fmc_qsfp_2_tx_rst_2_int), + .fmc_qsfp_2_txd_2(fmc_qsfp_2_txd_2_int), + .fmc_qsfp_2_txc_2(fmc_qsfp_2_txc_2_int), + .fmc_qsfp_2_rx_clk_2(fmc_qsfp_2_rx_clk_2_int), + .fmc_qsfp_2_rx_rst_2(fmc_qsfp_2_rx_rst_2_int), + .fmc_qsfp_2_rxd_2(fmc_qsfp_2_rxd_2_int), + .fmc_qsfp_2_rxc_2(fmc_qsfp_2_rxc_2_int), + .fmc_qsfp_2_tx_clk_3(fmc_qsfp_2_tx_clk_3_int), + .fmc_qsfp_2_tx_rst_3(fmc_qsfp_2_tx_rst_3_int), + .fmc_qsfp_2_txd_3(fmc_qsfp_2_txd_3_int), + .fmc_qsfp_2_txc_3(fmc_qsfp_2_txc_3_int), + .fmc_qsfp_2_rx_clk_3(fmc_qsfp_2_rx_clk_3_int), + .fmc_qsfp_2_rx_rst_3(fmc_qsfp_2_rx_rst_3_int), + .fmc_qsfp_2_rxd_3(fmc_qsfp_2_rxd_3_int), + .fmc_qsfp_2_rxc_3(fmc_qsfp_2_rxc_3_int), + .fmc_qsfp_2_tx_clk_4(fmc_qsfp_2_tx_clk_4_int), + .fmc_qsfp_2_tx_rst_4(fmc_qsfp_2_tx_rst_4_int), + .fmc_qsfp_2_txd_4(fmc_qsfp_2_txd_4_int), + .fmc_qsfp_2_txc_4(fmc_qsfp_2_txc_4_int), + .fmc_qsfp_2_rx_clk_4(fmc_qsfp_2_rx_clk_4_int), + .fmc_qsfp_2_rx_rst_4(fmc_qsfp_2_rx_rst_4_int), + .fmc_qsfp_2_rxd_4(fmc_qsfp_2_rxd_4_int), + .fmc_qsfp_2_rxc_4(fmc_qsfp_2_rxc_4_int), + .fmc_qsfp_3_tx_clk_1(fmc_qsfp_3_tx_clk_1_int), + .fmc_qsfp_3_tx_rst_1(fmc_qsfp_3_tx_rst_1_int), + .fmc_qsfp_3_txd_1(fmc_qsfp_3_txd_1_int), + .fmc_qsfp_3_txc_1(fmc_qsfp_3_txc_1_int), + .fmc_qsfp_3_rx_clk_1(fmc_qsfp_3_rx_clk_1_int), + .fmc_qsfp_3_rx_rst_1(fmc_qsfp_3_rx_rst_1_int), + .fmc_qsfp_3_rxd_1(fmc_qsfp_3_rxd_1_int), + .fmc_qsfp_3_rxc_1(fmc_qsfp_3_rxc_1_int), + .fmc_qsfp_3_tx_clk_2(fmc_qsfp_3_tx_clk_2_int), + .fmc_qsfp_3_tx_rst_2(fmc_qsfp_3_tx_rst_2_int), + .fmc_qsfp_3_txd_2(fmc_qsfp_3_txd_2_int), + .fmc_qsfp_3_txc_2(fmc_qsfp_3_txc_2_int), + .fmc_qsfp_3_rx_clk_2(fmc_qsfp_3_rx_clk_2_int), + .fmc_qsfp_3_rx_rst_2(fmc_qsfp_3_rx_rst_2_int), + .fmc_qsfp_3_rxd_2(fmc_qsfp_3_rxd_2_int), + .fmc_qsfp_3_rxc_2(fmc_qsfp_3_rxc_2_int), + .fmc_qsfp_3_tx_clk_3(fmc_qsfp_3_tx_clk_3_int), + .fmc_qsfp_3_tx_rst_3(fmc_qsfp_3_tx_rst_3_int), + .fmc_qsfp_3_txd_3(fmc_qsfp_3_txd_3_int), + .fmc_qsfp_3_txc_3(fmc_qsfp_3_txc_3_int), + .fmc_qsfp_3_rx_clk_3(fmc_qsfp_3_rx_clk_3_int), + .fmc_qsfp_3_rx_rst_3(fmc_qsfp_3_rx_rst_3_int), + .fmc_qsfp_3_rxd_3(fmc_qsfp_3_rxd_3_int), + .fmc_qsfp_3_rxc_3(fmc_qsfp_3_rxc_3_int), + .fmc_qsfp_3_tx_clk_4(fmc_qsfp_3_tx_clk_4_int), + .fmc_qsfp_3_tx_rst_4(fmc_qsfp_3_tx_rst_4_int), + .fmc_qsfp_3_txd_4(fmc_qsfp_3_txd_4_int), + .fmc_qsfp_3_txc_4(fmc_qsfp_3_txc_4_int), + .fmc_qsfp_3_rx_clk_4(fmc_qsfp_3_rx_clk_4_int), + .fmc_qsfp_3_rx_rst_4(fmc_qsfp_3_rx_rst_4_int), + .fmc_qsfp_3_rxd_4(fmc_qsfp_3_rxd_4_int), + .fmc_qsfp_3_rxc_4(fmc_qsfp_3_rxc_4_int), + .fmc_qsfp_4_tx_clk_1(fmc_qsfp_4_tx_clk_1_int), + .fmc_qsfp_4_tx_rst_1(fmc_qsfp_4_tx_rst_1_int), + .fmc_qsfp_4_txd_1(fmc_qsfp_4_txd_1_int), + .fmc_qsfp_4_txc_1(fmc_qsfp_4_txc_1_int), + .fmc_qsfp_4_rx_clk_1(fmc_qsfp_4_rx_clk_1_int), + .fmc_qsfp_4_rx_rst_1(fmc_qsfp_4_rx_rst_1_int), + .fmc_qsfp_4_rxd_1(fmc_qsfp_4_rxd_1_int), + .fmc_qsfp_4_rxc_1(fmc_qsfp_4_rxc_1_int), + .fmc_qsfp_4_tx_clk_2(fmc_qsfp_4_tx_clk_2_int), + .fmc_qsfp_4_tx_rst_2(fmc_qsfp_4_tx_rst_2_int), + .fmc_qsfp_4_txd_2(fmc_qsfp_4_txd_2_int), + .fmc_qsfp_4_txc_2(fmc_qsfp_4_txc_2_int), + .fmc_qsfp_4_rx_clk_2(fmc_qsfp_4_rx_clk_2_int), + .fmc_qsfp_4_rx_rst_2(fmc_qsfp_4_rx_rst_2_int), + .fmc_qsfp_4_rxd_2(fmc_qsfp_4_rxd_2_int), + .fmc_qsfp_4_rxc_2(fmc_qsfp_4_rxc_2_int), + .fmc_qsfp_4_tx_clk_3(fmc_qsfp_4_tx_clk_3_int), + .fmc_qsfp_4_tx_rst_3(fmc_qsfp_4_tx_rst_3_int), + .fmc_qsfp_4_txd_3(fmc_qsfp_4_txd_3_int), + .fmc_qsfp_4_txc_3(fmc_qsfp_4_txc_3_int), + .fmc_qsfp_4_rx_clk_3(fmc_qsfp_4_rx_clk_3_int), + .fmc_qsfp_4_rx_rst_3(fmc_qsfp_4_rx_rst_3_int), + .fmc_qsfp_4_rxd_3(fmc_qsfp_4_rxd_3_int), + .fmc_qsfp_4_rxc_3(fmc_qsfp_4_rxc_3_int), + .fmc_qsfp_4_tx_clk_4(fmc_qsfp_4_tx_clk_4_int), + .fmc_qsfp_4_tx_rst_4(fmc_qsfp_4_tx_rst_4_int), + .fmc_qsfp_4_txd_4(fmc_qsfp_4_txd_4_int), + .fmc_qsfp_4_txc_4(fmc_qsfp_4_txc_4_int), + .fmc_qsfp_4_rx_clk_4(fmc_qsfp_4_rx_clk_4_int), + .fmc_qsfp_4_rx_rst_4(fmc_qsfp_4_rx_rst_4_int), + .fmc_qsfp_4_rxd_4(fmc_qsfp_4_rxd_4_int), + .fmc_qsfp_4_rxc_4(fmc_qsfp_4_rxc_4_int), + .fmc_qsfp_5_tx_clk_1(fmc_qsfp_5_tx_clk_1_int), + .fmc_qsfp_5_tx_rst_1(fmc_qsfp_5_tx_rst_1_int), + .fmc_qsfp_5_txd_1(fmc_qsfp_5_txd_1_int), + .fmc_qsfp_5_txc_1(fmc_qsfp_5_txc_1_int), + .fmc_qsfp_5_rx_clk_1(fmc_qsfp_5_rx_clk_1_int), + .fmc_qsfp_5_rx_rst_1(fmc_qsfp_5_rx_rst_1_int), + .fmc_qsfp_5_rxd_1(fmc_qsfp_5_rxd_1_int), + .fmc_qsfp_5_rxc_1(fmc_qsfp_5_rxc_1_int), + .fmc_qsfp_5_tx_clk_2(fmc_qsfp_5_tx_clk_2_int), + .fmc_qsfp_5_tx_rst_2(fmc_qsfp_5_tx_rst_2_int), + .fmc_qsfp_5_txd_2(fmc_qsfp_5_txd_2_int), + .fmc_qsfp_5_txc_2(fmc_qsfp_5_txc_2_int), + .fmc_qsfp_5_rx_clk_2(fmc_qsfp_5_rx_clk_2_int), + .fmc_qsfp_5_rx_rst_2(fmc_qsfp_5_rx_rst_2_int), + .fmc_qsfp_5_rxd_2(fmc_qsfp_5_rxd_2_int), + .fmc_qsfp_5_rxc_2(fmc_qsfp_5_rxc_2_int), + .fmc_qsfp_5_tx_clk_3(fmc_qsfp_5_tx_clk_3_int), + .fmc_qsfp_5_tx_rst_3(fmc_qsfp_5_tx_rst_3_int), + .fmc_qsfp_5_txd_3(fmc_qsfp_5_txd_3_int), + .fmc_qsfp_5_txc_3(fmc_qsfp_5_txc_3_int), + .fmc_qsfp_5_rx_clk_3(fmc_qsfp_5_rx_clk_3_int), + .fmc_qsfp_5_rx_rst_3(fmc_qsfp_5_rx_rst_3_int), + .fmc_qsfp_5_rxd_3(fmc_qsfp_5_rxd_3_int), + .fmc_qsfp_5_rxc_3(fmc_qsfp_5_rxc_3_int), + .fmc_qsfp_5_tx_clk_4(fmc_qsfp_5_tx_clk_4_int), + .fmc_qsfp_5_tx_rst_4(fmc_qsfp_5_tx_rst_4_int), + .fmc_qsfp_5_txd_4(fmc_qsfp_5_txd_4_int), + .fmc_qsfp_5_txc_4(fmc_qsfp_5_txc_4_int), + .fmc_qsfp_5_rx_clk_4(fmc_qsfp_5_rx_clk_4_int), + .fmc_qsfp_5_rx_rst_4(fmc_qsfp_5_rx_rst_4_int), + .fmc_qsfp_5_rxd_4(fmc_qsfp_5_rxd_4_int), + .fmc_qsfp_5_rxc_4(fmc_qsfp_5_rxc_4_int), + .fmc_qsfp_6_tx_clk_1(fmc_qsfp_6_tx_clk_1_int), + .fmc_qsfp_6_tx_rst_1(fmc_qsfp_6_tx_rst_1_int), + .fmc_qsfp_6_txd_1(fmc_qsfp_6_txd_1_int), + .fmc_qsfp_6_txc_1(fmc_qsfp_6_txc_1_int), + .fmc_qsfp_6_rx_clk_1(fmc_qsfp_6_rx_clk_1_int), + .fmc_qsfp_6_rx_rst_1(fmc_qsfp_6_rx_rst_1_int), + .fmc_qsfp_6_rxd_1(fmc_qsfp_6_rxd_1_int), + .fmc_qsfp_6_rxc_1(fmc_qsfp_6_rxc_1_int), + .fmc_qsfp_6_tx_clk_2(fmc_qsfp_6_tx_clk_2_int), + .fmc_qsfp_6_tx_rst_2(fmc_qsfp_6_tx_rst_2_int), + .fmc_qsfp_6_txd_2(fmc_qsfp_6_txd_2_int), + .fmc_qsfp_6_txc_2(fmc_qsfp_6_txc_2_int), + .fmc_qsfp_6_rx_clk_2(fmc_qsfp_6_rx_clk_2_int), + .fmc_qsfp_6_rx_rst_2(fmc_qsfp_6_rx_rst_2_int), + .fmc_qsfp_6_rxd_2(fmc_qsfp_6_rxd_2_int), + .fmc_qsfp_6_rxc_2(fmc_qsfp_6_rxc_2_int), + .fmc_qsfp_6_tx_clk_3(fmc_qsfp_6_tx_clk_3_int), + .fmc_qsfp_6_tx_rst_3(fmc_qsfp_6_tx_rst_3_int), + .fmc_qsfp_6_txd_3(fmc_qsfp_6_txd_3_int), + .fmc_qsfp_6_txc_3(fmc_qsfp_6_txc_3_int), + .fmc_qsfp_6_rx_clk_3(fmc_qsfp_6_rx_clk_3_int), + .fmc_qsfp_6_rx_rst_3(fmc_qsfp_6_rx_rst_3_int), + .fmc_qsfp_6_rxd_3(fmc_qsfp_6_rxd_3_int), + .fmc_qsfp_6_rxc_3(fmc_qsfp_6_rxc_3_int), + .fmc_qsfp_6_tx_clk_4(fmc_qsfp_6_tx_clk_4_int), + .fmc_qsfp_6_tx_rst_4(fmc_qsfp_6_tx_rst_4_int), + .fmc_qsfp_6_txd_4(fmc_qsfp_6_txd_4_int), + .fmc_qsfp_6_txc_4(fmc_qsfp_6_txc_4_int), + .fmc_qsfp_6_rx_clk_4(fmc_qsfp_6_rx_clk_4_int), + .fmc_qsfp_6_rx_rst_4(fmc_qsfp_6_rx_rst_4_int), + .fmc_qsfp_6_rxd_4(fmc_qsfp_6_rxd_4_int), + .fmc_qsfp_6_rxc_4(fmc_qsfp_6_rxc_4_int) +); + +endmodule + +`resetall diff --git a/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v new file mode 100644 index 000000000..cfafade3c --- /dev/null +++ b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v @@ -0,0 +1,1213 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA core logic + */ +module fpga_core +( + /* + * Clock: 156.25MHz + * Synchronous reset + */ + input wire clk, + input wire rst, + + /* + * GPIO + */ + input wire btn, + input wire [7:0] sw, + output wire [7:0] led, + + /* + * UART: 115200 bps, 8N1 + */ + output wire uart_rxd, + input wire uart_txd, + input wire uart_rts, + output wire uart_cts, + output wire uart_rst_n, + output wire uart_suspend_n, + + /* + * Ethernet: QSFP28 + */ + input wire qsfp_1_tx_clk_1, + input wire qsfp_1_tx_rst_1, + output wire [63:0] qsfp_1_txd_1, + output wire [7:0] qsfp_1_txc_1, + input wire qsfp_1_rx_clk_1, + input wire qsfp_1_rx_rst_1, + input wire [63:0] qsfp_1_rxd_1, + input wire [7:0] qsfp_1_rxc_1, + input wire qsfp_1_tx_clk_2, + input wire qsfp_1_tx_rst_2, + output wire [63:0] qsfp_1_txd_2, + output wire [7:0] qsfp_1_txc_2, + input wire qsfp_1_rx_clk_2, + input wire qsfp_1_rx_rst_2, + input wire [63:0] qsfp_1_rxd_2, + input wire [7:0] qsfp_1_rxc_2, + input wire qsfp_1_tx_clk_3, + input wire qsfp_1_tx_rst_3, + output wire [63:0] qsfp_1_txd_3, + output wire [7:0] qsfp_1_txc_3, + input wire qsfp_1_rx_clk_3, + input wire qsfp_1_rx_rst_3, + input wire [63:0] qsfp_1_rxd_3, + input wire [7:0] qsfp_1_rxc_3, + input wire qsfp_1_tx_clk_4, + input wire qsfp_1_tx_rst_4, + output wire [63:0] qsfp_1_txd_4, + output wire [7:0] qsfp_1_txc_4, + input wire qsfp_1_rx_clk_4, + input wire qsfp_1_rx_rst_4, + input wire [63:0] qsfp_1_rxd_4, + input wire [7:0] qsfp_1_rxc_4, + input wire qsfp_2_tx_clk_1, + input wire qsfp_2_tx_rst_1, + output wire [63:0] qsfp_2_txd_1, + output wire [7:0] qsfp_2_txc_1, + input wire qsfp_2_rx_clk_1, + input wire qsfp_2_rx_rst_1, + input wire [63:0] qsfp_2_rxd_1, + input wire [7:0] qsfp_2_rxc_1, + input wire qsfp_2_tx_clk_2, + input wire qsfp_2_tx_rst_2, + output wire [63:0] qsfp_2_txd_2, + output wire [7:0] qsfp_2_txc_2, + input wire qsfp_2_rx_clk_2, + input wire qsfp_2_rx_rst_2, + input wire [63:0] qsfp_2_rxd_2, + input wire [7:0] qsfp_2_rxc_2, + input wire qsfp_2_tx_clk_3, + input wire qsfp_2_tx_rst_3, + output wire [63:0] qsfp_2_txd_3, + output wire [7:0] qsfp_2_txc_3, + input wire qsfp_2_rx_clk_3, + input wire qsfp_2_rx_rst_3, + input wire [63:0] qsfp_2_rxd_3, + input wire [7:0] qsfp_2_rxc_3, + input wire qsfp_2_tx_clk_4, + input wire qsfp_2_tx_rst_4, + output wire [63:0] qsfp_2_txd_4, + output wire [7:0] qsfp_2_txc_4, + input wire qsfp_2_rx_clk_4, + input wire qsfp_2_rx_rst_4, + input wire [63:0] qsfp_2_rxd_4, + input wire [7:0] qsfp_2_rxc_4, + input wire qsfp_3_tx_clk_1, + input wire qsfp_3_tx_rst_1, + output wire [63:0] qsfp_3_txd_1, + output wire [7:0] qsfp_3_txc_1, + input wire qsfp_3_rx_clk_1, + input wire qsfp_3_rx_rst_1, + input wire [63:0] qsfp_3_rxd_1, + input wire [7:0] qsfp_3_rxc_1, + input wire qsfp_3_tx_clk_2, + input wire qsfp_3_tx_rst_2, + output wire [63:0] qsfp_3_txd_2, + output wire [7:0] qsfp_3_txc_2, + input wire qsfp_3_rx_clk_2, + input wire qsfp_3_rx_rst_2, + input wire [63:0] qsfp_3_rxd_2, + input wire [7:0] qsfp_3_rxc_2, + input wire qsfp_3_tx_clk_3, + input wire qsfp_3_tx_rst_3, + output wire [63:0] qsfp_3_txd_3, + output wire [7:0] qsfp_3_txc_3, + input wire qsfp_3_rx_clk_3, + input wire qsfp_3_rx_rst_3, + input wire [63:0] qsfp_3_rxd_3, + input wire [7:0] qsfp_3_rxc_3, + input wire qsfp_3_tx_clk_4, + input wire qsfp_3_tx_rst_4, + output wire [63:0] qsfp_3_txd_4, + output wire [7:0] qsfp_3_txc_4, + input wire qsfp_3_rx_clk_4, + input wire qsfp_3_rx_rst_4, + input wire [63:0] qsfp_3_rxd_4, + input wire [7:0] qsfp_3_rxc_4, + input wire qsfp_4_tx_clk_1, + input wire qsfp_4_tx_rst_1, + output wire [63:0] qsfp_4_txd_1, + output wire [7:0] qsfp_4_txc_1, + input wire qsfp_4_rx_clk_1, + input wire qsfp_4_rx_rst_1, + input wire [63:0] qsfp_4_rxd_1, + input wire [7:0] qsfp_4_rxc_1, + input wire qsfp_4_tx_clk_2, + input wire qsfp_4_tx_rst_2, + output wire [63:0] qsfp_4_txd_2, + output wire [7:0] qsfp_4_txc_2, + input wire qsfp_4_rx_clk_2, + input wire qsfp_4_rx_rst_2, + input wire [63:0] qsfp_4_rxd_2, + input wire [7:0] qsfp_4_rxc_2, + input wire qsfp_4_tx_clk_3, + input wire qsfp_4_tx_rst_3, + output wire [63:0] qsfp_4_txd_3, + output wire [7:0] qsfp_4_txc_3, + input wire qsfp_4_rx_clk_3, + input wire qsfp_4_rx_rst_3, + input wire [63:0] qsfp_4_rxd_3, + input wire [7:0] qsfp_4_rxc_3, + input wire qsfp_4_tx_clk_4, + input wire qsfp_4_tx_rst_4, + output wire [63:0] qsfp_4_txd_4, + output wire [7:0] qsfp_4_txc_4, + input wire qsfp_4_rx_clk_4, + input wire qsfp_4_rx_rst_4, + input wire [63:0] qsfp_4_rxd_4, + input wire [7:0] qsfp_4_rxc_4, + input wire qsfp_5_tx_clk_1, + input wire qsfp_5_tx_rst_1, + output wire [63:0] qsfp_5_txd_1, + output wire [7:0] qsfp_5_txc_1, + input wire qsfp_5_rx_clk_1, + input wire qsfp_5_rx_rst_1, + input wire [63:0] qsfp_5_rxd_1, + input wire [7:0] qsfp_5_rxc_1, + input wire qsfp_5_tx_clk_2, + input wire qsfp_5_tx_rst_2, + output wire [63:0] qsfp_5_txd_2, + output wire [7:0] qsfp_5_txc_2, + input wire qsfp_5_rx_clk_2, + input wire qsfp_5_rx_rst_2, + input wire [63:0] qsfp_5_rxd_2, + input wire [7:0] qsfp_5_rxc_2, + input wire qsfp_5_tx_clk_3, + input wire qsfp_5_tx_rst_3, + output wire [63:0] qsfp_5_txd_3, + output wire [7:0] qsfp_5_txc_3, + input wire qsfp_5_rx_clk_3, + input wire qsfp_5_rx_rst_3, + input wire [63:0] qsfp_5_rxd_3, + input wire [7:0] qsfp_5_rxc_3, + input wire qsfp_5_tx_clk_4, + input wire qsfp_5_tx_rst_4, + output wire [63:0] qsfp_5_txd_4, + output wire [7:0] qsfp_5_txc_4, + input wire qsfp_5_rx_clk_4, + input wire qsfp_5_rx_rst_4, + input wire [63:0] qsfp_5_rxd_4, + input wire [7:0] qsfp_5_rxc_4, + input wire qsfp_6_tx_clk_1, + input wire qsfp_6_tx_rst_1, + output wire [63:0] qsfp_6_txd_1, + output wire [7:0] qsfp_6_txc_1, + input wire qsfp_6_rx_clk_1, + input wire qsfp_6_rx_rst_1, + input wire [63:0] qsfp_6_rxd_1, + input wire [7:0] qsfp_6_rxc_1, + input wire qsfp_6_tx_clk_2, + input wire qsfp_6_tx_rst_2, + output wire [63:0] qsfp_6_txd_2, + output wire [7:0] qsfp_6_txc_2, + input wire qsfp_6_rx_clk_2, + input wire qsfp_6_rx_rst_2, + input wire [63:0] qsfp_6_rxd_2, + input wire [7:0] qsfp_6_rxc_2, + input wire qsfp_6_tx_clk_3, + input wire qsfp_6_tx_rst_3, + output wire [63:0] qsfp_6_txd_3, + output wire [7:0] qsfp_6_txc_3, + input wire qsfp_6_rx_clk_3, + input wire qsfp_6_rx_rst_3, + input wire [63:0] qsfp_6_rxd_3, + input wire [7:0] qsfp_6_rxc_3, + input wire qsfp_6_tx_clk_4, + input wire qsfp_6_tx_rst_4, + output wire [63:0] qsfp_6_txd_4, + output wire [7:0] qsfp_6_txc_4, + input wire qsfp_6_rx_clk_4, + input wire qsfp_6_rx_rst_4, + input wire [63:0] qsfp_6_rxd_4, + input wire [7:0] qsfp_6_rxc_4, + input wire qsfp_7_tx_clk_1, + input wire qsfp_7_tx_rst_1, + output wire [63:0] qsfp_7_txd_1, + output wire [7:0] qsfp_7_txc_1, + input wire qsfp_7_rx_clk_1, + input wire qsfp_7_rx_rst_1, + input wire [63:0] qsfp_7_rxd_1, + input wire [7:0] qsfp_7_rxc_1, + input wire qsfp_7_tx_clk_2, + input wire qsfp_7_tx_rst_2, + output wire [63:0] qsfp_7_txd_2, + output wire [7:0] qsfp_7_txc_2, + input wire qsfp_7_rx_clk_2, + input wire qsfp_7_rx_rst_2, + input wire [63:0] qsfp_7_rxd_2, + input wire [7:0] qsfp_7_rxc_2, + input wire qsfp_7_tx_clk_3, + input wire qsfp_7_tx_rst_3, + output wire [63:0] qsfp_7_txd_3, + output wire [7:0] qsfp_7_txc_3, + input wire qsfp_7_rx_clk_3, + input wire qsfp_7_rx_rst_3, + input wire [63:0] qsfp_7_rxd_3, + input wire [7:0] qsfp_7_rxc_3, + input wire qsfp_7_tx_clk_4, + input wire qsfp_7_tx_rst_4, + output wire [63:0] qsfp_7_txd_4, + output wire [7:0] qsfp_7_txc_4, + input wire qsfp_7_rx_clk_4, + input wire qsfp_7_rx_rst_4, + input wire [63:0] qsfp_7_rxd_4, + input wire [7:0] qsfp_7_rxc_4, + input wire qsfp_8_tx_clk_1, + input wire qsfp_8_tx_rst_1, + output wire [63:0] qsfp_8_txd_1, + output wire [7:0] qsfp_8_txc_1, + input wire qsfp_8_rx_clk_1, + input wire qsfp_8_rx_rst_1, + input wire [63:0] qsfp_8_rxd_1, + input wire [7:0] qsfp_8_rxc_1, + input wire qsfp_8_tx_clk_2, + input wire qsfp_8_tx_rst_2, + output wire [63:0] qsfp_8_txd_2, + output wire [7:0] qsfp_8_txc_2, + input wire qsfp_8_rx_clk_2, + input wire qsfp_8_rx_rst_2, + input wire [63:0] qsfp_8_rxd_2, + input wire [7:0] qsfp_8_rxc_2, + input wire qsfp_8_tx_clk_3, + input wire qsfp_8_tx_rst_3, + output wire [63:0] qsfp_8_txd_3, + output wire [7:0] qsfp_8_txc_3, + input wire qsfp_8_rx_clk_3, + input wire qsfp_8_rx_rst_3, + input wire [63:0] qsfp_8_rxd_3, + input wire [7:0] qsfp_8_rxc_3, + input wire qsfp_8_tx_clk_4, + input wire qsfp_8_tx_rst_4, + output wire [63:0] qsfp_8_txd_4, + output wire [7:0] qsfp_8_txc_4, + input wire qsfp_8_rx_clk_4, + input wire qsfp_8_rx_rst_4, + input wire [63:0] qsfp_8_rxd_4, + input wire [7:0] qsfp_8_rxc_4, + input wire qsfp_9_tx_clk_1, + input wire qsfp_9_tx_rst_1, + output wire [63:0] qsfp_9_txd_1, + output wire [7:0] qsfp_9_txc_1, + input wire qsfp_9_rx_clk_1, + input wire qsfp_9_rx_rst_1, + input wire [63:0] qsfp_9_rxd_1, + input wire [7:0] qsfp_9_rxc_1, + input wire qsfp_9_tx_clk_2, + input wire qsfp_9_tx_rst_2, + output wire [63:0] qsfp_9_txd_2, + output wire [7:0] qsfp_9_txc_2, + input wire qsfp_9_rx_clk_2, + input wire qsfp_9_rx_rst_2, + input wire [63:0] qsfp_9_rxd_2, + input wire [7:0] qsfp_9_rxc_2, + input wire qsfp_9_tx_clk_3, + input wire qsfp_9_tx_rst_3, + output wire [63:0] qsfp_9_txd_3, + output wire [7:0] qsfp_9_txc_3, + input wire qsfp_9_rx_clk_3, + input wire qsfp_9_rx_rst_3, + input wire [63:0] qsfp_9_rxd_3, + input wire [7:0] qsfp_9_rxc_3, + input wire qsfp_9_tx_clk_4, + input wire qsfp_9_tx_rst_4, + output wire [63:0] qsfp_9_txd_4, + output wire [7:0] qsfp_9_txc_4, + input wire qsfp_9_rx_clk_4, + input wire qsfp_9_rx_rst_4, + input wire [63:0] qsfp_9_rxd_4, + input wire [7:0] qsfp_9_rxc_4, + + /* + * Ethernet: QSFP28 via HTG 6x QSFP28 FMC+ adapter + */ + input wire fmc_qsfp_1_tx_clk_1, + input wire fmc_qsfp_1_tx_rst_1, + output wire [63:0] fmc_qsfp_1_txd_1, + output wire [7:0] fmc_qsfp_1_txc_1, + input wire fmc_qsfp_1_rx_clk_1, + input wire fmc_qsfp_1_rx_rst_1, + input wire [63:0] fmc_qsfp_1_rxd_1, + input wire [7:0] fmc_qsfp_1_rxc_1, + input wire fmc_qsfp_1_tx_clk_2, + input wire fmc_qsfp_1_tx_rst_2, + output wire [63:0] fmc_qsfp_1_txd_2, + output wire [7:0] fmc_qsfp_1_txc_2, + input wire fmc_qsfp_1_rx_clk_2, + input wire fmc_qsfp_1_rx_rst_2, + input wire [63:0] fmc_qsfp_1_rxd_2, + input wire [7:0] fmc_qsfp_1_rxc_2, + input wire fmc_qsfp_1_tx_clk_3, + input wire fmc_qsfp_1_tx_rst_3, + output wire [63:0] fmc_qsfp_1_txd_3, + output wire [7:0] fmc_qsfp_1_txc_3, + input wire fmc_qsfp_1_rx_clk_3, + input wire fmc_qsfp_1_rx_rst_3, + input wire [63:0] fmc_qsfp_1_rxd_3, + input wire [7:0] fmc_qsfp_1_rxc_3, + input wire fmc_qsfp_1_tx_clk_4, + input wire fmc_qsfp_1_tx_rst_4, + output wire [63:0] fmc_qsfp_1_txd_4, + output wire [7:0] fmc_qsfp_1_txc_4, + input wire fmc_qsfp_1_rx_clk_4, + input wire fmc_qsfp_1_rx_rst_4, + input wire [63:0] fmc_qsfp_1_rxd_4, + input wire [7:0] fmc_qsfp_1_rxc_4, + input wire fmc_qsfp_2_tx_clk_1, + input wire fmc_qsfp_2_tx_rst_1, + output wire [63:0] fmc_qsfp_2_txd_1, + output wire [7:0] fmc_qsfp_2_txc_1, + input wire fmc_qsfp_2_rx_clk_1, + input wire fmc_qsfp_2_rx_rst_1, + input wire [63:0] fmc_qsfp_2_rxd_1, + input wire [7:0] fmc_qsfp_2_rxc_1, + input wire fmc_qsfp_2_tx_clk_2, + input wire fmc_qsfp_2_tx_rst_2, + output wire [63:0] fmc_qsfp_2_txd_2, + output wire [7:0] fmc_qsfp_2_txc_2, + input wire fmc_qsfp_2_rx_clk_2, + input wire fmc_qsfp_2_rx_rst_2, + input wire [63:0] fmc_qsfp_2_rxd_2, + input wire [7:0] fmc_qsfp_2_rxc_2, + input wire fmc_qsfp_2_tx_clk_3, + input wire fmc_qsfp_2_tx_rst_3, + output wire [63:0] fmc_qsfp_2_txd_3, + output wire [7:0] fmc_qsfp_2_txc_3, + input wire fmc_qsfp_2_rx_clk_3, + input wire fmc_qsfp_2_rx_rst_3, + input wire [63:0] fmc_qsfp_2_rxd_3, + input wire [7:0] fmc_qsfp_2_rxc_3, + input wire fmc_qsfp_2_tx_clk_4, + input wire fmc_qsfp_2_tx_rst_4, + output wire [63:0] fmc_qsfp_2_txd_4, + output wire [7:0] fmc_qsfp_2_txc_4, + input wire fmc_qsfp_2_rx_clk_4, + input wire fmc_qsfp_2_rx_rst_4, + input wire [63:0] fmc_qsfp_2_rxd_4, + input wire [7:0] fmc_qsfp_2_rxc_4, + input wire fmc_qsfp_3_tx_clk_1, + input wire fmc_qsfp_3_tx_rst_1, + output wire [63:0] fmc_qsfp_3_txd_1, + output wire [7:0] fmc_qsfp_3_txc_1, + input wire fmc_qsfp_3_rx_clk_1, + input wire fmc_qsfp_3_rx_rst_1, + input wire [63:0] fmc_qsfp_3_rxd_1, + input wire [7:0] fmc_qsfp_3_rxc_1, + input wire fmc_qsfp_3_tx_clk_2, + input wire fmc_qsfp_3_tx_rst_2, + output wire [63:0] fmc_qsfp_3_txd_2, + output wire [7:0] fmc_qsfp_3_txc_2, + input wire fmc_qsfp_3_rx_clk_2, + input wire fmc_qsfp_3_rx_rst_2, + input wire [63:0] fmc_qsfp_3_rxd_2, + input wire [7:0] fmc_qsfp_3_rxc_2, + input wire fmc_qsfp_3_tx_clk_3, + input wire fmc_qsfp_3_tx_rst_3, + output wire [63:0] fmc_qsfp_3_txd_3, + output wire [7:0] fmc_qsfp_3_txc_3, + input wire fmc_qsfp_3_rx_clk_3, + input wire fmc_qsfp_3_rx_rst_3, + input wire [63:0] fmc_qsfp_3_rxd_3, + input wire [7:0] fmc_qsfp_3_rxc_3, + input wire fmc_qsfp_3_tx_clk_4, + input wire fmc_qsfp_3_tx_rst_4, + output wire [63:0] fmc_qsfp_3_txd_4, + output wire [7:0] fmc_qsfp_3_txc_4, + input wire fmc_qsfp_3_rx_clk_4, + input wire fmc_qsfp_3_rx_rst_4, + input wire [63:0] fmc_qsfp_3_rxd_4, + input wire [7:0] fmc_qsfp_3_rxc_4, + input wire fmc_qsfp_4_tx_clk_1, + input wire fmc_qsfp_4_tx_rst_1, + output wire [63:0] fmc_qsfp_4_txd_1, + output wire [7:0] fmc_qsfp_4_txc_1, + input wire fmc_qsfp_4_rx_clk_1, + input wire fmc_qsfp_4_rx_rst_1, + input wire [63:0] fmc_qsfp_4_rxd_1, + input wire [7:0] fmc_qsfp_4_rxc_1, + input wire fmc_qsfp_4_tx_clk_2, + input wire fmc_qsfp_4_tx_rst_2, + output wire [63:0] fmc_qsfp_4_txd_2, + output wire [7:0] fmc_qsfp_4_txc_2, + input wire fmc_qsfp_4_rx_clk_2, + input wire fmc_qsfp_4_rx_rst_2, + input wire [63:0] fmc_qsfp_4_rxd_2, + input wire [7:0] fmc_qsfp_4_rxc_2, + input wire fmc_qsfp_4_tx_clk_3, + input wire fmc_qsfp_4_tx_rst_3, + output wire [63:0] fmc_qsfp_4_txd_3, + output wire [7:0] fmc_qsfp_4_txc_3, + input wire fmc_qsfp_4_rx_clk_3, + input wire fmc_qsfp_4_rx_rst_3, + input wire [63:0] fmc_qsfp_4_rxd_3, + input wire [7:0] fmc_qsfp_4_rxc_3, + input wire fmc_qsfp_4_tx_clk_4, + input wire fmc_qsfp_4_tx_rst_4, + output wire [63:0] fmc_qsfp_4_txd_4, + output wire [7:0] fmc_qsfp_4_txc_4, + input wire fmc_qsfp_4_rx_clk_4, + input wire fmc_qsfp_4_rx_rst_4, + input wire [63:0] fmc_qsfp_4_rxd_4, + input wire [7:0] fmc_qsfp_4_rxc_4, + input wire fmc_qsfp_5_tx_clk_1, + input wire fmc_qsfp_5_tx_rst_1, + output wire [63:0] fmc_qsfp_5_txd_1, + output wire [7:0] fmc_qsfp_5_txc_1, + input wire fmc_qsfp_5_rx_clk_1, + input wire fmc_qsfp_5_rx_rst_1, + input wire [63:0] fmc_qsfp_5_rxd_1, + input wire [7:0] fmc_qsfp_5_rxc_1, + input wire fmc_qsfp_5_tx_clk_2, + input wire fmc_qsfp_5_tx_rst_2, + output wire [63:0] fmc_qsfp_5_txd_2, + output wire [7:0] fmc_qsfp_5_txc_2, + input wire fmc_qsfp_5_rx_clk_2, + input wire fmc_qsfp_5_rx_rst_2, + input wire [63:0] fmc_qsfp_5_rxd_2, + input wire [7:0] fmc_qsfp_5_rxc_2, + input wire fmc_qsfp_5_tx_clk_3, + input wire fmc_qsfp_5_tx_rst_3, + output wire [63:0] fmc_qsfp_5_txd_3, + output wire [7:0] fmc_qsfp_5_txc_3, + input wire fmc_qsfp_5_rx_clk_3, + input wire fmc_qsfp_5_rx_rst_3, + input wire [63:0] fmc_qsfp_5_rxd_3, + input wire [7:0] fmc_qsfp_5_rxc_3, + input wire fmc_qsfp_5_tx_clk_4, + input wire fmc_qsfp_5_tx_rst_4, + output wire [63:0] fmc_qsfp_5_txd_4, + output wire [7:0] fmc_qsfp_5_txc_4, + input wire fmc_qsfp_5_rx_clk_4, + input wire fmc_qsfp_5_rx_rst_4, + input wire [63:0] fmc_qsfp_5_rxd_4, + input wire [7:0] fmc_qsfp_5_rxc_4, + input wire fmc_qsfp_6_tx_clk_1, + input wire fmc_qsfp_6_tx_rst_1, + output wire [63:0] fmc_qsfp_6_txd_1, + output wire [7:0] fmc_qsfp_6_txc_1, + input wire fmc_qsfp_6_rx_clk_1, + input wire fmc_qsfp_6_rx_rst_1, + input wire [63:0] fmc_qsfp_6_rxd_1, + input wire [7:0] fmc_qsfp_6_rxc_1, + input wire fmc_qsfp_6_tx_clk_2, + input wire fmc_qsfp_6_tx_rst_2, + output wire [63:0] fmc_qsfp_6_txd_2, + output wire [7:0] fmc_qsfp_6_txc_2, + input wire fmc_qsfp_6_rx_clk_2, + input wire fmc_qsfp_6_rx_rst_2, + input wire [63:0] fmc_qsfp_6_rxd_2, + input wire [7:0] fmc_qsfp_6_rxc_2, + input wire fmc_qsfp_6_tx_clk_3, + input wire fmc_qsfp_6_tx_rst_3, + output wire [63:0] fmc_qsfp_6_txd_3, + output wire [7:0] fmc_qsfp_6_txc_3, + input wire fmc_qsfp_6_rx_clk_3, + input wire fmc_qsfp_6_rx_rst_3, + input wire [63:0] fmc_qsfp_6_rxd_3, + input wire [7:0] fmc_qsfp_6_rxc_3, + input wire fmc_qsfp_6_tx_clk_4, + input wire fmc_qsfp_6_tx_rst_4, + output wire [63:0] fmc_qsfp_6_txd_4, + output wire [7:0] fmc_qsfp_6_txc_4, + input wire fmc_qsfp_6_rx_clk_4, + input wire fmc_qsfp_6_rx_rst_4, + input wire [63:0] fmc_qsfp_6_rxd_4, + input wire [7:0] fmc_qsfp_6_rxc_4 +); + +// AXI between MAC and Ethernet modules +wire [63:0] rx_axis_tdata; +wire [7:0] rx_axis_tkeep; +wire rx_axis_tvalid; +wire rx_axis_tready; +wire rx_axis_tlast; +wire rx_axis_tuser; + +wire [63:0] tx_axis_tdata; +wire [7:0] tx_axis_tkeep; +wire tx_axis_tvalid; +wire tx_axis_tready; +wire tx_axis_tlast; +wire tx_axis_tuser; + +// Ethernet frame between Ethernet modules and UDP stack +wire rx_eth_hdr_ready; +wire rx_eth_hdr_valid; +wire [47:0] rx_eth_dest_mac; +wire [47:0] rx_eth_src_mac; +wire [15:0] rx_eth_type; +wire [63:0] rx_eth_payload_axis_tdata; +wire [7:0] rx_eth_payload_axis_tkeep; +wire rx_eth_payload_axis_tvalid; +wire rx_eth_payload_axis_tready; +wire rx_eth_payload_axis_tlast; +wire rx_eth_payload_axis_tuser; + +wire tx_eth_hdr_ready; +wire tx_eth_hdr_valid; +wire [47:0] tx_eth_dest_mac; +wire [47:0] tx_eth_src_mac; +wire [15:0] tx_eth_type; +wire [63:0] tx_eth_payload_axis_tdata; +wire [7:0] tx_eth_payload_axis_tkeep; +wire tx_eth_payload_axis_tvalid; +wire tx_eth_payload_axis_tready; +wire tx_eth_payload_axis_tlast; +wire tx_eth_payload_axis_tuser; + +// IP frame connections +wire rx_ip_hdr_valid; +wire rx_ip_hdr_ready; +wire [47:0] rx_ip_eth_dest_mac; +wire [47:0] rx_ip_eth_src_mac; +wire [15:0] rx_ip_eth_type; +wire [3:0] rx_ip_version; +wire [3:0] rx_ip_ihl; +wire [5:0] rx_ip_dscp; +wire [1:0] rx_ip_ecn; +wire [15:0] rx_ip_length; +wire [15:0] rx_ip_identification; +wire [2:0] rx_ip_flags; +wire [12:0] rx_ip_fragment_offset; +wire [7:0] rx_ip_ttl; +wire [7:0] rx_ip_protocol; +wire [15:0] rx_ip_header_checksum; +wire [31:0] rx_ip_source_ip; +wire [31:0] rx_ip_dest_ip; +wire [63:0] rx_ip_payload_axis_tdata; +wire [7:0] rx_ip_payload_axis_tkeep; +wire rx_ip_payload_axis_tvalid; +wire rx_ip_payload_axis_tready; +wire rx_ip_payload_axis_tlast; +wire rx_ip_payload_axis_tuser; + +wire tx_ip_hdr_valid; +wire tx_ip_hdr_ready; +wire [5:0] tx_ip_dscp; +wire [1:0] tx_ip_ecn; +wire [15:0] tx_ip_length; +wire [7:0] tx_ip_ttl; +wire [7:0] tx_ip_protocol; +wire [31:0] tx_ip_source_ip; +wire [31:0] tx_ip_dest_ip; +wire [63:0] tx_ip_payload_axis_tdata; +wire [7:0] tx_ip_payload_axis_tkeep; +wire tx_ip_payload_axis_tvalid; +wire tx_ip_payload_axis_tready; +wire tx_ip_payload_axis_tlast; +wire tx_ip_payload_axis_tuser; + +// UDP frame connections +wire rx_udp_hdr_valid; +wire rx_udp_hdr_ready; +wire [47:0] rx_udp_eth_dest_mac; +wire [47:0] rx_udp_eth_src_mac; +wire [15:0] rx_udp_eth_type; +wire [3:0] rx_udp_ip_version; +wire [3:0] rx_udp_ip_ihl; +wire [5:0] rx_udp_ip_dscp; +wire [1:0] rx_udp_ip_ecn; +wire [15:0] rx_udp_ip_length; +wire [15:0] rx_udp_ip_identification; +wire [2:0] rx_udp_ip_flags; +wire [12:0] rx_udp_ip_fragment_offset; +wire [7:0] rx_udp_ip_ttl; +wire [7:0] rx_udp_ip_protocol; +wire [15:0] rx_udp_ip_header_checksum; +wire [31:0] rx_udp_ip_source_ip; +wire [31:0] rx_udp_ip_dest_ip; +wire [15:0] rx_udp_source_port; +wire [15:0] rx_udp_dest_port; +wire [15:0] rx_udp_length; +wire [15:0] rx_udp_checksum; +wire [63:0] rx_udp_payload_axis_tdata; +wire [7:0] rx_udp_payload_axis_tkeep; +wire rx_udp_payload_axis_tvalid; +wire rx_udp_payload_axis_tready; +wire rx_udp_payload_axis_tlast; +wire rx_udp_payload_axis_tuser; + +wire tx_udp_hdr_valid; +wire tx_udp_hdr_ready; +wire [5:0] tx_udp_ip_dscp; +wire [1:0] tx_udp_ip_ecn; +wire [7:0] tx_udp_ip_ttl; +wire [31:0] tx_udp_ip_source_ip; +wire [31:0] tx_udp_ip_dest_ip; +wire [15:0] tx_udp_source_port; +wire [15:0] tx_udp_dest_port; +wire [15:0] tx_udp_length; +wire [15:0] tx_udp_checksum; +wire [63:0] tx_udp_payload_axis_tdata; +wire [7:0] tx_udp_payload_axis_tkeep; +wire tx_udp_payload_axis_tvalid; +wire tx_udp_payload_axis_tready; +wire tx_udp_payload_axis_tlast; +wire tx_udp_payload_axis_tuser; + +wire [63:0] rx_fifo_udp_payload_axis_tdata; +wire [7:0] rx_fifo_udp_payload_axis_tkeep; +wire rx_fifo_udp_payload_axis_tvalid; +wire rx_fifo_udp_payload_axis_tready; +wire rx_fifo_udp_payload_axis_tlast; +wire rx_fifo_udp_payload_axis_tuser; + +wire [63:0] tx_fifo_udp_payload_axis_tdata; +wire [7:0] tx_fifo_udp_payload_axis_tkeep; +wire tx_fifo_udp_payload_axis_tvalid; +wire tx_fifo_udp_payload_axis_tready; +wire tx_fifo_udp_payload_axis_tlast; +wire tx_fifo_udp_payload_axis_tuser; + +// Configuration +wire [47:0] local_mac = 48'h02_00_00_00_00_00; +wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128}; +wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1}; +wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0}; + +// IP ports not used +assign rx_ip_hdr_ready = 1; +assign rx_ip_payload_axis_tready = 1; + +assign tx_ip_hdr_valid = 0; +assign tx_ip_dscp = 0; +assign tx_ip_ecn = 0; +assign tx_ip_length = 0; +assign tx_ip_ttl = 0; +assign tx_ip_protocol = 0; +assign tx_ip_source_ip = 0; +assign tx_ip_dest_ip = 0; +assign tx_ip_payload_axis_tdata = 0; +assign tx_ip_payload_axis_tkeep = 0; +assign tx_ip_payload_axis_tvalid = 0; +assign tx_ip_payload_axis_tlast = 0; +assign tx_ip_payload_axis_tuser = 0; + +// Loop back UDP +wire match_cond = rx_udp_dest_port == 1234; +wire no_match = !match_cond; + +reg match_cond_reg = 0; +reg no_match_reg = 0; + +always @(posedge clk) begin + if (rst) begin + match_cond_reg <= 0; + no_match_reg <= 0; + end else begin + if (rx_udp_payload_axis_tvalid) begin + if ((!match_cond_reg && !no_match_reg) || + (rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin + match_cond_reg <= match_cond; + no_match_reg <= no_match; + end + end else begin + match_cond_reg <= 0; + no_match_reg <= 0; + end + end +end + +assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond; +assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match; +assign tx_udp_ip_dscp = 0; +assign tx_udp_ip_ecn = 0; +assign tx_udp_ip_ttl = 64; +assign tx_udp_ip_source_ip = local_ip; +assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip; +assign tx_udp_source_port = rx_udp_dest_port; +assign tx_udp_dest_port = rx_udp_source_port; +assign tx_udp_length = rx_udp_length; +assign tx_udp_checksum = 0; + +assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata; +assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep; +assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid; +assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready; +assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast; +assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser; + +assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata; +assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep; +assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg; +assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg; +assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast; +assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser; + +// Place first payload byte onto LEDs +reg valid_last = 0; +reg [7:0] led_reg = 0; + +always @(posedge clk) begin + if (rst) begin + led_reg <= 0; + end else begin + valid_last <= tx_udp_payload_axis_tvalid; + if (tx_udp_payload_axis_tvalid && !valid_last) begin + led_reg <= tx_udp_payload_axis_tdata; + end + end +end + +assign led = led_reg; + +assign uart_rxd = 1'b1; +assign uart_cts = 1'b1; +assign uart_rst_n = 1'b1; +assign uart_suspend_n = 1'b1; + +// assign qsfp_1_txd_1 = 64'h0707070707070707; +// assign qsfp_1_txc_1 = 8'hff; +assign qsfp_1_txd_2 = 64'h0707070707070707; +assign qsfp_1_txc_2 = 8'hff; +assign qsfp_1_txd_3 = 64'h0707070707070707; +assign qsfp_1_txc_3 = 8'hff; +assign qsfp_1_txd_4 = 64'h0707070707070707; +assign qsfp_1_txc_4 = 8'hff; + +assign qsfp_2_txd_1 = 64'h0707070707070707; +assign qsfp_2_txc_1 = 8'hff; +assign qsfp_2_txd_2 = 64'h0707070707070707; +assign qsfp_2_txc_2 = 8'hff; +assign qsfp_2_txd_3 = 64'h0707070707070707; +assign qsfp_2_txc_3 = 8'hff; +assign qsfp_2_txd_4 = 64'h0707070707070707; +assign qsfp_2_txc_4 = 8'hff; + +assign qsfp_3_txd_1 = 64'h0707070707070707; +assign qsfp_3_txc_1 = 8'hff; +assign qsfp_3_txd_2 = 64'h0707070707070707; +assign qsfp_3_txc_2 = 8'hff; +assign qsfp_3_txd_3 = 64'h0707070707070707; +assign qsfp_3_txc_3 = 8'hff; +assign qsfp_3_txd_4 = 64'h0707070707070707; +assign qsfp_3_txc_4 = 8'hff; + +assign qsfp_4_txd_1 = 64'h0707070707070707; +assign qsfp_4_txc_1 = 8'hff; +assign qsfp_4_txd_2 = 64'h0707070707070707; +assign qsfp_4_txc_2 = 8'hff; +assign qsfp_4_txd_3 = 64'h0707070707070707; +assign qsfp_4_txc_3 = 8'hff; +assign qsfp_4_txd_4 = 64'h0707070707070707; +assign qsfp_4_txc_4 = 8'hff; + +assign qsfp_5_txd_1 = 64'h0707070707070707; +assign qsfp_5_txc_1 = 8'hff; +assign qsfp_5_txd_2 = 64'h0707070707070707; +assign qsfp_5_txc_2 = 8'hff; +assign qsfp_5_txd_3 = 64'h0707070707070707; +assign qsfp_5_txc_3 = 8'hff; +assign qsfp_5_txd_4 = 64'h0707070707070707; +assign qsfp_5_txc_4 = 8'hff; + +assign qsfp_6_txd_1 = 64'h0707070707070707; +assign qsfp_6_txc_1 = 8'hff; +assign qsfp_6_txd_2 = 64'h0707070707070707; +assign qsfp_6_txc_2 = 8'hff; +assign qsfp_6_txd_3 = 64'h0707070707070707; +assign qsfp_6_txc_3 = 8'hff; +assign qsfp_6_txd_4 = 64'h0707070707070707; +assign qsfp_6_txc_4 = 8'hff; + +assign qsfp_7_txd_1 = 64'h0707070707070707; +assign qsfp_7_txc_1 = 8'hff; +assign qsfp_7_txd_2 = 64'h0707070707070707; +assign qsfp_7_txc_2 = 8'hff; +assign qsfp_7_txd_3 = 64'h0707070707070707; +assign qsfp_7_txc_3 = 8'hff; +assign qsfp_7_txd_4 = 64'h0707070707070707; +assign qsfp_7_txc_4 = 8'hff; + +assign qsfp_8_txd_1 = 64'h0707070707070707; +assign qsfp_8_txc_1 = 8'hff; +assign qsfp_8_txd_2 = 64'h0707070707070707; +assign qsfp_8_txc_2 = 8'hff; +assign qsfp_8_txd_3 = 64'h0707070707070707; +assign qsfp_8_txc_3 = 8'hff; +assign qsfp_8_txd_4 = 64'h0707070707070707; +assign qsfp_8_txc_4 = 8'hff; + +assign qsfp_9_txd_1 = 64'h0707070707070707; +assign qsfp_9_txc_1 = 8'hff; +assign qsfp_9_txd_2 = 64'h0707070707070707; +assign qsfp_9_txc_2 = 8'hff; +assign qsfp_9_txd_3 = 64'h0707070707070707; +assign qsfp_9_txc_3 = 8'hff; +assign qsfp_9_txd_4 = 64'h0707070707070707; +assign qsfp_9_txc_4 = 8'hff; + +assign fmc_qsfp_1_txd_1 = 64'h0707070707070707; +assign fmc_qsfp_1_txc_1 = 8'hff; +assign fmc_qsfp_1_txd_2 = 64'h0707070707070707; +assign fmc_qsfp_1_txc_2 = 8'hff; +assign fmc_qsfp_1_txd_3 = 64'h0707070707070707; +assign fmc_qsfp_1_txc_3 = 8'hff; +assign fmc_qsfp_1_txd_4 = 64'h0707070707070707; +assign fmc_qsfp_1_txc_4 = 8'hff; + +assign fmc_qsfp_2_txd_1 = 64'h0707070707070707; +assign fmc_qsfp_2_txc_1 = 8'hff; +assign fmc_qsfp_2_txd_2 = 64'h0707070707070707; +assign fmc_qsfp_2_txc_2 = 8'hff; +assign fmc_qsfp_2_txd_3 = 64'h0707070707070707; +assign fmc_qsfp_2_txc_3 = 8'hff; +assign fmc_qsfp_2_txd_4 = 64'h0707070707070707; +assign fmc_qsfp_2_txc_4 = 8'hff; + +assign fmc_qsfp_3_txd_1 = 64'h0707070707070707; +assign fmc_qsfp_3_txc_1 = 8'hff; +assign fmc_qsfp_3_txd_2 = 64'h0707070707070707; +assign fmc_qsfp_3_txc_2 = 8'hff; +assign fmc_qsfp_3_txd_3 = 64'h0707070707070707; +assign fmc_qsfp_3_txc_3 = 8'hff; +assign fmc_qsfp_3_txd_4 = 64'h0707070707070707; +assign fmc_qsfp_3_txc_4 = 8'hff; + +assign fmc_qsfp_4_txd_1 = 64'h0707070707070707; +assign fmc_qsfp_4_txc_1 = 8'hff; +assign fmc_qsfp_4_txd_2 = 64'h0707070707070707; +assign fmc_qsfp_4_txc_2 = 8'hff; +assign fmc_qsfp_4_txd_3 = 64'h0707070707070707; +assign fmc_qsfp_4_txc_3 = 8'hff; +assign fmc_qsfp_4_txd_4 = 64'h0707070707070707; +assign fmc_qsfp_4_txc_4 = 8'hff; + +assign fmc_qsfp_5_txd_1 = 64'h0707070707070707; +assign fmc_qsfp_5_txc_1 = 8'hff; +assign fmc_qsfp_5_txd_2 = 64'h0707070707070707; +assign fmc_qsfp_5_txc_2 = 8'hff; +assign fmc_qsfp_5_txd_3 = 64'h0707070707070707; +assign fmc_qsfp_5_txc_3 = 8'hff; +assign fmc_qsfp_5_txd_4 = 64'h0707070707070707; +assign fmc_qsfp_5_txc_4 = 8'hff; + +assign fmc_qsfp_6_txd_1 = 64'h0707070707070707; +assign fmc_qsfp_6_txc_1 = 8'hff; +assign fmc_qsfp_6_txd_2 = 64'h0707070707070707; +assign fmc_qsfp_6_txc_2 = 8'hff; +assign fmc_qsfp_6_txd_3 = 64'h0707070707070707; +assign fmc_qsfp_6_txc_3 = 8'hff; +assign fmc_qsfp_6_txd_4 = 64'h0707070707070707; +assign fmc_qsfp_6_txc_4 = 8'hff; + +eth_mac_10g_fifo #( + .ENABLE_PADDING(1), + .ENABLE_DIC(1), + .MIN_FRAME_LENGTH(64), + .TX_FIFO_DEPTH(4096), + .TX_FRAME_FIFO(1), + .RX_FIFO_DEPTH(4096), + .RX_FRAME_FIFO(1) +) +eth_mac_10g_fifo_inst ( + .rx_clk(qsfp_1_rx_clk_1), + .rx_rst(qsfp_1_rx_rst_1), + .tx_clk(qsfp_1_tx_clk_1), + .tx_rst(qsfp_1_tx_rst_1), + .logic_clk(clk), + .logic_rst(rst), + + .tx_axis_tdata(tx_axis_tdata), + .tx_axis_tkeep(tx_axis_tkeep), + .tx_axis_tvalid(tx_axis_tvalid), + .tx_axis_tready(tx_axis_tready), + .tx_axis_tlast(tx_axis_tlast), + .tx_axis_tuser(tx_axis_tuser), + + .rx_axis_tdata(rx_axis_tdata), + .rx_axis_tkeep(rx_axis_tkeep), + .rx_axis_tvalid(rx_axis_tvalid), + .rx_axis_tready(rx_axis_tready), + .rx_axis_tlast(rx_axis_tlast), + .rx_axis_tuser(rx_axis_tuser), + + .xgmii_rxd(qsfp_1_rxd_1), + .xgmii_rxc(qsfp_1_rxc_1), + .xgmii_txd(qsfp_1_txd_1), + .xgmii_txc(qsfp_1_txc_1), + + .tx_fifo_overflow(), + .tx_fifo_bad_frame(), + .tx_fifo_good_frame(), + .rx_error_bad_frame(), + .rx_error_bad_fcs(), + .rx_fifo_overflow(), + .rx_fifo_bad_frame(), + .rx_fifo_good_frame(), + + .ifg_delay(8'd12) +); + +eth_axis_rx #( + .DATA_WIDTH(64) +) +eth_axis_rx_inst ( + .clk(clk), + .rst(rst), + // AXI input + .s_axis_tdata(rx_axis_tdata), + .s_axis_tkeep(rx_axis_tkeep), + .s_axis_tvalid(rx_axis_tvalid), + .s_axis_tready(rx_axis_tready), + .s_axis_tlast(rx_axis_tlast), + .s_axis_tuser(rx_axis_tuser), + // Ethernet frame output + .m_eth_hdr_valid(rx_eth_hdr_valid), + .m_eth_hdr_ready(rx_eth_hdr_ready), + .m_eth_dest_mac(rx_eth_dest_mac), + .m_eth_src_mac(rx_eth_src_mac), + .m_eth_type(rx_eth_type), + .m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), + .m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep), + .m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), + .m_eth_payload_axis_tready(rx_eth_payload_axis_tready), + .m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), + .m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), + // Status signals + .busy(), + .error_header_early_termination() +); + +eth_axis_tx #( + .DATA_WIDTH(64) +) +eth_axis_tx_inst ( + .clk(clk), + .rst(rst), + // Ethernet frame input + .s_eth_hdr_valid(tx_eth_hdr_valid), + .s_eth_hdr_ready(tx_eth_hdr_ready), + .s_eth_dest_mac(tx_eth_dest_mac), + .s_eth_src_mac(tx_eth_src_mac), + .s_eth_type(tx_eth_type), + .s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), + .s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep), + .s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), + .s_eth_payload_axis_tready(tx_eth_payload_axis_tready), + .s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), + .s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), + // AXI output + .m_axis_tdata(tx_axis_tdata), + .m_axis_tkeep(tx_axis_tkeep), + .m_axis_tvalid(tx_axis_tvalid), + .m_axis_tready(tx_axis_tready), + .m_axis_tlast(tx_axis_tlast), + .m_axis_tuser(tx_axis_tuser), + // Status signals + .busy() +); + +udp_complete_64 +udp_complete_inst ( + .clk(clk), + .rst(rst), + // Ethernet frame input + .s_eth_hdr_valid(rx_eth_hdr_valid), + .s_eth_hdr_ready(rx_eth_hdr_ready), + .s_eth_dest_mac(rx_eth_dest_mac), + .s_eth_src_mac(rx_eth_src_mac), + .s_eth_type(rx_eth_type), + .s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), + .s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep), + .s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), + .s_eth_payload_axis_tready(rx_eth_payload_axis_tready), + .s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), + .s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), + // Ethernet frame output + .m_eth_hdr_valid(tx_eth_hdr_valid), + .m_eth_hdr_ready(tx_eth_hdr_ready), + .m_eth_dest_mac(tx_eth_dest_mac), + .m_eth_src_mac(tx_eth_src_mac), + .m_eth_type(tx_eth_type), + .m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), + .m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep), + .m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), + .m_eth_payload_axis_tready(tx_eth_payload_axis_tready), + .m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), + .m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), + // IP frame input + .s_ip_hdr_valid(tx_ip_hdr_valid), + .s_ip_hdr_ready(tx_ip_hdr_ready), + .s_ip_dscp(tx_ip_dscp), + .s_ip_ecn(tx_ip_ecn), + .s_ip_length(tx_ip_length), + .s_ip_ttl(tx_ip_ttl), + .s_ip_protocol(tx_ip_protocol), + .s_ip_source_ip(tx_ip_source_ip), + .s_ip_dest_ip(tx_ip_dest_ip), + .s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata), + .s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep), + .s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid), + .s_ip_payload_axis_tready(tx_ip_payload_axis_tready), + .s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast), + .s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser), + // IP frame output + .m_ip_hdr_valid(rx_ip_hdr_valid), + .m_ip_hdr_ready(rx_ip_hdr_ready), + .m_ip_eth_dest_mac(rx_ip_eth_dest_mac), + .m_ip_eth_src_mac(rx_ip_eth_src_mac), + .m_ip_eth_type(rx_ip_eth_type), + .m_ip_version(rx_ip_version), + .m_ip_ihl(rx_ip_ihl), + .m_ip_dscp(rx_ip_dscp), + .m_ip_ecn(rx_ip_ecn), + .m_ip_length(rx_ip_length), + .m_ip_identification(rx_ip_identification), + .m_ip_flags(rx_ip_flags), + .m_ip_fragment_offset(rx_ip_fragment_offset), + .m_ip_ttl(rx_ip_ttl), + .m_ip_protocol(rx_ip_protocol), + .m_ip_header_checksum(rx_ip_header_checksum), + .m_ip_source_ip(rx_ip_source_ip), + .m_ip_dest_ip(rx_ip_dest_ip), + .m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata), + .m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep), + .m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid), + .m_ip_payload_axis_tready(rx_ip_payload_axis_tready), + .m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast), + .m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser), + // UDP frame input + .s_udp_hdr_valid(tx_udp_hdr_valid), + .s_udp_hdr_ready(tx_udp_hdr_ready), + .s_udp_ip_dscp(tx_udp_ip_dscp), + .s_udp_ip_ecn(tx_udp_ip_ecn), + .s_udp_ip_ttl(tx_udp_ip_ttl), + .s_udp_ip_source_ip(tx_udp_ip_source_ip), + .s_udp_ip_dest_ip(tx_udp_ip_dest_ip), + .s_udp_source_port(tx_udp_source_port), + .s_udp_dest_port(tx_udp_dest_port), + .s_udp_length(tx_udp_length), + .s_udp_checksum(tx_udp_checksum), + .s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata), + .s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep), + .s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid), + .s_udp_payload_axis_tready(tx_udp_payload_axis_tready), + .s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast), + .s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser), + // UDP frame output + .m_udp_hdr_valid(rx_udp_hdr_valid), + .m_udp_hdr_ready(rx_udp_hdr_ready), + .m_udp_eth_dest_mac(rx_udp_eth_dest_mac), + .m_udp_eth_src_mac(rx_udp_eth_src_mac), + .m_udp_eth_type(rx_udp_eth_type), + .m_udp_ip_version(rx_udp_ip_version), + .m_udp_ip_ihl(rx_udp_ip_ihl), + .m_udp_ip_dscp(rx_udp_ip_dscp), + .m_udp_ip_ecn(rx_udp_ip_ecn), + .m_udp_ip_length(rx_udp_ip_length), + .m_udp_ip_identification(rx_udp_ip_identification), + .m_udp_ip_flags(rx_udp_ip_flags), + .m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset), + .m_udp_ip_ttl(rx_udp_ip_ttl), + .m_udp_ip_protocol(rx_udp_ip_protocol), + .m_udp_ip_header_checksum(rx_udp_ip_header_checksum), + .m_udp_ip_source_ip(rx_udp_ip_source_ip), + .m_udp_ip_dest_ip(rx_udp_ip_dest_ip), + .m_udp_source_port(rx_udp_source_port), + .m_udp_dest_port(rx_udp_dest_port), + .m_udp_length(rx_udp_length), + .m_udp_checksum(rx_udp_checksum), + .m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata), + .m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep), + .m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid), + .m_udp_payload_axis_tready(rx_udp_payload_axis_tready), + .m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast), + .m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser), + // Status signals + .ip_rx_busy(), + .ip_tx_busy(), + .udp_rx_busy(), + .udp_tx_busy(), + .ip_rx_error_header_early_termination(), + .ip_rx_error_payload_early_termination(), + .ip_rx_error_invalid_header(), + .ip_rx_error_invalid_checksum(), + .ip_tx_error_payload_early_termination(), + .ip_tx_error_arp_failed(), + .udp_rx_error_header_early_termination(), + .udp_rx_error_payload_early_termination(), + .udp_tx_error_payload_early_termination(), + // Configuration + .local_mac(local_mac), + .local_ip(local_ip), + .gateway_ip(gateway_ip), + .subnet_mask(subnet_mask), + .clear_arp_cache(1'b0) +); + +axis_fifo #( + .DEPTH(8192), + .DATA_WIDTH(64), + .KEEP_ENABLE(1), + .KEEP_WIDTH(8), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(1), + .FRAME_FIFO(0) +) +udp_payload_fifo ( + .clk(clk), + .rst(rst), + + // AXI input + .s_axis_tdata(rx_fifo_udp_payload_axis_tdata), + .s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep), + .s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid), + .s_axis_tready(rx_fifo_udp_payload_axis_tready), + .s_axis_tlast(rx_fifo_udp_payload_axis_tlast), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(rx_fifo_udp_payload_axis_tuser), + + // AXI output + .m_axis_tdata(tx_fifo_udp_payload_axis_tdata), + .m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep), + .m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid), + .m_axis_tready(tx_fifo_udp_payload_axis_tready), + .m_axis_tlast(tx_fifo_udp_payload_axis_tlast), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(tx_fifo_udp_payload_axis_tuser), + + // Status + .status_overflow(), + .status_bad_frame(), + .status_good_frame() +); + +endmodule + +`resetall diff --git a/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/i2c_master.v b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/i2c_master.v new file mode 100644 index 000000000..b933316a1 --- /dev/null +++ b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/i2c_master.v @@ -0,0 +1,901 @@ +/* + +Copyright (c) 2015-2017 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * I2C master + */ +module i2c_master ( + input wire clk, + input wire rst, + + /* + * Host interface + */ + input wire [6:0] s_axis_cmd_address, + input wire s_axis_cmd_start, + input wire s_axis_cmd_read, + input wire s_axis_cmd_write, + input wire s_axis_cmd_write_multiple, + input wire s_axis_cmd_stop, + input wire s_axis_cmd_valid, + output wire s_axis_cmd_ready, + + input wire [7:0] s_axis_data_tdata, + input wire s_axis_data_tvalid, + output wire s_axis_data_tready, + input wire s_axis_data_tlast, + + output wire [7:0] m_axis_data_tdata, + output wire m_axis_data_tvalid, + input wire m_axis_data_tready, + output wire m_axis_data_tlast, + + /* + * I2C interface + */ + input wire scl_i, + output wire scl_o, + output wire scl_t, + input wire sda_i, + output wire sda_o, + output wire sda_t, + + /* + * Status + */ + output wire busy, + output wire bus_control, + output wire bus_active, + output wire missed_ack, + + /* + * Configuration + */ + input wire [15:0] prescale, + input wire stop_on_idle +); + +/* + +I2C + +Read + __ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __ +sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_\_R___A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A____/ + ____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____ +scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP + +Write + __ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __ +sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_/ W \_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_/ N \__/ + ____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____ +scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP + +Commands: + +read + read data byte + set start to force generation of a start condition + start is implied when bus is inactive or active with write or different address + set stop to issue a stop condition after reading current byte + if stop is set with read command, then m_axis_data_tlast will be set + +write + write data byte + set start to force generation of a start condition + start is implied when bus is inactive or active with read or different address + set stop to issue a stop condition after writing current byte + +write multiple + write multiple data bytes (until s_axis_data_tlast) + set start to force generation of a start condition + start is implied when bus is inactive or active with read or different address + set stop to issue a stop condition after writing block + +stop + issue stop condition if bus is active + +Status: + +busy + module is communicating over the bus + +bus_control + module has control of bus in active state + +bus_active + bus is active, not necessarily controlled by this module + +missed_ack + strobed when a slave ack is missed + +Parameters: + +prescale + set prescale to 1/4 of the minimum clock period in units + of input clk cycles (prescale = Fclk / (FI2Cclk * 4)) + +stop_on_idle + automatically issue stop when command input is not valid + +Example of interfacing with tristate pins: +(this will work for any tristate bus) + +assign scl_i = scl_pin; +assign scl_pin = scl_t ? 1'bz : scl_o; +assign sda_i = sda_pin; +assign sda_pin = sda_t ? 1'bz : sda_o; + +Equivalent code that does not use *_t connections: +(we can get away with this because I2C is open-drain) + +assign scl_i = scl_pin; +assign scl_pin = scl_o ? 1'bz : 1'b0; +assign sda_i = sda_pin; +assign sda_pin = sda_o ? 1'bz : 1'b0; + +Example of two interconnected I2C devices: + +assign scl_1_i = scl_1_o & scl_2_o; +assign scl_2_i = scl_1_o & scl_2_o; +assign sda_1_i = sda_1_o & sda_2_o; +assign sda_2_i = sda_1_o & sda_2_o; + +Example of two I2C devices sharing the same pins: + +assign scl_1_i = scl_pin; +assign scl_2_i = scl_pin; +assign scl_pin = (scl_1_o & scl_2_o) ? 1'bz : 1'b0; +assign sda_1_i = sda_pin; +assign sda_2_i = sda_pin; +assign sda_pin = (sda_1_o & sda_2_o) ? 1'bz : 1'b0; + +Notes: + +scl_o should not be connected directly to scl_i, only via AND logic or a tristate +I/O pin. This would prevent devices from stretching the clock period. + +*/ + +localparam [4:0] + STATE_IDLE = 4'd0, + STATE_ACTIVE_WRITE = 4'd1, + STATE_ACTIVE_READ = 4'd2, + STATE_START_WAIT = 4'd3, + STATE_START = 4'd4, + STATE_ADDRESS_1 = 4'd5, + STATE_ADDRESS_2 = 4'd6, + STATE_WRITE_1 = 4'd7, + STATE_WRITE_2 = 4'd8, + STATE_WRITE_3 = 4'd9, + STATE_READ = 4'd10, + STATE_STOP = 4'd11; + +reg [4:0] state_reg = STATE_IDLE, state_next; + +localparam [4:0] + PHY_STATE_IDLE = 5'd0, + PHY_STATE_ACTIVE = 5'd1, + PHY_STATE_REPEATED_START_1 = 5'd2, + PHY_STATE_REPEATED_START_2 = 5'd3, + PHY_STATE_START_1 = 5'd4, + PHY_STATE_START_2 = 5'd5, + PHY_STATE_WRITE_BIT_1 = 5'd6, + PHY_STATE_WRITE_BIT_2 = 5'd7, + PHY_STATE_WRITE_BIT_3 = 5'd8, + PHY_STATE_READ_BIT_1 = 5'd9, + PHY_STATE_READ_BIT_2 = 5'd10, + PHY_STATE_READ_BIT_3 = 5'd11, + PHY_STATE_READ_BIT_4 = 5'd12, + PHY_STATE_STOP_1 = 5'd13, + PHY_STATE_STOP_2 = 5'd14, + PHY_STATE_STOP_3 = 5'd15; + +reg [4:0] phy_state_reg = STATE_IDLE, phy_state_next; + +reg phy_start_bit; +reg phy_stop_bit; +reg phy_write_bit; +reg phy_read_bit; +reg phy_release_bus; + +reg phy_tx_data; + +reg phy_rx_data_reg = 1'b0, phy_rx_data_next; + +reg [6:0] addr_reg = 7'd0, addr_next; +reg [7:0] data_reg = 8'd0, data_next; +reg last_reg = 1'b0, last_next; + +reg mode_read_reg = 1'b0, mode_read_next; +reg mode_write_multiple_reg = 1'b0, mode_write_multiple_next; +reg mode_stop_reg = 1'b0, mode_stop_next; + +reg [16:0] delay_reg = 16'd0, delay_next; +reg delay_scl_reg = 1'b0, delay_scl_next; +reg delay_sda_reg = 1'b0, delay_sda_next; + +reg [3:0] bit_count_reg = 4'd0, bit_count_next; + +reg s_axis_cmd_ready_reg = 1'b0, s_axis_cmd_ready_next; + +reg s_axis_data_tready_reg = 1'b0, s_axis_data_tready_next; + +reg [7:0] m_axis_data_tdata_reg = 8'd0, m_axis_data_tdata_next; +reg m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next; +reg m_axis_data_tlast_reg = 1'b0, m_axis_data_tlast_next; + +reg scl_i_reg = 1'b1; +reg sda_i_reg = 1'b1; + +reg scl_o_reg = 1'b1, scl_o_next; +reg sda_o_reg = 1'b1, sda_o_next; + +reg last_scl_i_reg = 1'b1; +reg last_sda_i_reg = 1'b1; + +reg busy_reg = 1'b0; +reg bus_active_reg = 1'b0; +reg bus_control_reg = 1'b0, bus_control_next; +reg missed_ack_reg = 1'b0, missed_ack_next; + +assign s_axis_cmd_ready = s_axis_cmd_ready_reg; + +assign s_axis_data_tready = s_axis_data_tready_reg; + +assign m_axis_data_tdata = m_axis_data_tdata_reg; +assign m_axis_data_tvalid = m_axis_data_tvalid_reg; +assign m_axis_data_tlast = m_axis_data_tlast_reg; + +assign scl_o = scl_o_reg; +assign scl_t = scl_o_reg; +assign sda_o = sda_o_reg; +assign sda_t = sda_o_reg; + +assign busy = busy_reg; +assign bus_active = bus_active_reg; +assign bus_control = bus_control_reg; +assign missed_ack = missed_ack_reg; + +wire scl_posedge = scl_i_reg & ~last_scl_i_reg; +wire scl_negedge = ~scl_i_reg & last_scl_i_reg; +wire sda_posedge = sda_i_reg & ~last_sda_i_reg; +wire sda_negedge = ~sda_i_reg & last_sda_i_reg; + +wire start_bit = sda_negedge & scl_i_reg; +wire stop_bit = sda_posedge & scl_i_reg; + +always @* begin + state_next = STATE_IDLE; + + phy_start_bit = 1'b0; + phy_stop_bit = 1'b0; + phy_write_bit = 1'b0; + phy_read_bit = 1'b0; + phy_tx_data = 1'b0; + phy_release_bus = 1'b0; + + addr_next = addr_reg; + data_next = data_reg; + last_next = last_reg; + + mode_read_next = mode_read_reg; + mode_write_multiple_next = mode_write_multiple_reg; + mode_stop_next = mode_stop_reg; + + bit_count_next = bit_count_reg; + + s_axis_cmd_ready_next = 1'b0; + + s_axis_data_tready_next = 1'b0; + + m_axis_data_tdata_next = m_axis_data_tdata_reg; + m_axis_data_tvalid_next = m_axis_data_tvalid_reg & ~m_axis_data_tready; + m_axis_data_tlast_next = m_axis_data_tlast_reg; + + missed_ack_next = 1'b0; + + // generate delays + if (phy_state_reg != PHY_STATE_IDLE && phy_state_reg != PHY_STATE_ACTIVE) begin + // wait for phy operation + state_next = state_reg; + end else begin + // process states + case (state_reg) + STATE_IDLE: begin + // line idle + s_axis_cmd_ready_next = 1'b1; + + if (s_axis_cmd_ready & s_axis_cmd_valid) begin + // command valid + if (s_axis_cmd_read ^ (s_axis_cmd_write | s_axis_cmd_write_multiple)) begin + // read or write command + addr_next = s_axis_cmd_address; + mode_read_next = s_axis_cmd_read; + mode_write_multiple_next = s_axis_cmd_write_multiple; + mode_stop_next = s_axis_cmd_stop; + + s_axis_cmd_ready_next = 1'b0; + + // start bit + if (bus_active) begin + state_next = STATE_START_WAIT; + end else begin + phy_start_bit = 1'b1; + bit_count_next = 4'd8; + state_next = STATE_ADDRESS_1; + end + end else begin + // invalid or unspecified - ignore + state_next = STATE_IDLE; + end + end else begin + state_next = STATE_IDLE; + end + end + STATE_ACTIVE_WRITE: begin + // line active with current address and read/write mode + s_axis_cmd_ready_next = 1'b1; + + if (s_axis_cmd_ready & s_axis_cmd_valid) begin + // command valid + if (s_axis_cmd_read ^ (s_axis_cmd_write | s_axis_cmd_write_multiple)) begin + // read or write command + addr_next = s_axis_cmd_address; + mode_read_next = s_axis_cmd_read; + mode_write_multiple_next = s_axis_cmd_write_multiple; + mode_stop_next = s_axis_cmd_stop; + + s_axis_cmd_ready_next = 1'b0; + + if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_read) begin + // address or mode mismatch or forced start - repeated start + + // repeated start bit + phy_start_bit = 1'b1; + bit_count_next = 4'd8; + state_next = STATE_ADDRESS_1; + end else begin + // address and mode match + + // start write + s_axis_data_tready_next = 1'b1; + state_next = STATE_WRITE_1; + end + end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multiple)) begin + // stop command + phy_stop_bit = 1'b1; + state_next = STATE_IDLE; + end else begin + // invalid or unspecified - ignore + state_next = STATE_ACTIVE_WRITE; + end + end else begin + if (stop_on_idle & s_axis_cmd_ready & ~s_axis_cmd_valid) begin + // no waiting command and stop_on_idle selected, issue stop condition + phy_stop_bit = 1'b1; + state_next = STATE_IDLE; + end else begin + state_next = STATE_ACTIVE_WRITE; + end + end + end + STATE_ACTIVE_READ: begin + // line active to current address + s_axis_cmd_ready_next = ~m_axis_data_tvalid; + + if (s_axis_cmd_ready & s_axis_cmd_valid) begin + // command valid + if (s_axis_cmd_read ^ (s_axis_cmd_write | s_axis_cmd_write_multiple)) begin + // read or write command + addr_next = s_axis_cmd_address; + mode_read_next = s_axis_cmd_read; + mode_write_multiple_next = s_axis_cmd_write_multiple; + mode_stop_next = s_axis_cmd_stop; + + s_axis_cmd_ready_next = 1'b0; + + if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_write) begin + // address or mode mismatch or forced start - repeated start + + // write nack for previous read + phy_write_bit = 1'b1; + phy_tx_data = 1'b1; + // repeated start bit + state_next = STATE_START; + end else begin + // address and mode match + + // write ack for previous read + phy_write_bit = 1'b1; + phy_tx_data = 1'b0; + // start next read + bit_count_next = 4'd8; + data_next = 8'd0; + state_next = STATE_READ; + end + end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multiple)) begin + // stop command + // write nack for previous read + phy_write_bit = 1'b1; + phy_tx_data = 1'b1; + // send stop bit + state_next = STATE_STOP; + end else begin + // invalid or unspecified - ignore + state_next = STATE_ACTIVE_READ; + end + end else begin + if (stop_on_idle & s_axis_cmd_ready & ~s_axis_cmd_valid) begin + // no waiting command and stop_on_idle selected, issue stop condition + // write ack for previous read + phy_write_bit = 1'b1; + phy_tx_data = 1'b1; + // send stop bit + state_next = STATE_STOP; + end else begin + state_next = STATE_ACTIVE_READ; + end + end + end + STATE_START_WAIT: begin + // wait for bus idle + + if (bus_active) begin + state_next = STATE_START_WAIT; + end else begin + // bus is idle, take control + phy_start_bit = 1'b1; + bit_count_next = 4'd8; + state_next = STATE_ADDRESS_1; + end + end + STATE_START: begin + // send start bit + + phy_start_bit = 1'b1; + bit_count_next = 4'd8; + state_next = STATE_ADDRESS_1; + end + STATE_ADDRESS_1: begin + // send address + bit_count_next = bit_count_reg - 1; + if (bit_count_reg > 1) begin + // send address + phy_write_bit = 1'b1; + phy_tx_data = addr_reg[bit_count_reg-2]; + state_next = STATE_ADDRESS_1; + end else if (bit_count_reg > 0) begin + // send read/write bit + phy_write_bit = 1'b1; + phy_tx_data = mode_read_reg; + state_next = STATE_ADDRESS_1; + end else begin + // read ack bit + phy_read_bit = 1'b1; + state_next = STATE_ADDRESS_2; + end + end + STATE_ADDRESS_2: begin + // read ack bit + missed_ack_next = phy_rx_data_reg; + + if (mode_read_reg) begin + // start read + bit_count_next = 4'd8; + data_next = 1'b0; + state_next = STATE_READ; + end else begin + // start write + s_axis_data_tready_next = 1'b1; + state_next = STATE_WRITE_1; + end + end + STATE_WRITE_1: begin + s_axis_data_tready_next = 1'b1; + + if (s_axis_data_tready & s_axis_data_tvalid) begin + // got data, start write + data_next = s_axis_data_tdata; + last_next = s_axis_data_tlast; + bit_count_next = 4'd8; + s_axis_data_tready_next = 1'b0; + state_next = STATE_WRITE_2; + end else begin + // wait for data + state_next = STATE_WRITE_1; + end + end + STATE_WRITE_2: begin + // send data + bit_count_next = bit_count_reg - 1; + if (bit_count_reg > 0) begin + // write data bit + phy_write_bit = 1'b1; + phy_tx_data = data_reg[bit_count_reg-1]; + state_next = STATE_WRITE_2; + end else begin + // read ack bit + phy_read_bit = 1'b1; + state_next = STATE_WRITE_3; + end + end + STATE_WRITE_3: begin + // read ack bit + missed_ack_next = phy_rx_data_reg; + + if (mode_write_multiple_reg && !last_reg) begin + // more to write + state_next = STATE_WRITE_1; + end else if (mode_stop_reg) begin + // last cycle and stop selected + phy_stop_bit = 1'b1; + state_next = STATE_IDLE; + end else begin + // otherwise, return to bus active state + state_next = STATE_ACTIVE_WRITE; + end + end + STATE_READ: begin + // read data + + bit_count_next = bit_count_reg - 1; + data_next = {data_reg[6:0], phy_rx_data_reg}; + if (bit_count_reg > 0) begin + // read next bit + phy_read_bit = 1'b1; + state_next = STATE_READ; + end else begin + // output data word + m_axis_data_tdata_next = data_next; + m_axis_data_tvalid_next = 1'b1; + m_axis_data_tlast_next = 1'b0; + if (mode_stop_reg) begin + // send nack and stop + m_axis_data_tlast_next = 1'b1; + phy_write_bit = 1'b1; + phy_tx_data = 1'b1; + state_next = STATE_STOP; + end else begin + // return to bus active state + state_next = STATE_ACTIVE_READ; + end + end + end + STATE_STOP: begin + // send stop bit + phy_stop_bit = 1'b1; + state_next = STATE_IDLE; + end + endcase + end +end + +always @* begin + phy_state_next = PHY_STATE_IDLE; + + phy_rx_data_next = phy_rx_data_reg; + + delay_next = delay_reg; + delay_scl_next = delay_scl_reg; + delay_sda_next = delay_sda_reg; + + scl_o_next = scl_o_reg; + sda_o_next = sda_o_reg; + + bus_control_next = bus_control_reg; + + if (phy_release_bus) begin + // release bus and return to idle state + sda_o_next = 1'b1; + scl_o_next = 1'b1; + delay_scl_next = 1'b0; + delay_sda_next = 1'b0; + delay_next = 1'b0; + phy_state_next = PHY_STATE_IDLE; + end else if (delay_scl_reg) begin + // wait for SCL to match command + delay_scl_next = scl_o_reg & ~scl_i_reg; + phy_state_next = phy_state_reg; + end else if (delay_sda_reg) begin + // wait for SDA to match command + delay_sda_next = sda_o_reg & ~sda_i_reg; + phy_state_next = phy_state_reg; + end else if (delay_reg > 0) begin + // time delay + delay_next = delay_reg - 1; + phy_state_next = phy_state_reg; + end else begin + case (phy_state_reg) + PHY_STATE_IDLE: begin + // bus idle - wait for start command + sda_o_next = 1'b1; + scl_o_next = 1'b1; + if (phy_start_bit) begin + sda_o_next = 1'b0; + delay_next = prescale; + phy_state_next = PHY_STATE_START_1; + end else begin + phy_state_next = PHY_STATE_IDLE; + end + end + PHY_STATE_ACTIVE: begin + // bus active + if (phy_start_bit) begin + sda_o_next = 1'b1; + delay_next = prescale; + phy_state_next = PHY_STATE_REPEATED_START_1; + end else if (phy_write_bit) begin + sda_o_next = phy_tx_data; + delay_next = prescale; + phy_state_next = PHY_STATE_WRITE_BIT_1; + end else if (phy_read_bit) begin + sda_o_next = 1'b1; + delay_next = prescale; + phy_state_next = PHY_STATE_READ_BIT_1; + end else if (phy_stop_bit) begin + sda_o_next = 1'b0; + delay_next = prescale; + phy_state_next = PHY_STATE_STOP_1; + end else begin + phy_state_next = PHY_STATE_ACTIVE; + end + end + PHY_STATE_REPEATED_START_1: begin + // generate repeated start bit + // ______ + // sda XXX/ \_______ + // _______ + // scl ______/ \___ + // + + scl_o_next = 1'b1; + delay_scl_next = 1'b1; + delay_next = prescale; + phy_state_next = PHY_STATE_REPEATED_START_2; + end + PHY_STATE_REPEATED_START_2: begin + // generate repeated start bit + // ______ + // sda XXX/ \_______ + // _______ + // scl ______/ \___ + // + + sda_o_next = 1'b0; + delay_next = prescale; + phy_state_next = PHY_STATE_START_1; + end + PHY_STATE_START_1: begin + // generate start bit + // ___ + // sda \_______ + // _______ + // scl \___ + // + + scl_o_next = 1'b0; + delay_next = prescale; + phy_state_next = PHY_STATE_START_2; + end + PHY_STATE_START_2: begin + // generate start bit + // ___ + // sda \_______ + // _______ + // scl \___ + // + + bus_control_next = 1'b1; + phy_state_next = PHY_STATE_ACTIVE; + end + PHY_STATE_WRITE_BIT_1: begin + // write bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + scl_o_next = 1'b1; + delay_scl_next = 1'b1; + delay_next = prescale << 1; + phy_state_next = PHY_STATE_WRITE_BIT_2; + end + PHY_STATE_WRITE_BIT_2: begin + // write bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + scl_o_next = 1'b0; + delay_next = prescale; + phy_state_next = PHY_STATE_WRITE_BIT_3; + end + PHY_STATE_WRITE_BIT_3: begin + // write bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + phy_state_next = PHY_STATE_ACTIVE; + end + PHY_STATE_READ_BIT_1: begin + // read bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + scl_o_next = 1'b1; + delay_scl_next = 1'b1; + delay_next = prescale; + phy_state_next = PHY_STATE_READ_BIT_2; + end + PHY_STATE_READ_BIT_2: begin + // read bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + phy_rx_data_next = sda_i_reg; + delay_next = prescale; + phy_state_next = PHY_STATE_READ_BIT_3; + end + PHY_STATE_READ_BIT_3: begin + // read bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + scl_o_next = 1'b0; + delay_next = prescale; + phy_state_next = PHY_STATE_READ_BIT_4; + end + PHY_STATE_READ_BIT_4: begin + // read bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + phy_state_next = PHY_STATE_ACTIVE; + end + PHY_STATE_STOP_1: begin + // stop bit + // ___ + // sda XXX\_______/ + // _______ + // scl _______/ + + scl_o_next = 1'b1; + delay_scl_next = 1'b1; + delay_next = prescale; + phy_state_next = PHY_STATE_STOP_2; + end + PHY_STATE_STOP_2: begin + // stop bit + // ___ + // sda XXX\_______/ + // _______ + // scl _______/ + + sda_o_next = 1'b1; + delay_next = prescale; + phy_state_next = PHY_STATE_STOP_3; + end + PHY_STATE_STOP_3: begin + // stop bit + // ___ + // sda XXX\_______/ + // _______ + // scl _______/ + + bus_control_next = 1'b0; + phy_state_next = PHY_STATE_IDLE; + end + endcase + end +end + +always @(posedge clk) begin + state_reg <= state_next; + phy_state_reg <= phy_state_next; + + phy_rx_data_reg <= phy_rx_data_next; + + addr_reg <= addr_next; + data_reg <= data_next; + last_reg <= last_next; + + mode_read_reg <= mode_read_next; + mode_write_multiple_reg <= mode_write_multiple_next; + mode_stop_reg <= mode_stop_next; + + delay_reg <= delay_next; + delay_scl_reg <= delay_scl_next; + delay_sda_reg <= delay_sda_next; + + bit_count_reg <= bit_count_next; + + s_axis_cmd_ready_reg <= s_axis_cmd_ready_next; + + s_axis_data_tready_reg <= s_axis_data_tready_next; + + m_axis_data_tdata_reg <= m_axis_data_tdata_next; + m_axis_data_tlast_reg <= m_axis_data_tlast_next; + m_axis_data_tvalid_reg <= m_axis_data_tvalid_next; + + scl_i_reg <= scl_i; + sda_i_reg <= sda_i; + + scl_o_reg <= scl_o_next; + sda_o_reg <= sda_o_next; + + last_scl_i_reg <= scl_i_reg; + last_sda_i_reg <= sda_i_reg; + + busy_reg <= !(state_reg == STATE_IDLE || state_reg == STATE_ACTIVE_WRITE || state_reg == STATE_ACTIVE_READ) || !(phy_state_reg == PHY_STATE_IDLE || phy_state_reg == PHY_STATE_ACTIVE); + + if (start_bit) begin + bus_active_reg <= 1'b1; + end else if (stop_bit) begin + bus_active_reg <= 1'b0; + end else begin + bus_active_reg <= bus_active_reg; + end + + bus_control_reg <= bus_control_next; + missed_ack_reg <= missed_ack_next; + + if (rst) begin + state_reg <= STATE_IDLE; + phy_state_reg <= PHY_STATE_IDLE; + delay_reg <= 16'd0; + delay_scl_reg <= 1'b0; + delay_sda_reg <= 1'b0; + s_axis_cmd_ready_reg <= 1'b0; + s_axis_data_tready_reg <= 1'b0; + m_axis_data_tvalid_reg <= 1'b0; + scl_o_reg <= 1'b1; + sda_o_reg <= 1'b1; + busy_reg <= 1'b0; + bus_active_reg <= 1'b0; + bus_control_reg <= 1'b0; + missed_ack_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/fpga/lib/eth/example/fb2CG/fpga_10g/rtl/sync_signal.v b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/sync_signal.v similarity index 97% rename from fpga/lib/eth/example/fb2CG/fpga_10g/rtl/sync_signal.v rename to fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/sync_signal.v index 74b855fa1..645319304 100644 --- a/fpga/lib/eth/example/fb2CG/fpga_10g/rtl/sync_signal.v +++ b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/sync_signal.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2014-2018 Alex Forencich +Copyright (c) 2014-2017 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal diff --git a/fpga/lib/eth/example/HXT100G/fpga/tb/fpga_core/Makefile b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/Makefile similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga/tb/fpga_core/Makefile rename to fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/Makefile diff --git a/fpga/lib/eth/example/HXT100G/fpga/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/test_fpga_core.py similarity index 56% rename from fpga/lib/eth/example/HXT100G/fpga/tb/fpga_core/test_fpga_core.py rename to fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/test_fpga_core.py index a4698680d..11a30cd4a 100644 --- a/fpga/lib/eth/example/HXT100G/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/test_fpga_core.py @@ -45,103 +45,84 @@ class TB: self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) - cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) + cocotb.start_soon(Clock(dut.clk, 2.56, units="ns").start()) + + dut.btn.setimmediatevalue(0) + dut.sw.setimmediatevalue(0) + + dut.uart_txd.setimmediatevalue(1) + dut.uart_rts.setimmediatevalue(1) # Ethernet - self.eth_r0_source = XgmiiSource(dut.eth_r0_rxd, dut.eth_r0_rxc, dut.clk, dut.rst) - self.eth_r0_sink = XgmiiSink(dut.eth_r0_txd, dut.eth_r0_txc, dut.clk, dut.rst) + self.qsfp_source = [] + self.qsfp_sink = [] - self.eth_r1_source = XgmiiSource(dut.eth_r1_rxd, dut.eth_r1_rxc, dut.clk, dut.rst) - self.eth_r1_sink = XgmiiSink(dut.eth_r1_txd, dut.eth_r1_txc, dut.clk, dut.rst) + for x in range(1, 10): + sources = [] + sinks = [] + for y in range(1, 5): + cocotb.start_soon(Clock(getattr(dut, f"qsfp_{x}_rx_clk_{y}"), 2.56, units="ns").start()) + source = XgmiiSource(getattr(dut, f"qsfp_{x}_rxd_{y}"), getattr(dut, f"qsfp_{x}_rxc_{y}"), getattr(dut, f"qsfp_{x}_rx_clk_{y}"), getattr(dut, f"qsfp_{x}_rx_rst_{y}")) + sources.append(source) + cocotb.start_soon(Clock(getattr(dut, f"qsfp_{x}_tx_clk_{y}"), 2.56, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"qsfp_{x}_txd_{y}"), getattr(dut, f"qsfp_{x}_txc_{y}"), getattr(dut, f"qsfp_{x}_tx_clk_{y}"), getattr(dut, f"qsfp_{x}_tx_rst_{y}")) + sinks.append(sink) + self.qsfp_source.append(sources) + self.qsfp_sink.append(sinks) - self.eth_r2_source = XgmiiSource(dut.eth_r2_rxd, dut.eth_r2_rxc, dut.clk, dut.rst) - self.eth_r2_sink = XgmiiSink(dut.eth_r2_txd, dut.eth_r2_txc, dut.clk, dut.rst) + self.fmc_qsfp_source = [] + self.fmc_qsfp_sink = [] - self.eth_r3_source = XgmiiSource(dut.eth_r3_rxd, dut.eth_r3_rxc, dut.clk, dut.rst) - self.eth_r3_sink = XgmiiSink(dut.eth_r3_txd, dut.eth_r3_txc, dut.clk, dut.rst) - - self.eth_r4_source = XgmiiSource(dut.eth_r4_rxd, dut.eth_r4_rxc, dut.clk, dut.rst) - self.eth_r4_sink = XgmiiSink(dut.eth_r4_txd, dut.eth_r4_txc, dut.clk, dut.rst) - - self.eth_r5_source = XgmiiSource(dut.eth_r5_rxd, dut.eth_r5_rxc, dut.clk, dut.rst) - self.eth_r5_sink = XgmiiSink(dut.eth_r5_txd, dut.eth_r5_txc, dut.clk, dut.rst) - - self.eth_r6_source = XgmiiSource(dut.eth_r6_rxd, dut.eth_r6_rxc, dut.clk, dut.rst) - self.eth_r6_sink = XgmiiSink(dut.eth_r6_txd, dut.eth_r6_txc, dut.clk, dut.rst) - - self.eth_r7_source = XgmiiSource(dut.eth_r7_rxd, dut.eth_r7_rxc, dut.clk, dut.rst) - self.eth_r7_sink = XgmiiSink(dut.eth_r7_txd, dut.eth_r7_txc, dut.clk, dut.rst) - - self.eth_r8_source = XgmiiSource(dut.eth_r8_rxd, dut.eth_r8_rxc, dut.clk, dut.rst) - self.eth_r8_sink = XgmiiSink(dut.eth_r8_txd, dut.eth_r8_txc, dut.clk, dut.rst) - - self.eth_r9_source = XgmiiSource(dut.eth_r9_rxd, dut.eth_r9_rxc, dut.clk, dut.rst) - self.eth_r9_sink = XgmiiSink(dut.eth_r9_txd, dut.eth_r9_txc, dut.clk, dut.rst) - - self.eth_r10_source = XgmiiSource(dut.eth_r10_rxd, dut.eth_r10_rxc, dut.clk, dut.rst) - self.eth_r10_sink = XgmiiSink(dut.eth_r10_txd, dut.eth_r10_txc, dut.clk, dut.rst) - - self.eth_r11_source = XgmiiSource(dut.eth_r11_rxd, dut.eth_r11_rxc, dut.clk, dut.rst) - self.eth_r11_sink = XgmiiSink(dut.eth_r11_txd, dut.eth_r11_txc, dut.clk, dut.rst) - - self.eth_l0_source = XgmiiSource(dut.eth_l0_rxd, dut.eth_l0_rxc, dut.clk, dut.rst) - self.eth_l0_sink = XgmiiSink(dut.eth_l0_txd, dut.eth_l0_txc, dut.clk, dut.rst) - - self.eth_l1_source = XgmiiSource(dut.eth_l1_rxd, dut.eth_l1_rxc, dut.clk, dut.rst) - self.eth_l1_sink = XgmiiSink(dut.eth_l1_txd, dut.eth_l1_txc, dut.clk, dut.rst) - - self.eth_l2_source = XgmiiSource(dut.eth_l2_rxd, dut.eth_l2_rxc, dut.clk, dut.rst) - self.eth_l2_sink = XgmiiSink(dut.eth_l2_txd, dut.eth_l2_txc, dut.clk, dut.rst) - - self.eth_l3_source = XgmiiSource(dut.eth_l3_rxd, dut.eth_l3_rxc, dut.clk, dut.rst) - self.eth_l3_sink = XgmiiSink(dut.eth_l3_txd, dut.eth_l3_txc, dut.clk, dut.rst) - - self.eth_l4_source = XgmiiSource(dut.eth_l4_rxd, dut.eth_l4_rxc, dut.clk, dut.rst) - self.eth_l4_sink = XgmiiSink(dut.eth_l4_txd, dut.eth_l4_txc, dut.clk, dut.rst) - - self.eth_l5_source = XgmiiSource(dut.eth_l5_rxd, dut.eth_l5_rxc, dut.clk, dut.rst) - self.eth_l5_sink = XgmiiSink(dut.eth_l5_txd, dut.eth_l5_txc, dut.clk, dut.rst) - - self.eth_l6_source = XgmiiSource(dut.eth_l6_rxd, dut.eth_l6_rxc, dut.clk, dut.rst) - self.eth_l6_sink = XgmiiSink(dut.eth_l6_txd, dut.eth_l6_txc, dut.clk, dut.rst) - - self.eth_l7_source = XgmiiSource(dut.eth_l7_rxd, dut.eth_l7_rxc, dut.clk, dut.rst) - self.eth_l7_sink = XgmiiSink(dut.eth_l7_txd, dut.eth_l7_txc, dut.clk, dut.rst) - - self.eth_l8_source = XgmiiSource(dut.eth_l8_rxd, dut.eth_l8_rxc, dut.clk, dut.rst) - self.eth_l8_sink = XgmiiSink(dut.eth_l8_txd, dut.eth_l8_txc, dut.clk, dut.rst) - - self.eth_l9_source = XgmiiSource(dut.eth_l9_rxd, dut.eth_l9_rxc, dut.clk, dut.rst) - self.eth_l9_sink = XgmiiSink(dut.eth_l9_txd, dut.eth_l9_txc, dut.clk, dut.rst) - - self.eth_l10_source = XgmiiSource(dut.eth_l10_rxd, dut.eth_l10_rxc, dut.clk, dut.rst) - self.eth_l10_sink = XgmiiSink(dut.eth_l10_txd, dut.eth_l10_txc, dut.clk, dut.rst) - - self.eth_l11_source = XgmiiSource(dut.eth_l11_rxd, dut.eth_l11_rxc, dut.clk, dut.rst) - self.eth_l11_sink = XgmiiSink(dut.eth_l11_txd, dut.eth_l11_txc, dut.clk, dut.rst) - - dut.sw.setimmediatevalue(0) - dut.jp.setimmediatevalue(0) - dut.uart_suspend.setimmediatevalue(0) - dut.uart_dtr.setimmediatevalue(0) - dut.uart_txd.setimmediatevalue(0) - dut.uart_rts.setimmediatevalue(0) - dut.amh_right_mdio_i.setimmediatevalue(0) - dut.amh_left_mdio_i.setimmediatevalue(0) + for x in range(1, 7): + sources = [] + sinks = [] + for y in range(1, 5): + cocotb.start_soon(Clock(getattr(dut, f"fmc_qsfp_{x}_rx_clk_{y}"), 2.56, units="ns").start()) + source = XgmiiSource(getattr(dut, f"fmc_qsfp_{x}_rxd_{y}"), getattr(dut, f"fmc_qsfp_{x}_rxc_{y}"), getattr(dut, f"fmc_qsfp_{x}_rx_clk_{y}"), getattr(dut, f"fmc_qsfp_{x}_rx_rst_{y}")) + sources.append(source) + cocotb.start_soon(Clock(getattr(dut, f"fmc_qsfp_{x}_tx_clk_{y}"), 2.56, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"fmc_qsfp_{x}_txd_{y}"), getattr(dut, f"fmc_qsfp_{x}_txc_{y}"), getattr(dut, f"fmc_qsfp_{x}_tx_clk_{y}"), getattr(dut, f"fmc_qsfp_{x}_tx_rst_{y}")) + sinks.append(sink) + self.qsfp_source.append(sources) + self.qsfp_sink.append(sinks) async def init(self): self.dut.rst.setimmediatevalue(0) + for x in range(1, 10): + for y in range(1, 5): + getattr(self.dut, f"qsfp_{x}_rx_rst_{y}").setimmediatevalue(0) + getattr(self.dut, f"qsfp_{x}_tx_rst_{y}").setimmediatevalue(0) + for x in range(1, 7): + for y in range(1, 5): + getattr(self.dut, f"fmc_qsfp_{x}_rx_rst_{y}").setimmediatevalue(0) + getattr(self.dut, f"fmc_qsfp_{x}_tx_rst_{y}").setimmediatevalue(0) for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 1 + for x in range(1, 10): + for y in range(1, 5): + getattr(self.dut, f"qsfp_{x}_rx_rst_{y}").value = 1 + getattr(self.dut, f"qsfp_{x}_tx_rst_{y}").value = 1 + for x in range(1, 7): + for y in range(1, 5): + getattr(self.dut, f"fmc_qsfp_{x}_rx_rst_{y}").value = 1 + getattr(self.dut, f"fmc_qsfp_{x}_tx_rst_{y}").value = 1 for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 0 + for x in range(1, 10): + for y in range(1, 5): + getattr(self.dut, f"qsfp_{x}_rx_rst_{y}").value = 0 + getattr(self.dut, f"qsfp_{x}_tx_rst_{y}").value = 0 + for x in range(1, 7): + for y in range(1, 5): + getattr(self.dut, f"fmc_qsfp_{x}_rx_rst_{y}").value = 0 + getattr(self.dut, f"fmc_qsfp_{x}_tx_rst_{y}").value = 0 @cocotb.test() @@ -161,11 +142,11 @@ async def run_test(dut): test_frame = XgmiiFrame.from_payload(test_pkt.build()) - await tb.eth_l0_source.send(test_frame) + await tb.qsfp_source[0][0].send(test_frame) tb.log.info("receive ARP request") - rx_frame = await tb.eth_l0_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -193,11 +174,11 @@ async def run_test(dut): resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - await tb.eth_l0_source.send(resp_frame) + await tb.qsfp_source[0][0].send(resp_frame) tb.log.info("receive UDP packet") - rx_frame = await tb.eth_l0_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) diff --git a/fpga/lib/eth/example/KC705/fpga_gmii/common/vivado.mk b/fpga/lib/eth/example/KC705/fpga_gmii/common/vivado.mk index 21e6a5fed..1402e2382 100644 --- a/fpga/lib/eth/example/KC705/fpga_gmii/common/vivado.mk +++ b/fpga/lib/eth/example/KC705/fpga_gmii/common/vivado.mk @@ -28,7 +28,7 @@ ################################################################### # phony targets -.PHONY: clean fpga +.PHONY: fpga vivado tmpclean clean distclean # prevent make from deleting intermediate files and reports .PRECIOUS: %.xpr %.bit %.mcs %.prm @@ -40,15 +40,16 @@ CONFIG ?= config.mk FPGA_TOP ?= fpga PROJECT ?= $(FPGA_TOP) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else - XDC_FILES_REL = $(FPGA_TOP).xdc + XDC_FILES_REL = $(PROJECT).xdc endif ################################################################### @@ -60,20 +61,20 @@ endif all: fpga -fpga: $(FPGA_TOP).bit +fpga: $(PROJECT).bit -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr -tmpclean: +tmpclean:: -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt -distclean: clean +distclean:: clean -rm -rf rev ################################################################### @@ -91,12 +92,17 @@ create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done -$(PROJECT).xpr: create_project.tcl +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) # synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr echo "open_project $(PROJECT).xpr" > run_synth.tcl echo "reset_run synth_1" >> run_synth.tcl echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl diff --git a/fpga/lib/eth/example/KC705/fpga_gmii/fpga.xdc b/fpga/lib/eth/example/KC705/fpga_gmii/fpga.xdc index 3b4484e67..225dee937 100644 --- a/fpga/lib/eth/example/KC705/fpga_gmii/fpga.xdc +++ b/fpga/lib/eth/example/KC705/fpga_gmii/fpga.xdc @@ -2,9 +2,10 @@ # part: xc7k325tffg900-2 # General configuration -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 2.5 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 2.5 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # System clocks # 200 MHz diff --git a/fpga/lib/eth/example/KC705/fpga_rgmii/common/vivado.mk b/fpga/lib/eth/example/KC705/fpga_rgmii/common/vivado.mk index 21e6a5fed..1402e2382 100644 --- a/fpga/lib/eth/example/KC705/fpga_rgmii/common/vivado.mk +++ b/fpga/lib/eth/example/KC705/fpga_rgmii/common/vivado.mk @@ -28,7 +28,7 @@ ################################################################### # phony targets -.PHONY: clean fpga +.PHONY: fpga vivado tmpclean clean distclean # prevent make from deleting intermediate files and reports .PRECIOUS: %.xpr %.bit %.mcs %.prm @@ -40,15 +40,16 @@ CONFIG ?= config.mk FPGA_TOP ?= fpga PROJECT ?= $(FPGA_TOP) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else - XDC_FILES_REL = $(FPGA_TOP).xdc + XDC_FILES_REL = $(PROJECT).xdc endif ################################################################### @@ -60,20 +61,20 @@ endif all: fpga -fpga: $(FPGA_TOP).bit +fpga: $(PROJECT).bit -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr -tmpclean: +tmpclean:: -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt -distclean: clean +distclean:: clean -rm -rf rev ################################################################### @@ -91,12 +92,17 @@ create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done -$(PROJECT).xpr: create_project.tcl +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) # synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr echo "open_project $(PROJECT).xpr" > run_synth.tcl echo "reset_run synth_1" >> run_synth.tcl echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl diff --git a/fpga/lib/eth/example/KC705/fpga_rgmii/fpga.xdc b/fpga/lib/eth/example/KC705/fpga_rgmii/fpga.xdc index 1f6408855..0fae76968 100644 --- a/fpga/lib/eth/example/KC705/fpga_rgmii/fpga.xdc +++ b/fpga/lib/eth/example/KC705/fpga_rgmii/fpga.xdc @@ -2,9 +2,10 @@ # part: xc7k325tffg900-2 # General configuration -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 2.5 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 2.5 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # System clocks # 200 MHz diff --git a/fpga/lib/eth/example/KC705/fpga_sgmii/common/vivado.mk b/fpga/lib/eth/example/KC705/fpga_sgmii/common/vivado.mk index 21e6a5fed..1402e2382 100644 --- a/fpga/lib/eth/example/KC705/fpga_sgmii/common/vivado.mk +++ b/fpga/lib/eth/example/KC705/fpga_sgmii/common/vivado.mk @@ -28,7 +28,7 @@ ################################################################### # phony targets -.PHONY: clean fpga +.PHONY: fpga vivado tmpclean clean distclean # prevent make from deleting intermediate files and reports .PRECIOUS: %.xpr %.bit %.mcs %.prm @@ -40,15 +40,16 @@ CONFIG ?= config.mk FPGA_TOP ?= fpga PROJECT ?= $(FPGA_TOP) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else - XDC_FILES_REL = $(FPGA_TOP).xdc + XDC_FILES_REL = $(PROJECT).xdc endif ################################################################### @@ -60,20 +61,20 @@ endif all: fpga -fpga: $(FPGA_TOP).bit +fpga: $(PROJECT).bit -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr -tmpclean: +tmpclean:: -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt -distclean: clean +distclean:: clean -rm -rf rev ################################################################### @@ -91,12 +92,17 @@ create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done -$(PROJECT).xpr: create_project.tcl +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) # synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr echo "open_project $(PROJECT).xpr" > run_synth.tcl echo "reset_run synth_1" >> run_synth.tcl echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl diff --git a/fpga/lib/eth/example/KC705/fpga_sgmii/fpga.xdc b/fpga/lib/eth/example/KC705/fpga_sgmii/fpga.xdc index f384048d6..0b4d2e08b 100644 --- a/fpga/lib/eth/example/KC705/fpga_sgmii/fpga.xdc +++ b/fpga/lib/eth/example/KC705/fpga_sgmii/fpga.xdc @@ -2,9 +2,10 @@ # part: xc7k325tffg900-2 # General configuration -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 2.5 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 2.5 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # System clocks # 200 MHz diff --git a/fpga/lib/eth/example/NetFPGA_SUME/fpga/common/vivado.mk b/fpga/lib/eth/example/NetFPGA_SUME/fpga/common/vivado.mk index 21e6a5fed..1402e2382 100644 --- a/fpga/lib/eth/example/NetFPGA_SUME/fpga/common/vivado.mk +++ b/fpga/lib/eth/example/NetFPGA_SUME/fpga/common/vivado.mk @@ -28,7 +28,7 @@ ################################################################### # phony targets -.PHONY: clean fpga +.PHONY: fpga vivado tmpclean clean distclean # prevent make from deleting intermediate files and reports .PRECIOUS: %.xpr %.bit %.mcs %.prm @@ -40,15 +40,16 @@ CONFIG ?= config.mk FPGA_TOP ?= fpga PROJECT ?= $(FPGA_TOP) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else - XDC_FILES_REL = $(FPGA_TOP).xdc + XDC_FILES_REL = $(PROJECT).xdc endif ################################################################### @@ -60,20 +61,20 @@ endif all: fpga -fpga: $(FPGA_TOP).bit +fpga: $(PROJECT).bit -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr -tmpclean: +tmpclean:: -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt -distclean: clean +distclean:: clean -rm -rf rev ################################################################### @@ -91,12 +92,17 @@ create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done -$(PROJECT).xpr: create_project.tcl +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) # synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr echo "open_project $(PROJECT).xpr" > run_synth.tcl echo "reset_run synth_1" >> run_synth.tcl echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl diff --git a/fpga/lib/eth/example/NetFPGA_SUME/fpga/fpga.xdc b/fpga/lib/eth/example/NetFPGA_SUME/fpga/fpga.xdc index d5188a5c0..28f6ae3f1 100644 --- a/fpga/lib/eth/example/NetFPGA_SUME/fpga/fpga.xdc +++ b/fpga/lib/eth/example/NetFPGA_SUME/fpga/fpga.xdc @@ -2,10 +2,11 @@ # part: xc7vx690tffg1761-3 # General configuration -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # 200 MHz system clock set_property -dict {LOC H19 IOSTANDARD LVDS} [get_ports clk_200mhz_p] diff --git a/fpga/lib/eth/example/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py index 4a25a06c1..7b54ab033 100644 --- a/fpga/lib/eth/example/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py @@ -48,65 +48,41 @@ class TB: cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) # Ethernet - cocotb.start_soon(Clock(dut.sfp_1_rx_clk, 6.4, units="ns").start()) - self.sfp_1_source = XgmiiSource(dut.sfp_1_rxd, dut.sfp_1_rxc, dut.sfp_1_rx_clk, dut.sfp_1_rx_rst) - cocotb.start_soon(Clock(dut.sfp_1_tx_clk, 6.4, units="ns").start()) - self.sfp_1_sink = XgmiiSink(dut.sfp_1_txd, dut.sfp_1_txc, dut.sfp_1_tx_clk, dut.sfp_1_tx_rst) + self.sfp_source = [] + self.sfp_sink = [] - cocotb.start_soon(Clock(dut.sfp_2_rx_clk, 6.4, units="ns").start()) - self.sfp_2_source = XgmiiSource(dut.sfp_2_rxd, dut.sfp_2_rxc, dut.sfp_2_rx_clk, dut.sfp_2_rx_rst) - cocotb.start_soon(Clock(dut.sfp_2_tx_clk, 6.4, units="ns").start()) - self.sfp_2_sink = XgmiiSink(dut.sfp_2_txd, dut.sfp_2_txc, dut.sfp_2_tx_clk, dut.sfp_2_tx_rst) - - cocotb.start_soon(Clock(dut.sfp_3_rx_clk, 6.4, units="ns").start()) - self.sfp_3_source = XgmiiSource(dut.sfp_3_rxd, dut.sfp_3_rxc, dut.sfp_3_rx_clk, dut.sfp_3_rx_rst) - cocotb.start_soon(Clock(dut.sfp_3_tx_clk, 6.4, units="ns").start()) - self.sfp_3_sink = XgmiiSink(dut.sfp_3_txd, dut.sfp_3_txc, dut.sfp_3_tx_clk, dut.sfp_3_tx_rst) - - cocotb.start_soon(Clock(dut.sfp_4_rx_clk, 6.4, units="ns").start()) - self.sfp_4_source = XgmiiSource(dut.sfp_4_rxd, dut.sfp_4_rxc, dut.sfp_4_rx_clk, dut.sfp_4_rx_rst) - cocotb.start_soon(Clock(dut.sfp_4_tx_clk, 6.4, units="ns").start()) - self.sfp_4_sink = XgmiiSink(dut.sfp_4_txd, dut.sfp_4_txc, dut.sfp_4_tx_clk, dut.sfp_4_tx_rst) + for y in range(1, 5): + cocotb.start_soon(Clock(getattr(dut, f"sfp_{y}_rx_clk"), 6.4, units="ns").start()) + source = XgmiiSource(getattr(dut, f"sfp_{y}_rxd"), getattr(dut, f"sfp_{y}_rxc"), getattr(dut, f"sfp_{y}_rx_clk"), getattr(dut, f"sfp_{y}_rx_rst")) + self.sfp_source.append(source) + cocotb.start_soon(Clock(getattr(dut, f"sfp_{y}_tx_clk"), 6.4, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"sfp_{y}_txd"), getattr(dut, f"sfp_{y}_txc"), getattr(dut, f"sfp_{y}_tx_clk"), getattr(dut, f"sfp_{y}_tx_rst")) + self.sfp_sink.append(sink) dut.btn.setimmediatevalue(0) async def init(self): self.dut.rst.setimmediatevalue(0) - self.dut.sfp_1_rx_rst.setimmediatevalue(0) - self.dut.sfp_1_tx_rst.setimmediatevalue(0) - self.dut.sfp_2_rx_rst.setimmediatevalue(0) - self.dut.sfp_2_tx_rst.setimmediatevalue(0) - self.dut.sfp_3_rx_rst.setimmediatevalue(0) - self.dut.sfp_3_tx_rst.setimmediatevalue(0) - self.dut.sfp_4_rx_rst.setimmediatevalue(0) - self.dut.sfp_4_tx_rst.setimmediatevalue(0) + for y in range(1, 5): + getattr(self.dut, f"sfp_{y}_rx_rst").setimmediatevalue(0) + getattr(self.dut, f"sfp_{y}_tx_rst").setimmediatevalue(0) for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 1 - self.dut.sfp_1_rx_rst.value = 1 - self.dut.sfp_1_tx_rst.value = 1 - self.dut.sfp_2_rx_rst.value = 1 - self.dut.sfp_2_tx_rst.value = 1 - self.dut.sfp_3_rx_rst.value = 1 - self.dut.sfp_3_tx_rst.value = 1 - self.dut.sfp_4_rx_rst.value = 1 - self.dut.sfp_4_tx_rst.value = 1 + for y in range(1, 5): + getattr(self.dut, f"sfp_{y}_rx_rst").value = 1 + getattr(self.dut, f"sfp_{y}_tx_rst").value = 1 for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 0 - self.dut.sfp_1_rx_rst.value = 0 - self.dut.sfp_1_tx_rst.value = 0 - self.dut.sfp_2_rx_rst.value = 0 - self.dut.sfp_2_tx_rst.value = 0 - self.dut.sfp_3_rx_rst.value = 0 - self.dut.sfp_3_tx_rst.value = 0 - self.dut.sfp_4_rx_rst.value = 0 - self.dut.sfp_4_tx_rst.value = 0 + for y in range(1, 5): + getattr(self.dut, f"sfp_{y}_rx_rst").value = 0 + getattr(self.dut, f"sfp_{y}_tx_rst").value = 0 @cocotb.test() @@ -126,11 +102,11 @@ async def run_test(dut): test_frame = XgmiiFrame.from_payload(test_pkt.build()) - await tb.sfp_1_source.send(test_frame) + await tb.sfp_source[0].send(test_frame) tb.log.info("receive ARP request") - rx_frame = await tb.sfp_1_sink.recv() + rx_frame = await tb.sfp_sink[0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -158,11 +134,11 @@ async def run_test(dut): resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - await tb.sfp_1_source.send(resp_frame) + await tb.sfp_source[0].send(resp_frame) tb.log.info("receive UDP packet") - rx_frame = await tb.sfp_1_sink.recv() + rx_frame = await tb.sfp_sink[0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) diff --git a/fpga/lib/eth/example/NexysVideo/fpga/common/vivado.mk b/fpga/lib/eth/example/NexysVideo/fpga/common/vivado.mk index 21e6a5fed..1402e2382 100644 --- a/fpga/lib/eth/example/NexysVideo/fpga/common/vivado.mk +++ b/fpga/lib/eth/example/NexysVideo/fpga/common/vivado.mk @@ -28,7 +28,7 @@ ################################################################### # phony targets -.PHONY: clean fpga +.PHONY: fpga vivado tmpclean clean distclean # prevent make from deleting intermediate files and reports .PRECIOUS: %.xpr %.bit %.mcs %.prm @@ -40,15 +40,16 @@ CONFIG ?= config.mk FPGA_TOP ?= fpga PROJECT ?= $(FPGA_TOP) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else - XDC_FILES_REL = $(FPGA_TOP).xdc + XDC_FILES_REL = $(PROJECT).xdc endif ################################################################### @@ -60,20 +61,20 @@ endif all: fpga -fpga: $(FPGA_TOP).bit +fpga: $(PROJECT).bit -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr -tmpclean: +tmpclean:: -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt -distclean: clean +distclean:: clean -rm -rf rev ################################################################### @@ -91,12 +92,17 @@ create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done -$(PROJECT).xpr: create_project.tcl +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) # synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr echo "open_project $(PROJECT).xpr" > run_synth.tcl echo "reset_run synth_1" >> run_synth.tcl echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl diff --git a/fpga/lib/eth/example/NexysVideo/fpga/fpga.xdc b/fpga/lib/eth/example/NexysVideo/fpga/fpga.xdc index 05cd5d125..d56cf8375 100644 --- a/fpga/lib/eth/example/NexysVideo/fpga/fpga.xdc +++ b/fpga/lib/eth/example/NexysVideo/fpga/fpga.xdc @@ -2,9 +2,9 @@ # part: xc7a200tsbg484-1 # General configuration -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 3.3 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] # 100 MHz clock set_property -dict {LOC R4 IOSTANDARD LVCMOS33} [get_ports clk] diff --git a/fpga/lib/eth/example/S10DX_DK/fpga_10g/common/quartus_pro.mk b/fpga/lib/eth/example/S10DX_DK/fpga_10g/common/quartus_pro.mk index 1fc1b6fe8..f7e9cea62 100644 --- a/fpga/lib/eth/example/S10DX_DK/fpga_10g/common/quartus_pro.mk +++ b/fpga/lib/eth/example/S10DX_DK/fpga_10g/common/quartus_pro.mk @@ -39,7 +39,7 @@ CONFIG ?= config.mk -include ../$(CONFIG) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) IP_FILES_REL = $(patsubst %, ../%, $(IP_FILES)) IP_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_FILES))) @@ -48,13 +48,15 @@ IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) IP_TCL_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_TCL_FILES))) IP_TCL_FILES_IP_INT = $(patsubst %.tcl, ip/%.ip, $(notdir $(IP_TCL_FILES))) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) + ifdef QSF_FILES - QSF_FILES_REL = $(patsubst %, ../%, $(QSF_FILES)) + QSF_FILES_REL = $(foreach p,$(QSF_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else QSF_FILES_REL = ../$(FPGA_TOP).qsf endif -SDC_FILES_REL = $(patsubst %, ../%, $(SDC_FILES)) +SDC_FILES_REL = $(foreach p,$(SDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ASSIGNMENT_FILES = $(FPGA_TOP).qpf $(FPGA_TOP).qsf @@ -72,15 +74,16 @@ fpga: $(FPGA_TOP).sof quartus: $(FPGA_TOP).qpf quartus $(FPGA_TOP).qpf -tmpclean: +tmpclean:: -rm -rf defines.v -rm -rf *.rpt *.summary *.done *.smsg *.chg smart.log *.htm *.eqn *.pin *.qsf *.qpf *.sld *.txt *.qws *.stp -rm -rf ip db qdb incremental_db reconfig_mif tmp-clearbox synth_dumps .qsys_edit + -rm -rf create_project.tcl update_config.tcl update_ip_*.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.sof *.pof *.jdi *.jic *.map -distclean: clean +distclean:: clean -rm -rf rev syn: smart.log output_files/$(PROJECT).syn.rpt @@ -113,7 +116,8 @@ endef $(foreach l,$(IP_FILES_REL) $(IP_TCL_FILES_REL),$(eval $(call COPY_IP_RULE,$(l)))) define TCL_IP_GEN_RULE -$(patsubst %.tcl, %.ip, $(1)): $(1) +$(patsubst %.tcl,%.ip,$(1)): $(1) + cd ip && rm -f $(patsubst %.tcl,%,$(notdir $(1))).{qpf,qsf} cd ip && qsys-script --script=$(notdir $(1)) endef $(foreach l,$(IP_TCL_FILES_INT),$(eval $(call TCL_IP_GEN_RULE,$(l)))) @@ -149,25 +153,30 @@ smart.log: $(ASSIGNMENT_FILES) # Project initialization ################################################################### -$(ASSIGNMENT_FILES): $(QSF_FILES_REL) $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT) - rm -f $(FPGA_TOP).qsf - quartus_sh --prepare -f $(FPGA_FAMILY) -d $(FPGA_DEVICE) -t $(FPGA_TOP) $(FPGA_TOP) - echo >> $(FPGA_TOP).qsf - echo >> $(FPGA_TOP).qsf - echo "# Source files" >> $(FPGA_TOP).qsf +create_project.tcl: Makefile $(QSF_FILES_REL) | $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT) + rm -f update_config.tcl + echo "project_new $(FPGA_TOP) -overwrite" > $@ + echo "set_global_assignment -name FAMILY \"$(FPGA_FAMILY)\"" >> $@ + echo "set_global_assignment -name DEVICE \"$(FPGA_DEVICE)\"" >> $@ for x in $(SYN_FILES_REL) $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT); do \ case $${x##*.} in \ - v|V) echo set_global_assignment -name VERILOG_FILE $$x >> $(FPGA_TOP).qsf ;;\ - vhd|VHD) echo set_global_assignment -name VHDL_FILE $$x >> $(FPGA_TOP).qsf ;;\ - qip|QIP) echo set_global_assignment -name QIP_FILE $$x >> $(FPGA_TOP).qsf ;;\ - ip|IP) echo set_global_assignment -name IP_FILE $$x >> $(FPGA_TOP).qsf ;;\ - *) echo set_global_assignment -name SOURCE_FILE $$x >> $(FPGA_TOP).qsf ;;\ + v|V) echo set_global_assignment -name VERILOG_FILE "$$x" >> $@ ;;\ + vhd|VHD) echo set_global_assignment -name VHDL_FILE "$$x" >> $@ ;;\ + qip|QIP) echo set_global_assignment -name QIP_FILE "$$x" >> $@ ;;\ + ip|IP) echo set_global_assignment -name IP_FILE "$$x" >> $@ ;;\ + *) echo set_global_assignment -name SOURCE_FILE "$$x" >> $@ ;;\ esac; \ done - echo >> $(FPGA_TOP).qsf - echo "# SDC files" >> $(FPGA_TOP).qsf - for x in $(SDC_FILES_REL); do echo set_global_assignment -name SDC_FILE $$x >> $(FPGA_TOP).qsf; done - for x in $(QSF_FILES_REL); do printf "\n#\n# Included QSF file $$x\n#\n" >> $(FPGA_TOP).qsf; cat $$x >> $(FPGA_TOP).qsf; done + for x in $(SDC_FILES_REL); do echo set_global_assignment -name SDC_FILE "$$x" >> $@; done + for x in $(QSF_FILES_REL); do echo source "$$x" >> $@; done + +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) + echo "project_open $(FPGA_TOP)" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo source "$$x" >> $@; done + +$(ASSIGNMENT_FILES): create_project.tcl update_config.tcl + for x in $?; do quartus_sh -t "$$x"; done + touch -c $(ASSIGNMENT_FILES) syn.chg: $(STAMP) syn.chg diff --git a/fpga/lib/eth/example/S10DX_DK/fpga_10g/rtl/fpga_core.v b/fpga/lib/eth/example/S10DX_DK/fpga_10g/rtl/fpga_core.v index f73913abd..3bfb36b0d 100644 --- a/fpga/lib/eth/example/S10DX_DK/fpga_10g/rtl/fpga_core.v +++ b/fpga/lib/eth/example/S10DX_DK/fpga_10g/rtl/fpga_core.v @@ -498,14 +498,14 @@ axis_async_fifo #( .DEST_ENABLE(0), .USER_ENABLE(1), .USER_WIDTH(1), - .PIPELINE_OUTPUT(2), + .RAM_PIPELINE(2), .FRAME_FIFO(1), .USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_MASK(1'b1), .DROP_BAD_FRAME(1), .DROP_WHEN_FULL(1) ) -max_rx_fifo ( +mac_rx_fifo ( // AXI input .s_clk(qsfp1_mac_1_rx_clk), .s_rst(qsfp1_mac_1_rx_rst), @@ -548,14 +548,14 @@ axis_async_fifo #( .DEST_ENABLE(0), .USER_ENABLE(1), .USER_WIDTH(1), - .PIPELINE_OUTPUT(2), + .RAM_PIPELINE(2), .FRAME_FIFO(1), .USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_MASK(1'b1), .DROP_BAD_FRAME(1), .DROP_WHEN_FULL(0) ) -max_tx_fifo ( +mac_tx_fifo ( // AXI input .s_clk(clk), .s_rst(rst), diff --git a/fpga/lib/eth/example/S10DX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/S10DX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py index 72d03bd32..0b744bbcd 100644 --- a/fpga/lib/eth/example/S10DX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/S10DX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -49,173 +49,51 @@ class TB: cocotb.start_soon(Clock(dut.clk, 6.206, units="ns").start()) # Ethernet - cocotb.start_soon(Clock(dut.qsfp1_mac_1_rx_clk, 6.206, units="ns").start()) - cocotb.start_soon(Clock(dut.qsfp1_mac_1_tx_clk, 6.206, units="ns").start()) + self.qsfp_mac = [] - self.qsfp1_mac_1 = EthMac( - tx_clk=dut.qsfp1_mac_1_tx_clk, - tx_rst=dut.qsfp1_mac_1_tx_rst, - tx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_1_tx_axis"), - rx_clk=dut.qsfp1_mac_1_rx_clk, - rx_rst=dut.qsfp1_mac_1_rx_rst, - rx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_1_rx_axis"), - ifg=12, speed=10e9 - ) - - cocotb.start_soon(Clock(dut.qsfp1_mac_2_rx_clk, 6.206, units="ns").start()) - cocotb.start_soon(Clock(dut.qsfp1_mac_2_tx_clk, 6.206, units="ns").start()) - - self.qsfp1_mac_2 = EthMac( - tx_clk=dut.qsfp1_mac_2_tx_clk, - tx_rst=dut.qsfp1_mac_2_tx_rst, - tx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_2_tx_axis"), - rx_clk=dut.qsfp1_mac_2_rx_clk, - rx_rst=dut.qsfp1_mac_2_rx_rst, - rx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_2_rx_axis"), - ifg=12, speed=10e9 - ) - - cocotb.start_soon(Clock(dut.qsfp1_mac_3_rx_clk, 6.206, units="ns").start()) - cocotb.start_soon(Clock(dut.qsfp1_mac_3_tx_clk, 6.206, units="ns").start()) - - self.qsfp1_mac_3 = EthMac( - tx_clk=dut.qsfp1_mac_3_tx_clk, - tx_rst=dut.qsfp1_mac_3_tx_rst, - tx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_3_tx_axis"), - rx_clk=dut.qsfp1_mac_3_rx_clk, - rx_rst=dut.qsfp1_mac_3_rx_rst, - rx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_3_rx_axis"), - ifg=12, speed=10e9 - ) - - cocotb.start_soon(Clock(dut.qsfp1_mac_4_rx_clk, 6.206, units="ns").start()) - cocotb.start_soon(Clock(dut.qsfp1_mac_4_tx_clk, 6.206, units="ns").start()) - - self.qsfp1_mac_4 = EthMac( - tx_clk=dut.qsfp1_mac_4_tx_clk, - tx_rst=dut.qsfp1_mac_4_tx_rst, - tx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_4_tx_axis"), - rx_clk=dut.qsfp1_mac_4_rx_clk, - rx_rst=dut.qsfp1_mac_4_rx_rst, - rx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_4_rx_axis"), - ifg=12, speed=10e9 - ) - - cocotb.start_soon(Clock(dut.qsfp2_mac_1_rx_clk, 6.206, units="ns").start()) - cocotb.start_soon(Clock(dut.qsfp2_mac_1_tx_clk, 6.206, units="ns").start()) - - self.qsfp2_mac_1 = EthMac( - tx_clk=dut.qsfp2_mac_1_tx_clk, - tx_rst=dut.qsfp2_mac_1_tx_rst, - tx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_1_tx_axis"), - rx_clk=dut.qsfp2_mac_1_rx_clk, - rx_rst=dut.qsfp2_mac_1_rx_rst, - rx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_1_rx_axis"), - ifg=12, speed=10e9 - ) - - cocotb.start_soon(Clock(dut.qsfp2_mac_2_rx_clk, 6.206, units="ns").start()) - cocotb.start_soon(Clock(dut.qsfp2_mac_2_tx_clk, 6.206, units="ns").start()) - - self.qsfp2_mac_2 = EthMac( - tx_clk=dut.qsfp2_mac_2_tx_clk, - tx_rst=dut.qsfp2_mac_2_tx_rst, - tx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_2_tx_axis"), - rx_clk=dut.qsfp2_mac_2_rx_clk, - rx_rst=dut.qsfp2_mac_2_rx_rst, - rx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_2_rx_axis"), - ifg=12, speed=10e9 - ) - - cocotb.start_soon(Clock(dut.qsfp2_mac_3_rx_clk, 6.206, units="ns").start()) - cocotb.start_soon(Clock(dut.qsfp2_mac_3_tx_clk, 6.206, units="ns").start()) - - self.qsfp2_mac_3 = EthMac( - tx_clk=dut.qsfp2_mac_3_tx_clk, - tx_rst=dut.qsfp2_mac_3_tx_rst, - tx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_3_tx_axis"), - rx_clk=dut.qsfp2_mac_3_rx_clk, - rx_rst=dut.qsfp2_mac_3_rx_rst, - rx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_3_rx_axis"), - ifg=12, speed=10e9 - ) - - cocotb.start_soon(Clock(dut.qsfp2_mac_4_rx_clk, 6.206, units="ns").start()) - cocotb.start_soon(Clock(dut.qsfp2_mac_4_tx_clk, 6.206, units="ns").start()) - - self.qsfp2_mac_4 = EthMac( - tx_clk=dut.qsfp2_mac_4_tx_clk, - tx_rst=dut.qsfp2_mac_4_tx_rst, - tx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_4_tx_axis"), - rx_clk=dut.qsfp2_mac_4_rx_clk, - rx_rst=dut.qsfp2_mac_4_rx_rst, - rx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_4_rx_axis"), - ifg=12, speed=10e9 - ) + for x in range(1, 3): + macs = [] + for y in range(1, 5): + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_mac_{y}_tx_clk"), 6.206, units="ns").start()) + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_mac_{y}_rx_clk"), 6.206, units="ns").start()) + macs.append(EthMac( + tx_clk=getattr(dut, f"qsfp{x}_mac_{y}_tx_clk"), + tx_rst=getattr(dut, f"qsfp{x}_mac_{y}_tx_rst"), + tx_bus=AxiStreamBus.from_prefix(dut, f"qsfp{x}_mac_{y}_tx_axis"), + rx_clk=getattr(dut, f"qsfp{x}_mac_{y}_rx_clk"), + rx_rst=getattr(dut, f"qsfp{x}_mac_{y}_rx_rst"), + rx_bus=AxiStreamBus.from_prefix(dut, f"qsfp{x}_mac_{y}_rx_axis"), + ifg=12, speed=10e9 + )) + self.qsfp_mac.append(macs) dut.btn.setimmediatevalue(0) async def init(self): self.dut.rst.setimmediatevalue(0) - self.dut.qsfp1_mac_1_rx_rst.setimmediatevalue(0) - self.dut.qsfp1_mac_1_tx_rst.setimmediatevalue(0) - self.dut.qsfp1_mac_2_rx_rst.setimmediatevalue(0) - self.dut.qsfp1_mac_2_tx_rst.setimmediatevalue(0) - self.dut.qsfp1_mac_3_rx_rst.setimmediatevalue(0) - self.dut.qsfp1_mac_3_tx_rst.setimmediatevalue(0) - self.dut.qsfp1_mac_4_rx_rst.setimmediatevalue(0) - self.dut.qsfp1_mac_4_tx_rst.setimmediatevalue(0) - self.dut.qsfp2_mac_1_rx_rst.setimmediatevalue(0) - self.dut.qsfp2_mac_1_tx_rst.setimmediatevalue(0) - self.dut.qsfp2_mac_2_rx_rst.setimmediatevalue(0) - self.dut.qsfp2_mac_2_tx_rst.setimmediatevalue(0) - self.dut.qsfp2_mac_3_rx_rst.setimmediatevalue(0) - self.dut.qsfp2_mac_3_tx_rst.setimmediatevalue(0) - self.dut.qsfp2_mac_4_rx_rst.setimmediatevalue(0) - self.dut.qsfp2_mac_4_tx_rst.setimmediatevalue(0) + for x in range(1, 3): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_mac_{y}_rx_rst").setimmediatevalue(0) + getattr(self.dut, f"qsfp{x}_mac_{y}_tx_rst").setimmediatevalue(0) for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 1 - self.dut.qsfp1_mac_1_rx_rst.value = 1 - self.dut.qsfp1_mac_1_tx_rst.value = 1 - self.dut.qsfp1_mac_2_rx_rst.value = 1 - self.dut.qsfp1_mac_2_tx_rst.value = 1 - self.dut.qsfp1_mac_3_rx_rst.value = 1 - self.dut.qsfp1_mac_3_tx_rst.value = 1 - self.dut.qsfp1_mac_4_rx_rst.value = 1 - self.dut.qsfp1_mac_4_tx_rst.value = 1 - self.dut.qsfp2_mac_1_rx_rst.value = 1 - self.dut.qsfp2_mac_1_tx_rst.value = 1 - self.dut.qsfp2_mac_2_rx_rst.value = 1 - self.dut.qsfp2_mac_2_tx_rst.value = 1 - self.dut.qsfp2_mac_3_rx_rst.value = 1 - self.dut.qsfp2_mac_3_tx_rst.value = 1 - self.dut.qsfp2_mac_4_rx_rst.value = 1 - self.dut.qsfp2_mac_4_tx_rst.value = 1 + for x in range(1, 3): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_mac_{y}_rx_rst").value = 1 + getattr(self.dut, f"qsfp{x}_mac_{y}_tx_rst").value = 1 for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 0 - self.dut.qsfp1_mac_1_rx_rst.value = 0 - self.dut.qsfp1_mac_1_tx_rst.value = 0 - self.dut.qsfp1_mac_2_rx_rst.value = 0 - self.dut.qsfp1_mac_2_tx_rst.value = 0 - self.dut.qsfp1_mac_3_rx_rst.value = 0 - self.dut.qsfp1_mac_3_tx_rst.value = 0 - self.dut.qsfp1_mac_4_rx_rst.value = 0 - self.dut.qsfp1_mac_4_tx_rst.value = 0 - self.dut.qsfp2_mac_1_rx_rst.value = 0 - self.dut.qsfp2_mac_1_tx_rst.value = 0 - self.dut.qsfp2_mac_2_rx_rst.value = 0 - self.dut.qsfp2_mac_2_tx_rst.value = 0 - self.dut.qsfp2_mac_3_rx_rst.value = 0 - self.dut.qsfp2_mac_3_tx_rst.value = 0 - self.dut.qsfp2_mac_4_rx_rst.value = 0 - self.dut.qsfp2_mac_4_tx_rst.value = 0 + for x in range(1, 3): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_mac_{y}_rx_rst").value = 0 + getattr(self.dut, f"qsfp{x}_mac_{y}_tx_rst").value = 0 for k in range(10): await RisingEdge(self.dut.clk) @@ -236,11 +114,11 @@ async def run_test(dut): udp = UDP(sport=5678, dport=1234) test_pkt = eth / ip / udp / payload - await tb.qsfp1_mac_1.rx.send(test_pkt.build()) + await tb.qsfp_mac[0][0].rx.send(test_pkt.build()) tb.log.info("receive ARP request") - rx_frame = await tb.qsfp1_mac_1.tx.recv() + rx_frame = await tb.qsfp_mac[0][0].tx.recv() rx_pkt = Ether(bytes(rx_frame)) @@ -266,11 +144,11 @@ async def run_test(dut): hwdst=test_pkt.dst, pdst=test_pkt[IP].dst) resp_pkt = eth / arp - await tb.qsfp1_mac_1.rx.send(resp_pkt.build()) + await tb.qsfp_mac[0][0].rx.send(resp_pkt.build()) tb.log.info("receive UDP packet") - rx_frame = await tb.qsfp1_mac_1.tx.recv() + rx_frame = await tb.qsfp_mac[0][0].tx.recv() rx_pkt = Ether(bytes(rx_frame)) diff --git a/fpga/lib/eth/example/S10MX_DK/fpga_10g/common/quartus_pro.mk b/fpga/lib/eth/example/S10MX_DK/fpga_10g/common/quartus_pro.mk index 1fc1b6fe8..f7e9cea62 100644 --- a/fpga/lib/eth/example/S10MX_DK/fpga_10g/common/quartus_pro.mk +++ b/fpga/lib/eth/example/S10MX_DK/fpga_10g/common/quartus_pro.mk @@ -39,7 +39,7 @@ CONFIG ?= config.mk -include ../$(CONFIG) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) IP_FILES_REL = $(patsubst %, ../%, $(IP_FILES)) IP_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_FILES))) @@ -48,13 +48,15 @@ IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) IP_TCL_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_TCL_FILES))) IP_TCL_FILES_IP_INT = $(patsubst %.tcl, ip/%.ip, $(notdir $(IP_TCL_FILES))) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) + ifdef QSF_FILES - QSF_FILES_REL = $(patsubst %, ../%, $(QSF_FILES)) + QSF_FILES_REL = $(foreach p,$(QSF_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else QSF_FILES_REL = ../$(FPGA_TOP).qsf endif -SDC_FILES_REL = $(patsubst %, ../%, $(SDC_FILES)) +SDC_FILES_REL = $(foreach p,$(SDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ASSIGNMENT_FILES = $(FPGA_TOP).qpf $(FPGA_TOP).qsf @@ -72,15 +74,16 @@ fpga: $(FPGA_TOP).sof quartus: $(FPGA_TOP).qpf quartus $(FPGA_TOP).qpf -tmpclean: +tmpclean:: -rm -rf defines.v -rm -rf *.rpt *.summary *.done *.smsg *.chg smart.log *.htm *.eqn *.pin *.qsf *.qpf *.sld *.txt *.qws *.stp -rm -rf ip db qdb incremental_db reconfig_mif tmp-clearbox synth_dumps .qsys_edit + -rm -rf create_project.tcl update_config.tcl update_ip_*.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.sof *.pof *.jdi *.jic *.map -distclean: clean +distclean:: clean -rm -rf rev syn: smart.log output_files/$(PROJECT).syn.rpt @@ -113,7 +116,8 @@ endef $(foreach l,$(IP_FILES_REL) $(IP_TCL_FILES_REL),$(eval $(call COPY_IP_RULE,$(l)))) define TCL_IP_GEN_RULE -$(patsubst %.tcl, %.ip, $(1)): $(1) +$(patsubst %.tcl,%.ip,$(1)): $(1) + cd ip && rm -f $(patsubst %.tcl,%,$(notdir $(1))).{qpf,qsf} cd ip && qsys-script --script=$(notdir $(1)) endef $(foreach l,$(IP_TCL_FILES_INT),$(eval $(call TCL_IP_GEN_RULE,$(l)))) @@ -149,25 +153,30 @@ smart.log: $(ASSIGNMENT_FILES) # Project initialization ################################################################### -$(ASSIGNMENT_FILES): $(QSF_FILES_REL) $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT) - rm -f $(FPGA_TOP).qsf - quartus_sh --prepare -f $(FPGA_FAMILY) -d $(FPGA_DEVICE) -t $(FPGA_TOP) $(FPGA_TOP) - echo >> $(FPGA_TOP).qsf - echo >> $(FPGA_TOP).qsf - echo "# Source files" >> $(FPGA_TOP).qsf +create_project.tcl: Makefile $(QSF_FILES_REL) | $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT) + rm -f update_config.tcl + echo "project_new $(FPGA_TOP) -overwrite" > $@ + echo "set_global_assignment -name FAMILY \"$(FPGA_FAMILY)\"" >> $@ + echo "set_global_assignment -name DEVICE \"$(FPGA_DEVICE)\"" >> $@ for x in $(SYN_FILES_REL) $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT); do \ case $${x##*.} in \ - v|V) echo set_global_assignment -name VERILOG_FILE $$x >> $(FPGA_TOP).qsf ;;\ - vhd|VHD) echo set_global_assignment -name VHDL_FILE $$x >> $(FPGA_TOP).qsf ;;\ - qip|QIP) echo set_global_assignment -name QIP_FILE $$x >> $(FPGA_TOP).qsf ;;\ - ip|IP) echo set_global_assignment -name IP_FILE $$x >> $(FPGA_TOP).qsf ;;\ - *) echo set_global_assignment -name SOURCE_FILE $$x >> $(FPGA_TOP).qsf ;;\ + v|V) echo set_global_assignment -name VERILOG_FILE "$$x" >> $@ ;;\ + vhd|VHD) echo set_global_assignment -name VHDL_FILE "$$x" >> $@ ;;\ + qip|QIP) echo set_global_assignment -name QIP_FILE "$$x" >> $@ ;;\ + ip|IP) echo set_global_assignment -name IP_FILE "$$x" >> $@ ;;\ + *) echo set_global_assignment -name SOURCE_FILE "$$x" >> $@ ;;\ esac; \ done - echo >> $(FPGA_TOP).qsf - echo "# SDC files" >> $(FPGA_TOP).qsf - for x in $(SDC_FILES_REL); do echo set_global_assignment -name SDC_FILE $$x >> $(FPGA_TOP).qsf; done - for x in $(QSF_FILES_REL); do printf "\n#\n# Included QSF file $$x\n#\n" >> $(FPGA_TOP).qsf; cat $$x >> $(FPGA_TOP).qsf; done + for x in $(SDC_FILES_REL); do echo set_global_assignment -name SDC_FILE "$$x" >> $@; done + for x in $(QSF_FILES_REL); do echo source "$$x" >> $@; done + +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) + echo "project_open $(FPGA_TOP)" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo source "$$x" >> $@; done + +$(ASSIGNMENT_FILES): create_project.tcl update_config.tcl + for x in $?; do quartus_sh -t "$$x"; done + touch -c $(ASSIGNMENT_FILES) syn.chg: $(STAMP) syn.chg diff --git a/fpga/lib/eth/example/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py index 934d967e9..817236beb 100644 --- a/fpga/lib/eth/example/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -48,107 +48,47 @@ class TB: cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) # Ethernet - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_1, 6.4, units="ns").start()) - self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1, dut.qsfp0_rx_clk_1, dut.qsfp0_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_1, 6.4, units="ns").start()) - self.qsfp0_1_sink = XgmiiSink(dut.qsfp0_txd_1, dut.qsfp0_txc_1, dut.qsfp0_tx_clk_1, dut.qsfp0_tx_rst_1) + self.qsfp_source = [] + self.qsfp_sink = [] - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_2, 6.4, units="ns").start()) - self.qsfp0_2_source = XgmiiSource(dut.qsfp0_rxd_2, dut.qsfp0_rxc_2, dut.qsfp0_rx_clk_2, dut.qsfp0_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_2, 6.4, units="ns").start()) - self.qsfp0_2_sink = XgmiiSink(dut.qsfp0_txd_2, dut.qsfp0_txc_2, dut.qsfp0_tx_clk_2, dut.qsfp0_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_3, 6.4, units="ns").start()) - self.qsfp0_3_source = XgmiiSource(dut.qsfp0_rxd_3, dut.qsfp0_rxc_3, dut.qsfp0_rx_clk_3, dut.qsfp0_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_3, 6.4, units="ns").start()) - self.qsfp0_3_sink = XgmiiSink(dut.qsfp0_txd_3, dut.qsfp0_txc_3, dut.qsfp0_tx_clk_3, dut.qsfp0_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_4, 6.4, units="ns").start()) - self.qsfp0_4_source = XgmiiSource(dut.qsfp0_rxd_4, dut.qsfp0_rxc_4, dut.qsfp0_rx_clk_4, dut.qsfp0_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_4, 6.4, units="ns").start()) - self.qsfp0_4_sink = XgmiiSink(dut.qsfp0_txd_4, dut.qsfp0_txc_4, dut.qsfp0_tx_clk_4, dut.qsfp0_tx_rst_4) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_1, 6.4, units="ns").start()) - self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_1, 6.4, units="ns").start()) - self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_2, 6.4, units="ns").start()) - self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_2, 6.4, units="ns").start()) - self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_3, 6.4, units="ns").start()) - self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_3, 6.4, units="ns").start()) - self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_4, 6.4, units="ns").start()) - self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 6.4, units="ns").start()) - self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4) + for x in range(2): + sources = [] + sinks = [] + for y in range(1, 5): + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_rx_clk_{y}"), 6.4, units="ns").start()) + source = XgmiiSource(getattr(dut, f"qsfp{x}_rxd_{y}"), getattr(dut, f"qsfp{x}_rxc_{y}"), getattr(dut, f"qsfp{x}_rx_clk_{y}"), getattr(dut, f"qsfp{x}_rx_rst_{y}")) + sources.append(source) + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_tx_clk_{y}"), 6.4, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"qsfp{x}_txd_{y}"), getattr(dut, f"qsfp{x}_txc_{y}"), getattr(dut, f"qsfp{x}_tx_clk_{y}"), getattr(dut, f"qsfp{x}_tx_rst_{y}")) + sinks.append(sink) + self.qsfp_source.append(sources) + self.qsfp_sink.append(sinks) async def init(self): self.dut.rst.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_4.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) + for x in range(2): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(0) + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(0) for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 1 - self.dut.qsfp0_rx_rst_1.value = 1 - self.dut.qsfp0_tx_rst_1.value = 1 - self.dut.qsfp0_rx_rst_2.value = 1 - self.dut.qsfp0_tx_rst_2.value = 1 - self.dut.qsfp0_rx_rst_3.value = 1 - self.dut.qsfp0_tx_rst_3.value = 1 - self.dut.qsfp0_rx_rst_4.value = 1 - self.dut.qsfp0_tx_rst_4.value = 1 - self.dut.qsfp1_rx_rst_1.value = 1 - self.dut.qsfp1_tx_rst_1.value = 1 - self.dut.qsfp1_rx_rst_2.value = 1 - self.dut.qsfp1_tx_rst_2.value = 1 - self.dut.qsfp1_rx_rst_3.value = 1 - self.dut.qsfp1_tx_rst_3.value = 1 - self.dut.qsfp1_rx_rst_4.value = 1 - self.dut.qsfp1_tx_rst_4.value = 1 + for x in range(2): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").value = 1 + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").value = 1 for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 0 - self.dut.qsfp0_rx_rst_1.value = 0 - self.dut.qsfp0_tx_rst_1.value = 0 - self.dut.qsfp0_rx_rst_2.value = 0 - self.dut.qsfp0_tx_rst_2.value = 0 - self.dut.qsfp0_rx_rst_3.value = 0 - self.dut.qsfp0_tx_rst_3.value = 0 - self.dut.qsfp0_rx_rst_4.value = 0 - self.dut.qsfp0_tx_rst_4.value = 0 - self.dut.qsfp1_rx_rst_1.value = 0 - self.dut.qsfp1_tx_rst_1.value = 0 - self.dut.qsfp1_rx_rst_2.value = 0 - self.dut.qsfp1_tx_rst_2.value = 0 - self.dut.qsfp1_rx_rst_3.value = 0 - self.dut.qsfp1_tx_rst_3.value = 0 - self.dut.qsfp1_rx_rst_4.value = 0 - self.dut.qsfp1_tx_rst_4.value = 0 + for x in range(2): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").value = 0 + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").value = 0 @cocotb.test() @@ -168,11 +108,11 @@ async def run_test(dut): test_frame = XgmiiFrame.from_payload(test_pkt.build()) - await tb.qsfp0_1_source.send(test_frame) + await tb.qsfp_source[0][0].send(test_frame) tb.log.info("receive ARP request") - rx_frame = await tb.qsfp0_1_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -200,11 +140,11 @@ async def run_test(dut): resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - await tb.qsfp0_1_source.send(resp_frame) + await tb.qsfp_source[0][0].send(resp_frame) tb.log.info("receive UDP packet") - rx_frame = await tb.qsfp0_1_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) diff --git a/fpga/lib/eth/example/VCU108/fpga_10g/common/vivado.mk b/fpga/lib/eth/example/VCU108/fpga_10g/common/vivado.mk index 21e6a5fed..1402e2382 100644 --- a/fpga/lib/eth/example/VCU108/fpga_10g/common/vivado.mk +++ b/fpga/lib/eth/example/VCU108/fpga_10g/common/vivado.mk @@ -28,7 +28,7 @@ ################################################################### # phony targets -.PHONY: clean fpga +.PHONY: fpga vivado tmpclean clean distclean # prevent make from deleting intermediate files and reports .PRECIOUS: %.xpr %.bit %.mcs %.prm @@ -40,15 +40,16 @@ CONFIG ?= config.mk FPGA_TOP ?= fpga PROJECT ?= $(FPGA_TOP) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else - XDC_FILES_REL = $(FPGA_TOP).xdc + XDC_FILES_REL = $(PROJECT).xdc endif ################################################################### @@ -60,20 +61,20 @@ endif all: fpga -fpga: $(FPGA_TOP).bit +fpga: $(PROJECT).bit -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr -tmpclean: +tmpclean:: -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt -distclean: clean +distclean:: clean -rm -rf rev ################################################################### @@ -91,12 +92,17 @@ create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done -$(PROJECT).xpr: create_project.tcl +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) # synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr echo "open_project $(PROJECT).xpr" > run_synth.tcl echo "reset_run synth_1" >> run_synth.tcl echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl diff --git a/fpga/lib/eth/example/VCU108/fpga_10g/fpga.xdc b/fpga/lib/eth/example/VCU108/fpga_10g/fpga.xdc index 489efcb14..1187f1bd4 100644 --- a/fpga/lib/eth/example/VCU108/fpga_10g/fpga.xdc +++ b/fpga/lib/eth/example/VCU108/fpga_10g/fpga.xdc @@ -8,6 +8,7 @@ set_property BITSTREAM.GENERAL.COMPRESS true [current_design] set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1 [current_design] set_property CONFIG_MODE BPI16 [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # System clocks # 300 MHz @@ -308,6 +309,618 @@ set_input_delay 0 [get_ports {i2c_sda i2c_scl}] #set_false_path -from [get_ports {pcie_reset_n}] #set_input_delay 0 [get_ports {pcie_reset_n}] +# FMC interface +# FMC HPC0 J22 +#set_property -dict {LOC AY9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[0]"] ;# J22.G9 LA00_P_CC +#set_property -dict {LOC BA9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[0]"] ;# J22.G10 LA00_N_CC +#set_property -dict {LOC BC10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[1]"] ;# J22.D8 LA01_P_CC +#set_property -dict {LOC BD10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[1]"] ;# J22.D9 LA01_N_CC +#set_property -dict {LOC BA7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[2]"] ;# J22.H7 LA02_P +#set_property -dict {LOC BB7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[2]"] ;# J22.H8 LA02_N +#set_property -dict {LOC BD8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[3]"] ;# J22.G12 LA03_P +#set_property -dict {LOC BD7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[3]"] ;# J22.G13 LA03_N +#set_property -dict {LOC BE8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[4]"] ;# J22.H10 LA04_P +#set_property -dict {LOC BE7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[4]"] ;# J22.H11 LA04_N +#set_property -dict {LOC BF12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[5]"] ;# J22.D11 LA05_P +#set_property -dict {LOC BF11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[5]"] ;# J22.D12 LA05_N +#set_property -dict {LOC BE10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[6]"] ;# J22.C10 LA06_P +#set_property -dict {LOC BE9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[6]"] ;# J22.C11 LA06_N +#set_property -dict {LOC BD12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[7]"] ;# J22.H13 LA07_P +#set_property -dict {LOC BE12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[7]"] ;# J22.H14 LA07_N +#set_property -dict {LOC BF10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[8]"] ;# J22.G12 LA08_P +#set_property -dict {LOC BF9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[8]"] ;# J22.G13 LA08_N +#set_property -dict {LOC BD13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[9]"] ;# J22.D14 LA09_P +#set_property -dict {LOC BE13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[9]"] ;# J22.D15 LA09_N +#set_property -dict {LOC BE14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[10]"] ;# J22.C14 LA10_P +#set_property -dict {LOC BF14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[10]"] ;# J22.C15 LA10_N +#set_property -dict {LOC BC11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[11]"] ;# J22.H16 LA11_P +#set_property -dict {LOC BD11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[11]"] ;# J22.H17 LA11_N +#set_property -dict {LOC BE15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[12]"] ;# J22.G15 LA12_P +#set_property -dict {LOC BF15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[12]"] ;# J22.G16 LA12_N +#set_property -dict {LOC BA14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[13]"] ;# J22.D17 LA13_P +#set_property -dict {LOC BB14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[13]"] ;# J22.D18 LA13_N +#set_property -dict {LOC BB13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[14]"] ;# J22.C18 LA14_P +#set_property -dict {LOC BB12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[14]"] ;# J22.C19 LA14_N +#set_property -dict {LOC AV9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[15]"] ;# J22.H19 LA15_P +#set_property -dict {LOC AV8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[15]"] ;# J22.H20 LA15_N +#set_property -dict {LOC AY8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[16]"] ;# J22.G18 LA16_P +#set_property -dict {LOC AY7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[16]"] ;# J22.G19 LA16_N +#set_property -dict {LOC AV14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[17]"] ;# J22.D20 LA17_P_CC +#set_property -dict {LOC AV13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[17]"] ;# J22.D21 LA17_N_CC +#set_property -dict {LOC AP13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[18]"] ;# J22.C22 LA18_P_CC +#set_property -dict {LOC AR13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[18]"] ;# J22.C23 LA18_N_CC +#set_property -dict {LOC AV15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[19]"] ;# J22.H22 LA19_P +#set_property -dict {LOC AW15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[19]"] ;# J22.H23 LA19_N +#set_property -dict {LOC AY15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[20]"] ;# J22.G21 LA20_P +#set_property -dict {LOC AY14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[20]"] ;# J22.G22 LA20_N +#set_property -dict {LOC AN16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[21]"] ;# J22.H25 LA21_P +#set_property -dict {LOC AP16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[21]"] ;# J22.H26 LA21_N +#set_property -dict {LOC AN15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[22]"] ;# J22.G24 LA22_P +#set_property -dict {LOC AP15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[22]"] ;# J22.G25 LA22_N +#set_property -dict {LOC AT16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[23]"] ;# J22.D23 LA23_P +#set_property -dict {LOC AT15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[23]"] ;# J22.D24 LA23_N +#set_property -dict {LOC AK15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[24]"] ;# J22.H28 LA24_P +#set_property -dict {LOC AL15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[24]"] ;# J22.H29 LA24_N +#set_property -dict {LOC AM13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[25]"] ;# J22.G27 LA25_P +#set_property -dict {LOC AM12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[25]"] ;# J22.G28 LA25_N +#set_property -dict {LOC AL14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[26]"] ;# J22.D26 LA26_P +#set_property -dict {LOC AM14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[26]"] ;# J22.D27 LA26_N +#set_property -dict {LOC AN14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[27]"] ;# J22.C26 LA27_P +#set_property -dict {LOC AN13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[27]"] ;# J22.C27 LA27_N +#set_property -dict {LOC AJ13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[28]"] ;# J22.H31 LA28_P +#set_property -dict {LOC AJ12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[28]"] ;# J22.H32 LA28_N +#set_property -dict {LOC AK14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[29]"] ;# J22.G30 LA29_P +#set_property -dict {LOC AK13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[29]"] ;# J22.G31 LA29_N +#set_property -dict {LOC AK12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[30]"] ;# J22.H34 LA30_P +#set_property -dict {LOC AL12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[30]"] ;# J22.H35 LA30_N +#set_property -dict {LOC AP12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[31]"] ;# J22.G33 LA31_P +#set_property -dict {LOC AR12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[31]"] ;# J22.G34 LA31_N +#set_property -dict {LOC AU11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[32]"] ;# J22.H37 LA32_P +#set_property -dict {LOC AV11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[32]"] ;# J22.H38 LA32_N +#set_property -dict {LOC AU16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[33]"] ;# J22.G36 LA33_P +#set_property -dict {LOC AV16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[33]"] ;# J22.G37 LA33_N + +#set_property -dict {LOC N14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[0]"] ;# J22.F4 HA00_P_CC +#set_property -dict {LOC N13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[0]"] ;# J22.F5 HA00_N_CC +#set_property -dict {LOC T14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[1]"] ;# J22.E2 HA01_P_CC +#set_property -dict {LOC R13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[1]"] ;# J22.E3 HA01_N_CC +#set_property -dict {LOC T16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[2]"] ;# J22.K7 HA02_P +#set_property -dict {LOC T15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[2]"] ;# J22.K8 HA02_N +#set_property -dict {LOC K11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[3]"] ;# J22.J6 HA03_P +#set_property -dict {LOC J11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[3]"] ;# J22.J7 HA03_N +#set_property -dict {LOC AA13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[4]"] ;# J22.F7 HA04_P +#set_property -dict {LOC Y13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[4]"] ;# J22.F8 HA04_N +#set_property -dict {LOC AA12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[5]"] ;# J22.E6 HA05_P +#set_property -dict {LOC Y12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[5]"] ;# J22.E7 HA05_N +#set_property -dict {LOC P15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[6]"] ;# J22.K10 HA06_P +#set_property -dict {LOC N15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[6]"] ;# J22.K11 HA06_N +#set_property -dict {LOC R12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[7]"] ;# J22.J9 HA07_P +#set_property -dict {LOC P12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[7]"] ;# J22.J10 HA07_N +#set_property -dict {LOC W12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[8]"] ;# J22.F10 HA08_P +#set_property -dict {LOC V12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[8]"] ;# J22.F11 HA08_N +#set_property -dict {LOC AA14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[9]"] ;# J22.E9 HA09_P +#set_property -dict {LOC Y14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[9]"] ;# J22.E10 HA09_N +#set_property -dict {LOC K12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[10]"] ;# J22.K13 HA10_P +#set_property -dict {LOC J12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[10]"] ;# J22.K14 HA10_N +#set_property -dict {LOC M11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[11]"] ;# J22.J12 HA11_P +#set_property -dict {LOC L11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[11]"] ;# J22.J13 HA11_N +#set_property -dict {LOC V15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[12]"] ;# J22.F13 HA12_P +#set_property -dict {LOC U15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[12]"] ;# J22.F14 HA12_N +#set_property -dict {LOC W14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[13]"] ;# J22.E12 HA13_P +#set_property -dict {LOC V14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[13]"] ;# J22.E13 HA13_N +#set_property -dict {LOC K14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[14]"] ;# J22.J15 HA14_P +#set_property -dict {LOC K13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[14]"] ;# J22.J16 HA14_N +#set_property -dict {LOC V13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[15]"] ;# J22.F14 HA15_P +#set_property -dict {LOC U12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[15]"] ;# J22.F16 HA15_N +#set_property -dict {LOC V16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[16]"] ;# J22.E15 HA16_P +#set_property -dict {LOC U16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[16]"] ;# J22.E16 HA16_N +#set_property -dict {LOC U13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[17]"] ;# J22.K16 HA17_P_CC +#set_property -dict {LOC T13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[17]"] ;# J22.K17 HA17_N_CC +#set_property -dict {LOC L14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[18]"] ;# J22.J18 HA18_P_CC +#set_property -dict {LOC L13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[18]"] ;# J22.J19 HA18_N_CC +#set_property -dict {LOC R14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[19]"] ;# J22.F19 HA19_P +#set_property -dict {LOC P14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[19]"] ;# J22.F20 HA19_N +#set_property -dict {LOC R11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[20]"] ;# J22.E18 HA20_P +#set_property -dict {LOC P11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[20]"] ;# J22.E19 HA20_N +#set_property -dict {LOC M13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[21]"] ;# J22.K19 HA21_P +#set_property -dict {LOC M12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[21]"] ;# J22.K20 HA21_N +#set_property -dict {LOC M15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[22]"] ;# J22.J21 HA22_P +#set_property -dict {LOC L15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[22]"] ;# J22.J22 HA22_N +#set_property -dict {LOC U11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[23]"] ;# J22.K22 HA23_P +#set_property -dict {LOC T11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[23]"] ;# J22.K23 HA23_N + +#set_property -dict {LOC BB9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_clk0_m2c_p"] ;# J22.H4 CLK0_M2C_P +#set_property -dict {LOC BB8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_clk0_m2c_n"] ;# J22.H5 CLK0_M2C_N +#set_property -dict {LOC AU14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_clk1_m2c_p"] ;# J22.G2 CLK1_M2C_P +#set_property -dict {LOC AU13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_clk1_m2c_n"] ;# J22.G3 CLK1_M2C_N + +#set_property -dict {LOC AP22 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc0_pg_m2c}] ;# J22.F1 PG_M2C +#set_property -dict {LOC AL19 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc0_prsnt_m2c_l}] ;# J22.H2 PRSNT_M2C_L + +#set_property -dict {LOC G5 } [get_ports {fmc_hpc0_dp_c2m_p[0]}] ;# MGTHTXP0_230 GTHE3_CHANNEL_X0Y24 / GTHE3_COMMON_X0Y6 from J22.C2 DP0_C2M_P +#set_property -dict {LOC G4 } [get_ports {fmc_hpc0_dp_c2m_n[0]}] ;# MGTHTXN0_230 GTHE3_CHANNEL_X0Y24 / GTHE3_COMMON_X0Y6 from J22.C3 DP0_C2M_N +#set_property -dict {LOC K2 } [get_ports {fmc_hpc0_dp_m2c_p[0]}] ;# MGTHRXP0_230 GTHE3_CHANNEL_X0Y24 / GTHE3_COMMON_X0Y6 from J22.C6 DP0_M2C_P +#set_property -dict {LOC K1 } [get_ports {fmc_hpc0_dp_m2c_n[0]}] ;# MGTHRXN0_230 GTHE3_CHANNEL_X0Y24 / GTHE3_COMMON_X0Y6 from J22.C7 DP0_M2C_N +#set_property -dict {LOC F7 } [get_ports {fmc_hpc0_dp_c2m_p[1]}] ;# MGTHTXP1_230 GTHE3_CHANNEL_X0Y25 / GTHE3_COMMON_X0Y6 from J22.A22 DP1_C2M_P +#set_property -dict {LOC F6 } [get_ports {fmc_hpc0_dp_c2m_n[1]}] ;# MGTHTXN1_230 GTHE3_CHANNEL_X0Y25 / GTHE3_COMMON_X0Y6 from J22.A23 DP1_C2M_N +#set_property -dict {LOC H2 } [get_ports {fmc_hpc0_dp_m2c_p[1]}] ;# MGTHRXP1_230 GTHE3_CHANNEL_X0Y25 / GTHE3_COMMON_X0Y6 from J22.A2 DP1_M2C_P +#set_property -dict {LOC H1 } [get_ports {fmc_hpc0_dp_m2c_n[1]}] ;# MGTHRXN1_230 GTHE3_CHANNEL_X0Y25 / GTHE3_COMMON_X0Y6 from J22.A3 DP1_M2C_N +#set_property -dict {LOC E5 } [get_ports {fmc_hpc0_dp_c2m_p[2]}] ;# MGTHTXP2_230 GTHE3_CHANNEL_X0Y26 / GTHE3_COMMON_X0Y6 from J22.A26 DP2_C2M_P +#set_property -dict {LOC E4 } [get_ports {fmc_hpc0_dp_c2m_n[2]}] ;# MGTHTXN2_230 GTHE3_CHANNEL_X0Y26 / GTHE3_COMMON_X0Y6 from J22.A27 DP2_C2M_N +#set_property -dict {LOC F2 } [get_ports {fmc_hpc0_dp_m2c_p[2]}] ;# MGTHRXP2_230 GTHE3_CHANNEL_X0Y26 / GTHE3_COMMON_X0Y6 from J22.A6 DP2_M2C_P +#set_property -dict {LOC F1 } [get_ports {fmc_hpc0_dp_m2c_n[2]}] ;# MGTHRXN2_230 GTHE3_CHANNEL_X0Y26 / GTHE3_COMMON_X0Y6 from J22.A7 DP2_M2C_N +#set_property -dict {LOC C5 } [get_ports {fmc_hpc0_dp_c2m_p[3]}] ;# MGTHTXP3_230 GTHE3_CHANNEL_X0Y27 / GTHE3_COMMON_X0Y6 from J22.A30 DP3_C2M_P +#set_property -dict {LOC C4 } [get_ports {fmc_hpc0_dp_c2m_n[3]}] ;# MGTHTXN3_230 GTHE3_CHANNEL_X0Y27 / GTHE3_COMMON_X0Y6 from J22.A31 DP3_C2M_N +#set_property -dict {LOC D2 } [get_ports {fmc_hpc0_dp_m2c_p[3]}] ;# MGTHRXP3_230 GTHE3_CHANNEL_X0Y27 / GTHE3_COMMON_X0Y6 from J22.A10 DP3_M2C_P +#set_property -dict {LOC D1 } [get_ports {fmc_hpc0_dp_m2c_n[3]}] ;# MGTHRXN3_230 GTHE3_CHANNEL_X0Y27 / GTHE3_COMMON_X0Y6 from J22.A11 DP3_M2C_N + +#set_property -dict {LOC L5 } [get_ports {fmc_hpc0_dp_c2m_p[4]}] ;# MGTHTXP0_229 GTHE3_CHANNEL_X0Y20 / GTHE3_COMMON_X0Y5 from J22.A34 DP4_C2M_P +#set_property -dict {LOC L4 } [get_ports {fmc_hpc0_dp_c2m_n[4]}] ;# MGTHTXN0_229 GTHE3_CHANNEL_X0Y20 / GTHE3_COMMON_X0Y5 from J22.A35 DP4_C2M_N +#set_property -dict {LOC T2 } [get_ports {fmc_hpc0_dp_m2c_p[4]}] ;# MGTHRXP0_229 GTHE3_CHANNEL_X0Y20 / GTHE3_COMMON_X0Y5 from J22.A14 DP4_M2C_P +#set_property -dict {LOC T1 } [get_ports {fmc_hpc0_dp_m2c_n[4]}] ;# MGTHRXN0_229 GTHE3_CHANNEL_X0Y20 / GTHE3_COMMON_X0Y5 from J22.A15 DP4_M2C_N +#set_property -dict {LOC K7 } [get_ports {fmc_hpc0_dp_c2m_p[5]}] ;# MGTHTXP1_229 GTHE3_CHANNEL_X0Y21 / GTHE3_COMMON_X0Y5 from J22.A38 DP5_C2M_P +#set_property -dict {LOC K6 } [get_ports {fmc_hpc0_dp_c2m_n[5]}] ;# MGTHTXN1_229 GTHE3_CHANNEL_X0Y21 / GTHE3_COMMON_X0Y5 from J22.A39 DP5_C2M_N +#set_property -dict {LOC R4 } [get_ports {fmc_hpc0_dp_m2c_p[5]}] ;# MGTHRXP1_229 GTHE3_CHANNEL_X0Y21 / GTHE3_COMMON_X0Y5 from J22.A18 DP5_M2C_P +#set_property -dict {LOC R3 } [get_ports {fmc_hpc0_dp_m2c_n[5]}] ;# MGTHRXN1_229 GTHE3_CHANNEL_X0Y21 / GTHE3_COMMON_X0Y5 from J22.A19 DP5_M2C_N +#set_property -dict {LOC J5 } [get_ports {fmc_hpc0_dp_c2m_p[6]}] ;# MGTHTXP2_229 GTHE3_CHANNEL_X0Y22 / GTHE3_COMMON_X0Y5 from J22.B36 DP6_C2M_P +#set_property -dict {LOC J4 } [get_ports {fmc_hpc0_dp_c2m_n[6]}] ;# MGTHTXN2_229 GTHE3_CHANNEL_X0Y22 / GTHE3_COMMON_X0Y5 from J22.B37 DP6_C2M_N +#set_property -dict {LOC P2 } [get_ports {fmc_hpc0_dp_m2c_p[6]}] ;# MGTHRXP2_229 GTHE3_CHANNEL_X0Y22 / GTHE3_COMMON_X0Y5 from J22.B16 DP6_M2C_P +#set_property -dict {LOC P1 } [get_ports {fmc_hpc0_dp_m2c_n[6]}] ;# MGTHRXN2_229 GTHE3_CHANNEL_X0Y22 / GTHE3_COMMON_X0Y5 from J22.B17 DP6_M2C_N +#set_property -dict {LOC H7 } [get_ports {fmc_hpc0_dp_c2m_p[7]}] ;# MGTHTXP3_229 GTHE3_CHANNEL_X0Y23 / GTHE3_COMMON_X0Y5 from J22.B32 DP7_C2M_P +#set_property -dict {LOC H6 } [get_ports {fmc_hpc0_dp_c2m_n[7]}] ;# MGTHTXN3_229 GTHE3_CHANNEL_X0Y23 / GTHE3_COMMON_X0Y5 from J22.B33 DP7_C2M_N +#set_property -dict {LOC M2 } [get_ports {fmc_hpc0_dp_m2c_p[7]}] ;# MGTHRXP3_229 GTHE3_CHANNEL_X0Y23 / GTHE3_COMMON_X0Y5 from J22.B12 DP7_M2C_P +#set_property -dict {LOC M1 } [get_ports {fmc_hpc0_dp_m2c_n[7]}] ;# MGTHRXN3_229 GTHE3_CHANNEL_X0Y23 / GTHE3_COMMON_X0Y5 from J22.B13 DP7_M2C_N +#set_property -dict {LOC R9 } [get_ports fmc_hpc0_mgt_refclk_0_p] ;# MGTREFCLK0P_229 from J22.D4 GBTCLK0_M2C_P +#set_property -dict {LOC R8 } [get_ports fmc_hpc0_mgt_refclk_0_n] ;# MGTREFCLK0N_229 from J22.D5 GBTCLK0_M2C_N +#set_property -dict {LOC N9 } [get_ports fmc_hpc0_mgt_refclk_1_p] ;# MGTREFCLK1P_229 from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC N8 } [get_ports fmc_hpc0_mgt_refclk_1_n] ;# MGTREFCLK1N_229 from J22.B21 GBTCLK1_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmc_hpc0_mgt_refclk_0 [get_ports fmc_hpc0_mgt_refclk_0_p] +#create_clock -period 6.400 -name fmc_hpc0_mgt_refclk_1 [get_ports fmc_hpc0_mgt_refclk_1_p] + +#set_property -dict {LOC V7 } [get_ports {fmc_hpc0_dp_c2m_p[8]}] ;# MGTHTXP0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.B28 DP8_C2M_P +#set_property -dict {LOC V6 } [get_ports {fmc_hpc0_dp_c2m_n[8]}] ;# MGTHTXN0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.B29 DP8_C2M_N +#set_property -dict {LOC Y2 } [get_ports {fmc_hpc0_dp_m2c_p[8]}] ;# MGTHRXP0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.B8 DP8_M2C_P +#set_property -dict {LOC Y1 } [get_ports {fmc_hpc0_dp_m2c_n[8]}] ;# MGTHRXN0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.B9 DP8_M2C_N +#set_property -dict {LOC T7 } [get_ports {fmc_hpc0_dp_c2m_p[9]}] ;# MGTHTXP1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.B24 DP9_C2M_P +#set_property -dict {LOC T6 } [get_ports {fmc_hpc0_dp_c2m_n[9]}] ;# MGTHTXN1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.B25 DP9_C2M_N +#set_property -dict {LOC W4 } [get_ports {fmc_hpc0_dp_m2c_p[9]}] ;# MGTHRXP1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.B4 DP9_M2C_P +#set_property -dict {LOC W3 } [get_ports {fmc_hpc0_dp_m2c_n[9]}] ;# MGTHRXN1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.B5 DP9_M2C_N +#set_property -dict {LOC W9 } [get_ports fmc_hpc0_mgt_refclk_2_p] ;# MGTREFCLK0P_228 from from J87 P1 +#set_property -dict {LOC W8 } [get_ports fmc_hpc0_mgt_refclk_2_n] ;# MGTREFCLK0N_228 from from J87 P2 + +# reference clock +#create_clock -period 6.400 -name fmc_hpc1_mgt_refclk_2 [get_ports fmc_hpc1_mgt_refclk_2_p] + +# FMC HPC1 J2 +#set_property -dict {LOC T33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[0]"] ;# J2.G9 LA00_P_CC +#set_property -dict {LOC R33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[0]"] ;# J2.G10 LA00_N_CC +#set_property -dict {LOC P35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[1]"] ;# J2.D8 LA01_P_CC +#set_property -dict {LOC P36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[1]"] ;# J2.D9 LA01_N_CC +#set_property -dict {LOC N33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[2]"] ;# J2.H7 LA02_P +#set_property -dict {LOC M33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[2]"] ;# J2.H8 LA02_N +#set_property -dict {LOC N34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[3]"] ;# J2.G12 LA03_P +#set_property -dict {LOC N35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[3]"] ;# J2.G13 LA03_N +#set_property -dict {LOC M37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[4]"] ;# J2.H10 LA04_P +#set_property -dict {LOC L38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[4]"] ;# J2.H11 LA04_N +#set_property -dict {LOC N38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[5]"] ;# J2.D11 LA05_P +#set_property -dict {LOC M38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[5]"] ;# J2.D12 LA05_N +#set_property -dict {LOC P37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[6]"] ;# J2.C10 LA06_P +#set_property -dict {LOC N37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[6]"] ;# J2.C11 LA06_N +#set_property -dict {LOC L34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[7]"] ;# J2.H13 LA07_P +#set_property -dict {LOC K34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[7]"] ;# J2.H14 LA07_N +#set_property -dict {LOC M35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[8]"] ;# J2.G12 LA08_P +#set_property -dict {LOC L35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[8]"] ;# J2.G13 LA08_N +#set_property -dict {LOC M36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[9]"] ;# J2.D14 LA09_P +#set_property -dict {LOC L36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[9]"] ;# J2.D15 LA09_N +#set_property -dict {LOC N32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[10]"] ;# J2.C14 LA10_P +#set_property -dict {LOC M32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[10]"] ;# J2.C15 LA10_N +#set_property -dict {LOC Y31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[11]"] ;# J2.H16 LA11_P +#set_property -dict {LOC W31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[11]"] ;# J2.H17 LA11_N +#set_property -dict {LOC R31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[12]"] ;# J2.G15 LA12_P +#set_property -dict {LOC P31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[12]"] ;# J2.G16 LA12_N +#set_property -dict {LOC T30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[13]"] ;# J2.D17 LA13_P +#set_property -dict {LOC T31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[13]"] ;# J2.D18 LA13_N +#set_property -dict {LOC L33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[14]"] ;# J2.C18 LA14_P +#set_property -dict {LOC K33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[14]"] ;# J2.C19 LA14_N +#set_property -dict {LOC T34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[15]"] ;# J2.H19 LA15_P +#set_property -dict {LOC T35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[15]"] ;# J2.H20 LA15_N +#set_property -dict {LOC U31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[16]"] ;# J2.G18 LA16_P +#set_property -dict {LOC U32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[16]"] ;# J2.G19 LA16_N +#set_property -dict {LOC AJ32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[17]"] ;# J2.D20 LA17_P_CC +#set_property -dict {LOC AK32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[17]"] ;# J2.D21 LA17_N_CC +#set_property -dict {LOC AL32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[18]"] ;# J2.C22 LA18_P_CC +#set_property -dict {LOC AM32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[18]"] ;# J2.C23 LA18_N_CC +#set_property -dict {LOC AT39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[19]"] ;# J2.H22 LA19_P +#set_property -dict {LOC AT40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[19]"] ;# J2.H23 LA19_N +#set_property -dict {LOC AR37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[20]"] ;# J2.G21 LA20_P +#set_property -dict {LOC AT37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[20]"] ;# J2.G22 LA20_N +#set_property -dict {LOC AT35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[21]"] ;# J2.H25 LA21_P +#set_property -dict {LOC AT36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[21]"] ;# J2.H26 LA21_N +#set_property -dict {LOC AL30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[22]"] ;# J2.G24 LA22_P +#set_property -dict {LOC AL31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[22]"] ;# J2.G25 LA22_N +#set_property -dict {LOC AN33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[23]"] ;# J2.D23 LA23_P +#set_property -dict {LOC AP33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[23]"] ;# J2.D24 LA23_N +#set_property -dict {LOC AM36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[24]"] ;# J2.H28 LA24_P +#set_property -dict {LOC AN36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[24]"] ;# J2.H29 LA24_N +#set_property -dict {LOC AP36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[25]"] ;# J2.G27 LA25_P +#set_property -dict {LOC AP37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[25]"] ;# J2.G28 LA25_N +#set_property -dict {LOC AL29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[26]"] ;# J2.D26 LA26_P +#set_property -dict {LOC AM29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[26]"] ;# J2.D27 LA26_N +#set_property -dict {LOC AP35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[27]"] ;# J2.C26 LA27_P +#set_property -dict {LOC AR35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[27]"] ;# J2.C27 LA27_N +#set_property -dict {LOC AL35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[28]"] ;# J2.H31 LA28_P +#set_property -dict {LOC AL36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[28]"] ;# J2.H32 LA28_N +#set_property -dict {LOC AP38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[29]"] ;# J2.G30 LA29_P +#set_property -dict {LOC AR38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[29]"] ;# J2.G31 LA29_N +#set_property -dict {LOC AJ30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[30]"] ;# J2.H34 LA30_P +#set_property -dict {LOC AJ31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[30]"] ;# J2.H35 LA30_N +#set_property -dict {LOC AN34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[31]"] ;# J2.G33 LA31_P +#set_property -dict {LOC AN35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[31]"] ;# J2.G34 LA31_N +#set_property -dict {LOC AG31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[32]"] ;# J2.H37 LA32_P +#set_property -dict {LOC AH31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[32]"] ;# J2.H38 LA32_N +#set_property -dict {LOC AG32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[33]"] ;# J2.G36 LA33_P +#set_property -dict {LOC AG33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[33]"] ;# J2.G37 LA33_N + +#set_property -dict {LOC R32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_clk0_m2c_p"] ;# J2.H4 CLK0_M2C_P +#set_property -dict {LOC P32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_clk0_m2c_n"] ;# J2.H5 CLK0_M2C_N +#set_property -dict {LOC AK34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_clk1_m2c_p"] ;# J2.G2 CLK1_M2C_P +#set_property -dict {LOC AL34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_clk1_m2c_n"] ;# J2.G3 CLK1_M2C_N + +#set_property -dict {LOC AU24 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc1_pg_m2c}] ;# J2.F1 PG_M2C +#set_property -dict {LOC BD23 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc1_prsnt_m2c_l}] ;# J2.H2 PRSNT_M2C_L + +#set_property -dict {LOC AN5 } [get_ports {fmc_hpc1_dp_c2m_p[0]}] ;# MGTHTXP0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C2 DP0_C2M_P +#set_property -dict {LOC AN4 } [get_ports {fmc_hpc1_dp_c2m_n[0]}] ;# MGTHTXN0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C3 DP0_C2M_N +#set_property -dict {LOC AH2 } [get_ports {fmc_hpc1_dp_m2c_p[0]}] ;# MGTHRXP0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C6 DP0_M2C_P +#set_property -dict {LOC AH1 } [get_ports {fmc_hpc1_dp_m2c_n[0]}] ;# MGTHRXN0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C7 DP0_M2C_N +#set_property -dict {LOC AM7 } [get_ports {fmc_hpc1_dp_c2m_p[1]}] ;# MGTHTXP1_226 GTHE3_CHANNEL_X0Y9 / GTHE3_COMMON_X0Y2 from J2.A22 DP1_C2M_P +#set_property -dict {LOC AM6 } [get_ports {fmc_hpc1_dp_c2m_n[1]}] ;# MGTHTXN1_226 GTHE3_CHANNEL_X0Y9 / GTHE3_COMMON_X0Y2 from J2.A23 DP1_C2M_N +#set_property -dict {LOC AG4 } [get_ports {fmc_hpc1_dp_m2c_p[1]}] ;# MGTHRXP1_226 GTHE3_CHANNEL_X0Y9 / GTHE3_COMMON_X0Y2 from J2.A2 DP1_M2C_P +#set_property -dict {LOC AG3 } [get_ports {fmc_hpc1_dp_m2c_n[1]}] ;# MGTHRXN1_226 GTHE3_CHANNEL_X0Y9 / GTHE3_COMMON_X0Y2 from J2.A3 DP1_M2C_N +#set_property -dict {LOC AK7 } [get_ports {fmc_hpc1_dp_c2m_p[2]}] ;# MGTHTXP2_226 GTHE3_CHANNEL_X0Y10 / GTHE3_COMMON_X0Y2 from J2.A26 DP2_C2M_P +#set_property -dict {LOC AK6 } [get_ports {fmc_hpc1_dp_c2m_n[2]}] ;# MGTHTXN2_226 GTHE3_CHANNEL_X0Y10 / GTHE3_COMMON_X0Y2 from J2.A27 DP2_C2M_N +#set_property -dict {LOC AF2 } [get_ports {fmc_hpc1_dp_m2c_p[2]}] ;# MGTHRXP2_226 GTHE3_CHANNEL_X0Y10 / GTHE3_COMMON_X0Y2 from J2.A6 DP2_M2C_P +#set_property -dict {LOC AF1 } [get_ports {fmc_hpc1_dp_m2c_n[2]}] ;# MGTHRXN2_226 GTHE3_CHANNEL_X0Y10 / GTHE3_COMMON_X0Y2 from J2.A7 DP2_M2C_N +#set_property -dict {LOC AH7 } [get_ports {fmc_hpc1_dp_c2m_p[3]}] ;# MGTHTXP3_226 GTHE3_CHANNEL_X0Y11 / GTHE3_COMMON_X0Y2 from J2.A30 DP3_C2M_P +#set_property -dict {LOC AH6 } [get_ports {fmc_hpc1_dp_c2m_n[3]}] ;# MGTHTXN3_226 GTHE3_CHANNEL_X0Y11 / GTHE3_COMMON_X0Y2 from J2.A31 DP3_C2M_N +#set_property -dict {LOC AE4 } [get_ports {fmc_hpc1_dp_m2c_p[3]}] ;# MGTHRXP3_226 GTHE3_CHANNEL_X0Y11 / GTHE3_COMMON_X0Y2 from J2.A10 DP3_M2C_P +#set_property -dict {LOC AE3 } [get_ports {fmc_hpc1_dp_m2c_n[3]}] ;# MGTHRXN3_226 GTHE3_CHANNEL_X0Y11 / GTHE3_COMMON_X0Y2 from J2.A11 DP3_M2C_N + +#set_property -dict {LOC AF7 } [get_ports {fmc_hpc1_dp_c2m_p[4]}] ;# MGTHTXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J2.A34 DP4_C2M_P +#set_property -dict {LOC AF6 } [get_ports {fmc_hpc1_dp_c2m_n[4]}] ;# MGTHTXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J2.A35 DP4_C2M_N +#set_property -dict {LOC AD2 } [get_ports {fmc_hpc1_dp_m2c_p[4]}] ;# MGTHRXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J2.A14 DP4_M2C_P +#set_property -dict {LOC AD1 } [get_ports {fmc_hpc1_dp_m2c_n[4]}] ;# MGTHRXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J2.A15 DP4_M2C_N +#set_property -dict {LOC AD7 } [get_ports {fmc_hpc1_dp_c2m_p[5]}] ;# MGTHTXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J2.A38 DP5_C2M_P +#set_property -dict {LOC AD6 } [get_ports {fmc_hpc1_dp_c2m_n[5]}] ;# MGTHTXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J2.A39 DP5_C2M_N +#set_property -dict {LOC AC4 } [get_ports {fmc_hpc1_dp_m2c_p[5]}] ;# MGTHRXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J2.A18 DP5_M2C_P +#set_property -dict {LOC AC3 } [get_ports {fmc_hpc1_dp_m2c_n[5]}] ;# MGTHRXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J2.A19 DP5_M2C_N +#set_property -dict {LOC AB7 } [get_ports {fmc_hpc1_dp_c2m_p[6]}] ;# MGTHTXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J2.B36 DP6_C2M_P +#set_property -dict {LOC AB6 } [get_ports {fmc_hpc1_dp_c2m_n[6]}] ;# MGTHTXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J2.B37 DP6_C2M_N +#set_property -dict {LOC AB2 } [get_ports {fmc_hpc1_dp_m2c_p[6]}] ;# MGTHRXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J2.B16 DP6_M2C_P +#set_property -dict {LOC AB1 } [get_ports {fmc_hpc1_dp_m2c_n[6]}] ;# MGTHRXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J2.B17 DP6_M2C_N +#set_property -dict {LOC Y7 } [get_ports {fmc_hpc1_dp_c2m_p[7]}] ;# MGTHTXP3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J2.B32 DP7_C2M_P +#set_property -dict {LOC Y6 } [get_ports {fmc_hpc1_dp_c2m_n[7]}] ;# MGTHTXN3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J2.B33 DP7_C2M_N +#set_property -dict {LOC AA4 } [get_ports {fmc_hpc1_dp_m2c_p[7]}] ;# MGTHRXP3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J2.B12 DP7_M2C_P +#set_property -dict {LOC AA3 } [get_ports {fmc_hpc1_dp_m2c_n[7]}] ;# MGTHRXN3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J2.B13 DP7_M2C_N +#set_property -dict {LOC AC9 } [get_ports fmc_hpc1_mgt_refclk_0_p] ;# MGTREFCLK0P_227 from J2.D4 GBTCLK0_M2C_P +#set_property -dict {LOC AC8 } [get_ports fmc_hpc1_mgt_refclk_0_n] ;# MGTREFCLK0N_227 from J2.D5 GBTCLK0_M2C_N +#set_property -dict {LOC AA9 } [get_ports fmc_hpc1_mgt_refclk_1_p] ;# MGTREFCLK1P_227 from J2.B20 GBTCLK1_M2C_P +#set_property -dict {LOC AA8 } [get_ports fmc_hpc1_mgt_refclk_1_n] ;# MGTREFCLK1N_227 from J2.B21 GBTCLK1_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmc_hpc0_mgt_refclk_0 [get_ports fmc_hpc0_mgt_refclk_0_p] +#create_clock -period 6.400 -name fmc_hpc0_mgt_refclk_1 [get_ports fmc_hpc0_mgt_refclk_1_p] + +#set_property -dict {LOC P7 } [get_ports {fmc_hpc1_dp_c2m_p[8]}] ;# MGTHTXP2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B28 DP8_C2M_P +#set_property -dict {LOC P6 } [get_ports {fmc_hpc1_dp_c2m_n[8]}] ;# MGTHTXN2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B29 DP8_C2M_N +#set_property -dict {LOC V2 } [get_ports {fmc_hpc1_dp_m2c_p[8]}] ;# MGTHRXP2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B8 DP8_M2C_P +#set_property -dict {LOC V1 } [get_ports {fmc_hpc1_dp_m2c_n[8]}] ;# MGTHRXN2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B9 DP8_M2C_N +#set_property -dict {LOC M7 } [get_ports {fmc_hpc1_dp_c2m_p[9]}] ;# MGTHTXP3_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B24 DP9_C2M_P +#set_property -dict {LOC M6 } [get_ports {fmc_hpc1_dp_c2m_n[9]}] ;# MGTHTXN3_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B25 DP9_C2M_N +#set_property -dict {LOC U4 } [get_ports {fmc_hpc1_dp_m2c_p[9]}] ;# MGTHRXP3_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B4 DP9_M2C_P +#set_property -dict {LOC U3 } [get_ports {fmc_hpc1_dp_m2c_n[9]}] ;# MGTHRXN3_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B5 DP9_M2C_N +#set_property -dict {LOC W9 } [get_ports fmc_hpc1_mgt_refclk_2_p] ;# MGTREFCLK0P_228 from from J87 P1 +#set_property -dict {LOC W8 } [get_ports fmc_hpc1_mgt_refclk_2_n] ;# MGTREFCLK0N_228 from from J87 P2 + +# reference clock +#create_clock -period 6.400 -name fmc_hpc0_mgt_refclk_2 [get_ports fmc_hpc0_mgt_refclk_2_p] + +# DDR4 C1 +# 5x MT40A256M16GE-075E +#set_property -dict {LOC C30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +#set_property -dict {LOC D32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +#set_property -dict {LOC B30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +#set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +#set_property -dict {LOC E32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +#set_property -dict {LOC A29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +#set_property -dict {LOC C29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +#set_property -dict {LOC E29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +#set_property -dict {LOC A30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +#set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +#set_property -dict {LOC A31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +#set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +#set_property -dict {LOC F29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +#set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +#set_property -dict {LOC D29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +#set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +#set_property -dict {LOC B33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +#set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +#set_property -dict {LOC F30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +#set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +#set_property -dict {LOC E31 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}] +#set_property -dict {LOC D31 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}] +#set_property -dict {LOC K29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}] +#set_property -dict {LOC D30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}] +#set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}] +#set_property -dict {LOC R29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +#set_property -dict {LOC M28 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] +#set_property -dict {LOC J40 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}] + +#set_property -dict {LOC J37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] ;# U60.G2 DQL0 +#set_property -dict {LOC H40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] ;# U60.F7 DQL1 +#set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] ;# U60.H3 DQL2 +#set_property -dict {LOC H39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] ;# U60.H7 DQL3 +#set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] ;# U60.H2 DQL4 +#set_property -dict {LOC G40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] ;# U60.H8 DQL5 +#set_property -dict {LOC F39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] ;# U60.J3 DQL6 +#set_property -dict {LOC F40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] ;# U60.J7 DQL7 +#set_property -dict {LOC F36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] ;# U60.A3 DQU0 +#set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] ;# U60.B8 DQU1 +#set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] ;# U60.C3 DQU2 +#set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] ;# U60.C7 DQU3 +#set_property -dict {LOC G37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] ;# U60.C2 DQU4 +#set_property -dict {LOC H35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] ;# U60.C8 DQU5 +#set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] ;# U60.D3 DQU6 +#set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] ;# U60.D7 DQU7 +#set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] ;# U60.G3 DQSL_T +#set_property -dict {LOC G38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] ;# U60.F3 DQSL_C +#set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] ;# U60.B7 DQSU_T +#set_property -dict {LOC G35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] ;# U60.A7 DQSU_C +#set_property -dict {LOC J39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] ;# U60.E7 DML_B/DBIL_B +#set_property -dict {LOC F34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] ;# U60.E2 DMU_B/DBIU_B + +#set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] ;# U61.G2 DQL0 +#set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] ;# U61.F7 DQL1 +#set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] ;# U61.H3 DQL2 +#set_property -dict {LOC D40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] ;# U61.H7 DQL3 +#set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] ;# U61.H2 DQL4 +#set_property -dict {LOC B38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] ;# U61.H8 DQL5 +#set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] ;# U61.J3 DQL6 +#set_property -dict {LOC C40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] ;# U61.J7 DQL7 +#set_property -dict {LOC C34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] ;# U61.A3 DQU0 +#set_property -dict {LOC A34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] ;# U61.B8 DQU1 +#set_property -dict {LOC D34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] ;# U61.C3 DQU2 +#set_property -dict {LOC A35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] ;# U61.C7 DQU3 +#set_property -dict {LOC A36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] ;# U61.C2 DQU4 +#set_property -dict {LOC C35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] ;# U61.C8 DQU5 +#set_property -dict {LOC B35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] ;# U61.D3 DQU6 +#set_property -dict {LOC D35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] ;# U61.D7 DQU7 +#set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] ;# U61.G3 DQSL_T +#set_property -dict {LOC A40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] ;# U61.F3 DQSL_C +#set_property -dict {LOC B36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] ;# U61.B7 DQSU_T +#set_property -dict {LOC B37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] ;# U61.A7 DQSU_C +#set_property -dict {LOC E39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] ;# U61.E7 DML_B/DBIL_B +#set_property -dict {LOC D37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] ;# U61.E2 DMU_B/DBIU_B + +#set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] ;# U62.G2 DQL0 +#set_property -dict {LOC R27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] ;# U62.F7 DQL1 +#set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] ;# U62.H3 DQL2 +#set_property -dict {LOC R24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] ;# U62.H7 DQL3 +#set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] ;# U62.H2 DQL4 +#set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] ;# U62.H8 DQL5 +#set_property -dict {LOC P27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] ;# U62.J3 DQL6 +#set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] ;# U62.J7 DQL7 +#set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] ;# U62.A3 DQU0 +#set_property -dict {LOC L26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] ;# U62.B8 DQU1 +#set_property -dict {LOC J27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] ;# U62.C3 DQU2 +#set_property -dict {LOC K28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] ;# U62.C7 DQU3 +#set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] ;# U62.C2 DQU4 +#set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] ;# U62.C8 DQU5 +#set_property -dict {LOC J26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] ;# U62.D3 DQU6 +#set_property -dict {LOC L28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] ;# U62.D7 DQU7 +#set_property -dict {LOC P25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] ;# U62.G3 DQSL_T +#set_property -dict {LOC N25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] ;# U62.F3 DQSL_C +#set_property -dict {LOC L24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] ;# U62.B7 DQSU_T +#set_property -dict {LOC L25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] ;# U62.A7 DQSU_C +#set_property -dict {LOC T26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] ;# U62.E7 DML_B/DBIL_B +#set_property -dict {LOC M27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] ;# U62.E2 DMU_B/DBIU_B + +#set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] ;# U63.G2 DQL0 +#set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] ;# U63.F7 DQL1 +#set_property -dict {LOC E26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] ;# U63.H3 DQL2 +#set_property -dict {LOC H27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] ;# U63.H7 DQL3 +#set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] ;# U63.H2 DQL4 +#set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] ;# U63.H8 DQL5 +#set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] ;# U63.J3 DQL6 +#set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] ;# U63.J7 DQL7 +#set_property -dict {LOC B28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] ;# U63.A3 DQU0 +#set_property -dict {LOC A28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] ;# U63.B8 DQU1 +#set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] ;# U63.C3 DQU2 +#set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] ;# U63.C7 DQU3 +#set_property -dict {LOC D25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] ;# U63.C2 DQU4 +#set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] ;# U63.C8 DQU5 +#set_property -dict {LOC C25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] ;# U63.D3 DQU6 +#set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] ;# U63.D7 DQU7 +#set_property -dict {LOC H28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] ;# U63.G3 DQSL_T +#set_property -dict {LOC G28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] ;# U63.F3 DQSL_C +#set_property -dict {LOC B26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] ;# U63.B7 DQSU_T +#set_property -dict {LOC A26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] ;# U63.A7 DQSU_C +#set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] ;# U63.E7 DML_B/DBIL_B +#set_property -dict {LOC D27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] ;# U63.E2 DMU_B/DBIU_B + +#set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] ;# U64.G2 DQL0 +#set_property -dict {LOC M31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] ;# U64.F7 DQL1 +#set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] ;# U64.H3 DQL2 +#set_property -dict {LOC L29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] ;# U64.H7 DQL3 +#set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] ;# U64.H2 DQL4 +#set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] ;# U64.H8 DQL5 +#set_property -dict {LOC L31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] ;# U64.J3 DQL6 +#set_property -dict {LOC L30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] ;# U64.J7 DQL7 +#set_property -dict {LOC H30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[72]}] ;# U64.A3 DQU0 +#set_property -dict {LOC J32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[73]}] ;# U64.B8 DQU1 +#set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[74]}] ;# U64.C3 DQU2 +#set_property -dict {LOC H32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[75]}] ;# U64.C7 DQU3 +#set_property -dict {LOC J29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[76]}] ;# U64.C2 DQU4 +#set_property -dict {LOC K32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[77]}] ;# U64.C8 DQU5 +#set_property -dict {LOC J30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[78]}] ;# U64.D3 DQU6 +#set_property -dict {LOC G32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[79]}] ;# U64.D7 DQU7 +#set_property -dict {LOC N30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] ;# U64.G3 DQSL_T +#set_property -dict {LOC M30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] ;# U64.F3 DQSL_C +#set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] ;# U64.B7 DQSU_T +#set_property -dict {LOC G33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] ;# U64.A7 DQSU_C +#set_property -dict {LOC R28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}] ;# U64.E7 DML_B/DBIL_B +#set_property -dict {LOC K31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[9]}] ;# U64.E2 DMU_B/DBIU_B + +# DDR4 C2 +# 5x MT40A256M16GE-075E +#set_property -dict {LOC AM27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +#set_property -dict {LOC AT25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +#set_property -dict {LOC AN25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +#set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +#set_property -dict {LOC AR25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +#set_property -dict {LOC AU28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +#set_property -dict {LOC AU27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +#set_property -dict {LOC AR28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +#set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +#set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +#set_property -dict {LOC AN28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +#set_property -dict {LOC AR27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +#set_property -dict {LOC AP28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +#set_property -dict {LOC AL27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +#set_property -dict {LOC AP27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +#set_property -dict {LOC AM28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +#set_property -dict {LOC AU26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +#set_property -dict {LOC AV26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +#set_property -dict {LOC AV28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +#set_property -dict {LOC AT26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t}] +#set_property -dict {LOC AT27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c}] +#set_property -dict {LOC AY29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke}] +#set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n}] +#set_property -dict {LOC AW28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +#set_property -dict {LOC BB29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt}] +#set_property -dict {LOC BF29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +#set_property -dict {LOC BF40 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] +#set_property -dict {LOC AV25 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_alert_n}] + +#set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] ;# U135.G2 DQL0 +#set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] ;# U135.F7 DQL1 +#set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] ;# U135.H3 DQL2 +#set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] ;# U135.H7 DQL3 +#set_property -dict {LOC BD31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] ;# U135.H2 DQL4 +#set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] ;# U135.H8 DQL5 +#set_property -dict {LOC BD32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] ;# U135.J3 DQL6 +#set_property -dict {LOC BC31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] ;# U135.J7 DQL7 +#set_property -dict {LOC BA31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] ;# U135.A3 DQU0 +#set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] ;# U135.B8 DQU1 +#set_property -dict {LOC BA30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] ;# U135.C3 DQU2 +#set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] ;# U135.C7 DQU3 +#set_property -dict {LOC AW32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] ;# U135.C2 DQU4 +#set_property -dict {LOC BB33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] ;# U135.C8 DQU5 +#set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] ;# U135.D3 DQU6 +#set_property -dict {LOC BA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] ;# U135.D7 DQU7 +#set_property -dict {LOC BF30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] ;# U135.G3 DQSL_T +#set_property -dict {LOC BF31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] ;# U135.F3 DQSL_C +#set_property -dict {LOC AY34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] ;# U135.B7 DQSU_T +#set_property -dict {LOC BA34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] ;# U135.A7 DQSU_C +#set_property -dict {LOC BE32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[0]}] ;# U135.E7 DML_B/DBIL_B +#set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[1]}] ;# U135.E2 DMU_B/DBIU_B + +#set_property -dict {LOC AT31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] ;# U136.G2 DQL0 +#set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] ;# U136.F7 DQL1 +#set_property -dict {LOC AV30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] ;# U136.H3 DQL2 +#set_property -dict {LOC AU33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] ;# U136.H7 DQL3 +#set_property -dict {LOC AU31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] ;# U136.H2 DQL4 +#set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] ;# U136.H8 DQL5 +#set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] ;# U136.J3 DQL6 +#set_property -dict {LOC AU34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] ;# U136.J7 DQL7 +#set_property -dict {LOC AT29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] ;# U136.A3 DQU0 +#set_property -dict {LOC AT34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] ;# U136.B8 DQU1 +#set_property -dict {LOC AT30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] ;# U136.C3 DQU2 +#set_property -dict {LOC AR33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] ;# U136.C7 DQU3 +#set_property -dict {LOC AR30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] ;# U136.C2 DQU4 +#set_property -dict {LOC AN30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] ;# U136.C8 DQU5 +#set_property -dict {LOC AP30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] ;# U136.D3 DQU6 +#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] ;# U136.D7 DQU7 +#set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] ;# U136.G3 DQSL_T +#set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] ;# U136.F3 DQSL_C +#set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] ;# U136.B7 DQSU_T +#set_property -dict {LOC AP32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] ;# U136.A7 DQSU_C +#set_property -dict {LOC AV33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[2]}] ;# U136.E7 DML_B/DBIL_B +#set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[3]}] ;# U136.E2 DMU_B/DBIU_B + +#set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] ;# U137.G2 DQL0 +#set_property -dict {LOC BF36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] ;# U137.F7 DQL1 +#set_property -dict {LOC BC35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] ;# U137.H3 DQL2 +#set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] ;# U137.H7 DQL3 +#set_property -dict {LOC BE34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] ;# U137.H2 DQL4 +#set_property -dict {LOC BD36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] ;# U137.H8 DQL5 +#set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] ;# U137.J3 DQL6 +#set_property -dict {LOC BC36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] ;# U137.J7 DQL7 +#set_property -dict {LOC BD37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] ;# U137.A3 DQU0 +#set_property -dict {LOC BE38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] ;# U137.B8 DQU1 +#set_property -dict {LOC BD38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] ;# U137.C3 DQU2 +#set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] ;# U137.C7 DQU3 +#set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] ;# U137.C2 DQU4 +#set_property -dict {LOC BB39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] ;# U137.C8 DQU5 +#set_property -dict {LOC BC39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] ;# U137.D3 DQU6 +#set_property -dict {LOC BC38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] ;# U137.D7 DQU7 +#set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] ;# U137.G3 DQSL_T +#set_property -dict {LOC BF35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] ;# U137.F3 DQSL_C +#set_property -dict {LOC BE39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] ;# U137.B7 DQSU_T +#set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] ;# U137.A7 DQSU_C +#set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[4]}] ;# U137.E7 DML_B/DBIL_B +#set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[5]}] ;# U137.E2 DMU_B/DBIU_B + +#set_property -dict {LOC AW40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] ;# U138.G2 DQL0 +#set_property -dict {LOC BA40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] ;# U138.F7 DQL1 +#set_property -dict {LOC AY39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] ;# U138.H3 DQL2 +#set_property -dict {LOC AY38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] ;# U138.H7 DQL3 +#set_property -dict {LOC AY40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] ;# U138.H2 DQL4 +#set_property -dict {LOC BA39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] ;# U138.H8 DQL5 +#set_property -dict {LOC BB36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] ;# U138.J3 DQL6 +#set_property -dict {LOC BB37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] ;# U138.J7 DQL7 +#set_property -dict {LOC AV38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] ;# U138.A3 DQU0 +#set_property -dict {LOC AU38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] ;# U138.B8 DQU1 +#set_property -dict {LOC AU39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] ;# U138.C3 DQU2 +#set_property -dict {LOC AW35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] ;# U138.C7 DQU3 +#set_property -dict {LOC AU40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] ;# U138.C2 DQU4 +#set_property -dict {LOC AV40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] ;# U138.C8 DQU5 +#set_property -dict {LOC AW36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] ;# U138.D3 DQU6 +#set_property -dict {LOC AV39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] ;# U138.D7 DQU7 +#set_property -dict {LOC BA35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] ;# U138.G3 DQSL_T +#set_property -dict {LOC BA36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] ;# U138.F3 DQSL_C +#set_property -dict {LOC AW37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] ;# U138.B7 DQSU_T +#set_property -dict {LOC AW38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] ;# U138.A7 DQSU_C +#set_property -dict {LOC AY37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[6]}] ;# U138.E7 DML_B/DBIL_B +#set_property -dict {LOC AV35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[7]}] ;# U138.E2 DMU_B/DBIU_B + +#set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] ;# U139.G2 DQL0 +#set_property -dict {LOC BD26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] ;# U139.F7 DQL1 +#set_property -dict {LOC BD27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] ;# U139.H3 DQL2 +#set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] ;# U139.H7 DQL3 +#set_property -dict {LOC BD28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] ;# U139.H2 DQL4 +#set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] ;# U139.H8 DQL5 +#set_property -dict {LOC BF26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] ;# U139.J3 DQL6 +#set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] ;# U139.J7 DQL7 +#set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[72]}] ;# U139.A3 DQU0 +#set_property -dict {LOC BC26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[73]}] ;# U139.B8 DQU1 +#set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[74]}] ;# U139.C3 DQU2 +#set_property -dict {LOC BB28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[75]}] ;# U139.C7 DQU3 +#set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[76]}] ;# U139.C2 DQU4 +#set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[77]}] ;# U139.C8 DQU5 +#set_property -dict {LOC BC25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[78]}] ;# U139.D3 DQU6 +#set_property -dict {LOC BC28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[79]}] ;# U139.D7 DQU7 +#set_property -dict {LOC BE25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] ;# U139.G3 DQSL_T +#set_property -dict {LOC BF25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] ;# U139.F3 DQSL_C +#set_property -dict {LOC BA26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] ;# U139.B7 DQSU_T +#set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] ;# U139.A7 DQSU_C +#set_property -dict {LOC BE29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[8]}] ;# U139.E7 DML_B/DBIL_B +#set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[9]}] ;# U139.E2 DMU_B/DBIU_B + # BPI flash #set_property -dict {LOC AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[4]}] #set_property -dict {LOC AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[5]}] diff --git a/fpga/lib/eth/example/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py index 4ec069372..37c69b5ca 100644 --- a/fpga/lib/eth/example/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -58,25 +58,16 @@ class TB: dut.phy_gmii_clk_en.setimmediatevalue(1) - cocotb.start_soon(Clock(dut.qsfp_rx_clk_1, 6.4, units="ns").start()) - self.qsfp_1_source = XgmiiSource(dut.qsfp_rxd_1, dut.qsfp_rxc_1, dut.qsfp_rx_clk_1, dut.qsfp_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp_tx_clk_1, 6.4, units="ns").start()) - self.qsfp_1_sink = XgmiiSink(dut.qsfp_txd_1, dut.qsfp_txc_1, dut.qsfp_tx_clk_1, dut.qsfp_tx_rst_1) + self.qsfp_source = [] + self.qsfp_sink = [] - cocotb.start_soon(Clock(dut.qsfp_rx_clk_2, 6.4, units="ns").start()) - self.qsfp_2_source = XgmiiSource(dut.qsfp_rxd_2, dut.qsfp_rxc_2, dut.qsfp_rx_clk_2, dut.qsfp_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp_tx_clk_2, 6.4, units="ns").start()) - self.qsfp_2_sink = XgmiiSink(dut.qsfp_txd_2, dut.qsfp_txc_2, dut.qsfp_tx_clk_2, dut.qsfp_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp_rx_clk_3, 6.4, units="ns").start()) - self.qsfp_3_source = XgmiiSource(dut.qsfp_rxd_3, dut.qsfp_rxc_3, dut.qsfp_rx_clk_3, dut.qsfp_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp_tx_clk_3, 6.4, units="ns").start()) - self.qsfp_3_sink = XgmiiSink(dut.qsfp_txd_3, dut.qsfp_txc_3, dut.qsfp_tx_clk_3, dut.qsfp_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp_rx_clk_4, 6.4, units="ns").start()) - self.qsfp_4_source = XgmiiSource(dut.qsfp_rxd_4, dut.qsfp_rxc_4, dut.qsfp_rx_clk_4, dut.qsfp_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp_tx_clk_4, 6.4, units="ns").start()) - self.qsfp_4_sink = XgmiiSink(dut.qsfp_txd_4, dut.qsfp_txc_4, dut.qsfp_tx_clk_4, dut.qsfp_tx_rst_4) + for y in range(1, 5): + cocotb.start_soon(Clock(getattr(dut, f"qsfp_rx_clk_{y}"), 2.56, units="ns").start()) + source = XgmiiSource(getattr(dut, f"qsfp_rxd_{y}"), getattr(dut, f"qsfp_rxc_{y}"), getattr(dut, f"qsfp_rx_clk_{y}"), getattr(dut, f"qsfp_rx_rst_{y}")) + self.qsfp_source.append(source) + cocotb.start_soon(Clock(getattr(dut, f"qsfp_tx_clk_{y}"), 2.56, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"qsfp_txd_{y}"), getattr(dut, f"qsfp_txc_{y}"), getattr(dut, f"qsfp_tx_clk_{y}"), getattr(dut, f"qsfp_tx_rst_{y}")) + self.qsfp_sink.append(sink) dut.btnu.setimmediatevalue(0) dut.btnl.setimmediatevalue(0) @@ -91,42 +82,27 @@ class TB: self.dut.rst.setimmediatevalue(0) self.dut.phy_gmii_rst.setimmediatevalue(0) - self.dut.qsfp_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp_tx_rst_4.setimmediatevalue(0) + for y in range(1, 5): + getattr(self.dut, f"qsfp_rx_rst_{y}").setimmediatevalue(0) + getattr(self.dut, f"qsfp_tx_rst_{y}").setimmediatevalue(0) for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 1 self.dut.phy_gmii_rst.value = 1 - self.dut.qsfp_rx_rst_1.value = 1 - self.dut.qsfp_tx_rst_1.value = 1 - self.dut.qsfp_rx_rst_2.value = 1 - self.dut.qsfp_tx_rst_2.value = 1 - self.dut.qsfp_rx_rst_3.value = 1 - self.dut.qsfp_tx_rst_3.value = 1 - self.dut.qsfp_rx_rst_4.value = 1 - self.dut.qsfp_tx_rst_4.value = 1 + for y in range(1, 5): + getattr(self.dut, f"qsfp_rx_rst_{y}").value = 1 + getattr(self.dut, f"qsfp_tx_rst_{y}").value = 1 for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 0 self.dut.phy_gmii_rst.value = 0 - self.dut.qsfp_rx_rst_1.value = 0 - self.dut.qsfp_tx_rst_1.value = 0 - self.dut.qsfp_rx_rst_2.value = 0 - self.dut.qsfp_tx_rst_2.value = 0 - self.dut.qsfp_rx_rst_3.value = 0 - self.dut.qsfp_tx_rst_3.value = 0 - self.dut.qsfp_rx_rst_4.value = 0 - self.dut.qsfp_tx_rst_4.value = 0 + for y in range(1, 5): + getattr(self.dut, f"qsfp_rx_rst_{y}").value = 0 + getattr(self.dut, f"qsfp_tx_rst_{y}").value = 0 @cocotb.test() @@ -146,11 +122,11 @@ async def run_test(dut): test_frame = XgmiiFrame.from_payload(test_pkt.build()) - await tb.qsfp_1_source.send(test_frame) + await tb.qsfp_source[0].send(test_frame) tb.log.info("receive ARP request") - rx_frame = await tb.qsfp_1_sink.recv() + rx_frame = await tb.qsfp_sink[0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -178,11 +154,11 @@ async def run_test(dut): resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - await tb.qsfp_1_source.send(resp_frame) + await tb.qsfp_source[0].send(resp_frame) tb.log.info("receive UDP packet") - rx_frame = await tb.qsfp_1_sink.recv() + rx_frame = await tb.qsfp_sink[0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -215,13 +191,13 @@ async def run_test(dut): tb.log.info("loop back packet on XGMII interface") - rx_frame = await tb.qsfp_1_sink.recv() + rx_frame = await tb.qsfp_sink[0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) tb.log.info("RX packet: %s", repr(rx_pkt)) - await tb.qsfp_1_source.send(rx_frame) + await tb.qsfp_source[0].send(rx_frame) tb.log.info("receive UDP packet") @@ -258,13 +234,13 @@ async def run_test(dut): tb.log.info("loop back packet on XGMII interface") - rx_frame = await tb.qsfp_1_sink.recv() + rx_frame = await tb.qsfp_sink[0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) tb.log.info("RX packet: %s", repr(rx_pkt)) - await tb.qsfp_1_source.send(rx_frame) + await tb.qsfp_source[0].send(rx_frame) tb.log.info("receive UDP packet") diff --git a/fpga/lib/eth/example/VCU108/fpga_1g/common/vivado.mk b/fpga/lib/eth/example/VCU108/fpga_1g/common/vivado.mk index 21e6a5fed..1402e2382 100644 --- a/fpga/lib/eth/example/VCU108/fpga_1g/common/vivado.mk +++ b/fpga/lib/eth/example/VCU108/fpga_1g/common/vivado.mk @@ -28,7 +28,7 @@ ################################################################### # phony targets -.PHONY: clean fpga +.PHONY: fpga vivado tmpclean clean distclean # prevent make from deleting intermediate files and reports .PRECIOUS: %.xpr %.bit %.mcs %.prm @@ -40,15 +40,16 @@ CONFIG ?= config.mk FPGA_TOP ?= fpga PROJECT ?= $(FPGA_TOP) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else - XDC_FILES_REL = $(FPGA_TOP).xdc + XDC_FILES_REL = $(PROJECT).xdc endif ################################################################### @@ -60,20 +61,20 @@ endif all: fpga -fpga: $(FPGA_TOP).bit +fpga: $(PROJECT).bit -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr -tmpclean: +tmpclean:: -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt -distclean: clean +distclean:: clean -rm -rf rev ################################################################### @@ -91,12 +92,17 @@ create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done -$(PROJECT).xpr: create_project.tcl +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) # synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr echo "open_project $(PROJECT).xpr" > run_synth.tcl echo "reset_run synth_1" >> run_synth.tcl echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl diff --git a/fpga/lib/eth/example/VCU108/fpga_1g/fpga.xdc b/fpga/lib/eth/example/VCU108/fpga_1g/fpga.xdc index c5efbb26d..275e1869c 100644 --- a/fpga/lib/eth/example/VCU108/fpga_1g/fpga.xdc +++ b/fpga/lib/eth/example/VCU108/fpga_1g/fpga.xdc @@ -8,6 +8,7 @@ set_property BITSTREAM.GENERAL.COMPRESS true [current_design] set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1 [current_design] set_property CONFIG_MODE BPI16 [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # System clocks # 300 MHz @@ -308,6 +309,618 @@ set_input_delay 0 [get_ports {phy_int_n}] #set_false_path -from [get_ports {pcie_reset_n}] #set_input_delay 0 [get_ports {pcie_reset_n}] +# FMC interface +# FMC HPC0 J22 +#set_property -dict {LOC AY9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[0]"] ;# J22.G9 LA00_P_CC +#set_property -dict {LOC BA9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[0]"] ;# J22.G10 LA00_N_CC +#set_property -dict {LOC BC10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[1]"] ;# J22.D8 LA01_P_CC +#set_property -dict {LOC BD10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[1]"] ;# J22.D9 LA01_N_CC +#set_property -dict {LOC BA7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[2]"] ;# J22.H7 LA02_P +#set_property -dict {LOC BB7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[2]"] ;# J22.H8 LA02_N +#set_property -dict {LOC BD8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[3]"] ;# J22.G12 LA03_P +#set_property -dict {LOC BD7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[3]"] ;# J22.G13 LA03_N +#set_property -dict {LOC BE8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[4]"] ;# J22.H10 LA04_P +#set_property -dict {LOC BE7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[4]"] ;# J22.H11 LA04_N +#set_property -dict {LOC BF12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[5]"] ;# J22.D11 LA05_P +#set_property -dict {LOC BF11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[5]"] ;# J22.D12 LA05_N +#set_property -dict {LOC BE10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[6]"] ;# J22.C10 LA06_P +#set_property -dict {LOC BE9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[6]"] ;# J22.C11 LA06_N +#set_property -dict {LOC BD12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[7]"] ;# J22.H13 LA07_P +#set_property -dict {LOC BE12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[7]"] ;# J22.H14 LA07_N +#set_property -dict {LOC BF10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[8]"] ;# J22.G12 LA08_P +#set_property -dict {LOC BF9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[8]"] ;# J22.G13 LA08_N +#set_property -dict {LOC BD13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[9]"] ;# J22.D14 LA09_P +#set_property -dict {LOC BE13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[9]"] ;# J22.D15 LA09_N +#set_property -dict {LOC BE14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[10]"] ;# J22.C14 LA10_P +#set_property -dict {LOC BF14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[10]"] ;# J22.C15 LA10_N +#set_property -dict {LOC BC11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[11]"] ;# J22.H16 LA11_P +#set_property -dict {LOC BD11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[11]"] ;# J22.H17 LA11_N +#set_property -dict {LOC BE15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[12]"] ;# J22.G15 LA12_P +#set_property -dict {LOC BF15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[12]"] ;# J22.G16 LA12_N +#set_property -dict {LOC BA14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[13]"] ;# J22.D17 LA13_P +#set_property -dict {LOC BB14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[13]"] ;# J22.D18 LA13_N +#set_property -dict {LOC BB13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[14]"] ;# J22.C18 LA14_P +#set_property -dict {LOC BB12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[14]"] ;# J22.C19 LA14_N +#set_property -dict {LOC AV9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[15]"] ;# J22.H19 LA15_P +#set_property -dict {LOC AV8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[15]"] ;# J22.H20 LA15_N +#set_property -dict {LOC AY8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[16]"] ;# J22.G18 LA16_P +#set_property -dict {LOC AY7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[16]"] ;# J22.G19 LA16_N +#set_property -dict {LOC AV14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[17]"] ;# J22.D20 LA17_P_CC +#set_property -dict {LOC AV13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[17]"] ;# J22.D21 LA17_N_CC +#set_property -dict {LOC AP13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[18]"] ;# J22.C22 LA18_P_CC +#set_property -dict {LOC AR13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[18]"] ;# J22.C23 LA18_N_CC +#set_property -dict {LOC AV15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[19]"] ;# J22.H22 LA19_P +#set_property -dict {LOC AW15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[19]"] ;# J22.H23 LA19_N +#set_property -dict {LOC AY15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[20]"] ;# J22.G21 LA20_P +#set_property -dict {LOC AY14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[20]"] ;# J22.G22 LA20_N +#set_property -dict {LOC AN16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[21]"] ;# J22.H25 LA21_P +#set_property -dict {LOC AP16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[21]"] ;# J22.H26 LA21_N +#set_property -dict {LOC AN15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[22]"] ;# J22.G24 LA22_P +#set_property -dict {LOC AP15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[22]"] ;# J22.G25 LA22_N +#set_property -dict {LOC AT16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[23]"] ;# J22.D23 LA23_P +#set_property -dict {LOC AT15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[23]"] ;# J22.D24 LA23_N +#set_property -dict {LOC AK15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[24]"] ;# J22.H28 LA24_P +#set_property -dict {LOC AL15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[24]"] ;# J22.H29 LA24_N +#set_property -dict {LOC AM13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[25]"] ;# J22.G27 LA25_P +#set_property -dict {LOC AM12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[25]"] ;# J22.G28 LA25_N +#set_property -dict {LOC AL14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[26]"] ;# J22.D26 LA26_P +#set_property -dict {LOC AM14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[26]"] ;# J22.D27 LA26_N +#set_property -dict {LOC AN14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[27]"] ;# J22.C26 LA27_P +#set_property -dict {LOC AN13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[27]"] ;# J22.C27 LA27_N +#set_property -dict {LOC AJ13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[28]"] ;# J22.H31 LA28_P +#set_property -dict {LOC AJ12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[28]"] ;# J22.H32 LA28_N +#set_property -dict {LOC AK14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[29]"] ;# J22.G30 LA29_P +#set_property -dict {LOC AK13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[29]"] ;# J22.G31 LA29_N +#set_property -dict {LOC AK12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[30]"] ;# J22.H34 LA30_P +#set_property -dict {LOC AL12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[30]"] ;# J22.H35 LA30_N +#set_property -dict {LOC AP12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[31]"] ;# J22.G33 LA31_P +#set_property -dict {LOC AR12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[31]"] ;# J22.G34 LA31_N +#set_property -dict {LOC AU11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[32]"] ;# J22.H37 LA32_P +#set_property -dict {LOC AV11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[32]"] ;# J22.H38 LA32_N +#set_property -dict {LOC AU16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[33]"] ;# J22.G36 LA33_P +#set_property -dict {LOC AV16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[33]"] ;# J22.G37 LA33_N + +#set_property -dict {LOC N14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[0]"] ;# J22.F4 HA00_P_CC +#set_property -dict {LOC N13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[0]"] ;# J22.F5 HA00_N_CC +#set_property -dict {LOC T14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[1]"] ;# J22.E2 HA01_P_CC +#set_property -dict {LOC R13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[1]"] ;# J22.E3 HA01_N_CC +#set_property -dict {LOC T16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[2]"] ;# J22.K7 HA02_P +#set_property -dict {LOC T15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[2]"] ;# J22.K8 HA02_N +#set_property -dict {LOC K11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[3]"] ;# J22.J6 HA03_P +#set_property -dict {LOC J11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[3]"] ;# J22.J7 HA03_N +#set_property -dict {LOC AA13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[4]"] ;# J22.F7 HA04_P +#set_property -dict {LOC Y13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[4]"] ;# J22.F8 HA04_N +#set_property -dict {LOC AA12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[5]"] ;# J22.E6 HA05_P +#set_property -dict {LOC Y12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[5]"] ;# J22.E7 HA05_N +#set_property -dict {LOC P15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[6]"] ;# J22.K10 HA06_P +#set_property -dict {LOC N15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[6]"] ;# J22.K11 HA06_N +#set_property -dict {LOC R12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[7]"] ;# J22.J9 HA07_P +#set_property -dict {LOC P12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[7]"] ;# J22.J10 HA07_N +#set_property -dict {LOC W12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[8]"] ;# J22.F10 HA08_P +#set_property -dict {LOC V12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[8]"] ;# J22.F11 HA08_N +#set_property -dict {LOC AA14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[9]"] ;# J22.E9 HA09_P +#set_property -dict {LOC Y14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[9]"] ;# J22.E10 HA09_N +#set_property -dict {LOC K12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[10]"] ;# J22.K13 HA10_P +#set_property -dict {LOC J12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[10]"] ;# J22.K14 HA10_N +#set_property -dict {LOC M11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[11]"] ;# J22.J12 HA11_P +#set_property -dict {LOC L11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[11]"] ;# J22.J13 HA11_N +#set_property -dict {LOC V15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[12]"] ;# J22.F13 HA12_P +#set_property -dict {LOC U15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[12]"] ;# J22.F14 HA12_N +#set_property -dict {LOC W14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[13]"] ;# J22.E12 HA13_P +#set_property -dict {LOC V14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[13]"] ;# J22.E13 HA13_N +#set_property -dict {LOC K14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[14]"] ;# J22.J15 HA14_P +#set_property -dict {LOC K13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[14]"] ;# J22.J16 HA14_N +#set_property -dict {LOC V13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[15]"] ;# J22.F14 HA15_P +#set_property -dict {LOC U12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[15]"] ;# J22.F16 HA15_N +#set_property -dict {LOC V16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[16]"] ;# J22.E15 HA16_P +#set_property -dict {LOC U16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[16]"] ;# J22.E16 HA16_N +#set_property -dict {LOC U13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[17]"] ;# J22.K16 HA17_P_CC +#set_property -dict {LOC T13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[17]"] ;# J22.K17 HA17_N_CC +#set_property -dict {LOC L14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[18]"] ;# J22.J18 HA18_P_CC +#set_property -dict {LOC L13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[18]"] ;# J22.J19 HA18_N_CC +#set_property -dict {LOC R14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[19]"] ;# J22.F19 HA19_P +#set_property -dict {LOC P14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[19]"] ;# J22.F20 HA19_N +#set_property -dict {LOC R11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[20]"] ;# J22.E18 HA20_P +#set_property -dict {LOC P11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[20]"] ;# J22.E19 HA20_N +#set_property -dict {LOC M13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[21]"] ;# J22.K19 HA21_P +#set_property -dict {LOC M12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[21]"] ;# J22.K20 HA21_N +#set_property -dict {LOC M15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[22]"] ;# J22.J21 HA22_P +#set_property -dict {LOC L15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[22]"] ;# J22.J22 HA22_N +#set_property -dict {LOC U11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[23]"] ;# J22.K22 HA23_P +#set_property -dict {LOC T11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[23]"] ;# J22.K23 HA23_N + +#set_property -dict {LOC BB9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_clk0_m2c_p"] ;# J22.H4 CLK0_M2C_P +#set_property -dict {LOC BB8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_clk0_m2c_n"] ;# J22.H5 CLK0_M2C_N +#set_property -dict {LOC AU14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_clk1_m2c_p"] ;# J22.G2 CLK1_M2C_P +#set_property -dict {LOC AU13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_clk1_m2c_n"] ;# J22.G3 CLK1_M2C_N + +#set_property -dict {LOC AP22 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc0_pg_m2c}] ;# J22.F1 PG_M2C +#set_property -dict {LOC AL19 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc0_prsnt_m2c_l}] ;# J22.H2 PRSNT_M2C_L + +#set_property -dict {LOC G5 } [get_ports {fmc_hpc0_dp_c2m_p[0]}] ;# MGTHTXP0_230 GTHE3_CHANNEL_X0Y24 / GTHE3_COMMON_X0Y6 from J22.C2 DP0_C2M_P +#set_property -dict {LOC G4 } [get_ports {fmc_hpc0_dp_c2m_n[0]}] ;# MGTHTXN0_230 GTHE3_CHANNEL_X0Y24 / GTHE3_COMMON_X0Y6 from J22.C3 DP0_C2M_N +#set_property -dict {LOC K2 } [get_ports {fmc_hpc0_dp_m2c_p[0]}] ;# MGTHRXP0_230 GTHE3_CHANNEL_X0Y24 / GTHE3_COMMON_X0Y6 from J22.C6 DP0_M2C_P +#set_property -dict {LOC K1 } [get_ports {fmc_hpc0_dp_m2c_n[0]}] ;# MGTHRXN0_230 GTHE3_CHANNEL_X0Y24 / GTHE3_COMMON_X0Y6 from J22.C7 DP0_M2C_N +#set_property -dict {LOC F7 } [get_ports {fmc_hpc0_dp_c2m_p[1]}] ;# MGTHTXP1_230 GTHE3_CHANNEL_X0Y25 / GTHE3_COMMON_X0Y6 from J22.A22 DP1_C2M_P +#set_property -dict {LOC F6 } [get_ports {fmc_hpc0_dp_c2m_n[1]}] ;# MGTHTXN1_230 GTHE3_CHANNEL_X0Y25 / GTHE3_COMMON_X0Y6 from J22.A23 DP1_C2M_N +#set_property -dict {LOC H2 } [get_ports {fmc_hpc0_dp_m2c_p[1]}] ;# MGTHRXP1_230 GTHE3_CHANNEL_X0Y25 / GTHE3_COMMON_X0Y6 from J22.A2 DP1_M2C_P +#set_property -dict {LOC H1 } [get_ports {fmc_hpc0_dp_m2c_n[1]}] ;# MGTHRXN1_230 GTHE3_CHANNEL_X0Y25 / GTHE3_COMMON_X0Y6 from J22.A3 DP1_M2C_N +#set_property -dict {LOC E5 } [get_ports {fmc_hpc0_dp_c2m_p[2]}] ;# MGTHTXP2_230 GTHE3_CHANNEL_X0Y26 / GTHE3_COMMON_X0Y6 from J22.A26 DP2_C2M_P +#set_property -dict {LOC E4 } [get_ports {fmc_hpc0_dp_c2m_n[2]}] ;# MGTHTXN2_230 GTHE3_CHANNEL_X0Y26 / GTHE3_COMMON_X0Y6 from J22.A27 DP2_C2M_N +#set_property -dict {LOC F2 } [get_ports {fmc_hpc0_dp_m2c_p[2]}] ;# MGTHRXP2_230 GTHE3_CHANNEL_X0Y26 / GTHE3_COMMON_X0Y6 from J22.A6 DP2_M2C_P +#set_property -dict {LOC F1 } [get_ports {fmc_hpc0_dp_m2c_n[2]}] ;# MGTHRXN2_230 GTHE3_CHANNEL_X0Y26 / GTHE3_COMMON_X0Y6 from J22.A7 DP2_M2C_N +#set_property -dict {LOC C5 } [get_ports {fmc_hpc0_dp_c2m_p[3]}] ;# MGTHTXP3_230 GTHE3_CHANNEL_X0Y27 / GTHE3_COMMON_X0Y6 from J22.A30 DP3_C2M_P +#set_property -dict {LOC C4 } [get_ports {fmc_hpc0_dp_c2m_n[3]}] ;# MGTHTXN3_230 GTHE3_CHANNEL_X0Y27 / GTHE3_COMMON_X0Y6 from J22.A31 DP3_C2M_N +#set_property -dict {LOC D2 } [get_ports {fmc_hpc0_dp_m2c_p[3]}] ;# MGTHRXP3_230 GTHE3_CHANNEL_X0Y27 / GTHE3_COMMON_X0Y6 from J22.A10 DP3_M2C_P +#set_property -dict {LOC D1 } [get_ports {fmc_hpc0_dp_m2c_n[3]}] ;# MGTHRXN3_230 GTHE3_CHANNEL_X0Y27 / GTHE3_COMMON_X0Y6 from J22.A11 DP3_M2C_N + +#set_property -dict {LOC L5 } [get_ports {fmc_hpc0_dp_c2m_p[4]}] ;# MGTHTXP0_229 GTHE3_CHANNEL_X0Y20 / GTHE3_COMMON_X0Y5 from J22.A34 DP4_C2M_P +#set_property -dict {LOC L4 } [get_ports {fmc_hpc0_dp_c2m_n[4]}] ;# MGTHTXN0_229 GTHE3_CHANNEL_X0Y20 / GTHE3_COMMON_X0Y5 from J22.A35 DP4_C2M_N +#set_property -dict {LOC T2 } [get_ports {fmc_hpc0_dp_m2c_p[4]}] ;# MGTHRXP0_229 GTHE3_CHANNEL_X0Y20 / GTHE3_COMMON_X0Y5 from J22.A14 DP4_M2C_P +#set_property -dict {LOC T1 } [get_ports {fmc_hpc0_dp_m2c_n[4]}] ;# MGTHRXN0_229 GTHE3_CHANNEL_X0Y20 / GTHE3_COMMON_X0Y5 from J22.A15 DP4_M2C_N +#set_property -dict {LOC K7 } [get_ports {fmc_hpc0_dp_c2m_p[5]}] ;# MGTHTXP1_229 GTHE3_CHANNEL_X0Y21 / GTHE3_COMMON_X0Y5 from J22.A38 DP5_C2M_P +#set_property -dict {LOC K6 } [get_ports {fmc_hpc0_dp_c2m_n[5]}] ;# MGTHTXN1_229 GTHE3_CHANNEL_X0Y21 / GTHE3_COMMON_X0Y5 from J22.A39 DP5_C2M_N +#set_property -dict {LOC R4 } [get_ports {fmc_hpc0_dp_m2c_p[5]}] ;# MGTHRXP1_229 GTHE3_CHANNEL_X0Y21 / GTHE3_COMMON_X0Y5 from J22.A18 DP5_M2C_P +#set_property -dict {LOC R3 } [get_ports {fmc_hpc0_dp_m2c_n[5]}] ;# MGTHRXN1_229 GTHE3_CHANNEL_X0Y21 / GTHE3_COMMON_X0Y5 from J22.A19 DP5_M2C_N +#set_property -dict {LOC J5 } [get_ports {fmc_hpc0_dp_c2m_p[6]}] ;# MGTHTXP2_229 GTHE3_CHANNEL_X0Y22 / GTHE3_COMMON_X0Y5 from J22.B36 DP6_C2M_P +#set_property -dict {LOC J4 } [get_ports {fmc_hpc0_dp_c2m_n[6]}] ;# MGTHTXN2_229 GTHE3_CHANNEL_X0Y22 / GTHE3_COMMON_X0Y5 from J22.B37 DP6_C2M_N +#set_property -dict {LOC P2 } [get_ports {fmc_hpc0_dp_m2c_p[6]}] ;# MGTHRXP2_229 GTHE3_CHANNEL_X0Y22 / GTHE3_COMMON_X0Y5 from J22.B16 DP6_M2C_P +#set_property -dict {LOC P1 } [get_ports {fmc_hpc0_dp_m2c_n[6]}] ;# MGTHRXN2_229 GTHE3_CHANNEL_X0Y22 / GTHE3_COMMON_X0Y5 from J22.B17 DP6_M2C_N +#set_property -dict {LOC H7 } [get_ports {fmc_hpc0_dp_c2m_p[7]}] ;# MGTHTXP3_229 GTHE3_CHANNEL_X0Y23 / GTHE3_COMMON_X0Y5 from J22.B32 DP7_C2M_P +#set_property -dict {LOC H6 } [get_ports {fmc_hpc0_dp_c2m_n[7]}] ;# MGTHTXN3_229 GTHE3_CHANNEL_X0Y23 / GTHE3_COMMON_X0Y5 from J22.B33 DP7_C2M_N +#set_property -dict {LOC M2 } [get_ports {fmc_hpc0_dp_m2c_p[7]}] ;# MGTHRXP3_229 GTHE3_CHANNEL_X0Y23 / GTHE3_COMMON_X0Y5 from J22.B12 DP7_M2C_P +#set_property -dict {LOC M1 } [get_ports {fmc_hpc0_dp_m2c_n[7]}] ;# MGTHRXN3_229 GTHE3_CHANNEL_X0Y23 / GTHE3_COMMON_X0Y5 from J22.B13 DP7_M2C_N +#set_property -dict {LOC R9 } [get_ports fmc_hpc0_mgt_refclk_0_p] ;# MGTREFCLK0P_229 from J22.D4 GBTCLK0_M2C_P +#set_property -dict {LOC R8 } [get_ports fmc_hpc0_mgt_refclk_0_n] ;# MGTREFCLK0N_229 from J22.D5 GBTCLK0_M2C_N +#set_property -dict {LOC N9 } [get_ports fmc_hpc0_mgt_refclk_1_p] ;# MGTREFCLK1P_229 from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC N8 } [get_ports fmc_hpc0_mgt_refclk_1_n] ;# MGTREFCLK1N_229 from J22.B21 GBTCLK1_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmc_hpc0_mgt_refclk_0 [get_ports fmc_hpc0_mgt_refclk_0_p] +#create_clock -period 6.400 -name fmc_hpc0_mgt_refclk_1 [get_ports fmc_hpc0_mgt_refclk_1_p] + +#set_property -dict {LOC V7 } [get_ports {fmc_hpc0_dp_c2m_p[8]}] ;# MGTHTXP0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.B28 DP8_C2M_P +#set_property -dict {LOC V6 } [get_ports {fmc_hpc0_dp_c2m_n[8]}] ;# MGTHTXN0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.B29 DP8_C2M_N +#set_property -dict {LOC Y2 } [get_ports {fmc_hpc0_dp_m2c_p[8]}] ;# MGTHRXP0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.B8 DP8_M2C_P +#set_property -dict {LOC Y1 } [get_ports {fmc_hpc0_dp_m2c_n[8]}] ;# MGTHRXN0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.B9 DP8_M2C_N +#set_property -dict {LOC T7 } [get_ports {fmc_hpc0_dp_c2m_p[9]}] ;# MGTHTXP1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.B24 DP9_C2M_P +#set_property -dict {LOC T6 } [get_ports {fmc_hpc0_dp_c2m_n[9]}] ;# MGTHTXN1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.B25 DP9_C2M_N +#set_property -dict {LOC W4 } [get_ports {fmc_hpc0_dp_m2c_p[9]}] ;# MGTHRXP1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.B4 DP9_M2C_P +#set_property -dict {LOC W3 } [get_ports {fmc_hpc0_dp_m2c_n[9]}] ;# MGTHRXN1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.B5 DP9_M2C_N +#set_property -dict {LOC W9 } [get_ports fmc_hpc0_mgt_refclk_2_p] ;# MGTREFCLK0P_228 from from J87 P1 +#set_property -dict {LOC W8 } [get_ports fmc_hpc0_mgt_refclk_2_n] ;# MGTREFCLK0N_228 from from J87 P2 + +# reference clock +#create_clock -period 6.400 -name fmc_hpc0_mgt_refclk_2 [get_ports fmc_hpc0_mgt_refclk_2_p] + +# FMC HPC1 J2 +#set_property -dict {LOC T33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[0]"] ;# J2.G9 LA00_P_CC +#set_property -dict {LOC R33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[0]"] ;# J2.G10 LA00_N_CC +#set_property -dict {LOC P35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[1]"] ;# J2.D8 LA01_P_CC +#set_property -dict {LOC P36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[1]"] ;# J2.D9 LA01_N_CC +#set_property -dict {LOC N33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[2]"] ;# J2.H7 LA02_P +#set_property -dict {LOC M33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[2]"] ;# J2.H8 LA02_N +#set_property -dict {LOC N34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[3]"] ;# J2.G12 LA03_P +#set_property -dict {LOC N35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[3]"] ;# J2.G13 LA03_N +#set_property -dict {LOC M37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[4]"] ;# J2.H10 LA04_P +#set_property -dict {LOC L38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[4]"] ;# J2.H11 LA04_N +#set_property -dict {LOC N38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[5]"] ;# J2.D11 LA05_P +#set_property -dict {LOC M38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[5]"] ;# J2.D12 LA05_N +#set_property -dict {LOC P37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[6]"] ;# J2.C10 LA06_P +#set_property -dict {LOC N37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[6]"] ;# J2.C11 LA06_N +#set_property -dict {LOC L34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[7]"] ;# J2.H13 LA07_P +#set_property -dict {LOC K34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[7]"] ;# J2.H14 LA07_N +#set_property -dict {LOC M35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[8]"] ;# J2.G12 LA08_P +#set_property -dict {LOC L35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[8]"] ;# J2.G13 LA08_N +#set_property -dict {LOC M36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[9]"] ;# J2.D14 LA09_P +#set_property -dict {LOC L36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[9]"] ;# J2.D15 LA09_N +#set_property -dict {LOC N32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[10]"] ;# J2.C14 LA10_P +#set_property -dict {LOC M32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[10]"] ;# J2.C15 LA10_N +#set_property -dict {LOC Y31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[11]"] ;# J2.H16 LA11_P +#set_property -dict {LOC W31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[11]"] ;# J2.H17 LA11_N +#set_property -dict {LOC R31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[12]"] ;# J2.G15 LA12_P +#set_property -dict {LOC P31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[12]"] ;# J2.G16 LA12_N +#set_property -dict {LOC T30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[13]"] ;# J2.D17 LA13_P +#set_property -dict {LOC T31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[13]"] ;# J2.D18 LA13_N +#set_property -dict {LOC L33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[14]"] ;# J2.C18 LA14_P +#set_property -dict {LOC K33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[14]"] ;# J2.C19 LA14_N +#set_property -dict {LOC T34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[15]"] ;# J2.H19 LA15_P +#set_property -dict {LOC T35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[15]"] ;# J2.H20 LA15_N +#set_property -dict {LOC U31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[16]"] ;# J2.G18 LA16_P +#set_property -dict {LOC U32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[16]"] ;# J2.G19 LA16_N +#set_property -dict {LOC AJ32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[17]"] ;# J2.D20 LA17_P_CC +#set_property -dict {LOC AK32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[17]"] ;# J2.D21 LA17_N_CC +#set_property -dict {LOC AL32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[18]"] ;# J2.C22 LA18_P_CC +#set_property -dict {LOC AM32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[18]"] ;# J2.C23 LA18_N_CC +#set_property -dict {LOC AT39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[19]"] ;# J2.H22 LA19_P +#set_property -dict {LOC AT40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[19]"] ;# J2.H23 LA19_N +#set_property -dict {LOC AR37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[20]"] ;# J2.G21 LA20_P +#set_property -dict {LOC AT37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[20]"] ;# J2.G22 LA20_N +#set_property -dict {LOC AT35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[21]"] ;# J2.H25 LA21_P +#set_property -dict {LOC AT36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[21]"] ;# J2.H26 LA21_N +#set_property -dict {LOC AL30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[22]"] ;# J2.G24 LA22_P +#set_property -dict {LOC AL31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[22]"] ;# J2.G25 LA22_N +#set_property -dict {LOC AN33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[23]"] ;# J2.D23 LA23_P +#set_property -dict {LOC AP33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[23]"] ;# J2.D24 LA23_N +#set_property -dict {LOC AM36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[24]"] ;# J2.H28 LA24_P +#set_property -dict {LOC AN36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[24]"] ;# J2.H29 LA24_N +#set_property -dict {LOC AP36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[25]"] ;# J2.G27 LA25_P +#set_property -dict {LOC AP37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[25]"] ;# J2.G28 LA25_N +#set_property -dict {LOC AL29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[26]"] ;# J2.D26 LA26_P +#set_property -dict {LOC AM29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[26]"] ;# J2.D27 LA26_N +#set_property -dict {LOC AP35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[27]"] ;# J2.C26 LA27_P +#set_property -dict {LOC AR35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[27]"] ;# J2.C27 LA27_N +#set_property -dict {LOC AL35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[28]"] ;# J2.H31 LA28_P +#set_property -dict {LOC AL36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[28]"] ;# J2.H32 LA28_N +#set_property -dict {LOC AP38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[29]"] ;# J2.G30 LA29_P +#set_property -dict {LOC AR38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[29]"] ;# J2.G31 LA29_N +#set_property -dict {LOC AJ30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[30]"] ;# J2.H34 LA30_P +#set_property -dict {LOC AJ31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[30]"] ;# J2.H35 LA30_N +#set_property -dict {LOC AN34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[31]"] ;# J2.G33 LA31_P +#set_property -dict {LOC AN35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[31]"] ;# J2.G34 LA31_N +#set_property -dict {LOC AG31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[32]"] ;# J2.H37 LA32_P +#set_property -dict {LOC AH31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[32]"] ;# J2.H38 LA32_N +#set_property -dict {LOC AG32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[33]"] ;# J2.G36 LA33_P +#set_property -dict {LOC AG33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[33]"] ;# J2.G37 LA33_N + +#set_property -dict {LOC R32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_clk0_m2c_p"] ;# J2.H4 CLK0_M2C_P +#set_property -dict {LOC P32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_clk0_m2c_n"] ;# J2.H5 CLK0_M2C_N +#set_property -dict {LOC AK34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_clk1_m2c_p"] ;# J2.G2 CLK1_M2C_P +#set_property -dict {LOC AL34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_clk1_m2c_n"] ;# J2.G3 CLK1_M2C_N + +#set_property -dict {LOC AU24 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc1_pg_m2c}] ;# J2.F1 PG_M2C +#set_property -dict {LOC BD23 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc1_prsnt_m2c_l}] ;# J2.H2 PRSNT_M2C_L + +#set_property -dict {LOC AN5 } [get_ports {fmc_hpc1_dp_c2m_p[0]}] ;# MGTHTXP0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C2 DP0_C2M_P +#set_property -dict {LOC AN4 } [get_ports {fmc_hpc1_dp_c2m_n[0]}] ;# MGTHTXN0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C3 DP0_C2M_N +#set_property -dict {LOC AH2 } [get_ports {fmc_hpc1_dp_m2c_p[0]}] ;# MGTHRXP0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C6 DP0_M2C_P +#set_property -dict {LOC AH1 } [get_ports {fmc_hpc1_dp_m2c_n[0]}] ;# MGTHRXN0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C7 DP0_M2C_N +#set_property -dict {LOC AM7 } [get_ports {fmc_hpc1_dp_c2m_p[1]}] ;# MGTHTXP1_226 GTHE3_CHANNEL_X0Y9 / GTHE3_COMMON_X0Y2 from J2.A22 DP1_C2M_P +#set_property -dict {LOC AM6 } [get_ports {fmc_hpc1_dp_c2m_n[1]}] ;# MGTHTXN1_226 GTHE3_CHANNEL_X0Y9 / GTHE3_COMMON_X0Y2 from J2.A23 DP1_C2M_N +#set_property -dict {LOC AG4 } [get_ports {fmc_hpc1_dp_m2c_p[1]}] ;# MGTHRXP1_226 GTHE3_CHANNEL_X0Y9 / GTHE3_COMMON_X0Y2 from J2.A2 DP1_M2C_P +#set_property -dict {LOC AG3 } [get_ports {fmc_hpc1_dp_m2c_n[1]}] ;# MGTHRXN1_226 GTHE3_CHANNEL_X0Y9 / GTHE3_COMMON_X0Y2 from J2.A3 DP1_M2C_N +#set_property -dict {LOC AK7 } [get_ports {fmc_hpc1_dp_c2m_p[2]}] ;# MGTHTXP2_226 GTHE3_CHANNEL_X0Y10 / GTHE3_COMMON_X0Y2 from J2.A26 DP2_C2M_P +#set_property -dict {LOC AK6 } [get_ports {fmc_hpc1_dp_c2m_n[2]}] ;# MGTHTXN2_226 GTHE3_CHANNEL_X0Y10 / GTHE3_COMMON_X0Y2 from J2.A27 DP2_C2M_N +#set_property -dict {LOC AF2 } [get_ports {fmc_hpc1_dp_m2c_p[2]}] ;# MGTHRXP2_226 GTHE3_CHANNEL_X0Y10 / GTHE3_COMMON_X0Y2 from J2.A6 DP2_M2C_P +#set_property -dict {LOC AF1 } [get_ports {fmc_hpc1_dp_m2c_n[2]}] ;# MGTHRXN2_226 GTHE3_CHANNEL_X0Y10 / GTHE3_COMMON_X0Y2 from J2.A7 DP2_M2C_N +#set_property -dict {LOC AH7 } [get_ports {fmc_hpc1_dp_c2m_p[3]}] ;# MGTHTXP3_226 GTHE3_CHANNEL_X0Y11 / GTHE3_COMMON_X0Y2 from J2.A30 DP3_C2M_P +#set_property -dict {LOC AH6 } [get_ports {fmc_hpc1_dp_c2m_n[3]}] ;# MGTHTXN3_226 GTHE3_CHANNEL_X0Y11 / GTHE3_COMMON_X0Y2 from J2.A31 DP3_C2M_N +#set_property -dict {LOC AE4 } [get_ports {fmc_hpc1_dp_m2c_p[3]}] ;# MGTHRXP3_226 GTHE3_CHANNEL_X0Y11 / GTHE3_COMMON_X0Y2 from J2.A10 DP3_M2C_P +#set_property -dict {LOC AE3 } [get_ports {fmc_hpc1_dp_m2c_n[3]}] ;# MGTHRXN3_226 GTHE3_CHANNEL_X0Y11 / GTHE3_COMMON_X0Y2 from J2.A11 DP3_M2C_N + +#set_property -dict {LOC AF7 } [get_ports {fmc_hpc1_dp_c2m_p[4]}] ;# MGTHTXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J2.A34 DP4_C2M_P +#set_property -dict {LOC AF6 } [get_ports {fmc_hpc1_dp_c2m_n[4]}] ;# MGTHTXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J2.A35 DP4_C2M_N +#set_property -dict {LOC AD2 } [get_ports {fmc_hpc1_dp_m2c_p[4]}] ;# MGTHRXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J2.A14 DP4_M2C_P +#set_property -dict {LOC AD1 } [get_ports {fmc_hpc1_dp_m2c_n[4]}] ;# MGTHRXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J2.A15 DP4_M2C_N +#set_property -dict {LOC AD7 } [get_ports {fmc_hpc1_dp_c2m_p[5]}] ;# MGTHTXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J2.A38 DP5_C2M_P +#set_property -dict {LOC AD6 } [get_ports {fmc_hpc1_dp_c2m_n[5]}] ;# MGTHTXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J2.A39 DP5_C2M_N +#set_property -dict {LOC AC4 } [get_ports {fmc_hpc1_dp_m2c_p[5]}] ;# MGTHRXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J2.A18 DP5_M2C_P +#set_property -dict {LOC AC3 } [get_ports {fmc_hpc1_dp_m2c_n[5]}] ;# MGTHRXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J2.A19 DP5_M2C_N +#set_property -dict {LOC AB7 } [get_ports {fmc_hpc1_dp_c2m_p[6]}] ;# MGTHTXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J2.B36 DP6_C2M_P +#set_property -dict {LOC AB6 } [get_ports {fmc_hpc1_dp_c2m_n[6]}] ;# MGTHTXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J2.B37 DP6_C2M_N +#set_property -dict {LOC AB2 } [get_ports {fmc_hpc1_dp_m2c_p[6]}] ;# MGTHRXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J2.B16 DP6_M2C_P +#set_property -dict {LOC AB1 } [get_ports {fmc_hpc1_dp_m2c_n[6]}] ;# MGTHRXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J2.B17 DP6_M2C_N +#set_property -dict {LOC Y7 } [get_ports {fmc_hpc1_dp_c2m_p[7]}] ;# MGTHTXP3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J2.B32 DP7_C2M_P +#set_property -dict {LOC Y6 } [get_ports {fmc_hpc1_dp_c2m_n[7]}] ;# MGTHTXN3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J2.B33 DP7_C2M_N +#set_property -dict {LOC AA4 } [get_ports {fmc_hpc1_dp_m2c_p[7]}] ;# MGTHRXP3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J2.B12 DP7_M2C_P +#set_property -dict {LOC AA3 } [get_ports {fmc_hpc1_dp_m2c_n[7]}] ;# MGTHRXN3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J2.B13 DP7_M2C_N +#set_property -dict {LOC AC9 } [get_ports fmc_hpc1_mgt_refclk_0_p] ;# MGTREFCLK0P_227 from J2.D4 GBTCLK0_M2C_P +#set_property -dict {LOC AC8 } [get_ports fmc_hpc1_mgt_refclk_0_n] ;# MGTREFCLK0N_227 from J2.D5 GBTCLK0_M2C_N +#set_property -dict {LOC AA9 } [get_ports fmc_hpc1_mgt_refclk_1_p] ;# MGTREFCLK1P_227 from J2.B20 GBTCLK1_M2C_P +#set_property -dict {LOC AA8 } [get_ports fmc_hpc1_mgt_refclk_1_n] ;# MGTREFCLK1N_227 from J2.B21 GBTCLK1_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmc_hpc0_mgt_refclk_0 [get_ports fmc_hpc0_mgt_refclk_0_p] +#create_clock -period 6.400 -name fmc_hpc0_mgt_refclk_1 [get_ports fmc_hpc0_mgt_refclk_1_p] + +#set_property -dict {LOC P7 } [get_ports {fmc_hpc1_dp_c2m_p[8]}] ;# MGTHTXP2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B28 DP8_C2M_P +#set_property -dict {LOC P6 } [get_ports {fmc_hpc1_dp_c2m_n[8]}] ;# MGTHTXN2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B29 DP8_C2M_N +#set_property -dict {LOC V2 } [get_ports {fmc_hpc1_dp_m2c_p[8]}] ;# MGTHRXP2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B8 DP8_M2C_P +#set_property -dict {LOC V1 } [get_ports {fmc_hpc1_dp_m2c_n[8]}] ;# MGTHRXN2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B9 DP8_M2C_N +#set_property -dict {LOC M7 } [get_ports {fmc_hpc1_dp_c2m_p[9]}] ;# MGTHTXP3_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B24 DP9_C2M_P +#set_property -dict {LOC M6 } [get_ports {fmc_hpc1_dp_c2m_n[9]}] ;# MGTHTXN3_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B25 DP9_C2M_N +#set_property -dict {LOC U4 } [get_ports {fmc_hpc1_dp_m2c_p[9]}] ;# MGTHRXP3_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B4 DP9_M2C_P +#set_property -dict {LOC U3 } [get_ports {fmc_hpc1_dp_m2c_n[9]}] ;# MGTHRXN3_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B5 DP9_M2C_N +#set_property -dict {LOC W9 } [get_ports fmc_hpc1_mgt_refclk_2_p] ;# MGTREFCLK0P_228 from from J87 P1 +#set_property -dict {LOC W8 } [get_ports fmc_hpc1_mgt_refclk_2_n] ;# MGTREFCLK0N_228 from from J87 P2 + +# reference clock +#create_clock -period 6.400 -name fmc_hpc1_mgt_refclk_2 [get_ports fmc_hpc1_mgt_refclk_2_p] + +# DDR4 C1 +# 5x MT40A256M16GE-075E +#set_property -dict {LOC C30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +#set_property -dict {LOC D32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +#set_property -dict {LOC B30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +#set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +#set_property -dict {LOC E32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +#set_property -dict {LOC A29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +#set_property -dict {LOC C29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +#set_property -dict {LOC E29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +#set_property -dict {LOC A30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +#set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +#set_property -dict {LOC A31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +#set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +#set_property -dict {LOC F29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +#set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +#set_property -dict {LOC D29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +#set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +#set_property -dict {LOC B33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +#set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +#set_property -dict {LOC F30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +#set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +#set_property -dict {LOC E31 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}] +#set_property -dict {LOC D31 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}] +#set_property -dict {LOC K29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}] +#set_property -dict {LOC D30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}] +#set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}] +#set_property -dict {LOC R29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +#set_property -dict {LOC M28 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] +#set_property -dict {LOC J40 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}] + +#set_property -dict {LOC J37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] ;# U60.G2 DQL0 +#set_property -dict {LOC H40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] ;# U60.F7 DQL1 +#set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] ;# U60.H3 DQL2 +#set_property -dict {LOC H39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] ;# U60.H7 DQL3 +#set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] ;# U60.H2 DQL4 +#set_property -dict {LOC G40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] ;# U60.H8 DQL5 +#set_property -dict {LOC F39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] ;# U60.J3 DQL6 +#set_property -dict {LOC F40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] ;# U60.J7 DQL7 +#set_property -dict {LOC F36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] ;# U60.A3 DQU0 +#set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] ;# U60.B8 DQU1 +#set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] ;# U60.C3 DQU2 +#set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] ;# U60.C7 DQU3 +#set_property -dict {LOC G37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] ;# U60.C2 DQU4 +#set_property -dict {LOC H35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] ;# U60.C8 DQU5 +#set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] ;# U60.D3 DQU6 +#set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] ;# U60.D7 DQU7 +#set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] ;# U60.G3 DQSL_T +#set_property -dict {LOC G38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] ;# U60.F3 DQSL_C +#set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] ;# U60.B7 DQSU_T +#set_property -dict {LOC G35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] ;# U60.A7 DQSU_C +#set_property -dict {LOC J39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] ;# U60.E7 DML_B/DBIL_B +#set_property -dict {LOC F34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] ;# U60.E2 DMU_B/DBIU_B + +#set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] ;# U61.G2 DQL0 +#set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] ;# U61.F7 DQL1 +#set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] ;# U61.H3 DQL2 +#set_property -dict {LOC D40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] ;# U61.H7 DQL3 +#set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] ;# U61.H2 DQL4 +#set_property -dict {LOC B38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] ;# U61.H8 DQL5 +#set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] ;# U61.J3 DQL6 +#set_property -dict {LOC C40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] ;# U61.J7 DQL7 +#set_property -dict {LOC C34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] ;# U61.A3 DQU0 +#set_property -dict {LOC A34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] ;# U61.B8 DQU1 +#set_property -dict {LOC D34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] ;# U61.C3 DQU2 +#set_property -dict {LOC A35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] ;# U61.C7 DQU3 +#set_property -dict {LOC A36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] ;# U61.C2 DQU4 +#set_property -dict {LOC C35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] ;# U61.C8 DQU5 +#set_property -dict {LOC B35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] ;# U61.D3 DQU6 +#set_property -dict {LOC D35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] ;# U61.D7 DQU7 +#set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] ;# U61.G3 DQSL_T +#set_property -dict {LOC A40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] ;# U61.F3 DQSL_C +#set_property -dict {LOC B36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] ;# U61.B7 DQSU_T +#set_property -dict {LOC B37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] ;# U61.A7 DQSU_C +#set_property -dict {LOC E39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] ;# U61.E7 DML_B/DBIL_B +#set_property -dict {LOC D37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] ;# U61.E2 DMU_B/DBIU_B + +#set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] ;# U62.G2 DQL0 +#set_property -dict {LOC R27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] ;# U62.F7 DQL1 +#set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] ;# U62.H3 DQL2 +#set_property -dict {LOC R24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] ;# U62.H7 DQL3 +#set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] ;# U62.H2 DQL4 +#set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] ;# U62.H8 DQL5 +#set_property -dict {LOC P27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] ;# U62.J3 DQL6 +#set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] ;# U62.J7 DQL7 +#set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] ;# U62.A3 DQU0 +#set_property -dict {LOC L26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] ;# U62.B8 DQU1 +#set_property -dict {LOC J27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] ;# U62.C3 DQU2 +#set_property -dict {LOC K28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] ;# U62.C7 DQU3 +#set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] ;# U62.C2 DQU4 +#set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] ;# U62.C8 DQU5 +#set_property -dict {LOC J26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] ;# U62.D3 DQU6 +#set_property -dict {LOC L28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] ;# U62.D7 DQU7 +#set_property -dict {LOC P25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] ;# U62.G3 DQSL_T +#set_property -dict {LOC N25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] ;# U62.F3 DQSL_C +#set_property -dict {LOC L24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] ;# U62.B7 DQSU_T +#set_property -dict {LOC L25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] ;# U62.A7 DQSU_C +#set_property -dict {LOC T26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] ;# U62.E7 DML_B/DBIL_B +#set_property -dict {LOC M27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] ;# U62.E2 DMU_B/DBIU_B + +#set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] ;# U63.G2 DQL0 +#set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] ;# U63.F7 DQL1 +#set_property -dict {LOC E26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] ;# U63.H3 DQL2 +#set_property -dict {LOC H27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] ;# U63.H7 DQL3 +#set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] ;# U63.H2 DQL4 +#set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] ;# U63.H8 DQL5 +#set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] ;# U63.J3 DQL6 +#set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] ;# U63.J7 DQL7 +#set_property -dict {LOC B28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] ;# U63.A3 DQU0 +#set_property -dict {LOC A28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] ;# U63.B8 DQU1 +#set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] ;# U63.C3 DQU2 +#set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] ;# U63.C7 DQU3 +#set_property -dict {LOC D25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] ;# U63.C2 DQU4 +#set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] ;# U63.C8 DQU5 +#set_property -dict {LOC C25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] ;# U63.D3 DQU6 +#set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] ;# U63.D7 DQU7 +#set_property -dict {LOC H28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] ;# U63.G3 DQSL_T +#set_property -dict {LOC G28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] ;# U63.F3 DQSL_C +#set_property -dict {LOC B26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] ;# U63.B7 DQSU_T +#set_property -dict {LOC A26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] ;# U63.A7 DQSU_C +#set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] ;# U63.E7 DML_B/DBIL_B +#set_property -dict {LOC D27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] ;# U63.E2 DMU_B/DBIU_B + +#set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] ;# U64.G2 DQL0 +#set_property -dict {LOC M31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] ;# U64.F7 DQL1 +#set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] ;# U64.H3 DQL2 +#set_property -dict {LOC L29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] ;# U64.H7 DQL3 +#set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] ;# U64.H2 DQL4 +#set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] ;# U64.H8 DQL5 +#set_property -dict {LOC L31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] ;# U64.J3 DQL6 +#set_property -dict {LOC L30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] ;# U64.J7 DQL7 +#set_property -dict {LOC H30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[72]}] ;# U64.A3 DQU0 +#set_property -dict {LOC J32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[73]}] ;# U64.B8 DQU1 +#set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[74]}] ;# U64.C3 DQU2 +#set_property -dict {LOC H32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[75]}] ;# U64.C7 DQU3 +#set_property -dict {LOC J29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[76]}] ;# U64.C2 DQU4 +#set_property -dict {LOC K32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[77]}] ;# U64.C8 DQU5 +#set_property -dict {LOC J30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[78]}] ;# U64.D3 DQU6 +#set_property -dict {LOC G32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[79]}] ;# U64.D7 DQU7 +#set_property -dict {LOC N30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] ;# U64.G3 DQSL_T +#set_property -dict {LOC M30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] ;# U64.F3 DQSL_C +#set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] ;# U64.B7 DQSU_T +#set_property -dict {LOC G33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] ;# U64.A7 DQSU_C +#set_property -dict {LOC R28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}] ;# U64.E7 DML_B/DBIL_B +#set_property -dict {LOC K31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[9]}] ;# U64.E2 DMU_B/DBIU_B + +# DDR4 C2 +# 5x MT40A256M16GE-075E +#set_property -dict {LOC AM27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +#set_property -dict {LOC AT25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +#set_property -dict {LOC AN25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +#set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +#set_property -dict {LOC AR25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +#set_property -dict {LOC AU28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +#set_property -dict {LOC AU27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +#set_property -dict {LOC AR28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +#set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +#set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +#set_property -dict {LOC AN28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +#set_property -dict {LOC AR27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +#set_property -dict {LOC AP28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +#set_property -dict {LOC AL27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +#set_property -dict {LOC AP27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +#set_property -dict {LOC AM28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +#set_property -dict {LOC AU26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +#set_property -dict {LOC AV26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +#set_property -dict {LOC AV28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +#set_property -dict {LOC AT26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t}] +#set_property -dict {LOC AT27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c}] +#set_property -dict {LOC AY29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke}] +#set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n}] +#set_property -dict {LOC AW28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +#set_property -dict {LOC BB29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt}] +#set_property -dict {LOC BF29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +#set_property -dict {LOC BF40 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] +#set_property -dict {LOC AV25 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_alert_n}] + +#set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] ;# U135.G2 DQL0 +#set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] ;# U135.F7 DQL1 +#set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] ;# U135.H3 DQL2 +#set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] ;# U135.H7 DQL3 +#set_property -dict {LOC BD31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] ;# U135.H2 DQL4 +#set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] ;# U135.H8 DQL5 +#set_property -dict {LOC BD32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] ;# U135.J3 DQL6 +#set_property -dict {LOC BC31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] ;# U135.J7 DQL7 +#set_property -dict {LOC BA31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] ;# U135.A3 DQU0 +#set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] ;# U135.B8 DQU1 +#set_property -dict {LOC BA30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] ;# U135.C3 DQU2 +#set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] ;# U135.C7 DQU3 +#set_property -dict {LOC AW32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] ;# U135.C2 DQU4 +#set_property -dict {LOC BB33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] ;# U135.C8 DQU5 +#set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] ;# U135.D3 DQU6 +#set_property -dict {LOC BA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] ;# U135.D7 DQU7 +#set_property -dict {LOC BF30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] ;# U135.G3 DQSL_T +#set_property -dict {LOC BF31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] ;# U135.F3 DQSL_C +#set_property -dict {LOC AY34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] ;# U135.B7 DQSU_T +#set_property -dict {LOC BA34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] ;# U135.A7 DQSU_C +#set_property -dict {LOC BE32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[0]}] ;# U135.E7 DML_B/DBIL_B +#set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[1]}] ;# U135.E2 DMU_B/DBIU_B + +#set_property -dict {LOC AT31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] ;# U136.G2 DQL0 +#set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] ;# U136.F7 DQL1 +#set_property -dict {LOC AV30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] ;# U136.H3 DQL2 +#set_property -dict {LOC AU33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] ;# U136.H7 DQL3 +#set_property -dict {LOC AU31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] ;# U136.H2 DQL4 +#set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] ;# U136.H8 DQL5 +#set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] ;# U136.J3 DQL6 +#set_property -dict {LOC AU34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] ;# U136.J7 DQL7 +#set_property -dict {LOC AT29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] ;# U136.A3 DQU0 +#set_property -dict {LOC AT34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] ;# U136.B8 DQU1 +#set_property -dict {LOC AT30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] ;# U136.C3 DQU2 +#set_property -dict {LOC AR33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] ;# U136.C7 DQU3 +#set_property -dict {LOC AR30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] ;# U136.C2 DQU4 +#set_property -dict {LOC AN30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] ;# U136.C8 DQU5 +#set_property -dict {LOC AP30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] ;# U136.D3 DQU6 +#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] ;# U136.D7 DQU7 +#set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] ;# U136.G3 DQSL_T +#set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] ;# U136.F3 DQSL_C +#set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] ;# U136.B7 DQSU_T +#set_property -dict {LOC AP32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] ;# U136.A7 DQSU_C +#set_property -dict {LOC AV33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[2]}] ;# U136.E7 DML_B/DBIL_B +#set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[3]}] ;# U136.E2 DMU_B/DBIU_B + +#set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] ;# U137.G2 DQL0 +#set_property -dict {LOC BF36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] ;# U137.F7 DQL1 +#set_property -dict {LOC BC35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] ;# U137.H3 DQL2 +#set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] ;# U137.H7 DQL3 +#set_property -dict {LOC BE34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] ;# U137.H2 DQL4 +#set_property -dict {LOC BD36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] ;# U137.H8 DQL5 +#set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] ;# U137.J3 DQL6 +#set_property -dict {LOC BC36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] ;# U137.J7 DQL7 +#set_property -dict {LOC BD37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] ;# U137.A3 DQU0 +#set_property -dict {LOC BE38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] ;# U137.B8 DQU1 +#set_property -dict {LOC BD38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] ;# U137.C3 DQU2 +#set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] ;# U137.C7 DQU3 +#set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] ;# U137.C2 DQU4 +#set_property -dict {LOC BB39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] ;# U137.C8 DQU5 +#set_property -dict {LOC BC39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] ;# U137.D3 DQU6 +#set_property -dict {LOC BC38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] ;# U137.D7 DQU7 +#set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] ;# U137.G3 DQSL_T +#set_property -dict {LOC BF35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] ;# U137.F3 DQSL_C +#set_property -dict {LOC BE39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] ;# U137.B7 DQSU_T +#set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] ;# U137.A7 DQSU_C +#set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[4]}] ;# U137.E7 DML_B/DBIL_B +#set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[5]}] ;# U137.E2 DMU_B/DBIU_B + +#set_property -dict {LOC AW40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] ;# U138.G2 DQL0 +#set_property -dict {LOC BA40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] ;# U138.F7 DQL1 +#set_property -dict {LOC AY39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] ;# U138.H3 DQL2 +#set_property -dict {LOC AY38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] ;# U138.H7 DQL3 +#set_property -dict {LOC AY40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] ;# U138.H2 DQL4 +#set_property -dict {LOC BA39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] ;# U138.H8 DQL5 +#set_property -dict {LOC BB36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] ;# U138.J3 DQL6 +#set_property -dict {LOC BB37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] ;# U138.J7 DQL7 +#set_property -dict {LOC AV38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] ;# U138.A3 DQU0 +#set_property -dict {LOC AU38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] ;# U138.B8 DQU1 +#set_property -dict {LOC AU39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] ;# U138.C3 DQU2 +#set_property -dict {LOC AW35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] ;# U138.C7 DQU3 +#set_property -dict {LOC AU40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] ;# U138.C2 DQU4 +#set_property -dict {LOC AV40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] ;# U138.C8 DQU5 +#set_property -dict {LOC AW36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] ;# U138.D3 DQU6 +#set_property -dict {LOC AV39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] ;# U138.D7 DQU7 +#set_property -dict {LOC BA35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] ;# U138.G3 DQSL_T +#set_property -dict {LOC BA36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] ;# U138.F3 DQSL_C +#set_property -dict {LOC AW37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] ;# U138.B7 DQSU_T +#set_property -dict {LOC AW38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] ;# U138.A7 DQSU_C +#set_property -dict {LOC AY37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[6]}] ;# U138.E7 DML_B/DBIL_B +#set_property -dict {LOC AV35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[7]}] ;# U138.E2 DMU_B/DBIU_B + +#set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] ;# U139.G2 DQL0 +#set_property -dict {LOC BD26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] ;# U139.F7 DQL1 +#set_property -dict {LOC BD27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] ;# U139.H3 DQL2 +#set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] ;# U139.H7 DQL3 +#set_property -dict {LOC BD28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] ;# U139.H2 DQL4 +#set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] ;# U139.H8 DQL5 +#set_property -dict {LOC BF26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] ;# U139.J3 DQL6 +#set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] ;# U139.J7 DQL7 +#set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[72]}] ;# U139.A3 DQU0 +#set_property -dict {LOC BC26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[73]}] ;# U139.B8 DQU1 +#set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[74]}] ;# U139.C3 DQU2 +#set_property -dict {LOC BB28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[75]}] ;# U139.C7 DQU3 +#set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[76]}] ;# U139.C2 DQU4 +#set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[77]}] ;# U139.C8 DQU5 +#set_property -dict {LOC BC25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[78]}] ;# U139.D3 DQU6 +#set_property -dict {LOC BC28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[79]}] ;# U139.D7 DQU7 +#set_property -dict {LOC BE25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] ;# U139.G3 DQSL_T +#set_property -dict {LOC BF25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] ;# U139.F3 DQSL_C +#set_property -dict {LOC BA26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] ;# U139.B7 DQSU_T +#set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] ;# U139.A7 DQSU_C +#set_property -dict {LOC BE29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[8]}] ;# U139.E7 DML_B/DBIL_B +#set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[9]}] ;# U139.E2 DMU_B/DBIU_B + # BPI flash #set_property -dict {LOC AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[4]}] #set_property -dict {LOC AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[5]}] diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/README.md b/fpga/lib/eth/example/VCU118/fpga_10g/README.md deleted file mode 100644 index 25d58478b..000000000 --- a/fpga/lib/eth/example/VCU118/fpga_10g/README.md +++ /dev/null @@ -1,40 +0,0 @@ -# Verilog Ethernet VCU118 Example Design - -## Introduction - -This example design targets the Xilinx VCU118 FPGA board. - -The design by default listens to UDP port 1234 at IP address 192.168.1.128 and -will echo back any packets received. The design will also respond correctly -to ARP requests. The design also enables the gigabit Ethernet interface for -testing with a QSFP loopback adapter. - -* FPGA: xcvu9p-flga2104-2L-e -* PHY: 10G BASE-R PHY IP core and internal GTY transceiver - -## How to build - -Run make to build. Ensure that the Xilinx Vivado toolchain components are -in PATH. - -## How to test - -Run make program to program the VCU118 board with Vivado. Then run - - netcat -u 192.168.1.128 1234 - -to open a UDP connection to port 1234. Any text entered into netcat will be -echoed back after pressing enter. - -It is also possible to use hping to test the design by running - - hping 192.168.1.128 -2 -p 1234 -d 1024 - -Note that the gigabit PHY is also enabled for debugging. The gigabit port can -be inserted into the 10G data path between the 10G MAC and 10G PHY so that the -10G interface can be tested with a QSFP loopback adapter. Turn on SW12.1 to -insert the gigabit port into the 10G data path, or off to bypass the gigabit -port. Turn on SW12.2 to place the port in the TX path or off to place the -port in the RX path. - - diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/common/vivado.mk b/fpga/lib/eth/example/VCU118/fpga_10g/common/vivado.mk deleted file mode 100644 index 21e6a5fed..000000000 --- a/fpga/lib/eth/example/VCU118/fpga_10g/common/vivado.mk +++ /dev/null @@ -1,131 +0,0 @@ -################################################################### -# -# Xilinx Vivado FPGA Makefile -# -# Copyright (c) 2016 Alex Forencich -# -################################################################### -# -# Parameters: -# FPGA_TOP - Top module name -# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) -# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) -# SYN_FILES - space-separated list of source files -# INC_FILES - space-separated list of include files -# XDC_FILES - space-separated list of timing constraint files -# XCI_FILES - space-separated list of IP XCI files -# -# Example: -# -# FPGA_TOP = fpga -# FPGA_FAMILY = VirtexUltrascale -# FPGA_DEVICE = xcvu095-ffva2104-2-e -# SYN_FILES = rtl/fpga.v -# XDC_FILES = fpga.xdc -# XCI_FILES = ip/pcspma.xci -# include ../common/vivado.mk -# -################################################################### - -# phony targets -.PHONY: clean fpga - -# prevent make from deleting intermediate files and reports -.PRECIOUS: %.xpr %.bit %.mcs %.prm -.SECONDARY: - -CONFIG ?= config.mk --include ../$(CONFIG) - -FPGA_TOP ?= fpga -PROJECT ?= $(FPGA_TOP) - -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) - -ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) -else - XDC_FILES_REL = $(FPGA_TOP).xdc -endif - -################################################################### -# Main Targets -# -# all: build everything -# clean: remove output files and project files -################################################################### - -all: fpga - -fpga: $(FPGA_TOP).bit - -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr - -tmpclean: - -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl - -clean: tmpclean - -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl - -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt - -distclean: clean - -rm -rf rev - -################################################################### -# Target implementations -################################################################### - -# Vivado project file -create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) - rm -rf defines.v - touch defines.v - for x in $(DEFS); do echo '`define' $$x >> defines.v; done - echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ - echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ - echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ - echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ - for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done - for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done - -$(PROJECT).xpr: create_project.tcl - vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) - -# synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) - echo "open_project $(PROJECT).xpr" > run_synth.tcl - echo "reset_run synth_1" >> run_synth.tcl - echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl - echo "wait_on_run synth_1" >> run_synth.tcl - vivado -nojournal -nolog -mode batch -source run_synth.tcl - -# implementation run -$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp - echo "open_project $(PROJECT).xpr" > run_impl.tcl - echo "reset_run impl_1" >> run_impl.tcl - echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl - echo "wait_on_run impl_1" >> run_impl.tcl - echo "open_run impl_1" >> run_impl.tcl - echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl - echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl - vivado -nojournal -nolog -mode batch -source run_impl.tcl - -# bit file -$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp - echo "open_project $(PROJECT).xpr" > generate_bit.tcl - echo "open_run impl_1" >> generate_bit.tcl - echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl - echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl - vivado -nojournal -nolog -mode batch -source generate_bit.tcl - ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi - mkdir -p rev - COUNT=100; \ - while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ - do COUNT=$$((COUNT+1)); done; \ - cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/fpga.xdc b/fpga/lib/eth/example/VCU118/fpga_10g/fpga.xdc deleted file mode 100644 index fafef75ee..000000000 --- a/fpga/lib/eth/example/VCU118/fpga_10g/fpga.xdc +++ /dev/null @@ -1,302 +0,0 @@ -# XDC constraints for the Xilinx VCU118 board -# part: xcvu9p-flga2104-2L-e - -# General configuration -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] -set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] -set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] - -# System clocks -# 300 MHz -#set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_p] -#set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_n] -#create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p] - -# 250 MHz -#set_property -dict {LOC E12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_p] -#set_property -dict {LOC D12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_n] -#create_clock -period 4 -name clk_250mhz_1 [get_ports clk_250mhz_1_p] - -#set_property -dict {LOC AW26 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_p] -#set_property -dict {LOC AW27 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_n] -#create_clock -period 4 -name clk_250mhz_2 [get_ports clk_250mhz_2_p] - -# 125 MHz -set_property -dict {LOC AY24 IOSTANDARD LVDS} [get_ports clk_125mhz_p] -set_property -dict {LOC AY23 IOSTANDARD LVDS} [get_ports clk_125mhz_n] -create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p] - -# 90 MHz -#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz] -#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz] - -# LEDs -set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] -set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] -set_property -dict {LOC AY30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}] -set_property -dict {LOC BB32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[3]}] -set_property -dict {LOC BF32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[4]}] -set_property -dict {LOC AU37 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[5]}] -set_property -dict {LOC AV36 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[6]}] -set_property -dict {LOC BA37 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[7]}] - -set_false_path -to [get_ports {led[*]}] -set_output_delay 0 [get_ports {led[*]}] - -# Reset button -set_property -dict {LOC L19 IOSTANDARD LVCMOS12} [get_ports reset] - -set_false_path -from [get_ports {reset}] -set_input_delay 0 [get_ports {reset}] - -# Push buttons -set_property -dict {LOC BB24 IOSTANDARD LVCMOS18} [get_ports btnu] -set_property -dict {LOC BF22 IOSTANDARD LVCMOS18} [get_ports btnl] -set_property -dict {LOC BE22 IOSTANDARD LVCMOS18} [get_ports btnd] -set_property -dict {LOC BE23 IOSTANDARD LVCMOS18} [get_ports btnr] -set_property -dict {LOC BD23 IOSTANDARD LVCMOS18} [get_ports btnc] - -set_false_path -from [get_ports {btnu btnl btnd btnr btnc}] -set_input_delay 0 [get_ports {btnu btnl btnd btnr btnc}] - -# DIP switches -set_property -dict {LOC B17 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] -set_property -dict {LOC G16 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] -set_property -dict {LOC J16 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] -set_property -dict {LOC D21 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] - -set_false_path -from [get_ports {sw[*]}] -set_input_delay 0 [get_ports {sw[*]}] - -# PMOD0 -#set_property -dict {LOC AY14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[0]}] -#set_property -dict {LOC AY15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[1]}] -#set_property -dict {LOC AW15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[2]}] -#set_property -dict {LOC AV15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[3]}] -#set_property -dict {LOC AV16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[4]}] -#set_property -dict {LOC AU16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[5]}] -#set_property -dict {LOC AT15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[6]}] -#set_property -dict {LOC AT16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[7]}] - -#set_false_path -to [get_ports {pmod0[*]}] -#set_output_delay 0 [get_ports {pmod0[*]}] - -# PMOD1 -#set_property -dict {LOC N28 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[0]}] -#set_property -dict {LOC M30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[1]}] -#set_property -dict {LOC N30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[2]}] -#set_property -dict {LOC P30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[3]}] -#set_property -dict {LOC P29 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[4]}] -#set_property -dict {LOC L31 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[5]}] -#set_property -dict {LOC M31 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[6]}] -#set_property -dict {LOC R29 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[7]}] - -#set_false_path -to [get_ports {pmod1[*]}] -#set_output_delay 0 [get_ports {pmod1[*]}] - -# UART -set_property -dict {LOC BB21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] -set_property -dict {LOC AW25 IOSTANDARD LVCMOS18} [get_ports uart_rxd] -set_property -dict {LOC BB22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rts] -set_property -dict {LOC AY25 IOSTANDARD LVCMOS18} [get_ports uart_cts] - -set_false_path -to [get_ports {uart_txd uart_rts}] -set_output_delay 0 [get_ports {uart_txd uart_rts}] -set_false_path -from [get_ports {uart_rxd uart_cts}] -set_input_delay 0 [get_ports {uart_rxd uart_cts}] - -# Gigabit Ethernet SGMII PHY -set_property -dict {LOC AU24 IOSTANDARD LVDS} [get_ports phy_sgmii_rx_p] -set_property -dict {LOC AV24 IOSTANDARD LVDS} [get_ports phy_sgmii_rx_n] -set_property -dict {LOC AU21 IOSTANDARD LVDS} [get_ports phy_sgmii_tx_p] -set_property -dict {LOC AV21 IOSTANDARD LVDS} [get_ports phy_sgmii_tx_n] -set_property -dict {LOC AT22 IOSTANDARD LVDS} [get_ports phy_sgmii_clk_p] -set_property -dict {LOC AU22 IOSTANDARD LVDS} [get_ports phy_sgmii_clk_n] -set_property -dict {LOC BA21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_reset_n] -set_property -dict {LOC AR24 IOSTANDARD LVCMOS18} [get_ports phy_int_n] -set_property -dict {LOC AR23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdio] -set_property -dict {LOC AV23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdc] - -# 625 MHz ref clock from SGMII PHY -#create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p] - -set_false_path -to [get_ports {phy_reset_n phy_mdio phy_mdc}] -set_output_delay 0 [get_ports {phy_reset_n phy_mdio phy_mdc}] -set_false_path -from [get_ports {phy_int_n phy_mdio}] -set_input_delay 0 [get_ports {phy_int_n phy_mdio}] - -# QSFP28 Interfaces -set_property -dict {LOC Y2 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC Y1 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V7 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V6 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC W4 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC W3 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V2 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V1 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC P7 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC P6 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC U4 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC U3 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC W9 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U38.4 -set_property -dict {LOC W8 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U38.5 -#set_property -dict {LOC U9 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U57.28 -#set_property -dict {LOC U8 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_231 from U57.29 -#set_property -dict {LOC AM23 IOSTANDARD LVDS} [get_ports qsfp1_recclk_p] ;# to U57.16 -#set_property -dict {LOC AM22 IOSTANDARD LVDS} [get_ports qsfp1_recclk_n] ;# to U57.17 -set_property -dict {LOC AM21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_modsell] -set_property -dict {LOC BA22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl] -set_property -dict {LOC AL21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_modprsl] -set_property -dict {LOC AP21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_intl] -set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode] - -# 156.25 MHz MGT reference clock -create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p] - -set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}] -set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}] -set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] -set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] - -set_property -dict {LOC T2 } [get_ports qsfp2_rx1_p] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC T1 } [get_ports qsfp2_rx1_n] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC L5 } [get_ports qsfp2_tx1_p] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC L4 } [get_ports qsfp2_tx1_n] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC R4 } [get_ports qsfp2_rx2_p] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC R3 } [get_ports qsfp2_rx2_n] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC K7 } [get_ports qsfp2_tx2_p] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC K6 } [get_ports qsfp2_tx2_n] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC P2 } [get_ports qsfp2_rx3_p] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC P1 } [get_ports qsfp2_rx3_n] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC J5 } [get_ports qsfp2_tx3_p] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC J4 } [get_ports qsfp2_tx3_n] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC M2 } [get_ports qsfp2_rx4_p] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC M1 } [get_ports qsfp2_rx4_n] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC H7 } [get_ports qsfp2_tx4_p] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC H6 } [get_ports qsfp2_tx4_n] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13 -set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14 -#set_property -dict {LOC N9 } [get_ports qsfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_232 from U57.35 -#set_property -dict {LOC N8 } [get_ports qsfp2_mgt_refclk_1_n] ;# MGTREFCLK1N_232 from U57.34 -#set_property -dict {LOC AP23 IOSTANDARD LVDS} [get_ports qsfp2_recclk_p] ;# to U57.12 -#set_property -dict {LOC AP22 IOSTANDARD LVDS} [get_ports qsfp2_recclk_n] ;# to U57.13 -set_property -dict {LOC AN23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_modsell] -set_property -dict {LOC AY22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_resetl] -set_property -dict {LOC AN24 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp2_modprsl] -set_property -dict {LOC AT21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp2_intl] -set_property -dict {LOC AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_lpmode] - -# 156.25 MHz MGT reference clock -create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p] - -set_false_path -to [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}] -set_output_delay 0 [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}] -set_false_path -from [get_ports {qsfp2_modprsl qsfp2_intl}] -set_input_delay 0 [get_ports {qsfp2_modprsl qsfp2_intl}] - -# I2C interface -set_property -dict {LOC AM24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_scl] -set_property -dict {LOC AL24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_sda] - -set_false_path -to [get_ports {i2c_sda i2c_scl}] -set_output_delay 0 [get_ports {i2c_sda i2c_scl}] -set_false_path -from [get_ports {i2c_sda i2c_scl}] -set_input_delay 0 [get_ports {i2c_sda i2c_scl}] - -# PCIe Interface -#set_property -dict {LOC AA4 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AA3 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC Y7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC Y6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AB7 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AB6 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AC4 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AC3 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AN5 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AN4 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AR5 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AR4 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AU5 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AU4 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AW5 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AW4 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BA5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BA4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AY2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AY1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BC5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BC4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BB2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BB1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BE5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BE4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AC9 } [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_227 -#set_property -dict {LOC AC8 } [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_227 -#set_property -dict {LOC AL9 } [get_ports pcie_refclk_2_p] ;# MGTREFCLK0P_225 -#set_property -dict {LOC AL8 } [get_ports pcie_refclk_2_n] ;# MGTREFCLK0N_225 -#set_property -dict {LOC AM17 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n] - -# 100 MHz MGT reference clock -#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p] -#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports pcie_refclk_2_p] - -#set_false_path -from [get_ports {pcie_reset_n}] -#set_input_delay 0 [get_ports {pcie_reset_n}] - -# QSPI flash -#set_property -dict {LOC AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}] -#set_property -dict {LOC AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}] -#set_property -dict {LOC AN20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[2]}] -#set_property -dict {LOC AP20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[3]}] -#set_property -dict {LOC BF16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_cs}] - -#set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}] -#set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}] -#set_false_path -from [get_ports {qspi_1_dq}] -#set_input_delay 0 [get_ports {qspi_1_dq}] diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/rtl/fpga.v b/fpga/lib/eth/example/VCU118/fpga_10g/rtl/fpga.v deleted file mode 100644 index eaeaa06eb..000000000 --- a/fpga/lib/eth/example/VCU118/fpga_10g/rtl/fpga.v +++ /dev/null @@ -1,1222 +0,0 @@ -/* - -Copyright (c) 2014-2021 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA top-level module - */ -module fpga ( - /* - * Clock: 125MHz LVDS - * Reset: Push button, active low - */ - input wire clk_125mhz_p, - input wire clk_125mhz_n, - input wire reset, - - /* - * GPIO - */ - input wire btnu, - input wire btnl, - input wire btnd, - input wire btnr, - input wire btnc, - input wire [3:0] sw, - output wire [7:0] led, - - /* - * I2C for board management - */ - inout wire i2c_scl, - inout wire i2c_sda, - - /* - * Ethernet: QSFP28 - */ - output wire qsfp1_tx1_p, - output wire qsfp1_tx1_n, - input wire qsfp1_rx1_p, - input wire qsfp1_rx1_n, - output wire qsfp1_tx2_p, - output wire qsfp1_tx2_n, - input wire qsfp1_rx2_p, - input wire qsfp1_rx2_n, - output wire qsfp1_tx3_p, - output wire qsfp1_tx3_n, - input wire qsfp1_rx3_p, - input wire qsfp1_rx3_n, - output wire qsfp1_tx4_p, - output wire qsfp1_tx4_n, - input wire qsfp1_rx4_p, - input wire qsfp1_rx4_n, - input wire qsfp1_mgt_refclk_0_p, - input wire qsfp1_mgt_refclk_0_n, - // input wire qsfp1_mgt_refclk_1_p, - // input wire qsfp1_mgt_refclk_1_n, - // output wire qsfp1_recclk_p, - // output wire qsfp1_recclk_n, - output wire qsfp1_modsell, - output wire qsfp1_resetl, - input wire qsfp1_modprsl, - input wire qsfp1_intl, - output wire qsfp1_lpmode, - - output wire qsfp2_tx1_p, - output wire qsfp2_tx1_n, - input wire qsfp2_rx1_p, - input wire qsfp2_rx1_n, - output wire qsfp2_tx2_p, - output wire qsfp2_tx2_n, - input wire qsfp2_rx2_p, - input wire qsfp2_rx2_n, - output wire qsfp2_tx3_p, - output wire qsfp2_tx3_n, - input wire qsfp2_rx3_p, - input wire qsfp2_rx3_n, - output wire qsfp2_tx4_p, - output wire qsfp2_tx4_n, - input wire qsfp2_rx4_p, - input wire qsfp2_rx4_n, - input wire qsfp2_mgt_refclk_0_p, - input wire qsfp2_mgt_refclk_0_n, - // input wire qsfp2_mgt_refclk_1_p, - // input wire qsfp2_mgt_refclk_1_n, - // output wire qsfp2_recclk_p, - // output wire qsfp2_recclk_n, - output wire qsfp2_modsell, - output wire qsfp2_resetl, - input wire qsfp2_modprsl, - input wire qsfp2_intl, - output wire qsfp2_lpmode, - - /* - * Ethernet: 1000BASE-T SGMII - */ - input wire phy_sgmii_rx_p, - input wire phy_sgmii_rx_n, - output wire phy_sgmii_tx_p, - output wire phy_sgmii_tx_n, - input wire phy_sgmii_clk_p, - input wire phy_sgmii_clk_n, - output wire phy_reset_n, - input wire phy_int_n, - inout wire phy_mdio, - output wire phy_mdc, - - /* - * UART: 500000 bps, 8N1 - */ - input wire uart_rxd, - output wire uart_txd, - output wire uart_rts, - input wire uart_cts -); - -// Clock and reset - -wire clk_125mhz_ibufg; - -// Internal 125 MHz clock -wire clk_125mhz_mmcm_out; -wire clk_125mhz_int; -wire rst_125mhz_int; - -// Internal 156.25 MHz clock -wire clk_156mhz_int; -wire rst_156mhz_int; - -wire mmcm_rst = reset; -wire mmcm_locked; -wire mmcm_clkfb; - -IBUFGDS #( - .DIFF_TERM("FALSE"), - .IBUF_LOW_PWR("FALSE") -) -clk_125mhz_ibufg_inst ( - .O (clk_125mhz_ibufg), - .I (clk_125mhz_p), - .IB (clk_125mhz_n) -); - -// MMCM instance -// 125 MHz in, 125 MHz out -// PFD range: 10 MHz to 500 MHz -// VCO range: 800 MHz to 1600 MHz -// M = 8, D = 1 sets Fvco = 1000 MHz (in range) -// Divide by 8 to get output frequency of 125 MHz -MMCME3_BASE #( - .BANDWIDTH("OPTIMIZED"), - .CLKOUT0_DIVIDE_F(8), - .CLKOUT0_DUTY_CYCLE(0.5), - .CLKOUT0_PHASE(0), - .CLKOUT1_DIVIDE(1), - .CLKOUT1_DUTY_CYCLE(0.5), - .CLKOUT1_PHASE(0), - .CLKOUT2_DIVIDE(1), - .CLKOUT2_DUTY_CYCLE(0.5), - .CLKOUT2_PHASE(0), - .CLKOUT3_DIVIDE(1), - .CLKOUT3_DUTY_CYCLE(0.5), - .CLKOUT3_PHASE(0), - .CLKOUT4_DIVIDE(1), - .CLKOUT4_DUTY_CYCLE(0.5), - .CLKOUT4_PHASE(0), - .CLKOUT5_DIVIDE(1), - .CLKOUT5_DUTY_CYCLE(0.5), - .CLKOUT5_PHASE(0), - .CLKOUT6_DIVIDE(1), - .CLKOUT6_DUTY_CYCLE(0.5), - .CLKOUT6_PHASE(0), - .CLKFBOUT_MULT_F(8), - .CLKFBOUT_PHASE(0), - .DIVCLK_DIVIDE(1), - .REF_JITTER1(0.010), - .CLKIN1_PERIOD(8.0), - .STARTUP_WAIT("FALSE"), - .CLKOUT4_CASCADE("FALSE") -) -clk_mmcm_inst ( - .CLKIN1(clk_125mhz_ibufg), - .CLKFBIN(mmcm_clkfb), - .RST(mmcm_rst), - .PWRDWN(1'b0), - .CLKOUT0(clk_125mhz_mmcm_out), - .CLKOUT0B(), - .CLKOUT1(), - .CLKOUT1B(), - .CLKOUT2(), - .CLKOUT2B(), - .CLKOUT3(), - .CLKOUT3B(), - .CLKOUT4(), - .CLKOUT5(), - .CLKOUT6(), - .CLKFBOUT(mmcm_clkfb), - .CLKFBOUTB(), - .LOCKED(mmcm_locked) -); - -BUFG -clk_125mhz_bufg_inst ( - .I(clk_125mhz_mmcm_out), - .O(clk_125mhz_int) -); - -sync_reset #( - .N(4) -) -sync_reset_125mhz_inst ( - .clk(clk_125mhz_int), - .rst(~mmcm_locked), - .out(rst_125mhz_int) -); - -// GPIO -wire btnu_int; -wire btnl_int; -wire btnd_int; -wire btnr_int; -wire btnc_int; -wire [3:0] sw_int; - -debounce_switch #( - .WIDTH(9), - .N(4), - .RATE(156000) -) -debounce_switch_inst ( - .clk(clk_156mhz_int), - .rst(rst_156mhz_int), - .in({btnu, - btnl, - btnd, - btnr, - btnc, - sw}), - .out({btnu_int, - btnl_int, - btnd_int, - btnr_int, - btnc_int, - sw_int}) -); - -wire uart_rxd_int; -wire uart_cts_int; - -sync_signal #( - .WIDTH(2), - .N(2) -) -sync_signal_inst ( - .clk(clk_156mhz_int), - .in({uart_rxd, uart_cts}), - .out({uart_rxd_int, uart_cts_int}) -); - -// SI570 I2C -wire i2c_scl_i; -wire i2c_scl_o = 1'b1; -wire i2c_scl_t = 1'b1; -wire i2c_sda_i; -wire i2c_sda_o = 1'b1; -wire i2c_sda_t = 1'b1; - -assign i2c_scl_i = i2c_scl; -assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o; -assign i2c_sda_i = i2c_sda; -assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o; - -// XGMII 10G PHY - -// QSFP1 -assign qsfp1_modsell = 1'b0; -assign qsfp1_resetl = 1'b1; -assign qsfp1_lpmode = 1'b0; - -wire qsfp1_tx_clk_1_int; -wire qsfp1_tx_rst_1_int; -wire [63:0] qsfp1_txd_1_int; -wire [7:0] qsfp1_txc_1_int; -wire qsfp1_rx_clk_1_int; -wire qsfp1_rx_rst_1_int; -wire [63:0] qsfp1_rxd_1_int; -wire [7:0] qsfp1_rxc_1_int; -wire qsfp1_tx_clk_2_int; -wire qsfp1_tx_rst_2_int; -wire [63:0] qsfp1_txd_2_int; -wire [7:0] qsfp1_txc_2_int; -wire qsfp1_rx_clk_2_int; -wire qsfp1_rx_rst_2_int; -wire [63:0] qsfp1_rxd_2_int; -wire [7:0] qsfp1_rxc_2_int; -wire qsfp1_tx_clk_3_int; -wire qsfp1_tx_rst_3_int; -wire [63:0] qsfp1_txd_3_int; -wire [7:0] qsfp1_txc_3_int; -wire qsfp1_rx_clk_3_int; -wire qsfp1_rx_rst_3_int; -wire [63:0] qsfp1_rxd_3_int; -wire [7:0] qsfp1_rxc_3_int; -wire qsfp1_tx_clk_4_int; -wire qsfp1_tx_rst_4_int; -wire [63:0] qsfp1_txd_4_int; -wire [7:0] qsfp1_txc_4_int; -wire qsfp1_rx_clk_4_int; -wire qsfp1_rx_rst_4_int; -wire [63:0] qsfp1_rxd_4_int; -wire [7:0] qsfp1_rxc_4_int; - -assign clk_156mhz_int = qsfp1_tx_clk_1_int; -assign rst_156mhz_int = qsfp1_tx_rst_1_int; - -wire qsfp1_rx_block_lock_1; -wire qsfp1_rx_block_lock_2; -wire qsfp1_rx_block_lock_3; -wire qsfp1_rx_block_lock_4; - -wire qsfp1_mgt_refclk_0; - -IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_0_inst ( - .I (qsfp1_mgt_refclk_0_p), - .IB (qsfp1_mgt_refclk_0_n), - .CEB (1'b0), - .O (qsfp1_mgt_refclk_0), - .ODIV2 () -); - -wire qsfp1_qpll0lock; -wire qsfp1_qpll0outclk; -wire qsfp1_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp1_phy_1_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_0), - .xcvr_qpll0lock_out(qsfp1_qpll0lock), - .xcvr_qpll0outclk_out(qsfp1_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp1_qpll0outrefclk), - - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), - - // Serial data - .xcvr_txp(qsfp1_tx1_p), - .xcvr_txn(qsfp1_tx1_n), - .xcvr_rxp(qsfp1_rx1_p), - .xcvr_rxn(qsfp1_rx1_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_1_int), - .phy_tx_rst(qsfp1_tx_rst_1_int), - .phy_xgmii_txd(qsfp1_txd_1_int), - .phy_xgmii_txc(qsfp1_txc_1_int), - .phy_rx_clk(qsfp1_rx_clk_1_int), - .phy_rx_rst(qsfp1_rx_rst_1_int), - .phy_xgmii_rxd(qsfp1_rxd_1_int), - .phy_xgmii_rxc(qsfp1_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx2_p), - .xcvr_txn(qsfp1_tx2_n), - .xcvr_rxp(qsfp1_rx2_p), - .xcvr_rxn(qsfp1_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_2_int), - .phy_tx_rst(qsfp1_tx_rst_2_int), - .phy_xgmii_txd(qsfp1_txd_2_int), - .phy_xgmii_txc(qsfp1_txc_2_int), - .phy_rx_clk(qsfp1_rx_clk_2_int), - .phy_rx_rst(qsfp1_rx_rst_2_int), - .phy_xgmii_rxd(qsfp1_rxd_2_int), - .phy_xgmii_rxc(qsfp1_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx3_p), - .xcvr_txn(qsfp1_tx3_n), - .xcvr_rxp(qsfp1_rx3_p), - .xcvr_rxn(qsfp1_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_3_int), - .phy_tx_rst(qsfp1_tx_rst_3_int), - .phy_xgmii_txd(qsfp1_txd_3_int), - .phy_xgmii_txc(qsfp1_txc_3_int), - .phy_rx_clk(qsfp1_rx_clk_3_int), - .phy_rx_rst(qsfp1_rx_rst_3_int), - .phy_xgmii_rxd(qsfp1_rxd_3_int), - .phy_xgmii_rxc(qsfp1_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx4_p), - .xcvr_txn(qsfp1_tx4_n), - .xcvr_rxp(qsfp1_rx4_p), - .xcvr_rxn(qsfp1_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_4_int), - .phy_tx_rst(qsfp1_tx_rst_4_int), - .phy_xgmii_txd(qsfp1_txd_4_int), - .phy_xgmii_txc(qsfp1_txc_4_int), - .phy_rx_clk(qsfp1_rx_clk_4_int), - .phy_rx_rst(qsfp1_rx_rst_4_int), - .phy_xgmii_rxd(qsfp1_rxd_4_int), - .phy_xgmii_rxc(qsfp1_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -// QSFP2 -assign qsfp2_modsell = 1'b0; -assign qsfp2_resetl = 1'b1; -assign qsfp2_lpmode = 1'b0; - -wire qsfp2_tx_clk_1_int; -wire qsfp2_tx_rst_1_int; -wire [63:0] qsfp2_txd_1_int; -wire [7:0] qsfp2_txc_1_int; -wire qsfp2_rx_clk_1_int; -wire qsfp2_rx_rst_1_int; -wire [63:0] qsfp2_rxd_1_int; -wire [7:0] qsfp2_rxc_1_int; -wire qsfp2_tx_clk_2_int; -wire qsfp2_tx_rst_2_int; -wire [63:0] qsfp2_txd_2_int; -wire [7:0] qsfp2_txc_2_int; -wire qsfp2_rx_clk_2_int; -wire qsfp2_rx_rst_2_int; -wire [63:0] qsfp2_rxd_2_int; -wire [7:0] qsfp2_rxc_2_int; -wire qsfp2_tx_clk_3_int; -wire qsfp2_tx_rst_3_int; -wire [63:0] qsfp2_txd_3_int; -wire [7:0] qsfp2_txc_3_int; -wire qsfp2_rx_clk_3_int; -wire qsfp2_rx_rst_3_int; -wire [63:0] qsfp2_rxd_3_int; -wire [7:0] qsfp2_rxc_3_int; -wire qsfp2_tx_clk_4_int; -wire qsfp2_tx_rst_4_int; -wire [63:0] qsfp2_txd_4_int; -wire [7:0] qsfp2_txc_4_int; -wire qsfp2_rx_clk_4_int; -wire qsfp2_rx_rst_4_int; -wire [63:0] qsfp2_rxd_4_int; -wire [7:0] qsfp2_rxc_4_int; - -wire qsfp2_rx_block_lock_1; -wire qsfp2_rx_block_lock_2; -wire qsfp2_rx_block_lock_3; -wire qsfp2_rx_block_lock_4; - -wire qsfp2_mgt_refclk_0; - -IBUFDS_GTE4 ibufds_gte4_qsfp2_mgt_refclk_0_inst ( - .I (qsfp2_mgt_refclk_0_p), - .IB (qsfp2_mgt_refclk_0_n), - .CEB (1'b0), - .O (qsfp2_mgt_refclk_0), - .ODIV2 () -); - -wire qsfp2_qpll0lock; -wire qsfp2_qpll0outclk; -wire qsfp2_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp2_phy_1_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(qsfp2_mgt_refclk_0), - .xcvr_qpll0lock_out(qsfp2_qpll0lock), - .xcvr_qpll0outclk_out(qsfp2_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp2_qpll0outrefclk), - - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), - - // Serial data - .xcvr_txp(qsfp2_tx1_p), - .xcvr_txn(qsfp2_tx1_n), - .xcvr_rxp(qsfp2_rx1_p), - .xcvr_rxn(qsfp2_rx1_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_1_int), - .phy_tx_rst(qsfp2_tx_rst_1_int), - .phy_xgmii_txd(qsfp2_txd_1_int), - .phy_xgmii_txc(qsfp2_txc_1_int), - .phy_rx_clk(qsfp2_rx_clk_1_int), - .phy_rx_rst(qsfp2_rx_rst_1_int), - .phy_xgmii_rxd(qsfp2_rxd_1_int), - .phy_xgmii_rxc(qsfp2_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp2_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp2_tx2_p), - .xcvr_txn(qsfp2_tx2_n), - .xcvr_rxp(qsfp2_rx2_p), - .xcvr_rxn(qsfp2_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_2_int), - .phy_tx_rst(qsfp2_tx_rst_2_int), - .phy_xgmii_txd(qsfp2_txd_2_int), - .phy_xgmii_txc(qsfp2_txc_2_int), - .phy_rx_clk(qsfp2_rx_clk_2_int), - .phy_rx_rst(qsfp2_rx_rst_2_int), - .phy_xgmii_rxd(qsfp2_rxd_2_int), - .phy_xgmii_rxc(qsfp2_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp2_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp2_tx3_p), - .xcvr_txn(qsfp2_tx3_n), - .xcvr_rxp(qsfp2_rx3_p), - .xcvr_rxn(qsfp2_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_3_int), - .phy_tx_rst(qsfp2_tx_rst_3_int), - .phy_xgmii_txd(qsfp2_txd_3_int), - .phy_xgmii_txc(qsfp2_txc_3_int), - .phy_rx_clk(qsfp2_rx_clk_3_int), - .phy_rx_rst(qsfp2_rx_rst_3_int), - .phy_xgmii_rxd(qsfp2_rxd_3_int), - .phy_xgmii_rxc(qsfp2_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp2_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp2_tx4_p), - .xcvr_txn(qsfp2_tx4_n), - .xcvr_rxp(qsfp2_rx4_p), - .xcvr_rxn(qsfp2_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_4_int), - .phy_tx_rst(qsfp2_tx_rst_4_int), - .phy_xgmii_txd(qsfp2_txd_4_int), - .phy_xgmii_txc(qsfp2_txc_4_int), - .phy_rx_clk(qsfp2_rx_clk_4_int), - .phy_rx_rst(qsfp2_rx_rst_4_int), - .phy_xgmii_rxd(qsfp2_rxd_4_int), - .phy_xgmii_rxc(qsfp2_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -// SGMII interface to PHY -wire phy_gmii_clk_int; -wire phy_gmii_rst_int; -wire phy_gmii_clk_en_int; -wire [7:0] phy_gmii_txd_int; -wire phy_gmii_tx_en_int; -wire phy_gmii_tx_er_int; -wire [7:0] phy_gmii_rxd_int; -wire phy_gmii_rx_dv_int; -wire phy_gmii_rx_er_int; - -wire [15:0] gig_eth_pcspma_status_vector; - -wire gig_eth_pcspma_status_link_status = gig_eth_pcspma_status_vector[0]; -wire gig_eth_pcspma_status_link_synchronization = gig_eth_pcspma_status_vector[1]; -wire gig_eth_pcspma_status_rudi_c = gig_eth_pcspma_status_vector[2]; -wire gig_eth_pcspma_status_rudi_i = gig_eth_pcspma_status_vector[3]; -wire gig_eth_pcspma_status_rudi_invalid = gig_eth_pcspma_status_vector[4]; -wire gig_eth_pcspma_status_rxdisperr = gig_eth_pcspma_status_vector[5]; -wire gig_eth_pcspma_status_rxnotintable = gig_eth_pcspma_status_vector[6]; -wire gig_eth_pcspma_status_phy_link_status = gig_eth_pcspma_status_vector[7]; -wire [1:0] gig_eth_pcspma_status_remote_fault_encdg = gig_eth_pcspma_status_vector[9:8]; -wire [1:0] gig_eth_pcspma_status_speed = gig_eth_pcspma_status_vector[11:10]; -wire gig_eth_pcspma_status_duplex = gig_eth_pcspma_status_vector[12]; -wire gig_eth_pcspma_status_remote_fault = gig_eth_pcspma_status_vector[13]; -wire [1:0] gig_eth_pcspma_status_pause = gig_eth_pcspma_status_vector[15:14]; - -wire [4:0] gig_eth_pcspma_config_vector; - -assign gig_eth_pcspma_config_vector[4] = 1'b1; // autonegotiation enable -assign gig_eth_pcspma_config_vector[3] = 1'b0; // isolate -assign gig_eth_pcspma_config_vector[2] = 1'b0; // power down -assign gig_eth_pcspma_config_vector[1] = 1'b0; // loopback enable -assign gig_eth_pcspma_config_vector[0] = 1'b0; // unidirectional enable - -wire [15:0] gig_eth_pcspma_an_config_vector; - -assign gig_eth_pcspma_an_config_vector[15] = 1'b1; // SGMII link status -assign gig_eth_pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge -assign gig_eth_pcspma_an_config_vector[13:12] = 2'b01; // full duplex -assign gig_eth_pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed -assign gig_eth_pcspma_an_config_vector[9] = 1'b0; // reserved -assign gig_eth_pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved -assign gig_eth_pcspma_an_config_vector[6] = 1'b0; // reserved -assign gig_eth_pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved -assign gig_eth_pcspma_an_config_vector[4:1] = 4'b0000; // reserved -assign gig_eth_pcspma_an_config_vector[0] = 1'b1; // SGMII - -gig_ethernet_pcs_pma_0 -eth_pcspma ( - // SGMII - .txp_0 (phy_sgmii_tx_p), - .txn_0 (phy_sgmii_tx_n), - .rxp_0 (phy_sgmii_rx_p), - .rxn_0 (phy_sgmii_rx_n), - - // Ref clock from PHY - .refclk625_p (phy_sgmii_clk_p), - .refclk625_n (phy_sgmii_clk_n), - - // async reset - .reset (rst_125mhz_int), - - // clock and reset outputs - .clk125_out (phy_gmii_clk_int), - .clk312_out (), - .rst_125_out (phy_gmii_rst_int), - .tx_logic_reset (), - .rx_logic_reset (), - .tx_locked (), - .rx_locked (), - .tx_pll_clk_out (), - .rx_pll_clk_out (), - - // MAC clocking - .sgmii_clk_r_0 (), - .sgmii_clk_f_0 (), - .sgmii_clk_en_0 (phy_gmii_clk_en_int), - - // Speed control - .speed_is_10_100_0 (gig_eth_pcspma_status_speed != 2'b10), - .speed_is_100_0 (gig_eth_pcspma_status_speed == 2'b01), - - // Internal GMII - .gmii_txd_0 (phy_gmii_txd_int), - .gmii_tx_en_0 (phy_gmii_tx_en_int), - .gmii_tx_er_0 (phy_gmii_tx_er_int), - .gmii_rxd_0 (phy_gmii_rxd_int), - .gmii_rx_dv_0 (phy_gmii_rx_dv_int), - .gmii_rx_er_0 (phy_gmii_rx_er_int), - .gmii_isolate_0 (), - - // Configuration - .configuration_vector_0 (gig_eth_pcspma_config_vector), - - .an_interrupt_0 (), - .an_adv_config_vector_0 (gig_eth_pcspma_an_config_vector), - .an_restart_config_0 (1'b0), - - // Status - .status_vector_0 (gig_eth_pcspma_status_vector), - .signal_detect_0 (1'b1), - - // Cascade - .tx_bsc_rst_out (), - .rx_bsc_rst_out (), - .tx_bs_rst_out (), - .rx_bs_rst_out (), - .tx_rst_dly_out (), - .rx_rst_dly_out (), - .tx_bsc_en_vtc_out (), - .rx_bsc_en_vtc_out (), - .tx_bs_en_vtc_out (), - .rx_bs_en_vtc_out (), - .riu_clk_out (), - .riu_addr_out (), - .riu_wr_data_out (), - .riu_wr_en_out (), - .riu_nibble_sel_out (), - .riu_rddata_1 (16'b0), - .riu_valid_1 (1'b0), - .riu_prsnt_1 (1'b0), - .riu_rddata_2 (16'b0), - .riu_valid_2 (1'b0), - .riu_prsnt_2 (1'b0), - .riu_rddata_3 (16'b0), - .riu_valid_3 (1'b0), - .riu_prsnt_3 (1'b0), - .rx_btval_1 (), - .rx_btval_2 (), - .rx_btval_3 (), - .tx_dly_rdy_1 (1'b1), - .rx_dly_rdy_1 (1'b1), - .rx_vtc_rdy_1 (1'b1), - .tx_vtc_rdy_1 (1'b1), - .tx_dly_rdy_2 (1'b1), - .rx_dly_rdy_2 (1'b1), - .rx_vtc_rdy_2 (1'b1), - .tx_vtc_rdy_2 (1'b1), - .tx_dly_rdy_3 (1'b1), - .rx_dly_rdy_3 (1'b1), - .rx_vtc_rdy_3 (1'b1), - .tx_vtc_rdy_3 (1'b1), - .tx_rdclk_out () -); - -reg [19:0] delay_reg = 20'hfffff; - -reg [4:0] mdio_cmd_phy_addr = 5'h03; -reg [4:0] mdio_cmd_reg_addr = 5'h00; -reg [15:0] mdio_cmd_data = 16'd0; -reg [1:0] mdio_cmd_opcode = 2'b01; -reg mdio_cmd_valid = 1'b0; -wire mdio_cmd_ready; - -reg [3:0] state_reg = 0; - -always @(posedge clk_125mhz_int) begin - if (rst_125mhz_int) begin - state_reg <= 0; - delay_reg <= 20'hfffff; - mdio_cmd_reg_addr <= 5'h00; - mdio_cmd_data <= 16'd0; - mdio_cmd_valid <= 1'b0; - end else begin - mdio_cmd_valid <= mdio_cmd_valid & !mdio_cmd_ready; - if (delay_reg > 0) begin - delay_reg <= delay_reg - 1; - end else if (!mdio_cmd_ready) begin - // wait for ready - state_reg <= state_reg; - end else begin - mdio_cmd_valid <= 1'b0; - case (state_reg) - // set SGMII autonegotiation timer to 11 ms - // write 0x0070 to CFG4 (0x0031) - 4'd0: begin - // write to REGCR to load address - mdio_cmd_reg_addr <= 5'h0D; - mdio_cmd_data <= 16'h001F; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd1; - end - 4'd1: begin - // write address of CFG4 to ADDAR - mdio_cmd_reg_addr <= 5'h0E; - mdio_cmd_data <= 16'h0031; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd2; - end - 4'd2: begin - // write to REGCR to load data - mdio_cmd_reg_addr <= 5'h0D; - mdio_cmd_data <= 16'h401F; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd3; - end - 4'd3: begin - // write data for CFG4 to ADDAR - mdio_cmd_reg_addr <= 5'h0E; - mdio_cmd_data <= 16'h0070; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd4; - end - // enable SGMII clock output - // write 0x4000 to SGMIICTL1 (0x00D3) - 4'd4: begin - // write to REGCR to load address - mdio_cmd_reg_addr <= 5'h0D; - mdio_cmd_data <= 16'h001F; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd5; - end - 4'd5: begin - // write address of SGMIICTL1 to ADDAR - mdio_cmd_reg_addr <= 5'h0E; - mdio_cmd_data <= 16'h00D3; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd6; - end - 4'd6: begin - // write to REGCR to load data - mdio_cmd_reg_addr <= 5'h0D; - mdio_cmd_data <= 16'h401F; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd7; - end - 4'd7: begin - // write data for SGMIICTL1 to ADDAR - mdio_cmd_reg_addr <= 5'h0E; - mdio_cmd_data <= 16'h4000; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd8; - end - // enable 10Mbps operation - // write 0x0015 to 10M_SGMII_CFG (0x016F) - 4'd8: begin - // write to REGCR to load address - mdio_cmd_reg_addr <= 5'h0D; - mdio_cmd_data <= 16'h001F; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd9; - end - 4'd9: begin - // write address of 10M_SGMII_CFG to ADDAR - mdio_cmd_reg_addr <= 5'h0E; - mdio_cmd_data <= 16'h016F; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd10; - end - 4'd10: begin - // write to REGCR to load data - mdio_cmd_reg_addr <= 5'h0D; - mdio_cmd_data <= 16'h401F; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd11; - end - 4'd11: begin - // write data for 10M_SGMII_CFG to ADDAR - mdio_cmd_reg_addr <= 5'h0E; - mdio_cmd_data <= 16'h0015; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd12; - end - 4'd12: begin - // done - state_reg <= 4'd12; - end - endcase - end - end -end - -wire mdc; -wire mdio_i; -wire mdio_o; -wire mdio_t; - -mdio_master -mdio_master_inst ( - .clk(clk_125mhz_int), - .rst(rst_125mhz_int), - - .cmd_phy_addr(mdio_cmd_phy_addr), - .cmd_reg_addr(mdio_cmd_reg_addr), - .cmd_data(mdio_cmd_data), - .cmd_opcode(mdio_cmd_opcode), - .cmd_valid(mdio_cmd_valid), - .cmd_ready(mdio_cmd_ready), - - .data_out(), - .data_out_valid(), - .data_out_ready(1'b1), - - .mdc_o(mdc), - .mdio_i(mdio_i), - .mdio_o(mdio_o), - .mdio_t(mdio_t), - - .busy(), - - .prescale(8'd3) -); - -assign phy_mdc = mdc; -assign mdio_i = phy_mdio; -assign phy_mdio = mdio_t ? 1'bz : mdio_o; - -wire [7:0] led_int; - -assign led[0] = sw[0] ? qsfp1_rx_block_lock_1 : led_int[0]; -assign led[1] = sw[0] ? qsfp1_rx_block_lock_2 : led_int[1]; -assign led[2] = sw[0] ? qsfp1_rx_block_lock_3 : led_int[2]; -assign led[3] = sw[0] ? qsfp1_rx_block_lock_4 : led_int[3]; -assign led[4] = sw[0] ? qsfp2_rx_block_lock_1 : led_int[4]; -assign led[5] = sw[0] ? qsfp2_rx_block_lock_2 : led_int[5]; -assign led[6] = sw[0] ? qsfp2_rx_block_lock_3 : led_int[6]; -assign led[7] = sw[0] ? qsfp2_rx_block_lock_4 : led_int[7]; - -fpga_core -core_inst ( - /* - * Clock: 156.25 MHz - * Synchronous reset - */ - .clk(clk_156mhz_int), - .rst(rst_156mhz_int), - /* - * GPIO - */ - .btnu(btnu_int), - .btnl(btnl_int), - .btnd(btnd_int), - .btnr(btnr_int), - .btnc(btnc_int), - .sw(sw_int), - .led(led_int), - /* - * Ethernet: QSFP28 - */ - .qsfp1_tx_clk_1(qsfp1_tx_clk_1_int), - .qsfp1_tx_rst_1(qsfp1_tx_rst_1_int), - .qsfp1_txd_1(qsfp1_txd_1_int), - .qsfp1_txc_1(qsfp1_txc_1_int), - .qsfp1_rx_clk_1(qsfp1_rx_clk_1_int), - .qsfp1_rx_rst_1(qsfp1_rx_rst_1_int), - .qsfp1_rxd_1(qsfp1_rxd_1_int), - .qsfp1_rxc_1(qsfp1_rxc_1_int), - .qsfp1_tx_clk_2(qsfp1_tx_clk_2_int), - .qsfp1_tx_rst_2(qsfp1_tx_rst_2_int), - .qsfp1_txd_2(qsfp1_txd_2_int), - .qsfp1_txc_2(qsfp1_txc_2_int), - .qsfp1_rx_clk_2(qsfp1_rx_clk_2_int), - .qsfp1_rx_rst_2(qsfp1_rx_rst_2_int), - .qsfp1_rxd_2(qsfp1_rxd_2_int), - .qsfp1_rxc_2(qsfp1_rxc_2_int), - .qsfp1_tx_clk_3(qsfp1_tx_clk_3_int), - .qsfp1_tx_rst_3(qsfp1_tx_rst_3_int), - .qsfp1_txd_3(qsfp1_txd_3_int), - .qsfp1_txc_3(qsfp1_txc_3_int), - .qsfp1_rx_clk_3(qsfp1_rx_clk_3_int), - .qsfp1_rx_rst_3(qsfp1_rx_rst_3_int), - .qsfp1_rxd_3(qsfp1_rxd_3_int), - .qsfp1_rxc_3(qsfp1_rxc_3_int), - .qsfp1_tx_clk_4(qsfp1_tx_clk_4_int), - .qsfp1_tx_rst_4(qsfp1_tx_rst_4_int), - .qsfp1_txd_4(qsfp1_txd_4_int), - .qsfp1_txc_4(qsfp1_txc_4_int), - .qsfp1_rx_clk_4(qsfp1_rx_clk_4_int), - .qsfp1_rx_rst_4(qsfp1_rx_rst_4_int), - .qsfp1_rxd_4(qsfp1_rxd_4_int), - .qsfp1_rxc_4(qsfp1_rxc_4_int), - .qsfp2_tx_clk_1(qsfp2_tx_clk_1_int), - .qsfp2_tx_rst_1(qsfp2_tx_rst_1_int), - .qsfp2_txd_1(qsfp2_txd_1_int), - .qsfp2_txc_1(qsfp2_txc_1_int), - .qsfp2_rx_clk_1(qsfp2_rx_clk_1_int), - .qsfp2_rx_rst_1(qsfp2_rx_rst_1_int), - .qsfp2_rxd_1(qsfp2_rxd_1_int), - .qsfp2_rxc_1(qsfp2_rxc_1_int), - .qsfp2_tx_clk_2(qsfp2_tx_clk_2_int), - .qsfp2_tx_rst_2(qsfp2_tx_rst_2_int), - .qsfp2_txd_2(qsfp2_txd_2_int), - .qsfp2_txc_2(qsfp2_txc_2_int), - .qsfp2_rx_clk_2(qsfp2_rx_clk_2_int), - .qsfp2_rx_rst_2(qsfp2_rx_rst_2_int), - .qsfp2_rxd_2(qsfp2_rxd_2_int), - .qsfp2_rxc_2(qsfp2_rxc_2_int), - .qsfp2_tx_clk_3(qsfp2_tx_clk_3_int), - .qsfp2_tx_rst_3(qsfp2_tx_rst_3_int), - .qsfp2_txd_3(qsfp2_txd_3_int), - .qsfp2_txc_3(qsfp2_txc_3_int), - .qsfp2_rx_clk_3(qsfp2_rx_clk_3_int), - .qsfp2_rx_rst_3(qsfp2_rx_rst_3_int), - .qsfp2_rxd_3(qsfp2_rxd_3_int), - .qsfp2_rxc_3(qsfp2_rxc_3_int), - .qsfp2_tx_clk_4(qsfp2_tx_clk_4_int), - .qsfp2_tx_rst_4(qsfp2_tx_rst_4_int), - .qsfp2_txd_4(qsfp2_txd_4_int), - .qsfp2_txc_4(qsfp2_txc_4_int), - .qsfp2_rx_clk_4(qsfp2_rx_clk_4_int), - .qsfp2_rx_rst_4(qsfp2_rx_rst_4_int), - .qsfp2_rxd_4(qsfp2_rxd_4_int), - .qsfp2_rxc_4(qsfp2_rxc_4_int), - /* - * Ethernet: 1000BASE-T SGMII - */ - .phy_gmii_clk(phy_gmii_clk_int), - .phy_gmii_rst(phy_gmii_rst_int), - .phy_gmii_clk_en(phy_gmii_clk_en_int), - .phy_gmii_rxd(phy_gmii_rxd_int), - .phy_gmii_rx_dv(phy_gmii_rx_dv_int), - .phy_gmii_rx_er(phy_gmii_rx_er_int), - .phy_gmii_txd(phy_gmii_txd_int), - .phy_gmii_tx_en(phy_gmii_tx_en_int), - .phy_gmii_tx_er(phy_gmii_tx_er_int), - .phy_reset_n(phy_reset_n), - .phy_int_n(phy_int_n), - /* - * UART: 115200 bps, 8N1 - */ - .uart_rxd(uart_rxd_int), - .uart_txd(uart_txd), - .uart_rts(uart_rts), - .uart_cts(uart_cts_int) -); - -endmodule - -`resetall diff --git a/fpga/lib/eth/example/VCU118/fpga_1g/common/vivado.mk b/fpga/lib/eth/example/VCU118/fpga_1g/common/vivado.mk index 21e6a5fed..1402e2382 100644 --- a/fpga/lib/eth/example/VCU118/fpga_1g/common/vivado.mk +++ b/fpga/lib/eth/example/VCU118/fpga_1g/common/vivado.mk @@ -28,7 +28,7 @@ ################################################################### # phony targets -.PHONY: clean fpga +.PHONY: fpga vivado tmpclean clean distclean # prevent make from deleting intermediate files and reports .PRECIOUS: %.xpr %.bit %.mcs %.prm @@ -40,15 +40,16 @@ CONFIG ?= config.mk FPGA_TOP ?= fpga PROJECT ?= $(FPGA_TOP) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else - XDC_FILES_REL = $(FPGA_TOP).xdc + XDC_FILES_REL = $(PROJECT).xdc endif ################################################################### @@ -60,20 +61,20 @@ endif all: fpga -fpga: $(FPGA_TOP).bit +fpga: $(PROJECT).bit -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr -tmpclean: +tmpclean:: -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt -distclean: clean +distclean:: clean -rm -rf rev ################################################################### @@ -91,12 +92,17 @@ create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done -$(PROJECT).xpr: create_project.tcl +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) # synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr echo "open_project $(PROJECT).xpr" > run_synth.tcl echo "reset_run synth_1" >> run_synth.tcl echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl diff --git a/fpga/lib/eth/example/VCU118/fpga_1g/fpga.xdc b/fpga/lib/eth/example/VCU118/fpga_1g/fpga.xdc index 2e8d1d897..3b1fd2272 100644 --- a/fpga/lib/eth/example/VCU118/fpga_1g/fpga.xdc +++ b/fpga/lib/eth/example/VCU118/fpga_1g/fpga.xdc @@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # System clocks # 300 MHz @@ -289,6 +290,667 @@ set_input_delay 0 [get_ports {phy_int_n phy_mdio}] #set_false_path -from [get_ports {pcie_reset_n}] #set_input_delay 0 [get_ports {pcie_reset_n}] +# FMC+ HSPC J22 +#set_property -dict {LOC AL35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[0]}] ;# J22.G9 LA00_P_CC +#set_property -dict {LOC AL36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[0]}] ;# J22.G10 LA00_N_CC +#set_property -dict {LOC AL30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[1]}] ;# J22.D8 LA01_P_CC +#set_property -dict {LOC AL31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[1]}] ;# J22.D9 LA01_N_CC +#set_property -dict {LOC AJ32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[2]}] ;# J22.H7 LA02_P +#set_property -dict {LOC AK32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[2]}] ;# J22.H8 LA02_N +#set_property -dict {LOC AT39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[3]}] ;# J22.G12 LA03_P +#set_property -dict {LOC AT40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[3]}] ;# J22.G13 LA03_N +#set_property -dict {LOC AR37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[4]}] ;# J22.H10 LA04_P +#set_property -dict {LOC AT37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[4]}] ;# J22.H11 LA04_N +#set_property -dict {LOC AP38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[5]}] ;# J22.D11 LA05_P +#set_property -dict {LOC AR38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[5]}] ;# J22.D12 LA05_N +#set_property -dict {LOC AT35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[6]}] ;# J22.C10 LA06_P +#set_property -dict {LOC AT36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[6]}] ;# J22.C11 LA06_N +#set_property -dict {LOC AP36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[7]}] ;# J22.H13 LA07_P +#set_property -dict {LOC AP37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[7]}] ;# J22.H14 LA07_N +#set_property -dict {LOC AK29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[8]}] ;# J22.G12 LA08_P +#set_property -dict {LOC AK30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[8]}] ;# J22.G13 LA08_N +#set_property -dict {LOC AJ33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[9]}] ;# J22.D14 LA09_P +#set_property -dict {LOC AK33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[9]}] ;# J22.D15 LA09_N +#set_property -dict {LOC AP35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[10]}] ;# J22.C14 LA10_P +#set_property -dict {LOC AR35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[10]}] ;# J22.C15 LA10_N +#set_property -dict {LOC AJ30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[11]}] ;# J22.H16 LA11_P +#set_property -dict {LOC AJ31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[11]}] ;# J22.H17 LA11_N +#set_property -dict {LOC AH33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[12]}] ;# J22.G15 LA12_P +#set_property -dict {LOC AH34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[12]}] ;# J22.G16 LA12_N +#set_property -dict {LOC AJ35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[13]}] ;# J22.D17 LA13_P +#set_property -dict {LOC AJ36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[13]}] ;# J22.D18 LA13_N +#set_property -dict {LOC AG31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[14]}] ;# J22.C18 LA14_P +#set_property -dict {LOC AH31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[14]}] ;# J22.C19 LA14_N +#set_property -dict {LOC AG32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[15]}] ;# J22.H19 LA15_P +#set_property -dict {LOC AG33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[15]}] ;# J22.H20 LA15_N +#set_property -dict {LOC AG34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[16]}] ;# J22.G18 LA16_P +#set_property -dict {LOC AH35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[16]}] ;# J22.G19 LA16_N +#set_property -dict {LOC R34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[17]}] ;# J22.D20 LA17_P_CC +#set_property -dict {LOC P34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[17]}] ;# J22.D21 LA17_N_CC +#set_property -dict {LOC R31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[18]}] ;# J22.C22 LA18_P_CC +#set_property -dict {LOC P31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[18]}] ;# J22.C23 LA18_N_CC +#set_property -dict {LOC N33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[19]}] ;# J22.H22 LA19_P +#set_property -dict {LOC M33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[19]}] ;# J22.H23 LA19_N +#set_property -dict {LOC N32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[20]}] ;# J22.G21 LA20_P +#set_property -dict {LOC M32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[20]}] ;# J22.G22 LA20_N +#set_property -dict {LOC M35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[21]}] ;# J22.H25 LA21_P +#set_property -dict {LOC L35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[21]}] ;# J22.H26 LA21_N +#set_property -dict {LOC N34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[22]}] ;# J22.G24 LA22_P +#set_property -dict {LOC N35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[22]}] ;# J22.G25 LA22_N +#set_property -dict {LOC Y32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[23]}] ;# J22.D23 LA23_P +#set_property -dict {LOC W32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[23]}] ;# J22.D24 LA23_N +#set_property -dict {LOC T34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[24]}] ;# J22.H28 LA24_P +#set_property -dict {LOC T35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[24]}] ;# J22.H29 LA24_N +#set_property -dict {LOC Y34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[25]}] ;# J22.G27 LA25_P +#set_property -dict {LOC W34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[25]}] ;# J22.G28 LA25_N +#set_property -dict {LOC V32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[26]}] ;# J22.D26 LA26_P +#set_property -dict {LOC U33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[26]}] ;# J22.D27 LA26_N +#set_property -dict {LOC V33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[27]}] ;# J22.C26 LA27_P +#set_property -dict {LOC V34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[27]}] ;# J22.C27 LA27_N +#set_property -dict {LOC M36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[28]}] ;# J22.H31 LA28_P +#set_property -dict {LOC L36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[28]}] ;# J22.H32 LA28_N +#set_property -dict {LOC U35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[29]}] ;# J22.G30 LA29_P +#set_property -dict {LOC T36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[29]}] ;# J22.G31 LA29_N +#set_property -dict {LOC N38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[30]}] ;# J22.H34 LA30_P +#set_property -dict {LOC M38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[30]}] ;# J22.H35 LA30_N +#set_property -dict {LOC P37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[31]}] ;# J22.G33 LA31_P +#set_property -dict {LOC N37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[31]}] ;# J22.G34 LA31_N +#set_property -dict {LOC L33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[32]}] ;# J22.H37 LA32_P +#set_property -dict {LOC K33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[32]}] ;# J22.H38 LA32_N +#set_property -dict {LOC L34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[33]}] ;# J22.G36 LA33_P +#set_property -dict {LOC K34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[33]}] ;# J22.G37 LA33_N + +#set_property -dict {LOC N14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[0]}] ;# J22.F4 HA00_P_CC +#set_property -dict {LOC N13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[0]}] ;# J22.F5 HA00_N_CC +#set_property -dict {LOC V15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[1]}] ;# J22.E2 HA01_P_CC +#set_property -dict {LOC U15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[1]}] ;# J22.E3 HA01_N_CC +#set_property -dict {LOC AA12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[2]}] ;# J22.K7 HA02_P +#set_property -dict {LOC Y12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[2]}] ;# J22.K8 HA02_N +#set_property -dict {LOC W12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[3]}] ;# J22.J6 HA03_P +#set_property -dict {LOC V12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[3]}] ;# J22.J7 HA03_N +#set_property -dict {LOC AA13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[4]}] ;# J22.F7 HA04_P +#set_property -dict {LOC Y13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[4]}] ;# J22.F8 HA04_N +#set_property -dict {LOC R14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[5]}] ;# J22.E6 HA05_P +#set_property -dict {LOC P14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[5]}] ;# J22.E7 HA05_N +#set_property -dict {LOC U13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[6]}] ;# J22.K10 HA06_P +#set_property -dict {LOC T13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[6]}] ;# J22.K11 HA06_N +#set_property -dict {LOC AA14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[7]}] ;# J22.J9 HA07_P +#set_property -dict {LOC Y14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[7]}] ;# J22.J10 HA07_N +#set_property -dict {LOC U11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[8]}] ;# J22.F10 HA08_P +#set_property -dict {LOC T11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[8]}] ;# J22.F11 HA08_N +#set_property -dict {LOC W14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[9]}] ;# J22.E9 HA09_P +#set_property -dict {LOC V14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[9]}] ;# J22.E10 HA09_N +#set_property -dict {LOC V16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[10]}] ;# J22.K13 HA10_P +#set_property -dict {LOC U16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[10]}] ;# J22.K14 HA10_N +#set_property -dict {LOC R12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[11]}] ;# J22.J12 HA11_P +#set_property -dict {LOC P12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[11]}] ;# J22.J13 HA11_N +#set_property -dict {LOC T16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[12]}] ;# J22.F13 HA12_P +#set_property -dict {LOC T15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[12]}] ;# J22.F14 HA12_N +#set_property -dict {LOC V13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[13]}] ;# J22.E12 HA13_P +#set_property -dict {LOC U12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[13]}] ;# J22.E13 HA13_N +#set_property -dict {LOC M11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[14]}] ;# J22.J15 HA14_P +#set_property -dict {LOC L11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[14]}] ;# J22.J16 HA14_N +#set_property -dict {LOC M13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[15]}] ;# J22.F14 HA15_P +#set_property -dict {LOC M12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[15]}] ;# J22.F16 HA15_N +#set_property -dict {LOC T14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[16]}] ;# J22.E15 HA16_P +#set_property -dict {LOC R13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[16]}] ;# J22.E16 HA16_N +#set_property -dict {LOC R11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[17]}] ;# J22.K16 HA17_P_CC +#set_property -dict {LOC P11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[17]}] ;# J22.K17 HA17_N_CC +#set_property -dict {LOC P15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[18]}] ;# J22.J18 HA18_P_CC +#set_property -dict {LOC N15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[18]}] ;# J22.J19 HA18_N_CC +#set_property -dict {LOC L14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[19]}] ;# J22.F19 HA19_P +#set_property -dict {LOC L13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[19]}] ;# J22.F20 HA19_N +#set_property -dict {LOC M15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[20]}] ;# J22.E18 HA20_P +#set_property -dict {LOC L15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[20]}] ;# J22.E19 HA20_N +#set_property -dict {LOC K14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[21]}] ;# J22.K19 HA21_P +#set_property -dict {LOC K13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[21]}] ;# J22.K20 HA21_N +#set_property -dict {LOC K12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[22]}] ;# J22.J21 HA22_P +#set_property -dict {LOC J12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[22]}] ;# J22.J22 HA22_N +#set_property -dict {LOC K11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[23]}] ;# J22.K22 HA23_P +#set_property -dict {LOC J11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[23]}] ;# J22.K23 HA23_N + +#set_property -dict {LOC AL32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_clk0_m2c_p}] ;# J22.H4 CLK0_M2C_P +#set_property -dict {LOC AM32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_clk0_m2c_n}] ;# J22.H5 CLK0_M2C_N +#set_property -dict {LOC P35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_clk1_m2c_p}] ;# J22.G2 CLK1_M2C_P +#set_property -dict {LOC P36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_clk1_m2c_n}] ;# J22.G3 CLK1_M2C_N + +#set_property -dict {LOC AN33 IOSTANDARD LVDS } [get_ports {fmcp_hspc_refclk_c2m_p}] ;# J22.L20 REFCLK_C2M_P +#set_property -dict {LOC AP33 IOSTANDARD LVDS } [get_ports {fmcp_hspc_refclk_c2m_n}] ;# J22.L21 REFCLK_C2M_N +#set_property -dict {LOC AK34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_refclk_m2c_p}] ;# J22.L24 REFCLK_M2C_P +#set_property -dict {LOC AL34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_refclk_m2c_n}] ;# J22.L25 REFCLK_M2C_N +#set_property -dict {LOC AN34 IOSTANDARD LVDS } [get_ports {fmcp_hspc_sync_c2m_p}] ;# J22.L16 SYNC_C2M_P +#set_property -dict {LOC AN35 IOSTANDARD LVDS } [get_ports {fmcp_hspc_sync_c2m_n}] ;# J22.L17 SYNC_C2M_N +#set_property -dict {LOC AM36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_sync_m2c_p}] ;# J22.L28 SYNC_M2C_P +#set_property -dict {LOC AN36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_sync_m2c_n}] ;# J22.L29 SYNC_M2C_N + +#set_property -dict {LOC AL36 IOSTANDARD LVCMOS18} [get_ports {fmcp_hspc_pg_m2c}] ;# J22.F1 PG_M2C +#set_property -dict {LOC AM33 IOSTANDARD LVCMOS18} [get_ports {fmcp_hspc_h_prsnt_m2c_l}] ;# J22.H2 PRSNT_M2C_L +#set_property -dict {LOC AM29 IOSTANDARD LVCMOS18} [get_ports {fmcp_hspc_z_prsnt_m2c_l}] ;# J22.Z1 HSPC_PRSNT_M2C_L + +#set_property -dict {LOC AT42} [get_ports {fmcp_hspc_dp_c2m_p[0]}] ;# MGTYTXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C2 DP0_C2M_P +#set_property -dict {LOC AT43} [get_ports {fmcp_hspc_dp_c2m_n[0]}] ;# MGTYTXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C3 DP0_C2M_N +#set_property -dict {LOC AR45} [get_ports {fmcp_hspc_dp_m2c_p[0]}] ;# MGTYRXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C6 DP0_M2C_P +#set_property -dict {LOC AR46} [get_ports {fmcp_hspc_dp_m2c_n[0]}] ;# MGTYRXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C7 DP0_M2C_N +#set_property -dict {LOC AP42} [get_ports {fmcp_hspc_dp_c2m_p[1]}] ;# MGTYTXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A22 DP1_C2M_P +#set_property -dict {LOC AP43} [get_ports {fmcp_hspc_dp_c2m_n[1]}] ;# MGTYTXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A23 DP1_C2M_N +#set_property -dict {LOC AN45} [get_ports {fmcp_hspc_dp_m2c_p[1]}] ;# MGTYRXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A2 DP1_M2C_P +#set_property -dict {LOC AN46} [get_ports {fmcp_hspc_dp_m2c_n[1]}] ;# MGTYRXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A3 DP1_M2C_N +#set_property -dict {LOC AM42} [get_ports {fmcp_hspc_dp_c2m_p[2]}] ;# MGTYTXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A26 DP2_C2M_P +#set_property -dict {LOC AM43} [get_ports {fmcp_hspc_dp_c2m_n[2]}] ;# MGTYTXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A27 DP2_C2M_N +#set_property -dict {LOC AL45} [get_ports {fmcp_hspc_dp_m2c_p[2]}] ;# MGTYRXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A6 DP2_M2C_P +#set_property -dict {LOC AL46} [get_ports {fmcp_hspc_dp_m2c_n[2]}] ;# MGTYRXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A7 DP2_M2C_N +#set_property -dict {LOC AL40} [get_ports {fmcp_hspc_dp_c2m_p[3]}] ;# MGTYTXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A30 DP3_C2M_P +#set_property -dict {LOC AL41} [get_ports {fmcp_hspc_dp_c2m_n[3]}] ;# MGTYTXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A31 DP3_C2M_N +#set_property -dict {LOC AJ45} [get_ports {fmcp_hspc_dp_m2c_p[3]}] ;# MGTYRXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A10 DP3_M2C_P +#set_property -dict {LOC AJ46} [get_ports {fmcp_hspc_dp_m2c_n[3]}] ;# MGTYRXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A11 DP3_M2C_N +#set_property -dict {LOC AK38} [get_ports fmcp_hspc_mgt_refclk_0_0_p] ;# MGTREFCLK0P_121 from U40.1 Q0 from J22.D4 GBTCLK0_M2C_P +#set_property -dict {LOC AK39} [get_ports fmcp_hspc_mgt_refclk_0_0_n] ;# MGTREFCLK0N_121 from U40.2 NQ0 from J22.D5 GBTCLK0_M2C_N +#set_property -dict {LOC AH38} [get_ports fmcp_hspc_mgt_refclk_0_1_p] ;# MGTREFCLK1P_121 from U39.5 Q0_P from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC AH39} [get_ports fmcp_hspc_mgt_refclk_0_1_n] ;# MGTREFCLK1N_121 from U39.6 Q0_N from J22.B21 GBTCLK1_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_0_0 [get_ports fmcp_hspc_mgt_refclk_0_0_p] +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_0_1 [get_ports fmcp_hspc_mgt_refclk_0_1_p] + +#set_property -dict {LOC T42 } [get_ports {fmcp_hspc_dp_c2m_p[4]}] ;# MGTYTXP0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A34 DP4_C2M_P +#set_property -dict {LOC T43 } [get_ports {fmcp_hspc_dp_c2m_n[4]}] ;# MGTYTXN0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A35 DP4_C2M_N +#set_property -dict {LOC W45 } [get_ports {fmcp_hspc_dp_m2c_p[4]}] ;# MGTYRXP0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A14 DP4_M2C_P +#set_property -dict {LOC W46 } [get_ports {fmcp_hspc_dp_m2c_n[4]}] ;# MGTYRXN0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A15 DP4_M2C_N +#set_property -dict {LOC P42 } [get_ports {fmcp_hspc_dp_c2m_p[5]}] ;# MGTYTXP1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A38 DP5_C2M_P +#set_property -dict {LOC P43 } [get_ports {fmcp_hspc_dp_c2m_n[5]}] ;# MGTYTXN1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A39 DP5_C2M_N +#set_property -dict {LOC U45 } [get_ports {fmcp_hspc_dp_m2c_p[5]}] ;# MGTYRXP1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A18 DP5_M2C_P +#set_property -dict {LOC U46 } [get_ports {fmcp_hspc_dp_m2c_n[5]}] ;# MGTYRXN1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A19 DP5_M2C_N +#set_property -dict {LOC M42 } [get_ports {fmcp_hspc_dp_c2m_p[6]}] ;# MGTYTXP2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B36 DP6_C2M_P +#set_property -dict {LOC M43 } [get_ports {fmcp_hspc_dp_c2m_n[6]}] ;# MGTYTXN2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B37 DP6_C2M_N +#set_property -dict {LOC R45 } [get_ports {fmcp_hspc_dp_m2c_p[6]}] ;# MGTYRXP2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B16 DP6_M2C_P +#set_property -dict {LOC R46 } [get_ports {fmcp_hspc_dp_m2c_n[6]}] ;# MGTYRXN2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B17 DP6_M2C_N +#set_property -dict {LOC K42 } [get_ports {fmcp_hspc_dp_c2m_p[7]}] ;# MGTYTXP3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B32 DP7_C2M_P +#set_property -dict {LOC K43 } [get_ports {fmcp_hspc_dp_c2m_n[7]}] ;# MGTYTXN3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B33 DP7_C2M_N +#set_property -dict {LOC N45 } [get_ports {fmcp_hspc_dp_m2c_p[7]}] ;# MGTYRXP3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B12 DP7_M2C_P +#set_property -dict {LOC N46 } [get_ports {fmcp_hspc_dp_m2c_n[7]}] ;# MGTYRXN3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B13 DP7_M2C_N +#set_property -dict {LOC V38 } [get_ports fmcp_hspc_mgt_refclk_1_0_p] ;# MGTREFCLK0P_126 from U40.3 Q1 from J22.D4 GBTCLK0_M2C_P +#set_property -dict {LOC V39 } [get_ports fmcp_hspc_mgt_refclk_1_0_n] ;# MGTREFCLK0N_126 from U40.4 NQ1 from J22.D5 GBTCLK0_M2C_N +#set_property -dict {LOC T38 } [get_ports fmcp_hspc_mgt_refclk_1_1_p] ;# MGTREFCLK1P_126 from U39.8 Q1_P from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC T39 } [get_ports fmcp_hspc_mgt_refclk_1_1_n] ;# MGTREFCLK1N_126 from U39.9 Q1_N from J22.B21 GBTCLK1_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_1_0 [get_ports fmcp_hspc_mgt_refclk_1_0_p] +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_1_1 [get_ports fmcp_hspc_mgt_refclk_1_1_p] + +#set_property -dict {LOC AK42} [get_ports {fmcp_hspc_dp_c2m_p[8]}] ;# MGTYTXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B28 DP8_C2M_P +#set_property -dict {LOC AK43} [get_ports {fmcp_hspc_dp_c2m_n[8]}] ;# MGTYTXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B29 DP8_C2M_N +#set_property -dict {LOC AG45} [get_ports {fmcp_hspc_dp_m2c_p[8]}] ;# MGTYRXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B8 DP8_M2C_P +#set_property -dict {LOC AG46} [get_ports {fmcp_hspc_dp_m2c_n[8]}] ;# MGTYRXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B9 DP8_M2C_N +#set_property -dict {LOC AJ40} [get_ports {fmcp_hspc_dp_c2m_p[9]}] ;# MGTYTXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B24 DP9_C2M_P +#set_property -dict {LOC AJ41} [get_ports {fmcp_hspc_dp_c2m_n[9]}] ;# MGTYTXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B25 DP9_C2M_N +#set_property -dict {LOC AF43} [get_ports {fmcp_hspc_dp_m2c_p[9]}] ;# MGTYRXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B4 DP9_M2C_P +#set_property -dict {LOC AF44} [get_ports {fmcp_hspc_dp_m2c_n[9]}] ;# MGTYRXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B5 DP9_M2C_N +#set_property -dict {LOC AG40} [get_ports {fmcp_hspc_dp_c2m_p[10]}] ;# MGTYTXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Z24 DP10_C2M_P +#set_property -dict {LOC AG41} [get_ports {fmcp_hspc_dp_c2m_n[10]}] ;# MGTYTXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Z25 DP10_C2M_N +#set_property -dict {LOC AE45} [get_ports {fmcp_hspc_dp_m2c_p[10]}] ;# MGTYRXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Y10 DP10_M2C_P +#set_property -dict {LOC AE46} [get_ports {fmcp_hspc_dp_m2c_n[10]}] ;# MGTYRXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Y11 DP10_M2C_N +#set_property -dict {LOC AE40} [get_ports {fmcp_hspc_dp_c2m_p[11]}] ;# MGTYTXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Y26 DP11_C2M_P +#set_property -dict {LOC AE41} [get_ports {fmcp_hspc_dp_c2m_n[11]}] ;# MGTYTXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Y27 DP11_C2M_N +#set_property -dict {LOC AD43} [get_ports {fmcp_hspc_dp_m2c_p[11]}] ;# MGTYRXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Z12 DP11_M2C_P +#set_property -dict {LOC AD44} [get_ports {fmcp_hspc_dp_m2c_n[11]}] ;# MGTYRXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Z13 DP11_M2C_N +#set_property -dict {LOC AF38} [get_ports fmcp_hspc_mgt_refclk_2_0_p] ;# MGTREFCLK0P_122 from J22.L12 GBTCLK2_M2C_P +#set_property -dict {LOC AF39} [get_ports fmcp_hspc_mgt_refclk_2_0_n] ;# MGTREFCLK0N_122 from J22.L13 GBTCLK2_M2C_N +#set_property -dict {LOC AD38} [get_ports fmcp_hspc_mgt_refclk_2_1_p] ;# MGTREFCLK1P_122 from U39.11 Q2_P from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC AD39} [get_ports fmcp_hspc_mgt_refclk_2_1_n] ;# MGTREFCLK1N_122 from U39.12 Q2_N from J22.B21 GBTCLK1_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_2_0 [get_ports fmcp_hspc_mgt_refclk_2_0_p] +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_2_1 [get_ports fmcp_hspc_mgt_refclk_2_1_p] + +#set_property -dict {LOC AC40} [get_ports {fmcp_hspc_dp_c2m_p[12]}] ;# MGTYTXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Z28 DP12_C2M_P +#set_property -dict {LOC AC41} [get_ports {fmcp_hspc_dp_c2m_n[12]}] ;# MGTYTXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Z29 DP12_C2M_N +#set_property -dict {LOC AC45} [get_ports {fmcp_hspc_dp_m2c_p[12]}] ;# MGTYRXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Y14 DP12_M2C_P +#set_property -dict {LOC AC46} [get_ports {fmcp_hspc_dp_m2c_n[12]}] ;# MGTYRXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Y15 DP12_M2C_N +#set_property -dict {LOC AA40} [get_ports {fmcp_hspc_dp_c2m_p[13]}] ;# MGTYTXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Y30 DP13_C2M_P +#set_property -dict {LOC AA41} [get_ports {fmcp_hspc_dp_c2m_n[13]}] ;# MGTYTXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Y31 DP13_C2M_N +#set_property -dict {LOC AB43} [get_ports {fmcp_hspc_dp_m2c_p[13]}] ;# MGTYRXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Z16 DP13_M2C_P +#set_property -dict {LOC AB44} [get_ports {fmcp_hspc_dp_m2c_n[13]}] ;# MGTYRXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Z17 DP13_M2C_N +#set_property -dict {LOC W40 } [get_ports {fmcp_hspc_dp_c2m_p[14]}] ;# MGTYTXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.M18 DP14_C2M_P +#set_property -dict {LOC W41 } [get_ports {fmcp_hspc_dp_c2m_n[14]}] ;# MGTYTXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.M19 DP14_C2M_N +#set_property -dict {LOC AA45} [get_ports {fmcp_hspc_dp_m2c_p[14]}] ;# MGTYRXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.Y18 DP14_M2C_P +#set_property -dict {LOC AA46} [get_ports {fmcp_hspc_dp_m2c_n[14]}] ;# MGTYRXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.Y19 DP14_M2C_N +#set_property -dict {LOC U40 } [get_ports {fmcp_hspc_dp_c2m_p[15]}] ;# MGTYTXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.M22 DP15_C2M_P +#set_property -dict {LOC U41 } [get_ports {fmcp_hspc_dp_c2m_n[15]}] ;# MGTYTXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.M23 DP15_C2M_N +#set_property -dict {LOC Y43 } [get_ports {fmcp_hspc_dp_m2c_p[15]}] ;# MGTYRXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.Y22 DP15_M2C_P +#set_property -dict {LOC Y44 } [get_ports {fmcp_hspc_dp_m2c_n[15]}] ;# MGTYRXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.Y23 DP15_M2C_N +#set_property -dict {LOC AB38} [get_ports fmcp_hspc_mgt_refclk_3_0_p] ;# MGTREFCLK0P_125 from J22.L8 GBTCLK3_M2C_P +#set_property -dict {LOC AB39} [get_ports fmcp_hspc_mgt_refclk_3_0_n] ;# MGTREFCLK0N_125 from J22.L9 GBTCLK3_M2C_N +#set_property -dict {LOC Y38 } [get_ports fmcp_hspc_mgt_refclk_3_1_p] ;# MGTREFCLK1P_125 from U39.13 Q3_P from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC Y39 } [get_ports fmcp_hspc_mgt_refclk_3_1_n] ;# MGTREFCLK1N_125 from U39.14 Q3_N from J22.B21 GBTCLK1_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_3_0 [get_ports fmcp_hspc_mgt_refclk_3_0_p] +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_3_1 [get_ports fmcp_hspc_mgt_refclk_3_1_p] + +#set_property -dict {LOC H42 } [get_ports {fmcp_hspc_dp_c2m_p[16]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.M26 DP16_C2M_P +#set_property -dict {LOC H43 } [get_ports {fmcp_hspc_dp_c2m_n[16]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.M27 DP16_C2M_N +#set_property -dict {LOC L45 } [get_ports {fmcp_hspc_dp_m2c_p[16]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.Z32 DP16_M2C_P +#set_property -dict {LOC L46 } [get_ports {fmcp_hspc_dp_m2c_n[16]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.Z33 DP16_M2C_N +#set_property -dict {LOC F42 } [get_ports {fmcp_hspc_dp_c2m_p[17]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.M30 DP17_C2M_P +#set_property -dict {LOC F43 } [get_ports {fmcp_hspc_dp_c2m_n[17]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.M31 DP17_C2M_N +#set_property -dict {LOC J45 } [get_ports {fmcp_hspc_dp_m2c_p[17]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.Y34 DP17_M2C_P +#set_property -dict {LOC J46 } [get_ports {fmcp_hspc_dp_m2c_n[17]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.Y35 DP17_M2C_N +#set_property -dict {LOC D42 } [get_ports {fmcp_hspc_dp_c2m_p[18]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.M34 DP18_C2M_P +#set_property -dict {LOC D43 } [get_ports {fmcp_hspc_dp_c2m_n[18]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.M35 DP18_C2M_N +#set_property -dict {LOC G45 } [get_ports {fmcp_hspc_dp_m2c_p[18]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.Z36 DP18_M2C_P +#set_property -dict {LOC G46 } [get_ports {fmcp_hspc_dp_m2c_n[18]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.Z37 DP18_M2C_N +#set_property -dict {LOC B42 } [get_ports {fmcp_hspc_dp_c2m_p[19]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.M38 DP19_C2M_P +#set_property -dict {LOC B43 } [get_ports {fmcp_hspc_dp_c2m_n[19]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.M39 DP19_C2M_N +#set_property -dict {LOC E45 } [get_ports {fmcp_hspc_dp_m2c_p[19]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.Y38 DP19_M2C_P +#set_property -dict {LOC E46 } [get_ports {fmcp_hspc_dp_m2c_n[19]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.Y39 DP19_M2C_N +#set_property -dict {LOC R40 } [get_ports fmcp_hspc_mgt_refclk_4_0_p] ;# MGTREFCLK0P_127 from J22.L4 GBTCLK4_M2C_P +#set_property -dict {LOC R41 } [get_ports fmcp_hspc_mgt_refclk_4_0_n] ;# MGTREFCLK0N_127 from J22.L5 GBTCLK4_M2C_N +#set_property -dict {LOC N40 } [get_ports fmcp_hspc_mgt_refclk_4_1_p] ;# MGTREFCLK1P_127 from U39.16 Q4_P from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC N41 } [get_ports fmcp_hspc_mgt_refclk_4_1_n] ;# MGTREFCLK1N_127 from U39.17 Q4_N from J22.B21 GBTCLK1_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_4_0 [get_ports fmcp_hspc_mgt_refclk_4_0_p] +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_4_1 [get_ports fmcp_hspc_mgt_refclk_4_1_p] + +#set_property -dict {LOC BD42} [get_ports {fmcp_hspc_dp_c2m_p[20]}] ;# MGTYTXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.Z8 DP20_C2M_P +#set_property -dict {LOC BD43} [get_ports {fmcp_hspc_dp_c2m_n[20]}] ;# MGTYTXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.Z9 DP20_C2M_N +#set_property -dict {LOC BC45} [get_ports {fmcp_hspc_dp_m2c_p[20]}] ;# MGTYRXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.M14 DP20_M2C_P +#set_property -dict {LOC BC46} [get_ports {fmcp_hspc_dp_m2c_n[20]}] ;# MGTYRXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.M15 DP20_M2C_N +#set_property -dict {LOC BB42} [get_ports {fmcp_hspc_dp_c2m_p[21]}] ;# MGTYTXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.Y6 DP21_C2M_P +#set_property -dict {LOC BB43} [get_ports {fmcp_hspc_dp_c2m_n[21]}] ;# MGTYTXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.Y7 DP21_C2M_N +#set_property -dict {LOC BA45} [get_ports {fmcp_hspc_dp_m2c_p[21]}] ;# MGTYRXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.M10 DP21_M2C_P +#set_property -dict {LOC BA46} [get_ports {fmcp_hspc_dp_m2c_n[21]}] ;# MGTYRXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.M11 DP21_M2C_N +#set_property -dict {LOC AY42} [get_ports {fmcp_hspc_dp_c2m_p[22]}] ;# MGTYTXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.Z4 DP22_C2M_P +#set_property -dict {LOC AY43} [get_ports {fmcp_hspc_dp_c2m_n[22]}] ;# MGTYTXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.Z5 DP22_C2M_N +#set_property -dict {LOC AW45} [get_ports {fmcp_hspc_dp_m2c_p[22]}] ;# MGTYRXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.M6 DP22_M2C_P +#set_property -dict {LOC AW46} [get_ports {fmcp_hspc_dp_m2c_n[22]}] ;# MGTYRXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.M7 DP22_M2C_N +#set_property -dict {LOC AV42} [get_ports {fmcp_hspc_dp_c2m_p[23]}] ;# MGTYTXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.Y2 DP23_C2M_P +#set_property -dict {LOC AV43} [get_ports {fmcp_hspc_dp_c2m_n[23]}] ;# MGTYTXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.Y3 DP23_C2M_N +#set_property -dict {LOC AU45} [get_ports {fmcp_hspc_dp_m2c_p[23]}] ;# MGTYRXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.M2 DP23_M2C_P +#set_property -dict {LOC AU46} [get_ports {fmcp_hspc_dp_m2c_n[23]}] ;# MGTYRXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.M3 DP23_M2C_N +#set_property -dict {LOC AN40} [get_ports fmcp_hspc_mgt_refclk_5_0_p] ;# MGTREFCLK0P_120 from J22.Z20 GBTCLK5_M2C_P +#set_property -dict {LOC AN41} [get_ports fmcp_hspc_mgt_refclk_5_0_n] ;# MGTREFCLK0N_120 from J22.Z21 GBTCLK5_M2C_N +#set_property -dict {LOC AM38} [get_ports fmcp_hspc_mgt_refclk_5_1_p] ;# MGTREFCLK1P_120 from U39.19 Q5_P from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC AM39} [get_ports fmcp_hspc_mgt_refclk_5_1_n] ;# MGTREFCLK1N_120 from U39.20 Q5_N from J22.B21 GBTCLK1_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_5_0 [get_ports fmcp_hspc_mgt_refclk_5_0_p] +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_5_1 [get_ports fmcp_hspc_mgt_refclk_5_1_p] + +# FMC HPC1 J2 +#set_property -dict {LOC AY9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[0]}] ;# J2.G9 LA00_P_CC +#set_property -dict {LOC BA9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[0]}] ;# J2.G10 LA00_N_CC +#set_property -dict {LOC BF10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[1]}] ;# J2.D8 LA01_P_CC +#set_property -dict {LOC BF9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[1]}] ;# J2.D9 LA01_N_CC +#set_property -dict {LOC BC11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[2]}] ;# J2.H7 LA02_P +#set_property -dict {LOC BD11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[2]}] ;# J2.H8 LA02_N +#set_property -dict {LOC BD12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[3]}] ;# J2.G12 LA03_P +#set_property -dict {LOC BE12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[3]}] ;# J2.G13 LA03_N +#set_property -dict {LOC BD12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[4]}] ;# J2.H10 LA04_P +#set_property -dict {LOC BF11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[4]}] ;# J2.H11 LA04_N +#set_property -dict {LOC BE14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[5]}] ;# J2.D11 LA05_P +#set_property -dict {LOC BF14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[5]}] ;# J2.D12 LA05_N +#set_property -dict {LOC BD13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[6]}] ;# J2.C10 LA06_P +#set_property -dict {LOC BE13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[6]}] ;# J2.C11 LA06_N +#set_property -dict {LOC BC15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[7]}] ;# J2.H13 LA07_P +#set_property -dict {LOC BD15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[7]}] ;# J2.H14 LA07_N +#set_property -dict {LOC BE15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[8]}] ;# J2.G12 LA08_P +#set_property -dict {LOC BF15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[8]}] ;# J2.G13 LA08_N +#set_property -dict {LOC BA14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[9]}] ;# J2.D14 LA09_P +#set_property -dict {LOC BB14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[9]}] ;# J2.D15 LA09_N +#set_property -dict {LOC BB13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[10]}] ;# J2.C14 LA10_P +#set_property -dict {LOC BB12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[10]}] ;# J2.C15 LA10_N +#set_property -dict {LOC BA16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[11]}] ;# J2.H16 LA11_P +#set_property -dict {LOC BA15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[11]}] ;# J2.H17 LA11_N +#set_property -dict {LOC BC14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[12]}] ;# J2.G15 LA12_P +#set_property -dict {LOC BC13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[12]}] ;# J2.G16 LA12_N +#set_property -dict {LOC AY8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[13]}] ;# J2.D17 LA13_P +#set_property -dict {LOC AY7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[13]}] ;# J2.D18 LA13_N +#set_property -dict {LOC AW8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[14]}] ;# J2.C18 LA14_P +#set_property -dict {LOC AW7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[14]}] ;# J2.C19 LA14_N +#set_property -dict {LOC BB16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[15]}] ;# J2.H19 LA15_P +#set_property -dict {LOC BC16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[15]}] ;# J2.H20 LA15_N +#set_property -dict {LOC AV9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[16]}] ;# J2.G18 LA16_P +#set_property -dict {LOC AB8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[16]}] ;# J2.G19 LA16_N +#set_property -dict {LOC AR14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[17]}] ;# J2.D20 LA17_P_CC +#set_property -dict {LOC AT14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[17]}] ;# J2.D21 LA17_N_CC +#set_property -dict {LOC AP12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[18]}] ;# J2.C22 LA18_P_CC +#set_property -dict {LOC AR12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[18]}] ;# J2.C23 LA18_N_CC +#set_property -dict {LOC AW12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[19]}] ;# J2.H22 LA19_P +#set_property -dict {LOC AY12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[19]}] ;# J2.H23 LA19_N +#set_property -dict {LOC AW11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[20]}] ;# J2.G21 LA20_P +#set_property -dict {LOC AY10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[20]}] ;# J2.G22 LA20_N +#set_property -dict {LOC AU11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[21]}] ;# J2.H25 LA21_P +#set_property -dict {LOC AV11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[21]}] ;# J2.H26 LA21_N +#set_property -dict {LOC AW13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[22]}] ;# J2.G24 LA22_P +#set_property -dict {LOC AY13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[22]}] ;# J2.G25 LA22_N +#set_property -dict {LOC AN16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[23]}] ;# J2.D23 LA23_P +#set_property -dict {LOC AP16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[23]}] ;# J2.D24 LA23_N +#set_property -dict {LOC AP13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[24]}] ;# J2.H28 LA24_P +#set_property -dict {LOC AR13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[24]}] ;# J2.H29 LA24_N +#set_property -dict {LOC AT12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[25]}] ;# J2.G27 LA25_P +#set_property -dict {LOC AU12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[25]}] ;# J2.G28 LA25_N +#set_property -dict {LOC AK15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[26]}] ;# J2.D26 LA26_P +#set_property -dict {LOC AL15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[26]}] ;# J2.D27 LA26_N +#set_property -dict {LOC AL14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[27]}] ;# J2.C26 LA27_P +#set_property -dict {LOC AM14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[27]}] ;# J2.C27 LA27_N +#set_property -dict {LOC AV10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[28]}] ;# J2.H31 LA28_P +#set_property -dict {LOC AW10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[28]}] ;# J2.H32 LA28_N +#set_property -dict {LOC AN15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[29]}] ;# J2.G30 LA29_P +#set_property -dict {LOC AP15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[29]}] ;# J2.G31 LA29_N +#set_property -dict {LOC AK12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[30]}] ;# J2.H34 LA30_P +#set_property -dict {LOC AL12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[30]}] ;# J2.H35 LA30_N +#set_property -dict {LOC AM13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[31]}] ;# J2.G33 LA31_P +#set_property -dict {LOC AM12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[31]}] ;# J2.G34 LA31_N +#set_property -dict {LOC AJ13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[32]}] ;# J2.H37 LA32_P +#set_property -dict {LOC AJ12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[32]}] ;# J2.H38 LA32_N +#set_property -dict {LOC AK14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[33]}] ;# J2.G36 LA33_P +#set_property -dict {LOC AK13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[33]}] ;# J2.G37 LA33_N + +#set_property -dict {LOC BC9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_clk0_m2c_p}] ;# J2.H4 CLK0_M2C_P +#set_property -dict {LOC BC8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_clk0_m2c_n}] ;# J2.H5 CLK0_M2C_N +#set_property -dict {LOC AV14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_clk1_m2c_p}] ;# J2.G2 CLK1_M2C_P +#set_property -dict {LOC AV13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_clk1_m2c_n}] ;# J2.G3 CLK1_M2C_N + +#set_property -dict {LOC BA7 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc1_pg_m2c}] ;# J2.F1 PG_M2C +#set_property -dict {LOC BB7 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc1_prsnt_m2c_l}] ;# J2.H2 PRSNT_M2C_L + +# DDR4 C1 +# 5x MT40A256M16GE-075E +#set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +#set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +#set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +#set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +#set_property -dict {LOC C15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +#set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +#set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +#set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +#set_property -dict {LOC A16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +#set_property -dict {LOC B12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +#set_property -dict {LOC C12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +#set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +#set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +#set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +#set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +#set_property -dict {LOC H15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +#set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +#set_property -dict {LOC G15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +#set_property -dict {LOC G13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +#set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +#set_property -dict {LOC F14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}] +#set_property -dict {LOC E14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}] +#set_property -dict {LOC A10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}] +#set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}] +#set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +#set_property -dict {LOC C8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}] +#set_property -dict {LOC G10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +#set_property -dict {LOC N20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] +#set_property -dict {LOC R17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}] +#set_property -dict {LOC A20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}] + +#set_property -dict {LOC F11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] ;# U60.G2 DQL0 +#set_property -dict {LOC E11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] ;# U60.F7 DQL1 +#set_property -dict {LOC F10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] ;# U60.H3 DQL2 +#set_property -dict {LOC F9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] ;# U60.H7 DQL3 +#set_property -dict {LOC H12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] ;# U60.H2 DQL4 +#set_property -dict {LOC G12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] ;# U60.H8 DQL5 +#set_property -dict {LOC E9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] ;# U60.J3 DQL6 +#set_property -dict {LOC D9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] ;# U60.J7 DQL7 +#set_property -dict {LOC R19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] ;# U60.A3 DQU0 +#set_property -dict {LOC P19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] ;# U60.B8 DQU1 +#set_property -dict {LOC M18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] ;# U60.C3 DQU2 +#set_property -dict {LOC M17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] ;# U60.C7 DQU3 +#set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] ;# U60.C2 DQU4 +#set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] ;# U60.C8 DQU5 +#set_property -dict {LOC N17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] ;# U60.D3 DQU6 +#set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] ;# U60.D7 DQU7 +#set_property -dict {LOC D11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] ;# U60.G3 DQSL_T +#set_property -dict {LOC D10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] ;# U60.F3 DQSL_C +#set_property -dict {LOC P17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] ;# U60.B7 DQSU_T +#set_property -dict {LOC P16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] ;# U60.A7 DQSU_C +#set_property -dict {LOC G11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] ;# U60.E7 DML_B/DBIL_B +#set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] ;# U60.E2 DMU_B/DBIU_B + +#set_property -dict {LOC L16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] ;# U61.G2 DQL0 +#set_property -dict {LOC K16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] ;# U61.F7 DQL1 +#set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] ;# U61.H3 DQL2 +#set_property -dict {LOC K18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] ;# U61.H7 DQL3 +#set_property -dict {LOC J17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] ;# U61.H2 DQL4 +#set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] ;# U61.H8 DQL5 +#set_property -dict {LOC H19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] ;# U61.J3 DQL6 +#set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] ;# U61.J7 DQL7 +#set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] ;# U61.A3 DQU0 +#set_property -dict {LOC F18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] ;# U61.B8 DQU1 +#set_property -dict {LOC E19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] ;# U61.C3 DQU2 +#set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] ;# U61.C7 DQU3 +#set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] ;# U61.C2 DQU4 +#set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] ;# U61.C8 DQU5 +#set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] ;# U61.D3 DQU6 +#set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] ;# U61.D7 DQU7 +#set_property -dict {LOC K19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] ;# U61.G3 DQSL_T +#set_property -dict {LOC J19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] ;# U61.F3 DQSL_C +#set_property -dict {LOC F16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] ;# U61.B7 DQSU_T +#set_property -dict {LOC E16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] ;# U61.A7 DQSU_C +#set_property -dict {LOC K17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] ;# U61.E7 DML_B/DBIL_B +#set_property -dict {LOC G18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] ;# U61.E2 DMU_B/DBIU_B + +#set_property -dict {LOC D17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] ;# U62.G2 DQL0 +#set_property -dict {LOC C17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] ;# U62.F7 DQL1 +#set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] ;# U62.H3 DQL2 +#set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] ;# U62.H7 DQL3 +#set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] ;# U62.H2 DQL4 +#set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] ;# U62.H8 DQL5 +#set_property -dict {LOC C20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] ;# U62.J3 DQL6 +#set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] ;# U62.J7 DQL7 +#set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] ;# U62.A3 DQU0 +#set_property -dict {LOC M23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] ;# U62.B8 DQU1 +#set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] ;# U62.C3 DQU2 +#set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] ;# U62.C7 DQU3 +#set_property -dict {LOC R22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] ;# U62.C2 DQU4 +#set_property -dict {LOC P22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] ;# U62.C8 DQU5 +#set_property -dict {LOC T23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] ;# U62.D3 DQU6 +#set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] ;# U62.D7 DQU7 +#set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] ;# U62.G3 DQSL_T +#set_property -dict {LOC A18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] ;# U62.F3 DQSL_C +#set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] ;# U62.B7 DQSU_T +#set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] ;# U62.A7 DQSU_C +#set_property -dict {LOC B18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] ;# U62.E7 DML_B/DBIL_B +#set_property -dict {LOC P20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] ;# U62.E2 DMU_B/DBIU_B + +#set_property -dict {LOC K24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] ;# U63.G2 DQL0 +#set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] ;# U63.F7 DQL1 +#set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] ;# U63.H3 DQL2 +#set_property -dict {LOC L21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] ;# U63.H7 DQL3 +#set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] ;# U63.H2 DQL4 +#set_property -dict {LOC J21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] ;# U63.H8 DQL5 +#set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] ;# U63.J3 DQL6 +#set_property -dict {LOC J22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] ;# U63.J7 DQL7 +#set_property -dict {LOC H23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] ;# U63.A3 DQU0 +#set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] ;# U63.B8 DQU1 +#set_property -dict {LOC E23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] ;# U63.C3 DQU2 +#set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] ;# U63.C7 DQU3 +#set_property -dict {LOC F21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] ;# U63.C2 DQU4 +#set_property -dict {LOC E21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] ;# U63.C8 DQU5 +#set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] ;# U63.D3 DQU6 +#set_property -dict {LOC F23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] ;# U63.D7 DQU7 +#set_property -dict {LOC M20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] ;# U63.G3 DQSL_T +#set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] ;# U63.F3 DQSL_C +#set_property -dict {LOC H24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] ;# U63.B7 DQSU_T +#set_property -dict {LOC G23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] ;# U63.A7 DQSU_C +#set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] ;# U63.E7 DML_B/DBIL_B +#set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] ;# U63.E2 DMU_B/DBIU_B + +#set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] ;# U64.G2 DQL0 +#set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] ;# U64.F7 DQL1 +#set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] ;# U64.H3 DQL2 +#set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] ;# U64.H7 DQL3 +#set_property -dict {LOC B23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] ;# U64.H2 DQL4 +#set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] ;# U64.H8 DQL5 +#set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] ;# U64.J3 DQL6 +#set_property -dict {LOC A21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] ;# U64.J7 DQL7 +#set_property -dict {LOC D7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[72]}] ;# U64.A3 DQU0 +#set_property -dict {LOC C7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[73]}] ;# U64.B8 DQU1 +#set_property -dict {LOC B8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[74]}] ;# U64.C3 DQU2 +#set_property -dict {LOC B7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[75]}] ;# U64.C7 DQU3 +#set_property -dict {LOC C10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[76]}] ;# U64.C2 DQU4 +#set_property -dict {LOC B10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[77]}] ;# U64.C8 DQU5 +#set_property -dict {LOC B11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[78]}] ;# U64.D3 DQU6 +#set_property -dict {LOC A11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[79]}] ;# U64.D7 DQU7 +#set_property -dict {LOC D22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] ;# U64.G3 DQSL_T +#set_property -dict {LOC C22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] ;# U64.F3 DQSL_C +#set_property -dict {LOC A9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] ;# U64.B7 DQSU_T +#set_property -dict {LOC A8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] ;# U64.A7 DQSU_C +#set_property -dict {LOC E24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}] ;# U64.E7 DML_B/DBIL_B +#set_property -dict {LOC C9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[9]}] ;# U64.E2 DMU_B/DBIU_B + +# DDR4 C2 +# 5x MT40A256M16GE-075E +#set_property -dict {LOC AM27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +#set_property -dict {LOC AL27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +#set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +#set_property -dict {LOC AN28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +#set_property -dict {LOC AM28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +#set_property -dict {LOC AP28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +#set_property -dict {LOC AP27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +#set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +#set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +#set_property -dict {LOC AR28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +#set_property -dict {LOC AR27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +#set_property -dict {LOC AV25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +#set_property -dict {LOC AT25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +#set_property -dict {LOC AV28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +#set_property -dict {LOC AU26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +#set_property -dict {LOC AV26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +#set_property -dict {LOC AR25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +#set_property -dict {LOC AU28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +#set_property -dict {LOC AU27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +#set_property -dict {LOC AT26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t}] +#set_property -dict {LOC AT27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c}] +#set_property -dict {LOC AW28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke}] +#set_property -dict {LOC AY29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n}] +#set_property -dict {LOC AN25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +#set_property -dict {LOC BB29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt}] +#set_property -dict {LOC BF29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +#set_property -dict {LOC BD35 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] +#set_property -dict {LOC AR29 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_alert_n}] +#set_property -dict {LOC AY35 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_ten}] + +#set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] ;# U135.G2 DQL0 +#set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] ;# U135.F7 DQL1 +#set_property -dict {LOC BD32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] ;# U135.H3 DQL2 +#set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] ;# U135.H7 DQL3 +#set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] ;# U135.H2 DQL4 +#set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] ;# U135.H8 DQL5 +#set_property -dict {LOC BC31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] ;# U135.J3 DQL6 +#set_property -dict {LOC BD31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] ;# U135.J7 DQL7 +#set_property -dict {LOC BA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] ;# U135.A3 DQU0 +#set_property -dict {LOC BB33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] ;# U135.B8 DQU1 +#set_property -dict {LOC BA30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] ;# U135.C3 DQU2 +#set_property -dict {LOC BA31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] ;# U135.C7 DQU3 +#set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] ;# U135.C2 DQU4 +#set_property -dict {LOC AW32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] ;# U135.C8 DQU5 +#set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] ;# U135.D3 DQU6 +#set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] ;# U135.D7 DQU7 +#set_property -dict {LOC BF30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] ;# U135.G3 DQSL_T +#set_property -dict {LOC BF31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] ;# U135.F3 DQSL_C +#set_property -dict {LOC AY34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] ;# U135.B7 DQSU_T +#set_property -dict {LOC BA34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] ;# U135.A7 DQSU_C +#set_property -dict {LOC BE32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[0]}] ;# U135.E7 DML_B/DBIL_B +#set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[1]}] ;# U135.E2 DMU_B/DBIU_B + +#set_property -dict {LOC AV30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] ;# U136.G2 DQL0 +#set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] ;# U136.F7 DQL1 +#set_property -dict {LOC AU33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] ;# U136.H3 DQL2 +#set_property -dict {LOC AU34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] ;# U136.H7 DQL3 +#set_property -dict {LOC AT31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] ;# U136.H2 DQL4 +#set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] ;# U136.H8 DQL5 +#set_property -dict {LOC AU31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] ;# U136.J3 DQL6 +#set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] ;# U136.J7 DQL7 +#set_property -dict {LOC AR33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] ;# U136.A3 DQU0 +#set_property -dict {LOC AT34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] ;# U136.B8 DQU1 +#set_property -dict {LOC AT29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] ;# U136.C3 DQU2 +#set_property -dict {LOC AT30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] ;# U136.C7 DQU3 +#set_property -dict {LOC AP30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] ;# U136.C2 DQU4 +#set_property -dict {LOC AR30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] ;# U136.C8 DQU5 +#set_property -dict {LOC AN30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] ;# U136.D3 DQU6 +#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] ;# U136.D7 DQU7 +#set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] ;# U136.G3 DQSL_T +#set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] ;# U136.F3 DQSL_C +#set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] ;# U136.B7 DQSU_T +#set_property -dict {LOC AP32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] ;# U136.A7 DQSU_C +#set_property -dict {LOC AV33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[2]}] ;# U136.E7 DML_B/DBIL_B +#set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[3]}] ;# U136.E2 DMU_B/DBIU_B + +#set_property -dict {LOC BE34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] ;# U137.G2 DQL0 +#set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] ;# U137.F7 DQL1 +#set_property -dict {LOC BC35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] ;# U137.H3 DQL2 +#set_property -dict {LOC BC36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] ;# U137.H7 DQL3 +#set_property -dict {LOC BD36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] ;# U137.H2 DQL4 +#set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] ;# U137.H8 DQL5 +#set_property -dict {LOC BF36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] ;# U137.J3 DQL6 +#set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] ;# U137.J7 DQL7 +#set_property -dict {LOC BD37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] ;# U137.A3 DQU0 +#set_property -dict {LOC BE38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] ;# U137.B8 DQU1 +#set_property -dict {LOC BC39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] ;# U137.C3 DQU2 +#set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] ;# U137.C7 DQU3 +#set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] ;# U137.C2 DQU4 +#set_property -dict {LOC BB39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] ;# U137.C8 DQU5 +#set_property -dict {LOC BC38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] ;# U137.D3 DQU6 +#set_property -dict {LOC BD38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] ;# U137.D7 DQU7 +#set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] ;# U137.G3 DQSL_T +#set_property -dict {LOC BF35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] ;# U137.F3 DQSL_C +#set_property -dict {LOC BE39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] ;# U137.B7 DQSU_T +#set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] ;# U137.A7 DQSU_C +#set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[4]}] ;# U137.E7 DML_B/DBIL_B +#set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[5]}] ;# U137.E2 DMU_B/DBIU_B + +#set_property -dict {LOC BB36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] ;# U138.G2 DQL0 +#set_property -dict {LOC BB37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] ;# U138.F7 DQL1 +#set_property -dict {LOC BA39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] ;# U138.H3 DQL2 +#set_property -dict {LOC BA40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] ;# U138.H7 DQL3 +#set_property -dict {LOC AW40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] ;# U138.H2 DQL4 +#set_property -dict {LOC AY40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] ;# U138.H8 DQL5 +#set_property -dict {LOC AY38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] ;# U138.J3 DQL6 +#set_property -dict {LOC AY39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] ;# U138.J7 DQL7 +#set_property -dict {LOC AW35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] ;# U138.A3 DQU0 +#set_property -dict {LOC AW36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] ;# U138.B8 DQU1 +#set_property -dict {LOC AU40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] ;# U138.C3 DQU2 +#set_property -dict {LOC AV40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] ;# U138.C7 DQU3 +#set_property -dict {LOC AU38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] ;# U138.C2 DQU4 +#set_property -dict {LOC AU39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] ;# U138.C8 DQU5 +#set_property -dict {LOC AV38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] ;# U138.D3 DQU6 +#set_property -dict {LOC AV39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] ;# U138.D7 DQU7 +#set_property -dict {LOC BA35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] ;# U138.G3 DQSL_T +#set_property -dict {LOC BA36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] ;# U138.F3 DQSL_C +#set_property -dict {LOC AW37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] ;# U138.B7 DQSU_T +#set_property -dict {LOC AW38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] ;# U138.A7 DQSU_C +#set_property -dict {LOC AY37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[6]}] ;# U138.E7 DML_B/DBIL_B +#set_property -dict {LOC AV35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[7]}] ;# U138.E2 DMU_B/DBIU_B + +#set_property -dict {LOC BF26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] ;# U139.G2 DQL0 +#set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] ;# U139.F7 DQL1 +#set_property -dict {LOC BD28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] ;# U139.H3 DQL2 +#set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] ;# U139.H7 DQL3 +#set_property -dict {LOC BD27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] ;# U139.H2 DQL4 +#set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] ;# U139.H8 DQL5 +#set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] ;# U139.J3 DQL6 +#set_property -dict {LOC BD26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] ;# U139.J7 DQL7 +#set_property -dict {LOC BC25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[72]}] ;# U139.A3 DQU0 +#set_property -dict {LOC BC26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[73]}] ;# U139.B8 DQU1 +#set_property -dict {LOC BB28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[74]}] ;# U139.C3 DQU2 +#set_property -dict {LOC BC28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[75]}] ;# U139.C7 DQU3 +#set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[76]}] ;# U139.C2 DQU4 +#set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[77]}] ;# U139.C8 DQU5 +#set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[78]}] ;# U139.D3 DQU6 +#set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[79]}] ;# U139.D7 DQU7 +#set_property -dict {LOC BE25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] ;# U139.G3 DQSL_T +#set_property -dict {LOC BF25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] ;# U139.F3 DQSL_C +#set_property -dict {LOC BA26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] ;# U139.B7 DQSU_T +#set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] ;# U139.A7 DQSU_C +#set_property -dict {LOC BE29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[8]}] ;# U139.E7 DML_B/DBIL_B +#set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[9]}] ;# U139.E2 DMU_B/DBIU_B + # QSPI flash #set_property -dict {LOC AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}] #set_property -dict {LOC AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}] diff --git a/fpga/lib/eth/example/VCU118/fpga_25g/common/vivado.mk b/fpga/lib/eth/example/VCU118/fpga_25g/common/vivado.mk index 21e6a5fed..1402e2382 100644 --- a/fpga/lib/eth/example/VCU118/fpga_25g/common/vivado.mk +++ b/fpga/lib/eth/example/VCU118/fpga_25g/common/vivado.mk @@ -28,7 +28,7 @@ ################################################################### # phony targets -.PHONY: clean fpga +.PHONY: fpga vivado tmpclean clean distclean # prevent make from deleting intermediate files and reports .PRECIOUS: %.xpr %.bit %.mcs %.prm @@ -40,15 +40,16 @@ CONFIG ?= config.mk FPGA_TOP ?= fpga PROJECT ?= $(FPGA_TOP) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else - XDC_FILES_REL = $(FPGA_TOP).xdc + XDC_FILES_REL = $(PROJECT).xdc endif ################################################################### @@ -60,20 +61,20 @@ endif all: fpga -fpga: $(FPGA_TOP).bit +fpga: $(PROJECT).bit -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr -tmpclean: +tmpclean:: -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt -distclean: clean +distclean:: clean -rm -rf rev ################################################################### @@ -91,12 +92,17 @@ create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done -$(PROJECT).xpr: create_project.tcl +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) # synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr echo "open_project $(PROJECT).xpr" > run_synth.tcl echo "reset_run synth_1" >> run_synth.tcl echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl diff --git a/fpga/lib/eth/example/VCU118/fpga_25g/fpga.xdc b/fpga/lib/eth/example/VCU118/fpga_25g/fpga.xdc index fafef75ee..c2fda604f 100644 --- a/fpga/lib/eth/example/VCU118/fpga_25g/fpga.xdc +++ b/fpga/lib/eth/example/VCU118/fpga_25g/fpga.xdc @@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # System clocks # 300 MHz @@ -182,8 +183,8 @@ set_property -dict {LOC M2 } [get_ports qsfp2_rx4_p] ;# MGTYRXP3_232 GTYE4_CHAN set_property -dict {LOC M1 } [get_ports qsfp2_rx4_n] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 set_property -dict {LOC H7 } [get_ports qsfp2_tx4_p] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 set_property -dict {LOC H6 } [get_ports qsfp2_tx4_n] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13 -set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14 +#set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13 +#set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14 #set_property -dict {LOC N9 } [get_ports qsfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_232 from U57.35 #set_property -dict {LOC N8 } [get_ports qsfp2_mgt_refclk_1_n] ;# MGTREFCLK1N_232 from U57.34 #set_property -dict {LOC AP23 IOSTANDARD LVDS} [get_ports qsfp2_recclk_p] ;# to U57.12 @@ -195,7 +196,7 @@ set_property -dict {LOC AT21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp2_i set_property -dict {LOC AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_lpmode] # 156.25 MHz MGT reference clock -create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p] +#create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p] set_false_path -to [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}] set_output_delay 0 [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}] @@ -289,6 +290,667 @@ set_input_delay 0 [get_ports {i2c_sda i2c_scl}] #set_false_path -from [get_ports {pcie_reset_n}] #set_input_delay 0 [get_ports {pcie_reset_n}] +# FMC+ HSPC J22 +#set_property -dict {LOC AL35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[0]}] ;# J22.G9 LA00_P_CC +#set_property -dict {LOC AL36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[0]}] ;# J22.G10 LA00_N_CC +#set_property -dict {LOC AL30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[1]}] ;# J22.D8 LA01_P_CC +#set_property -dict {LOC AL31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[1]}] ;# J22.D9 LA01_N_CC +#set_property -dict {LOC AJ32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[2]}] ;# J22.H7 LA02_P +#set_property -dict {LOC AK32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[2]}] ;# J22.H8 LA02_N +#set_property -dict {LOC AT39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[3]}] ;# J22.G12 LA03_P +#set_property -dict {LOC AT40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[3]}] ;# J22.G13 LA03_N +#set_property -dict {LOC AR37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[4]}] ;# J22.H10 LA04_P +#set_property -dict {LOC AT37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[4]}] ;# J22.H11 LA04_N +#set_property -dict {LOC AP38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[5]}] ;# J22.D11 LA05_P +#set_property -dict {LOC AR38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[5]}] ;# J22.D12 LA05_N +#set_property -dict {LOC AT35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[6]}] ;# J22.C10 LA06_P +#set_property -dict {LOC AT36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[6]}] ;# J22.C11 LA06_N +#set_property -dict {LOC AP36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[7]}] ;# J22.H13 LA07_P +#set_property -dict {LOC AP37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[7]}] ;# J22.H14 LA07_N +#set_property -dict {LOC AK29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[8]}] ;# J22.G12 LA08_P +#set_property -dict {LOC AK30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[8]}] ;# J22.G13 LA08_N +#set_property -dict {LOC AJ33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[9]}] ;# J22.D14 LA09_P +#set_property -dict {LOC AK33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[9]}] ;# J22.D15 LA09_N +#set_property -dict {LOC AP35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[10]}] ;# J22.C14 LA10_P +#set_property -dict {LOC AR35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[10]}] ;# J22.C15 LA10_N +#set_property -dict {LOC AJ30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[11]}] ;# J22.H16 LA11_P +#set_property -dict {LOC AJ31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[11]}] ;# J22.H17 LA11_N +#set_property -dict {LOC AH33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[12]}] ;# J22.G15 LA12_P +#set_property -dict {LOC AH34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[12]}] ;# J22.G16 LA12_N +#set_property -dict {LOC AJ35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[13]}] ;# J22.D17 LA13_P +#set_property -dict {LOC AJ36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[13]}] ;# J22.D18 LA13_N +#set_property -dict {LOC AG31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[14]}] ;# J22.C18 LA14_P +#set_property -dict {LOC AH31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[14]}] ;# J22.C19 LA14_N +#set_property -dict {LOC AG32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[15]}] ;# J22.H19 LA15_P +#set_property -dict {LOC AG33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[15]}] ;# J22.H20 LA15_N +#set_property -dict {LOC AG34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[16]}] ;# J22.G18 LA16_P +#set_property -dict {LOC AH35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[16]}] ;# J22.G19 LA16_N +#set_property -dict {LOC R34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[17]}] ;# J22.D20 LA17_P_CC +#set_property -dict {LOC P34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[17]}] ;# J22.D21 LA17_N_CC +#set_property -dict {LOC R31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[18]}] ;# J22.C22 LA18_P_CC +#set_property -dict {LOC P31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[18]}] ;# J22.C23 LA18_N_CC +#set_property -dict {LOC N33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[19]}] ;# J22.H22 LA19_P +#set_property -dict {LOC M33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[19]}] ;# J22.H23 LA19_N +#set_property -dict {LOC N32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[20]}] ;# J22.G21 LA20_P +#set_property -dict {LOC M32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[20]}] ;# J22.G22 LA20_N +#set_property -dict {LOC M35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[21]}] ;# J22.H25 LA21_P +#set_property -dict {LOC L35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[21]}] ;# J22.H26 LA21_N +#set_property -dict {LOC N34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[22]}] ;# J22.G24 LA22_P +#set_property -dict {LOC N35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[22]}] ;# J22.G25 LA22_N +#set_property -dict {LOC Y32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[23]}] ;# J22.D23 LA23_P +#set_property -dict {LOC W32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[23]}] ;# J22.D24 LA23_N +#set_property -dict {LOC T34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[24]}] ;# J22.H28 LA24_P +#set_property -dict {LOC T35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[24]}] ;# J22.H29 LA24_N +#set_property -dict {LOC Y34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[25]}] ;# J22.G27 LA25_P +#set_property -dict {LOC W34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[25]}] ;# J22.G28 LA25_N +#set_property -dict {LOC V32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[26]}] ;# J22.D26 LA26_P +#set_property -dict {LOC U33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[26]}] ;# J22.D27 LA26_N +#set_property -dict {LOC V33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[27]}] ;# J22.C26 LA27_P +#set_property -dict {LOC V34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[27]}] ;# J22.C27 LA27_N +#set_property -dict {LOC M36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[28]}] ;# J22.H31 LA28_P +#set_property -dict {LOC L36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[28]}] ;# J22.H32 LA28_N +#set_property -dict {LOC U35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[29]}] ;# J22.G30 LA29_P +#set_property -dict {LOC T36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[29]}] ;# J22.G31 LA29_N +#set_property -dict {LOC N38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[30]}] ;# J22.H34 LA30_P +#set_property -dict {LOC M38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[30]}] ;# J22.H35 LA30_N +#set_property -dict {LOC P37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[31]}] ;# J22.G33 LA31_P +#set_property -dict {LOC N37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[31]}] ;# J22.G34 LA31_N +#set_property -dict {LOC L33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[32]}] ;# J22.H37 LA32_P +#set_property -dict {LOC K33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[32]}] ;# J22.H38 LA32_N +#set_property -dict {LOC L34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[33]}] ;# J22.G36 LA33_P +#set_property -dict {LOC K34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[33]}] ;# J22.G37 LA33_N + +#set_property -dict {LOC N14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[0]}] ;# J22.F4 HA00_P_CC +#set_property -dict {LOC N13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[0]}] ;# J22.F5 HA00_N_CC +#set_property -dict {LOC V15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[1]}] ;# J22.E2 HA01_P_CC +#set_property -dict {LOC U15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[1]}] ;# J22.E3 HA01_N_CC +#set_property -dict {LOC AA12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[2]}] ;# J22.K7 HA02_P +#set_property -dict {LOC Y12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[2]}] ;# J22.K8 HA02_N +#set_property -dict {LOC W12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[3]}] ;# J22.J6 HA03_P +#set_property -dict {LOC V12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[3]}] ;# J22.J7 HA03_N +#set_property -dict {LOC AA13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[4]}] ;# J22.F7 HA04_P +#set_property -dict {LOC Y13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[4]}] ;# J22.F8 HA04_N +#set_property -dict {LOC R14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[5]}] ;# J22.E6 HA05_P +#set_property -dict {LOC P14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[5]}] ;# J22.E7 HA05_N +#set_property -dict {LOC U13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[6]}] ;# J22.K10 HA06_P +#set_property -dict {LOC T13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[6]}] ;# J22.K11 HA06_N +#set_property -dict {LOC AA14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[7]}] ;# J22.J9 HA07_P +#set_property -dict {LOC Y14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[7]}] ;# J22.J10 HA07_N +#set_property -dict {LOC U11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[8]}] ;# J22.F10 HA08_P +#set_property -dict {LOC T11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[8]}] ;# J22.F11 HA08_N +#set_property -dict {LOC W14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[9]}] ;# J22.E9 HA09_P +#set_property -dict {LOC V14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[9]}] ;# J22.E10 HA09_N +#set_property -dict {LOC V16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[10]}] ;# J22.K13 HA10_P +#set_property -dict {LOC U16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[10]}] ;# J22.K14 HA10_N +#set_property -dict {LOC R12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[11]}] ;# J22.J12 HA11_P +#set_property -dict {LOC P12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[11]}] ;# J22.J13 HA11_N +#set_property -dict {LOC T16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[12]}] ;# J22.F13 HA12_P +#set_property -dict {LOC T15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[12]}] ;# J22.F14 HA12_N +#set_property -dict {LOC V13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[13]}] ;# J22.E12 HA13_P +#set_property -dict {LOC U12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[13]}] ;# J22.E13 HA13_N +#set_property -dict {LOC M11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[14]}] ;# J22.J15 HA14_P +#set_property -dict {LOC L11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[14]}] ;# J22.J16 HA14_N +#set_property -dict {LOC M13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[15]}] ;# J22.F14 HA15_P +#set_property -dict {LOC M12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[15]}] ;# J22.F16 HA15_N +#set_property -dict {LOC T14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[16]}] ;# J22.E15 HA16_P +#set_property -dict {LOC R13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[16]}] ;# J22.E16 HA16_N +#set_property -dict {LOC R11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[17]}] ;# J22.K16 HA17_P_CC +#set_property -dict {LOC P11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[17]}] ;# J22.K17 HA17_N_CC +#set_property -dict {LOC P15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[18]}] ;# J22.J18 HA18_P_CC +#set_property -dict {LOC N15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[18]}] ;# J22.J19 HA18_N_CC +#set_property -dict {LOC L14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[19]}] ;# J22.F19 HA19_P +#set_property -dict {LOC L13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[19]}] ;# J22.F20 HA19_N +#set_property -dict {LOC M15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[20]}] ;# J22.E18 HA20_P +#set_property -dict {LOC L15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[20]}] ;# J22.E19 HA20_N +#set_property -dict {LOC K14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[21]}] ;# J22.K19 HA21_P +#set_property -dict {LOC K13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[21]}] ;# J22.K20 HA21_N +#set_property -dict {LOC K12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[22]}] ;# J22.J21 HA22_P +#set_property -dict {LOC J12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[22]}] ;# J22.J22 HA22_N +#set_property -dict {LOC K11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[23]}] ;# J22.K22 HA23_P +#set_property -dict {LOC J11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[23]}] ;# J22.K23 HA23_N + +#set_property -dict {LOC AL32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_clk0_m2c_p}] ;# J22.H4 CLK0_M2C_P +#set_property -dict {LOC AM32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_clk0_m2c_n}] ;# J22.H5 CLK0_M2C_N +#set_property -dict {LOC P35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_clk1_m2c_p}] ;# J22.G2 CLK1_M2C_P +#set_property -dict {LOC P36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_clk1_m2c_n}] ;# J22.G3 CLK1_M2C_N + +#set_property -dict {LOC AN33 IOSTANDARD LVDS } [get_ports {fmcp_hspc_refclk_c2m_p}] ;# J22.L20 REFCLK_C2M_P +#set_property -dict {LOC AP33 IOSTANDARD LVDS } [get_ports {fmcp_hspc_refclk_c2m_n}] ;# J22.L21 REFCLK_C2M_N +#set_property -dict {LOC AK34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_refclk_m2c_p}] ;# J22.L24 REFCLK_M2C_P +#set_property -dict {LOC AL34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_refclk_m2c_n}] ;# J22.L25 REFCLK_M2C_N +#set_property -dict {LOC AN34 IOSTANDARD LVDS } [get_ports {fmcp_hspc_sync_c2m_p}] ;# J22.L16 SYNC_C2M_P +#set_property -dict {LOC AN35 IOSTANDARD LVDS } [get_ports {fmcp_hspc_sync_c2m_n}] ;# J22.L17 SYNC_C2M_N +#set_property -dict {LOC AM36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_sync_m2c_p}] ;# J22.L28 SYNC_M2C_P +#set_property -dict {LOC AN36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_sync_m2c_n}] ;# J22.L29 SYNC_M2C_N + +#set_property -dict {LOC AL36 IOSTANDARD LVCMOS18} [get_ports {fmcp_hspc_pg_m2c}] ;# J22.F1 PG_M2C +#set_property -dict {LOC AM33 IOSTANDARD LVCMOS18} [get_ports {fmcp_hspc_h_prsnt_m2c_l}] ;# J22.H2 PRSNT_M2C_L +#set_property -dict {LOC AM29 IOSTANDARD LVCMOS18} [get_ports {fmcp_hspc_z_prsnt_m2c_l}] ;# J22.Z1 HSPC_PRSNT_M2C_L + +#set_property -dict {LOC AT42} [get_ports {fmcp_hspc_dp_c2m_p[0]}] ;# MGTYTXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C2 DP0_C2M_P +#set_property -dict {LOC AT43} [get_ports {fmcp_hspc_dp_c2m_n[0]}] ;# MGTYTXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C3 DP0_C2M_N +#set_property -dict {LOC AR45} [get_ports {fmcp_hspc_dp_m2c_p[0]}] ;# MGTYRXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C6 DP0_M2C_P +#set_property -dict {LOC AR46} [get_ports {fmcp_hspc_dp_m2c_n[0]}] ;# MGTYRXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C7 DP0_M2C_N +#set_property -dict {LOC AP42} [get_ports {fmcp_hspc_dp_c2m_p[1]}] ;# MGTYTXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A22 DP1_C2M_P +#set_property -dict {LOC AP43} [get_ports {fmcp_hspc_dp_c2m_n[1]}] ;# MGTYTXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A23 DP1_C2M_N +#set_property -dict {LOC AN45} [get_ports {fmcp_hspc_dp_m2c_p[1]}] ;# MGTYRXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A2 DP1_M2C_P +#set_property -dict {LOC AN46} [get_ports {fmcp_hspc_dp_m2c_n[1]}] ;# MGTYRXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A3 DP1_M2C_N +#set_property -dict {LOC AM42} [get_ports {fmcp_hspc_dp_c2m_p[2]}] ;# MGTYTXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A26 DP2_C2M_P +#set_property -dict {LOC AM43} [get_ports {fmcp_hspc_dp_c2m_n[2]}] ;# MGTYTXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A27 DP2_C2M_N +#set_property -dict {LOC AL45} [get_ports {fmcp_hspc_dp_m2c_p[2]}] ;# MGTYRXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A6 DP2_M2C_P +#set_property -dict {LOC AL46} [get_ports {fmcp_hspc_dp_m2c_n[2]}] ;# MGTYRXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A7 DP2_M2C_N +#set_property -dict {LOC AL40} [get_ports {fmcp_hspc_dp_c2m_p[3]}] ;# MGTYTXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A30 DP3_C2M_P +#set_property -dict {LOC AL41} [get_ports {fmcp_hspc_dp_c2m_n[3]}] ;# MGTYTXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A31 DP3_C2M_N +#set_property -dict {LOC AJ45} [get_ports {fmcp_hspc_dp_m2c_p[3]}] ;# MGTYRXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A10 DP3_M2C_P +#set_property -dict {LOC AJ46} [get_ports {fmcp_hspc_dp_m2c_n[3]}] ;# MGTYRXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A11 DP3_M2C_N +#set_property -dict {LOC AK38} [get_ports fmcp_hspc_mgt_refclk_0_0_p] ;# MGTREFCLK0P_121 from U40.1 Q0 from J22.D4 GBTCLK0_M2C_P +#set_property -dict {LOC AK39} [get_ports fmcp_hspc_mgt_refclk_0_0_n] ;# MGTREFCLK0N_121 from U40.2 NQ0 from J22.D5 GBTCLK0_M2C_N +#set_property -dict {LOC AH38} [get_ports fmcp_hspc_mgt_refclk_0_1_p] ;# MGTREFCLK1P_121 from U39.5 Q0_P from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC AH39} [get_ports fmcp_hspc_mgt_refclk_0_1_n] ;# MGTREFCLK1N_121 from U39.6 Q0_N from J22.B21 GBTCLK1_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_0_0 [get_ports fmcp_hspc_mgt_refclk_0_0_p] +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_0_1 [get_ports fmcp_hspc_mgt_refclk_0_1_p] + +#set_property -dict {LOC T42 } [get_ports {fmcp_hspc_dp_c2m_p[4]}] ;# MGTYTXP0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A34 DP4_C2M_P +#set_property -dict {LOC T43 } [get_ports {fmcp_hspc_dp_c2m_n[4]}] ;# MGTYTXN0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A35 DP4_C2M_N +#set_property -dict {LOC W45 } [get_ports {fmcp_hspc_dp_m2c_p[4]}] ;# MGTYRXP0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A14 DP4_M2C_P +#set_property -dict {LOC W46 } [get_ports {fmcp_hspc_dp_m2c_n[4]}] ;# MGTYRXN0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A15 DP4_M2C_N +#set_property -dict {LOC P42 } [get_ports {fmcp_hspc_dp_c2m_p[5]}] ;# MGTYTXP1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A38 DP5_C2M_P +#set_property -dict {LOC P43 } [get_ports {fmcp_hspc_dp_c2m_n[5]}] ;# MGTYTXN1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A39 DP5_C2M_N +#set_property -dict {LOC U45 } [get_ports {fmcp_hspc_dp_m2c_p[5]}] ;# MGTYRXP1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A18 DP5_M2C_P +#set_property -dict {LOC U46 } [get_ports {fmcp_hspc_dp_m2c_n[5]}] ;# MGTYRXN1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A19 DP5_M2C_N +#set_property -dict {LOC M42 } [get_ports {fmcp_hspc_dp_c2m_p[6]}] ;# MGTYTXP2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B36 DP6_C2M_P +#set_property -dict {LOC M43 } [get_ports {fmcp_hspc_dp_c2m_n[6]}] ;# MGTYTXN2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B37 DP6_C2M_N +#set_property -dict {LOC R45 } [get_ports {fmcp_hspc_dp_m2c_p[6]}] ;# MGTYRXP2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B16 DP6_M2C_P +#set_property -dict {LOC R46 } [get_ports {fmcp_hspc_dp_m2c_n[6]}] ;# MGTYRXN2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B17 DP6_M2C_N +#set_property -dict {LOC K42 } [get_ports {fmcp_hspc_dp_c2m_p[7]}] ;# MGTYTXP3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B32 DP7_C2M_P +#set_property -dict {LOC K43 } [get_ports {fmcp_hspc_dp_c2m_n[7]}] ;# MGTYTXN3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B33 DP7_C2M_N +#set_property -dict {LOC N45 } [get_ports {fmcp_hspc_dp_m2c_p[7]}] ;# MGTYRXP3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B12 DP7_M2C_P +#set_property -dict {LOC N46 } [get_ports {fmcp_hspc_dp_m2c_n[7]}] ;# MGTYRXN3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B13 DP7_M2C_N +#set_property -dict {LOC V38 } [get_ports fmcp_hspc_mgt_refclk_1_0_p] ;# MGTREFCLK0P_126 from U40.3 Q1 from J22.D4 GBTCLK0_M2C_P +#set_property -dict {LOC V39 } [get_ports fmcp_hspc_mgt_refclk_1_0_n] ;# MGTREFCLK0N_126 from U40.4 NQ1 from J22.D5 GBTCLK0_M2C_N +#set_property -dict {LOC T38 } [get_ports fmcp_hspc_mgt_refclk_1_1_p] ;# MGTREFCLK1P_126 from U39.8 Q1_P from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC T39 } [get_ports fmcp_hspc_mgt_refclk_1_1_n] ;# MGTREFCLK1N_126 from U39.9 Q1_N from J22.B21 GBTCLK1_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_1_0 [get_ports fmcp_hspc_mgt_refclk_1_0_p] +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_1_1 [get_ports fmcp_hspc_mgt_refclk_1_1_p] + +#set_property -dict {LOC AK42} [get_ports {fmcp_hspc_dp_c2m_p[8]}] ;# MGTYTXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B28 DP8_C2M_P +#set_property -dict {LOC AK43} [get_ports {fmcp_hspc_dp_c2m_n[8]}] ;# MGTYTXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B29 DP8_C2M_N +#set_property -dict {LOC AG45} [get_ports {fmcp_hspc_dp_m2c_p[8]}] ;# MGTYRXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B8 DP8_M2C_P +#set_property -dict {LOC AG46} [get_ports {fmcp_hspc_dp_m2c_n[8]}] ;# MGTYRXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B9 DP8_M2C_N +#set_property -dict {LOC AJ40} [get_ports {fmcp_hspc_dp_c2m_p[9]}] ;# MGTYTXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B24 DP9_C2M_P +#set_property -dict {LOC AJ41} [get_ports {fmcp_hspc_dp_c2m_n[9]}] ;# MGTYTXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B25 DP9_C2M_N +#set_property -dict {LOC AF43} [get_ports {fmcp_hspc_dp_m2c_p[9]}] ;# MGTYRXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B4 DP9_M2C_P +#set_property -dict {LOC AF44} [get_ports {fmcp_hspc_dp_m2c_n[9]}] ;# MGTYRXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B5 DP9_M2C_N +#set_property -dict {LOC AG40} [get_ports {fmcp_hspc_dp_c2m_p[10]}] ;# MGTYTXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Z24 DP10_C2M_P +#set_property -dict {LOC AG41} [get_ports {fmcp_hspc_dp_c2m_n[10]}] ;# MGTYTXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Z25 DP10_C2M_N +#set_property -dict {LOC AE45} [get_ports {fmcp_hspc_dp_m2c_p[10]}] ;# MGTYRXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Y10 DP10_M2C_P +#set_property -dict {LOC AE46} [get_ports {fmcp_hspc_dp_m2c_n[10]}] ;# MGTYRXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Y11 DP10_M2C_N +#set_property -dict {LOC AE40} [get_ports {fmcp_hspc_dp_c2m_p[11]}] ;# MGTYTXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Y26 DP11_C2M_P +#set_property -dict {LOC AE41} [get_ports {fmcp_hspc_dp_c2m_n[11]}] ;# MGTYTXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Y27 DP11_C2M_N +#set_property -dict {LOC AD43} [get_ports {fmcp_hspc_dp_m2c_p[11]}] ;# MGTYRXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Z12 DP11_M2C_P +#set_property -dict {LOC AD44} [get_ports {fmcp_hspc_dp_m2c_n[11]}] ;# MGTYRXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Z13 DP11_M2C_N +#set_property -dict {LOC AF38} [get_ports fmcp_hspc_mgt_refclk_2_0_p] ;# MGTREFCLK0P_122 from J22.L12 GBTCLK2_M2C_P +#set_property -dict {LOC AF39} [get_ports fmcp_hspc_mgt_refclk_2_0_n] ;# MGTREFCLK0N_122 from J22.L13 GBTCLK2_M2C_N +#set_property -dict {LOC AD38} [get_ports fmcp_hspc_mgt_refclk_2_1_p] ;# MGTREFCLK1P_122 from U39.11 Q2_P from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC AD39} [get_ports fmcp_hspc_mgt_refclk_2_1_n] ;# MGTREFCLK1N_122 from U39.12 Q2_N from J22.B21 GBTCLK1_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_2_0 [get_ports fmcp_hspc_mgt_refclk_2_0_p] +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_2_1 [get_ports fmcp_hspc_mgt_refclk_2_1_p] + +#set_property -dict {LOC AC40} [get_ports {fmcp_hspc_dp_c2m_p[12]}] ;# MGTYTXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Z28 DP12_C2M_P +#set_property -dict {LOC AC41} [get_ports {fmcp_hspc_dp_c2m_n[12]}] ;# MGTYTXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Z29 DP12_C2M_N +#set_property -dict {LOC AC45} [get_ports {fmcp_hspc_dp_m2c_p[12]}] ;# MGTYRXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Y14 DP12_M2C_P +#set_property -dict {LOC AC46} [get_ports {fmcp_hspc_dp_m2c_n[12]}] ;# MGTYRXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Y15 DP12_M2C_N +#set_property -dict {LOC AA40} [get_ports {fmcp_hspc_dp_c2m_p[13]}] ;# MGTYTXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Y30 DP13_C2M_P +#set_property -dict {LOC AA41} [get_ports {fmcp_hspc_dp_c2m_n[13]}] ;# MGTYTXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Y31 DP13_C2M_N +#set_property -dict {LOC AB43} [get_ports {fmcp_hspc_dp_m2c_p[13]}] ;# MGTYRXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Z16 DP13_M2C_P +#set_property -dict {LOC AB44} [get_ports {fmcp_hspc_dp_m2c_n[13]}] ;# MGTYRXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Z17 DP13_M2C_N +#set_property -dict {LOC W40 } [get_ports {fmcp_hspc_dp_c2m_p[14]}] ;# MGTYTXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.M18 DP14_C2M_P +#set_property -dict {LOC W41 } [get_ports {fmcp_hspc_dp_c2m_n[14]}] ;# MGTYTXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.M19 DP14_C2M_N +#set_property -dict {LOC AA45} [get_ports {fmcp_hspc_dp_m2c_p[14]}] ;# MGTYRXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.Y18 DP14_M2C_P +#set_property -dict {LOC AA46} [get_ports {fmcp_hspc_dp_m2c_n[14]}] ;# MGTYRXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.Y19 DP14_M2C_N +#set_property -dict {LOC U40 } [get_ports {fmcp_hspc_dp_c2m_p[15]}] ;# MGTYTXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.M22 DP15_C2M_P +#set_property -dict {LOC U41 } [get_ports {fmcp_hspc_dp_c2m_n[15]}] ;# MGTYTXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.M23 DP15_C2M_N +#set_property -dict {LOC Y43 } [get_ports {fmcp_hspc_dp_m2c_p[15]}] ;# MGTYRXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.Y22 DP15_M2C_P +#set_property -dict {LOC Y44 } [get_ports {fmcp_hspc_dp_m2c_n[15]}] ;# MGTYRXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.Y23 DP15_M2C_N +#set_property -dict {LOC AB38} [get_ports fmcp_hspc_mgt_refclk_3_0_p] ;# MGTREFCLK0P_125 from J22.L8 GBTCLK3_M2C_P +#set_property -dict {LOC AB39} [get_ports fmcp_hspc_mgt_refclk_3_0_n] ;# MGTREFCLK0N_125 from J22.L9 GBTCLK3_M2C_N +#set_property -dict {LOC Y38 } [get_ports fmcp_hspc_mgt_refclk_3_1_p] ;# MGTREFCLK1P_125 from U39.13 Q3_P from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC Y39 } [get_ports fmcp_hspc_mgt_refclk_3_1_n] ;# MGTREFCLK1N_125 from U39.14 Q3_N from J22.B21 GBTCLK1_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_3_0 [get_ports fmcp_hspc_mgt_refclk_3_0_p] +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_3_1 [get_ports fmcp_hspc_mgt_refclk_3_1_p] + +#set_property -dict {LOC H42 } [get_ports {fmcp_hspc_dp_c2m_p[16]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.M26 DP16_C2M_P +#set_property -dict {LOC H43 } [get_ports {fmcp_hspc_dp_c2m_n[16]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.M27 DP16_C2M_N +#set_property -dict {LOC L45 } [get_ports {fmcp_hspc_dp_m2c_p[16]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.Z32 DP16_M2C_P +#set_property -dict {LOC L46 } [get_ports {fmcp_hspc_dp_m2c_n[16]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.Z33 DP16_M2C_N +#set_property -dict {LOC F42 } [get_ports {fmcp_hspc_dp_c2m_p[17]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.M30 DP17_C2M_P +#set_property -dict {LOC F43 } [get_ports {fmcp_hspc_dp_c2m_n[17]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.M31 DP17_C2M_N +#set_property -dict {LOC J45 } [get_ports {fmcp_hspc_dp_m2c_p[17]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.Y34 DP17_M2C_P +#set_property -dict {LOC J46 } [get_ports {fmcp_hspc_dp_m2c_n[17]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.Y35 DP17_M2C_N +#set_property -dict {LOC D42 } [get_ports {fmcp_hspc_dp_c2m_p[18]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.M34 DP18_C2M_P +#set_property -dict {LOC D43 } [get_ports {fmcp_hspc_dp_c2m_n[18]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.M35 DP18_C2M_N +#set_property -dict {LOC G45 } [get_ports {fmcp_hspc_dp_m2c_p[18]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.Z36 DP18_M2C_P +#set_property -dict {LOC G46 } [get_ports {fmcp_hspc_dp_m2c_n[18]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.Z37 DP18_M2C_N +#set_property -dict {LOC B42 } [get_ports {fmcp_hspc_dp_c2m_p[19]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.M38 DP19_C2M_P +#set_property -dict {LOC B43 } [get_ports {fmcp_hspc_dp_c2m_n[19]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.M39 DP19_C2M_N +#set_property -dict {LOC E45 } [get_ports {fmcp_hspc_dp_m2c_p[19]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.Y38 DP19_M2C_P +#set_property -dict {LOC E46 } [get_ports {fmcp_hspc_dp_m2c_n[19]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.Y39 DP19_M2C_N +#set_property -dict {LOC R40 } [get_ports fmcp_hspc_mgt_refclk_4_0_p] ;# MGTREFCLK0P_127 from J22.L4 GBTCLK4_M2C_P +#set_property -dict {LOC R41 } [get_ports fmcp_hspc_mgt_refclk_4_0_n] ;# MGTREFCLK0N_127 from J22.L5 GBTCLK4_M2C_N +#set_property -dict {LOC N40 } [get_ports fmcp_hspc_mgt_refclk_4_1_p] ;# MGTREFCLK1P_127 from U39.16 Q4_P from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC N41 } [get_ports fmcp_hspc_mgt_refclk_4_1_n] ;# MGTREFCLK1N_127 from U39.17 Q4_N from J22.B21 GBTCLK1_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_4_0 [get_ports fmcp_hspc_mgt_refclk_4_0_p] +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_4_1 [get_ports fmcp_hspc_mgt_refclk_4_1_p] + +#set_property -dict {LOC BD42} [get_ports {fmcp_hspc_dp_c2m_p[20]}] ;# MGTYTXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.Z8 DP20_C2M_P +#set_property -dict {LOC BD43} [get_ports {fmcp_hspc_dp_c2m_n[20]}] ;# MGTYTXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.Z9 DP20_C2M_N +#set_property -dict {LOC BC45} [get_ports {fmcp_hspc_dp_m2c_p[20]}] ;# MGTYRXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.M14 DP20_M2C_P +#set_property -dict {LOC BC46} [get_ports {fmcp_hspc_dp_m2c_n[20]}] ;# MGTYRXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.M15 DP20_M2C_N +#set_property -dict {LOC BB42} [get_ports {fmcp_hspc_dp_c2m_p[21]}] ;# MGTYTXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.Y6 DP21_C2M_P +#set_property -dict {LOC BB43} [get_ports {fmcp_hspc_dp_c2m_n[21]}] ;# MGTYTXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.Y7 DP21_C2M_N +#set_property -dict {LOC BA45} [get_ports {fmcp_hspc_dp_m2c_p[21]}] ;# MGTYRXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.M10 DP21_M2C_P +#set_property -dict {LOC BA46} [get_ports {fmcp_hspc_dp_m2c_n[21]}] ;# MGTYRXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.M11 DP21_M2C_N +#set_property -dict {LOC AY42} [get_ports {fmcp_hspc_dp_c2m_p[22]}] ;# MGTYTXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.Z4 DP22_C2M_P +#set_property -dict {LOC AY43} [get_ports {fmcp_hspc_dp_c2m_n[22]}] ;# MGTYTXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.Z5 DP22_C2M_N +#set_property -dict {LOC AW45} [get_ports {fmcp_hspc_dp_m2c_p[22]}] ;# MGTYRXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.M6 DP22_M2C_P +#set_property -dict {LOC AW46} [get_ports {fmcp_hspc_dp_m2c_n[22]}] ;# MGTYRXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.M7 DP22_M2C_N +#set_property -dict {LOC AV42} [get_ports {fmcp_hspc_dp_c2m_p[23]}] ;# MGTYTXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.Y2 DP23_C2M_P +#set_property -dict {LOC AV43} [get_ports {fmcp_hspc_dp_c2m_n[23]}] ;# MGTYTXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.Y3 DP23_C2M_N +#set_property -dict {LOC AU45} [get_ports {fmcp_hspc_dp_m2c_p[23]}] ;# MGTYRXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.M2 DP23_M2C_P +#set_property -dict {LOC AU46} [get_ports {fmcp_hspc_dp_m2c_n[23]}] ;# MGTYRXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.M3 DP23_M2C_N +#set_property -dict {LOC AN40} [get_ports fmcp_hspc_mgt_refclk_5_0_p] ;# MGTREFCLK0P_120 from J22.Z20 GBTCLK5_M2C_P +#set_property -dict {LOC AN41} [get_ports fmcp_hspc_mgt_refclk_5_0_n] ;# MGTREFCLK0N_120 from J22.Z21 GBTCLK5_M2C_N +#set_property -dict {LOC AM38} [get_ports fmcp_hspc_mgt_refclk_5_1_p] ;# MGTREFCLK1P_120 from U39.19 Q5_P from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC AM39} [get_ports fmcp_hspc_mgt_refclk_5_1_n] ;# MGTREFCLK1N_120 from U39.20 Q5_N from J22.B21 GBTCLK1_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_5_0 [get_ports fmcp_hspc_mgt_refclk_5_0_p] +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_5_1 [get_ports fmcp_hspc_mgt_refclk_5_1_p] + +# FMC HPC1 J2 +#set_property -dict {LOC AY9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[0]}] ;# J2.G9 LA00_P_CC +#set_property -dict {LOC BA9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[0]}] ;# J2.G10 LA00_N_CC +#set_property -dict {LOC BF10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[1]}] ;# J2.D8 LA01_P_CC +#set_property -dict {LOC BF9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[1]}] ;# J2.D9 LA01_N_CC +#set_property -dict {LOC BC11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[2]}] ;# J2.H7 LA02_P +#set_property -dict {LOC BD11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[2]}] ;# J2.H8 LA02_N +#set_property -dict {LOC BD12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[3]}] ;# J2.G12 LA03_P +#set_property -dict {LOC BE12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[3]}] ;# J2.G13 LA03_N +#set_property -dict {LOC BD12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[4]}] ;# J2.H10 LA04_P +#set_property -dict {LOC BF11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[4]}] ;# J2.H11 LA04_N +#set_property -dict {LOC BE14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[5]}] ;# J2.D11 LA05_P +#set_property -dict {LOC BF14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[5]}] ;# J2.D12 LA05_N +#set_property -dict {LOC BD13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[6]}] ;# J2.C10 LA06_P +#set_property -dict {LOC BE13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[6]}] ;# J2.C11 LA06_N +#set_property -dict {LOC BC15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[7]}] ;# J2.H13 LA07_P +#set_property -dict {LOC BD15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[7]}] ;# J2.H14 LA07_N +#set_property -dict {LOC BE15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[8]}] ;# J2.G12 LA08_P +#set_property -dict {LOC BF15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[8]}] ;# J2.G13 LA08_N +#set_property -dict {LOC BA14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[9]}] ;# J2.D14 LA09_P +#set_property -dict {LOC BB14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[9]}] ;# J2.D15 LA09_N +#set_property -dict {LOC BB13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[10]}] ;# J2.C14 LA10_P +#set_property -dict {LOC BB12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[10]}] ;# J2.C15 LA10_N +#set_property -dict {LOC BA16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[11]}] ;# J2.H16 LA11_P +#set_property -dict {LOC BA15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[11]}] ;# J2.H17 LA11_N +#set_property -dict {LOC BC14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[12]}] ;# J2.G15 LA12_P +#set_property -dict {LOC BC13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[12]}] ;# J2.G16 LA12_N +#set_property -dict {LOC AY8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[13]}] ;# J2.D17 LA13_P +#set_property -dict {LOC AY7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[13]}] ;# J2.D18 LA13_N +#set_property -dict {LOC AW8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[14]}] ;# J2.C18 LA14_P +#set_property -dict {LOC AW7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[14]}] ;# J2.C19 LA14_N +#set_property -dict {LOC BB16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[15]}] ;# J2.H19 LA15_P +#set_property -dict {LOC BC16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[15]}] ;# J2.H20 LA15_N +#set_property -dict {LOC AV9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[16]}] ;# J2.G18 LA16_P +#set_property -dict {LOC AB8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[16]}] ;# J2.G19 LA16_N +#set_property -dict {LOC AR14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[17]}] ;# J2.D20 LA17_P_CC +#set_property -dict {LOC AT14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[17]}] ;# J2.D21 LA17_N_CC +#set_property -dict {LOC AP12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[18]}] ;# J2.C22 LA18_P_CC +#set_property -dict {LOC AR12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[18]}] ;# J2.C23 LA18_N_CC +#set_property -dict {LOC AW12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[19]}] ;# J2.H22 LA19_P +#set_property -dict {LOC AY12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[19]}] ;# J2.H23 LA19_N +#set_property -dict {LOC AW11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[20]}] ;# J2.G21 LA20_P +#set_property -dict {LOC AY10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[20]}] ;# J2.G22 LA20_N +#set_property -dict {LOC AU11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[21]}] ;# J2.H25 LA21_P +#set_property -dict {LOC AV11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[21]}] ;# J2.H26 LA21_N +#set_property -dict {LOC AW13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[22]}] ;# J2.G24 LA22_P +#set_property -dict {LOC AY13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[22]}] ;# J2.G25 LA22_N +#set_property -dict {LOC AN16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[23]}] ;# J2.D23 LA23_P +#set_property -dict {LOC AP16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[23]}] ;# J2.D24 LA23_N +#set_property -dict {LOC AP13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[24]}] ;# J2.H28 LA24_P +#set_property -dict {LOC AR13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[24]}] ;# J2.H29 LA24_N +#set_property -dict {LOC AT12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[25]}] ;# J2.G27 LA25_P +#set_property -dict {LOC AU12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[25]}] ;# J2.G28 LA25_N +#set_property -dict {LOC AK15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[26]}] ;# J2.D26 LA26_P +#set_property -dict {LOC AL15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[26]}] ;# J2.D27 LA26_N +#set_property -dict {LOC AL14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[27]}] ;# J2.C26 LA27_P +#set_property -dict {LOC AM14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[27]}] ;# J2.C27 LA27_N +#set_property -dict {LOC AV10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[28]}] ;# J2.H31 LA28_P +#set_property -dict {LOC AW10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[28]}] ;# J2.H32 LA28_N +#set_property -dict {LOC AN15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[29]}] ;# J2.G30 LA29_P +#set_property -dict {LOC AP15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[29]}] ;# J2.G31 LA29_N +#set_property -dict {LOC AK12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[30]}] ;# J2.H34 LA30_P +#set_property -dict {LOC AL12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[30]}] ;# J2.H35 LA30_N +#set_property -dict {LOC AM13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[31]}] ;# J2.G33 LA31_P +#set_property -dict {LOC AM12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[31]}] ;# J2.G34 LA31_N +#set_property -dict {LOC AJ13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[32]}] ;# J2.H37 LA32_P +#set_property -dict {LOC AJ12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[32]}] ;# J2.H38 LA32_N +#set_property -dict {LOC AK14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[33]}] ;# J2.G36 LA33_P +#set_property -dict {LOC AK13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[33]}] ;# J2.G37 LA33_N + +#set_property -dict {LOC BC9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_clk0_m2c_p}] ;# J2.H4 CLK0_M2C_P +#set_property -dict {LOC BC8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_clk0_m2c_n}] ;# J2.H5 CLK0_M2C_N +#set_property -dict {LOC AV14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_clk1_m2c_p}] ;# J2.G2 CLK1_M2C_P +#set_property -dict {LOC AV13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_clk1_m2c_n}] ;# J2.G3 CLK1_M2C_N + +#set_property -dict {LOC BA7 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc1_pg_m2c}] ;# J2.F1 PG_M2C +#set_property -dict {LOC BB7 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc1_prsnt_m2c_l}] ;# J2.H2 PRSNT_M2C_L + +# DDR4 C1 +# 5x MT40A256M16GE-075E +#set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +#set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +#set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +#set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +#set_property -dict {LOC C15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +#set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +#set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +#set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +#set_property -dict {LOC A16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +#set_property -dict {LOC B12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +#set_property -dict {LOC C12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +#set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +#set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +#set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +#set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +#set_property -dict {LOC H15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +#set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +#set_property -dict {LOC G15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +#set_property -dict {LOC G13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +#set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +#set_property -dict {LOC F14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}] +#set_property -dict {LOC E14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}] +#set_property -dict {LOC A10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}] +#set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}] +#set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +#set_property -dict {LOC C8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}] +#set_property -dict {LOC G10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +#set_property -dict {LOC N20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] +#set_property -dict {LOC R17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}] +#set_property -dict {LOC A20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}] + +#set_property -dict {LOC F11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] ;# U60.G2 DQL0 +#set_property -dict {LOC E11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] ;# U60.F7 DQL1 +#set_property -dict {LOC F10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] ;# U60.H3 DQL2 +#set_property -dict {LOC F9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] ;# U60.H7 DQL3 +#set_property -dict {LOC H12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] ;# U60.H2 DQL4 +#set_property -dict {LOC G12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] ;# U60.H8 DQL5 +#set_property -dict {LOC E9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] ;# U60.J3 DQL6 +#set_property -dict {LOC D9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] ;# U60.J7 DQL7 +#set_property -dict {LOC R19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] ;# U60.A3 DQU0 +#set_property -dict {LOC P19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] ;# U60.B8 DQU1 +#set_property -dict {LOC M18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] ;# U60.C3 DQU2 +#set_property -dict {LOC M17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] ;# U60.C7 DQU3 +#set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] ;# U60.C2 DQU4 +#set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] ;# U60.C8 DQU5 +#set_property -dict {LOC N17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] ;# U60.D3 DQU6 +#set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] ;# U60.D7 DQU7 +#set_property -dict {LOC D11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] ;# U60.G3 DQSL_T +#set_property -dict {LOC D10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] ;# U60.F3 DQSL_C +#set_property -dict {LOC P17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] ;# U60.B7 DQSU_T +#set_property -dict {LOC P16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] ;# U60.A7 DQSU_C +#set_property -dict {LOC G11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] ;# U60.E7 DML_B/DBIL_B +#set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] ;# U60.E2 DMU_B/DBIU_B + +#set_property -dict {LOC L16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] ;# U61.G2 DQL0 +#set_property -dict {LOC K16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] ;# U61.F7 DQL1 +#set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] ;# U61.H3 DQL2 +#set_property -dict {LOC K18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] ;# U61.H7 DQL3 +#set_property -dict {LOC J17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] ;# U61.H2 DQL4 +#set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] ;# U61.H8 DQL5 +#set_property -dict {LOC H19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] ;# U61.J3 DQL6 +#set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] ;# U61.J7 DQL7 +#set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] ;# U61.A3 DQU0 +#set_property -dict {LOC F18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] ;# U61.B8 DQU1 +#set_property -dict {LOC E19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] ;# U61.C3 DQU2 +#set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] ;# U61.C7 DQU3 +#set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] ;# U61.C2 DQU4 +#set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] ;# U61.C8 DQU5 +#set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] ;# U61.D3 DQU6 +#set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] ;# U61.D7 DQU7 +#set_property -dict {LOC K19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] ;# U61.G3 DQSL_T +#set_property -dict {LOC J19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] ;# U61.F3 DQSL_C +#set_property -dict {LOC F16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] ;# U61.B7 DQSU_T +#set_property -dict {LOC E16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] ;# U61.A7 DQSU_C +#set_property -dict {LOC K17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] ;# U61.E7 DML_B/DBIL_B +#set_property -dict {LOC G18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] ;# U61.E2 DMU_B/DBIU_B + +#set_property -dict {LOC D17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] ;# U62.G2 DQL0 +#set_property -dict {LOC C17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] ;# U62.F7 DQL1 +#set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] ;# U62.H3 DQL2 +#set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] ;# U62.H7 DQL3 +#set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] ;# U62.H2 DQL4 +#set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] ;# U62.H8 DQL5 +#set_property -dict {LOC C20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] ;# U62.J3 DQL6 +#set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] ;# U62.J7 DQL7 +#set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] ;# U62.A3 DQU0 +#set_property -dict {LOC M23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] ;# U62.B8 DQU1 +#set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] ;# U62.C3 DQU2 +#set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] ;# U62.C7 DQU3 +#set_property -dict {LOC R22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] ;# U62.C2 DQU4 +#set_property -dict {LOC P22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] ;# U62.C8 DQU5 +#set_property -dict {LOC T23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] ;# U62.D3 DQU6 +#set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] ;# U62.D7 DQU7 +#set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] ;# U62.G3 DQSL_T +#set_property -dict {LOC A18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] ;# U62.F3 DQSL_C +#set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] ;# U62.B7 DQSU_T +#set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] ;# U62.A7 DQSU_C +#set_property -dict {LOC B18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] ;# U62.E7 DML_B/DBIL_B +#set_property -dict {LOC P20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] ;# U62.E2 DMU_B/DBIU_B + +#set_property -dict {LOC K24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] ;# U63.G2 DQL0 +#set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] ;# U63.F7 DQL1 +#set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] ;# U63.H3 DQL2 +#set_property -dict {LOC L21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] ;# U63.H7 DQL3 +#set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] ;# U63.H2 DQL4 +#set_property -dict {LOC J21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] ;# U63.H8 DQL5 +#set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] ;# U63.J3 DQL6 +#set_property -dict {LOC J22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] ;# U63.J7 DQL7 +#set_property -dict {LOC H23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] ;# U63.A3 DQU0 +#set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] ;# U63.B8 DQU1 +#set_property -dict {LOC E23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] ;# U63.C3 DQU2 +#set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] ;# U63.C7 DQU3 +#set_property -dict {LOC F21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] ;# U63.C2 DQU4 +#set_property -dict {LOC E21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] ;# U63.C8 DQU5 +#set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] ;# U63.D3 DQU6 +#set_property -dict {LOC F23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] ;# U63.D7 DQU7 +#set_property -dict {LOC M20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] ;# U63.G3 DQSL_T +#set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] ;# U63.F3 DQSL_C +#set_property -dict {LOC H24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] ;# U63.B7 DQSU_T +#set_property -dict {LOC G23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] ;# U63.A7 DQSU_C +#set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] ;# U63.E7 DML_B/DBIL_B +#set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] ;# U63.E2 DMU_B/DBIU_B + +#set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] ;# U64.G2 DQL0 +#set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] ;# U64.F7 DQL1 +#set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] ;# U64.H3 DQL2 +#set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] ;# U64.H7 DQL3 +#set_property -dict {LOC B23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] ;# U64.H2 DQL4 +#set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] ;# U64.H8 DQL5 +#set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] ;# U64.J3 DQL6 +#set_property -dict {LOC A21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] ;# U64.J7 DQL7 +#set_property -dict {LOC D7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[72]}] ;# U64.A3 DQU0 +#set_property -dict {LOC C7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[73]}] ;# U64.B8 DQU1 +#set_property -dict {LOC B8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[74]}] ;# U64.C3 DQU2 +#set_property -dict {LOC B7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[75]}] ;# U64.C7 DQU3 +#set_property -dict {LOC C10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[76]}] ;# U64.C2 DQU4 +#set_property -dict {LOC B10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[77]}] ;# U64.C8 DQU5 +#set_property -dict {LOC B11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[78]}] ;# U64.D3 DQU6 +#set_property -dict {LOC A11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[79]}] ;# U64.D7 DQU7 +#set_property -dict {LOC D22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] ;# U64.G3 DQSL_T +#set_property -dict {LOC C22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] ;# U64.F3 DQSL_C +#set_property -dict {LOC A9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] ;# U64.B7 DQSU_T +#set_property -dict {LOC A8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] ;# U64.A7 DQSU_C +#set_property -dict {LOC E24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}] ;# U64.E7 DML_B/DBIL_B +#set_property -dict {LOC C9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[9]}] ;# U64.E2 DMU_B/DBIU_B + +# DDR4 C2 +# 5x MT40A256M16GE-075E +#set_property -dict {LOC AM27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +#set_property -dict {LOC AL27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +#set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +#set_property -dict {LOC AN28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +#set_property -dict {LOC AM28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +#set_property -dict {LOC AP28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +#set_property -dict {LOC AP27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +#set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +#set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +#set_property -dict {LOC AR28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +#set_property -dict {LOC AR27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +#set_property -dict {LOC AV25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +#set_property -dict {LOC AT25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +#set_property -dict {LOC AV28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +#set_property -dict {LOC AU26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +#set_property -dict {LOC AV26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +#set_property -dict {LOC AR25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +#set_property -dict {LOC AU28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +#set_property -dict {LOC AU27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +#set_property -dict {LOC AT26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t}] +#set_property -dict {LOC AT27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c}] +#set_property -dict {LOC AW28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke}] +#set_property -dict {LOC AY29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n}] +#set_property -dict {LOC AN25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +#set_property -dict {LOC BB29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt}] +#set_property -dict {LOC BF29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +#set_property -dict {LOC BD35 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] +#set_property -dict {LOC AR29 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_alert_n}] +#set_property -dict {LOC AY35 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_ten}] + +#set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] ;# U135.G2 DQL0 +#set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] ;# U135.F7 DQL1 +#set_property -dict {LOC BD32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] ;# U135.H3 DQL2 +#set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] ;# U135.H7 DQL3 +#set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] ;# U135.H2 DQL4 +#set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] ;# U135.H8 DQL5 +#set_property -dict {LOC BC31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] ;# U135.J3 DQL6 +#set_property -dict {LOC BD31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] ;# U135.J7 DQL7 +#set_property -dict {LOC BA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] ;# U135.A3 DQU0 +#set_property -dict {LOC BB33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] ;# U135.B8 DQU1 +#set_property -dict {LOC BA30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] ;# U135.C3 DQU2 +#set_property -dict {LOC BA31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] ;# U135.C7 DQU3 +#set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] ;# U135.C2 DQU4 +#set_property -dict {LOC AW32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] ;# U135.C8 DQU5 +#set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] ;# U135.D3 DQU6 +#set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] ;# U135.D7 DQU7 +#set_property -dict {LOC BF30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] ;# U135.G3 DQSL_T +#set_property -dict {LOC BF31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] ;# U135.F3 DQSL_C +#set_property -dict {LOC AY34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] ;# U135.B7 DQSU_T +#set_property -dict {LOC BA34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] ;# U135.A7 DQSU_C +#set_property -dict {LOC BE32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[0]}] ;# U135.E7 DML_B/DBIL_B +#set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[1]}] ;# U135.E2 DMU_B/DBIU_B + +#set_property -dict {LOC AV30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] ;# U136.G2 DQL0 +#set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] ;# U136.F7 DQL1 +#set_property -dict {LOC AU33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] ;# U136.H3 DQL2 +#set_property -dict {LOC AU34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] ;# U136.H7 DQL3 +#set_property -dict {LOC AT31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] ;# U136.H2 DQL4 +#set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] ;# U136.H8 DQL5 +#set_property -dict {LOC AU31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] ;# U136.J3 DQL6 +#set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] ;# U136.J7 DQL7 +#set_property -dict {LOC AR33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] ;# U136.A3 DQU0 +#set_property -dict {LOC AT34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] ;# U136.B8 DQU1 +#set_property -dict {LOC AT29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] ;# U136.C3 DQU2 +#set_property -dict {LOC AT30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] ;# U136.C7 DQU3 +#set_property -dict {LOC AP30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] ;# U136.C2 DQU4 +#set_property -dict {LOC AR30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] ;# U136.C8 DQU5 +#set_property -dict {LOC AN30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] ;# U136.D3 DQU6 +#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] ;# U136.D7 DQU7 +#set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] ;# U136.G3 DQSL_T +#set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] ;# U136.F3 DQSL_C +#set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] ;# U136.B7 DQSU_T +#set_property -dict {LOC AP32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] ;# U136.A7 DQSU_C +#set_property -dict {LOC AV33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[2]}] ;# U136.E7 DML_B/DBIL_B +#set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[3]}] ;# U136.E2 DMU_B/DBIU_B + +#set_property -dict {LOC BE34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] ;# U137.G2 DQL0 +#set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] ;# U137.F7 DQL1 +#set_property -dict {LOC BC35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] ;# U137.H3 DQL2 +#set_property -dict {LOC BC36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] ;# U137.H7 DQL3 +#set_property -dict {LOC BD36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] ;# U137.H2 DQL4 +#set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] ;# U137.H8 DQL5 +#set_property -dict {LOC BF36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] ;# U137.J3 DQL6 +#set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] ;# U137.J7 DQL7 +#set_property -dict {LOC BD37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] ;# U137.A3 DQU0 +#set_property -dict {LOC BE38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] ;# U137.B8 DQU1 +#set_property -dict {LOC BC39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] ;# U137.C3 DQU2 +#set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] ;# U137.C7 DQU3 +#set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] ;# U137.C2 DQU4 +#set_property -dict {LOC BB39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] ;# U137.C8 DQU5 +#set_property -dict {LOC BC38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] ;# U137.D3 DQU6 +#set_property -dict {LOC BD38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] ;# U137.D7 DQU7 +#set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] ;# U137.G3 DQSL_T +#set_property -dict {LOC BF35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] ;# U137.F3 DQSL_C +#set_property -dict {LOC BE39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] ;# U137.B7 DQSU_T +#set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] ;# U137.A7 DQSU_C +#set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[4]}] ;# U137.E7 DML_B/DBIL_B +#set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[5]}] ;# U137.E2 DMU_B/DBIU_B + +#set_property -dict {LOC BB36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] ;# U138.G2 DQL0 +#set_property -dict {LOC BB37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] ;# U138.F7 DQL1 +#set_property -dict {LOC BA39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] ;# U138.H3 DQL2 +#set_property -dict {LOC BA40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] ;# U138.H7 DQL3 +#set_property -dict {LOC AW40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] ;# U138.H2 DQL4 +#set_property -dict {LOC AY40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] ;# U138.H8 DQL5 +#set_property -dict {LOC AY38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] ;# U138.J3 DQL6 +#set_property -dict {LOC AY39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] ;# U138.J7 DQL7 +#set_property -dict {LOC AW35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] ;# U138.A3 DQU0 +#set_property -dict {LOC AW36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] ;# U138.B8 DQU1 +#set_property -dict {LOC AU40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] ;# U138.C3 DQU2 +#set_property -dict {LOC AV40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] ;# U138.C7 DQU3 +#set_property -dict {LOC AU38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] ;# U138.C2 DQU4 +#set_property -dict {LOC AU39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] ;# U138.C8 DQU5 +#set_property -dict {LOC AV38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] ;# U138.D3 DQU6 +#set_property -dict {LOC AV39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] ;# U138.D7 DQU7 +#set_property -dict {LOC BA35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] ;# U138.G3 DQSL_T +#set_property -dict {LOC BA36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] ;# U138.F3 DQSL_C +#set_property -dict {LOC AW37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] ;# U138.B7 DQSU_T +#set_property -dict {LOC AW38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] ;# U138.A7 DQSU_C +#set_property -dict {LOC AY37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[6]}] ;# U138.E7 DML_B/DBIL_B +#set_property -dict {LOC AV35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[7]}] ;# U138.E2 DMU_B/DBIU_B + +#set_property -dict {LOC BF26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] ;# U139.G2 DQL0 +#set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] ;# U139.F7 DQL1 +#set_property -dict {LOC BD28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] ;# U139.H3 DQL2 +#set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] ;# U139.H7 DQL3 +#set_property -dict {LOC BD27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] ;# U139.H2 DQL4 +#set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] ;# U139.H8 DQL5 +#set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] ;# U139.J3 DQL6 +#set_property -dict {LOC BD26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] ;# U139.J7 DQL7 +#set_property -dict {LOC BC25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[72]}] ;# U139.A3 DQU0 +#set_property -dict {LOC BC26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[73]}] ;# U139.B8 DQU1 +#set_property -dict {LOC BB28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[74]}] ;# U139.C3 DQU2 +#set_property -dict {LOC BC28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[75]}] ;# U139.C7 DQU3 +#set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[76]}] ;# U139.C2 DQU4 +#set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[77]}] ;# U139.C8 DQU5 +#set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[78]}] ;# U139.D3 DQU6 +#set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[79]}] ;# U139.D7 DQU7 +#set_property -dict {LOC BE25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] ;# U139.G3 DQSL_T +#set_property -dict {LOC BF25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] ;# U139.F3 DQSL_C +#set_property -dict {LOC BA26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] ;# U139.B7 DQSU_T +#set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] ;# U139.A7 DQSU_C +#set_property -dict {LOC BE29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[8]}] ;# U139.E7 DML_B/DBIL_B +#set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[9]}] ;# U139.E2 DMU_B/DBIU_B + # QSPI flash #set_property -dict {LOC AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}] #set_property -dict {LOC AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}] diff --git a/fpga/lib/eth/example/VCU118/fpga_25g/fpga/Makefile b/fpga/lib/eth/example/VCU118/fpga_25g/fpga/Makefile index d4f4ee3a7..81d9f3750 100644 --- a/fpga/lib/eth/example/VCU118/fpga_25g/fpga/Makefile +++ b/fpga/lib/eth/example/VCU118/fpga_25g/fpga/Makefile @@ -67,6 +67,9 @@ XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl IP_TCL_FILES += ip/eth_xcvr_gt.tcl +# Configuration +CONFIG_TCL_FILES = ./config.tcl + include ../common/vivado.mk program: $(FPGA_TOP).bit diff --git a/fpga/lib/eth/example/VCU118/fpga_25g/fpga/config.tcl b/fpga/lib/eth/example/VCU118/fpga_25g/fpga/config.tcl new file mode 100644 index 000000000..1fda15c32 --- /dev/null +++ b/fpga/lib/eth/example/VCU118/fpga_25g/fpga/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {156.25} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/fpga/Makefile b/fpga/lib/eth/example/VCU118/fpga_25g/fpga_10g/Makefile similarity index 99% rename from fpga/lib/eth/example/VCU118/fpga_10g/fpga/Makefile rename to fpga/lib/eth/example/VCU118/fpga_25g/fpga_10g/Makefile index d4f4ee3a7..81d9f3750 100644 --- a/fpga/lib/eth/example/VCU118/fpga_10g/fpga/Makefile +++ b/fpga/lib/eth/example/VCU118/fpga_25g/fpga_10g/Makefile @@ -67,6 +67,9 @@ XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl IP_TCL_FILES += ip/eth_xcvr_gt.tcl +# Configuration +CONFIG_TCL_FILES = ./config.tcl + include ../common/vivado.mk program: $(FPGA_TOP).bit diff --git a/fpga/lib/eth/example/VCU118/fpga_25g/fpga_10g/config.tcl b/fpga/lib/eth/example/VCU118/fpga_25g/fpga_10g/config.tcl new file mode 100644 index 000000000..9b95d246e --- /dev/null +++ b/fpga/lib/eth/example/VCU118/fpga_25g/fpga_10g/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {156.25} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/VCU118/fpga_25g/rtl/fpga.v b/fpga/lib/eth/example/VCU118/fpga_25g/rtl/fpga.v index 721117efb..9a9154f1e 100644 --- a/fpga/lib/eth/example/VCU118/fpga_25g/rtl/fpga.v +++ b/fpga/lib/eth/example/VCU118/fpga_25g/rtl/fpga.v @@ -104,8 +104,8 @@ module fpga ( output wire qsfp2_tx4_n, input wire qsfp2_rx4_p, input wire qsfp2_rx4_n, - input wire qsfp2_mgt_refclk_0_p, - input wire qsfp2_mgt_refclk_0_n, + // input wire qsfp2_mgt_refclk_0_p, + // input wire qsfp2_mgt_refclk_0_n, // input wire qsfp2_mgt_refclk_1_p, // input wire qsfp2_mgt_refclk_1_n, // output wire qsfp2_recclk_p, @@ -600,16 +600,6 @@ wire qsfp2_rx_block_lock_2; wire qsfp2_rx_block_lock_3; wire qsfp2_rx_block_lock_4; -wire qsfp2_mgt_refclk_0; - -IBUFDS_GTE4 ibufds_gte4_qsfp2_mgt_refclk_0_inst ( - .I (qsfp2_mgt_refclk_0_p), - .IB (qsfp2_mgt_refclk_0_n), - .CEB (1'b0), - .O (qsfp2_mgt_refclk_0), - .ODIV2 () -); - wire qsfp2_qpll0lock; wire qsfp2_qpll0outclk; wire qsfp2_qpll0outrefclk; @@ -628,7 +618,7 @@ qsfp2_phy_1_inst ( .xcvr_gtpowergood_out(), // PLL out - .xcvr_gtrefclk00_in(qsfp2_mgt_refclk_0), + .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_0), .xcvr_qpll0lock_out(qsfp2_qpll0lock), .xcvr_qpll0outclk_out(qsfp2_qpll0outclk), .xcvr_qpll0outrefclk_out(qsfp2_qpll0outrefclk), diff --git a/fpga/lib/eth/example/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py index 0b751835f..b2ed1bb51 100644 --- a/fpga/lib/eth/example/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -58,45 +58,21 @@ class TB: dut.phy_gmii_clk_en.setimmediatevalue(1) - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_1, 2.56, units="ns").start()) - self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_1, 2.56, units="ns").start()) - self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1) + self.qsfp_source = [] + self.qsfp_sink = [] - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_2, 2.56, units="ns").start()) - self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_2, 2.56, units="ns").start()) - self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_3, 2.56, units="ns").start()) - self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_3, 2.56, units="ns").start()) - self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_4, 2.56, units="ns").start()) - self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 2.56, units="ns").start()) - self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4) - - cocotb.start_soon(Clock(dut.qsfp2_rx_clk_1, 2.56, units="ns").start()) - self.qsfp2_1_source = XgmiiSource(dut.qsfp2_rxd_1, dut.qsfp2_rxc_1, dut.qsfp2_rx_clk_1, dut.qsfp2_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp2_tx_clk_1, 2.56, units="ns").start()) - self.qsfp2_1_sink = XgmiiSink(dut.qsfp2_txd_1, dut.qsfp2_txc_1, dut.qsfp2_tx_clk_1, dut.qsfp2_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp2_rx_clk_2, 2.56, units="ns").start()) - self.qsfp2_2_source = XgmiiSource(dut.qsfp2_rxd_2, dut.qsfp2_rxc_2, dut.qsfp2_rx_clk_2, dut.qsfp2_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp2_tx_clk_2, 2.56, units="ns").start()) - self.qsfp2_2_sink = XgmiiSink(dut.qsfp2_txd_2, dut.qsfp2_txc_2, dut.qsfp2_tx_clk_2, dut.qsfp2_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp2_rx_clk_3, 2.56, units="ns").start()) - self.qsfp2_3_source = XgmiiSource(dut.qsfp2_rxd_3, dut.qsfp2_rxc_3, dut.qsfp2_rx_clk_3, dut.qsfp2_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp2_tx_clk_3, 2.56, units="ns").start()) - self.qsfp2_3_sink = XgmiiSink(dut.qsfp2_txd_3, dut.qsfp2_txc_3, dut.qsfp2_tx_clk_3, dut.qsfp2_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp2_rx_clk_4, 2.56, units="ns").start()) - self.qsfp2_4_source = XgmiiSource(dut.qsfp2_rxd_4, dut.qsfp2_rxc_4, dut.qsfp2_rx_clk_4, dut.qsfp2_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp2_tx_clk_4, 2.56, units="ns").start()) - self.qsfp2_4_sink = XgmiiSink(dut.qsfp2_txd_4, dut.qsfp2_txc_4, dut.qsfp2_tx_clk_4, dut.qsfp2_tx_rst_4) + for x in range(1, 3): + sources = [] + sinks = [] + for y in range(1, 5): + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_rx_clk_{y}"), 2.56, units="ns").start()) + source = XgmiiSource(getattr(dut, f"qsfp{x}_rxd_{y}"), getattr(dut, f"qsfp{x}_rxc_{y}"), getattr(dut, f"qsfp{x}_rx_clk_{y}"), getattr(dut, f"qsfp{x}_rx_rst_{y}")) + sources.append(source) + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_tx_clk_{y}"), 2.56, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"qsfp{x}_txd_{y}"), getattr(dut, f"qsfp{x}_txc_{y}"), getattr(dut, f"qsfp{x}_tx_clk_{y}"), getattr(dut, f"qsfp{x}_tx_rst_{y}")) + sinks.append(sink) + self.qsfp_source.append(sources) + self.qsfp_sink.append(sinks) dut.btnu.setimmediatevalue(0) dut.btnl.setimmediatevalue(0) @@ -111,66 +87,30 @@ class TB: self.dut.rst.setimmediatevalue(0) self.dut.phy_gmii_rst.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) - self.dut.qsfp2_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp2_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp2_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp2_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp2_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp2_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp2_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp2_tx_rst_4.setimmediatevalue(0) + for x in range(1, 3): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(0) + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(0) for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 1 self.dut.phy_gmii_rst.value = 1 - self.dut.qsfp1_rx_rst_1.value = 1 - self.dut.qsfp1_tx_rst_1.value = 1 - self.dut.qsfp1_rx_rst_2.value = 1 - self.dut.qsfp1_tx_rst_2.value = 1 - self.dut.qsfp1_rx_rst_3.value = 1 - self.dut.qsfp1_tx_rst_3.value = 1 - self.dut.qsfp1_rx_rst_4.value = 1 - self.dut.qsfp1_tx_rst_4.value = 1 - self.dut.qsfp2_rx_rst_1.value = 1 - self.dut.qsfp2_tx_rst_1.value = 1 - self.dut.qsfp2_rx_rst_2.value = 1 - self.dut.qsfp2_tx_rst_2.value = 1 - self.dut.qsfp2_rx_rst_3.value = 1 - self.dut.qsfp2_tx_rst_3.value = 1 - self.dut.qsfp2_rx_rst_4.value = 1 - self.dut.qsfp2_tx_rst_4.value = 1 + for x in range(1, 3): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").value = 1 + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").value = 1 for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 0 self.dut.phy_gmii_rst.value = 0 - self.dut.qsfp1_rx_rst_1.value = 0 - self.dut.qsfp1_tx_rst_1.value = 0 - self.dut.qsfp1_rx_rst_2.value = 0 - self.dut.qsfp1_tx_rst_2.value = 0 - self.dut.qsfp1_rx_rst_3.value = 0 - self.dut.qsfp1_tx_rst_3.value = 0 - self.dut.qsfp1_rx_rst_4.value = 0 - self.dut.qsfp1_tx_rst_4.value = 0 - self.dut.qsfp2_rx_rst_1.value = 0 - self.dut.qsfp2_tx_rst_1.value = 0 - self.dut.qsfp2_rx_rst_2.value = 0 - self.dut.qsfp2_tx_rst_2.value = 0 - self.dut.qsfp2_rx_rst_3.value = 0 - self.dut.qsfp2_tx_rst_3.value = 0 - self.dut.qsfp2_rx_rst_4.value = 0 - self.dut.qsfp2_tx_rst_4.value = 0 + for x in range(1, 3): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").value = 0 + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").value = 0 @cocotb.test() @@ -190,11 +130,11 @@ async def run_test(dut): test_frame = XgmiiFrame.from_payload(test_pkt.build()) - await tb.qsfp1_1_source.send(test_frame) + await tb.qsfp_source[0][0].send(test_frame) tb.log.info("receive ARP request") - rx_frame = await tb.qsfp1_1_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -222,11 +162,11 @@ async def run_test(dut): resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - await tb.qsfp1_1_source.send(resp_frame) + await tb.qsfp_source[0][0].send(resp_frame) tb.log.info("receive UDP packet") - rx_frame = await tb.qsfp1_1_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -259,13 +199,13 @@ async def run_test(dut): tb.log.info("loop back packet on XGMII interface") - rx_frame = await tb.qsfp1_1_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) tb.log.info("RX packet: %s", repr(rx_pkt)) - await tb.qsfp1_1_source.send(rx_frame) + await tb.qsfp_source[0][0].send(rx_frame) tb.log.info("receive UDP packet") @@ -302,13 +242,13 @@ async def run_test(dut): tb.log.info("loop back packet on XGMII interface") - rx_frame = await tb.qsfp1_1_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) tb.log.info("RX packet: %s", repr(rx_pkt)) - await tb.qsfp1_1_source.send(rx_frame) + await tb.qsfp_source[0][0].send(rx_frame) tb.log.info("receive UDP packet") diff --git a/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/README.md b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/README.md new file mode 100644 index 000000000..80409dc04 --- /dev/null +++ b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/README.md @@ -0,0 +1,30 @@ +# Verilog Ethernet VCU118 + HTG 6x QSFP28 FMC+ Example Design + +## Introduction + +This example design targets the Xilinx VCU118 FPGA board with the HiTech Global HTG-FMC-X6QSFP28 FMC+ board installed on J22. + +The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. The design also enables the gigabit Ethernet interface for testing with a QSFP loopback adapter. + +The design is configured to run all 8 QSFP28 modules synchronous to the QSFP Si570 (U38) on the VCU118. This is done by forwarding the MGT reference clock for QSFP1 through the FPGA to the SYNC_C2M pins on the FMC+, which is connected as a reference input to the Si5341 PLL (U7) on the FMC+. + +* FPGA: xcvu9p-flga2104-2L-e +* PHY: 25G BASE-R PHY IP core and internal GTY transceiver + +## How to build + +Run make to build. Ensure that the Xilinx Vivado toolchain components are in PATH. + +## How to test + +Run make program to program the VCU118 board with Vivado. Then run + + netcat -u 192.168.1.128 1234 + +to open a UDP connection to port 1234. Any text entered into netcat will be echoed back after pressing enter. + +It is also possible to use hping to test the design by running + + hping 192.168.1.128 -2 -p 1234 -d 1024 + +Note that the gigabit PHY is also enabled for debugging. The gigabit port can be inserted into the 25G data path between the 25G MAC and 25G PHY so that the 25G interface can be tested with a QSFP loopback adapter. Turn on SW12.1 to insert the gigabit port into the 25G data path, or off to bypass the gigabit port. Turn on SW12.2 to place the port in the TX path or off to place the port in the RX path. diff --git a/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/common/vivado.mk b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/common/vivado.mk new file mode 100644 index 000000000..1402e2382 --- /dev/null +++ b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/common/vivado.mk @@ -0,0 +1,137 @@ +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - space-separated list of source files +# INC_FILES - space-separated list of include files +# XDC_FILES - space-separated list of timing constraint files +# XCI_FILES - space-separated list of IP XCI files +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: fpga vivado tmpclean clean distclean + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include ../$(CONFIG) + +FPGA_TOP ?= fpga +PROJECT ?= $(FPGA_TOP) + +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) + +ifdef XDC_FILES + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +else + XDC_FILES_REL = $(PROJECT).xdc +endif + +################################################################### +# Main Targets +# +# all: build everything +# clean: remove output files and project files +################################################################### + +all: fpga + +fpga: $(PROJECT).bit + +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr + +tmpclean:: + -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean:: tmpclean + -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt + +distclean:: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file +create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ + echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ + echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ + echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ + for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl + vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) + +# synthesis run +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr + echo "open_project $(PROJECT).xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp + echo "open_project $(PROJECT).xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + echo "open_run impl_1" >> run_impl.tcl + echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl + echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# bit file +$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp + echo "open_project $(PROJECT).xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl + echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi + mkdir -p rev + COUNT=100; \ + while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc new file mode 100644 index 000000000..fb3596a51 --- /dev/null +++ b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc @@ -0,0 +1,964 @@ +# XDC constraints for the Xilinx VCU118 board +# part: xcvu9p-flga2104-2L-e + +# General configuration +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] + +# System clocks +# 300 MHz +#set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_p] +#set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_n] +#create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p] + +# 250 MHz +#set_property -dict {LOC E12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_p] +#set_property -dict {LOC D12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_n] +#create_clock -period 4 -name clk_250mhz_1 [get_ports clk_250mhz_1_p] + +#set_property -dict {LOC AW26 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_p] +#set_property -dict {LOC AW27 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_n] +#create_clock -period 4 -name clk_250mhz_2 [get_ports clk_250mhz_2_p] + +# 125 MHz +set_property -dict {LOC AY24 IOSTANDARD LVDS} [get_ports clk_125mhz_p] +set_property -dict {LOC AY23 IOSTANDARD LVDS} [get_ports clk_125mhz_n] +create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p] + +# 90 MHz +#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz] +#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz] + +# LEDs +set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] +set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] +set_property -dict {LOC AY30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}] +set_property -dict {LOC BB32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[3]}] +set_property -dict {LOC BF32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[4]}] +set_property -dict {LOC AU37 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[5]}] +set_property -dict {LOC AV36 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[6]}] +set_property -dict {LOC BA37 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[7]}] + +set_false_path -to [get_ports {led[*]}] +set_output_delay 0 [get_ports {led[*]}] + +# Reset button +set_property -dict {LOC L19 IOSTANDARD LVCMOS12} [get_ports reset] + +set_false_path -from [get_ports {reset}] +set_input_delay 0 [get_ports {reset}] + +# Push buttons +set_property -dict {LOC BB24 IOSTANDARD LVCMOS18} [get_ports btnu] +set_property -dict {LOC BF22 IOSTANDARD LVCMOS18} [get_ports btnl] +set_property -dict {LOC BE22 IOSTANDARD LVCMOS18} [get_ports btnd] +set_property -dict {LOC BE23 IOSTANDARD LVCMOS18} [get_ports btnr] +set_property -dict {LOC BD23 IOSTANDARD LVCMOS18} [get_ports btnc] + +set_false_path -from [get_ports {btnu btnl btnd btnr btnc}] +set_input_delay 0 [get_ports {btnu btnl btnd btnr btnc}] + +# DIP switches +set_property -dict {LOC B17 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] +set_property -dict {LOC G16 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] +set_property -dict {LOC J16 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] +set_property -dict {LOC D21 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] + +set_false_path -from [get_ports {sw[*]}] +set_input_delay 0 [get_ports {sw[*]}] + +# PMOD0 +#set_property -dict {LOC AY14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[0]}] +#set_property -dict {LOC AY15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[1]}] +#set_property -dict {LOC AW15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[2]}] +#set_property -dict {LOC AV15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[3]}] +#set_property -dict {LOC AV16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[4]}] +#set_property -dict {LOC AU16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[5]}] +#set_property -dict {LOC AT15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[6]}] +#set_property -dict {LOC AT16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[7]}] + +#set_false_path -to [get_ports {pmod0[*]}] +#set_output_delay 0 [get_ports {pmod0[*]}] + +# PMOD1 +#set_property -dict {LOC N28 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[0]}] +#set_property -dict {LOC M30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[1]}] +#set_property -dict {LOC N30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[2]}] +#set_property -dict {LOC P30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[3]}] +#set_property -dict {LOC P29 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[4]}] +#set_property -dict {LOC L31 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[5]}] +#set_property -dict {LOC M31 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[6]}] +#set_property -dict {LOC R29 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[7]}] + +#set_false_path -to [get_ports {pmod1[*]}] +#set_output_delay 0 [get_ports {pmod1[*]}] + +# UART +set_property -dict {LOC BB21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] +set_property -dict {LOC AW25 IOSTANDARD LVCMOS18} [get_ports uart_rxd] +set_property -dict {LOC BB22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rts] +set_property -dict {LOC AY25 IOSTANDARD LVCMOS18} [get_ports uart_cts] + +set_false_path -to [get_ports {uart_txd uart_rts}] +set_output_delay 0 [get_ports {uart_txd uart_rts}] +set_false_path -from [get_ports {uart_rxd uart_cts}] +set_input_delay 0 [get_ports {uart_rxd uart_cts}] + +# Gigabit Ethernet SGMII PHY +set_property -dict {LOC AU24 IOSTANDARD LVDS} [get_ports phy_sgmii_rx_p] +set_property -dict {LOC AV24 IOSTANDARD LVDS} [get_ports phy_sgmii_rx_n] +set_property -dict {LOC AU21 IOSTANDARD LVDS} [get_ports phy_sgmii_tx_p] +set_property -dict {LOC AV21 IOSTANDARD LVDS} [get_ports phy_sgmii_tx_n] +set_property -dict {LOC AT22 IOSTANDARD LVDS} [get_ports phy_sgmii_clk_p] +set_property -dict {LOC AU22 IOSTANDARD LVDS} [get_ports phy_sgmii_clk_n] +set_property -dict {LOC BA21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_reset_n] +set_property -dict {LOC AR24 IOSTANDARD LVCMOS18} [get_ports phy_int_n] +set_property -dict {LOC AR23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdio] +set_property -dict {LOC AV23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdc] + +# 625 MHz ref clock from SGMII PHY +#create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p] + +set_false_path -to [get_ports {phy_reset_n phy_mdio phy_mdc}] +set_output_delay 0 [get_ports {phy_reset_n phy_mdio phy_mdc}] +set_false_path -from [get_ports {phy_int_n phy_mdio}] +set_input_delay 0 [get_ports {phy_int_n phy_mdio}] + +# QSFP28 Interfaces +set_property -dict {LOC Y2 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC Y1 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V7 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V6 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC W4 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC W3 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V2 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V1 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC P7 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC P6 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC U4 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC U3 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC W9 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U38.4 +set_property -dict {LOC W8 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U38.5 +#set_property -dict {LOC U9 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U57.28 +#set_property -dict {LOC U8 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_231 from U57.29 +#set_property -dict {LOC AM23 IOSTANDARD LVDS} [get_ports qsfp1_recclk_p] ;# to U57.16 +#set_property -dict {LOC AM22 IOSTANDARD LVDS} [get_ports qsfp1_recclk_n] ;# to U57.17 +set_property -dict {LOC AM21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_modsell] +set_property -dict {LOC BA22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl] +set_property -dict {LOC AL21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_modprsl] +set_property -dict {LOC AP21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_intl] +set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode] + +# 156.25 MHz MGT reference clock +create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p] + +set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}] +set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}] +set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] +set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] + +set_property -dict {LOC T2 } [get_ports qsfp2_rx1_p] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC T1 } [get_ports qsfp2_rx1_n] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC L5 } [get_ports qsfp2_tx1_p] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC L4 } [get_ports qsfp2_tx1_n] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC R4 } [get_ports qsfp2_rx2_p] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC R3 } [get_ports qsfp2_rx2_n] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC K7 } [get_ports qsfp2_tx2_p] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC K6 } [get_ports qsfp2_tx2_n] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC P2 } [get_ports qsfp2_rx3_p] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC P1 } [get_ports qsfp2_rx3_n] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC J5 } [get_ports qsfp2_tx3_p] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC J4 } [get_ports qsfp2_tx3_n] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC M2 } [get_ports qsfp2_rx4_p] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC M1 } [get_ports qsfp2_rx4_n] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC H7 } [get_ports qsfp2_tx4_p] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC H6 } [get_ports qsfp2_tx4_n] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13 +#set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14 +#set_property -dict {LOC N9 } [get_ports qsfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_232 from U57.35 +#set_property -dict {LOC N8 } [get_ports qsfp2_mgt_refclk_1_n] ;# MGTREFCLK1N_232 from U57.34 +#set_property -dict {LOC AP23 IOSTANDARD LVDS} [get_ports qsfp2_recclk_p] ;# to U57.12 +#set_property -dict {LOC AP22 IOSTANDARD LVDS} [get_ports qsfp2_recclk_n] ;# to U57.13 +set_property -dict {LOC AN23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_modsell] +set_property -dict {LOC AY22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_resetl] +set_property -dict {LOC AN24 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp2_modprsl] +set_property -dict {LOC AT21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp2_intl] +set_property -dict {LOC AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_lpmode] + +# 156.25 MHz MGT reference clock +#create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p] + +set_false_path -to [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}] +set_output_delay 0 [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}] +set_false_path -from [get_ports {qsfp2_modprsl qsfp2_intl}] +set_input_delay 0 [get_ports {qsfp2_modprsl qsfp2_intl}] + +# I2C interface +set_property -dict {LOC AM24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_scl] +set_property -dict {LOC AL24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_sda] + +set_false_path -to [get_ports {i2c_sda i2c_scl}] +set_output_delay 0 [get_ports {i2c_sda i2c_scl}] +set_false_path -from [get_ports {i2c_sda i2c_scl}] +set_input_delay 0 [get_ports {i2c_sda i2c_scl}] + +# PCIe Interface +#set_property -dict {LOC AA4 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AA3 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC Y7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC Y6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AB7 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AB6 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AC4 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AC3 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AN5 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AN4 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR5 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR4 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU5 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU4 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AW5 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AW4 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BA5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BA4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AY2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AY1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BC5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BC4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BB2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BB1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BE5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BE4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AC9 } [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_227 +#set_property -dict {LOC AC8 } [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_227 +#set_property -dict {LOC AL9 } [get_ports pcie_refclk_2_p] ;# MGTREFCLK0P_225 +#set_property -dict {LOC AL8 } [get_ports pcie_refclk_2_n] ;# MGTREFCLK0N_225 +#set_property -dict {LOC AM17 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n] + +# 100 MHz MGT reference clock +#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p] +#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports pcie_refclk_2_p] + +#set_false_path -from [get_ports {pcie_reset_n}] +#set_input_delay 0 [get_ports {pcie_reset_n}] + +# FMC+ J22 +set_property -dict {LOC AL35 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp1_lpmode] ;# J22.G9 LA00_P_CC +set_property -dict {LOC AL36 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp6_resetl] ;# J22.G10 LA00_N_CC +set_property -dict {LOC AL30 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp1_modprsl] ;# J22.D8 LA01_P_CC +set_property -dict {LOC AL31 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp1_intl] ;# J22.D9 LA01_N_CC +set_property -dict {LOC AJ32 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp6_modsell] ;# J22.H7 LA02_P +set_property -dict {LOC AK32 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp6_modprsl] ;# J22.H8 LA02_N +set_property -dict {LOC AT39 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp6_intl] ;# J22.G12 LA03_P +set_property -dict {LOC AT40 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp5_modsell] ;# J22.G13 LA03_N +set_property -dict {LOC AR37 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp6_lpmode] ;# J22.H10 LA04_P +set_property -dict {LOC AT37 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp5_resetl] ;# J22.H11 LA04_N +set_property -dict {LOC AP38 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp1_modsell] ;# J22.D11 LA05_P +set_property -dict {LOC AR38 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp2_intl] ;# J22.D12 LA05_N +set_property -dict {LOC AT35 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp1_resetl] ;# J22.C10 LA06_P +set_property -dict {LOC AT36 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp2_lpmode] ;# J22.C11 LA06_N +set_property -dict {LOC AP36 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp4_modprsl] ;# J22.H13 LA07_P +set_property -dict {LOC AP37 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp4_modsell] ;# J22.H14 LA07_N +set_property -dict {LOC AK29 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp4_lpmode] ;# J22.G12 LA08_P +set_property -dict {LOC AK30 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp4_intl] ;# J22.G13 LA08_N +set_property -dict {LOC AJ33 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp2_modprsl] ;# J22.D14 LA09_P +set_property -dict {LOC AK33 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp2_modsell] ;# J22.D15 LA09_N +set_property -dict {LOC AP35 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp2_resetl] ;# J22.C14 LA10_P +set_property -dict {LOC AR35 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp3_lpmode] ;# J22.C15 LA10_N +set_property -dict {LOC AJ30 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp5_intl] ;# J22.H16 LA11_P +set_property -dict {LOC AJ31 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp5_modprsl] ;# J22.H17 LA11_N +set_property -dict {LOC AH33 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp4_resetl] ;# J22.G15 LA12_P +set_property -dict {LOC AH34 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp5_lpmode] ;# J22.G16 LA12_N +set_property -dict {LOC AJ35 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp3_intl] ;# J22.D17 LA13_P +set_property -dict {LOC AJ36 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp3_modprsl] ;# J22.D18 LA13_N +set_property -dict {LOC AG31 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp3_modsell] ;# J22.C18 LA14_P +set_property -dict {LOC AH31 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp3_resetl] ;# J22.C19 LA14_N +set_property -dict {LOC AG32 IOSTANDARD LVCMOS18} [get_ports fmcp_clk_finc] ;# J22.H19 LA15_P +set_property -dict {LOC AG33 IOSTANDARD LVCMOS18} [get_ports fmcp_clk_fdec] ;# J22.H20 LA15_N +set_property -dict {LOC AG34 IOSTANDARD LVCMOS18} [get_ports fmcp_clk_rst_n] ;# J22.G18 LA16_P +set_property -dict {LOC AH35 IOSTANDARD LVCMOS18} [get_ports fmcp_clk_lol_n] ;# J22.G19 LA16_N +set_property -dict {LOC R34 IOSTANDARD LVCMOS18} [get_ports fmcp_clk_sync_n] ;# J22.D20 LA17_P_CC +set_property -dict {LOC P34 IOSTANDARD LVCMOS18} [get_ports fmcp_clk_intr_n] ;# J22.D21 LA17_N_CC +#set_property -dict {LOC R31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[18]}] ;# J22.C22 LA18_P_CC +#set_property -dict {LOC P31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[18]}] ;# J22.C23 LA18_N_CC +#set_property -dict {LOC N33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[19]}] ;# J22.H22 LA19_P +#set_property -dict {LOC M33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[19]}] ;# J22.H23 LA19_N +#set_property -dict {LOC N32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[20]}] ;# J22.G21 LA20_P +#set_property -dict {LOC M32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[20]}] ;# J22.G22 LA20_N +#set_property -dict {LOC M35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[21]}] ;# J22.H25 LA21_P +#set_property -dict {LOC L35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[21]}] ;# J22.H26 LA21_N +#set_property -dict {LOC N34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[22]}] ;# J22.G24 LA22_P +#set_property -dict {LOC N35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[22]}] ;# J22.G25 LA22_N +#set_property -dict {LOC Y32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[23]}] ;# J22.D23 LA23_P +#set_property -dict {LOC W32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[23]}] ;# J22.D24 LA23_N +#set_property -dict {LOC T34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[24]}] ;# J22.H28 LA24_P +#set_property -dict {LOC T35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[24]}] ;# J22.H29 LA24_N +#set_property -dict {LOC Y34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[25]}] ;# J22.G27 LA25_P +#set_property -dict {LOC W34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[25]}] ;# J22.G28 LA25_N +#set_property -dict {LOC V32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[26]}] ;# J22.D26 LA26_P +#set_property -dict {LOC U33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[26]}] ;# J22.D27 LA26_N +#set_property -dict {LOC V33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[27]}] ;# J22.C26 LA27_P +#set_property -dict {LOC V34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[27]}] ;# J22.C27 LA27_N +#set_property -dict {LOC M36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[28]}] ;# J22.H31 LA28_P +#set_property -dict {LOC L36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[28]}] ;# J22.H32 LA28_N +#set_property -dict {LOC U35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[29]}] ;# J22.G30 LA29_P +#set_property -dict {LOC T36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[29]}] ;# J22.G31 LA29_N +#set_property -dict {LOC N38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[30]}] ;# J22.H34 LA30_P +#set_property -dict {LOC M38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[30]}] ;# J22.H35 LA30_N +#set_property -dict {LOC P37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[31]}] ;# J22.G33 LA31_P +#set_property -dict {LOC N37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[31]}] ;# J22.G34 LA31_N +#set_property -dict {LOC L33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[32]}] ;# J22.H37 LA32_P +#set_property -dict {LOC K33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[32]}] ;# J22.H38 LA32_N +#set_property -dict {LOC L34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[33]}] ;# J22.G36 LA33_P +#set_property -dict {LOC K34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[33]}] ;# J22.G37 LA33_N + +#set_property -dict {LOC N14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[0]}] ;# J22.F4 HA00_P_CC +#set_property -dict {LOC N13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[0]}] ;# J22.F5 HA00_N_CC +#set_property -dict {LOC V15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[1]}] ;# J22.E2 HA01_P_CC +#set_property -dict {LOC U15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[1]}] ;# J22.E3 HA01_N_CC +#set_property -dict {LOC AA12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[2]}] ;# J22.K7 HA02_P +#set_property -dict {LOC Y12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[2]}] ;# J22.K8 HA02_N +#set_property -dict {LOC W12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[3]}] ;# J22.J6 HA03_P +#set_property -dict {LOC V12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[3]}] ;# J22.J7 HA03_N +#set_property -dict {LOC AA13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[4]}] ;# J22.F7 HA04_P +#set_property -dict {LOC Y13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[4]}] ;# J22.F8 HA04_N +#set_property -dict {LOC R14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[5]}] ;# J22.E6 HA05_P +#set_property -dict {LOC P14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[5]}] ;# J22.E7 HA05_N +#set_property -dict {LOC U13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[6]}] ;# J22.K10 HA06_P +#set_property -dict {LOC T13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[6]}] ;# J22.K11 HA06_N +#set_property -dict {LOC AA14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[7]}] ;# J22.J9 HA07_P +#set_property -dict {LOC Y14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[7]}] ;# J22.J10 HA07_N +#set_property -dict {LOC U11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[8]}] ;# J22.F10 HA08_P +#set_property -dict {LOC T11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[8]}] ;# J22.F11 HA08_N +#set_property -dict {LOC W14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[9]}] ;# J22.E9 HA09_P +#set_property -dict {LOC V14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[9]}] ;# J22.E10 HA09_N +#set_property -dict {LOC V16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[10]}] ;# J22.K13 HA10_P +#set_property -dict {LOC U16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[10]}] ;# J22.K14 HA10_N +#set_property -dict {LOC R12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[11]}] ;# J22.J12 HA11_P +#set_property -dict {LOC P12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[11]}] ;# J22.J13 HA11_N +#set_property -dict {LOC T16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[12]}] ;# J22.F13 HA12_P +#set_property -dict {LOC T15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[12]}] ;# J22.F14 HA12_N +#set_property -dict {LOC V13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[13]}] ;# J22.E12 HA13_P +#set_property -dict {LOC U12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[13]}] ;# J22.E13 HA13_N +#set_property -dict {LOC M11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[14]}] ;# J22.J15 HA14_P +#set_property -dict {LOC L11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[14]}] ;# J22.J16 HA14_N +#set_property -dict {LOC M13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[15]}] ;# J22.F14 HA15_P +#set_property -dict {LOC M12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[15]}] ;# J22.F16 HA15_N +#set_property -dict {LOC T14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[16]}] ;# J22.E15 HA16_P +#set_property -dict {LOC R13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[16]}] ;# J22.E16 HA16_N +#set_property -dict {LOC R11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[17]}] ;# J22.K16 HA17_P_CC +#set_property -dict {LOC P11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[17]}] ;# J22.K17 HA17_N_CC +#set_property -dict {LOC P15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[18]}] ;# J22.J18 HA18_P_CC +#set_property -dict {LOC N15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[18]}] ;# J22.J19 HA18_N_CC +#set_property -dict {LOC L14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[19]}] ;# J22.F19 HA19_P +#set_property -dict {LOC L13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[19]}] ;# J22.F20 HA19_N +#set_property -dict {LOC M15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[20]}] ;# J22.E18 HA20_P +#set_property -dict {LOC L15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[20]}] ;# J22.E19 HA20_N +#set_property -dict {LOC K14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[21]}] ;# J22.K19 HA21_P +#set_property -dict {LOC K13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[21]}] ;# J22.K20 HA21_N +#set_property -dict {LOC K12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[22]}] ;# J22.J21 HA22_P +#set_property -dict {LOC J12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[22]}] ;# J22.J22 HA22_N +#set_property -dict {LOC K11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[23]}] ;# J22.K22 HA23_P +#set_property -dict {LOC J11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[23]}] ;# J22.K23 HA23_N + +#set_property -dict {LOC AL32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_clk0_m2c_p}] ;# J22.H4 CLK0_M2C_P +#set_property -dict {LOC AM32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_clk0_m2c_n}] ;# J22.H5 CLK0_M2C_N +#set_property -dict {LOC P35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_clk1_m2c_p}] ;# J22.G2 CLK1_M2C_P +#set_property -dict {LOC P36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_clk1_m2c_n}] ;# J22.G3 CLK1_M2C_N + +#set_property -dict {LOC AN33 IOSTANDARD LVDS } [get_ports {fmcp_hspc_refclk_c2m_p}] ;# J22.L20 REFCLK_C2M_P +#set_property -dict {LOC AP33 IOSTANDARD LVDS } [get_ports {fmcp_hspc_refclk_c2m_n}] ;# J22.L21 REFCLK_C2M_N +#set_property -dict {LOC AK34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_refclk_m2c_p}] ;# J22.L24 REFCLK_M2C_P +#set_property -dict {LOC AL34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_refclk_m2c_n}] ;# J22.L25 REFCLK_M2C_N +set_property -dict {LOC AN34 IOSTANDARD LVDS } [get_ports {fmcp_hspc_sync_c2m_p}] ;# J22.L16 SYNC_C2M_P +set_property -dict {LOC AN35 IOSTANDARD LVDS } [get_ports {fmcp_hspc_sync_c2m_n}] ;# J22.L17 SYNC_C2M_N +#set_property -dict {LOC AM36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_sync_m2c_p}] ;# J22.L28 SYNC_M2C_P +#set_property -dict {LOC AN36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_sync_m2c_n}] ;# J22.L29 SYNC_M2C_N + +#set_property -dict {LOC AL36 IOSTANDARD LVCMOS18} [get_ports {fmcp_hspc_pg_m2c}] ;# J22.F1 PG_M2C +#set_property -dict {LOC AM33 IOSTANDARD LVCMOS18} [get_ports {fmcp_hspc_h_prsnt_m2c_l}] ;# J22.H2 PRSNT_M2C_L +#set_property -dict {LOC AM29 IOSTANDARD LVCMOS18} [get_ports {fmcp_hspc_z_prsnt_m2c_l}] ;# J22.Z1 HSPC_PRSNT_M2C_L + +set_property -dict {LOC AT42} [get_ports {fmcp_qsfp1_tx_p[0]}] ;# MGTYTXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C2 DP0_C2M_P +set_property -dict {LOC AT43} [get_ports {fmcp_qsfp1_tx_n[0]}] ;# MGTYTXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C3 DP0_C2M_N +set_property -dict {LOC AR45} [get_ports {fmcp_qsfp1_rx_p[0]}] ;# MGTYRXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C6 DP0_M2C_P +set_property -dict {LOC AR46} [get_ports {fmcp_qsfp1_rx_n[0]}] ;# MGTYRXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C7 DP0_M2C_N +set_property -dict {LOC AP42} [get_ports {fmcp_qsfp1_tx_p[2]}] ;# MGTYTXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A22 DP1_C2M_P +set_property -dict {LOC AP43} [get_ports {fmcp_qsfp1_tx_n[2]}] ;# MGTYTXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A23 DP1_C2M_N +set_property -dict {LOC AN45} [get_ports {fmcp_qsfp1_rx_p[2]}] ;# MGTYRXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A2 DP1_M2C_P +set_property -dict {LOC AN46} [get_ports {fmcp_qsfp1_rx_n[2]}] ;# MGTYRXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A3 DP1_M2C_N +set_property -dict {LOC AM42} [get_ports {fmcp_qsfp1_tx_p[1]}] ;# MGTYTXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A26 DP2_C2M_P +set_property -dict {LOC AM43} [get_ports {fmcp_qsfp1_tx_n[1]}] ;# MGTYTXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A27 DP2_C2M_N +set_property -dict {LOC AL45} [get_ports {fmcp_qsfp1_rx_p[1]}] ;# MGTYRXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A6 DP2_M2C_P +set_property -dict {LOC AL46} [get_ports {fmcp_qsfp1_rx_n[1]}] ;# MGTYRXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A7 DP2_M2C_N +set_property -dict {LOC AL40} [get_ports {fmcp_qsfp1_tx_p[3]}] ;# MGTYTXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A30 DP3_C2M_P +set_property -dict {LOC AL41} [get_ports {fmcp_qsfp1_tx_n[3]}] ;# MGTYTXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A31 DP3_C2M_N +set_property -dict {LOC AJ45} [get_ports {fmcp_qsfp1_rx_p[3]}] ;# MGTYRXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A10 DP3_M2C_P +set_property -dict {LOC AJ46} [get_ports {fmcp_qsfp1_rx_n[3]}] ;# MGTYRXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A11 DP3_M2C_N +set_property -dict {LOC AK38} [get_ports fmcp_qsfp1_mgt_refclk_p] ;# MGTREFCLK0P_121 from U40.1 Q0 from J22.D4 GBTCLK0_M2C_P +set_property -dict {LOC AK39} [get_ports fmcp_qsfp1_mgt_refclk_n] ;# MGTREFCLK0N_121 from U40.2 NQ0 from J22.D5 GBTCLK0_M2C_N +#set_property -dict {LOC AH38} [get_ports fmcp_hspc_mgt_refclk_0_1_p] ;# MGTREFCLK1P_121 from U39.5 Q0_P from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC AH39} [get_ports fmcp_hspc_mgt_refclk_0_1_n] ;# MGTREFCLK1N_121 from U39.6 Q0_N from J22.B21 GBTCLK1_M2C_N + +# reference clock +create_clock -period 6.400 -name fmcp_qsfp1_mgt_refclk [get_ports fmcp_qsfp1_mgt_refclk_p] +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_0_1 [get_ports fmcp_hspc_mgt_refclk_0_1_p] + +set_property -dict {LOC T42 } [get_ports {fmcp_qsfp6_tx_p[1]}] ;# MGTYTXP0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A34 DP4_C2M_P +set_property -dict {LOC T43 } [get_ports {fmcp_qsfp6_tx_n[1]}] ;# MGTYTXN0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A35 DP4_C2M_N +set_property -dict {LOC W45 } [get_ports {fmcp_qsfp6_rx_p[1]}] ;# MGTYRXP0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A14 DP4_M2C_P +set_property -dict {LOC W46 } [get_ports {fmcp_qsfp6_rx_n[1]}] ;# MGTYRXN0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A15 DP4_M2C_N +set_property -dict {LOC P42 } [get_ports {fmcp_qsfp6_tx_p[0]}] ;# MGTYTXP1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A38 DP5_C2M_P +set_property -dict {LOC P43 } [get_ports {fmcp_qsfp6_tx_n[0]}] ;# MGTYTXN1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A39 DP5_C2M_N +set_property -dict {LOC U45 } [get_ports {fmcp_qsfp6_rx_p[0]}] ;# MGTYRXP1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A18 DP5_M2C_P +set_property -dict {LOC U46 } [get_ports {fmcp_qsfp6_rx_n[0]}] ;# MGTYRXN1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A19 DP5_M2C_N +set_property -dict {LOC M42 } [get_ports {fmcp_qsfp6_tx_p[2]}] ;# MGTYTXP2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B36 DP6_C2M_P +set_property -dict {LOC M43 } [get_ports {fmcp_qsfp6_tx_n[2]}] ;# MGTYTXN2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B37 DP6_C2M_N +set_property -dict {LOC R45 } [get_ports {fmcp_qsfp6_rx_p[2]}] ;# MGTYRXP2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B16 DP6_M2C_P +set_property -dict {LOC R46 } [get_ports {fmcp_qsfp6_rx_n[2]}] ;# MGTYRXN2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B17 DP6_M2C_N +set_property -dict {LOC K42 } [get_ports {fmcp_qsfp6_tx_p[3]}] ;# MGTYTXP3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B32 DP7_C2M_P +set_property -dict {LOC K43 } [get_ports {fmcp_qsfp6_tx_n[3]}] ;# MGTYTXN3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B33 DP7_C2M_N +set_property -dict {LOC N45 } [get_ports {fmcp_qsfp6_rx_p[3]}] ;# MGTYRXP3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B12 DP7_M2C_P +set_property -dict {LOC N46 } [get_ports {fmcp_qsfp6_rx_n[3]}] ;# MGTYRXN3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B13 DP7_M2C_N +set_property -dict {LOC V38 } [get_ports fmcp_qsfp6_mgt_refclk_p] ;# MGTREFCLK0P_126 from U40.3 Q1 from J22.D4 GBTCLK0_M2C_P +set_property -dict {LOC V39 } [get_ports fmcp_qsfp6_mgt_refclk_n] ;# MGTREFCLK0N_126 from U40.4 NQ1 from J22.D5 GBTCLK0_M2C_N +#set_property -dict {LOC T38 } [get_ports fmcp_hspc_mgt_refclk_1_1_p] ;# MGTREFCLK1P_126 from U39.8 Q1_P from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC T39 } [get_ports fmcp_hspc_mgt_refclk_1_1_n] ;# MGTREFCLK1N_126 from U39.9 Q1_N from J22.B21 GBTCLK1_M2C_N + +# reference clock +create_clock -period 6.400 -name fmcp_qsfp6_mgt_refclk [get_ports fmcp_qsfp6_mgt_refclk_p] +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_1_1 [get_ports fmcp_hspc_mgt_refclk_1_1_p] + +set_property -dict {LOC AK42} [get_ports {fmcp_qsfp4_tx_p[3]}] ;# MGTYTXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B28 DP8_C2M_P +set_property -dict {LOC AK43} [get_ports {fmcp_qsfp4_tx_n[3]}] ;# MGTYTXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B29 DP8_C2M_N +set_property -dict {LOC AG45} [get_ports {fmcp_qsfp4_rx_p[3]}] ;# MGTYRXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B8 DP8_M2C_P +set_property -dict {LOC AG46} [get_ports {fmcp_qsfp4_rx_n[3]}] ;# MGTYRXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B9 DP8_M2C_N +set_property -dict {LOC AJ40} [get_ports {fmcp_qsfp4_tx_p[2]}] ;# MGTYTXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B24 DP9_C2M_P +set_property -dict {LOC AJ41} [get_ports {fmcp_qsfp4_tx_n[2]}] ;# MGTYTXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B25 DP9_C2M_N +set_property -dict {LOC AF43} [get_ports {fmcp_qsfp4_rx_p[2]}] ;# MGTYRXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B4 DP9_M2C_P +set_property -dict {LOC AF44} [get_ports {fmcp_qsfp4_rx_n[2]}] ;# MGTYRXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B5 DP9_M2C_N +set_property -dict {LOC AG40} [get_ports {fmcp_qsfp4_tx_p[1]}] ;# MGTYTXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Z24 DP10_C2M_P +set_property -dict {LOC AG41} [get_ports {fmcp_qsfp4_tx_n[1]}] ;# MGTYTXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Z25 DP10_C2M_N +set_property -dict {LOC AE45} [get_ports {fmcp_qsfp4_rx_p[1]}] ;# MGTYRXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Y10 DP10_M2C_P +set_property -dict {LOC AE46} [get_ports {fmcp_qsfp4_rx_n[1]}] ;# MGTYRXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Y11 DP10_M2C_N +set_property -dict {LOC AE40} [get_ports {fmcp_qsfp4_tx_p[0]}] ;# MGTYTXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Y26 DP11_C2M_P +set_property -dict {LOC AE41} [get_ports {fmcp_qsfp4_tx_n[0]}] ;# MGTYTXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Y27 DP11_C2M_N +set_property -dict {LOC AD43} [get_ports {fmcp_qsfp4_rx_p[0]}] ;# MGTYRXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Z12 DP11_M2C_P +set_property -dict {LOC AD44} [get_ports {fmcp_qsfp4_rx_n[0]}] ;# MGTYRXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Z13 DP11_M2C_N +set_property -dict {LOC AF38} [get_ports fmcp_qsfp4_mgt_refclk_p] ;# MGTREFCLK0P_122 from J22.L12 GBTCLK2_M2C_P +set_property -dict {LOC AF39} [get_ports fmcp_qsfp4_mgt_refclk_n] ;# MGTREFCLK0N_122 from J22.L13 GBTCLK2_M2C_N +#set_property -dict {LOC AD38} [get_ports fmcp_hspc_mgt_refclk_2_1_p] ;# MGTREFCLK1P_122 from U39.11 Q2_P from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC AD39} [get_ports fmcp_hspc_mgt_refclk_2_1_n] ;# MGTREFCLK1N_122 from U39.12 Q2_N from J22.B21 GBTCLK1_M2C_N + +# reference clock +create_clock -period 6.400 -name fmcp_qsfp4_mgt_refclk [get_ports fmcp_qsfp4_mgt_refclk_p] +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_2_1 [get_ports fmcp_hspc_mgt_refclk_2_1_p] + +set_property -dict {LOC AC40} [get_ports {fmcp_qsfp3_tx_p[2]}] ;# MGTYTXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Z28 DP12_C2M_P +set_property -dict {LOC AC41} [get_ports {fmcp_qsfp3_tx_n[2]}] ;# MGTYTXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Z29 DP12_C2M_N +set_property -dict {LOC AC45} [get_ports {fmcp_qsfp3_rx_p[2]}] ;# MGTYRXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Y14 DP12_M2C_P +set_property -dict {LOC AC46} [get_ports {fmcp_qsfp3_rx_n[2]}] ;# MGTYRXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Y15 DP12_M2C_N +set_property -dict {LOC AA40} [get_ports {fmcp_qsfp3_tx_p[3]}] ;# MGTYTXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Y30 DP13_C2M_P +set_property -dict {LOC AA41} [get_ports {fmcp_qsfp3_tx_n[3]}] ;# MGTYTXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Y31 DP13_C2M_N +set_property -dict {LOC AB43} [get_ports {fmcp_qsfp3_rx_p[3]}] ;# MGTYRXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Z16 DP13_M2C_P +set_property -dict {LOC AB44} [get_ports {fmcp_qsfp3_rx_n[3]}] ;# MGTYRXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Z17 DP13_M2C_N +set_property -dict {LOC W40 } [get_ports {fmcp_qsfp3_tx_p[1]}] ;# MGTYTXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.M18 DP14_C2M_P +set_property -dict {LOC W41 } [get_ports {fmcp_qsfp3_tx_n[1]}] ;# MGTYTXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.M19 DP14_C2M_N +set_property -dict {LOC AA45} [get_ports {fmcp_qsfp3_rx_p[1]}] ;# MGTYRXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.Y18 DP14_M2C_P +set_property -dict {LOC AA46} [get_ports {fmcp_qsfp3_rx_n[1]}] ;# MGTYRXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.Y19 DP14_M2C_N +set_property -dict {LOC U40 } [get_ports {fmcp_qsfp3_tx_p[0]}] ;# MGTYTXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.M22 DP15_C2M_P +set_property -dict {LOC U41 } [get_ports {fmcp_qsfp3_tx_n[0]}] ;# MGTYTXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.M23 DP15_C2M_N +set_property -dict {LOC Y43 } [get_ports {fmcp_qsfp3_rx_p[0]}] ;# MGTYRXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.Y22 DP15_M2C_P +set_property -dict {LOC Y44 } [get_ports {fmcp_qsfp3_rx_n[0]}] ;# MGTYRXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.Y23 DP15_M2C_N +set_property -dict {LOC AB38} [get_ports fmcp_qsfp3_mgt_refclk_p] ;# MGTREFCLK0P_125 from J22.L8 GBTCLK3_M2C_P +set_property -dict {LOC AB39} [get_ports fmcp_qsfp3_mgt_refclk_n] ;# MGTREFCLK0N_125 from J22.L9 GBTCLK3_M2C_N +#set_property -dict {LOC Y38 } [get_ports fmcp_hspc_mgt_refclk_3_1_p] ;# MGTREFCLK1P_125 from U39.13 Q3_P from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC Y39 } [get_ports fmcp_hspc_mgt_refclk_3_1_n] ;# MGTREFCLK1N_125 from U39.14 Q3_N from J22.B21 GBTCLK1_M2C_N + +# reference clock +create_clock -period 6.400 -name fmcp_qsfp3_mgt_refclk [get_ports fmcp_qsfp3_mgt_refclk_p] +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_3_1 [get_ports fmcp_hspc_mgt_refclk_3_1_p] + +set_property -dict {LOC H42 } [get_ports {fmcp_qsfp5_tx_p[3]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.M26 DP16_C2M_P +set_property -dict {LOC H43 } [get_ports {fmcp_qsfp5_tx_n[3]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.M27 DP16_C2M_N +set_property -dict {LOC L45 } [get_ports {fmcp_qsfp5_rx_p[3]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.Z32 DP16_M2C_P +set_property -dict {LOC L46 } [get_ports {fmcp_qsfp5_rx_n[3]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.Z33 DP16_M2C_N +set_property -dict {LOC F42 } [get_ports {fmcp_qsfp5_tx_p[1]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.M30 DP17_C2M_P +set_property -dict {LOC F43 } [get_ports {fmcp_qsfp5_tx_n[1]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.M31 DP17_C2M_N +set_property -dict {LOC J45 } [get_ports {fmcp_qsfp5_rx_p[1]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.Y34 DP17_M2C_P +set_property -dict {LOC J46 } [get_ports {fmcp_qsfp5_rx_n[1]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.Y35 DP17_M2C_N +set_property -dict {LOC D42 } [get_ports {fmcp_qsfp5_tx_p[2]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.M34 DP18_C2M_P +set_property -dict {LOC D43 } [get_ports {fmcp_qsfp5_tx_n[2]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.M35 DP18_C2M_N +set_property -dict {LOC G45 } [get_ports {fmcp_qsfp5_rx_p[2]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.Z36 DP18_M2C_P +set_property -dict {LOC G46 } [get_ports {fmcp_qsfp5_rx_n[2]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.Z37 DP18_M2C_N +set_property -dict {LOC B42 } [get_ports {fmcp_qsfp5_tx_p[0]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.M38 DP19_C2M_P +set_property -dict {LOC B43 } [get_ports {fmcp_qsfp5_tx_n[0]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.M39 DP19_C2M_N +set_property -dict {LOC E45 } [get_ports {fmcp_qsfp5_rx_p[0]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.Y38 DP19_M2C_P +set_property -dict {LOC E46 } [get_ports {fmcp_qsfp5_rx_n[0]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.Y39 DP19_M2C_N +set_property -dict {LOC R40 } [get_ports fmcp_qsfp5_mgt_refclk_p] ;# MGTREFCLK0P_127 from J22.L4 GBTCLK4_M2C_P +set_property -dict {LOC R41 } [get_ports fmcp_qsfp5_mgt_refclk_n] ;# MGTREFCLK0N_127 from J22.L5 GBTCLK4_M2C_N +#set_property -dict {LOC N40 } [get_ports fmcp_hspc_mgt_refclk_4_1_p] ;# MGTREFCLK1P_127 from U39.16 Q4_P from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC N41 } [get_ports fmcp_hspc_mgt_refclk_4_1_n] ;# MGTREFCLK1N_127 from U39.17 Q4_N from J22.B21 GBTCLK1_M2C_N + +# reference clock +create_clock -period 6.400 -name fmcp_qsfp5_mgt_refclk [get_ports fmcp_qsfp5_mgt_refclk_p] +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_4_1 [get_ports fmcp_hspc_mgt_refclk_4_1_p] + +set_property -dict {LOC BD42} [get_ports {fmcp_qsfp2_tx_p[3]}] ;# MGTYTXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.Z8 DP20_C2M_P +set_property -dict {LOC BD43} [get_ports {fmcp_qsfp2_tx_n[3]}] ;# MGTYTXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.Z9 DP20_C2M_N +set_property -dict {LOC BC45} [get_ports {fmcp_qsfp2_rx_p[3]}] ;# MGTYRXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.M14 DP20_M2C_P +set_property -dict {LOC BC46} [get_ports {fmcp_qsfp2_rx_n[3]}] ;# MGTYRXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.M15 DP20_M2C_N +set_property -dict {LOC BB42} [get_ports {fmcp_qsfp2_tx_p[2]}] ;# MGTYTXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.Y6 DP21_C2M_P +set_property -dict {LOC BB43} [get_ports {fmcp_qsfp2_tx_n[2]}] ;# MGTYTXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.Y7 DP21_C2M_N +set_property -dict {LOC BA45} [get_ports {fmcp_qsfp2_rx_p[2]}] ;# MGTYRXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.M10 DP21_M2C_P +set_property -dict {LOC BA46} [get_ports {fmcp_qsfp2_rx_n[2]}] ;# MGTYRXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.M11 DP21_M2C_N +set_property -dict {LOC AY42} [get_ports {fmcp_qsfp2_tx_p[0]}] ;# MGTYTXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.Z4 DP22_C2M_P +set_property -dict {LOC AY43} [get_ports {fmcp_qsfp2_tx_n[0]}] ;# MGTYTXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.Z5 DP22_C2M_N +set_property -dict {LOC AW45} [get_ports {fmcp_qsfp2_rx_p[0]}] ;# MGTYRXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.M6 DP22_M2C_P +set_property -dict {LOC AW46} [get_ports {fmcp_qsfp2_rx_n[0]}] ;# MGTYRXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.M7 DP22_M2C_N +set_property -dict {LOC AV42} [get_ports {fmcp_qsfp2_tx_p[1]}] ;# MGTYTXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.Y2 DP23_C2M_P +set_property -dict {LOC AV43} [get_ports {fmcp_qsfp2_tx_n[1]}] ;# MGTYTXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.Y3 DP23_C2M_N +set_property -dict {LOC AU45} [get_ports {fmcp_qsfp2_rx_p[1]}] ;# MGTYRXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.M2 DP23_M2C_P +set_property -dict {LOC AU46} [get_ports {fmcp_qsfp2_rx_n[1]}] ;# MGTYRXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.M3 DP23_M2C_N +set_property -dict {LOC AN40} [get_ports fmcp_qsfp2_mgt_refclk_p] ;# MGTREFCLK0P_120 from J22.Z20 GBTCLK5_M2C_P +set_property -dict {LOC AN41} [get_ports fmcp_qsfp2_mgt_refclk_n] ;# MGTREFCLK0N_120 from J22.Z21 GBTCLK5_M2C_N +#set_property -dict {LOC AM38} [get_ports fmcp_hspc_mgt_refclk_5_1_p] ;# MGTREFCLK1P_120 from U39.19 Q5_P from J22.B20 GBTCLK1_M2C_P +#set_property -dict {LOC AM39} [get_ports fmcp_hspc_mgt_refclk_5_1_n] ;# MGTREFCLK1N_120 from U39.20 Q5_N from J22.B21 GBTCLK1_M2C_N + +# reference clock +create_clock -period 6.400 -name fmcp_qsfp2_mgt_refclk [get_ports fmcp_qsfp2_mgt_refclk_p] +#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_5_1 [get_ports fmcp_hspc_mgt_refclk_5_1_p] + +# FMC HPC1 J2 +#set_property -dict {LOC AY9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[0]}] ;# J2.G9 LA00_P_CC +#set_property -dict {LOC BA9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[0]}] ;# J2.G10 LA00_N_CC +#set_property -dict {LOC BF10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[1]}] ;# J2.D8 LA01_P_CC +#set_property -dict {LOC BF9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[1]}] ;# J2.D9 LA01_N_CC +#set_property -dict {LOC BC11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[2]}] ;# J2.H7 LA02_P +#set_property -dict {LOC BD11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[2]}] ;# J2.H8 LA02_N +#set_property -dict {LOC BD12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[3]}] ;# J2.G12 LA03_P +#set_property -dict {LOC BE12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[3]}] ;# J2.G13 LA03_N +#set_property -dict {LOC BD12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[4]}] ;# J2.H10 LA04_P +#set_property -dict {LOC BF11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[4]}] ;# J2.H11 LA04_N +#set_property -dict {LOC BE14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[5]}] ;# J2.D11 LA05_P +#set_property -dict {LOC BF14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[5]}] ;# J2.D12 LA05_N +#set_property -dict {LOC BD13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[6]}] ;# J2.C10 LA06_P +#set_property -dict {LOC BE13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[6]}] ;# J2.C11 LA06_N +#set_property -dict {LOC BC15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[7]}] ;# J2.H13 LA07_P +#set_property -dict {LOC BD15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[7]}] ;# J2.H14 LA07_N +#set_property -dict {LOC BE15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[8]}] ;# J2.G12 LA08_P +#set_property -dict {LOC BF15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[8]}] ;# J2.G13 LA08_N +#set_property -dict {LOC BA14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[9]}] ;# J2.D14 LA09_P +#set_property -dict {LOC BB14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[9]}] ;# J2.D15 LA09_N +#set_property -dict {LOC BB13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[10]}] ;# J2.C14 LA10_P +#set_property -dict {LOC BB12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[10]}] ;# J2.C15 LA10_N +#set_property -dict {LOC BA16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[11]}] ;# J2.H16 LA11_P +#set_property -dict {LOC BA15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[11]}] ;# J2.H17 LA11_N +#set_property -dict {LOC BC14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[12]}] ;# J2.G15 LA12_P +#set_property -dict {LOC BC13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[12]}] ;# J2.G16 LA12_N +#set_property -dict {LOC AY8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[13]}] ;# J2.D17 LA13_P +#set_property -dict {LOC AY7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[13]}] ;# J2.D18 LA13_N +#set_property -dict {LOC AW8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[14]}] ;# J2.C18 LA14_P +#set_property -dict {LOC AW7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[14]}] ;# J2.C19 LA14_N +#set_property -dict {LOC BB16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[15]}] ;# J2.H19 LA15_P +#set_property -dict {LOC BC16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[15]}] ;# J2.H20 LA15_N +#set_property -dict {LOC AV9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[16]}] ;# J2.G18 LA16_P +#set_property -dict {LOC AB8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[16]}] ;# J2.G19 LA16_N +#set_property -dict {LOC AR14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[17]}] ;# J2.D20 LA17_P_CC +#set_property -dict {LOC AT14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[17]}] ;# J2.D21 LA17_N_CC +#set_property -dict {LOC AP12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[18]}] ;# J2.C22 LA18_P_CC +#set_property -dict {LOC AR12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[18]}] ;# J2.C23 LA18_N_CC +#set_property -dict {LOC AW12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[19]}] ;# J2.H22 LA19_P +#set_property -dict {LOC AY12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[19]}] ;# J2.H23 LA19_N +#set_property -dict {LOC AW11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[20]}] ;# J2.G21 LA20_P +#set_property -dict {LOC AY10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[20]}] ;# J2.G22 LA20_N +#set_property -dict {LOC AU11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[21]}] ;# J2.H25 LA21_P +#set_property -dict {LOC AV11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[21]}] ;# J2.H26 LA21_N +#set_property -dict {LOC AW13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[22]}] ;# J2.G24 LA22_P +#set_property -dict {LOC AY13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[22]}] ;# J2.G25 LA22_N +#set_property -dict {LOC AN16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[23]}] ;# J2.D23 LA23_P +#set_property -dict {LOC AP16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[23]}] ;# J2.D24 LA23_N +#set_property -dict {LOC AP13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[24]}] ;# J2.H28 LA24_P +#set_property -dict {LOC AR13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[24]}] ;# J2.H29 LA24_N +#set_property -dict {LOC AT12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[25]}] ;# J2.G27 LA25_P +#set_property -dict {LOC AU12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[25]}] ;# J2.G28 LA25_N +#set_property -dict {LOC AK15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[26]}] ;# J2.D26 LA26_P +#set_property -dict {LOC AL15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[26]}] ;# J2.D27 LA26_N +#set_property -dict {LOC AL14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[27]}] ;# J2.C26 LA27_P +#set_property -dict {LOC AM14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[27]}] ;# J2.C27 LA27_N +#set_property -dict {LOC AV10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[28]}] ;# J2.H31 LA28_P +#set_property -dict {LOC AW10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[28]}] ;# J2.H32 LA28_N +#set_property -dict {LOC AN15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[29]}] ;# J2.G30 LA29_P +#set_property -dict {LOC AP15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[29]}] ;# J2.G31 LA29_N +#set_property -dict {LOC AK12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[30]}] ;# J2.H34 LA30_P +#set_property -dict {LOC AL12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[30]}] ;# J2.H35 LA30_N +#set_property -dict {LOC AM13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[31]}] ;# J2.G33 LA31_P +#set_property -dict {LOC AM12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[31]}] ;# J2.G34 LA31_N +#set_property -dict {LOC AJ13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[32]}] ;# J2.H37 LA32_P +#set_property -dict {LOC AJ12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[32]}] ;# J2.H38 LA32_N +#set_property -dict {LOC AK14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[33]}] ;# J2.G36 LA33_P +#set_property -dict {LOC AK13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[33]}] ;# J2.G37 LA33_N + +#set_property -dict {LOC BC9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_clk0_m2c_p}] ;# J2.H4 CLK0_M2C_P +#set_property -dict {LOC BC8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_clk0_m2c_n}] ;# J2.H5 CLK0_M2C_N +#set_property -dict {LOC AV14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_clk1_m2c_p}] ;# J2.G2 CLK1_M2C_P +#set_property -dict {LOC AV13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_clk1_m2c_n}] ;# J2.G3 CLK1_M2C_N + +#set_property -dict {LOC BA7 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc1_pg_m2c}] ;# J2.F1 PG_M2C +#set_property -dict {LOC BB7 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc1_prsnt_m2c_l}] ;# J2.H2 PRSNT_M2C_L + +# DDR4 C1 +# 5x MT40A256M16GE-075E +#set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +#set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +#set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +#set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +#set_property -dict {LOC C15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +#set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +#set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +#set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +#set_property -dict {LOC A16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +#set_property -dict {LOC B12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +#set_property -dict {LOC C12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +#set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +#set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +#set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +#set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +#set_property -dict {LOC H15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +#set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +#set_property -dict {LOC G15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +#set_property -dict {LOC G13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +#set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +#set_property -dict {LOC F14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}] +#set_property -dict {LOC E14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}] +#set_property -dict {LOC A10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}] +#set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}] +#set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +#set_property -dict {LOC C8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}] +#set_property -dict {LOC G10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +#set_property -dict {LOC N20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] +#set_property -dict {LOC R17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}] +#set_property -dict {LOC A20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}] + +#set_property -dict {LOC F11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] ;# U60.G2 DQL0 +#set_property -dict {LOC E11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] ;# U60.F7 DQL1 +#set_property -dict {LOC F10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] ;# U60.H3 DQL2 +#set_property -dict {LOC F9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] ;# U60.H7 DQL3 +#set_property -dict {LOC H12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] ;# U60.H2 DQL4 +#set_property -dict {LOC G12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] ;# U60.H8 DQL5 +#set_property -dict {LOC E9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] ;# U60.J3 DQL6 +#set_property -dict {LOC D9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] ;# U60.J7 DQL7 +#set_property -dict {LOC R19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] ;# U60.A3 DQU0 +#set_property -dict {LOC P19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] ;# U60.B8 DQU1 +#set_property -dict {LOC M18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] ;# U60.C3 DQU2 +#set_property -dict {LOC M17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] ;# U60.C7 DQU3 +#set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] ;# U60.C2 DQU4 +#set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] ;# U60.C8 DQU5 +#set_property -dict {LOC N17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] ;# U60.D3 DQU6 +#set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] ;# U60.D7 DQU7 +#set_property -dict {LOC D11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] ;# U60.G3 DQSL_T +#set_property -dict {LOC D10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] ;# U60.F3 DQSL_C +#set_property -dict {LOC P17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] ;# U60.B7 DQSU_T +#set_property -dict {LOC P16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] ;# U60.A7 DQSU_C +#set_property -dict {LOC G11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] ;# U60.E7 DML_B/DBIL_B +#set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] ;# U60.E2 DMU_B/DBIU_B + +#set_property -dict {LOC L16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] ;# U61.G2 DQL0 +#set_property -dict {LOC K16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] ;# U61.F7 DQL1 +#set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] ;# U61.H3 DQL2 +#set_property -dict {LOC K18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] ;# U61.H7 DQL3 +#set_property -dict {LOC J17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] ;# U61.H2 DQL4 +#set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] ;# U61.H8 DQL5 +#set_property -dict {LOC H19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] ;# U61.J3 DQL6 +#set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] ;# U61.J7 DQL7 +#set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] ;# U61.A3 DQU0 +#set_property -dict {LOC F18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] ;# U61.B8 DQU1 +#set_property -dict {LOC E19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] ;# U61.C3 DQU2 +#set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] ;# U61.C7 DQU3 +#set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] ;# U61.C2 DQU4 +#set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] ;# U61.C8 DQU5 +#set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] ;# U61.D3 DQU6 +#set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] ;# U61.D7 DQU7 +#set_property -dict {LOC K19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] ;# U61.G3 DQSL_T +#set_property -dict {LOC J19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] ;# U61.F3 DQSL_C +#set_property -dict {LOC F16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] ;# U61.B7 DQSU_T +#set_property -dict {LOC E16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] ;# U61.A7 DQSU_C +#set_property -dict {LOC K17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] ;# U61.E7 DML_B/DBIL_B +#set_property -dict {LOC G18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] ;# U61.E2 DMU_B/DBIU_B + +#set_property -dict {LOC D17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] ;# U62.G2 DQL0 +#set_property -dict {LOC C17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] ;# U62.F7 DQL1 +#set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] ;# U62.H3 DQL2 +#set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] ;# U62.H7 DQL3 +#set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] ;# U62.H2 DQL4 +#set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] ;# U62.H8 DQL5 +#set_property -dict {LOC C20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] ;# U62.J3 DQL6 +#set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] ;# U62.J7 DQL7 +#set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] ;# U62.A3 DQU0 +#set_property -dict {LOC M23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] ;# U62.B8 DQU1 +#set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] ;# U62.C3 DQU2 +#set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] ;# U62.C7 DQU3 +#set_property -dict {LOC R22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] ;# U62.C2 DQU4 +#set_property -dict {LOC P22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] ;# U62.C8 DQU5 +#set_property -dict {LOC T23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] ;# U62.D3 DQU6 +#set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] ;# U62.D7 DQU7 +#set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] ;# U62.G3 DQSL_T +#set_property -dict {LOC A18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] ;# U62.F3 DQSL_C +#set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] ;# U62.B7 DQSU_T +#set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] ;# U62.A7 DQSU_C +#set_property -dict {LOC B18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] ;# U62.E7 DML_B/DBIL_B +#set_property -dict {LOC P20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] ;# U62.E2 DMU_B/DBIU_B + +#set_property -dict {LOC K24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] ;# U63.G2 DQL0 +#set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] ;# U63.F7 DQL1 +#set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] ;# U63.H3 DQL2 +#set_property -dict {LOC L21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] ;# U63.H7 DQL3 +#set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] ;# U63.H2 DQL4 +#set_property -dict {LOC J21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] ;# U63.H8 DQL5 +#set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] ;# U63.J3 DQL6 +#set_property -dict {LOC J22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] ;# U63.J7 DQL7 +#set_property -dict {LOC H23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] ;# U63.A3 DQU0 +#set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] ;# U63.B8 DQU1 +#set_property -dict {LOC E23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] ;# U63.C3 DQU2 +#set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] ;# U63.C7 DQU3 +#set_property -dict {LOC F21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] ;# U63.C2 DQU4 +#set_property -dict {LOC E21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] ;# U63.C8 DQU5 +#set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] ;# U63.D3 DQU6 +#set_property -dict {LOC F23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] ;# U63.D7 DQU7 +#set_property -dict {LOC M20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] ;# U63.G3 DQSL_T +#set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] ;# U63.F3 DQSL_C +#set_property -dict {LOC H24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] ;# U63.B7 DQSU_T +#set_property -dict {LOC G23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] ;# U63.A7 DQSU_C +#set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] ;# U63.E7 DML_B/DBIL_B +#set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] ;# U63.E2 DMU_B/DBIU_B + +#set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] ;# U64.G2 DQL0 +#set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] ;# U64.F7 DQL1 +#set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] ;# U64.H3 DQL2 +#set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] ;# U64.H7 DQL3 +#set_property -dict {LOC B23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] ;# U64.H2 DQL4 +#set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] ;# U64.H8 DQL5 +#set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] ;# U64.J3 DQL6 +#set_property -dict {LOC A21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] ;# U64.J7 DQL7 +#set_property -dict {LOC D7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[72]}] ;# U64.A3 DQU0 +#set_property -dict {LOC C7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[73]}] ;# U64.B8 DQU1 +#set_property -dict {LOC B8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[74]}] ;# U64.C3 DQU2 +#set_property -dict {LOC B7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[75]}] ;# U64.C7 DQU3 +#set_property -dict {LOC C10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[76]}] ;# U64.C2 DQU4 +#set_property -dict {LOC B10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[77]}] ;# U64.C8 DQU5 +#set_property -dict {LOC B11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[78]}] ;# U64.D3 DQU6 +#set_property -dict {LOC A11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[79]}] ;# U64.D7 DQU7 +#set_property -dict {LOC D22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] ;# U64.G3 DQSL_T +#set_property -dict {LOC C22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] ;# U64.F3 DQSL_C +#set_property -dict {LOC A9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] ;# U64.B7 DQSU_T +#set_property -dict {LOC A8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] ;# U64.A7 DQSU_C +#set_property -dict {LOC E24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}] ;# U64.E7 DML_B/DBIL_B +#set_property -dict {LOC C9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[9]}] ;# U64.E2 DMU_B/DBIU_B + +# DDR4 C2 +# 5x MT40A256M16GE-075E +#set_property -dict {LOC AM27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +#set_property -dict {LOC AL27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +#set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +#set_property -dict {LOC AN28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +#set_property -dict {LOC AM28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +#set_property -dict {LOC AP28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +#set_property -dict {LOC AP27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +#set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +#set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +#set_property -dict {LOC AR28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +#set_property -dict {LOC AR27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +#set_property -dict {LOC AV25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +#set_property -dict {LOC AT25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +#set_property -dict {LOC AV28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +#set_property -dict {LOC AU26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +#set_property -dict {LOC AV26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +#set_property -dict {LOC AR25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +#set_property -dict {LOC AU28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +#set_property -dict {LOC AU27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +#set_property -dict {LOC AT26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t}] +#set_property -dict {LOC AT27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c}] +#set_property -dict {LOC AW28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke}] +#set_property -dict {LOC AY29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n}] +#set_property -dict {LOC AN25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +#set_property -dict {LOC BB29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt}] +#set_property -dict {LOC BF29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +#set_property -dict {LOC BD35 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] +#set_property -dict {LOC AR29 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_alert_n}] +#set_property -dict {LOC AY35 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_ten}] + +#set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] ;# U135.G2 DQL0 +#set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] ;# U135.F7 DQL1 +#set_property -dict {LOC BD32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] ;# U135.H3 DQL2 +#set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] ;# U135.H7 DQL3 +#set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] ;# U135.H2 DQL4 +#set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] ;# U135.H8 DQL5 +#set_property -dict {LOC BC31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] ;# U135.J3 DQL6 +#set_property -dict {LOC BD31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] ;# U135.J7 DQL7 +#set_property -dict {LOC BA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] ;# U135.A3 DQU0 +#set_property -dict {LOC BB33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] ;# U135.B8 DQU1 +#set_property -dict {LOC BA30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] ;# U135.C3 DQU2 +#set_property -dict {LOC BA31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] ;# U135.C7 DQU3 +#set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] ;# U135.C2 DQU4 +#set_property -dict {LOC AW32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] ;# U135.C8 DQU5 +#set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] ;# U135.D3 DQU6 +#set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] ;# U135.D7 DQU7 +#set_property -dict {LOC BF30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] ;# U135.G3 DQSL_T +#set_property -dict {LOC BF31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] ;# U135.F3 DQSL_C +#set_property -dict {LOC AY34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] ;# U135.B7 DQSU_T +#set_property -dict {LOC BA34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] ;# U135.A7 DQSU_C +#set_property -dict {LOC BE32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[0]}] ;# U135.E7 DML_B/DBIL_B +#set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[1]}] ;# U135.E2 DMU_B/DBIU_B + +#set_property -dict {LOC AV30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] ;# U136.G2 DQL0 +#set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] ;# U136.F7 DQL1 +#set_property -dict {LOC AU33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] ;# U136.H3 DQL2 +#set_property -dict {LOC AU34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] ;# U136.H7 DQL3 +#set_property -dict {LOC AT31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] ;# U136.H2 DQL4 +#set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] ;# U136.H8 DQL5 +#set_property -dict {LOC AU31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] ;# U136.J3 DQL6 +#set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] ;# U136.J7 DQL7 +#set_property -dict {LOC AR33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] ;# U136.A3 DQU0 +#set_property -dict {LOC AT34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] ;# U136.B8 DQU1 +#set_property -dict {LOC AT29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] ;# U136.C3 DQU2 +#set_property -dict {LOC AT30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] ;# U136.C7 DQU3 +#set_property -dict {LOC AP30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] ;# U136.C2 DQU4 +#set_property -dict {LOC AR30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] ;# U136.C8 DQU5 +#set_property -dict {LOC AN30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] ;# U136.D3 DQU6 +#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] ;# U136.D7 DQU7 +#set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] ;# U136.G3 DQSL_T +#set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] ;# U136.F3 DQSL_C +#set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] ;# U136.B7 DQSU_T +#set_property -dict {LOC AP32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] ;# U136.A7 DQSU_C +#set_property -dict {LOC AV33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[2]}] ;# U136.E7 DML_B/DBIL_B +#set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[3]}] ;# U136.E2 DMU_B/DBIU_B + +#set_property -dict {LOC BE34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] ;# U137.G2 DQL0 +#set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] ;# U137.F7 DQL1 +#set_property -dict {LOC BC35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] ;# U137.H3 DQL2 +#set_property -dict {LOC BC36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] ;# U137.H7 DQL3 +#set_property -dict {LOC BD36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] ;# U137.H2 DQL4 +#set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] ;# U137.H8 DQL5 +#set_property -dict {LOC BF36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] ;# U137.J3 DQL6 +#set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] ;# U137.J7 DQL7 +#set_property -dict {LOC BD37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] ;# U137.A3 DQU0 +#set_property -dict {LOC BE38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] ;# U137.B8 DQU1 +#set_property -dict {LOC BC39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] ;# U137.C3 DQU2 +#set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] ;# U137.C7 DQU3 +#set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] ;# U137.C2 DQU4 +#set_property -dict {LOC BB39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] ;# U137.C8 DQU5 +#set_property -dict {LOC BC38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] ;# U137.D3 DQU6 +#set_property -dict {LOC BD38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] ;# U137.D7 DQU7 +#set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] ;# U137.G3 DQSL_T +#set_property -dict {LOC BF35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] ;# U137.F3 DQSL_C +#set_property -dict {LOC BE39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] ;# U137.B7 DQSU_T +#set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] ;# U137.A7 DQSU_C +#set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[4]}] ;# U137.E7 DML_B/DBIL_B +#set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[5]}] ;# U137.E2 DMU_B/DBIU_B + +#set_property -dict {LOC BB36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] ;# U138.G2 DQL0 +#set_property -dict {LOC BB37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] ;# U138.F7 DQL1 +#set_property -dict {LOC BA39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] ;# U138.H3 DQL2 +#set_property -dict {LOC BA40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] ;# U138.H7 DQL3 +#set_property -dict {LOC AW40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] ;# U138.H2 DQL4 +#set_property -dict {LOC AY40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] ;# U138.H8 DQL5 +#set_property -dict {LOC AY38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] ;# U138.J3 DQL6 +#set_property -dict {LOC AY39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] ;# U138.J7 DQL7 +#set_property -dict {LOC AW35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] ;# U138.A3 DQU0 +#set_property -dict {LOC AW36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] ;# U138.B8 DQU1 +#set_property -dict {LOC AU40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] ;# U138.C3 DQU2 +#set_property -dict {LOC AV40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] ;# U138.C7 DQU3 +#set_property -dict {LOC AU38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] ;# U138.C2 DQU4 +#set_property -dict {LOC AU39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] ;# U138.C8 DQU5 +#set_property -dict {LOC AV38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] ;# U138.D3 DQU6 +#set_property -dict {LOC AV39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] ;# U138.D7 DQU7 +#set_property -dict {LOC BA35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] ;# U138.G3 DQSL_T +#set_property -dict {LOC BA36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] ;# U138.F3 DQSL_C +#set_property -dict {LOC AW37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] ;# U138.B7 DQSU_T +#set_property -dict {LOC AW38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] ;# U138.A7 DQSU_C +#set_property -dict {LOC AY37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[6]}] ;# U138.E7 DML_B/DBIL_B +#set_property -dict {LOC AV35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[7]}] ;# U138.E2 DMU_B/DBIU_B + +#set_property -dict {LOC BF26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] ;# U139.G2 DQL0 +#set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] ;# U139.F7 DQL1 +#set_property -dict {LOC BD28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] ;# U139.H3 DQL2 +#set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] ;# U139.H7 DQL3 +#set_property -dict {LOC BD27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] ;# U139.H2 DQL4 +#set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] ;# U139.H8 DQL5 +#set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] ;# U139.J3 DQL6 +#set_property -dict {LOC BD26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] ;# U139.J7 DQL7 +#set_property -dict {LOC BC25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[72]}] ;# U139.A3 DQU0 +#set_property -dict {LOC BC26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[73]}] ;# U139.B8 DQU1 +#set_property -dict {LOC BB28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[74]}] ;# U139.C3 DQU2 +#set_property -dict {LOC BC28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[75]}] ;# U139.C7 DQU3 +#set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[76]}] ;# U139.C2 DQU4 +#set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[77]}] ;# U139.C8 DQU5 +#set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[78]}] ;# U139.D3 DQU6 +#set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[79]}] ;# U139.D7 DQU7 +#set_property -dict {LOC BE25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] ;# U139.G3 DQSL_T +#set_property -dict {LOC BF25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] ;# U139.F3 DQSL_C +#set_property -dict {LOC BA26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] ;# U139.B7 DQSU_T +#set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] ;# U139.A7 DQSU_C +#set_property -dict {LOC BE29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[8]}] ;# U139.E7 DML_B/DBIL_B +#set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[9]}] ;# U139.E2 DMU_B/DBIU_B + +# QSPI flash +#set_property -dict {LOC AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}] +#set_property -dict {LOC AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}] +#set_property -dict {LOC AN20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[2]}] +#set_property -dict {LOC AP20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[3]}] +#set_property -dict {LOC BF16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_cs}] + +#set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}] +#set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}] +#set_false_path -from [get_ports {qspi_1_dq}] +#set_input_delay 0 [get_ports {qspi_1_dq}] diff --git a/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga/Makefile b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga/Makefile new file mode 100644 index 000000000..42996a88f --- /dev/null +++ b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga/Makefile @@ -0,0 +1,124 @@ + +# FPGA settings +FPGA_PART = xcvu9p-flga2104-2L-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/debounce_switch.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/mdio_master.v +SYN_FILES += rtl/i2c_master.v +SYN_FILES += pll/si5341_i2c_init.v +SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_1g.v +SYN_FILES += lib/eth/rtl/axis_gmii_rx.v +SYN_FILES += lib/eth/rtl/axis_gmii_tx.v +SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete_64.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v +SYN_FILES += lib/eth/rtl/udp_64.v +SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v +SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v +SYN_FILES += lib/eth/rtl/ip_complete_64.v +SYN_FILES += lib/eth/rtl/ip_64.v +SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v +SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_switch.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl + +# IP +IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl +IP_TCL_FILES += ip/eth_xcvr_gt.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 256 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + diff --git a/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga/config.tcl b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga/config.tcl new file mode 100644 index 000000000..1fda15c32 --- /dev/null +++ b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {156.25} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile new file mode 100644 index 000000000..42996a88f --- /dev/null +++ b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile @@ -0,0 +1,124 @@ + +# FPGA settings +FPGA_PART = xcvu9p-flga2104-2L-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/debounce_switch.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/mdio_master.v +SYN_FILES += rtl/i2c_master.v +SYN_FILES += pll/si5341_i2c_init.v +SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_1g.v +SYN_FILES += lib/eth/rtl/axis_gmii_rx.v +SYN_FILES += lib/eth/rtl/axis_gmii_tx.v +SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete_64.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v +SYN_FILES += lib/eth/rtl/udp_64.v +SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v +SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v +SYN_FILES += lib/eth/rtl/ip_complete_64.v +SYN_FILES += lib/eth/rtl/ip_64.v +SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v +SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_switch.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl + +# IP +IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl +IP_TCL_FILES += ip/eth_xcvr_gt.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 256 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + diff --git a/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga_10g/config.tcl b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga_10g/config.tcl new file mode 100644 index 000000000..9b95d246e --- /dev/null +++ b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga_10g/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {156.25} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/ip/eth_xcvr_gt.tcl similarity index 99% rename from fpga/lib/eth/example/VCU118/fpga_10g/ip/eth_xcvr_gt.tcl rename to fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/ip/eth_xcvr_gt.tcl index 7464143a6..b01843774 100644 --- a/fpga/lib/eth/example/VCU118/fpga_10g/ip/eth_xcvr_gt.tcl +++ b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/ip/eth_xcvr_gt.tcl @@ -23,7 +23,7 @@ set base_name {eth_xcvr_gt} set preset {GTY-10GBASE-R} set freerun_freq {125} -set line_rate {10.3125} +set line_rate {25.78125} set refclk_freq {156.25} set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] set user_data_width {64} diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/ip/gig_ethernet_pcs_pma_0.tcl b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/ip/gig_ethernet_pcs_pma_0.tcl similarity index 100% rename from fpga/lib/eth/example/VCU118/fpga_10g/ip/gig_ethernet_pcs_pma_0.tcl rename to fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/ip/gig_ethernet_pcs_pma_0.tcl diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/lib/eth b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/lib/eth similarity index 100% rename from fpga/lib/eth/example/VCU118/fpga_10g/lib/eth rename to fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/lib/eth diff --git a/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/pll/VCU118_HTG_FMC_6QSFP_156-HTG6Q156-Registers.txt b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/pll/VCU118_HTG_FMC_6QSFP_156-HTG6Q156-Registers.txt new file mode 100644 index 000000000..ee2795dab --- /dev/null +++ b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/pll/VCU118_HTG_FMC_6QSFP_156-HTG6Q156-Registers.txt @@ -0,0 +1,412 @@ +# Si534x/7x/8x/9x Registers Script +# +# Part: Si5341 +# Project File: X:\Projects\verilog-ethernet\example\VCU118\fpga_fmc_htg_6qsfp_25g\pll\VCU118_HTG_FMC_6QSFP_156-HTG6Q156.slabtimeproj +# Design ID: HTG6Q156 +# Includes Pre/Post Download Control Register Writes: Yes +# Die Revision: B1 +# Creator: ClockBuilder Pro v4.1 [2021-09-22] +# Created On: 2023-07-19 01:56:40 GMT-07:00 +Address,Data +# +# Start configuration preamble +0x0B24,0xC0 +0x0B25,0x00 +# Rev D stuck divider fix +0x0502,0x01 +0x0505,0x03 +0x0957,0x17 +0x0B4E,0x1A +# End configuration preamble +# +# Delay 300 msec +# Delay is worst case time for device to complete any calibration +# that is running due to device state change previous to this script +# being processed. +# +# Start configuration registers +0x0006,0x00 +0x0007,0x00 +0x0008,0x00 +0x000B,0x74 +0x0017,0xD0 +0x0018,0xFF +0x0021,0x0D +0x0022,0x00 +0x002B,0x02 +0x002C,0x34 +0x002D,0x10 +0x002E,0x00 +0x002F,0x00 +0x0030,0x00 +0x0031,0x00 +0x0032,0xB1 +0x0033,0x00 +0x0034,0x00 +0x0035,0x00 +0x0036,0x00 +0x0037,0x00 +0x0038,0x00 +0x0039,0x00 +0x003A,0xB1 +0x003B,0x00 +0x003C,0x00 +0x003D,0x00 +0x0041,0x00 +0x0042,0x00 +0x0043,0x07 +0x0044,0x00 +0x009E,0x00 +0x0102,0x01 +0x0108,0x06 +0x0109,0x09 +0x010A,0x33 +0x010B,0x08 +0x010D,0x06 +0x010E,0x09 +0x010F,0x33 +0x0110,0x08 +0x0112,0x06 +0x0113,0x09 +0x0114,0x33 +0x0115,0x08 +0x0117,0x06 +0x0118,0x09 +0x0119,0x33 +0x011A,0x08 +0x011C,0x06 +0x011D,0x09 +0x011E,0x33 +0x011F,0x08 +0x0121,0x06 +0x0122,0x09 +0x0123,0x33 +0x0124,0x08 +0x0126,0x06 +0x0127,0x09 +0x0128,0x33 +0x0129,0x08 +0x012B,0x06 +0x012C,0x09 +0x012D,0x33 +0x012E,0x08 +0x0130,0x06 +0x0131,0x09 +0x0132,0x33 +0x0133,0x08 +0x013A,0x01 +0x013B,0x09 +0x013C,0x3B +0x013D,0x28 +0x013F,0x00 +0x0140,0x00 +0x0141,0x40 +0x0206,0x00 +0x0208,0x00 +0x0209,0x00 +0x020A,0x00 +0x020B,0x00 +0x020C,0x00 +0x020D,0x00 +0x020E,0x00 +0x020F,0x00 +0x0210,0x00 +0x0211,0x00 +0x0212,0x00 +0x0213,0x00 +0x0214,0x00 +0x0215,0x00 +0x0216,0x00 +0x0217,0x00 +0x0218,0x00 +0x0219,0x00 +0x021A,0x00 +0x021B,0x00 +0x021C,0x02 +0x021D,0x00 +0x021E,0x00 +0x021F,0x00 +0x0220,0x00 +0x0221,0x00 +0x0222,0x01 +0x0223,0x00 +0x0224,0x00 +0x0225,0x00 +0x0226,0x00 +0x0227,0x00 +0x0228,0x00 +0x0229,0x00 +0x022A,0x00 +0x022B,0x00 +0x022C,0x00 +0x022D,0x00 +0x022E,0x00 +0x022F,0x00 +0x0235,0x00 +0x0236,0x00 +0x0237,0x00 +0x0238,0x00 +0x0239,0x56 +0x023A,0x00 +0x023B,0x00 +0x023C,0x00 +0x023D,0x00 +0x023E,0x80 +0x024A,0x00 +0x024B,0x00 +0x024C,0x00 +0x024D,0x00 +0x024E,0x00 +0x024F,0x00 +0x0250,0x00 +0x0251,0x00 +0x0252,0x00 +0x0253,0x00 +0x0254,0x00 +0x0255,0x00 +0x0256,0x00 +0x0257,0x00 +0x0258,0x00 +0x0259,0x00 +0x025A,0x00 +0x025B,0x00 +0x025C,0x00 +0x025D,0x00 +0x025E,0x00 +0x025F,0x00 +0x0260,0x00 +0x0261,0x00 +0x0262,0x00 +0x0263,0x00 +0x0264,0x00 +0x0268,0x00 +0x0269,0x00 +0x026A,0x00 +0x026B,0x48 +0x026C,0x54 +0x026D,0x47 +0x026E,0x36 +0x026F,0x51 +0x0270,0x31 +0x0271,0x35 +0x0272,0x36 +0x0302,0x00 +0x0303,0x00 +0x0304,0x00 +0x0305,0x80 +0x0306,0x15 +0x0307,0x00 +0x0308,0x00 +0x0309,0x00 +0x030A,0x00 +0x030B,0x80 +0x030C,0x00 +0x030D,0x00 +0x030E,0x00 +0x030F,0x00 +0x0310,0x00 +0x0311,0x00 +0x0312,0x00 +0x0313,0x00 +0x0314,0x00 +0x0315,0x00 +0x0316,0x00 +0x0317,0x00 +0x0318,0x00 +0x0319,0x00 +0x031A,0x00 +0x031B,0x00 +0x031C,0x00 +0x031D,0x00 +0x031E,0x00 +0x031F,0x00 +0x0320,0x00 +0x0321,0x00 +0x0322,0x00 +0x0323,0x00 +0x0324,0x00 +0x0325,0x00 +0x0326,0x00 +0x0327,0x00 +0x0328,0x00 +0x0329,0x00 +0x032A,0x00 +0x032B,0x00 +0x032C,0x00 +0x032D,0x00 +0x032E,0x00 +0x032F,0x00 +0x0330,0x00 +0x0331,0x00 +0x0332,0x00 +0x0333,0x00 +0x0334,0x00 +0x0335,0x00 +0x0336,0x00 +0x0337,0x00 +0x0338,0x00 +0x0339,0x1F +0x033B,0x00 +0x033C,0x00 +0x033D,0x00 +0x033E,0x00 +0x033F,0x00 +0x0340,0x00 +0x0341,0x00 +0x0342,0x00 +0x0343,0x00 +0x0344,0x00 +0x0345,0x00 +0x0346,0x00 +0x0347,0x00 +0x0348,0x00 +0x0349,0x00 +0x034A,0x00 +0x034B,0x00 +0x034C,0x00 +0x034D,0x00 +0x034E,0x00 +0x034F,0x00 +0x0350,0x00 +0x0351,0x00 +0x0352,0x00 +0x0353,0x00 +0x0354,0x00 +0x0355,0x00 +0x0356,0x00 +0x0357,0x00 +0x0358,0x00 +0x0359,0x00 +0x035A,0x00 +0x035B,0x00 +0x035C,0x00 +0x035D,0x00 +0x035E,0x00 +0x035F,0x00 +0x0360,0x00 +0x0361,0x00 +0x0362,0x00 +0x0802,0x00 +0x0803,0x00 +0x0804,0x00 +0x0805,0x00 +0x0806,0x00 +0x0807,0x00 +0x0808,0x00 +0x0809,0x00 +0x080A,0x00 +0x080B,0x00 +0x080C,0x00 +0x080D,0x00 +0x080E,0x00 +0x080F,0x00 +0x0810,0x00 +0x0811,0x00 +0x0812,0x00 +0x0813,0x00 +0x0814,0x00 +0x0815,0x00 +0x0816,0x00 +0x0817,0x00 +0x0818,0x00 +0x0819,0x00 +0x081A,0x00 +0x081B,0x00 +0x081C,0x00 +0x081D,0x00 +0x081E,0x00 +0x081F,0x00 +0x0820,0x00 +0x0821,0x00 +0x0822,0x00 +0x0823,0x00 +0x0824,0x00 +0x0825,0x00 +0x0826,0x00 +0x0827,0x00 +0x0828,0x00 +0x0829,0x00 +0x082A,0x00 +0x082B,0x00 +0x082C,0x00 +0x082D,0x00 +0x082E,0x00 +0x082F,0x00 +0x0830,0x00 +0x0831,0x00 +0x0832,0x00 +0x0833,0x00 +0x0834,0x00 +0x0835,0x00 +0x0836,0x00 +0x0837,0x00 +0x0838,0x00 +0x0839,0x00 +0x083A,0x00 +0x083B,0x00 +0x083C,0x00 +0x083D,0x00 +0x083E,0x00 +0x083F,0x00 +0x0840,0x00 +0x0841,0x00 +0x0842,0x00 +0x0843,0x00 +0x0844,0x00 +0x0845,0x00 +0x0846,0x00 +0x0847,0x00 +0x0848,0x00 +0x0849,0x00 +0x084A,0x00 +0x084B,0x00 +0x084C,0x00 +0x084D,0x00 +0x084E,0x00 +0x084F,0x00 +0x0850,0x00 +0x0851,0x00 +0x0852,0x00 +0x0853,0x00 +0x0854,0x00 +0x0855,0x00 +0x0856,0x00 +0x0857,0x00 +0x0858,0x00 +0x0859,0x00 +0x085A,0x00 +0x085B,0x00 +0x085C,0x00 +0x085D,0x00 +0x085E,0x00 +0x085F,0x00 +0x0860,0x00 +0x0861,0x00 +0x090E,0x00 +0x091C,0x04 +0x0943,0x00 +0x0949,0x04 +0x094A,0x40 +0x094E,0x49 +0x094F,0x02 +0x095E,0x00 +0x0A02,0x00 +0x0A03,0x01 +0x0A04,0x01 +0x0A05,0x01 +0x0A14,0x00 +0x0A1A,0x00 +0x0A20,0x00 +0x0A26,0x00 +0x0A2C,0x00 +0x0B44,0x0F +0x0B4A,0x1E +0x0B57,0xA5 +0x0B58,0x00 +# End configuration registers +# +# Start configuration postamble +0x001C,0x01 +0x0B24,0xC3 +0x0B25,0x02 +# End configuration postamble diff --git a/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/pll/VCU118_HTG_FMC_6QSFP_156-HTG6Q156.slabtimeproj b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/pll/VCU118_HTG_FMC_6QSFP_156-HTG6Q156.slabtimeproj new file mode 100644 index 000000000..02415fb71 Binary files /dev/null and b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/pll/VCU118_HTG_FMC_6QSFP_156-HTG6Q156.slabtimeproj differ diff --git a/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.py b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.py new file mode 100755 index 000000000..2e5a9b228 --- /dev/null +++ b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.py @@ -0,0 +1,599 @@ +#!/usr/bin/env python +""" +Generates an I2C init module for multiple chips +""" + +from jinja2 import Template + + +def si5341_cmds(regs, dev_addr=0x77): + cur_page = None + cur_addr = None + + cmds = [] + + print(f"Reading register list file '{regs}'...") + + with open(regs, "r") as f: + for line in f: + line = line.strip() + if not line or line == "Address,Data": + continue + if line[0] == '#': + cmds.append(f"// {line[1:].strip()}") + + if line.startswith("# Delay"): + cmds.append("9'b000011010; // delay 300 ms") + cur_addr = None + + continue + + d = line.split(",") + addr = int(d[0], 0) + page = (addr >> 8) & 0xff + data = int(d[1], 0) + + if page != cur_page: + cmds.append(f"{{2'b01, 7'h{dev_addr:02x}}};") + cmds.append("{1'b1, 8'h01};") + cmds.append(f"{{1'b1, 8'h{page:02x}}}; // set page {page:#04x}") + cur_page = page + cur_addr = None + + if addr != cur_addr: + cmds.append(f"{{2'b01, 7'h{dev_addr:02x}}};") + cmds.append(f"{{1'b1, 8'h{addr & 0xff:02x}}};") + cur_addr = addr + + cmds.append(f"{{1'b1, 8'h{data:02x}}}; // write {data:#04x} to {addr:#06x}") + cur_addr += 1 + + return cmds + + +def mux_cmds(val, dev_addr): + cmds = [] + cmds.append(f"{{2'b01, 7'h{dev_addr:02x}}};") + cmds.append(f"{{1'b1, 8'h{val:02x}}};") + cmds.append("9'b001000001; // I2C stop") + return cmds + + +def main(): + cmds = [] + + cmds.append("// Initial delay") + cmds.append("9'b000010110; // delay 30 ms") + + # Si5341 on FMC+ + cmds.append("// Set muxes to select U7 Si5341 on HTG-FMC-x6-QSFP28") + cmds.extend(mux_cmds(0x00, 0x74)) + cmds.extend(mux_cmds(0x02, 0x75)) + + cmds.extend(si5341_cmds("VCU118_HTG_FMC_6QSFP_156-HTG6Q156-Registers.txt", 0x77)) + + generate(cmds) + + +def generate(cmds=None, name=None, output=None): + if cmds is None: + raise Exception("Command list is required") + + if name is None: + name = "si5341_i2c_init" + + if output is None: + output = name + ".v" + + print(f"Generating Si5341 I2C init module {name}...") + + cmds.append("9'd0; // end") + + cmd_str = "" + cmd_count = 0 + + for cmd in cmds: + if cmd.startswith('//'): + cmd_str += f" {cmd}\n" + else: + cmd_str += f" init_data[{cmd_count}] = {cmd}\n" + cmd_count += 1 + + t = Template(u"""/* + +Copyright (c) 2015-2021 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * {{name}} + */ +module {{name}} ( + input wire clk, + input wire rst, + + /* + * I2C master interface + */ + output wire [6:0] m_axis_cmd_address, + output wire m_axis_cmd_start, + output wire m_axis_cmd_read, + output wire m_axis_cmd_write, + output wire m_axis_cmd_write_multiple, + output wire m_axis_cmd_stop, + output wire m_axis_cmd_valid, + input wire m_axis_cmd_ready, + + output wire [7:0] m_axis_data_tdata, + output wire m_axis_data_tvalid, + input wire m_axis_data_tready, + output wire m_axis_data_tlast, + + /* + * Status + */ + output wire busy, + + /* + * Configuration + */ + input wire start +); + +/* + +Generic module for I2C bus initialization. Good for use when multiple devices +on an I2C bus must be initialized on system start without intervention of a +general-purpose processor. + +Copy this file and change init_data and INIT_DATA_LEN as needed. + +This module can be used in two modes: simple device initialization, or multiple +device initialization. In multiple device mode, the same initialization sequence +can be performed on multiple different device addresses. + +To use single device mode, only use the start write to address and write data commands. +The module will generate the I2C commands in sequential order. Terminate the list +with a 0 entry. + +To use the multiple device mode, use the start data and start address block commands +to set up lists of initialization data and device addresses. The module enters +multiple device mode upon seeing a start data block command. The module stores the +offset of the start of the data block and then skips ahead until it reaches a start +address block command. The module will store the offset to the address block and +read the first address in the block. Then it will jump back to the data block +and execute it, substituting the stored address for each current address write +command. Upon reaching the start address block command, the module will read out the +next address and start again at the top of the data block. If the module encounters +a start data block command while looking for an address, then it will store a new data +offset and then look for a start address block command. Terminate the list with a 0 +entry. Normal address commands will operate normally inside a data block. + +Commands: + +00 0000000 : stop +00 0000001 : exit multiple device mode +00 0000011 : start write to current address +00 0001000 : start address block +00 0001001 : start data block +00 001dddd : delay 2**(16+d) cycles +00 1000001 : send I2C stop +01 aaaaaaa : start write to address +1 dddddddd : write 8-bit data + +Examples + +write 0x11223344 to register 0x0004 on device at 0x50 + +01 1010000 start write to 0x50 +1 00000000 write address 0x0004 +1 00000100 +1 00010001 write data 0x11223344 +1 00100010 +1 00110011 +1 01000100 +0 00000000 stop + +write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53 + +00 0001001 start data block +00 0000011 start write to current address +1 00000000 write address 0x0004 +1 00000100 +1 00010001 write data 0x11223344 +1 00100010 +1 00110011 +1 01000100 +00 0001000 start address block +01 1010000 address 0x50 +01 1010001 address 0x51 +01 1010010 address 0x52 +01 1010011 address 0x53 +00 0000000 stop + +*/ + +// init_data ROM +localparam INIT_DATA_LEN = {{cmd_count}}; + +reg [8:0] init_data [INIT_DATA_LEN-1:0]; + +initial begin +{{cmd_str-}} +end + +localparam [3:0] + STATE_IDLE = 3'd0, + STATE_RUN = 3'd1, + STATE_TABLE_1 = 3'd2, + STATE_TABLE_2 = 3'd3, + STATE_TABLE_3 = 3'd4; + +reg [4:0] state_reg = STATE_IDLE, state_next; + +parameter AW = $clog2(INIT_DATA_LEN); + +reg [8:0] init_data_reg = 9'd0; + +reg [AW-1:0] address_reg = {AW{1'b0}}, address_next; +reg [AW-1:0] address_ptr_reg = {AW{1'b0}}, address_ptr_next; +reg [AW-1:0] data_ptr_reg = {AW{1'b0}}, data_ptr_next; + +reg [6:0] cur_address_reg = 7'd0, cur_address_next; + +reg [31:0] delay_counter_reg = 32'd0, delay_counter_next; + +reg [6:0] m_axis_cmd_address_reg = 7'd0, m_axis_cmd_address_next; +reg m_axis_cmd_start_reg = 1'b0, m_axis_cmd_start_next; +reg m_axis_cmd_write_reg = 1'b0, m_axis_cmd_write_next; +reg m_axis_cmd_stop_reg = 1'b0, m_axis_cmd_stop_next; +reg m_axis_cmd_valid_reg = 1'b0, m_axis_cmd_valid_next; + +reg [7:0] m_axis_data_tdata_reg = 8'd0, m_axis_data_tdata_next; +reg m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next; + +reg start_flag_reg = 1'b0, start_flag_next; + +reg busy_reg = 1'b0; + +assign m_axis_cmd_address = m_axis_cmd_address_reg; +assign m_axis_cmd_start = m_axis_cmd_start_reg; +assign m_axis_cmd_read = 1'b0; +assign m_axis_cmd_write = m_axis_cmd_write_reg; +assign m_axis_cmd_write_multiple = 1'b0; +assign m_axis_cmd_stop = m_axis_cmd_stop_reg; +assign m_axis_cmd_valid = m_axis_cmd_valid_reg; + +assign m_axis_data_tdata = m_axis_data_tdata_reg; +assign m_axis_data_tvalid = m_axis_data_tvalid_reg; +assign m_axis_data_tlast = 1'b1; + +assign busy = busy_reg; + +always @* begin + state_next = STATE_IDLE; + + address_next = address_reg; + address_ptr_next = address_ptr_reg; + data_ptr_next = data_ptr_reg; + + cur_address_next = cur_address_reg; + + delay_counter_next = delay_counter_reg; + + m_axis_cmd_address_next = m_axis_cmd_address_reg; + m_axis_cmd_start_next = m_axis_cmd_start_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready); + m_axis_cmd_write_next = m_axis_cmd_write_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready); + m_axis_cmd_stop_next = m_axis_cmd_stop_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready); + m_axis_cmd_valid_next = m_axis_cmd_valid_reg & ~m_axis_cmd_ready; + + m_axis_data_tdata_next = m_axis_data_tdata_reg; + m_axis_data_tvalid_next = m_axis_data_tvalid_reg & ~m_axis_data_tready; + + start_flag_next = start_flag_reg; + + if (m_axis_cmd_valid | m_axis_data_tvalid) begin + // wait for output registers to clear + state_next = state_reg; + end else if (delay_counter_reg != 0) begin + // delay + delay_counter_next = delay_counter_reg - 1; + state_next = state_reg; + end else begin + case (state_reg) + STATE_IDLE: begin + // wait for start signal + if (~start_flag_reg & start) begin + address_next = {AW{1'b0}}; + start_flag_next = 1'b1; + state_next = STATE_RUN; + end else begin + state_next = STATE_IDLE; + end + end + STATE_RUN: begin + // process commands + if (init_data_reg[8] == 1'b1) begin + // write data + m_axis_cmd_write_next = 1'b1; + m_axis_cmd_stop_next = 1'b0; + m_axis_cmd_valid_next = 1'b1; + + m_axis_data_tdata_next = init_data_reg[7:0]; + m_axis_data_tvalid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg[8:7] == 2'b01) begin + // write address + m_axis_cmd_address_next = init_data_reg[6:0]; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg[8:4] == 5'b00001) begin + // delay + delay_counter_next = 32'd1 << (init_data_reg[3:0]+16); + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg == 9'b001000001) begin + // send stop + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_RUN; + end + end + STATE_TABLE_1: begin + // find address table start + if (init_data_reg == 9'b000001000) begin + // address table start + address_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_2; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end + end + STATE_TABLE_2: begin + // find next address + if (init_data_reg[8:7] == 2'b01) begin + // write address command + // store address and move to data table + cur_address_next = init_data_reg[6:0]; + address_ptr_next = address_reg + 1; + address_next = data_ptr_reg; + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'd1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_2; + end + end + STATE_TABLE_3: begin + // process data table with selected address + if (init_data_reg[8] == 1'b1) begin + // write data + m_axis_cmd_write_next = 1'b1; + m_axis_cmd_stop_next = 1'b0; + m_axis_cmd_valid_next = 1'b1; + + m_axis_data_tdata_next = init_data_reg[7:0]; + m_axis_data_tvalid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg[8:7] == 2'b01) begin + // write address + m_axis_cmd_address_next = init_data_reg[6:0]; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000000011) begin + // write current address + m_axis_cmd_address_next = cur_address_reg; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b001000001) begin + // send stop + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'b000001000) begin + // address table start + address_next = address_ptr_reg; + state_next = STATE_TABLE_2; + end else if (init_data_reg == 9'd1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_3; + end + end + endcase + end +end + +always @(posedge clk) begin + state_reg <= state_next; + + // read init_data ROM + init_data_reg <= init_data[address_next]; + + address_reg <= address_next; + address_ptr_reg <= address_ptr_next; + data_ptr_reg <= data_ptr_next; + + cur_address_reg <= cur_address_next; + + delay_counter_reg <= delay_counter_next; + + m_axis_cmd_address_reg <= m_axis_cmd_address_next; + m_axis_cmd_start_reg <= m_axis_cmd_start_next; + m_axis_cmd_write_reg <= m_axis_cmd_write_next; + m_axis_cmd_stop_reg <= m_axis_cmd_stop_next; + m_axis_cmd_valid_reg <= m_axis_cmd_valid_next; + + m_axis_data_tdata_reg <= m_axis_data_tdata_next; + m_axis_data_tvalid_reg <= m_axis_data_tvalid_next; + + start_flag_reg <= start & start_flag_next; + + busy_reg <= (state_reg != STATE_IDLE); + + if (rst) begin + state_reg <= STATE_IDLE; + + init_data_reg <= 9'd0; + + address_reg <= {AW{1'b0}}; + address_ptr_reg <= {AW{1'b0}}; + data_ptr_reg <= {AW{1'b0}}; + + cur_address_reg <= 7'd0; + + delay_counter_reg <= 32'd0; + + m_axis_cmd_valid_reg <= 1'b0; + + m_axis_data_tvalid_reg <= 1'b0; + + start_flag_reg <= 1'b0; + + busy_reg <= 1'b0; + end +end + +endmodule + +`resetall + +""") + + print(f"Writing file '{output}'...") + + with open(output, 'w') as f: + f.write(t.render( + cmd_str=cmd_str, + cmd_count=cmd_count, + name=name + )) + f.flush() + + print("Done") + + +if __name__ == "__main__": + main() diff --git a/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.v b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.v new file mode 100644 index 000000000..3a9acd67b --- /dev/null +++ b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.v @@ -0,0 +1,1041 @@ +/* + +Copyright (c) 2015-2021 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * si5341_i2c_init + */ +module si5341_i2c_init ( + input wire clk, + input wire rst, + + /* + * I2C master interface + */ + output wire [6:0] m_axis_cmd_address, + output wire m_axis_cmd_start, + output wire m_axis_cmd_read, + output wire m_axis_cmd_write, + output wire m_axis_cmd_write_multiple, + output wire m_axis_cmd_stop, + output wire m_axis_cmd_valid, + input wire m_axis_cmd_ready, + + output wire [7:0] m_axis_data_tdata, + output wire m_axis_data_tvalid, + input wire m_axis_data_tready, + output wire m_axis_data_tlast, + + /* + * Status + */ + output wire busy, + + /* + * Configuration + */ + input wire start +); + +/* + +Generic module for I2C bus initialization. Good for use when multiple devices +on an I2C bus must be initialized on system start without intervention of a +general-purpose processor. + +Copy this file and change init_data and INIT_DATA_LEN as needed. + +This module can be used in two modes: simple device initialization, or multiple +device initialization. In multiple device mode, the same initialization sequence +can be performed on multiple different device addresses. + +To use single device mode, only use the start write to address and write data commands. +The module will generate the I2C commands in sequential order. Terminate the list +with a 0 entry. + +To use the multiple device mode, use the start data and start address block commands +to set up lists of initialization data and device addresses. The module enters +multiple device mode upon seeing a start data block command. The module stores the +offset of the start of the data block and then skips ahead until it reaches a start +address block command. The module will store the offset to the address block and +read the first address in the block. Then it will jump back to the data block +and execute it, substituting the stored address for each current address write +command. Upon reaching the start address block command, the module will read out the +next address and start again at the top of the data block. If the module encounters +a start data block command while looking for an address, then it will store a new data +offset and then look for a start address block command. Terminate the list with a 0 +entry. Normal address commands will operate normally inside a data block. + +Commands: + +00 0000000 : stop +00 0000001 : exit multiple device mode +00 0000011 : start write to current address +00 0001000 : start address block +00 0001001 : start data block +00 001dddd : delay 2**(16+d) cycles +00 1000001 : send I2C stop +01 aaaaaaa : start write to address +1 dddddddd : write 8-bit data + +Examples + +write 0x11223344 to register 0x0004 on device at 0x50 + +01 1010000 start write to 0x50 +1 00000000 write address 0x0004 +1 00000100 +1 00010001 write data 0x11223344 +1 00100010 +1 00110011 +1 01000100 +0 00000000 stop + +write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53 + +00 0001001 start data block +00 0000011 start write to current address +1 00000000 write address 0x0004 +1 00000100 +1 00010001 write data 0x11223344 +1 00100010 +1 00110011 +1 01000100 +00 0001000 start address block +01 1010000 address 0x50 +01 1010001 address 0x51 +01 1010010 address 0x52 +01 1010011 address 0x53 +00 0000000 stop + +*/ + +// init_data ROM +localparam INIT_DATA_LEN = 536; + +reg [8:0] init_data [INIT_DATA_LEN-1:0]; + +initial begin + // Initial delay + init_data[0] = 9'b000010110; // delay 30 ms + // Set muxes to select U7 Si5341 on HTG-FMC-x6-QSFP28 + init_data[1] = {2'b01, 7'h74}; + init_data[2] = {1'b1, 8'h00}; + init_data[3] = 9'b001000001; // I2C stop + init_data[4] = {2'b01, 7'h75}; + init_data[5] = {1'b1, 8'h02}; + init_data[6] = 9'b001000001; // I2C stop + // Si534x/7x/8x/9x Registers Script + // + // Part: Si5341 + // Project File: X:\Projects\verilog-ethernet\example\VCU118\fpga_fmc_htg_6qsfp_25g\pll\VCU118_HTG_FMC_6QSFP_156-HTG6Q156.slabtimeproj + // Design ID: HTG6Q156 + // Includes Pre/Post Download Control Register Writes: Yes + // Die Revision: B1 + // Creator: ClockBuilder Pro v4.1 [2021-09-22] + // Created On: 2023-07-19 01:56:40 GMT-07:00 + // + // Start configuration preamble + init_data[7] = {2'b01, 7'h77}; + init_data[8] = {1'b1, 8'h01}; + init_data[9] = {1'b1, 8'h0b}; // set page 0x0b + init_data[10] = {2'b01, 7'h77}; + init_data[11] = {1'b1, 8'h24}; + init_data[12] = {1'b1, 8'hc0}; // write 0xc0 to 0x0b24 + init_data[13] = {1'b1, 8'h00}; // write 0x00 to 0x0b25 + // Rev D stuck divider fix + init_data[14] = {2'b01, 7'h77}; + init_data[15] = {1'b1, 8'h01}; + init_data[16] = {1'b1, 8'h05}; // set page 0x05 + init_data[17] = {2'b01, 7'h77}; + init_data[18] = {1'b1, 8'h02}; + init_data[19] = {1'b1, 8'h01}; // write 0x01 to 0x0502 + init_data[20] = {2'b01, 7'h77}; + init_data[21] = {1'b1, 8'h05}; + init_data[22] = {1'b1, 8'h03}; // write 0x03 to 0x0505 + init_data[23] = {2'b01, 7'h77}; + init_data[24] = {1'b1, 8'h01}; + init_data[25] = {1'b1, 8'h09}; // set page 0x09 + init_data[26] = {2'b01, 7'h77}; + init_data[27] = {1'b1, 8'h57}; + init_data[28] = {1'b1, 8'h17}; // write 0x17 to 0x0957 + init_data[29] = {2'b01, 7'h77}; + init_data[30] = {1'b1, 8'h01}; + init_data[31] = {1'b1, 8'h0b}; // set page 0x0b + init_data[32] = {2'b01, 7'h77}; + init_data[33] = {1'b1, 8'h4e}; + init_data[34] = {1'b1, 8'h1a}; // write 0x1a to 0x0b4e + // End configuration preamble + // + // Delay 300 msec + init_data[35] = 9'b000011010; // delay 300 ms + // Delay is worst case time for device to complete any calibration + // that is running due to device state change previous to this script + // being processed. + // + // Start configuration registers + init_data[36] = {2'b01, 7'h77}; + init_data[37] = {1'b1, 8'h01}; + init_data[38] = {1'b1, 8'h00}; // set page 0x00 + init_data[39] = {2'b01, 7'h77}; + init_data[40] = {1'b1, 8'h06}; + init_data[41] = {1'b1, 8'h00}; // write 0x00 to 0x0006 + init_data[42] = {1'b1, 8'h00}; // write 0x00 to 0x0007 + init_data[43] = {1'b1, 8'h00}; // write 0x00 to 0x0008 + init_data[44] = {2'b01, 7'h77}; + init_data[45] = {1'b1, 8'h0b}; + init_data[46] = {1'b1, 8'h74}; // write 0x74 to 0x000b + init_data[47] = {2'b01, 7'h77}; + init_data[48] = {1'b1, 8'h17}; + init_data[49] = {1'b1, 8'hd0}; // write 0xd0 to 0x0017 + init_data[50] = {1'b1, 8'hff}; // write 0xff to 0x0018 + init_data[51] = {2'b01, 7'h77}; + init_data[52] = {1'b1, 8'h21}; + init_data[53] = {1'b1, 8'h0d}; // write 0x0d to 0x0021 + init_data[54] = {1'b1, 8'h00}; // write 0x00 to 0x0022 + init_data[55] = {2'b01, 7'h77}; + init_data[56] = {1'b1, 8'h2b}; + init_data[57] = {1'b1, 8'h02}; // write 0x02 to 0x002b + init_data[58] = {1'b1, 8'h34}; // write 0x34 to 0x002c + init_data[59] = {1'b1, 8'h10}; // write 0x10 to 0x002d + init_data[60] = {1'b1, 8'h00}; // write 0x00 to 0x002e + init_data[61] = {1'b1, 8'h00}; // write 0x00 to 0x002f + init_data[62] = {1'b1, 8'h00}; // write 0x00 to 0x0030 + init_data[63] = {1'b1, 8'h00}; // write 0x00 to 0x0031 + init_data[64] = {1'b1, 8'hb1}; // write 0xb1 to 0x0032 + init_data[65] = {1'b1, 8'h00}; // write 0x00 to 0x0033 + init_data[66] = {1'b1, 8'h00}; // write 0x00 to 0x0034 + init_data[67] = {1'b1, 8'h00}; // write 0x00 to 0x0035 + init_data[68] = {1'b1, 8'h00}; // write 0x00 to 0x0036 + init_data[69] = {1'b1, 8'h00}; // write 0x00 to 0x0037 + init_data[70] = {1'b1, 8'h00}; // write 0x00 to 0x0038 + init_data[71] = {1'b1, 8'h00}; // write 0x00 to 0x0039 + init_data[72] = {1'b1, 8'hb1}; // write 0xb1 to 0x003a + init_data[73] = {1'b1, 8'h00}; // write 0x00 to 0x003b + init_data[74] = {1'b1, 8'h00}; // write 0x00 to 0x003c + init_data[75] = {1'b1, 8'h00}; // write 0x00 to 0x003d + init_data[76] = {2'b01, 7'h77}; + init_data[77] = {1'b1, 8'h41}; + init_data[78] = {1'b1, 8'h00}; // write 0x00 to 0x0041 + init_data[79] = {1'b1, 8'h00}; // write 0x00 to 0x0042 + init_data[80] = {1'b1, 8'h07}; // write 0x07 to 0x0043 + init_data[81] = {1'b1, 8'h00}; // write 0x00 to 0x0044 + init_data[82] = {2'b01, 7'h77}; + init_data[83] = {1'b1, 8'h9e}; + init_data[84] = {1'b1, 8'h00}; // write 0x00 to 0x009e + init_data[85] = {2'b01, 7'h77}; + init_data[86] = {1'b1, 8'h01}; + init_data[87] = {1'b1, 8'h01}; // set page 0x01 + init_data[88] = {2'b01, 7'h77}; + init_data[89] = {1'b1, 8'h02}; + init_data[90] = {1'b1, 8'h01}; // write 0x01 to 0x0102 + init_data[91] = {2'b01, 7'h77}; + init_data[92] = {1'b1, 8'h08}; + init_data[93] = {1'b1, 8'h06}; // write 0x06 to 0x0108 + init_data[94] = {1'b1, 8'h09}; // write 0x09 to 0x0109 + init_data[95] = {1'b1, 8'h33}; // write 0x33 to 0x010a + init_data[96] = {1'b1, 8'h08}; // write 0x08 to 0x010b + init_data[97] = {2'b01, 7'h77}; + init_data[98] = {1'b1, 8'h0d}; + init_data[99] = {1'b1, 8'h06}; // write 0x06 to 0x010d + init_data[100] = {1'b1, 8'h09}; // write 0x09 to 0x010e + init_data[101] = {1'b1, 8'h33}; // write 0x33 to 0x010f + init_data[102] = {1'b1, 8'h08}; // write 0x08 to 0x0110 + init_data[103] = {2'b01, 7'h77}; + init_data[104] = {1'b1, 8'h12}; + init_data[105] = {1'b1, 8'h06}; // write 0x06 to 0x0112 + init_data[106] = {1'b1, 8'h09}; // write 0x09 to 0x0113 + init_data[107] = {1'b1, 8'h33}; // write 0x33 to 0x0114 + init_data[108] = {1'b1, 8'h08}; // write 0x08 to 0x0115 + init_data[109] = {2'b01, 7'h77}; + init_data[110] = {1'b1, 8'h17}; + init_data[111] = {1'b1, 8'h06}; // write 0x06 to 0x0117 + init_data[112] = {1'b1, 8'h09}; // write 0x09 to 0x0118 + init_data[113] = {1'b1, 8'h33}; // write 0x33 to 0x0119 + init_data[114] = {1'b1, 8'h08}; // write 0x08 to 0x011a + init_data[115] = {2'b01, 7'h77}; + init_data[116] = {1'b1, 8'h1c}; + init_data[117] = {1'b1, 8'h06}; // write 0x06 to 0x011c + init_data[118] = {1'b1, 8'h09}; // write 0x09 to 0x011d + init_data[119] = {1'b1, 8'h33}; // write 0x33 to 0x011e + init_data[120] = {1'b1, 8'h08}; // write 0x08 to 0x011f + init_data[121] = {2'b01, 7'h77}; + init_data[122] = {1'b1, 8'h21}; + init_data[123] = {1'b1, 8'h06}; // write 0x06 to 0x0121 + init_data[124] = {1'b1, 8'h09}; // write 0x09 to 0x0122 + init_data[125] = {1'b1, 8'h33}; // write 0x33 to 0x0123 + init_data[126] = {1'b1, 8'h08}; // write 0x08 to 0x0124 + init_data[127] = {2'b01, 7'h77}; + init_data[128] = {1'b1, 8'h26}; + init_data[129] = {1'b1, 8'h06}; // write 0x06 to 0x0126 + init_data[130] = {1'b1, 8'h09}; // write 0x09 to 0x0127 + init_data[131] = {1'b1, 8'h33}; // write 0x33 to 0x0128 + init_data[132] = {1'b1, 8'h08}; // write 0x08 to 0x0129 + init_data[133] = {2'b01, 7'h77}; + init_data[134] = {1'b1, 8'h2b}; + init_data[135] = {1'b1, 8'h06}; // write 0x06 to 0x012b + init_data[136] = {1'b1, 8'h09}; // write 0x09 to 0x012c + init_data[137] = {1'b1, 8'h33}; // write 0x33 to 0x012d + init_data[138] = {1'b1, 8'h08}; // write 0x08 to 0x012e + init_data[139] = {2'b01, 7'h77}; + init_data[140] = {1'b1, 8'h30}; + init_data[141] = {1'b1, 8'h06}; // write 0x06 to 0x0130 + init_data[142] = {1'b1, 8'h09}; // write 0x09 to 0x0131 + init_data[143] = {1'b1, 8'h33}; // write 0x33 to 0x0132 + init_data[144] = {1'b1, 8'h08}; // write 0x08 to 0x0133 + init_data[145] = {2'b01, 7'h77}; + init_data[146] = {1'b1, 8'h3a}; + init_data[147] = {1'b1, 8'h01}; // write 0x01 to 0x013a + init_data[148] = {1'b1, 8'h09}; // write 0x09 to 0x013b + init_data[149] = {1'b1, 8'h3b}; // write 0x3b to 0x013c + init_data[150] = {1'b1, 8'h28}; // write 0x28 to 0x013d + init_data[151] = {2'b01, 7'h77}; + init_data[152] = {1'b1, 8'h3f}; + init_data[153] = {1'b1, 8'h00}; // write 0x00 to 0x013f + init_data[154] = {1'b1, 8'h00}; // write 0x00 to 0x0140 + init_data[155] = {1'b1, 8'h40}; // write 0x40 to 0x0141 + init_data[156] = {2'b01, 7'h77}; + init_data[157] = {1'b1, 8'h01}; + init_data[158] = {1'b1, 8'h02}; // set page 0x02 + init_data[159] = {2'b01, 7'h77}; + init_data[160] = {1'b1, 8'h06}; + init_data[161] = {1'b1, 8'h00}; // write 0x00 to 0x0206 + init_data[162] = {2'b01, 7'h77}; + init_data[163] = {1'b1, 8'h08}; + init_data[164] = {1'b1, 8'h00}; // write 0x00 to 0x0208 + init_data[165] = {1'b1, 8'h00}; // write 0x00 to 0x0209 + init_data[166] = {1'b1, 8'h00}; // write 0x00 to 0x020a + init_data[167] = {1'b1, 8'h00}; // write 0x00 to 0x020b + init_data[168] = {1'b1, 8'h00}; // write 0x00 to 0x020c + init_data[169] = {1'b1, 8'h00}; // write 0x00 to 0x020d + init_data[170] = {1'b1, 8'h00}; // write 0x00 to 0x020e + init_data[171] = {1'b1, 8'h00}; // write 0x00 to 0x020f + init_data[172] = {1'b1, 8'h00}; // write 0x00 to 0x0210 + init_data[173] = {1'b1, 8'h00}; // write 0x00 to 0x0211 + init_data[174] = {1'b1, 8'h00}; // write 0x00 to 0x0212 + init_data[175] = {1'b1, 8'h00}; // write 0x00 to 0x0213 + init_data[176] = {1'b1, 8'h00}; // write 0x00 to 0x0214 + init_data[177] = {1'b1, 8'h00}; // write 0x00 to 0x0215 + init_data[178] = {1'b1, 8'h00}; // write 0x00 to 0x0216 + init_data[179] = {1'b1, 8'h00}; // write 0x00 to 0x0217 + init_data[180] = {1'b1, 8'h00}; // write 0x00 to 0x0218 + init_data[181] = {1'b1, 8'h00}; // write 0x00 to 0x0219 + init_data[182] = {1'b1, 8'h00}; // write 0x00 to 0x021a + init_data[183] = {1'b1, 8'h00}; // write 0x00 to 0x021b + init_data[184] = {1'b1, 8'h02}; // write 0x02 to 0x021c + init_data[185] = {1'b1, 8'h00}; // write 0x00 to 0x021d + init_data[186] = {1'b1, 8'h00}; // write 0x00 to 0x021e + init_data[187] = {1'b1, 8'h00}; // write 0x00 to 0x021f + init_data[188] = {1'b1, 8'h00}; // write 0x00 to 0x0220 + init_data[189] = {1'b1, 8'h00}; // write 0x00 to 0x0221 + init_data[190] = {1'b1, 8'h01}; // write 0x01 to 0x0222 + init_data[191] = {1'b1, 8'h00}; // write 0x00 to 0x0223 + init_data[192] = {1'b1, 8'h00}; // write 0x00 to 0x0224 + init_data[193] = {1'b1, 8'h00}; // write 0x00 to 0x0225 + init_data[194] = {1'b1, 8'h00}; // write 0x00 to 0x0226 + init_data[195] = {1'b1, 8'h00}; // write 0x00 to 0x0227 + init_data[196] = {1'b1, 8'h00}; // write 0x00 to 0x0228 + init_data[197] = {1'b1, 8'h00}; // write 0x00 to 0x0229 + init_data[198] = {1'b1, 8'h00}; // write 0x00 to 0x022a + init_data[199] = {1'b1, 8'h00}; // write 0x00 to 0x022b + init_data[200] = {1'b1, 8'h00}; // write 0x00 to 0x022c + init_data[201] = {1'b1, 8'h00}; // write 0x00 to 0x022d + init_data[202] = {1'b1, 8'h00}; // write 0x00 to 0x022e + init_data[203] = {1'b1, 8'h00}; // write 0x00 to 0x022f + init_data[204] = {2'b01, 7'h77}; + init_data[205] = {1'b1, 8'h35}; + init_data[206] = {1'b1, 8'h00}; // write 0x00 to 0x0235 + init_data[207] = {1'b1, 8'h00}; // write 0x00 to 0x0236 + init_data[208] = {1'b1, 8'h00}; // write 0x00 to 0x0237 + init_data[209] = {1'b1, 8'h00}; // write 0x00 to 0x0238 + init_data[210] = {1'b1, 8'h56}; // write 0x56 to 0x0239 + init_data[211] = {1'b1, 8'h00}; // write 0x00 to 0x023a + init_data[212] = {1'b1, 8'h00}; // write 0x00 to 0x023b + init_data[213] = {1'b1, 8'h00}; // write 0x00 to 0x023c + init_data[214] = {1'b1, 8'h00}; // write 0x00 to 0x023d + init_data[215] = {1'b1, 8'h80}; // write 0x80 to 0x023e + init_data[216] = {2'b01, 7'h77}; + init_data[217] = {1'b1, 8'h4a}; + init_data[218] = {1'b1, 8'h00}; // write 0x00 to 0x024a + init_data[219] = {1'b1, 8'h00}; // write 0x00 to 0x024b + init_data[220] = {1'b1, 8'h00}; // write 0x00 to 0x024c + init_data[221] = {1'b1, 8'h00}; // write 0x00 to 0x024d + init_data[222] = {1'b1, 8'h00}; // write 0x00 to 0x024e + init_data[223] = {1'b1, 8'h00}; // write 0x00 to 0x024f + init_data[224] = {1'b1, 8'h00}; // write 0x00 to 0x0250 + init_data[225] = {1'b1, 8'h00}; // write 0x00 to 0x0251 + init_data[226] = {1'b1, 8'h00}; // write 0x00 to 0x0252 + init_data[227] = {1'b1, 8'h00}; // write 0x00 to 0x0253 + init_data[228] = {1'b1, 8'h00}; // write 0x00 to 0x0254 + init_data[229] = {1'b1, 8'h00}; // write 0x00 to 0x0255 + init_data[230] = {1'b1, 8'h00}; // write 0x00 to 0x0256 + init_data[231] = {1'b1, 8'h00}; // write 0x00 to 0x0257 + init_data[232] = {1'b1, 8'h00}; // write 0x00 to 0x0258 + init_data[233] = {1'b1, 8'h00}; // write 0x00 to 0x0259 + init_data[234] = {1'b1, 8'h00}; // write 0x00 to 0x025a + init_data[235] = {1'b1, 8'h00}; // write 0x00 to 0x025b + init_data[236] = {1'b1, 8'h00}; // write 0x00 to 0x025c + init_data[237] = {1'b1, 8'h00}; // write 0x00 to 0x025d + init_data[238] = {1'b1, 8'h00}; // write 0x00 to 0x025e + init_data[239] = {1'b1, 8'h00}; // write 0x00 to 0x025f + init_data[240] = {1'b1, 8'h00}; // write 0x00 to 0x0260 + init_data[241] = {1'b1, 8'h00}; // write 0x00 to 0x0261 + init_data[242] = {1'b1, 8'h00}; // write 0x00 to 0x0262 + init_data[243] = {1'b1, 8'h00}; // write 0x00 to 0x0263 + init_data[244] = {1'b1, 8'h00}; // write 0x00 to 0x0264 + init_data[245] = {2'b01, 7'h77}; + init_data[246] = {1'b1, 8'h68}; + init_data[247] = {1'b1, 8'h00}; // write 0x00 to 0x0268 + init_data[248] = {1'b1, 8'h00}; // write 0x00 to 0x0269 + init_data[249] = {1'b1, 8'h00}; // write 0x00 to 0x026a + init_data[250] = {1'b1, 8'h48}; // write 0x48 to 0x026b + init_data[251] = {1'b1, 8'h54}; // write 0x54 to 0x026c + init_data[252] = {1'b1, 8'h47}; // write 0x47 to 0x026d + init_data[253] = {1'b1, 8'h36}; // write 0x36 to 0x026e + init_data[254] = {1'b1, 8'h51}; // write 0x51 to 0x026f + init_data[255] = {1'b1, 8'h31}; // write 0x31 to 0x0270 + init_data[256] = {1'b1, 8'h35}; // write 0x35 to 0x0271 + init_data[257] = {1'b1, 8'h36}; // write 0x36 to 0x0272 + init_data[258] = {2'b01, 7'h77}; + init_data[259] = {1'b1, 8'h01}; + init_data[260] = {1'b1, 8'h03}; // set page 0x03 + init_data[261] = {2'b01, 7'h77}; + init_data[262] = {1'b1, 8'h02}; + init_data[263] = {1'b1, 8'h00}; // write 0x00 to 0x0302 + init_data[264] = {1'b1, 8'h00}; // write 0x00 to 0x0303 + init_data[265] = {1'b1, 8'h00}; // write 0x00 to 0x0304 + init_data[266] = {1'b1, 8'h80}; // write 0x80 to 0x0305 + init_data[267] = {1'b1, 8'h15}; // write 0x15 to 0x0306 + init_data[268] = {1'b1, 8'h00}; // write 0x00 to 0x0307 + init_data[269] = {1'b1, 8'h00}; // write 0x00 to 0x0308 + init_data[270] = {1'b1, 8'h00}; // write 0x00 to 0x0309 + init_data[271] = {1'b1, 8'h00}; // write 0x00 to 0x030a + init_data[272] = {1'b1, 8'h80}; // write 0x80 to 0x030b + init_data[273] = {1'b1, 8'h00}; // write 0x00 to 0x030c + init_data[274] = {1'b1, 8'h00}; // write 0x00 to 0x030d + init_data[275] = {1'b1, 8'h00}; // write 0x00 to 0x030e + init_data[276] = {1'b1, 8'h00}; // write 0x00 to 0x030f + init_data[277] = {1'b1, 8'h00}; // write 0x00 to 0x0310 + init_data[278] = {1'b1, 8'h00}; // write 0x00 to 0x0311 + init_data[279] = {1'b1, 8'h00}; // write 0x00 to 0x0312 + init_data[280] = {1'b1, 8'h00}; // write 0x00 to 0x0313 + init_data[281] = {1'b1, 8'h00}; // write 0x00 to 0x0314 + init_data[282] = {1'b1, 8'h00}; // write 0x00 to 0x0315 + init_data[283] = {1'b1, 8'h00}; // write 0x00 to 0x0316 + init_data[284] = {1'b1, 8'h00}; // write 0x00 to 0x0317 + init_data[285] = {1'b1, 8'h00}; // write 0x00 to 0x0318 + init_data[286] = {1'b1, 8'h00}; // write 0x00 to 0x0319 + init_data[287] = {1'b1, 8'h00}; // write 0x00 to 0x031a + init_data[288] = {1'b1, 8'h00}; // write 0x00 to 0x031b + init_data[289] = {1'b1, 8'h00}; // write 0x00 to 0x031c + init_data[290] = {1'b1, 8'h00}; // write 0x00 to 0x031d + init_data[291] = {1'b1, 8'h00}; // write 0x00 to 0x031e + init_data[292] = {1'b1, 8'h00}; // write 0x00 to 0x031f + init_data[293] = {1'b1, 8'h00}; // write 0x00 to 0x0320 + init_data[294] = {1'b1, 8'h00}; // write 0x00 to 0x0321 + init_data[295] = {1'b1, 8'h00}; // write 0x00 to 0x0322 + init_data[296] = {1'b1, 8'h00}; // write 0x00 to 0x0323 + init_data[297] = {1'b1, 8'h00}; // write 0x00 to 0x0324 + init_data[298] = {1'b1, 8'h00}; // write 0x00 to 0x0325 + init_data[299] = {1'b1, 8'h00}; // write 0x00 to 0x0326 + init_data[300] = {1'b1, 8'h00}; // write 0x00 to 0x0327 + init_data[301] = {1'b1, 8'h00}; // write 0x00 to 0x0328 + init_data[302] = {1'b1, 8'h00}; // write 0x00 to 0x0329 + init_data[303] = {1'b1, 8'h00}; // write 0x00 to 0x032a + init_data[304] = {1'b1, 8'h00}; // write 0x00 to 0x032b + init_data[305] = {1'b1, 8'h00}; // write 0x00 to 0x032c + init_data[306] = {1'b1, 8'h00}; // write 0x00 to 0x032d + init_data[307] = {1'b1, 8'h00}; // write 0x00 to 0x032e + init_data[308] = {1'b1, 8'h00}; // write 0x00 to 0x032f + init_data[309] = {1'b1, 8'h00}; // write 0x00 to 0x0330 + init_data[310] = {1'b1, 8'h00}; // write 0x00 to 0x0331 + init_data[311] = {1'b1, 8'h00}; // write 0x00 to 0x0332 + init_data[312] = {1'b1, 8'h00}; // write 0x00 to 0x0333 + init_data[313] = {1'b1, 8'h00}; // write 0x00 to 0x0334 + init_data[314] = {1'b1, 8'h00}; // write 0x00 to 0x0335 + init_data[315] = {1'b1, 8'h00}; // write 0x00 to 0x0336 + init_data[316] = {1'b1, 8'h00}; // write 0x00 to 0x0337 + init_data[317] = {1'b1, 8'h00}; // write 0x00 to 0x0338 + init_data[318] = {1'b1, 8'h1f}; // write 0x1f to 0x0339 + init_data[319] = {2'b01, 7'h77}; + init_data[320] = {1'b1, 8'h3b}; + init_data[321] = {1'b1, 8'h00}; // write 0x00 to 0x033b + init_data[322] = {1'b1, 8'h00}; // write 0x00 to 0x033c + init_data[323] = {1'b1, 8'h00}; // write 0x00 to 0x033d + init_data[324] = {1'b1, 8'h00}; // write 0x00 to 0x033e + init_data[325] = {1'b1, 8'h00}; // write 0x00 to 0x033f + init_data[326] = {1'b1, 8'h00}; // write 0x00 to 0x0340 + init_data[327] = {1'b1, 8'h00}; // write 0x00 to 0x0341 + init_data[328] = {1'b1, 8'h00}; // write 0x00 to 0x0342 + init_data[329] = {1'b1, 8'h00}; // write 0x00 to 0x0343 + init_data[330] = {1'b1, 8'h00}; // write 0x00 to 0x0344 + init_data[331] = {1'b1, 8'h00}; // write 0x00 to 0x0345 + init_data[332] = {1'b1, 8'h00}; // write 0x00 to 0x0346 + init_data[333] = {1'b1, 8'h00}; // write 0x00 to 0x0347 + init_data[334] = {1'b1, 8'h00}; // write 0x00 to 0x0348 + init_data[335] = {1'b1, 8'h00}; // write 0x00 to 0x0349 + init_data[336] = {1'b1, 8'h00}; // write 0x00 to 0x034a + init_data[337] = {1'b1, 8'h00}; // write 0x00 to 0x034b + init_data[338] = {1'b1, 8'h00}; // write 0x00 to 0x034c + init_data[339] = {1'b1, 8'h00}; // write 0x00 to 0x034d + init_data[340] = {1'b1, 8'h00}; // write 0x00 to 0x034e + init_data[341] = {1'b1, 8'h00}; // write 0x00 to 0x034f + init_data[342] = {1'b1, 8'h00}; // write 0x00 to 0x0350 + init_data[343] = {1'b1, 8'h00}; // write 0x00 to 0x0351 + init_data[344] = {1'b1, 8'h00}; // write 0x00 to 0x0352 + init_data[345] = {1'b1, 8'h00}; // write 0x00 to 0x0353 + init_data[346] = {1'b1, 8'h00}; // write 0x00 to 0x0354 + init_data[347] = {1'b1, 8'h00}; // write 0x00 to 0x0355 + init_data[348] = {1'b1, 8'h00}; // write 0x00 to 0x0356 + init_data[349] = {1'b1, 8'h00}; // write 0x00 to 0x0357 + init_data[350] = {1'b1, 8'h00}; // write 0x00 to 0x0358 + init_data[351] = {1'b1, 8'h00}; // write 0x00 to 0x0359 + init_data[352] = {1'b1, 8'h00}; // write 0x00 to 0x035a + init_data[353] = {1'b1, 8'h00}; // write 0x00 to 0x035b + init_data[354] = {1'b1, 8'h00}; // write 0x00 to 0x035c + init_data[355] = {1'b1, 8'h00}; // write 0x00 to 0x035d + init_data[356] = {1'b1, 8'h00}; // write 0x00 to 0x035e + init_data[357] = {1'b1, 8'h00}; // write 0x00 to 0x035f + init_data[358] = {1'b1, 8'h00}; // write 0x00 to 0x0360 + init_data[359] = {1'b1, 8'h00}; // write 0x00 to 0x0361 + init_data[360] = {1'b1, 8'h00}; // write 0x00 to 0x0362 + init_data[361] = {2'b01, 7'h77}; + init_data[362] = {1'b1, 8'h01}; + init_data[363] = {1'b1, 8'h08}; // set page 0x08 + init_data[364] = {2'b01, 7'h77}; + init_data[365] = {1'b1, 8'h02}; + init_data[366] = {1'b1, 8'h00}; // write 0x00 to 0x0802 + init_data[367] = {1'b1, 8'h00}; // write 0x00 to 0x0803 + init_data[368] = {1'b1, 8'h00}; // write 0x00 to 0x0804 + init_data[369] = {1'b1, 8'h00}; // write 0x00 to 0x0805 + init_data[370] = {1'b1, 8'h00}; // write 0x00 to 0x0806 + init_data[371] = {1'b1, 8'h00}; // write 0x00 to 0x0807 + init_data[372] = {1'b1, 8'h00}; // write 0x00 to 0x0808 + init_data[373] = {1'b1, 8'h00}; // write 0x00 to 0x0809 + init_data[374] = {1'b1, 8'h00}; // write 0x00 to 0x080a + init_data[375] = {1'b1, 8'h00}; // write 0x00 to 0x080b + init_data[376] = {1'b1, 8'h00}; // write 0x00 to 0x080c + init_data[377] = {1'b1, 8'h00}; // write 0x00 to 0x080d + init_data[378] = {1'b1, 8'h00}; // write 0x00 to 0x080e + init_data[379] = {1'b1, 8'h00}; // write 0x00 to 0x080f + init_data[380] = {1'b1, 8'h00}; // write 0x00 to 0x0810 + init_data[381] = {1'b1, 8'h00}; // write 0x00 to 0x0811 + init_data[382] = {1'b1, 8'h00}; // write 0x00 to 0x0812 + init_data[383] = {1'b1, 8'h00}; // write 0x00 to 0x0813 + init_data[384] = {1'b1, 8'h00}; // write 0x00 to 0x0814 + init_data[385] = {1'b1, 8'h00}; // write 0x00 to 0x0815 + init_data[386] = {1'b1, 8'h00}; // write 0x00 to 0x0816 + init_data[387] = {1'b1, 8'h00}; // write 0x00 to 0x0817 + init_data[388] = {1'b1, 8'h00}; // write 0x00 to 0x0818 + init_data[389] = {1'b1, 8'h00}; // write 0x00 to 0x0819 + init_data[390] = {1'b1, 8'h00}; // write 0x00 to 0x081a + init_data[391] = {1'b1, 8'h00}; // write 0x00 to 0x081b + init_data[392] = {1'b1, 8'h00}; // write 0x00 to 0x081c + init_data[393] = {1'b1, 8'h00}; // write 0x00 to 0x081d + init_data[394] = {1'b1, 8'h00}; // write 0x00 to 0x081e + init_data[395] = {1'b1, 8'h00}; // write 0x00 to 0x081f + init_data[396] = {1'b1, 8'h00}; // write 0x00 to 0x0820 + init_data[397] = {1'b1, 8'h00}; // write 0x00 to 0x0821 + init_data[398] = {1'b1, 8'h00}; // write 0x00 to 0x0822 + init_data[399] = {1'b1, 8'h00}; // write 0x00 to 0x0823 + init_data[400] = {1'b1, 8'h00}; // write 0x00 to 0x0824 + init_data[401] = {1'b1, 8'h00}; // write 0x00 to 0x0825 + init_data[402] = {1'b1, 8'h00}; // write 0x00 to 0x0826 + init_data[403] = {1'b1, 8'h00}; // write 0x00 to 0x0827 + init_data[404] = {1'b1, 8'h00}; // write 0x00 to 0x0828 + init_data[405] = {1'b1, 8'h00}; // write 0x00 to 0x0829 + init_data[406] = {1'b1, 8'h00}; // write 0x00 to 0x082a + init_data[407] = {1'b1, 8'h00}; // write 0x00 to 0x082b + init_data[408] = {1'b1, 8'h00}; // write 0x00 to 0x082c + init_data[409] = {1'b1, 8'h00}; // write 0x00 to 0x082d + init_data[410] = {1'b1, 8'h00}; // write 0x00 to 0x082e + init_data[411] = {1'b1, 8'h00}; // write 0x00 to 0x082f + init_data[412] = {1'b1, 8'h00}; // write 0x00 to 0x0830 + init_data[413] = {1'b1, 8'h00}; // write 0x00 to 0x0831 + init_data[414] = {1'b1, 8'h00}; // write 0x00 to 0x0832 + init_data[415] = {1'b1, 8'h00}; // write 0x00 to 0x0833 + init_data[416] = {1'b1, 8'h00}; // write 0x00 to 0x0834 + init_data[417] = {1'b1, 8'h00}; // write 0x00 to 0x0835 + init_data[418] = {1'b1, 8'h00}; // write 0x00 to 0x0836 + init_data[419] = {1'b1, 8'h00}; // write 0x00 to 0x0837 + init_data[420] = {1'b1, 8'h00}; // write 0x00 to 0x0838 + init_data[421] = {1'b1, 8'h00}; // write 0x00 to 0x0839 + init_data[422] = {1'b1, 8'h00}; // write 0x00 to 0x083a + init_data[423] = {1'b1, 8'h00}; // write 0x00 to 0x083b + init_data[424] = {1'b1, 8'h00}; // write 0x00 to 0x083c + init_data[425] = {1'b1, 8'h00}; // write 0x00 to 0x083d + init_data[426] = {1'b1, 8'h00}; // write 0x00 to 0x083e + init_data[427] = {1'b1, 8'h00}; // write 0x00 to 0x083f + init_data[428] = {1'b1, 8'h00}; // write 0x00 to 0x0840 + init_data[429] = {1'b1, 8'h00}; // write 0x00 to 0x0841 + init_data[430] = {1'b1, 8'h00}; // write 0x00 to 0x0842 + init_data[431] = {1'b1, 8'h00}; // write 0x00 to 0x0843 + init_data[432] = {1'b1, 8'h00}; // write 0x00 to 0x0844 + init_data[433] = {1'b1, 8'h00}; // write 0x00 to 0x0845 + init_data[434] = {1'b1, 8'h00}; // write 0x00 to 0x0846 + init_data[435] = {1'b1, 8'h00}; // write 0x00 to 0x0847 + init_data[436] = {1'b1, 8'h00}; // write 0x00 to 0x0848 + init_data[437] = {1'b1, 8'h00}; // write 0x00 to 0x0849 + init_data[438] = {1'b1, 8'h00}; // write 0x00 to 0x084a + init_data[439] = {1'b1, 8'h00}; // write 0x00 to 0x084b + init_data[440] = {1'b1, 8'h00}; // write 0x00 to 0x084c + init_data[441] = {1'b1, 8'h00}; // write 0x00 to 0x084d + init_data[442] = {1'b1, 8'h00}; // write 0x00 to 0x084e + init_data[443] = {1'b1, 8'h00}; // write 0x00 to 0x084f + init_data[444] = {1'b1, 8'h00}; // write 0x00 to 0x0850 + init_data[445] = {1'b1, 8'h00}; // write 0x00 to 0x0851 + init_data[446] = {1'b1, 8'h00}; // write 0x00 to 0x0852 + init_data[447] = {1'b1, 8'h00}; // write 0x00 to 0x0853 + init_data[448] = {1'b1, 8'h00}; // write 0x00 to 0x0854 + init_data[449] = {1'b1, 8'h00}; // write 0x00 to 0x0855 + init_data[450] = {1'b1, 8'h00}; // write 0x00 to 0x0856 + init_data[451] = {1'b1, 8'h00}; // write 0x00 to 0x0857 + init_data[452] = {1'b1, 8'h00}; // write 0x00 to 0x0858 + init_data[453] = {1'b1, 8'h00}; // write 0x00 to 0x0859 + init_data[454] = {1'b1, 8'h00}; // write 0x00 to 0x085a + init_data[455] = {1'b1, 8'h00}; // write 0x00 to 0x085b + init_data[456] = {1'b1, 8'h00}; // write 0x00 to 0x085c + init_data[457] = {1'b1, 8'h00}; // write 0x00 to 0x085d + init_data[458] = {1'b1, 8'h00}; // write 0x00 to 0x085e + init_data[459] = {1'b1, 8'h00}; // write 0x00 to 0x085f + init_data[460] = {1'b1, 8'h00}; // write 0x00 to 0x0860 + init_data[461] = {1'b1, 8'h00}; // write 0x00 to 0x0861 + init_data[462] = {2'b01, 7'h77}; + init_data[463] = {1'b1, 8'h01}; + init_data[464] = {1'b1, 8'h09}; // set page 0x09 + init_data[465] = {2'b01, 7'h77}; + init_data[466] = {1'b1, 8'h0e}; + init_data[467] = {1'b1, 8'h00}; // write 0x00 to 0x090e + init_data[468] = {2'b01, 7'h77}; + init_data[469] = {1'b1, 8'h1c}; + init_data[470] = {1'b1, 8'h04}; // write 0x04 to 0x091c + init_data[471] = {2'b01, 7'h77}; + init_data[472] = {1'b1, 8'h43}; + init_data[473] = {1'b1, 8'h00}; // write 0x00 to 0x0943 + init_data[474] = {2'b01, 7'h77}; + init_data[475] = {1'b1, 8'h49}; + init_data[476] = {1'b1, 8'h04}; // write 0x04 to 0x0949 + init_data[477] = {1'b1, 8'h40}; // write 0x40 to 0x094a + init_data[478] = {2'b01, 7'h77}; + init_data[479] = {1'b1, 8'h4e}; + init_data[480] = {1'b1, 8'h49}; // write 0x49 to 0x094e + init_data[481] = {1'b1, 8'h02}; // write 0x02 to 0x094f + init_data[482] = {2'b01, 7'h77}; + init_data[483] = {1'b1, 8'h5e}; + init_data[484] = {1'b1, 8'h00}; // write 0x00 to 0x095e + init_data[485] = {2'b01, 7'h77}; + init_data[486] = {1'b1, 8'h01}; + init_data[487] = {1'b1, 8'h0a}; // set page 0x0a + init_data[488] = {2'b01, 7'h77}; + init_data[489] = {1'b1, 8'h02}; + init_data[490] = {1'b1, 8'h00}; // write 0x00 to 0x0a02 + init_data[491] = {1'b1, 8'h01}; // write 0x01 to 0x0a03 + init_data[492] = {1'b1, 8'h01}; // write 0x01 to 0x0a04 + init_data[493] = {1'b1, 8'h01}; // write 0x01 to 0x0a05 + init_data[494] = {2'b01, 7'h77}; + init_data[495] = {1'b1, 8'h14}; + init_data[496] = {1'b1, 8'h00}; // write 0x00 to 0x0a14 + init_data[497] = {2'b01, 7'h77}; + init_data[498] = {1'b1, 8'h1a}; + init_data[499] = {1'b1, 8'h00}; // write 0x00 to 0x0a1a + init_data[500] = {2'b01, 7'h77}; + init_data[501] = {1'b1, 8'h20}; + init_data[502] = {1'b1, 8'h00}; // write 0x00 to 0x0a20 + init_data[503] = {2'b01, 7'h77}; + init_data[504] = {1'b1, 8'h26}; + init_data[505] = {1'b1, 8'h00}; // write 0x00 to 0x0a26 + init_data[506] = {2'b01, 7'h77}; + init_data[507] = {1'b1, 8'h2c}; + init_data[508] = {1'b1, 8'h00}; // write 0x00 to 0x0a2c + init_data[509] = {2'b01, 7'h77}; + init_data[510] = {1'b1, 8'h01}; + init_data[511] = {1'b1, 8'h0b}; // set page 0x0b + init_data[512] = {2'b01, 7'h77}; + init_data[513] = {1'b1, 8'h44}; + init_data[514] = {1'b1, 8'h0f}; // write 0x0f to 0x0b44 + init_data[515] = {2'b01, 7'h77}; + init_data[516] = {1'b1, 8'h4a}; + init_data[517] = {1'b1, 8'h1e}; // write 0x1e to 0x0b4a + init_data[518] = {2'b01, 7'h77}; + init_data[519] = {1'b1, 8'h57}; + init_data[520] = {1'b1, 8'ha5}; // write 0xa5 to 0x0b57 + init_data[521] = {1'b1, 8'h00}; // write 0x00 to 0x0b58 + // End configuration registers + // + // Start configuration postamble + init_data[522] = {2'b01, 7'h77}; + init_data[523] = {1'b1, 8'h01}; + init_data[524] = {1'b1, 8'h00}; // set page 0x00 + init_data[525] = {2'b01, 7'h77}; + init_data[526] = {1'b1, 8'h1c}; + init_data[527] = {1'b1, 8'h01}; // write 0x01 to 0x001c + init_data[528] = {2'b01, 7'h77}; + init_data[529] = {1'b1, 8'h01}; + init_data[530] = {1'b1, 8'h0b}; // set page 0x0b + init_data[531] = {2'b01, 7'h77}; + init_data[532] = {1'b1, 8'h24}; + init_data[533] = {1'b1, 8'hc3}; // write 0xc3 to 0x0b24 + init_data[534] = {1'b1, 8'h02}; // write 0x02 to 0x0b25 + // End configuration postamble + init_data[535] = 9'd0; // end +end + +localparam [3:0] + STATE_IDLE = 3'd0, + STATE_RUN = 3'd1, + STATE_TABLE_1 = 3'd2, + STATE_TABLE_2 = 3'd3, + STATE_TABLE_3 = 3'd4; + +reg [4:0] state_reg = STATE_IDLE, state_next; + +parameter AW = $clog2(INIT_DATA_LEN); + +reg [8:0] init_data_reg = 9'd0; + +reg [AW-1:0] address_reg = {AW{1'b0}}, address_next; +reg [AW-1:0] address_ptr_reg = {AW{1'b0}}, address_ptr_next; +reg [AW-1:0] data_ptr_reg = {AW{1'b0}}, data_ptr_next; + +reg [6:0] cur_address_reg = 7'd0, cur_address_next; + +reg [31:0] delay_counter_reg = 32'd0, delay_counter_next; + +reg [6:0] m_axis_cmd_address_reg = 7'd0, m_axis_cmd_address_next; +reg m_axis_cmd_start_reg = 1'b0, m_axis_cmd_start_next; +reg m_axis_cmd_write_reg = 1'b0, m_axis_cmd_write_next; +reg m_axis_cmd_stop_reg = 1'b0, m_axis_cmd_stop_next; +reg m_axis_cmd_valid_reg = 1'b0, m_axis_cmd_valid_next; + +reg [7:0] m_axis_data_tdata_reg = 8'd0, m_axis_data_tdata_next; +reg m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next; + +reg start_flag_reg = 1'b0, start_flag_next; + +reg busy_reg = 1'b0; + +assign m_axis_cmd_address = m_axis_cmd_address_reg; +assign m_axis_cmd_start = m_axis_cmd_start_reg; +assign m_axis_cmd_read = 1'b0; +assign m_axis_cmd_write = m_axis_cmd_write_reg; +assign m_axis_cmd_write_multiple = 1'b0; +assign m_axis_cmd_stop = m_axis_cmd_stop_reg; +assign m_axis_cmd_valid = m_axis_cmd_valid_reg; + +assign m_axis_data_tdata = m_axis_data_tdata_reg; +assign m_axis_data_tvalid = m_axis_data_tvalid_reg; +assign m_axis_data_tlast = 1'b1; + +assign busy = busy_reg; + +always @* begin + state_next = STATE_IDLE; + + address_next = address_reg; + address_ptr_next = address_ptr_reg; + data_ptr_next = data_ptr_reg; + + cur_address_next = cur_address_reg; + + delay_counter_next = delay_counter_reg; + + m_axis_cmd_address_next = m_axis_cmd_address_reg; + m_axis_cmd_start_next = m_axis_cmd_start_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready); + m_axis_cmd_write_next = m_axis_cmd_write_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready); + m_axis_cmd_stop_next = m_axis_cmd_stop_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready); + m_axis_cmd_valid_next = m_axis_cmd_valid_reg & ~m_axis_cmd_ready; + + m_axis_data_tdata_next = m_axis_data_tdata_reg; + m_axis_data_tvalid_next = m_axis_data_tvalid_reg & ~m_axis_data_tready; + + start_flag_next = start_flag_reg; + + if (m_axis_cmd_valid | m_axis_data_tvalid) begin + // wait for output registers to clear + state_next = state_reg; + end else if (delay_counter_reg != 0) begin + // delay + delay_counter_next = delay_counter_reg - 1; + state_next = state_reg; + end else begin + case (state_reg) + STATE_IDLE: begin + // wait for start signal + if (~start_flag_reg & start) begin + address_next = {AW{1'b0}}; + start_flag_next = 1'b1; + state_next = STATE_RUN; + end else begin + state_next = STATE_IDLE; + end + end + STATE_RUN: begin + // process commands + if (init_data_reg[8] == 1'b1) begin + // write data + m_axis_cmd_write_next = 1'b1; + m_axis_cmd_stop_next = 1'b0; + m_axis_cmd_valid_next = 1'b1; + + m_axis_data_tdata_next = init_data_reg[7:0]; + m_axis_data_tvalid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg[8:7] == 2'b01) begin + // write address + m_axis_cmd_address_next = init_data_reg[6:0]; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg[8:4] == 5'b00001) begin + // delay + delay_counter_next = 32'd1 << (init_data_reg[3:0]+16); + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg == 9'b001000001) begin + // send stop + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_RUN; + end + end + STATE_TABLE_1: begin + // find address table start + if (init_data_reg == 9'b000001000) begin + // address table start + address_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_2; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end + end + STATE_TABLE_2: begin + // find next address + if (init_data_reg[8:7] == 2'b01) begin + // write address command + // store address and move to data table + cur_address_next = init_data_reg[6:0]; + address_ptr_next = address_reg + 1; + address_next = data_ptr_reg; + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'd1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_2; + end + end + STATE_TABLE_3: begin + // process data table with selected address + if (init_data_reg[8] == 1'b1) begin + // write data + m_axis_cmd_write_next = 1'b1; + m_axis_cmd_stop_next = 1'b0; + m_axis_cmd_valid_next = 1'b1; + + m_axis_data_tdata_next = init_data_reg[7:0]; + m_axis_data_tvalid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg[8:7] == 2'b01) begin + // write address + m_axis_cmd_address_next = init_data_reg[6:0]; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000000011) begin + // write current address + m_axis_cmd_address_next = cur_address_reg; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b001000001) begin + // send stop + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'b000001000) begin + // address table start + address_next = address_ptr_reg; + state_next = STATE_TABLE_2; + end else if (init_data_reg == 9'd1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_3; + end + end + endcase + end +end + +always @(posedge clk) begin + state_reg <= state_next; + + // read init_data ROM + init_data_reg <= init_data[address_next]; + + address_reg <= address_next; + address_ptr_reg <= address_ptr_next; + data_ptr_reg <= data_ptr_next; + + cur_address_reg <= cur_address_next; + + delay_counter_reg <= delay_counter_next; + + m_axis_cmd_address_reg <= m_axis_cmd_address_next; + m_axis_cmd_start_reg <= m_axis_cmd_start_next; + m_axis_cmd_write_reg <= m_axis_cmd_write_next; + m_axis_cmd_stop_reg <= m_axis_cmd_stop_next; + m_axis_cmd_valid_reg <= m_axis_cmd_valid_next; + + m_axis_data_tdata_reg <= m_axis_data_tdata_next; + m_axis_data_tvalid_reg <= m_axis_data_tvalid_next; + + start_flag_reg <= start & start_flag_next; + + busy_reg <= (state_reg != STATE_IDLE); + + if (rst) begin + state_reg <= STATE_IDLE; + + init_data_reg <= 9'd0; + + address_reg <= {AW{1'b0}}; + address_ptr_reg <= {AW{1'b0}}; + data_ptr_reg <= {AW{1'b0}}; + + cur_address_reg <= 7'd0; + + delay_counter_reg <= 32'd0; + + m_axis_cmd_valid_reg <= 1'b0; + + m_axis_data_tvalid_reg <= 1'b0; + + start_flag_reg <= 1'b0; + + busy_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/fpga/lib/eth/example/AU250/fpga_10g/rtl/debounce_switch.v b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/debounce_switch.v similarity index 100% rename from fpga/lib/eth/example/AU250/fpga_10g/rtl/debounce_switch.v rename to fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/debounce_switch.v diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v similarity index 100% rename from fpga/lib/eth/example/VCU118/fpga_10g/rtl/eth_xcvr_phy_wrapper.v rename to fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v diff --git a/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v new file mode 100644 index 000000000..eacf0b8e5 --- /dev/null +++ b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v @@ -0,0 +1,3083 @@ +/* + +Copyright (c) 2014-2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA top-level module + */ +module fpga ( + /* + * Clock: 125MHz LVDS + * Reset: Push button, active low + */ + input wire clk_125mhz_p, + input wire clk_125mhz_n, + input wire reset, + + /* + * GPIO + */ + input wire btnu, + input wire btnl, + input wire btnd, + input wire btnr, + input wire btnc, + input wire [3:0] sw, + output wire [7:0] led, + + /* + * I2C for board management + */ + inout wire i2c_scl, + inout wire i2c_sda, + + /* + * Ethernet: QSFP28 + */ + output wire qsfp1_tx1_p, + output wire qsfp1_tx1_n, + input wire qsfp1_rx1_p, + input wire qsfp1_rx1_n, + output wire qsfp1_tx2_p, + output wire qsfp1_tx2_n, + input wire qsfp1_rx2_p, + input wire qsfp1_rx2_n, + output wire qsfp1_tx3_p, + output wire qsfp1_tx3_n, + input wire qsfp1_rx3_p, + input wire qsfp1_rx3_n, + output wire qsfp1_tx4_p, + output wire qsfp1_tx4_n, + input wire qsfp1_rx4_p, + input wire qsfp1_rx4_n, + input wire qsfp1_mgt_refclk_0_p, + input wire qsfp1_mgt_refclk_0_n, + // input wire qsfp1_mgt_refclk_1_p, + // input wire qsfp1_mgt_refclk_1_n, + // output wire qsfp1_recclk_p, + // output wire qsfp1_recclk_n, + output wire qsfp1_modsell, + output wire qsfp1_resetl, + input wire qsfp1_modprsl, + input wire qsfp1_intl, + output wire qsfp1_lpmode, + + output wire qsfp2_tx1_p, + output wire qsfp2_tx1_n, + input wire qsfp2_rx1_p, + input wire qsfp2_rx1_n, + output wire qsfp2_tx2_p, + output wire qsfp2_tx2_n, + input wire qsfp2_rx2_p, + input wire qsfp2_rx2_n, + output wire qsfp2_tx3_p, + output wire qsfp2_tx3_n, + input wire qsfp2_rx3_p, + input wire qsfp2_rx3_n, + output wire qsfp2_tx4_p, + output wire qsfp2_tx4_n, + input wire qsfp2_rx4_p, + input wire qsfp2_rx4_n, + // input wire qsfp2_mgt_refclk_0_p, + // input wire qsfp2_mgt_refclk_0_n, + // input wire qsfp2_mgt_refclk_1_p, + // input wire qsfp2_mgt_refclk_1_n, + // output wire qsfp2_recclk_p, + // output wire qsfp2_recclk_n, + output wire qsfp2_modsell, + output wire qsfp2_resetl, + input wire qsfp2_modprsl, + input wire qsfp2_intl, + output wire qsfp2_lpmode, + + /* + * Ethernet: QSFP28 via HTG 6x QSFP28 FMC+ adapter + */ + output wire [3:0] fmcp_qsfp1_tx_p, + output wire [3:0] fmcp_qsfp1_tx_n, + input wire [3:0] fmcp_qsfp1_rx_p, + input wire [3:0] fmcp_qsfp1_rx_n, + input wire fmcp_qsfp1_mgt_refclk_p, + input wire fmcp_qsfp1_mgt_refclk_n, + output wire fmcp_qsfp1_modsell, + output wire fmcp_qsfp1_resetl, + input wire fmcp_qsfp1_modprsl, + input wire fmcp_qsfp1_intl, + output wire fmcp_qsfp1_lpmode, + + output wire [3:0] fmcp_qsfp2_tx_p, + output wire [3:0] fmcp_qsfp2_tx_n, + input wire [3:0] fmcp_qsfp2_rx_p, + input wire [3:0] fmcp_qsfp2_rx_n, + input wire fmcp_qsfp2_mgt_refclk_p, + input wire fmcp_qsfp2_mgt_refclk_n, + output wire fmcp_qsfp2_modsell, + output wire fmcp_qsfp2_resetl, + input wire fmcp_qsfp2_modprsl, + input wire fmcp_qsfp2_intl, + output wire fmcp_qsfp2_lpmode, + + output wire [3:0] fmcp_qsfp3_tx_p, + output wire [3:0] fmcp_qsfp3_tx_n, + input wire [3:0] fmcp_qsfp3_rx_p, + input wire [3:0] fmcp_qsfp3_rx_n, + input wire fmcp_qsfp3_mgt_refclk_p, + input wire fmcp_qsfp3_mgt_refclk_n, + output wire fmcp_qsfp3_modsell, + output wire fmcp_qsfp3_resetl, + input wire fmcp_qsfp3_modprsl, + input wire fmcp_qsfp3_intl, + output wire fmcp_qsfp3_lpmode, + + output wire [3:0] fmcp_qsfp4_tx_p, + output wire [3:0] fmcp_qsfp4_tx_n, + input wire [3:0] fmcp_qsfp4_rx_p, + input wire [3:0] fmcp_qsfp4_rx_n, + input wire fmcp_qsfp4_mgt_refclk_p, + input wire fmcp_qsfp4_mgt_refclk_n, + output wire fmcp_qsfp4_modsell, + output wire fmcp_qsfp4_resetl, + input wire fmcp_qsfp4_modprsl, + input wire fmcp_qsfp4_intl, + output wire fmcp_qsfp4_lpmode, + + output wire [3:0] fmcp_qsfp5_tx_p, + output wire [3:0] fmcp_qsfp5_tx_n, + input wire [3:0] fmcp_qsfp5_rx_p, + input wire [3:0] fmcp_qsfp5_rx_n, + input wire fmcp_qsfp5_mgt_refclk_p, + input wire fmcp_qsfp5_mgt_refclk_n, + output wire fmcp_qsfp5_modsell, + output wire fmcp_qsfp5_resetl, + input wire fmcp_qsfp5_modprsl, + input wire fmcp_qsfp5_intl, + output wire fmcp_qsfp5_lpmode, + + output wire [3:0] fmcp_qsfp6_tx_p, + output wire [3:0] fmcp_qsfp6_tx_n, + input wire [3:0] fmcp_qsfp6_rx_p, + input wire [3:0] fmcp_qsfp6_rx_n, + input wire fmcp_qsfp6_mgt_refclk_p, + input wire fmcp_qsfp6_mgt_refclk_n, + output wire fmcp_qsfp6_modsell, + output wire fmcp_qsfp6_resetl, + input wire fmcp_qsfp6_modprsl, + input wire fmcp_qsfp6_intl, + output wire fmcp_qsfp6_lpmode, + + output wire fmcp_clk_finc, + output wire fmcp_clk_fdec, + output wire fmcp_clk_rst_n, + input wire fmcp_clk_lol_n, + output wire fmcp_clk_sync_n, + input wire fmcp_clk_intr_n, + + output wire fmcp_hspc_sync_c2m_p, + output wire fmcp_hspc_sync_c2m_n, + + /* + * Ethernet: 1000BASE-T SGMII + */ + input wire phy_sgmii_rx_p, + input wire phy_sgmii_rx_n, + output wire phy_sgmii_tx_p, + output wire phy_sgmii_tx_n, + input wire phy_sgmii_clk_p, + input wire phy_sgmii_clk_n, + output wire phy_reset_n, + input wire phy_int_n, + inout wire phy_mdio, + output wire phy_mdc, + + /* + * UART: 500000 bps, 8N1 + */ + input wire uart_rxd, + output wire uart_txd, + output wire uart_rts, + input wire uart_cts +); + +// Clock and reset + +wire clk_125mhz_ibufg; + +// Internal 125 MHz clock +wire clk_125mhz_mmcm_out; +wire clk_125mhz_int; +wire rst_125mhz_int; + +// Internal 390.625 MHz clock +wire clk_390mhz_int; +wire rst_390mhz_int; + +wire mmcm_rst = reset; +wire mmcm_locked; +wire mmcm_clkfb; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_125mhz_ibufg_inst ( + .O (clk_125mhz_ibufg), + .I (clk_125mhz_p), + .IB (clk_125mhz_n) +); + +// MMCM instance +// 125 MHz in, 125 MHz out +// PFD range: 10 MHz to 500 MHz +// VCO range: 800 MHz to 1600 MHz +// M = 8, D = 1 sets Fvco = 1000 MHz (in range) +// Divide by 8 to get output frequency of 125 MHz +MMCME3_BASE #( + .BANDWIDTH("OPTIMIZED"), + .CLKOUT0_DIVIDE_F(8), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + .CLKFBOUT_MULT_F(8), + .CLKFBOUT_PHASE(0), + .DIVCLK_DIVIDE(1), + .REF_JITTER1(0.010), + .CLKIN1_PERIOD(8.0), + .STARTUP_WAIT("FALSE"), + .CLKOUT4_CASCADE("FALSE") +) +clk_mmcm_inst ( + .CLKIN1(clk_125mhz_ibufg), + .CLKFBIN(mmcm_clkfb), + .RST(mmcm_rst), + .PWRDWN(1'b0), + .CLKOUT0(clk_125mhz_mmcm_out), + .CLKOUT0B(), + .CLKOUT1(), + .CLKOUT1B(), + .CLKOUT2(), + .CLKOUT2B(), + .CLKOUT3(), + .CLKOUT3B(), + .CLKOUT4(), + .CLKOUT5(), + .CLKOUT6(), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + .LOCKED(mmcm_locked) +); + +BUFG +clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int) +); + +sync_reset #( + .N(4) +) +sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .out(rst_125mhz_int) +); + +// GPIO +wire btnu_int; +wire btnl_int; +wire btnd_int; +wire btnr_int; +wire btnc_int; +wire [3:0] sw_int; + +debounce_switch #( + .WIDTH(9), + .N(4), + .RATE(156000) +) +debounce_switch_inst ( + .clk(clk_390mhz_int), + .rst(rst_390mhz_int), + .in({btnu, + btnl, + btnd, + btnr, + btnc, + sw}), + .out({btnu_int, + btnl_int, + btnd_int, + btnr_int, + btnc_int, + sw_int}) +); + +wire uart_rxd_int; +wire uart_cts_int; + +sync_signal #( + .WIDTH(2), + .N(2) +) +sync_signal_inst ( + .clk(clk_390mhz_int), + .in({uart_rxd, uart_cts}), + .out({uart_rxd_int, uart_cts_int}) +); + +wire i2c_scl_i; +wire i2c_scl_o; +wire i2c_scl_t; +wire i2c_sda_i; +wire i2c_sda_o; +wire i2c_sda_t; + +assign i2c_scl_i = i2c_scl; +assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o; +assign i2c_sda_i = i2c_sda; +assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o; + +// Si5341 init +wire [6:0] si5341_i2c_cmd_address; +wire si5341_i2c_cmd_start; +wire si5341_i2c_cmd_read; +wire si5341_i2c_cmd_write; +wire si5341_i2c_cmd_write_multiple; +wire si5341_i2c_cmd_stop; +wire si5341_i2c_cmd_valid; +wire si5341_i2c_cmd_ready; + +wire [7:0] si5341_i2c_data_tdata; +wire si5341_i2c_data_tvalid; +wire si5341_i2c_data_tready; +wire si5341_i2c_data_tlast; + +wire si5341_i2c_busy; + +i2c_master +si5341_i2c_master_inst ( + .clk(clk_125mhz_int), + .rst(rst_125mhz_int), + .s_axis_cmd_address(si5341_i2c_cmd_address), + .s_axis_cmd_start(si5341_i2c_cmd_start), + .s_axis_cmd_read(si5341_i2c_cmd_read), + .s_axis_cmd_write(si5341_i2c_cmd_write), + .s_axis_cmd_write_multiple(si5341_i2c_cmd_write_multiple), + .s_axis_cmd_stop(si5341_i2c_cmd_stop), + .s_axis_cmd_valid(si5341_i2c_cmd_valid), + .s_axis_cmd_ready(si5341_i2c_cmd_ready), + .s_axis_data_tdata(si5341_i2c_data_tdata), + .s_axis_data_tvalid(si5341_i2c_data_tvalid), + .s_axis_data_tready(si5341_i2c_data_tready), + .s_axis_data_tlast(si5341_i2c_data_tlast), + .m_axis_data_tdata(), + .m_axis_data_tvalid(), + .m_axis_data_tready(1'b1), + .m_axis_data_tlast(), + .scl_i(i2c_scl_i), + .scl_o(i2c_scl_o), + .scl_t(i2c_scl_t), + .sda_i(i2c_sda_i), + .sda_o(i2c_sda_o), + .sda_t(i2c_sda_t), + .busy(), + .bus_control(), + .bus_active(), + .missed_ack(), + .prescale(312), + .stop_on_idle(1) +); + +si5341_i2c_init +si5341_i2c_init_inst ( + .clk(clk_125mhz_int), + .rst(rst_125mhz_int), + .m_axis_cmd_address(si5341_i2c_cmd_address), + .m_axis_cmd_start(si5341_i2c_cmd_start), + .m_axis_cmd_read(si5341_i2c_cmd_read), + .m_axis_cmd_write(si5341_i2c_cmd_write), + .m_axis_cmd_write_multiple(si5341_i2c_cmd_write_multiple), + .m_axis_cmd_stop(si5341_i2c_cmd_stop), + .m_axis_cmd_valid(si5341_i2c_cmd_valid), + .m_axis_cmd_ready(si5341_i2c_cmd_ready), + .m_axis_data_tdata(si5341_i2c_data_tdata), + .m_axis_data_tvalid(si5341_i2c_data_tvalid), + .m_axis_data_tready(si5341_i2c_data_tready), + .m_axis_data_tlast(si5341_i2c_data_tlast), + .busy(si5341_i2c_busy), + .start(1'b1) +); + +assign fmcp_clk_finc = 1'b0; +assign fmcp_clk_fdec = 1'b0; +assign fmcp_clk_rst_n = !reset; +assign fmcp_clk_sync_n = 1'b1; + +// XGMII 10G PHY +wire fmcp_qsfp_reset = rst_125mhz_int || si5341_i2c_busy || !fmcp_clk_lol_n; + +// QSFP1 +assign qsfp1_modsell = 1'b0; +assign qsfp1_resetl = 1'b1; +assign qsfp1_lpmode = 1'b0; + +wire qsfp1_tx_clk_1_int; +wire qsfp1_tx_rst_1_int; +wire [63:0] qsfp1_txd_1_int; +wire [7:0] qsfp1_txc_1_int; +wire qsfp1_rx_clk_1_int; +wire qsfp1_rx_rst_1_int; +wire [63:0] qsfp1_rxd_1_int; +wire [7:0] qsfp1_rxc_1_int; +wire qsfp1_tx_clk_2_int; +wire qsfp1_tx_rst_2_int; +wire [63:0] qsfp1_txd_2_int; +wire [7:0] qsfp1_txc_2_int; +wire qsfp1_rx_clk_2_int; +wire qsfp1_rx_rst_2_int; +wire [63:0] qsfp1_rxd_2_int; +wire [7:0] qsfp1_rxc_2_int; +wire qsfp1_tx_clk_3_int; +wire qsfp1_tx_rst_3_int; +wire [63:0] qsfp1_txd_3_int; +wire [7:0] qsfp1_txc_3_int; +wire qsfp1_rx_clk_3_int; +wire qsfp1_rx_rst_3_int; +wire [63:0] qsfp1_rxd_3_int; +wire [7:0] qsfp1_rxc_3_int; +wire qsfp1_tx_clk_4_int; +wire qsfp1_tx_rst_4_int; +wire [63:0] qsfp1_txd_4_int; +wire [7:0] qsfp1_txc_4_int; +wire qsfp1_rx_clk_4_int; +wire qsfp1_rx_rst_4_int; +wire [63:0] qsfp1_rxd_4_int; +wire [7:0] qsfp1_rxc_4_int; + +assign clk_390mhz_int = qsfp1_tx_clk_1_int; +assign rst_390mhz_int = qsfp1_tx_rst_1_int; + +wire qsfp1_rx_block_lock_1; +wire qsfp1_rx_block_lock_2; +wire qsfp1_rx_block_lock_3; +wire qsfp1_rx_block_lock_4; + +wire qsfp1_gtpowergood; + +wire qsfp1_mgt_refclk; +wire qsfp1_mgt_refclk_int; +wire qsfp1_mgt_refclk_bufg; + +IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_0_inst ( + .I (qsfp1_mgt_refclk_0_p), + .IB (qsfp1_mgt_refclk_0_n), + .CEB (1'b0), + .O (qsfp1_mgt_refclk), + .ODIV2 (qsfp1_mgt_refclk_int) +); + +BUFG_GT bufg_gt_qsfp1_mgt_refclk_inst ( + .CE (qsfp1_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (qsfp1_mgt_refclk_int), + .O (qsfp1_mgt_refclk_bufg) +); + +// forward MGT ref clock to PLL on FMC+ board +OBUFDS obufds_fmc_refclk_inst ( + .I(qsfp1_mgt_refclk_bufg), + .O(fmcp_hspc_sync_c2m_p), + .OB(fmcp_hspc_sync_c2m_n) +); + +wire qsfp1_qpll0lock; +wire qsfp1_qpll0outclk; +wire qsfp1_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) +) +qsfp1_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(rst_125mhz_int), + + // Common + .xcvr_gtpowergood_out(qsfp1_gtpowergood), + + // PLL out + .xcvr_gtrefclk00_in(qsfp1_mgt_refclk), + .xcvr_qpll0lock_out(qsfp1_qpll0lock), + .xcvr_qpll0outclk_out(qsfp1_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp1_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp1_tx1_p), + .xcvr_txn(qsfp1_tx1_n), + .xcvr_rxp(qsfp1_rx1_p), + .xcvr_rxn(qsfp1_rx1_n), + + // PHY connections + .phy_tx_clk(qsfp1_tx_clk_1_int), + .phy_tx_rst(qsfp1_tx_rst_1_int), + .phy_xgmii_txd(qsfp1_txd_1_int), + .phy_xgmii_txc(qsfp1_txc_1_int), + .phy_rx_clk(qsfp1_rx_clk_1_int), + .phy_rx_rst(qsfp1_rx_rst_1_int), + .phy_xgmii_rxd(qsfp1_rxd_1_int), + .phy_xgmii_rxc(qsfp1_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp1_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) +) +qsfp1_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(rst_125mhz_int), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp1_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp1_tx2_p), + .xcvr_txn(qsfp1_tx2_n), + .xcvr_rxp(qsfp1_rx2_p), + .xcvr_rxn(qsfp1_rx2_n), + + // PHY connections + .phy_tx_clk(qsfp1_tx_clk_2_int), + .phy_tx_rst(qsfp1_tx_rst_2_int), + .phy_xgmii_txd(qsfp1_txd_2_int), + .phy_xgmii_txc(qsfp1_txc_2_int), + .phy_rx_clk(qsfp1_rx_clk_2_int), + .phy_rx_rst(qsfp1_rx_rst_2_int), + .phy_xgmii_rxd(qsfp1_rxd_2_int), + .phy_xgmii_rxc(qsfp1_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp1_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) +) +qsfp1_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(rst_125mhz_int), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp1_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp1_tx3_p), + .xcvr_txn(qsfp1_tx3_n), + .xcvr_rxp(qsfp1_rx3_p), + .xcvr_rxn(qsfp1_rx3_n), + + // PHY connections + .phy_tx_clk(qsfp1_tx_clk_3_int), + .phy_tx_rst(qsfp1_tx_rst_3_int), + .phy_xgmii_txd(qsfp1_txd_3_int), + .phy_xgmii_txc(qsfp1_txc_3_int), + .phy_rx_clk(qsfp1_rx_clk_3_int), + .phy_rx_rst(qsfp1_rx_rst_3_int), + .phy_xgmii_rxd(qsfp1_rxd_3_int), + .phy_xgmii_rxc(qsfp1_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp1_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) +) +qsfp1_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(rst_125mhz_int), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp1_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp1_tx4_p), + .xcvr_txn(qsfp1_tx4_n), + .xcvr_rxp(qsfp1_rx4_p), + .xcvr_rxn(qsfp1_rx4_n), + + // PHY connections + .phy_tx_clk(qsfp1_tx_clk_4_int), + .phy_tx_rst(qsfp1_tx_rst_4_int), + .phy_xgmii_txd(qsfp1_txd_4_int), + .phy_xgmii_txc(qsfp1_txc_4_int), + .phy_rx_clk(qsfp1_rx_clk_4_int), + .phy_rx_rst(qsfp1_rx_rst_4_int), + .phy_xgmii_rxd(qsfp1_rxd_4_int), + .phy_xgmii_rxc(qsfp1_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp1_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// QSFP2 +assign qsfp2_modsell = 1'b0; +assign qsfp2_resetl = 1'b1; +assign qsfp2_lpmode = 1'b0; + +wire qsfp2_tx_clk_1_int; +wire qsfp2_tx_rst_1_int; +wire [63:0] qsfp2_txd_1_int; +wire [7:0] qsfp2_txc_1_int; +wire qsfp2_rx_clk_1_int; +wire qsfp2_rx_rst_1_int; +wire [63:0] qsfp2_rxd_1_int; +wire [7:0] qsfp2_rxc_1_int; +wire qsfp2_tx_clk_2_int; +wire qsfp2_tx_rst_2_int; +wire [63:0] qsfp2_txd_2_int; +wire [7:0] qsfp2_txc_2_int; +wire qsfp2_rx_clk_2_int; +wire qsfp2_rx_rst_2_int; +wire [63:0] qsfp2_rxd_2_int; +wire [7:0] qsfp2_rxc_2_int; +wire qsfp2_tx_clk_3_int; +wire qsfp2_tx_rst_3_int; +wire [63:0] qsfp2_txd_3_int; +wire [7:0] qsfp2_txc_3_int; +wire qsfp2_rx_clk_3_int; +wire qsfp2_rx_rst_3_int; +wire [63:0] qsfp2_rxd_3_int; +wire [7:0] qsfp2_rxc_3_int; +wire qsfp2_tx_clk_4_int; +wire qsfp2_tx_rst_4_int; +wire [63:0] qsfp2_txd_4_int; +wire [7:0] qsfp2_txc_4_int; +wire qsfp2_rx_clk_4_int; +wire qsfp2_rx_rst_4_int; +wire [63:0] qsfp2_rxd_4_int; +wire [7:0] qsfp2_rxc_4_int; + +wire qsfp2_rx_block_lock_1; +wire qsfp2_rx_block_lock_2; +wire qsfp2_rx_block_lock_3; +wire qsfp2_rx_block_lock_4; + +wire qsfp2_qpll0lock; +wire qsfp2_qpll0outclk; +wire qsfp2_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) +) +qsfp2_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(rst_125mhz_int), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(qsfp1_mgt_refclk), + .xcvr_qpll0lock_out(qsfp2_qpll0lock), + .xcvr_qpll0outclk_out(qsfp2_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp2_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp2_tx1_p), + .xcvr_txn(qsfp2_tx1_n), + .xcvr_rxp(qsfp2_rx1_p), + .xcvr_rxn(qsfp2_rx1_n), + + // PHY connections + .phy_tx_clk(qsfp2_tx_clk_1_int), + .phy_tx_rst(qsfp2_tx_rst_1_int), + .phy_xgmii_txd(qsfp2_txd_1_int), + .phy_xgmii_txc(qsfp2_txc_1_int), + .phy_rx_clk(qsfp2_rx_clk_1_int), + .phy_rx_rst(qsfp2_rx_rst_1_int), + .phy_xgmii_rxd(qsfp2_rxd_1_int), + .phy_xgmii_rxc(qsfp2_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp2_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) +) +qsfp2_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(rst_125mhz_int), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp2_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp2_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp2_tx2_p), + .xcvr_txn(qsfp2_tx2_n), + .xcvr_rxp(qsfp2_rx2_p), + .xcvr_rxn(qsfp2_rx2_n), + + // PHY connections + .phy_tx_clk(qsfp2_tx_clk_2_int), + .phy_tx_rst(qsfp2_tx_rst_2_int), + .phy_xgmii_txd(qsfp2_txd_2_int), + .phy_xgmii_txc(qsfp2_txc_2_int), + .phy_rx_clk(qsfp2_rx_clk_2_int), + .phy_rx_rst(qsfp2_rx_rst_2_int), + .phy_xgmii_rxd(qsfp2_rxd_2_int), + .phy_xgmii_rxc(qsfp2_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp2_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) +) +qsfp2_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(rst_125mhz_int), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp2_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp2_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp2_tx3_p), + .xcvr_txn(qsfp2_tx3_n), + .xcvr_rxp(qsfp2_rx3_p), + .xcvr_rxn(qsfp2_rx3_n), + + // PHY connections + .phy_tx_clk(qsfp2_tx_clk_3_int), + .phy_tx_rst(qsfp2_tx_rst_3_int), + .phy_xgmii_txd(qsfp2_txd_3_int), + .phy_xgmii_txc(qsfp2_txc_3_int), + .phy_rx_clk(qsfp2_rx_clk_3_int), + .phy_rx_rst(qsfp2_rx_rst_3_int), + .phy_xgmii_rxd(qsfp2_rxd_3_int), + .phy_xgmii_rxc(qsfp2_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp2_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) +) +qsfp2_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(rst_125mhz_int), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp2_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp2_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp2_tx4_p), + .xcvr_txn(qsfp2_tx4_n), + .xcvr_rxp(qsfp2_rx4_p), + .xcvr_rxn(qsfp2_rx4_n), + + // PHY connections + .phy_tx_clk(qsfp2_tx_clk_4_int), + .phy_tx_rst(qsfp2_tx_rst_4_int), + .phy_xgmii_txd(qsfp2_txd_4_int), + .phy_xgmii_txc(qsfp2_txc_4_int), + .phy_rx_clk(qsfp2_rx_clk_4_int), + .phy_rx_rst(qsfp2_rx_rst_4_int), + .phy_xgmii_rxd(qsfp2_rxd_4_int), + .phy_xgmii_rxc(qsfp2_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp2_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// FMC QSFP1 +assign fmcp_qsfp1_modsell = 1'b1; +assign fmcp_qsfp1_resetl = 1'b1; +assign fmcp_qsfp1_lpmode = 1'b0; + +wire fmcp_qsfp1_tx_clk_1_int; +wire fmcp_qsfp1_tx_rst_1_int; +wire [63:0] fmcp_qsfp1_txd_1_int; +wire [7:0] fmcp_qsfp1_txc_1_int; +wire fmcp_qsfp1_rx_clk_1_int; +wire fmcp_qsfp1_rx_rst_1_int; +wire [63:0] fmcp_qsfp1_rxd_1_int; +wire [7:0] fmcp_qsfp1_rxc_1_int; +wire fmcp_qsfp1_tx_clk_2_int; +wire fmcp_qsfp1_tx_rst_2_int; +wire [63:0] fmcp_qsfp1_txd_2_int; +wire [7:0] fmcp_qsfp1_txc_2_int; +wire fmcp_qsfp1_rx_clk_2_int; +wire fmcp_qsfp1_rx_rst_2_int; +wire [63:0] fmcp_qsfp1_rxd_2_int; +wire [7:0] fmcp_qsfp1_rxc_2_int; +wire fmcp_qsfp1_tx_clk_3_int; +wire fmcp_qsfp1_tx_rst_3_int; +wire [63:0] fmcp_qsfp1_txd_3_int; +wire [7:0] fmcp_qsfp1_txc_3_int; +wire fmcp_qsfp1_rx_clk_3_int; +wire fmcp_qsfp1_rx_rst_3_int; +wire [63:0] fmcp_qsfp1_rxd_3_int; +wire [7:0] fmcp_qsfp1_rxc_3_int; +wire fmcp_qsfp1_tx_clk_4_int; +wire fmcp_qsfp1_tx_rst_4_int; +wire [63:0] fmcp_qsfp1_txd_4_int; +wire [7:0] fmcp_qsfp1_txc_4_int; +wire fmcp_qsfp1_rx_clk_4_int; +wire fmcp_qsfp1_rx_rst_4_int; +wire [63:0] fmcp_qsfp1_rxd_4_int; +wire [7:0] fmcp_qsfp1_rxc_4_int; + +wire fmcp_qsfp1_rx_block_lock_1; +wire fmcp_qsfp1_rx_block_lock_2; +wire fmcp_qsfp1_rx_block_lock_3; +wire fmcp_qsfp1_rx_block_lock_4; + +wire fmcp_qsfp1_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_fmcp_qsfp1_mgt_refclk_inst ( + .I (fmcp_qsfp1_mgt_refclk_p), + .IB (fmcp_qsfp1_mgt_refclk_n), + .CEB (1'b0), + .O (fmcp_qsfp1_mgt_refclk), + .ODIV2 () +); + +wire fmcp_qsfp1_qpll0lock; +wire fmcp_qsfp1_qpll0outclk; +wire fmcp_qsfp1_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +fmcp_qsfp1_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(fmcp_qsfp1_mgt_refclk), + .xcvr_qpll0lock_out(fmcp_qsfp1_qpll0lock), + .xcvr_qpll0outclk_out(fmcp_qsfp1_qpll0outclk), + .xcvr_qpll0outrefclk_out(fmcp_qsfp1_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(fmcp_qsfp1_tx_p[0]), + .xcvr_txn(fmcp_qsfp1_tx_n[0]), + .xcvr_rxp(fmcp_qsfp1_rx_p[0]), + .xcvr_rxn(fmcp_qsfp1_rx_n[0]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp1_tx_clk_1_int), + .phy_tx_rst(fmcp_qsfp1_tx_rst_1_int), + .phy_xgmii_txd(fmcp_qsfp1_txd_1_int), + .phy_xgmii_txc(fmcp_qsfp1_txc_1_int), + .phy_rx_clk(fmcp_qsfp1_rx_clk_1_int), + .phy_rx_rst(fmcp_qsfp1_rx_rst_1_int), + .phy_xgmii_rxd(fmcp_qsfp1_rxd_1_int), + .phy_xgmii_rxc(fmcp_qsfp1_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmcp_qsfp1_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmcp_qsfp1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmcp_qsfp1_qpll0outclk), + .xcvr_qpll0refclk_in(fmcp_qsfp1_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmcp_qsfp1_tx_p[1]), + .xcvr_txn(fmcp_qsfp1_tx_n[1]), + .xcvr_rxp(fmcp_qsfp1_rx_p[1]), + .xcvr_rxn(fmcp_qsfp1_rx_n[1]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp1_tx_clk_2_int), + .phy_tx_rst(fmcp_qsfp1_tx_rst_2_int), + .phy_xgmii_txd(fmcp_qsfp1_txd_2_int), + .phy_xgmii_txc(fmcp_qsfp1_txc_2_int), + .phy_rx_clk(fmcp_qsfp1_rx_clk_2_int), + .phy_rx_rst(fmcp_qsfp1_rx_rst_2_int), + .phy_xgmii_rxd(fmcp_qsfp1_rxd_2_int), + .phy_xgmii_rxc(fmcp_qsfp1_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmcp_qsfp1_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmcp_qsfp1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmcp_qsfp1_qpll0outclk), + .xcvr_qpll0refclk_in(fmcp_qsfp1_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmcp_qsfp1_tx_p[2]), + .xcvr_txn(fmcp_qsfp1_tx_n[2]), + .xcvr_rxp(fmcp_qsfp1_rx_p[2]), + .xcvr_rxn(fmcp_qsfp1_rx_n[2]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp1_tx_clk_3_int), + .phy_tx_rst(fmcp_qsfp1_tx_rst_3_int), + .phy_xgmii_txd(fmcp_qsfp1_txd_3_int), + .phy_xgmii_txc(fmcp_qsfp1_txc_3_int), + .phy_rx_clk(fmcp_qsfp1_rx_clk_3_int), + .phy_rx_rst(fmcp_qsfp1_rx_rst_3_int), + .phy_xgmii_rxd(fmcp_qsfp1_rxd_3_int), + .phy_xgmii_rxc(fmcp_qsfp1_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmcp_qsfp1_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmcp_qsfp1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmcp_qsfp1_qpll0outclk), + .xcvr_qpll0refclk_in(fmcp_qsfp1_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmcp_qsfp1_tx_p[3]), + .xcvr_txn(fmcp_qsfp1_tx_n[3]), + .xcvr_rxp(fmcp_qsfp1_rx_p[3]), + .xcvr_rxn(fmcp_qsfp1_rx_n[3]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp1_tx_clk_4_int), + .phy_tx_rst(fmcp_qsfp1_tx_rst_4_int), + .phy_xgmii_txd(fmcp_qsfp1_txd_4_int), + .phy_xgmii_txc(fmcp_qsfp1_txc_4_int), + .phy_rx_clk(fmcp_qsfp1_rx_clk_4_int), + .phy_rx_rst(fmcp_qsfp1_rx_rst_4_int), + .phy_xgmii_rxd(fmcp_qsfp1_rxd_4_int), + .phy_xgmii_rxc(fmcp_qsfp1_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// FMC QSFP2 +assign fmcp_qsfp2_modsell = 1'b1; +assign fmcp_qsfp2_resetl = 1'b1; +assign fmcp_qsfp2_lpmode = 1'b0; + +wire fmcp_qsfp2_tx_clk_1_int; +wire fmcp_qsfp2_tx_rst_1_int; +wire [63:0] fmcp_qsfp2_txd_1_int; +wire [7:0] fmcp_qsfp2_txc_1_int; +wire fmcp_qsfp2_rx_clk_1_int; +wire fmcp_qsfp2_rx_rst_1_int; +wire [63:0] fmcp_qsfp2_rxd_1_int; +wire [7:0] fmcp_qsfp2_rxc_1_int; +wire fmcp_qsfp2_tx_clk_2_int; +wire fmcp_qsfp2_tx_rst_2_int; +wire [63:0] fmcp_qsfp2_txd_2_int; +wire [7:0] fmcp_qsfp2_txc_2_int; +wire fmcp_qsfp2_rx_clk_2_int; +wire fmcp_qsfp2_rx_rst_2_int; +wire [63:0] fmcp_qsfp2_rxd_2_int; +wire [7:0] fmcp_qsfp2_rxc_2_int; +wire fmcp_qsfp2_tx_clk_3_int; +wire fmcp_qsfp2_tx_rst_3_int; +wire [63:0] fmcp_qsfp2_txd_3_int; +wire [7:0] fmcp_qsfp2_txc_3_int; +wire fmcp_qsfp2_rx_clk_3_int; +wire fmcp_qsfp2_rx_rst_3_int; +wire [63:0] fmcp_qsfp2_rxd_3_int; +wire [7:0] fmcp_qsfp2_rxc_3_int; +wire fmcp_qsfp2_tx_clk_4_int; +wire fmcp_qsfp2_tx_rst_4_int; +wire [63:0] fmcp_qsfp2_txd_4_int; +wire [7:0] fmcp_qsfp2_txc_4_int; +wire fmcp_qsfp2_rx_clk_4_int; +wire fmcp_qsfp2_rx_rst_4_int; +wire [63:0] fmcp_qsfp2_rxd_4_int; +wire [7:0] fmcp_qsfp2_rxc_4_int; + +wire fmcp_qsfp2_rx_block_lock_1; +wire fmcp_qsfp2_rx_block_lock_2; +wire fmcp_qsfp2_rx_block_lock_3; +wire fmcp_qsfp2_rx_block_lock_4; + +wire fmcp_qsfp2_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_fmcp_qsfp2_mgt_refclk_inst ( + .I (fmcp_qsfp2_mgt_refclk_p), + .IB (fmcp_qsfp2_mgt_refclk_n), + .CEB (1'b0), + .O (fmcp_qsfp2_mgt_refclk), + .ODIV2 () +); + +wire fmcp_qsfp2_qpll0lock; +wire fmcp_qsfp2_qpll0outclk; +wire fmcp_qsfp2_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +fmcp_qsfp2_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(fmcp_qsfp2_mgt_refclk), + .xcvr_qpll0lock_out(fmcp_qsfp2_qpll0lock), + .xcvr_qpll0outclk_out(fmcp_qsfp2_qpll0outclk), + .xcvr_qpll0outrefclk_out(fmcp_qsfp2_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(fmcp_qsfp2_tx_p[0]), + .xcvr_txn(fmcp_qsfp2_tx_n[0]), + .xcvr_rxp(fmcp_qsfp2_rx_p[0]), + .xcvr_rxn(fmcp_qsfp2_rx_n[0]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp2_tx_clk_1_int), + .phy_tx_rst(fmcp_qsfp2_tx_rst_1_int), + .phy_xgmii_txd(fmcp_qsfp2_txd_1_int), + .phy_xgmii_txc(fmcp_qsfp2_txc_1_int), + .phy_rx_clk(fmcp_qsfp2_rx_clk_1_int), + .phy_rx_rst(fmcp_qsfp2_rx_rst_1_int), + .phy_xgmii_rxd(fmcp_qsfp2_rxd_1_int), + .phy_xgmii_rxc(fmcp_qsfp2_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmcp_qsfp2_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmcp_qsfp2_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmcp_qsfp2_qpll0outclk), + .xcvr_qpll0refclk_in(fmcp_qsfp2_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmcp_qsfp2_tx_p[1]), + .xcvr_txn(fmcp_qsfp2_tx_n[1]), + .xcvr_rxp(fmcp_qsfp2_rx_p[1]), + .xcvr_rxn(fmcp_qsfp2_rx_n[1]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp2_tx_clk_2_int), + .phy_tx_rst(fmcp_qsfp2_tx_rst_2_int), + .phy_xgmii_txd(fmcp_qsfp2_txd_2_int), + .phy_xgmii_txc(fmcp_qsfp2_txc_2_int), + .phy_rx_clk(fmcp_qsfp2_rx_clk_2_int), + .phy_rx_rst(fmcp_qsfp2_rx_rst_2_int), + .phy_xgmii_rxd(fmcp_qsfp2_rxd_2_int), + .phy_xgmii_rxc(fmcp_qsfp2_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmcp_qsfp2_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmcp_qsfp2_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmcp_qsfp2_qpll0outclk), + .xcvr_qpll0refclk_in(fmcp_qsfp2_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmcp_qsfp2_tx_p[2]), + .xcvr_txn(fmcp_qsfp2_tx_n[2]), + .xcvr_rxp(fmcp_qsfp2_rx_p[2]), + .xcvr_rxn(fmcp_qsfp2_rx_n[2]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp2_tx_clk_3_int), + .phy_tx_rst(fmcp_qsfp2_tx_rst_3_int), + .phy_xgmii_txd(fmcp_qsfp2_txd_3_int), + .phy_xgmii_txc(fmcp_qsfp2_txc_3_int), + .phy_rx_clk(fmcp_qsfp2_rx_clk_3_int), + .phy_rx_rst(fmcp_qsfp2_rx_rst_3_int), + .phy_xgmii_rxd(fmcp_qsfp2_rxd_3_int), + .phy_xgmii_rxc(fmcp_qsfp2_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmcp_qsfp2_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmcp_qsfp2_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmcp_qsfp2_qpll0outclk), + .xcvr_qpll0refclk_in(fmcp_qsfp2_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmcp_qsfp2_tx_p[3]), + .xcvr_txn(fmcp_qsfp2_tx_n[3]), + .xcvr_rxp(fmcp_qsfp2_rx_p[3]), + .xcvr_rxn(fmcp_qsfp2_rx_n[3]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp2_tx_clk_4_int), + .phy_tx_rst(fmcp_qsfp2_tx_rst_4_int), + .phy_xgmii_txd(fmcp_qsfp2_txd_4_int), + .phy_xgmii_txc(fmcp_qsfp2_txc_4_int), + .phy_rx_clk(fmcp_qsfp2_rx_clk_4_int), + .phy_rx_rst(fmcp_qsfp2_rx_rst_4_int), + .phy_xgmii_rxd(fmcp_qsfp2_rxd_4_int), + .phy_xgmii_rxc(fmcp_qsfp2_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// FMC QSFP3 +assign fmcp_qsfp3_modsell = 1'b1; +assign fmcp_qsfp3_resetl = 1'b1; +assign fmcp_qsfp3_lpmode = 1'b0; + +wire fmcp_qsfp3_tx_clk_1_int; +wire fmcp_qsfp3_tx_rst_1_int; +wire [63:0] fmcp_qsfp3_txd_1_int; +wire [7:0] fmcp_qsfp3_txc_1_int; +wire fmcp_qsfp3_rx_clk_1_int; +wire fmcp_qsfp3_rx_rst_1_int; +wire [63:0] fmcp_qsfp3_rxd_1_int; +wire [7:0] fmcp_qsfp3_rxc_1_int; +wire fmcp_qsfp3_tx_clk_2_int; +wire fmcp_qsfp3_tx_rst_2_int; +wire [63:0] fmcp_qsfp3_txd_2_int; +wire [7:0] fmcp_qsfp3_txc_2_int; +wire fmcp_qsfp3_rx_clk_2_int; +wire fmcp_qsfp3_rx_rst_2_int; +wire [63:0] fmcp_qsfp3_rxd_2_int; +wire [7:0] fmcp_qsfp3_rxc_2_int; +wire fmcp_qsfp3_tx_clk_3_int; +wire fmcp_qsfp3_tx_rst_3_int; +wire [63:0] fmcp_qsfp3_txd_3_int; +wire [7:0] fmcp_qsfp3_txc_3_int; +wire fmcp_qsfp3_rx_clk_3_int; +wire fmcp_qsfp3_rx_rst_3_int; +wire [63:0] fmcp_qsfp3_rxd_3_int; +wire [7:0] fmcp_qsfp3_rxc_3_int; +wire fmcp_qsfp3_tx_clk_4_int; +wire fmcp_qsfp3_tx_rst_4_int; +wire [63:0] fmcp_qsfp3_txd_4_int; +wire [7:0] fmcp_qsfp3_txc_4_int; +wire fmcp_qsfp3_rx_clk_4_int; +wire fmcp_qsfp3_rx_rst_4_int; +wire [63:0] fmcp_qsfp3_rxd_4_int; +wire [7:0] fmcp_qsfp3_rxc_4_int; + +wire fmcp_qsfp3_rx_block_lock_1; +wire fmcp_qsfp3_rx_block_lock_2; +wire fmcp_qsfp3_rx_block_lock_3; +wire fmcp_qsfp3_rx_block_lock_4; + +wire fmcp_qsfp3_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_fmcp_qsfp3_mgt_refclk_inst ( + .I (fmcp_qsfp3_mgt_refclk_p), + .IB (fmcp_qsfp3_mgt_refclk_n), + .CEB (1'b0), + .O (fmcp_qsfp3_mgt_refclk), + .ODIV2 () +); + +wire fmcp_qsfp3_qpll0lock; +wire fmcp_qsfp3_qpll0outclk; +wire fmcp_qsfp3_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +fmcp_qsfp3_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(fmcp_qsfp3_mgt_refclk), + .xcvr_qpll0lock_out(fmcp_qsfp3_qpll0lock), + .xcvr_qpll0outclk_out(fmcp_qsfp3_qpll0outclk), + .xcvr_qpll0outrefclk_out(fmcp_qsfp3_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(fmcp_qsfp3_tx_p[0]), + .xcvr_txn(fmcp_qsfp3_tx_n[0]), + .xcvr_rxp(fmcp_qsfp3_rx_p[0]), + .xcvr_rxn(fmcp_qsfp3_rx_n[0]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp3_tx_clk_1_int), + .phy_tx_rst(fmcp_qsfp3_tx_rst_1_int), + .phy_xgmii_txd(fmcp_qsfp3_txd_1_int), + .phy_xgmii_txc(fmcp_qsfp3_txc_1_int), + .phy_rx_clk(fmcp_qsfp3_rx_clk_1_int), + .phy_rx_rst(fmcp_qsfp3_rx_rst_1_int), + .phy_xgmii_rxd(fmcp_qsfp3_rxd_1_int), + .phy_xgmii_rxc(fmcp_qsfp3_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmcp_qsfp3_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmcp_qsfp3_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmcp_qsfp3_qpll0outclk), + .xcvr_qpll0refclk_in(fmcp_qsfp3_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmcp_qsfp3_tx_p[1]), + .xcvr_txn(fmcp_qsfp3_tx_n[1]), + .xcvr_rxp(fmcp_qsfp3_rx_p[1]), + .xcvr_rxn(fmcp_qsfp3_rx_n[1]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp3_tx_clk_2_int), + .phy_tx_rst(fmcp_qsfp3_tx_rst_2_int), + .phy_xgmii_txd(fmcp_qsfp3_txd_2_int), + .phy_xgmii_txc(fmcp_qsfp3_txc_2_int), + .phy_rx_clk(fmcp_qsfp3_rx_clk_2_int), + .phy_rx_rst(fmcp_qsfp3_rx_rst_2_int), + .phy_xgmii_rxd(fmcp_qsfp3_rxd_2_int), + .phy_xgmii_rxc(fmcp_qsfp3_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmcp_qsfp3_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmcp_qsfp3_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmcp_qsfp3_qpll0outclk), + .xcvr_qpll0refclk_in(fmcp_qsfp3_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmcp_qsfp3_tx_p[2]), + .xcvr_txn(fmcp_qsfp3_tx_n[2]), + .xcvr_rxp(fmcp_qsfp3_rx_p[2]), + .xcvr_rxn(fmcp_qsfp3_rx_n[2]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp3_tx_clk_3_int), + .phy_tx_rst(fmcp_qsfp3_tx_rst_3_int), + .phy_xgmii_txd(fmcp_qsfp3_txd_3_int), + .phy_xgmii_txc(fmcp_qsfp3_txc_3_int), + .phy_rx_clk(fmcp_qsfp3_rx_clk_3_int), + .phy_rx_rst(fmcp_qsfp3_rx_rst_3_int), + .phy_xgmii_rxd(fmcp_qsfp3_rxd_3_int), + .phy_xgmii_rxc(fmcp_qsfp3_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmcp_qsfp3_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmcp_qsfp3_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmcp_qsfp3_qpll0outclk), + .xcvr_qpll0refclk_in(fmcp_qsfp3_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmcp_qsfp3_tx_p[3]), + .xcvr_txn(fmcp_qsfp3_tx_n[3]), + .xcvr_rxp(fmcp_qsfp3_rx_p[3]), + .xcvr_rxn(fmcp_qsfp3_rx_n[3]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp3_tx_clk_4_int), + .phy_tx_rst(fmcp_qsfp3_tx_rst_4_int), + .phy_xgmii_txd(fmcp_qsfp3_txd_4_int), + .phy_xgmii_txc(fmcp_qsfp3_txc_4_int), + .phy_rx_clk(fmcp_qsfp3_rx_clk_4_int), + .phy_rx_rst(fmcp_qsfp3_rx_rst_4_int), + .phy_xgmii_rxd(fmcp_qsfp3_rxd_4_int), + .phy_xgmii_rxc(fmcp_qsfp3_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// FMC QSFP4 +assign fmcp_qsfp4_modsell = 1'b1; +assign fmcp_qsfp4_resetl = 1'b1; +assign fmcp_qsfp4_lpmode = 1'b0; + +wire fmcp_qsfp4_tx_clk_1_int; +wire fmcp_qsfp4_tx_rst_1_int; +wire [63:0] fmcp_qsfp4_txd_1_int; +wire [7:0] fmcp_qsfp4_txc_1_int; +wire fmcp_qsfp4_rx_clk_1_int; +wire fmcp_qsfp4_rx_rst_1_int; +wire [63:0] fmcp_qsfp4_rxd_1_int; +wire [7:0] fmcp_qsfp4_rxc_1_int; +wire fmcp_qsfp4_tx_clk_2_int; +wire fmcp_qsfp4_tx_rst_2_int; +wire [63:0] fmcp_qsfp4_txd_2_int; +wire [7:0] fmcp_qsfp4_txc_2_int; +wire fmcp_qsfp4_rx_clk_2_int; +wire fmcp_qsfp4_rx_rst_2_int; +wire [63:0] fmcp_qsfp4_rxd_2_int; +wire [7:0] fmcp_qsfp4_rxc_2_int; +wire fmcp_qsfp4_tx_clk_3_int; +wire fmcp_qsfp4_tx_rst_3_int; +wire [63:0] fmcp_qsfp4_txd_3_int; +wire [7:0] fmcp_qsfp4_txc_3_int; +wire fmcp_qsfp4_rx_clk_3_int; +wire fmcp_qsfp4_rx_rst_3_int; +wire [63:0] fmcp_qsfp4_rxd_3_int; +wire [7:0] fmcp_qsfp4_rxc_3_int; +wire fmcp_qsfp4_tx_clk_4_int; +wire fmcp_qsfp4_tx_rst_4_int; +wire [63:0] fmcp_qsfp4_txd_4_int; +wire [7:0] fmcp_qsfp4_txc_4_int; +wire fmcp_qsfp4_rx_clk_4_int; +wire fmcp_qsfp4_rx_rst_4_int; +wire [63:0] fmcp_qsfp4_rxd_4_int; +wire [7:0] fmcp_qsfp4_rxc_4_int; + +wire fmcp_qsfp4_rx_block_lock_1; +wire fmcp_qsfp4_rx_block_lock_2; +wire fmcp_qsfp4_rx_block_lock_3; +wire fmcp_qsfp4_rx_block_lock_4; + +wire fmcp_qsfp4_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_fmcp_qsfp4_mgt_refclk_inst ( + .I (fmcp_qsfp4_mgt_refclk_p), + .IB (fmcp_qsfp4_mgt_refclk_n), + .CEB (1'b0), + .O (fmcp_qsfp4_mgt_refclk), + .ODIV2 () +); + +wire fmcp_qsfp4_qpll0lock; +wire fmcp_qsfp4_qpll0outclk; +wire fmcp_qsfp4_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +fmcp_qsfp4_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(fmcp_qsfp4_mgt_refclk), + .xcvr_qpll0lock_out(fmcp_qsfp4_qpll0lock), + .xcvr_qpll0outclk_out(fmcp_qsfp4_qpll0outclk), + .xcvr_qpll0outrefclk_out(fmcp_qsfp4_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(fmcp_qsfp4_tx_p[0]), + .xcvr_txn(fmcp_qsfp4_tx_n[0]), + .xcvr_rxp(fmcp_qsfp4_rx_p[0]), + .xcvr_rxn(fmcp_qsfp4_rx_n[0]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp4_tx_clk_1_int), + .phy_tx_rst(fmcp_qsfp4_tx_rst_1_int), + .phy_xgmii_txd(fmcp_qsfp4_txd_1_int), + .phy_xgmii_txc(fmcp_qsfp4_txc_1_int), + .phy_rx_clk(fmcp_qsfp4_rx_clk_1_int), + .phy_rx_rst(fmcp_qsfp4_rx_rst_1_int), + .phy_xgmii_rxd(fmcp_qsfp4_rxd_1_int), + .phy_xgmii_rxc(fmcp_qsfp4_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmcp_qsfp4_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmcp_qsfp4_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmcp_qsfp4_qpll0outclk), + .xcvr_qpll0refclk_in(fmcp_qsfp4_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmcp_qsfp4_tx_p[1]), + .xcvr_txn(fmcp_qsfp4_tx_n[1]), + .xcvr_rxp(fmcp_qsfp4_rx_p[1]), + .xcvr_rxn(fmcp_qsfp4_rx_n[1]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp4_tx_clk_2_int), + .phy_tx_rst(fmcp_qsfp4_tx_rst_2_int), + .phy_xgmii_txd(fmcp_qsfp4_txd_2_int), + .phy_xgmii_txc(fmcp_qsfp4_txc_2_int), + .phy_rx_clk(fmcp_qsfp4_rx_clk_2_int), + .phy_rx_rst(fmcp_qsfp4_rx_rst_2_int), + .phy_xgmii_rxd(fmcp_qsfp4_rxd_2_int), + .phy_xgmii_rxc(fmcp_qsfp4_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmcp_qsfp4_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmcp_qsfp4_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmcp_qsfp4_qpll0outclk), + .xcvr_qpll0refclk_in(fmcp_qsfp4_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmcp_qsfp4_tx_p[2]), + .xcvr_txn(fmcp_qsfp4_tx_n[2]), + .xcvr_rxp(fmcp_qsfp4_rx_p[2]), + .xcvr_rxn(fmcp_qsfp4_rx_n[2]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp4_tx_clk_3_int), + .phy_tx_rst(fmcp_qsfp4_tx_rst_3_int), + .phy_xgmii_txd(fmcp_qsfp4_txd_3_int), + .phy_xgmii_txc(fmcp_qsfp4_txc_3_int), + .phy_rx_clk(fmcp_qsfp4_rx_clk_3_int), + .phy_rx_rst(fmcp_qsfp4_rx_rst_3_int), + .phy_xgmii_rxd(fmcp_qsfp4_rxd_3_int), + .phy_xgmii_rxc(fmcp_qsfp4_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmcp_qsfp4_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmcp_qsfp4_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmcp_qsfp4_qpll0outclk), + .xcvr_qpll0refclk_in(fmcp_qsfp4_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmcp_qsfp4_tx_p[3]), + .xcvr_txn(fmcp_qsfp4_tx_n[3]), + .xcvr_rxp(fmcp_qsfp4_rx_p[3]), + .xcvr_rxn(fmcp_qsfp4_rx_n[3]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp4_tx_clk_4_int), + .phy_tx_rst(fmcp_qsfp4_tx_rst_4_int), + .phy_xgmii_txd(fmcp_qsfp4_txd_4_int), + .phy_xgmii_txc(fmcp_qsfp4_txc_4_int), + .phy_rx_clk(fmcp_qsfp4_rx_clk_4_int), + .phy_rx_rst(fmcp_qsfp4_rx_rst_4_int), + .phy_xgmii_rxd(fmcp_qsfp4_rxd_4_int), + .phy_xgmii_rxc(fmcp_qsfp4_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// FMC QSFP5 +assign fmcp_qsfp5_modsell = 1'b1; +assign fmcp_qsfp5_resetl = 1'b1; +assign fmcp_qsfp5_lpmode = 1'b0; + +wire fmcp_qsfp5_tx_clk_1_int; +wire fmcp_qsfp5_tx_rst_1_int; +wire [63:0] fmcp_qsfp5_txd_1_int; +wire [7:0] fmcp_qsfp5_txc_1_int; +wire fmcp_qsfp5_rx_clk_1_int; +wire fmcp_qsfp5_rx_rst_1_int; +wire [63:0] fmcp_qsfp5_rxd_1_int; +wire [7:0] fmcp_qsfp5_rxc_1_int; +wire fmcp_qsfp5_tx_clk_2_int; +wire fmcp_qsfp5_tx_rst_2_int; +wire [63:0] fmcp_qsfp5_txd_2_int; +wire [7:0] fmcp_qsfp5_txc_2_int; +wire fmcp_qsfp5_rx_clk_2_int; +wire fmcp_qsfp5_rx_rst_2_int; +wire [63:0] fmcp_qsfp5_rxd_2_int; +wire [7:0] fmcp_qsfp5_rxc_2_int; +wire fmcp_qsfp5_tx_clk_3_int; +wire fmcp_qsfp5_tx_rst_3_int; +wire [63:0] fmcp_qsfp5_txd_3_int; +wire [7:0] fmcp_qsfp5_txc_3_int; +wire fmcp_qsfp5_rx_clk_3_int; +wire fmcp_qsfp5_rx_rst_3_int; +wire [63:0] fmcp_qsfp5_rxd_3_int; +wire [7:0] fmcp_qsfp5_rxc_3_int; +wire fmcp_qsfp5_tx_clk_4_int; +wire fmcp_qsfp5_tx_rst_4_int; +wire [63:0] fmcp_qsfp5_txd_4_int; +wire [7:0] fmcp_qsfp5_txc_4_int; +wire fmcp_qsfp5_rx_clk_4_int; +wire fmcp_qsfp5_rx_rst_4_int; +wire [63:0] fmcp_qsfp5_rxd_4_int; +wire [7:0] fmcp_qsfp5_rxc_4_int; + +wire fmcp_qsfp5_rx_block_lock_1; +wire fmcp_qsfp5_rx_block_lock_2; +wire fmcp_qsfp5_rx_block_lock_3; +wire fmcp_qsfp5_rx_block_lock_4; + +wire fmcp_qsfp5_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_fmcp_qsfp5_mgt_refclk_inst ( + .I (fmcp_qsfp5_mgt_refclk_p), + .IB (fmcp_qsfp5_mgt_refclk_n), + .CEB (1'b0), + .O (fmcp_qsfp5_mgt_refclk), + .ODIV2 () +); + +wire fmcp_qsfp5_qpll0lock; +wire fmcp_qsfp5_qpll0outclk; +wire fmcp_qsfp5_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +fmcp_qsfp5_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(fmcp_qsfp5_mgt_refclk), + .xcvr_qpll0lock_out(fmcp_qsfp5_qpll0lock), + .xcvr_qpll0outclk_out(fmcp_qsfp5_qpll0outclk), + .xcvr_qpll0outrefclk_out(fmcp_qsfp5_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(fmcp_qsfp5_tx_p[0]), + .xcvr_txn(fmcp_qsfp5_tx_n[0]), + .xcvr_rxp(fmcp_qsfp5_rx_p[0]), + .xcvr_rxn(fmcp_qsfp5_rx_n[0]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp5_tx_clk_1_int), + .phy_tx_rst(fmcp_qsfp5_tx_rst_1_int), + .phy_xgmii_txd(fmcp_qsfp5_txd_1_int), + .phy_xgmii_txc(fmcp_qsfp5_txc_1_int), + .phy_rx_clk(fmcp_qsfp5_rx_clk_1_int), + .phy_rx_rst(fmcp_qsfp5_rx_rst_1_int), + .phy_xgmii_rxd(fmcp_qsfp5_rxd_1_int), + .phy_xgmii_rxc(fmcp_qsfp5_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmcp_qsfp5_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmcp_qsfp5_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmcp_qsfp5_qpll0outclk), + .xcvr_qpll0refclk_in(fmcp_qsfp5_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmcp_qsfp5_tx_p[1]), + .xcvr_txn(fmcp_qsfp5_tx_n[1]), + .xcvr_rxp(fmcp_qsfp5_rx_p[1]), + .xcvr_rxn(fmcp_qsfp5_rx_n[1]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp5_tx_clk_2_int), + .phy_tx_rst(fmcp_qsfp5_tx_rst_2_int), + .phy_xgmii_txd(fmcp_qsfp5_txd_2_int), + .phy_xgmii_txc(fmcp_qsfp5_txc_2_int), + .phy_rx_clk(fmcp_qsfp5_rx_clk_2_int), + .phy_rx_rst(fmcp_qsfp5_rx_rst_2_int), + .phy_xgmii_rxd(fmcp_qsfp5_rxd_2_int), + .phy_xgmii_rxc(fmcp_qsfp5_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmcp_qsfp5_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmcp_qsfp5_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmcp_qsfp5_qpll0outclk), + .xcvr_qpll0refclk_in(fmcp_qsfp5_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmcp_qsfp5_tx_p[2]), + .xcvr_txn(fmcp_qsfp5_tx_n[2]), + .xcvr_rxp(fmcp_qsfp5_rx_p[2]), + .xcvr_rxn(fmcp_qsfp5_rx_n[2]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp5_tx_clk_3_int), + .phy_tx_rst(fmcp_qsfp5_tx_rst_3_int), + .phy_xgmii_txd(fmcp_qsfp5_txd_3_int), + .phy_xgmii_txc(fmcp_qsfp5_txc_3_int), + .phy_rx_clk(fmcp_qsfp5_rx_clk_3_int), + .phy_rx_rst(fmcp_qsfp5_rx_rst_3_int), + .phy_xgmii_rxd(fmcp_qsfp5_rxd_3_int), + .phy_xgmii_rxc(fmcp_qsfp5_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmcp_qsfp5_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmcp_qsfp5_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmcp_qsfp5_qpll0outclk), + .xcvr_qpll0refclk_in(fmcp_qsfp5_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmcp_qsfp5_tx_p[3]), + .xcvr_txn(fmcp_qsfp5_tx_n[3]), + .xcvr_rxp(fmcp_qsfp5_rx_p[3]), + .xcvr_rxn(fmcp_qsfp5_rx_n[3]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp5_tx_clk_4_int), + .phy_tx_rst(fmcp_qsfp5_tx_rst_4_int), + .phy_xgmii_txd(fmcp_qsfp5_txd_4_int), + .phy_xgmii_txc(fmcp_qsfp5_txc_4_int), + .phy_rx_clk(fmcp_qsfp5_rx_clk_4_int), + .phy_rx_rst(fmcp_qsfp5_rx_rst_4_int), + .phy_xgmii_rxd(fmcp_qsfp5_rxd_4_int), + .phy_xgmii_rxc(fmcp_qsfp5_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// FMC QSFP6 +assign fmcp_qsfp6_modsell = 1'b1; +assign fmcp_qsfp6_resetl = 1'b1; +assign fmcp_qsfp6_lpmode = 1'b0; + +wire fmcp_qsfp6_tx_clk_1_int; +wire fmcp_qsfp6_tx_rst_1_int; +wire [63:0] fmcp_qsfp6_txd_1_int; +wire [7:0] fmcp_qsfp6_txc_1_int; +wire fmcp_qsfp6_rx_clk_1_int; +wire fmcp_qsfp6_rx_rst_1_int; +wire [63:0] fmcp_qsfp6_rxd_1_int; +wire [7:0] fmcp_qsfp6_rxc_1_int; +wire fmcp_qsfp6_tx_clk_2_int; +wire fmcp_qsfp6_tx_rst_2_int; +wire [63:0] fmcp_qsfp6_txd_2_int; +wire [7:0] fmcp_qsfp6_txc_2_int; +wire fmcp_qsfp6_rx_clk_2_int; +wire fmcp_qsfp6_rx_rst_2_int; +wire [63:0] fmcp_qsfp6_rxd_2_int; +wire [7:0] fmcp_qsfp6_rxc_2_int; +wire fmcp_qsfp6_tx_clk_3_int; +wire fmcp_qsfp6_tx_rst_3_int; +wire [63:0] fmcp_qsfp6_txd_3_int; +wire [7:0] fmcp_qsfp6_txc_3_int; +wire fmcp_qsfp6_rx_clk_3_int; +wire fmcp_qsfp6_rx_rst_3_int; +wire [63:0] fmcp_qsfp6_rxd_3_int; +wire [7:0] fmcp_qsfp6_rxc_3_int; +wire fmcp_qsfp6_tx_clk_4_int; +wire fmcp_qsfp6_tx_rst_4_int; +wire [63:0] fmcp_qsfp6_txd_4_int; +wire [7:0] fmcp_qsfp6_txc_4_int; +wire fmcp_qsfp6_rx_clk_4_int; +wire fmcp_qsfp6_rx_rst_4_int; +wire [63:0] fmcp_qsfp6_rxd_4_int; +wire [7:0] fmcp_qsfp6_rxc_4_int; + +wire fmcp_qsfp6_rx_block_lock_1; +wire fmcp_qsfp6_rx_block_lock_2; +wire fmcp_qsfp6_rx_block_lock_3; +wire fmcp_qsfp6_rx_block_lock_4; + +wire fmcp_qsfp6_mgt_refclk; + +IBUFDS_GTE4 ibufds_gte4_fmcp_qsfp6_mgt_refclk_inst ( + .I (fmcp_qsfp6_mgt_refclk_p), + .IB (fmcp_qsfp6_mgt_refclk_n), + .CEB (1'b0), + .O (fmcp_qsfp6_mgt_refclk), + .ODIV2 () +); + +wire fmcp_qsfp6_qpll0lock; +wire fmcp_qsfp6_qpll0outclk; +wire fmcp_qsfp6_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1) +) +fmcp_qsfp6_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(fmcp_qsfp6_mgt_refclk), + .xcvr_qpll0lock_out(fmcp_qsfp6_qpll0lock), + .xcvr_qpll0outclk_out(fmcp_qsfp6_qpll0outclk), + .xcvr_qpll0outrefclk_out(fmcp_qsfp6_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(fmcp_qsfp6_tx_p[0]), + .xcvr_txn(fmcp_qsfp6_tx_n[0]), + .xcvr_rxp(fmcp_qsfp6_rx_p[0]), + .xcvr_rxn(fmcp_qsfp6_rx_n[0]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp6_tx_clk_1_int), + .phy_tx_rst(fmcp_qsfp6_tx_rst_1_int), + .phy_xgmii_txd(fmcp_qsfp6_txd_1_int), + .phy_xgmii_txc(fmcp_qsfp6_txc_1_int), + .phy_rx_clk(fmcp_qsfp6_rx_clk_1_int), + .phy_rx_rst(fmcp_qsfp6_rx_rst_1_int), + .phy_xgmii_rxd(fmcp_qsfp6_rxd_1_int), + .phy_xgmii_rxc(fmcp_qsfp6_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmcp_qsfp6_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmcp_qsfp6_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmcp_qsfp6_qpll0outclk), + .xcvr_qpll0refclk_in(fmcp_qsfp6_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmcp_qsfp6_tx_p[1]), + .xcvr_txn(fmcp_qsfp6_tx_n[1]), + .xcvr_rxp(fmcp_qsfp6_rx_p[1]), + .xcvr_rxn(fmcp_qsfp6_rx_n[1]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp6_tx_clk_2_int), + .phy_tx_rst(fmcp_qsfp6_tx_rst_2_int), + .phy_xgmii_txd(fmcp_qsfp6_txd_2_int), + .phy_xgmii_txc(fmcp_qsfp6_txc_2_int), + .phy_rx_clk(fmcp_qsfp6_rx_clk_2_int), + .phy_rx_rst(fmcp_qsfp6_rx_rst_2_int), + .phy_xgmii_rxd(fmcp_qsfp6_rxd_2_int), + .phy_xgmii_rxc(fmcp_qsfp6_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmcp_qsfp6_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmcp_qsfp6_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmcp_qsfp6_qpll0outclk), + .xcvr_qpll0refclk_in(fmcp_qsfp6_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmcp_qsfp6_tx_p[2]), + .xcvr_txn(fmcp_qsfp6_tx_n[2]), + .xcvr_rxp(fmcp_qsfp6_rx_p[2]), + .xcvr_rxn(fmcp_qsfp6_rx_n[2]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp6_tx_clk_3_int), + .phy_tx_rst(fmcp_qsfp6_tx_rst_3_int), + .phy_xgmii_txd(fmcp_qsfp6_txd_3_int), + .phy_xgmii_txc(fmcp_qsfp6_txc_3_int), + .phy_rx_clk(fmcp_qsfp6_rx_clk_3_int), + .phy_rx_rst(fmcp_qsfp6_rx_rst_3_int), + .phy_xgmii_rxd(fmcp_qsfp6_rxd_3_int), + .phy_xgmii_rxc(fmcp_qsfp6_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0) +) +fmcp_qsfp6_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(fmcp_qsfp_reset), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(fmcp_qsfp6_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(fmcp_qsfp6_qpll0outclk), + .xcvr_qpll0refclk_in(fmcp_qsfp6_qpll0outrefclk), + + // Serial data + .xcvr_txp(fmcp_qsfp6_tx_p[3]), + .xcvr_txn(fmcp_qsfp6_tx_n[3]), + .xcvr_rxp(fmcp_qsfp6_rx_p[3]), + .xcvr_rxn(fmcp_qsfp6_rx_n[3]), + + // PHY connections + .phy_tx_clk(fmcp_qsfp6_tx_clk_4_int), + .phy_tx_rst(fmcp_qsfp6_tx_rst_4_int), + .phy_xgmii_txd(fmcp_qsfp6_txd_4_int), + .phy_xgmii_txc(fmcp_qsfp6_txc_4_int), + .phy_rx_clk(fmcp_qsfp6_rx_clk_4_int), + .phy_rx_rst(fmcp_qsfp6_rx_rst_4_int), + .phy_xgmii_rxd(fmcp_qsfp6_rxd_4_int), + .phy_xgmii_rxc(fmcp_qsfp6_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(), + .phy_rx_prbs31_enable() +); + +// SGMII interface to PHY +wire phy_gmii_clk_int; +wire phy_gmii_rst_int; +wire phy_gmii_clk_en_int; +wire [7:0] phy_gmii_txd_int; +wire phy_gmii_tx_en_int; +wire phy_gmii_tx_er_int; +wire [7:0] phy_gmii_rxd_int; +wire phy_gmii_rx_dv_int; +wire phy_gmii_rx_er_int; + +wire [15:0] gig_eth_pcspma_status_vector; + +wire gig_eth_pcspma_status_link_status = gig_eth_pcspma_status_vector[0]; +wire gig_eth_pcspma_status_link_synchronization = gig_eth_pcspma_status_vector[1]; +wire gig_eth_pcspma_status_rudi_c = gig_eth_pcspma_status_vector[2]; +wire gig_eth_pcspma_status_rudi_i = gig_eth_pcspma_status_vector[3]; +wire gig_eth_pcspma_status_rudi_invalid = gig_eth_pcspma_status_vector[4]; +wire gig_eth_pcspma_status_rxdisperr = gig_eth_pcspma_status_vector[5]; +wire gig_eth_pcspma_status_rxnotintable = gig_eth_pcspma_status_vector[6]; +wire gig_eth_pcspma_status_phy_link_status = gig_eth_pcspma_status_vector[7]; +wire [1:0] gig_eth_pcspma_status_remote_fault_encdg = gig_eth_pcspma_status_vector[9:8]; +wire [1:0] gig_eth_pcspma_status_speed = gig_eth_pcspma_status_vector[11:10]; +wire gig_eth_pcspma_status_duplex = gig_eth_pcspma_status_vector[12]; +wire gig_eth_pcspma_status_remote_fault = gig_eth_pcspma_status_vector[13]; +wire [1:0] gig_eth_pcspma_status_pause = gig_eth_pcspma_status_vector[15:14]; + +wire [4:0] gig_eth_pcspma_config_vector; + +assign gig_eth_pcspma_config_vector[4] = 1'b1; // autonegotiation enable +assign gig_eth_pcspma_config_vector[3] = 1'b0; // isolate +assign gig_eth_pcspma_config_vector[2] = 1'b0; // power down +assign gig_eth_pcspma_config_vector[1] = 1'b0; // loopback enable +assign gig_eth_pcspma_config_vector[0] = 1'b0; // unidirectional enable + +wire [15:0] gig_eth_pcspma_an_config_vector; + +assign gig_eth_pcspma_an_config_vector[15] = 1'b1; // SGMII link status +assign gig_eth_pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge +assign gig_eth_pcspma_an_config_vector[13:12] = 2'b01; // full duplex +assign gig_eth_pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed +assign gig_eth_pcspma_an_config_vector[9] = 1'b0; // reserved +assign gig_eth_pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved +assign gig_eth_pcspma_an_config_vector[6] = 1'b0; // reserved +assign gig_eth_pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved +assign gig_eth_pcspma_an_config_vector[4:1] = 4'b0000; // reserved +assign gig_eth_pcspma_an_config_vector[0] = 1'b1; // SGMII + +gig_ethernet_pcs_pma_0 +eth_pcspma ( + // SGMII + .txp_0 (phy_sgmii_tx_p), + .txn_0 (phy_sgmii_tx_n), + .rxp_0 (phy_sgmii_rx_p), + .rxn_0 (phy_sgmii_rx_n), + + // Ref clock from PHY + .refclk625_p (phy_sgmii_clk_p), + .refclk625_n (phy_sgmii_clk_n), + + // async reset + .reset (rst_125mhz_int), + + // clock and reset outputs + .clk125_out (phy_gmii_clk_int), + .clk312_out (), + .rst_125_out (phy_gmii_rst_int), + .tx_logic_reset (), + .rx_logic_reset (), + .tx_locked (), + .rx_locked (), + .tx_pll_clk_out (), + .rx_pll_clk_out (), + + // MAC clocking + .sgmii_clk_r_0 (), + .sgmii_clk_f_0 (), + .sgmii_clk_en_0 (phy_gmii_clk_en_int), + + // Speed control + .speed_is_10_100_0 (gig_eth_pcspma_status_speed != 2'b10), + .speed_is_100_0 (gig_eth_pcspma_status_speed == 2'b01), + + // Internal GMII + .gmii_txd_0 (phy_gmii_txd_int), + .gmii_tx_en_0 (phy_gmii_tx_en_int), + .gmii_tx_er_0 (phy_gmii_tx_er_int), + .gmii_rxd_0 (phy_gmii_rxd_int), + .gmii_rx_dv_0 (phy_gmii_rx_dv_int), + .gmii_rx_er_0 (phy_gmii_rx_er_int), + .gmii_isolate_0 (), + + // Configuration + .configuration_vector_0 (gig_eth_pcspma_config_vector), + + .an_interrupt_0 (), + .an_adv_config_vector_0 (gig_eth_pcspma_an_config_vector), + .an_restart_config_0 (1'b0), + + // Status + .status_vector_0 (gig_eth_pcspma_status_vector), + .signal_detect_0 (1'b1), + + // Cascade + .tx_bsc_rst_out (), + .rx_bsc_rst_out (), + .tx_bs_rst_out (), + .rx_bs_rst_out (), + .tx_rst_dly_out (), + .rx_rst_dly_out (), + .tx_bsc_en_vtc_out (), + .rx_bsc_en_vtc_out (), + .tx_bs_en_vtc_out (), + .rx_bs_en_vtc_out (), + .riu_clk_out (), + .riu_addr_out (), + .riu_wr_data_out (), + .riu_wr_en_out (), + .riu_nibble_sel_out (), + .riu_rddata_1 (16'b0), + .riu_valid_1 (1'b0), + .riu_prsnt_1 (1'b0), + .riu_rddata_2 (16'b0), + .riu_valid_2 (1'b0), + .riu_prsnt_2 (1'b0), + .riu_rddata_3 (16'b0), + .riu_valid_3 (1'b0), + .riu_prsnt_3 (1'b0), + .rx_btval_1 (), + .rx_btval_2 (), + .rx_btval_3 (), + .tx_dly_rdy_1 (1'b1), + .rx_dly_rdy_1 (1'b1), + .rx_vtc_rdy_1 (1'b1), + .tx_vtc_rdy_1 (1'b1), + .tx_dly_rdy_2 (1'b1), + .rx_dly_rdy_2 (1'b1), + .rx_vtc_rdy_2 (1'b1), + .tx_vtc_rdy_2 (1'b1), + .tx_dly_rdy_3 (1'b1), + .rx_dly_rdy_3 (1'b1), + .rx_vtc_rdy_3 (1'b1), + .tx_vtc_rdy_3 (1'b1), + .tx_rdclk_out () +); + +reg [19:0] delay_reg = 20'hfffff; + +reg [4:0] mdio_cmd_phy_addr = 5'h03; +reg [4:0] mdio_cmd_reg_addr = 5'h00; +reg [15:0] mdio_cmd_data = 16'd0; +reg [1:0] mdio_cmd_opcode = 2'b01; +reg mdio_cmd_valid = 1'b0; +wire mdio_cmd_ready; + +reg [3:0] state_reg = 0; + +always @(posedge clk_125mhz_int) begin + if (rst_125mhz_int) begin + state_reg <= 0; + delay_reg <= 20'hfffff; + mdio_cmd_reg_addr <= 5'h00; + mdio_cmd_data <= 16'd0; + mdio_cmd_valid <= 1'b0; + end else begin + mdio_cmd_valid <= mdio_cmd_valid & !mdio_cmd_ready; + if (delay_reg > 0) begin + delay_reg <= delay_reg - 1; + end else if (!mdio_cmd_ready) begin + // wait for ready + state_reg <= state_reg; + end else begin + mdio_cmd_valid <= 1'b0; + case (state_reg) + // set SGMII autonegotiation timer to 11 ms + // write 0x0070 to CFG4 (0x0031) + 4'd0: begin + // write to REGCR to load address + mdio_cmd_reg_addr <= 5'h0D; + mdio_cmd_data <= 16'h001F; + mdio_cmd_valid <= 1'b1; + state_reg <= 4'd1; + end + 4'd1: begin + // write address of CFG4 to ADDAR + mdio_cmd_reg_addr <= 5'h0E; + mdio_cmd_data <= 16'h0031; + mdio_cmd_valid <= 1'b1; + state_reg <= 4'd2; + end + 4'd2: begin + // write to REGCR to load data + mdio_cmd_reg_addr <= 5'h0D; + mdio_cmd_data <= 16'h401F; + mdio_cmd_valid <= 1'b1; + state_reg <= 4'd3; + end + 4'd3: begin + // write data for CFG4 to ADDAR + mdio_cmd_reg_addr <= 5'h0E; + mdio_cmd_data <= 16'h0070; + mdio_cmd_valid <= 1'b1; + state_reg <= 4'd4; + end + // enable SGMII clock output + // write 0x4000 to SGMIICTL1 (0x00D3) + 4'd4: begin + // write to REGCR to load address + mdio_cmd_reg_addr <= 5'h0D; + mdio_cmd_data <= 16'h001F; + mdio_cmd_valid <= 1'b1; + state_reg <= 4'd5; + end + 4'd5: begin + // write address of SGMIICTL1 to ADDAR + mdio_cmd_reg_addr <= 5'h0E; + mdio_cmd_data <= 16'h00D3; + mdio_cmd_valid <= 1'b1; + state_reg <= 4'd6; + end + 4'd6: begin + // write to REGCR to load data + mdio_cmd_reg_addr <= 5'h0D; + mdio_cmd_data <= 16'h401F; + mdio_cmd_valid <= 1'b1; + state_reg <= 4'd7; + end + 4'd7: begin + // write data for SGMIICTL1 to ADDAR + mdio_cmd_reg_addr <= 5'h0E; + mdio_cmd_data <= 16'h4000; + mdio_cmd_valid <= 1'b1; + state_reg <= 4'd8; + end + // enable 10Mbps operation + // write 0x0015 to 10M_SGMII_CFG (0x016F) + 4'd8: begin + // write to REGCR to load address + mdio_cmd_reg_addr <= 5'h0D; + mdio_cmd_data <= 16'h001F; + mdio_cmd_valid <= 1'b1; + state_reg <= 4'd9; + end + 4'd9: begin + // write address of 10M_SGMII_CFG to ADDAR + mdio_cmd_reg_addr <= 5'h0E; + mdio_cmd_data <= 16'h016F; + mdio_cmd_valid <= 1'b1; + state_reg <= 4'd10; + end + 4'd10: begin + // write to REGCR to load data + mdio_cmd_reg_addr <= 5'h0D; + mdio_cmd_data <= 16'h401F; + mdio_cmd_valid <= 1'b1; + state_reg <= 4'd11; + end + 4'd11: begin + // write data for 10M_SGMII_CFG to ADDAR + mdio_cmd_reg_addr <= 5'h0E; + mdio_cmd_data <= 16'h0015; + mdio_cmd_valid <= 1'b1; + state_reg <= 4'd12; + end + 4'd12: begin + // done + state_reg <= 4'd12; + end + endcase + end + end +end + +wire mdc; +wire mdio_i; +wire mdio_o; +wire mdio_t; + +mdio_master +mdio_master_inst ( + .clk(clk_125mhz_int), + .rst(rst_125mhz_int), + + .cmd_phy_addr(mdio_cmd_phy_addr), + .cmd_reg_addr(mdio_cmd_reg_addr), + .cmd_data(mdio_cmd_data), + .cmd_opcode(mdio_cmd_opcode), + .cmd_valid(mdio_cmd_valid), + .cmd_ready(mdio_cmd_ready), + + .data_out(), + .data_out_valid(), + .data_out_ready(1'b1), + + .mdc_o(mdc), + .mdio_i(mdio_i), + .mdio_o(mdio_o), + .mdio_t(mdio_t), + + .busy(), + + .prescale(8'd3) +); + +assign phy_mdc = mdc; +assign mdio_i = phy_mdio; +assign phy_mdio = mdio_t ? 1'bz : mdio_o; + +wire [7:0] led_int; + +assign led[0] = sw[0] ? qsfp1_rx_block_lock_1 : led_int[0]; +assign led[1] = sw[0] ? qsfp1_rx_block_lock_2 : led_int[1]; +assign led[2] = sw[0] ? qsfp1_rx_block_lock_3 : led_int[2]; +assign led[3] = sw[0] ? qsfp1_rx_block_lock_4 : led_int[3]; +assign led[4] = sw[0] ? qsfp2_rx_block_lock_1 : led_int[4]; +assign led[5] = sw[0] ? qsfp2_rx_block_lock_2 : led_int[5]; +assign led[6] = sw[0] ? qsfp2_rx_block_lock_3 : led_int[6]; +assign led[7] = sw[0] ? qsfp2_rx_block_lock_4 : led_int[7]; + +fpga_core +core_inst ( + /* + * Clock: 390.625 MHz + * Synchronous reset + */ + .clk(clk_390mhz_int), + .rst(rst_390mhz_int), + /* + * GPIO + */ + .btnu(btnu_int), + .btnl(btnl_int), + .btnd(btnd_int), + .btnr(btnr_int), + .btnc(btnc_int), + .sw(sw_int), + .led(led_int), + /* + * Ethernet: QSFP28 + */ + .qsfp1_tx_clk_1(qsfp1_tx_clk_1_int), + .qsfp1_tx_rst_1(qsfp1_tx_rst_1_int), + .qsfp1_txd_1(qsfp1_txd_1_int), + .qsfp1_txc_1(qsfp1_txc_1_int), + .qsfp1_rx_clk_1(qsfp1_rx_clk_1_int), + .qsfp1_rx_rst_1(qsfp1_rx_rst_1_int), + .qsfp1_rxd_1(qsfp1_rxd_1_int), + .qsfp1_rxc_1(qsfp1_rxc_1_int), + .qsfp1_tx_clk_2(qsfp1_tx_clk_2_int), + .qsfp1_tx_rst_2(qsfp1_tx_rst_2_int), + .qsfp1_txd_2(qsfp1_txd_2_int), + .qsfp1_txc_2(qsfp1_txc_2_int), + .qsfp1_rx_clk_2(qsfp1_rx_clk_2_int), + .qsfp1_rx_rst_2(qsfp1_rx_rst_2_int), + .qsfp1_rxd_2(qsfp1_rxd_2_int), + .qsfp1_rxc_2(qsfp1_rxc_2_int), + .qsfp1_tx_clk_3(qsfp1_tx_clk_3_int), + .qsfp1_tx_rst_3(qsfp1_tx_rst_3_int), + .qsfp1_txd_3(qsfp1_txd_3_int), + .qsfp1_txc_3(qsfp1_txc_3_int), + .qsfp1_rx_clk_3(qsfp1_rx_clk_3_int), + .qsfp1_rx_rst_3(qsfp1_rx_rst_3_int), + .qsfp1_rxd_3(qsfp1_rxd_3_int), + .qsfp1_rxc_3(qsfp1_rxc_3_int), + .qsfp1_tx_clk_4(qsfp1_tx_clk_4_int), + .qsfp1_tx_rst_4(qsfp1_tx_rst_4_int), + .qsfp1_txd_4(qsfp1_txd_4_int), + .qsfp1_txc_4(qsfp1_txc_4_int), + .qsfp1_rx_clk_4(qsfp1_rx_clk_4_int), + .qsfp1_rx_rst_4(qsfp1_rx_rst_4_int), + .qsfp1_rxd_4(qsfp1_rxd_4_int), + .qsfp1_rxc_4(qsfp1_rxc_4_int), + .qsfp2_tx_clk_1(qsfp2_tx_clk_1_int), + .qsfp2_tx_rst_1(qsfp2_tx_rst_1_int), + .qsfp2_txd_1(qsfp2_txd_1_int), + .qsfp2_txc_1(qsfp2_txc_1_int), + .qsfp2_rx_clk_1(qsfp2_rx_clk_1_int), + .qsfp2_rx_rst_1(qsfp2_rx_rst_1_int), + .qsfp2_rxd_1(qsfp2_rxd_1_int), + .qsfp2_rxc_1(qsfp2_rxc_1_int), + .qsfp2_tx_clk_2(qsfp2_tx_clk_2_int), + .qsfp2_tx_rst_2(qsfp2_tx_rst_2_int), + .qsfp2_txd_2(qsfp2_txd_2_int), + .qsfp2_txc_2(qsfp2_txc_2_int), + .qsfp2_rx_clk_2(qsfp2_rx_clk_2_int), + .qsfp2_rx_rst_2(qsfp2_rx_rst_2_int), + .qsfp2_rxd_2(qsfp2_rxd_2_int), + .qsfp2_rxc_2(qsfp2_rxc_2_int), + .qsfp2_tx_clk_3(qsfp2_tx_clk_3_int), + .qsfp2_tx_rst_3(qsfp2_tx_rst_3_int), + .qsfp2_txd_3(qsfp2_txd_3_int), + .qsfp2_txc_3(qsfp2_txc_3_int), + .qsfp2_rx_clk_3(qsfp2_rx_clk_3_int), + .qsfp2_rx_rst_3(qsfp2_rx_rst_3_int), + .qsfp2_rxd_3(qsfp2_rxd_3_int), + .qsfp2_rxc_3(qsfp2_rxc_3_int), + .qsfp2_tx_clk_4(qsfp2_tx_clk_4_int), + .qsfp2_tx_rst_4(qsfp2_tx_rst_4_int), + .qsfp2_txd_4(qsfp2_txd_4_int), + .qsfp2_txc_4(qsfp2_txc_4_int), + .qsfp2_rx_clk_4(qsfp2_rx_clk_4_int), + .qsfp2_rx_rst_4(qsfp2_rx_rst_4_int), + .qsfp2_rxd_4(qsfp2_rxd_4_int), + .qsfp2_rxc_4(qsfp2_rxc_4_int), + /* + * Ethernet: QSFP28 via HTG 6x QSFP28 FMC+ adapter + */ + .fmcp_qsfp1_tx_clk_1(fmcp_qsfp1_tx_clk_1_int), + .fmcp_qsfp1_tx_rst_1(fmcp_qsfp1_tx_rst_1_int), + .fmcp_qsfp1_txd_1(fmcp_qsfp1_txd_1_int), + .fmcp_qsfp1_txc_1(fmcp_qsfp1_txc_1_int), + .fmcp_qsfp1_rx_clk_1(fmcp_qsfp1_rx_clk_1_int), + .fmcp_qsfp1_rx_rst_1(fmcp_qsfp1_rx_rst_1_int), + .fmcp_qsfp1_rxd_1(fmcp_qsfp1_rxd_1_int), + .fmcp_qsfp1_rxc_1(fmcp_qsfp1_rxc_1_int), + .fmcp_qsfp1_tx_clk_2(fmcp_qsfp1_tx_clk_2_int), + .fmcp_qsfp1_tx_rst_2(fmcp_qsfp1_tx_rst_2_int), + .fmcp_qsfp1_txd_2(fmcp_qsfp1_txd_2_int), + .fmcp_qsfp1_txc_2(fmcp_qsfp1_txc_2_int), + .fmcp_qsfp1_rx_clk_2(fmcp_qsfp1_rx_clk_2_int), + .fmcp_qsfp1_rx_rst_2(fmcp_qsfp1_rx_rst_2_int), + .fmcp_qsfp1_rxd_2(fmcp_qsfp1_rxd_2_int), + .fmcp_qsfp1_rxc_2(fmcp_qsfp1_rxc_2_int), + .fmcp_qsfp1_tx_clk_3(fmcp_qsfp1_tx_clk_3_int), + .fmcp_qsfp1_tx_rst_3(fmcp_qsfp1_tx_rst_3_int), + .fmcp_qsfp1_txd_3(fmcp_qsfp1_txd_3_int), + .fmcp_qsfp1_txc_3(fmcp_qsfp1_txc_3_int), + .fmcp_qsfp1_rx_clk_3(fmcp_qsfp1_rx_clk_3_int), + .fmcp_qsfp1_rx_rst_3(fmcp_qsfp1_rx_rst_3_int), + .fmcp_qsfp1_rxd_3(fmcp_qsfp1_rxd_3_int), + .fmcp_qsfp1_rxc_3(fmcp_qsfp1_rxc_3_int), + .fmcp_qsfp1_tx_clk_4(fmcp_qsfp1_tx_clk_4_int), + .fmcp_qsfp1_tx_rst_4(fmcp_qsfp1_tx_rst_4_int), + .fmcp_qsfp1_txd_4(fmcp_qsfp1_txd_4_int), + .fmcp_qsfp1_txc_4(fmcp_qsfp1_txc_4_int), + .fmcp_qsfp1_rx_clk_4(fmcp_qsfp1_rx_clk_4_int), + .fmcp_qsfp1_rx_rst_4(fmcp_qsfp1_rx_rst_4_int), + .fmcp_qsfp1_rxd_4(fmcp_qsfp1_rxd_4_int), + .fmcp_qsfp1_rxc_4(fmcp_qsfp1_rxc_4_int), + .fmcp_qsfp2_tx_clk_1(fmcp_qsfp2_tx_clk_1_int), + .fmcp_qsfp2_tx_rst_1(fmcp_qsfp2_tx_rst_1_int), + .fmcp_qsfp2_txd_1(fmcp_qsfp2_txd_1_int), + .fmcp_qsfp2_txc_1(fmcp_qsfp2_txc_1_int), + .fmcp_qsfp2_rx_clk_1(fmcp_qsfp2_rx_clk_1_int), + .fmcp_qsfp2_rx_rst_1(fmcp_qsfp2_rx_rst_1_int), + .fmcp_qsfp2_rxd_1(fmcp_qsfp2_rxd_1_int), + .fmcp_qsfp2_rxc_1(fmcp_qsfp2_rxc_1_int), + .fmcp_qsfp2_tx_clk_2(fmcp_qsfp2_tx_clk_2_int), + .fmcp_qsfp2_tx_rst_2(fmcp_qsfp2_tx_rst_2_int), + .fmcp_qsfp2_txd_2(fmcp_qsfp2_txd_2_int), + .fmcp_qsfp2_txc_2(fmcp_qsfp2_txc_2_int), + .fmcp_qsfp2_rx_clk_2(fmcp_qsfp2_rx_clk_2_int), + .fmcp_qsfp2_rx_rst_2(fmcp_qsfp2_rx_rst_2_int), + .fmcp_qsfp2_rxd_2(fmcp_qsfp2_rxd_2_int), + .fmcp_qsfp2_rxc_2(fmcp_qsfp2_rxc_2_int), + .fmcp_qsfp2_tx_clk_3(fmcp_qsfp2_tx_clk_3_int), + .fmcp_qsfp2_tx_rst_3(fmcp_qsfp2_tx_rst_3_int), + .fmcp_qsfp2_txd_3(fmcp_qsfp2_txd_3_int), + .fmcp_qsfp2_txc_3(fmcp_qsfp2_txc_3_int), + .fmcp_qsfp2_rx_clk_3(fmcp_qsfp2_rx_clk_3_int), + .fmcp_qsfp2_rx_rst_3(fmcp_qsfp2_rx_rst_3_int), + .fmcp_qsfp2_rxd_3(fmcp_qsfp2_rxd_3_int), + .fmcp_qsfp2_rxc_3(fmcp_qsfp2_rxc_3_int), + .fmcp_qsfp2_tx_clk_4(fmcp_qsfp2_tx_clk_4_int), + .fmcp_qsfp2_tx_rst_4(fmcp_qsfp2_tx_rst_4_int), + .fmcp_qsfp2_txd_4(fmcp_qsfp2_txd_4_int), + .fmcp_qsfp2_txc_4(fmcp_qsfp2_txc_4_int), + .fmcp_qsfp2_rx_clk_4(fmcp_qsfp2_rx_clk_4_int), + .fmcp_qsfp2_rx_rst_4(fmcp_qsfp2_rx_rst_4_int), + .fmcp_qsfp2_rxd_4(fmcp_qsfp2_rxd_4_int), + .fmcp_qsfp2_rxc_4(fmcp_qsfp2_rxc_4_int), + .fmcp_qsfp3_tx_clk_1(fmcp_qsfp3_tx_clk_1_int), + .fmcp_qsfp3_tx_rst_1(fmcp_qsfp3_tx_rst_1_int), + .fmcp_qsfp3_txd_1(fmcp_qsfp3_txd_1_int), + .fmcp_qsfp3_txc_1(fmcp_qsfp3_txc_1_int), + .fmcp_qsfp3_rx_clk_1(fmcp_qsfp3_rx_clk_1_int), + .fmcp_qsfp3_rx_rst_1(fmcp_qsfp3_rx_rst_1_int), + .fmcp_qsfp3_rxd_1(fmcp_qsfp3_rxd_1_int), + .fmcp_qsfp3_rxc_1(fmcp_qsfp3_rxc_1_int), + .fmcp_qsfp3_tx_clk_2(fmcp_qsfp3_tx_clk_2_int), + .fmcp_qsfp3_tx_rst_2(fmcp_qsfp3_tx_rst_2_int), + .fmcp_qsfp3_txd_2(fmcp_qsfp3_txd_2_int), + .fmcp_qsfp3_txc_2(fmcp_qsfp3_txc_2_int), + .fmcp_qsfp3_rx_clk_2(fmcp_qsfp3_rx_clk_2_int), + .fmcp_qsfp3_rx_rst_2(fmcp_qsfp3_rx_rst_2_int), + .fmcp_qsfp3_rxd_2(fmcp_qsfp3_rxd_2_int), + .fmcp_qsfp3_rxc_2(fmcp_qsfp3_rxc_2_int), + .fmcp_qsfp3_tx_clk_3(fmcp_qsfp3_tx_clk_3_int), + .fmcp_qsfp3_tx_rst_3(fmcp_qsfp3_tx_rst_3_int), + .fmcp_qsfp3_txd_3(fmcp_qsfp3_txd_3_int), + .fmcp_qsfp3_txc_3(fmcp_qsfp3_txc_3_int), + .fmcp_qsfp3_rx_clk_3(fmcp_qsfp3_rx_clk_3_int), + .fmcp_qsfp3_rx_rst_3(fmcp_qsfp3_rx_rst_3_int), + .fmcp_qsfp3_rxd_3(fmcp_qsfp3_rxd_3_int), + .fmcp_qsfp3_rxc_3(fmcp_qsfp3_rxc_3_int), + .fmcp_qsfp3_tx_clk_4(fmcp_qsfp3_tx_clk_4_int), + .fmcp_qsfp3_tx_rst_4(fmcp_qsfp3_tx_rst_4_int), + .fmcp_qsfp3_txd_4(fmcp_qsfp3_txd_4_int), + .fmcp_qsfp3_txc_4(fmcp_qsfp3_txc_4_int), + .fmcp_qsfp3_rx_clk_4(fmcp_qsfp3_rx_clk_4_int), + .fmcp_qsfp3_rx_rst_4(fmcp_qsfp3_rx_rst_4_int), + .fmcp_qsfp3_rxd_4(fmcp_qsfp3_rxd_4_int), + .fmcp_qsfp3_rxc_4(fmcp_qsfp3_rxc_4_int), + .fmcp_qsfp4_tx_clk_1(fmcp_qsfp4_tx_clk_1_int), + .fmcp_qsfp4_tx_rst_1(fmcp_qsfp4_tx_rst_1_int), + .fmcp_qsfp4_txd_1(fmcp_qsfp4_txd_1_int), + .fmcp_qsfp4_txc_1(fmcp_qsfp4_txc_1_int), + .fmcp_qsfp4_rx_clk_1(fmcp_qsfp4_rx_clk_1_int), + .fmcp_qsfp4_rx_rst_1(fmcp_qsfp4_rx_rst_1_int), + .fmcp_qsfp4_rxd_1(fmcp_qsfp4_rxd_1_int), + .fmcp_qsfp4_rxc_1(fmcp_qsfp4_rxc_1_int), + .fmcp_qsfp4_tx_clk_2(fmcp_qsfp4_tx_clk_2_int), + .fmcp_qsfp4_tx_rst_2(fmcp_qsfp4_tx_rst_2_int), + .fmcp_qsfp4_txd_2(fmcp_qsfp4_txd_2_int), + .fmcp_qsfp4_txc_2(fmcp_qsfp4_txc_2_int), + .fmcp_qsfp4_rx_clk_2(fmcp_qsfp4_rx_clk_2_int), + .fmcp_qsfp4_rx_rst_2(fmcp_qsfp4_rx_rst_2_int), + .fmcp_qsfp4_rxd_2(fmcp_qsfp4_rxd_2_int), + .fmcp_qsfp4_rxc_2(fmcp_qsfp4_rxc_2_int), + .fmcp_qsfp4_tx_clk_3(fmcp_qsfp4_tx_clk_3_int), + .fmcp_qsfp4_tx_rst_3(fmcp_qsfp4_tx_rst_3_int), + .fmcp_qsfp4_txd_3(fmcp_qsfp4_txd_3_int), + .fmcp_qsfp4_txc_3(fmcp_qsfp4_txc_3_int), + .fmcp_qsfp4_rx_clk_3(fmcp_qsfp4_rx_clk_3_int), + .fmcp_qsfp4_rx_rst_3(fmcp_qsfp4_rx_rst_3_int), + .fmcp_qsfp4_rxd_3(fmcp_qsfp4_rxd_3_int), + .fmcp_qsfp4_rxc_3(fmcp_qsfp4_rxc_3_int), + .fmcp_qsfp4_tx_clk_4(fmcp_qsfp4_tx_clk_4_int), + .fmcp_qsfp4_tx_rst_4(fmcp_qsfp4_tx_rst_4_int), + .fmcp_qsfp4_txd_4(fmcp_qsfp4_txd_4_int), + .fmcp_qsfp4_txc_4(fmcp_qsfp4_txc_4_int), + .fmcp_qsfp4_rx_clk_4(fmcp_qsfp4_rx_clk_4_int), + .fmcp_qsfp4_rx_rst_4(fmcp_qsfp4_rx_rst_4_int), + .fmcp_qsfp4_rxd_4(fmcp_qsfp4_rxd_4_int), + .fmcp_qsfp4_rxc_4(fmcp_qsfp4_rxc_4_int), + .fmcp_qsfp5_tx_clk_1(fmcp_qsfp5_tx_clk_1_int), + .fmcp_qsfp5_tx_rst_1(fmcp_qsfp5_tx_rst_1_int), + .fmcp_qsfp5_txd_1(fmcp_qsfp5_txd_1_int), + .fmcp_qsfp5_txc_1(fmcp_qsfp5_txc_1_int), + .fmcp_qsfp5_rx_clk_1(fmcp_qsfp5_rx_clk_1_int), + .fmcp_qsfp5_rx_rst_1(fmcp_qsfp5_rx_rst_1_int), + .fmcp_qsfp5_rxd_1(fmcp_qsfp5_rxd_1_int), + .fmcp_qsfp5_rxc_1(fmcp_qsfp5_rxc_1_int), + .fmcp_qsfp5_tx_clk_2(fmcp_qsfp5_tx_clk_2_int), + .fmcp_qsfp5_tx_rst_2(fmcp_qsfp5_tx_rst_2_int), + .fmcp_qsfp5_txd_2(fmcp_qsfp5_txd_2_int), + .fmcp_qsfp5_txc_2(fmcp_qsfp5_txc_2_int), + .fmcp_qsfp5_rx_clk_2(fmcp_qsfp5_rx_clk_2_int), + .fmcp_qsfp5_rx_rst_2(fmcp_qsfp5_rx_rst_2_int), + .fmcp_qsfp5_rxd_2(fmcp_qsfp5_rxd_2_int), + .fmcp_qsfp5_rxc_2(fmcp_qsfp5_rxc_2_int), + .fmcp_qsfp5_tx_clk_3(fmcp_qsfp5_tx_clk_3_int), + .fmcp_qsfp5_tx_rst_3(fmcp_qsfp5_tx_rst_3_int), + .fmcp_qsfp5_txd_3(fmcp_qsfp5_txd_3_int), + .fmcp_qsfp5_txc_3(fmcp_qsfp5_txc_3_int), + .fmcp_qsfp5_rx_clk_3(fmcp_qsfp5_rx_clk_3_int), + .fmcp_qsfp5_rx_rst_3(fmcp_qsfp5_rx_rst_3_int), + .fmcp_qsfp5_rxd_3(fmcp_qsfp5_rxd_3_int), + .fmcp_qsfp5_rxc_3(fmcp_qsfp5_rxc_3_int), + .fmcp_qsfp5_tx_clk_4(fmcp_qsfp5_tx_clk_4_int), + .fmcp_qsfp5_tx_rst_4(fmcp_qsfp5_tx_rst_4_int), + .fmcp_qsfp5_txd_4(fmcp_qsfp5_txd_4_int), + .fmcp_qsfp5_txc_4(fmcp_qsfp5_txc_4_int), + .fmcp_qsfp5_rx_clk_4(fmcp_qsfp5_rx_clk_4_int), + .fmcp_qsfp5_rx_rst_4(fmcp_qsfp5_rx_rst_4_int), + .fmcp_qsfp5_rxd_4(fmcp_qsfp5_rxd_4_int), + .fmcp_qsfp5_rxc_4(fmcp_qsfp5_rxc_4_int), + .fmcp_qsfp6_tx_clk_1(fmcp_qsfp6_tx_clk_1_int), + .fmcp_qsfp6_tx_rst_1(fmcp_qsfp6_tx_rst_1_int), + .fmcp_qsfp6_txd_1(fmcp_qsfp6_txd_1_int), + .fmcp_qsfp6_txc_1(fmcp_qsfp6_txc_1_int), + .fmcp_qsfp6_rx_clk_1(fmcp_qsfp6_rx_clk_1_int), + .fmcp_qsfp6_rx_rst_1(fmcp_qsfp6_rx_rst_1_int), + .fmcp_qsfp6_rxd_1(fmcp_qsfp6_rxd_1_int), + .fmcp_qsfp6_rxc_1(fmcp_qsfp6_rxc_1_int), + .fmcp_qsfp6_tx_clk_2(fmcp_qsfp6_tx_clk_2_int), + .fmcp_qsfp6_tx_rst_2(fmcp_qsfp6_tx_rst_2_int), + .fmcp_qsfp6_txd_2(fmcp_qsfp6_txd_2_int), + .fmcp_qsfp6_txc_2(fmcp_qsfp6_txc_2_int), + .fmcp_qsfp6_rx_clk_2(fmcp_qsfp6_rx_clk_2_int), + .fmcp_qsfp6_rx_rst_2(fmcp_qsfp6_rx_rst_2_int), + .fmcp_qsfp6_rxd_2(fmcp_qsfp6_rxd_2_int), + .fmcp_qsfp6_rxc_2(fmcp_qsfp6_rxc_2_int), + .fmcp_qsfp6_tx_clk_3(fmcp_qsfp6_tx_clk_3_int), + .fmcp_qsfp6_tx_rst_3(fmcp_qsfp6_tx_rst_3_int), + .fmcp_qsfp6_txd_3(fmcp_qsfp6_txd_3_int), + .fmcp_qsfp6_txc_3(fmcp_qsfp6_txc_3_int), + .fmcp_qsfp6_rx_clk_3(fmcp_qsfp6_rx_clk_3_int), + .fmcp_qsfp6_rx_rst_3(fmcp_qsfp6_rx_rst_3_int), + .fmcp_qsfp6_rxd_3(fmcp_qsfp6_rxd_3_int), + .fmcp_qsfp6_rxc_3(fmcp_qsfp6_rxc_3_int), + .fmcp_qsfp6_tx_clk_4(fmcp_qsfp6_tx_clk_4_int), + .fmcp_qsfp6_tx_rst_4(fmcp_qsfp6_tx_rst_4_int), + .fmcp_qsfp6_txd_4(fmcp_qsfp6_txd_4_int), + .fmcp_qsfp6_txc_4(fmcp_qsfp6_txc_4_int), + .fmcp_qsfp6_rx_clk_4(fmcp_qsfp6_rx_clk_4_int), + .fmcp_qsfp6_rx_rst_4(fmcp_qsfp6_rx_rst_4_int), + .fmcp_qsfp6_rxd_4(fmcp_qsfp6_rxd_4_int), + .fmcp_qsfp6_rxc_4(fmcp_qsfp6_rxc_4_int), + /* + * Ethernet: 1000BASE-T SGMII + */ + .phy_gmii_clk(phy_gmii_clk_int), + .phy_gmii_rst(phy_gmii_rst_int), + .phy_gmii_clk_en(phy_gmii_clk_en_int), + .phy_gmii_rxd(phy_gmii_rxd_int), + .phy_gmii_rx_dv(phy_gmii_rx_dv_int), + .phy_gmii_rx_er(phy_gmii_rx_er_int), + .phy_gmii_txd(phy_gmii_txd_int), + .phy_gmii_tx_en(phy_gmii_tx_en_int), + .phy_gmii_tx_er(phy_gmii_tx_er_int), + .phy_reset_n(phy_reset_n), + .phy_int_n(phy_int_n), + /* + * UART: 115200 bps, 8N1 + */ + .uart_rxd(uart_rxd_int), + .uart_txd(uart_txd), + .uart_rts(uart_rts), + .uart_cts(uart_cts_int) +); + +endmodule + +`resetall diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/rtl/fpga_core.v b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v similarity index 73% rename from fpga/lib/eth/example/VCU118/fpga_10g/rtl/fpga_core.v rename to fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v index d796f0cab..6d5e2beba 100644 --- a/fpga/lib/eth/example/VCU118/fpga_10g/rtl/fpga_core.v +++ b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2014-2021 Alex Forencich +Copyright (c) 2014-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -37,7 +37,7 @@ module fpga_core # ) ( /* - * Clock: 156.25MHz + * Clock: 390.625 MHz * Synchronous reset */ input wire clk, @@ -122,6 +122,202 @@ module fpga_core # input wire [63:0] qsfp2_rxd_4, input wire [7:0] qsfp2_rxc_4, + /* + * Ethernet: QSFP28 via HTG 6x QSFP28 FMC+ adapter + */ + input wire fmcp_qsfp1_tx_clk_1, + input wire fmcp_qsfp1_tx_rst_1, + output wire [63:0] fmcp_qsfp1_txd_1, + output wire [7:0] fmcp_qsfp1_txc_1, + input wire fmcp_qsfp1_rx_clk_1, + input wire fmcp_qsfp1_rx_rst_1, + input wire [63:0] fmcp_qsfp1_rxd_1, + input wire [7:0] fmcp_qsfp1_rxc_1, + input wire fmcp_qsfp1_tx_clk_2, + input wire fmcp_qsfp1_tx_rst_2, + output wire [63:0] fmcp_qsfp1_txd_2, + output wire [7:0] fmcp_qsfp1_txc_2, + input wire fmcp_qsfp1_rx_clk_2, + input wire fmcp_qsfp1_rx_rst_2, + input wire [63:0] fmcp_qsfp1_rxd_2, + input wire [7:0] fmcp_qsfp1_rxc_2, + input wire fmcp_qsfp1_tx_clk_3, + input wire fmcp_qsfp1_tx_rst_3, + output wire [63:0] fmcp_qsfp1_txd_3, + output wire [7:0] fmcp_qsfp1_txc_3, + input wire fmcp_qsfp1_rx_clk_3, + input wire fmcp_qsfp1_rx_rst_3, + input wire [63:0] fmcp_qsfp1_rxd_3, + input wire [7:0] fmcp_qsfp1_rxc_3, + input wire fmcp_qsfp1_tx_clk_4, + input wire fmcp_qsfp1_tx_rst_4, + output wire [63:0] fmcp_qsfp1_txd_4, + output wire [7:0] fmcp_qsfp1_txc_4, + input wire fmcp_qsfp1_rx_clk_4, + input wire fmcp_qsfp1_rx_rst_4, + input wire [63:0] fmcp_qsfp1_rxd_4, + input wire [7:0] fmcp_qsfp1_rxc_4, + input wire fmcp_qsfp2_tx_clk_1, + input wire fmcp_qsfp2_tx_rst_1, + output wire [63:0] fmcp_qsfp2_txd_1, + output wire [7:0] fmcp_qsfp2_txc_1, + input wire fmcp_qsfp2_rx_clk_1, + input wire fmcp_qsfp2_rx_rst_1, + input wire [63:0] fmcp_qsfp2_rxd_1, + input wire [7:0] fmcp_qsfp2_rxc_1, + input wire fmcp_qsfp2_tx_clk_2, + input wire fmcp_qsfp2_tx_rst_2, + output wire [63:0] fmcp_qsfp2_txd_2, + output wire [7:0] fmcp_qsfp2_txc_2, + input wire fmcp_qsfp2_rx_clk_2, + input wire fmcp_qsfp2_rx_rst_2, + input wire [63:0] fmcp_qsfp2_rxd_2, + input wire [7:0] fmcp_qsfp2_rxc_2, + input wire fmcp_qsfp2_tx_clk_3, + input wire fmcp_qsfp2_tx_rst_3, + output wire [63:0] fmcp_qsfp2_txd_3, + output wire [7:0] fmcp_qsfp2_txc_3, + input wire fmcp_qsfp2_rx_clk_3, + input wire fmcp_qsfp2_rx_rst_3, + input wire [63:0] fmcp_qsfp2_rxd_3, + input wire [7:0] fmcp_qsfp2_rxc_3, + input wire fmcp_qsfp2_tx_clk_4, + input wire fmcp_qsfp2_tx_rst_4, + output wire [63:0] fmcp_qsfp2_txd_4, + output wire [7:0] fmcp_qsfp2_txc_4, + input wire fmcp_qsfp2_rx_clk_4, + input wire fmcp_qsfp2_rx_rst_4, + input wire [63:0] fmcp_qsfp2_rxd_4, + input wire [7:0] fmcp_qsfp2_rxc_4, + input wire fmcp_qsfp3_tx_clk_1, + input wire fmcp_qsfp3_tx_rst_1, + output wire [63:0] fmcp_qsfp3_txd_1, + output wire [7:0] fmcp_qsfp3_txc_1, + input wire fmcp_qsfp3_rx_clk_1, + input wire fmcp_qsfp3_rx_rst_1, + input wire [63:0] fmcp_qsfp3_rxd_1, + input wire [7:0] fmcp_qsfp3_rxc_1, + input wire fmcp_qsfp3_tx_clk_2, + input wire fmcp_qsfp3_tx_rst_2, + output wire [63:0] fmcp_qsfp3_txd_2, + output wire [7:0] fmcp_qsfp3_txc_2, + input wire fmcp_qsfp3_rx_clk_2, + input wire fmcp_qsfp3_rx_rst_2, + input wire [63:0] fmcp_qsfp3_rxd_2, + input wire [7:0] fmcp_qsfp3_rxc_2, + input wire fmcp_qsfp3_tx_clk_3, + input wire fmcp_qsfp3_tx_rst_3, + output wire [63:0] fmcp_qsfp3_txd_3, + output wire [7:0] fmcp_qsfp3_txc_3, + input wire fmcp_qsfp3_rx_clk_3, + input wire fmcp_qsfp3_rx_rst_3, + input wire [63:0] fmcp_qsfp3_rxd_3, + input wire [7:0] fmcp_qsfp3_rxc_3, + input wire fmcp_qsfp3_tx_clk_4, + input wire fmcp_qsfp3_tx_rst_4, + output wire [63:0] fmcp_qsfp3_txd_4, + output wire [7:0] fmcp_qsfp3_txc_4, + input wire fmcp_qsfp3_rx_clk_4, + input wire fmcp_qsfp3_rx_rst_4, + input wire [63:0] fmcp_qsfp3_rxd_4, + input wire [7:0] fmcp_qsfp3_rxc_4, + input wire fmcp_qsfp4_tx_clk_1, + input wire fmcp_qsfp4_tx_rst_1, + output wire [63:0] fmcp_qsfp4_txd_1, + output wire [7:0] fmcp_qsfp4_txc_1, + input wire fmcp_qsfp4_rx_clk_1, + input wire fmcp_qsfp4_rx_rst_1, + input wire [63:0] fmcp_qsfp4_rxd_1, + input wire [7:0] fmcp_qsfp4_rxc_1, + input wire fmcp_qsfp4_tx_clk_2, + input wire fmcp_qsfp4_tx_rst_2, + output wire [63:0] fmcp_qsfp4_txd_2, + output wire [7:0] fmcp_qsfp4_txc_2, + input wire fmcp_qsfp4_rx_clk_2, + input wire fmcp_qsfp4_rx_rst_2, + input wire [63:0] fmcp_qsfp4_rxd_2, + input wire [7:0] fmcp_qsfp4_rxc_2, + input wire fmcp_qsfp4_tx_clk_3, + input wire fmcp_qsfp4_tx_rst_3, + output wire [63:0] fmcp_qsfp4_txd_3, + output wire [7:0] fmcp_qsfp4_txc_3, + input wire fmcp_qsfp4_rx_clk_3, + input wire fmcp_qsfp4_rx_rst_3, + input wire [63:0] fmcp_qsfp4_rxd_3, + input wire [7:0] fmcp_qsfp4_rxc_3, + input wire fmcp_qsfp4_tx_clk_4, + input wire fmcp_qsfp4_tx_rst_4, + output wire [63:0] fmcp_qsfp4_txd_4, + output wire [7:0] fmcp_qsfp4_txc_4, + input wire fmcp_qsfp4_rx_clk_4, + input wire fmcp_qsfp4_rx_rst_4, + input wire [63:0] fmcp_qsfp4_rxd_4, + input wire [7:0] fmcp_qsfp4_rxc_4, + input wire fmcp_qsfp5_tx_clk_1, + input wire fmcp_qsfp5_tx_rst_1, + output wire [63:0] fmcp_qsfp5_txd_1, + output wire [7:0] fmcp_qsfp5_txc_1, + input wire fmcp_qsfp5_rx_clk_1, + input wire fmcp_qsfp5_rx_rst_1, + input wire [63:0] fmcp_qsfp5_rxd_1, + input wire [7:0] fmcp_qsfp5_rxc_1, + input wire fmcp_qsfp5_tx_clk_2, + input wire fmcp_qsfp5_tx_rst_2, + output wire [63:0] fmcp_qsfp5_txd_2, + output wire [7:0] fmcp_qsfp5_txc_2, + input wire fmcp_qsfp5_rx_clk_2, + input wire fmcp_qsfp5_rx_rst_2, + input wire [63:0] fmcp_qsfp5_rxd_2, + input wire [7:0] fmcp_qsfp5_rxc_2, + input wire fmcp_qsfp5_tx_clk_3, + input wire fmcp_qsfp5_tx_rst_3, + output wire [63:0] fmcp_qsfp5_txd_3, + output wire [7:0] fmcp_qsfp5_txc_3, + input wire fmcp_qsfp5_rx_clk_3, + input wire fmcp_qsfp5_rx_rst_3, + input wire [63:0] fmcp_qsfp5_rxd_3, + input wire [7:0] fmcp_qsfp5_rxc_3, + input wire fmcp_qsfp5_tx_clk_4, + input wire fmcp_qsfp5_tx_rst_4, + output wire [63:0] fmcp_qsfp5_txd_4, + output wire [7:0] fmcp_qsfp5_txc_4, + input wire fmcp_qsfp5_rx_clk_4, + input wire fmcp_qsfp5_rx_rst_4, + input wire [63:0] fmcp_qsfp5_rxd_4, + input wire [7:0] fmcp_qsfp5_rxc_4, + input wire fmcp_qsfp6_tx_clk_1, + input wire fmcp_qsfp6_tx_rst_1, + output wire [63:0] fmcp_qsfp6_txd_1, + output wire [7:0] fmcp_qsfp6_txc_1, + input wire fmcp_qsfp6_rx_clk_1, + input wire fmcp_qsfp6_rx_rst_1, + input wire [63:0] fmcp_qsfp6_rxd_1, + input wire [7:0] fmcp_qsfp6_rxc_1, + input wire fmcp_qsfp6_tx_clk_2, + input wire fmcp_qsfp6_tx_rst_2, + output wire [63:0] fmcp_qsfp6_txd_2, + output wire [7:0] fmcp_qsfp6_txc_2, + input wire fmcp_qsfp6_rx_clk_2, + input wire fmcp_qsfp6_rx_rst_2, + input wire [63:0] fmcp_qsfp6_rxd_2, + input wire [7:0] fmcp_qsfp6_rxc_2, + input wire fmcp_qsfp6_tx_clk_3, + input wire fmcp_qsfp6_tx_rst_3, + output wire [63:0] fmcp_qsfp6_txd_3, + output wire [7:0] fmcp_qsfp6_txc_3, + input wire fmcp_qsfp6_rx_clk_3, + input wire fmcp_qsfp6_rx_rst_3, + input wire [63:0] fmcp_qsfp6_rxd_3, + input wire [7:0] fmcp_qsfp6_rxc_3, + input wire fmcp_qsfp6_tx_clk_4, + input wire fmcp_qsfp6_tx_rst_4, + output wire [63:0] fmcp_qsfp6_txd_4, + output wire [7:0] fmcp_qsfp6_txc_4, + input wire fmcp_qsfp6_rx_clk_4, + input wire fmcp_qsfp6_rx_rst_4, + input wire [63:0] fmcp_qsfp6_rxd_4, + input wire [7:0] fmcp_qsfp6_rxc_4, + /* * Ethernet: 1000BASE-T SGMII */ @@ -414,6 +610,60 @@ assign qsfp2_txc_3 = 8'hff; assign qsfp2_txd_4 = 64'h0707070707070707; assign qsfp2_txc_4 = 8'hff; +assign fmcp_qsfp1_txd_1 = 64'h0707070707070707; +assign fmcp_qsfp1_txc_1 = 8'hff; +assign fmcp_qsfp1_txd_2 = 64'h0707070707070707; +assign fmcp_qsfp1_txc_2 = 8'hff; +assign fmcp_qsfp1_txd_3 = 64'h0707070707070707; +assign fmcp_qsfp1_txc_3 = 8'hff; +assign fmcp_qsfp1_txd_4 = 64'h0707070707070707; +assign fmcp_qsfp1_txc_4 = 8'hff; + +assign fmcp_qsfp2_txd_1 = 64'h0707070707070707; +assign fmcp_qsfp2_txc_1 = 8'hff; +assign fmcp_qsfp2_txd_2 = 64'h0707070707070707; +assign fmcp_qsfp2_txc_2 = 8'hff; +assign fmcp_qsfp2_txd_3 = 64'h0707070707070707; +assign fmcp_qsfp2_txc_3 = 8'hff; +assign fmcp_qsfp2_txd_4 = 64'h0707070707070707; +assign fmcp_qsfp2_txc_4 = 8'hff; + +assign fmcp_qsfp3_txd_1 = 64'h0707070707070707; +assign fmcp_qsfp3_txc_1 = 8'hff; +assign fmcp_qsfp3_txd_2 = 64'h0707070707070707; +assign fmcp_qsfp3_txc_2 = 8'hff; +assign fmcp_qsfp3_txd_3 = 64'h0707070707070707; +assign fmcp_qsfp3_txc_3 = 8'hff; +assign fmcp_qsfp3_txd_4 = 64'h0707070707070707; +assign fmcp_qsfp3_txc_4 = 8'hff; + +assign fmcp_qsfp4_txd_1 = 64'h0707070707070707; +assign fmcp_qsfp4_txc_1 = 8'hff; +assign fmcp_qsfp4_txd_2 = 64'h0707070707070707; +assign fmcp_qsfp4_txc_2 = 8'hff; +assign fmcp_qsfp4_txd_3 = 64'h0707070707070707; +assign fmcp_qsfp4_txc_3 = 8'hff; +assign fmcp_qsfp4_txd_4 = 64'h0707070707070707; +assign fmcp_qsfp4_txc_4 = 8'hff; + +assign fmcp_qsfp5_txd_1 = 64'h0707070707070707; +assign fmcp_qsfp5_txc_1 = 8'hff; +assign fmcp_qsfp5_txd_2 = 64'h0707070707070707; +assign fmcp_qsfp5_txc_2 = 8'hff; +assign fmcp_qsfp5_txd_3 = 64'h0707070707070707; +assign fmcp_qsfp5_txc_3 = 8'hff; +assign fmcp_qsfp5_txd_4 = 64'h0707070707070707; +assign fmcp_qsfp5_txc_4 = 8'hff; + +assign fmcp_qsfp6_txd_1 = 64'h0707070707070707; +assign fmcp_qsfp6_txc_1 = 8'hff; +assign fmcp_qsfp6_txd_2 = 64'h0707070707070707; +assign fmcp_qsfp6_txc_2 = 8'hff; +assign fmcp_qsfp6_txd_3 = 64'h0707070707070707; +assign fmcp_qsfp6_txc_3 = 8'hff; +assign fmcp_qsfp6_txd_4 = 64'h0707070707070707; +assign fmcp_qsfp6_txc_4 = 8'hff; + eth_mac_10g_fifo #( .ENABLE_PADDING(1), .ENABLE_DIC(1), diff --git a/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/i2c_master.v b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/i2c_master.v new file mode 100644 index 000000000..b933316a1 --- /dev/null +++ b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/i2c_master.v @@ -0,0 +1,901 @@ +/* + +Copyright (c) 2015-2017 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * I2C master + */ +module i2c_master ( + input wire clk, + input wire rst, + + /* + * Host interface + */ + input wire [6:0] s_axis_cmd_address, + input wire s_axis_cmd_start, + input wire s_axis_cmd_read, + input wire s_axis_cmd_write, + input wire s_axis_cmd_write_multiple, + input wire s_axis_cmd_stop, + input wire s_axis_cmd_valid, + output wire s_axis_cmd_ready, + + input wire [7:0] s_axis_data_tdata, + input wire s_axis_data_tvalid, + output wire s_axis_data_tready, + input wire s_axis_data_tlast, + + output wire [7:0] m_axis_data_tdata, + output wire m_axis_data_tvalid, + input wire m_axis_data_tready, + output wire m_axis_data_tlast, + + /* + * I2C interface + */ + input wire scl_i, + output wire scl_o, + output wire scl_t, + input wire sda_i, + output wire sda_o, + output wire sda_t, + + /* + * Status + */ + output wire busy, + output wire bus_control, + output wire bus_active, + output wire missed_ack, + + /* + * Configuration + */ + input wire [15:0] prescale, + input wire stop_on_idle +); + +/* + +I2C + +Read + __ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __ +sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_\_R___A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A____/ + ____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____ +scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP + +Write + __ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __ +sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_/ W \_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_/ N \__/ + ____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____ +scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP + +Commands: + +read + read data byte + set start to force generation of a start condition + start is implied when bus is inactive or active with write or different address + set stop to issue a stop condition after reading current byte + if stop is set with read command, then m_axis_data_tlast will be set + +write + write data byte + set start to force generation of a start condition + start is implied when bus is inactive or active with read or different address + set stop to issue a stop condition after writing current byte + +write multiple + write multiple data bytes (until s_axis_data_tlast) + set start to force generation of a start condition + start is implied when bus is inactive or active with read or different address + set stop to issue a stop condition after writing block + +stop + issue stop condition if bus is active + +Status: + +busy + module is communicating over the bus + +bus_control + module has control of bus in active state + +bus_active + bus is active, not necessarily controlled by this module + +missed_ack + strobed when a slave ack is missed + +Parameters: + +prescale + set prescale to 1/4 of the minimum clock period in units + of input clk cycles (prescale = Fclk / (FI2Cclk * 4)) + +stop_on_idle + automatically issue stop when command input is not valid + +Example of interfacing with tristate pins: +(this will work for any tristate bus) + +assign scl_i = scl_pin; +assign scl_pin = scl_t ? 1'bz : scl_o; +assign sda_i = sda_pin; +assign sda_pin = sda_t ? 1'bz : sda_o; + +Equivalent code that does not use *_t connections: +(we can get away with this because I2C is open-drain) + +assign scl_i = scl_pin; +assign scl_pin = scl_o ? 1'bz : 1'b0; +assign sda_i = sda_pin; +assign sda_pin = sda_o ? 1'bz : 1'b0; + +Example of two interconnected I2C devices: + +assign scl_1_i = scl_1_o & scl_2_o; +assign scl_2_i = scl_1_o & scl_2_o; +assign sda_1_i = sda_1_o & sda_2_o; +assign sda_2_i = sda_1_o & sda_2_o; + +Example of two I2C devices sharing the same pins: + +assign scl_1_i = scl_pin; +assign scl_2_i = scl_pin; +assign scl_pin = (scl_1_o & scl_2_o) ? 1'bz : 1'b0; +assign sda_1_i = sda_pin; +assign sda_2_i = sda_pin; +assign sda_pin = (sda_1_o & sda_2_o) ? 1'bz : 1'b0; + +Notes: + +scl_o should not be connected directly to scl_i, only via AND logic or a tristate +I/O pin. This would prevent devices from stretching the clock period. + +*/ + +localparam [4:0] + STATE_IDLE = 4'd0, + STATE_ACTIVE_WRITE = 4'd1, + STATE_ACTIVE_READ = 4'd2, + STATE_START_WAIT = 4'd3, + STATE_START = 4'd4, + STATE_ADDRESS_1 = 4'd5, + STATE_ADDRESS_2 = 4'd6, + STATE_WRITE_1 = 4'd7, + STATE_WRITE_2 = 4'd8, + STATE_WRITE_3 = 4'd9, + STATE_READ = 4'd10, + STATE_STOP = 4'd11; + +reg [4:0] state_reg = STATE_IDLE, state_next; + +localparam [4:0] + PHY_STATE_IDLE = 5'd0, + PHY_STATE_ACTIVE = 5'd1, + PHY_STATE_REPEATED_START_1 = 5'd2, + PHY_STATE_REPEATED_START_2 = 5'd3, + PHY_STATE_START_1 = 5'd4, + PHY_STATE_START_2 = 5'd5, + PHY_STATE_WRITE_BIT_1 = 5'd6, + PHY_STATE_WRITE_BIT_2 = 5'd7, + PHY_STATE_WRITE_BIT_3 = 5'd8, + PHY_STATE_READ_BIT_1 = 5'd9, + PHY_STATE_READ_BIT_2 = 5'd10, + PHY_STATE_READ_BIT_3 = 5'd11, + PHY_STATE_READ_BIT_4 = 5'd12, + PHY_STATE_STOP_1 = 5'd13, + PHY_STATE_STOP_2 = 5'd14, + PHY_STATE_STOP_3 = 5'd15; + +reg [4:0] phy_state_reg = STATE_IDLE, phy_state_next; + +reg phy_start_bit; +reg phy_stop_bit; +reg phy_write_bit; +reg phy_read_bit; +reg phy_release_bus; + +reg phy_tx_data; + +reg phy_rx_data_reg = 1'b0, phy_rx_data_next; + +reg [6:0] addr_reg = 7'd0, addr_next; +reg [7:0] data_reg = 8'd0, data_next; +reg last_reg = 1'b0, last_next; + +reg mode_read_reg = 1'b0, mode_read_next; +reg mode_write_multiple_reg = 1'b0, mode_write_multiple_next; +reg mode_stop_reg = 1'b0, mode_stop_next; + +reg [16:0] delay_reg = 16'd0, delay_next; +reg delay_scl_reg = 1'b0, delay_scl_next; +reg delay_sda_reg = 1'b0, delay_sda_next; + +reg [3:0] bit_count_reg = 4'd0, bit_count_next; + +reg s_axis_cmd_ready_reg = 1'b0, s_axis_cmd_ready_next; + +reg s_axis_data_tready_reg = 1'b0, s_axis_data_tready_next; + +reg [7:0] m_axis_data_tdata_reg = 8'd0, m_axis_data_tdata_next; +reg m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next; +reg m_axis_data_tlast_reg = 1'b0, m_axis_data_tlast_next; + +reg scl_i_reg = 1'b1; +reg sda_i_reg = 1'b1; + +reg scl_o_reg = 1'b1, scl_o_next; +reg sda_o_reg = 1'b1, sda_o_next; + +reg last_scl_i_reg = 1'b1; +reg last_sda_i_reg = 1'b1; + +reg busy_reg = 1'b0; +reg bus_active_reg = 1'b0; +reg bus_control_reg = 1'b0, bus_control_next; +reg missed_ack_reg = 1'b0, missed_ack_next; + +assign s_axis_cmd_ready = s_axis_cmd_ready_reg; + +assign s_axis_data_tready = s_axis_data_tready_reg; + +assign m_axis_data_tdata = m_axis_data_tdata_reg; +assign m_axis_data_tvalid = m_axis_data_tvalid_reg; +assign m_axis_data_tlast = m_axis_data_tlast_reg; + +assign scl_o = scl_o_reg; +assign scl_t = scl_o_reg; +assign sda_o = sda_o_reg; +assign sda_t = sda_o_reg; + +assign busy = busy_reg; +assign bus_active = bus_active_reg; +assign bus_control = bus_control_reg; +assign missed_ack = missed_ack_reg; + +wire scl_posedge = scl_i_reg & ~last_scl_i_reg; +wire scl_negedge = ~scl_i_reg & last_scl_i_reg; +wire sda_posedge = sda_i_reg & ~last_sda_i_reg; +wire sda_negedge = ~sda_i_reg & last_sda_i_reg; + +wire start_bit = sda_negedge & scl_i_reg; +wire stop_bit = sda_posedge & scl_i_reg; + +always @* begin + state_next = STATE_IDLE; + + phy_start_bit = 1'b0; + phy_stop_bit = 1'b0; + phy_write_bit = 1'b0; + phy_read_bit = 1'b0; + phy_tx_data = 1'b0; + phy_release_bus = 1'b0; + + addr_next = addr_reg; + data_next = data_reg; + last_next = last_reg; + + mode_read_next = mode_read_reg; + mode_write_multiple_next = mode_write_multiple_reg; + mode_stop_next = mode_stop_reg; + + bit_count_next = bit_count_reg; + + s_axis_cmd_ready_next = 1'b0; + + s_axis_data_tready_next = 1'b0; + + m_axis_data_tdata_next = m_axis_data_tdata_reg; + m_axis_data_tvalid_next = m_axis_data_tvalid_reg & ~m_axis_data_tready; + m_axis_data_tlast_next = m_axis_data_tlast_reg; + + missed_ack_next = 1'b0; + + // generate delays + if (phy_state_reg != PHY_STATE_IDLE && phy_state_reg != PHY_STATE_ACTIVE) begin + // wait for phy operation + state_next = state_reg; + end else begin + // process states + case (state_reg) + STATE_IDLE: begin + // line idle + s_axis_cmd_ready_next = 1'b1; + + if (s_axis_cmd_ready & s_axis_cmd_valid) begin + // command valid + if (s_axis_cmd_read ^ (s_axis_cmd_write | s_axis_cmd_write_multiple)) begin + // read or write command + addr_next = s_axis_cmd_address; + mode_read_next = s_axis_cmd_read; + mode_write_multiple_next = s_axis_cmd_write_multiple; + mode_stop_next = s_axis_cmd_stop; + + s_axis_cmd_ready_next = 1'b0; + + // start bit + if (bus_active) begin + state_next = STATE_START_WAIT; + end else begin + phy_start_bit = 1'b1; + bit_count_next = 4'd8; + state_next = STATE_ADDRESS_1; + end + end else begin + // invalid or unspecified - ignore + state_next = STATE_IDLE; + end + end else begin + state_next = STATE_IDLE; + end + end + STATE_ACTIVE_WRITE: begin + // line active with current address and read/write mode + s_axis_cmd_ready_next = 1'b1; + + if (s_axis_cmd_ready & s_axis_cmd_valid) begin + // command valid + if (s_axis_cmd_read ^ (s_axis_cmd_write | s_axis_cmd_write_multiple)) begin + // read or write command + addr_next = s_axis_cmd_address; + mode_read_next = s_axis_cmd_read; + mode_write_multiple_next = s_axis_cmd_write_multiple; + mode_stop_next = s_axis_cmd_stop; + + s_axis_cmd_ready_next = 1'b0; + + if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_read) begin + // address or mode mismatch or forced start - repeated start + + // repeated start bit + phy_start_bit = 1'b1; + bit_count_next = 4'd8; + state_next = STATE_ADDRESS_1; + end else begin + // address and mode match + + // start write + s_axis_data_tready_next = 1'b1; + state_next = STATE_WRITE_1; + end + end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multiple)) begin + // stop command + phy_stop_bit = 1'b1; + state_next = STATE_IDLE; + end else begin + // invalid or unspecified - ignore + state_next = STATE_ACTIVE_WRITE; + end + end else begin + if (stop_on_idle & s_axis_cmd_ready & ~s_axis_cmd_valid) begin + // no waiting command and stop_on_idle selected, issue stop condition + phy_stop_bit = 1'b1; + state_next = STATE_IDLE; + end else begin + state_next = STATE_ACTIVE_WRITE; + end + end + end + STATE_ACTIVE_READ: begin + // line active to current address + s_axis_cmd_ready_next = ~m_axis_data_tvalid; + + if (s_axis_cmd_ready & s_axis_cmd_valid) begin + // command valid + if (s_axis_cmd_read ^ (s_axis_cmd_write | s_axis_cmd_write_multiple)) begin + // read or write command + addr_next = s_axis_cmd_address; + mode_read_next = s_axis_cmd_read; + mode_write_multiple_next = s_axis_cmd_write_multiple; + mode_stop_next = s_axis_cmd_stop; + + s_axis_cmd_ready_next = 1'b0; + + if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_write) begin + // address or mode mismatch or forced start - repeated start + + // write nack for previous read + phy_write_bit = 1'b1; + phy_tx_data = 1'b1; + // repeated start bit + state_next = STATE_START; + end else begin + // address and mode match + + // write ack for previous read + phy_write_bit = 1'b1; + phy_tx_data = 1'b0; + // start next read + bit_count_next = 4'd8; + data_next = 8'd0; + state_next = STATE_READ; + end + end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multiple)) begin + // stop command + // write nack for previous read + phy_write_bit = 1'b1; + phy_tx_data = 1'b1; + // send stop bit + state_next = STATE_STOP; + end else begin + // invalid or unspecified - ignore + state_next = STATE_ACTIVE_READ; + end + end else begin + if (stop_on_idle & s_axis_cmd_ready & ~s_axis_cmd_valid) begin + // no waiting command and stop_on_idle selected, issue stop condition + // write ack for previous read + phy_write_bit = 1'b1; + phy_tx_data = 1'b1; + // send stop bit + state_next = STATE_STOP; + end else begin + state_next = STATE_ACTIVE_READ; + end + end + end + STATE_START_WAIT: begin + // wait for bus idle + + if (bus_active) begin + state_next = STATE_START_WAIT; + end else begin + // bus is idle, take control + phy_start_bit = 1'b1; + bit_count_next = 4'd8; + state_next = STATE_ADDRESS_1; + end + end + STATE_START: begin + // send start bit + + phy_start_bit = 1'b1; + bit_count_next = 4'd8; + state_next = STATE_ADDRESS_1; + end + STATE_ADDRESS_1: begin + // send address + bit_count_next = bit_count_reg - 1; + if (bit_count_reg > 1) begin + // send address + phy_write_bit = 1'b1; + phy_tx_data = addr_reg[bit_count_reg-2]; + state_next = STATE_ADDRESS_1; + end else if (bit_count_reg > 0) begin + // send read/write bit + phy_write_bit = 1'b1; + phy_tx_data = mode_read_reg; + state_next = STATE_ADDRESS_1; + end else begin + // read ack bit + phy_read_bit = 1'b1; + state_next = STATE_ADDRESS_2; + end + end + STATE_ADDRESS_2: begin + // read ack bit + missed_ack_next = phy_rx_data_reg; + + if (mode_read_reg) begin + // start read + bit_count_next = 4'd8; + data_next = 1'b0; + state_next = STATE_READ; + end else begin + // start write + s_axis_data_tready_next = 1'b1; + state_next = STATE_WRITE_1; + end + end + STATE_WRITE_1: begin + s_axis_data_tready_next = 1'b1; + + if (s_axis_data_tready & s_axis_data_tvalid) begin + // got data, start write + data_next = s_axis_data_tdata; + last_next = s_axis_data_tlast; + bit_count_next = 4'd8; + s_axis_data_tready_next = 1'b0; + state_next = STATE_WRITE_2; + end else begin + // wait for data + state_next = STATE_WRITE_1; + end + end + STATE_WRITE_2: begin + // send data + bit_count_next = bit_count_reg - 1; + if (bit_count_reg > 0) begin + // write data bit + phy_write_bit = 1'b1; + phy_tx_data = data_reg[bit_count_reg-1]; + state_next = STATE_WRITE_2; + end else begin + // read ack bit + phy_read_bit = 1'b1; + state_next = STATE_WRITE_3; + end + end + STATE_WRITE_3: begin + // read ack bit + missed_ack_next = phy_rx_data_reg; + + if (mode_write_multiple_reg && !last_reg) begin + // more to write + state_next = STATE_WRITE_1; + end else if (mode_stop_reg) begin + // last cycle and stop selected + phy_stop_bit = 1'b1; + state_next = STATE_IDLE; + end else begin + // otherwise, return to bus active state + state_next = STATE_ACTIVE_WRITE; + end + end + STATE_READ: begin + // read data + + bit_count_next = bit_count_reg - 1; + data_next = {data_reg[6:0], phy_rx_data_reg}; + if (bit_count_reg > 0) begin + // read next bit + phy_read_bit = 1'b1; + state_next = STATE_READ; + end else begin + // output data word + m_axis_data_tdata_next = data_next; + m_axis_data_tvalid_next = 1'b1; + m_axis_data_tlast_next = 1'b0; + if (mode_stop_reg) begin + // send nack and stop + m_axis_data_tlast_next = 1'b1; + phy_write_bit = 1'b1; + phy_tx_data = 1'b1; + state_next = STATE_STOP; + end else begin + // return to bus active state + state_next = STATE_ACTIVE_READ; + end + end + end + STATE_STOP: begin + // send stop bit + phy_stop_bit = 1'b1; + state_next = STATE_IDLE; + end + endcase + end +end + +always @* begin + phy_state_next = PHY_STATE_IDLE; + + phy_rx_data_next = phy_rx_data_reg; + + delay_next = delay_reg; + delay_scl_next = delay_scl_reg; + delay_sda_next = delay_sda_reg; + + scl_o_next = scl_o_reg; + sda_o_next = sda_o_reg; + + bus_control_next = bus_control_reg; + + if (phy_release_bus) begin + // release bus and return to idle state + sda_o_next = 1'b1; + scl_o_next = 1'b1; + delay_scl_next = 1'b0; + delay_sda_next = 1'b0; + delay_next = 1'b0; + phy_state_next = PHY_STATE_IDLE; + end else if (delay_scl_reg) begin + // wait for SCL to match command + delay_scl_next = scl_o_reg & ~scl_i_reg; + phy_state_next = phy_state_reg; + end else if (delay_sda_reg) begin + // wait for SDA to match command + delay_sda_next = sda_o_reg & ~sda_i_reg; + phy_state_next = phy_state_reg; + end else if (delay_reg > 0) begin + // time delay + delay_next = delay_reg - 1; + phy_state_next = phy_state_reg; + end else begin + case (phy_state_reg) + PHY_STATE_IDLE: begin + // bus idle - wait for start command + sda_o_next = 1'b1; + scl_o_next = 1'b1; + if (phy_start_bit) begin + sda_o_next = 1'b0; + delay_next = prescale; + phy_state_next = PHY_STATE_START_1; + end else begin + phy_state_next = PHY_STATE_IDLE; + end + end + PHY_STATE_ACTIVE: begin + // bus active + if (phy_start_bit) begin + sda_o_next = 1'b1; + delay_next = prescale; + phy_state_next = PHY_STATE_REPEATED_START_1; + end else if (phy_write_bit) begin + sda_o_next = phy_tx_data; + delay_next = prescale; + phy_state_next = PHY_STATE_WRITE_BIT_1; + end else if (phy_read_bit) begin + sda_o_next = 1'b1; + delay_next = prescale; + phy_state_next = PHY_STATE_READ_BIT_1; + end else if (phy_stop_bit) begin + sda_o_next = 1'b0; + delay_next = prescale; + phy_state_next = PHY_STATE_STOP_1; + end else begin + phy_state_next = PHY_STATE_ACTIVE; + end + end + PHY_STATE_REPEATED_START_1: begin + // generate repeated start bit + // ______ + // sda XXX/ \_______ + // _______ + // scl ______/ \___ + // + + scl_o_next = 1'b1; + delay_scl_next = 1'b1; + delay_next = prescale; + phy_state_next = PHY_STATE_REPEATED_START_2; + end + PHY_STATE_REPEATED_START_2: begin + // generate repeated start bit + // ______ + // sda XXX/ \_______ + // _______ + // scl ______/ \___ + // + + sda_o_next = 1'b0; + delay_next = prescale; + phy_state_next = PHY_STATE_START_1; + end + PHY_STATE_START_1: begin + // generate start bit + // ___ + // sda \_______ + // _______ + // scl \___ + // + + scl_o_next = 1'b0; + delay_next = prescale; + phy_state_next = PHY_STATE_START_2; + end + PHY_STATE_START_2: begin + // generate start bit + // ___ + // sda \_______ + // _______ + // scl \___ + // + + bus_control_next = 1'b1; + phy_state_next = PHY_STATE_ACTIVE; + end + PHY_STATE_WRITE_BIT_1: begin + // write bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + scl_o_next = 1'b1; + delay_scl_next = 1'b1; + delay_next = prescale << 1; + phy_state_next = PHY_STATE_WRITE_BIT_2; + end + PHY_STATE_WRITE_BIT_2: begin + // write bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + scl_o_next = 1'b0; + delay_next = prescale; + phy_state_next = PHY_STATE_WRITE_BIT_3; + end + PHY_STATE_WRITE_BIT_3: begin + // write bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + phy_state_next = PHY_STATE_ACTIVE; + end + PHY_STATE_READ_BIT_1: begin + // read bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + scl_o_next = 1'b1; + delay_scl_next = 1'b1; + delay_next = prescale; + phy_state_next = PHY_STATE_READ_BIT_2; + end + PHY_STATE_READ_BIT_2: begin + // read bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + phy_rx_data_next = sda_i_reg; + delay_next = prescale; + phy_state_next = PHY_STATE_READ_BIT_3; + end + PHY_STATE_READ_BIT_3: begin + // read bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + scl_o_next = 1'b0; + delay_next = prescale; + phy_state_next = PHY_STATE_READ_BIT_4; + end + PHY_STATE_READ_BIT_4: begin + // read bit + // ________ + // sda X________X + // ____ + // scl __/ \__ + + phy_state_next = PHY_STATE_ACTIVE; + end + PHY_STATE_STOP_1: begin + // stop bit + // ___ + // sda XXX\_______/ + // _______ + // scl _______/ + + scl_o_next = 1'b1; + delay_scl_next = 1'b1; + delay_next = prescale; + phy_state_next = PHY_STATE_STOP_2; + end + PHY_STATE_STOP_2: begin + // stop bit + // ___ + // sda XXX\_______/ + // _______ + // scl _______/ + + sda_o_next = 1'b1; + delay_next = prescale; + phy_state_next = PHY_STATE_STOP_3; + end + PHY_STATE_STOP_3: begin + // stop bit + // ___ + // sda XXX\_______/ + // _______ + // scl _______/ + + bus_control_next = 1'b0; + phy_state_next = PHY_STATE_IDLE; + end + endcase + end +end + +always @(posedge clk) begin + state_reg <= state_next; + phy_state_reg <= phy_state_next; + + phy_rx_data_reg <= phy_rx_data_next; + + addr_reg <= addr_next; + data_reg <= data_next; + last_reg <= last_next; + + mode_read_reg <= mode_read_next; + mode_write_multiple_reg <= mode_write_multiple_next; + mode_stop_reg <= mode_stop_next; + + delay_reg <= delay_next; + delay_scl_reg <= delay_scl_next; + delay_sda_reg <= delay_sda_next; + + bit_count_reg <= bit_count_next; + + s_axis_cmd_ready_reg <= s_axis_cmd_ready_next; + + s_axis_data_tready_reg <= s_axis_data_tready_next; + + m_axis_data_tdata_reg <= m_axis_data_tdata_next; + m_axis_data_tlast_reg <= m_axis_data_tlast_next; + m_axis_data_tvalid_reg <= m_axis_data_tvalid_next; + + scl_i_reg <= scl_i; + sda_i_reg <= sda_i; + + scl_o_reg <= scl_o_next; + sda_o_reg <= sda_o_next; + + last_scl_i_reg <= scl_i_reg; + last_sda_i_reg <= sda_i_reg; + + busy_reg <= !(state_reg == STATE_IDLE || state_reg == STATE_ACTIVE_WRITE || state_reg == STATE_ACTIVE_READ) || !(phy_state_reg == PHY_STATE_IDLE || phy_state_reg == PHY_STATE_ACTIVE); + + if (start_bit) begin + bus_active_reg <= 1'b1; + end else if (stop_bit) begin + bus_active_reg <= 1'b0; + end else begin + bus_active_reg <= bus_active_reg; + end + + bus_control_reg <= bus_control_next; + missed_ack_reg <= missed_ack_next; + + if (rst) begin + state_reg <= STATE_IDLE; + phy_state_reg <= PHY_STATE_IDLE; + delay_reg <= 16'd0; + delay_scl_reg <= 1'b0; + delay_sda_reg <= 1'b0; + s_axis_cmd_ready_reg <= 1'b0; + s_axis_data_tready_reg <= 1'b0; + m_axis_data_tvalid_reg <= 1'b0; + scl_o_reg <= 1'b1; + sda_o_reg <= 1'b1; + busy_reg <= 1'b0; + bus_active_reg <= 1'b0; + bus_control_reg <= 1'b0; + missed_ack_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/rtl/mdio_master.v b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/mdio_master.v similarity index 100% rename from fpga/lib/eth/example/VCU118/fpga_10g/rtl/mdio_master.v rename to fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/mdio_master.v diff --git a/fpga/lib/eth/example/HXT100G/fpga_cxpt16/rtl/sync_signal.v b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/sync_signal.v similarity index 100% rename from fpga/lib/eth/example/HXT100G/fpga_cxpt16/rtl/sync_signal.v rename to fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/sync_signal.v diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/Makefile similarity index 100% rename from fpga/lib/eth/example/VCU118/fpga_10g/tb/fpga_core/Makefile rename to fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/Makefile diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/test_fpga_core.py similarity index 63% rename from fpga/lib/eth/example/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py rename to fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/test_fpga_core.py index 2ada7550b..be990e00a 100644 --- a/fpga/lib/eth/example/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/test_fpga_core.py @@ -46,7 +46,7 @@ class TB: self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) - cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) + cocotb.start_soon(Clock(dut.clk, 2.56, units="ns").start()) # Ethernet cocotb.start_soon(Clock(dut.phy_gmii_clk, 8, units="ns").start()) @@ -58,45 +58,37 @@ class TB: dut.phy_gmii_clk_en.setimmediatevalue(1) - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_1, 6.4, units="ns").start()) - self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_1, 6.4, units="ns").start()) - self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1) + self.qsfp_source = [] + self.qsfp_sink = [] - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_2, 6.4, units="ns").start()) - self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_2, 6.4, units="ns").start()) - self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2) + for x in range(1, 3): + sources = [] + sinks = [] + for y in range(1, 5): + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_rx_clk_{y}"), 2.56, units="ns").start()) + source = XgmiiSource(getattr(dut, f"qsfp{x}_rxd_{y}"), getattr(dut, f"qsfp{x}_rxc_{y}"), getattr(dut, f"qsfp{x}_rx_clk_{y}"), getattr(dut, f"qsfp{x}_rx_rst_{y}")) + sources.append(source) + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_tx_clk_{y}"), 2.56, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"qsfp{x}_txd_{y}"), getattr(dut, f"qsfp{x}_txc_{y}"), getattr(dut, f"qsfp{x}_tx_clk_{y}"), getattr(dut, f"qsfp{x}_tx_rst_{y}")) + sinks.append(sink) + self.qsfp_source.append(sources) + self.qsfp_sink.append(sinks) - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_3, 6.4, units="ns").start()) - self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_3, 6.4, units="ns").start()) - self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3) + self.fmcp_qsfp_source = [] + self.fmcp_qsfp_sink = [] - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_4, 6.4, units="ns").start()) - self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 6.4, units="ns").start()) - self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4) - - cocotb.start_soon(Clock(dut.qsfp2_rx_clk_1, 6.4, units="ns").start()) - self.qsfp2_1_source = XgmiiSource(dut.qsfp2_rxd_1, dut.qsfp2_rxc_1, dut.qsfp2_rx_clk_1, dut.qsfp2_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp2_tx_clk_1, 6.4, units="ns").start()) - self.qsfp2_1_sink = XgmiiSink(dut.qsfp2_txd_1, dut.qsfp2_txc_1, dut.qsfp2_tx_clk_1, dut.qsfp2_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp2_rx_clk_2, 6.4, units="ns").start()) - self.qsfp2_2_source = XgmiiSource(dut.qsfp2_rxd_2, dut.qsfp2_rxc_2, dut.qsfp2_rx_clk_2, dut.qsfp2_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp2_tx_clk_2, 6.4, units="ns").start()) - self.qsfp2_2_sink = XgmiiSink(dut.qsfp2_txd_2, dut.qsfp2_txc_2, dut.qsfp2_tx_clk_2, dut.qsfp2_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp2_rx_clk_3, 6.4, units="ns").start()) - self.qsfp2_3_source = XgmiiSource(dut.qsfp2_rxd_3, dut.qsfp2_rxc_3, dut.qsfp2_rx_clk_3, dut.qsfp2_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp2_tx_clk_3, 6.4, units="ns").start()) - self.qsfp2_3_sink = XgmiiSink(dut.qsfp2_txd_3, dut.qsfp2_txc_3, dut.qsfp2_tx_clk_3, dut.qsfp2_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp2_rx_clk_4, 6.4, units="ns").start()) - self.qsfp2_4_source = XgmiiSource(dut.qsfp2_rxd_4, dut.qsfp2_rxc_4, dut.qsfp2_rx_clk_4, dut.qsfp2_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp2_tx_clk_4, 6.4, units="ns").start()) - self.qsfp2_4_sink = XgmiiSink(dut.qsfp2_txd_4, dut.qsfp2_txc_4, dut.qsfp2_tx_clk_4, dut.qsfp2_tx_rst_4) + for x in range(1, 7): + sources = [] + sinks = [] + for y in range(1, 5): + cocotb.start_soon(Clock(getattr(dut, f"fmcp_qsfp{x}_rx_clk_{y}"), 2.56, units="ns").start()) + source = XgmiiSource(getattr(dut, f"fmcp_qsfp{x}_rxd_{y}"), getattr(dut, f"fmcp_qsfp{x}_rxc_{y}"), getattr(dut, f"fmcp_qsfp{x}_rx_clk_{y}"), getattr(dut, f"fmcp_qsfp{x}_rx_rst_{y}")) + sources.append(source) + cocotb.start_soon(Clock(getattr(dut, f"fmcp_qsfp{x}_tx_clk_{y}"), 2.56, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"fmcp_qsfp{x}_txd_{y}"), getattr(dut, f"fmcp_qsfp{x}_txc_{y}"), getattr(dut, f"fmcp_qsfp{x}_tx_clk_{y}"), getattr(dut, f"fmcp_qsfp{x}_tx_rst_{y}")) + sinks.append(sink) + self.qsfp_source.append(sources) + self.qsfp_sink.append(sinks) dut.btnu.setimmediatevalue(0) dut.btnl.setimmediatevalue(0) @@ -111,66 +103,42 @@ class TB: self.dut.rst.setimmediatevalue(0) self.dut.phy_gmii_rst.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) - self.dut.qsfp2_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp2_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp2_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp2_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp2_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp2_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp2_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp2_tx_rst_4.setimmediatevalue(0) + for x in range(1, 3): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(0) + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(0) + for x in range(1, 7): + for y in range(1, 5): + getattr(self.dut, f"fmcp_qsfp{x}_rx_rst_{y}").setimmediatevalue(0) + getattr(self.dut, f"fmcp_qsfp{x}_tx_rst_{y}").setimmediatevalue(0) for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 1 self.dut.phy_gmii_rst.value = 1 - self.dut.qsfp1_rx_rst_1.value = 1 - self.dut.qsfp1_tx_rst_1.value = 1 - self.dut.qsfp1_rx_rst_2.value = 1 - self.dut.qsfp1_tx_rst_2.value = 1 - self.dut.qsfp1_rx_rst_3.value = 1 - self.dut.qsfp1_tx_rst_3.value = 1 - self.dut.qsfp1_rx_rst_4.value = 1 - self.dut.qsfp1_tx_rst_4.value = 1 - self.dut.qsfp2_rx_rst_1.value = 1 - self.dut.qsfp2_tx_rst_1.value = 1 - self.dut.qsfp2_rx_rst_2.value = 1 - self.dut.qsfp2_tx_rst_2.value = 1 - self.dut.qsfp2_rx_rst_3.value = 1 - self.dut.qsfp2_tx_rst_3.value = 1 - self.dut.qsfp2_rx_rst_4.value = 1 - self.dut.qsfp2_tx_rst_4.value = 1 + for x in range(1, 3): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").value = 1 + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").value = 1 + for x in range(1, 7): + for y in range(1, 5): + getattr(self.dut, f"fmcp_qsfp{x}_rx_rst_{y}").value = 1 + getattr(self.dut, f"fmcp_qsfp{x}_tx_rst_{y}").value = 1 for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 0 self.dut.phy_gmii_rst.value = 0 - self.dut.qsfp1_rx_rst_1.value = 0 - self.dut.qsfp1_tx_rst_1.value = 0 - self.dut.qsfp1_rx_rst_2.value = 0 - self.dut.qsfp1_tx_rst_2.value = 0 - self.dut.qsfp1_rx_rst_3.value = 0 - self.dut.qsfp1_tx_rst_3.value = 0 - self.dut.qsfp1_rx_rst_4.value = 0 - self.dut.qsfp1_tx_rst_4.value = 0 - self.dut.qsfp2_rx_rst_1.value = 0 - self.dut.qsfp2_tx_rst_1.value = 0 - self.dut.qsfp2_rx_rst_2.value = 0 - self.dut.qsfp2_tx_rst_2.value = 0 - self.dut.qsfp2_rx_rst_3.value = 0 - self.dut.qsfp2_tx_rst_3.value = 0 - self.dut.qsfp2_rx_rst_4.value = 0 - self.dut.qsfp2_tx_rst_4.value = 0 + for x in range(1, 3): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").value = 0 + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").value = 0 + for x in range(1, 7): + for y in range(1, 5): + getattr(self.dut, f"fmcp_qsfp{x}_rx_rst_{y}").value = 0 + getattr(self.dut, f"fmcp_qsfp{x}_tx_rst_{y}").value = 0 @cocotb.test() @@ -190,11 +158,11 @@ async def run_test(dut): test_frame = XgmiiFrame.from_payload(test_pkt.build()) - await tb.qsfp1_1_source.send(test_frame) + await tb.qsfp_source[0][0].send(test_frame) tb.log.info("receive ARP request") - rx_frame = await tb.qsfp1_1_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -222,11 +190,11 @@ async def run_test(dut): resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - await tb.qsfp1_1_source.send(resp_frame) + await tb.qsfp_source[0][0].send(resp_frame) tb.log.info("receive UDP packet") - rx_frame = await tb.qsfp1_1_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -259,13 +227,13 @@ async def run_test(dut): tb.log.info("loop back packet on XGMII interface") - rx_frame = await tb.qsfp1_1_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) tb.log.info("RX packet: %s", repr(rx_pkt)) - await tb.qsfp1_1_source.send(rx_frame) + await tb.qsfp_source[0][0].send(rx_frame) tb.log.info("receive UDP packet") @@ -302,13 +270,13 @@ async def run_test(dut): tb.log.info("loop back packet on XGMII interface") - rx_frame = await tb.qsfp1_1_sink.recv() + rx_frame = await tb.qsfp_sink[0][0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) tb.log.info("RX packet: %s", repr(rx_pkt)) - await tb.qsfp1_1_source.send(rx_frame) + await tb.qsfp_source[0][0].send(rx_frame) tb.log.info("receive UDP packet") diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/Makefile b/fpga/lib/eth/example/VCU1525/fpga_10g/Makefile deleted file mode 100644 index f504bd06f..000000000 --- a/fpga/lib/eth/example/VCU1525/fpga_10g/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# Targets -TARGETS:= - -# Subdirectories -SUBDIRS = fpga -SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) - -# Rules -.PHONY: all -all: $(SUBDIRS) $(TARGETS) - -.PHONY: $(SUBDIRS) -$(SUBDIRS): - cd $@ && $(MAKE) - -.PHONY: $(SUBDIRS_CLEAN) -$(SUBDIRS_CLEAN): - cd $(@:.clean=) && $(MAKE) clean - -.PHONY: clean -clean: $(SUBDIRS_CLEAN) - -rm -rf $(TARGETS) - -program: - #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/common/vivado.mk b/fpga/lib/eth/example/VCU1525/fpga_10g/common/vivado.mk deleted file mode 100644 index 21e6a5fed..000000000 --- a/fpga/lib/eth/example/VCU1525/fpga_10g/common/vivado.mk +++ /dev/null @@ -1,131 +0,0 @@ -################################################################### -# -# Xilinx Vivado FPGA Makefile -# -# Copyright (c) 2016 Alex Forencich -# -################################################################### -# -# Parameters: -# FPGA_TOP - Top module name -# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) -# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) -# SYN_FILES - space-separated list of source files -# INC_FILES - space-separated list of include files -# XDC_FILES - space-separated list of timing constraint files -# XCI_FILES - space-separated list of IP XCI files -# -# Example: -# -# FPGA_TOP = fpga -# FPGA_FAMILY = VirtexUltrascale -# FPGA_DEVICE = xcvu095-ffva2104-2-e -# SYN_FILES = rtl/fpga.v -# XDC_FILES = fpga.xdc -# XCI_FILES = ip/pcspma.xci -# include ../common/vivado.mk -# -################################################################### - -# phony targets -.PHONY: clean fpga - -# prevent make from deleting intermediate files and reports -.PRECIOUS: %.xpr %.bit %.mcs %.prm -.SECONDARY: - -CONFIG ?= config.mk --include ../$(CONFIG) - -FPGA_TOP ?= fpga -PROJECT ?= $(FPGA_TOP) - -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) - -ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) -else - XDC_FILES_REL = $(FPGA_TOP).xdc -endif - -################################################################### -# Main Targets -# -# all: build everything -# clean: remove output files and project files -################################################################### - -all: fpga - -fpga: $(FPGA_TOP).bit - -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr - -tmpclean: - -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl - -clean: tmpclean - -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl - -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt - -distclean: clean - -rm -rf rev - -################################################################### -# Target implementations -################################################################### - -# Vivado project file -create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) - rm -rf defines.v - touch defines.v - for x in $(DEFS); do echo '`define' $$x >> defines.v; done - echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ - echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ - echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ - echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ - for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done - for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done - -$(PROJECT).xpr: create_project.tcl - vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) - -# synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) - echo "open_project $(PROJECT).xpr" > run_synth.tcl - echo "reset_run synth_1" >> run_synth.tcl - echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl - echo "wait_on_run synth_1" >> run_synth.tcl - vivado -nojournal -nolog -mode batch -source run_synth.tcl - -# implementation run -$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp - echo "open_project $(PROJECT).xpr" > run_impl.tcl - echo "reset_run impl_1" >> run_impl.tcl - echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl - echo "wait_on_run impl_1" >> run_impl.tcl - echo "open_run impl_1" >> run_impl.tcl - echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl - echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl - vivado -nojournal -nolog -mode batch -source run_impl.tcl - -# bit file -$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp - echo "open_project $(PROJECT).xpr" > generate_bit.tcl - echo "open_run impl_1" >> generate_bit.tcl - echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl - echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl - vivado -nojournal -nolog -mode batch -source generate_bit.tcl - ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi - mkdir -p rev - COUNT=100; \ - while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ - do COUNT=$$((COUNT+1)); done; \ - cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/fpga.xdc b/fpga/lib/eth/example/VCU1525/fpga_10g/fpga.xdc deleted file mode 100644 index 35eff0096..000000000 --- a/fpga/lib/eth/example/VCU1525/fpga_10g/fpga.xdc +++ /dev/null @@ -1,244 +0,0 @@ -# XDC constraints for the Xilinx VCU1525 board -# part: xcvu9p-fsgd2104-2L-e - -# General configuration -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design] -set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] -set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] -set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] - -# System clocks -# 300 MHz (DDR 0) -#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] -#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] -#create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p] - -# 300 MHz (DDR 1) -#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] -#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] -#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] - -# 300 MHz (DDR 2) -#set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] -#set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] -#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] - -# 300 MHz (DDR 3) -#set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] -#set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] -#create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p] - -# SI570 user clock -#set_property -dict {LOC AU19 IOSTANDARD LVDS} [get_ports clk_user_p] -#set_property -dict {LOC AV19 IOSTANDARD LVDS} [get_ports clk_user_n] -#create_clock -period 6.400 -name clk_user [get_ports clk_user_p] - -# LEDs -set_property -dict {LOC BC21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] -set_property -dict {LOC BB21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] -set_property -dict {LOC BA20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}] - -set_false_path -to [get_ports {led[*]}] -set_output_delay 0 [get_ports {led[*]}] - -# Reset button -set_property -dict {LOC AL20 IOSTANDARD LVCMOS12} [get_ports reset] - -set_false_path -from [get_ports {reset}] -set_input_delay 0 [get_ports {reset}] - -# DIP switches -set_property -dict {LOC AN22 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] -set_property -dict {LOC AM19 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] -set_property -dict {LOC AL19 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] -set_property -dict {LOC AP20 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] - -set_false_path -from [get_ports {sw[*]}] -set_input_delay 0 [get_ports {sw[*]}] - -# UART -set_property -dict {LOC BF18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd] -set_property -dict {LOC BB20 IOSTANDARD LVCMOS12} [get_ports uart_rxd] - -#set_false_path -to [get_ports {uart_txd}] -#set_output_delay 0 [get_ports {uart_txd}] -#set_false_path -from [get_ports {uart_rxd}] -#set_input_delay 0 [get_ports {uart_rxd}] - -# QSFP28 Interfaces -set_property -dict {LOC N4 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC N3 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC N9 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC N8 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M2 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M1 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M7 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M6 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L4 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L3 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L9 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L8 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K2 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K1 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K7 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K6 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13 -#set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14 -set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18 -set_property -dict {LOC K10 } [get_ports qsfp0_mgt_refclk_1_n] ;# MGTREFCLK1N_231 from U9.17 -set_property -dict {LOC BE16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_modsell] -set_property -dict {LOC BE17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl] -set_property -dict {LOC BE20 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_modprsl] -set_property -dict {LOC BE21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_intl] -set_property -dict {LOC BD18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode] -set_property -dict {LOC AT22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_refclk_reset] -set_property -dict {LOC AT20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[0]}] -set_property -dict {LOC AU22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[1]}] - -# 156.25 MHz MGT reference clock (from SI570) -#create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports qsfp0_mgt_refclk_0_p] - -# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) -#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] - -# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) -create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] - -set_false_path -to [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] -set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] -set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}] -set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}] - -set_property -dict {LOC U4 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC U3 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC U9 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC U8 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T2 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T1 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R4 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R3 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R9 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R8 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P2 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P1 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15 -#set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16 -set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18 -set_property -dict {LOC P10 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U12.17 -set_property -dict {LOC AY20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_modsell] -set_property -dict {LOC BC18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl] -set_property -dict {LOC BC19 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_modprsl] -set_property -dict {LOC AV21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_intl] -set_property -dict {LOC AV22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode] -set_property -dict {LOC AR21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_refclk_reset] -set_property -dict {LOC AR22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[0]}] -set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[1]}] - -# 156.25 MHz MGT reference clock (from SI570) -#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p] - -# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) -#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] - -# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) -create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] - -set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] -set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] -set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] -set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] - -# I2C interface -#set_property -dict {LOC BF19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset] -set_property -dict {LOC BF20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_scl] -set_property -dict {LOC BF17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_sda] - -set_false_path -to [get_ports {i2c_sda i2c_scl}] -set_output_delay 0 [get_ports {i2c_sda i2c_scl}] -set_false_path -from [get_ports {i2c_sda i2c_scl}] -set_input_delay 0 [get_ports {i2c_sda i2c_scl}] - -# PCIe Interface -#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AG9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AG8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AJ9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AJ8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AL4 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AL3 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AL9 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AL8 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AN4 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AN3 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AN9 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AN8 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AR4 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AR3 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AR9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AR8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AU4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AU3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AU9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AU8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AV7 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AV6 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AW4 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AW3 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BB5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BB4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BD5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BD4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BF5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BF4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AM11 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_226 -#set_property -dict {LOC AM10 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_226 -#set_property -dict {LOC BD21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n] - -# 100 MHz MGT reference clock -#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p] - -#set_false_path -from [get_ports {pcie_reset_n}] -#set_input_delay 0 [get_ports {pcie_reset_n}] diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/VCU1525/fpga_10g/tb/fpga_core/test_fpga_core.py deleted file mode 100644 index 6f609015c..000000000 --- a/fpga/lib/eth/example/VCU1525/fpga_10g/tb/fpga_core/test_fpga_core.py +++ /dev/null @@ -1,289 +0,0 @@ -""" - -Copyright (c) 2020 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -""" - -import logging -import os - -from scapy.layers.l2 import Ether, ARP -from scapy.layers.inet import IP, UDP - -import cocotb_test.simulator - -import cocotb -from cocotb.log import SimLog -from cocotb.clock import Clock -from cocotb.triggers import RisingEdge - -from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink - - -class TB: - def __init__(self, dut): - self.dut = dut - - self.log = SimLog("cocotb.tb") - self.log.setLevel(logging.DEBUG) - - cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) - - # Ethernet - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_1, 6.4, units="ns").start()) - self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1, dut.qsfp0_rx_clk_1, dut.qsfp0_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_1, 6.4, units="ns").start()) - self.qsfp0_1_sink = XgmiiSink(dut.qsfp0_txd_1, dut.qsfp0_txc_1, dut.qsfp0_tx_clk_1, dut.qsfp0_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_2, 6.4, units="ns").start()) - self.qsfp0_2_source = XgmiiSource(dut.qsfp0_rxd_2, dut.qsfp0_rxc_2, dut.qsfp0_rx_clk_2, dut.qsfp0_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_2, 6.4, units="ns").start()) - self.qsfp0_2_sink = XgmiiSink(dut.qsfp0_txd_2, dut.qsfp0_txc_2, dut.qsfp0_tx_clk_2, dut.qsfp0_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_3, 6.4, units="ns").start()) - self.qsfp0_3_source = XgmiiSource(dut.qsfp0_rxd_3, dut.qsfp0_rxc_3, dut.qsfp0_rx_clk_3, dut.qsfp0_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_3, 6.4, units="ns").start()) - self.qsfp0_3_sink = XgmiiSink(dut.qsfp0_txd_3, dut.qsfp0_txc_3, dut.qsfp0_tx_clk_3, dut.qsfp0_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp0_rx_clk_4, 6.4, units="ns").start()) - self.qsfp0_4_source = XgmiiSource(dut.qsfp0_rxd_4, dut.qsfp0_rxc_4, dut.qsfp0_rx_clk_4, dut.qsfp0_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp0_tx_clk_4, 6.4, units="ns").start()) - self.qsfp0_4_sink = XgmiiSink(dut.qsfp0_txd_4, dut.qsfp0_txc_4, dut.qsfp0_tx_clk_4, dut.qsfp0_tx_rst_4) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_1, 6.4, units="ns").start()) - self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_1, 6.4, units="ns").start()) - self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_2, 6.4, units="ns").start()) - self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_2, 6.4, units="ns").start()) - self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_3, 6.4, units="ns").start()) - self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_3, 6.4, units="ns").start()) - self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_4, 6.4, units="ns").start()) - self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 6.4, units="ns").start()) - self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4) - - dut.sw.setimmediatevalue(0) - - async def init(self): - - self.dut.rst.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp0_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp0_tx_rst_4.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) - - for k in range(10): - await RisingEdge(self.dut.clk) - - self.dut.rst.value = 1 - self.dut.qsfp0_rx_rst_1.value = 1 - self.dut.qsfp0_tx_rst_1.value = 1 - self.dut.qsfp0_rx_rst_2.value = 1 - self.dut.qsfp0_tx_rst_2.value = 1 - self.dut.qsfp0_rx_rst_3.value = 1 - self.dut.qsfp0_tx_rst_3.value = 1 - self.dut.qsfp0_rx_rst_4.value = 1 - self.dut.qsfp0_tx_rst_4.value = 1 - self.dut.qsfp1_rx_rst_1.value = 1 - self.dut.qsfp1_tx_rst_1.value = 1 - self.dut.qsfp1_rx_rst_2.value = 1 - self.dut.qsfp1_tx_rst_2.value = 1 - self.dut.qsfp1_rx_rst_3.value = 1 - self.dut.qsfp1_tx_rst_3.value = 1 - self.dut.qsfp1_rx_rst_4.value = 1 - self.dut.qsfp1_tx_rst_4.value = 1 - - for k in range(10): - await RisingEdge(self.dut.clk) - - self.dut.rst.value = 0 - self.dut.qsfp0_rx_rst_1.value = 0 - self.dut.qsfp0_tx_rst_1.value = 0 - self.dut.qsfp0_rx_rst_2.value = 0 - self.dut.qsfp0_tx_rst_2.value = 0 - self.dut.qsfp0_rx_rst_3.value = 0 - self.dut.qsfp0_tx_rst_3.value = 0 - self.dut.qsfp0_rx_rst_4.value = 0 - self.dut.qsfp0_tx_rst_4.value = 0 - self.dut.qsfp1_rx_rst_1.value = 0 - self.dut.qsfp1_tx_rst_1.value = 0 - self.dut.qsfp1_rx_rst_2.value = 0 - self.dut.qsfp1_tx_rst_2.value = 0 - self.dut.qsfp1_rx_rst_3.value = 0 - self.dut.qsfp1_tx_rst_3.value = 0 - self.dut.qsfp1_rx_rst_4.value = 0 - self.dut.qsfp1_tx_rst_4.value = 0 - - -@cocotb.test() -async def run_test(dut): - - tb = TB(dut) - - await tb.init() - - tb.log.info("test UDP RX packet") - - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00') - ip = IP(src='192.168.1.100', dst='192.168.1.128') - udp = UDP(sport=5678, dport=1234) - test_pkt = eth / ip / udp / payload - - test_frame = XgmiiFrame.from_payload(test_pkt.build()) - - await tb.qsfp0_1_source.send(test_frame) - - tb.log.info("receive ARP request") - - rx_frame = await tb.qsfp0_1_sink.recv() - - rx_pkt = Ether(bytes(rx_frame.get_payload())) - - tb.log.info("RX packet: %s", repr(rx_pkt)) - - assert rx_pkt.dst == 'ff:ff:ff:ff:ff:ff' - assert rx_pkt.src == test_pkt.dst - assert rx_pkt[ARP].hwtype == 1 - assert rx_pkt[ARP].ptype == 0x0800 - assert rx_pkt[ARP].hwlen == 6 - assert rx_pkt[ARP].plen == 4 - assert rx_pkt[ARP].op == 1 - assert rx_pkt[ARP].hwsrc == test_pkt.dst - assert rx_pkt[ARP].psrc == test_pkt[IP].dst - assert rx_pkt[ARP].hwdst == '00:00:00:00:00:00' - assert rx_pkt[ARP].pdst == test_pkt[IP].src - - tb.log.info("send ARP response") - - eth = Ether(src=test_pkt.src, dst=test_pkt.dst) - arp = ARP(hwtype=1, ptype=0x0800, hwlen=6, plen=4, op=2, - hwsrc=test_pkt.src, psrc=test_pkt[IP].src, - hwdst=test_pkt.dst, pdst=test_pkt[IP].dst) - resp_pkt = eth / arp - - resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - - await tb.qsfp0_1_source.send(resp_frame) - - tb.log.info("receive UDP packet") - - rx_frame = await tb.qsfp0_1_sink.recv() - - rx_pkt = Ether(bytes(rx_frame.get_payload())) - - tb.log.info("RX packet: %s", repr(rx_pkt)) - - assert rx_pkt.dst == test_pkt.src - assert rx_pkt.src == test_pkt.dst - assert rx_pkt[IP].dst == test_pkt[IP].src - assert rx_pkt[IP].src == test_pkt[IP].dst - assert rx_pkt[UDP].dport == test_pkt[UDP].sport - assert rx_pkt[UDP].sport == test_pkt[UDP].dport - assert rx_pkt[UDP].payload == test_pkt[UDP].payload - - await RisingEdge(dut.clk) - await RisingEdge(dut.clk) - - -# cocotb-test - -tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) -axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'lib', 'axis', 'rtl')) -eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) - - -def test_fpga_core(request): - dut = "fpga_core" - module = os.path.splitext(os.path.basename(__file__))[0] - toplevel = dut - - verilog_sources = [ - os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g_fifo.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), - os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "eth_axis_rx.v"), - os.path.join(eth_rtl_dir, "eth_axis_tx.v"), - os.path.join(eth_rtl_dir, "udp_complete_64.v"), - os.path.join(eth_rtl_dir, "udp_checksum_gen_64.v"), - os.path.join(eth_rtl_dir, "udp_64.v"), - os.path.join(eth_rtl_dir, "udp_ip_rx_64.v"), - os.path.join(eth_rtl_dir, "udp_ip_tx_64.v"), - os.path.join(eth_rtl_dir, "ip_complete_64.v"), - os.path.join(eth_rtl_dir, "ip_64.v"), - os.path.join(eth_rtl_dir, "ip_eth_rx_64.v"), - os.path.join(eth_rtl_dir, "ip_eth_tx_64.v"), - os.path.join(eth_rtl_dir, "ip_arb_mux.v"), - os.path.join(eth_rtl_dir, "arp.v"), - os.path.join(eth_rtl_dir, "arp_cache.v"), - os.path.join(eth_rtl_dir, "arp_eth_rx.v"), - os.path.join(eth_rtl_dir, "arp_eth_tx.v"), - os.path.join(eth_rtl_dir, "eth_arb_mux.v"), - os.path.join(axis_rtl_dir, "arbiter.v"), - os.path.join(axis_rtl_dir, "priority_encoder.v"), - os.path.join(axis_rtl_dir, "axis_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), - ] - - parameters = {} - - # parameters['A'] = val - - extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} - - sim_build = os.path.join(tests_dir, "sim_build", - request.node.name.replace('[', '-').replace(']', '')) - - cocotb_test.simulator.run( - python_search=[tests_dir], - verilog_sources=verilog_sources, - toplevel=toplevel, - module=module, - parameters=parameters, - sim_build=sim_build, - extra_env=extra_env, - ) diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/Makefile b/fpga/lib/eth/example/VCU1525/fpga_25g/Makefile similarity index 100% rename from fpga/lib/eth/example/ExaNIC_X25/fpga_10g/Makefile rename to fpga/lib/eth/example/VCU1525/fpga_25g/Makefile diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/README.md b/fpga/lib/eth/example/VCU1525/fpga_25g/README.md similarity index 100% rename from fpga/lib/eth/example/VCU1525/fpga_10g/README.md rename to fpga/lib/eth/example/VCU1525/fpga_25g/README.md diff --git a/fpga/lib/eth/example/VCU1525/fpga_25g/common/vivado.mk b/fpga/lib/eth/example/VCU1525/fpga_25g/common/vivado.mk new file mode 100644 index 000000000..1402e2382 --- /dev/null +++ b/fpga/lib/eth/example/VCU1525/fpga_25g/common/vivado.mk @@ -0,0 +1,137 @@ +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - space-separated list of source files +# INC_FILES - space-separated list of include files +# XDC_FILES - space-separated list of timing constraint files +# XCI_FILES - space-separated list of IP XCI files +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: fpga vivado tmpclean clean distclean + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include ../$(CONFIG) + +FPGA_TOP ?= fpga +PROJECT ?= $(FPGA_TOP) + +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) + +ifdef XDC_FILES + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +else + XDC_FILES_REL = $(PROJECT).xdc +endif + +################################################################### +# Main Targets +# +# all: build everything +# clean: remove output files and project files +################################################################### + +all: fpga + +fpga: $(PROJECT).bit + +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr + +tmpclean:: + -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean:: tmpclean + -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt + +distclean:: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file +create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ + echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ + echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ + echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ + for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl + vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) + +# synthesis run +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr + echo "open_project $(PROJECT).xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp + echo "open_project $(PROJECT).xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + echo "open_run impl_1" >> run_impl.tcl + echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl + echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# bit file +$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp + echo "open_project $(PROJECT).xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl + echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi + mkdir -p rev + COUNT=100; \ + while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/lib/eth/example/VCU1525/fpga_25g/fpga.xdc b/fpga/lib/eth/example/VCU1525/fpga_25g/fpga.xdc new file mode 100644 index 000000000..d78cb3ec2 --- /dev/null +++ b/fpga/lib/eth/example/VCU1525/fpga_25g/fpga.xdc @@ -0,0 +1,833 @@ +# XDC constraints for the Xilinx VCU1525 board +# part: xcvu9p-fsgd2104-2L-e + +# General configuration +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] + +# System clocks +# 300 MHz (DDR 0) +#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] +#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] +#create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p] + +# 300 MHz (DDR 1) +#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] +#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] +#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] + +# 300 MHz (DDR 2) +#set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] +#set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] +#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] + +# 300 MHz (DDR 3) +#set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] +#set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] +#create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p] + +# SI570 user clock +#set_property -dict {LOC AU19 IOSTANDARD LVDS} [get_ports clk_user_p] +#set_property -dict {LOC AV19 IOSTANDARD LVDS} [get_ports clk_user_n] +#create_clock -period 6.400 -name clk_user [get_ports clk_user_p] + +# LEDs +set_property -dict {LOC BC21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] +set_property -dict {LOC BB21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] +set_property -dict {LOC BA20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}] + +set_false_path -to [get_ports {led[*]}] +set_output_delay 0 [get_ports {led[*]}] + +# Reset button +set_property -dict {LOC AL20 IOSTANDARD LVCMOS12} [get_ports reset] + +set_false_path -from [get_ports {reset}] +set_input_delay 0 [get_ports {reset}] + +# DIP switches +set_property -dict {LOC AN22 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] +set_property -dict {LOC AM19 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] +set_property -dict {LOC AL19 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] +set_property -dict {LOC AP20 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] + +set_false_path -from [get_ports {sw[*]}] +set_input_delay 0 [get_ports {sw[*]}] + +# UART +set_property -dict {LOC BF18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd] +set_property -dict {LOC BB20 IOSTANDARD LVCMOS12} [get_ports uart_rxd] + +#set_false_path -to [get_ports {uart_txd}] +#set_output_delay 0 [get_ports {uart_txd}] +#set_false_path -from [get_ports {uart_rxd}] +#set_input_delay 0 [get_ports {uart_rxd}] + +# QSFP28 Interfaces +set_property -dict {LOC N4 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N3 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N9 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N8 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M2 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M1 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M7 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M6 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L4 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L3 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L9 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L8 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K2 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K1 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K7 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K6 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13 +#set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14 +set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18 +set_property -dict {LOC K10 } [get_ports qsfp0_mgt_refclk_1_n] ;# MGTREFCLK1N_231 from U9.17 +set_property -dict {LOC BE16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_modsell] +set_property -dict {LOC BE17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl] +set_property -dict {LOC BE20 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_modprsl] +set_property -dict {LOC BE21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_intl] +set_property -dict {LOC BD18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode] +set_property -dict {LOC AT22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_refclk_reset] +set_property -dict {LOC AT20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[0]}] +set_property -dict {LOC AU22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[1]}] + +# 156.25 MHz MGT reference clock (from SI570) +#create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports qsfp0_mgt_refclk_0_p] + +# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) +#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] + +# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) +create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] + +set_false_path -to [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] +set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] +set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}] +set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}] + +set_property -dict {LOC U4 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U3 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U9 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U8 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T2 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T1 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R4 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R3 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R9 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R8 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P2 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P1 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +#set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15 +#set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16 +set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18 +set_property -dict {LOC P10 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U12.17 +set_property -dict {LOC AY20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_modsell] +set_property -dict {LOC BC18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl] +set_property -dict {LOC BC19 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_modprsl] +set_property -dict {LOC AV21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_intl] +set_property -dict {LOC AV22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode] +set_property -dict {LOC AR21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_refclk_reset] +set_property -dict {LOC AR22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[0]}] +set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[1]}] + +# 156.25 MHz MGT reference clock (from SI570) +#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p] + +# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) +#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] + +# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) +create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] + +set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] +set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] +set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] +set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] + +# I2C interface +#set_property -dict {LOC BF19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset] +set_property -dict {LOC BF20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_scl] +set_property -dict {LOC BF17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_sda] + +set_false_path -to [get_ports {i2c_sda i2c_scl}] +set_output_delay 0 [get_ports {i2c_sda i2c_scl}] +set_false_path -from [get_ports {i2c_sda i2c_scl}] +set_input_delay 0 [get_ports {i2c_sda i2c_scl}] + +# PCIe Interface +#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AG9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AG8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AJ9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AJ8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AL4 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AL3 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AL9 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AL8 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AN4 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AN3 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AN9 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AN8 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR4 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR3 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AV7 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AV6 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AW4 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AW3 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BB5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BB4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BD5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BD4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BF5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC BF4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AM11 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_226 +#set_property -dict {LOC AM10 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_226 +#set_property -dict {LOC BD21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n] + +# 100 MHz MGT reference clock +#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p] + +#set_false_path -from [get_ports {pcie_reset_n}] +#set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 C0 +#set_property -dict {LOC AT36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +#set_property -dict {LOC AV36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +#set_property -dict {LOC AV37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +#set_property -dict {LOC AW35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +#set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +#set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +#set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +#set_property -dict {LOC BA40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +#set_property -dict {LOC BA37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +#set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +#set_property -dict {LOC AR35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +#set_property -dict {LOC BA39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +#set_property -dict {LOC BB40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +#set_property -dict {LOC AN36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +#set_property -dict {LOC AP35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +#set_property -dict {LOC AP36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +#set_property -dict {LOC AR36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +#set_property -dict {LOC AT35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +#set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +#set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +#set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +#set_property -dict {LOC AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[0]}] +#set_property -dict {LOC AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[0]}] +#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[1]}] +#set_property -dict {LOC AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[1]}] +#set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}] +#set_property -dict {LOC BC40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}] +#set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}] +#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}] +#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}] +#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}] +#set_property -dict {LOC BB39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +#set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}] +#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}] +#set_property -dict {LOC AU36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +#set_property -dict {LOC AU31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] + +#set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +#set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +#set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +#set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +#set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +#set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +#set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +#set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +#set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +#set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +#set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +#set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +#set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +#set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +#set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +#set_property -dict {LOC BF29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +#set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +#set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +#set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +#set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +#set_property -dict {LOC BC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +#set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +#set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +#set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +#set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +#set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +#set_property -dict {LOC AV34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +#set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +#set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +#set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +#set_property -dict {LOC BA35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +#set_property -dict {LOC BA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +#set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +#set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +#set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +#set_property -dict {LOC AT32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +#set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +#set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +#set_property -dict {LOC AR31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +#set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +#set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +#set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +#set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +#set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +#set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +#set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +#set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +#set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +#set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +#set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +#set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +#set_property -dict {LOC AV29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +#set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +#set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +#set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +#set_property -dict {LOC BD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +#set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +#set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +#set_property -dict {LOC BD35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +#set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +#set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +#set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +#set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +#set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +#set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +#set_property -dict {LOC BF43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +#set_property -dict {LOC BF42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +#set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +#set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +#set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +#set_property -dict {LOC BF41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +#set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +#set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +#set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +#set_property -dict {LOC BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +#set_property -dict {LOC BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +#set_property -dict {LOC BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +#set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +#set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +#set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +#set_property -dict {LOC BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +#set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +#set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +#set_property -dict {LOC AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +#set_property -dict {LOC AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +#set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +#set_property -dict {LOC BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +#set_property -dict {LOC AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +#set_property -dict {LOC AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +#set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}] +#set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}] +#set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}] +#set_property -dict {LOC AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}] +#set_property -dict {LOC AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}] +#set_property -dict {LOC AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}] +#set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}] +#set_property -dict {LOC AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}] +#set_property -dict {LOC AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}] +#set_property -dict {LOC AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}] +#set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}] +#set_property -dict {LOC BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}] +#set_property -dict {LOC BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}] +#set_property -dict {LOC BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}] +#set_property -dict {LOC BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}] +#set_property -dict {LOC BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}] +#set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}] +#set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}] + +# DDR4 C1 +#set_property -dict {LOC AN24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +#set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +#set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +#set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +#set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +#set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +#set_property -dict {LOC AV24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +#set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +#set_property -dict {LOC AY25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +#set_property -dict {LOC BA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +#set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +#set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +#set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +#set_property -dict {LOC AL24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +#set_property -dict {LOC AL25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +#set_property -dict {LOC AM25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +#set_property -dict {LOC AN23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +#set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +#set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +#set_property -dict {LOC BC22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +#set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +#set_property -dict {LOC AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[0]}] +#set_property -dict {LOC AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[0]}] +#set_property -dict {LOC AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[1]}] +#set_property -dict {LOC AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[1]}] +#set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}] +#set_property -dict {LOC BB24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}] +#set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}] +#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}] +#set_property -dict {LOC AR23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}] +#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}] +#set_property -dict {LOC AW25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +#set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}] +#set_property -dict {LOC AP24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}] +#set_property -dict {LOC AT23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +#set_property -dict {LOC AR17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] + +#set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +#set_property -dict {LOC BD7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +#set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +#set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +#set_property -dict {LOC BD10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +#set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +#set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +#set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +#set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +#set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +#set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +#set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +#set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +#set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +#set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +#set_property -dict {LOC BA11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +#set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +#set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +#set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +#set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +#set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +#set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +#set_property -dict {LOC BA7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +#set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +#set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +#set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +#set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +#set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +#set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +#set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +#set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +#set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +#set_property -dict {LOC BE13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +#set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +#set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +#set_property -dict {LOC BD13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +#set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +#set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +#set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +#set_property -dict {LOC BF13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +#set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +#set_property -dict {LOC BA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +#set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +#set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +#set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +#set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +#set_property -dict {LOC BC11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +#set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +#set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +#set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +#set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +#set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +#set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +#set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +#set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +#set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +#set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +#set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +#set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +#set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +#set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +#set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +#set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +#set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +#set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +#set_property -dict {LOC BF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +#set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +#set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +#set_property -dict {LOC BD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +#set_property -dict {LOC BC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +#set_property -dict {LOC BF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +#set_property -dict {LOC BE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +#set_property -dict {LOC BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +#set_property -dict {LOC BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +#set_property -dict {LOC BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +#set_property -dict {LOC BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +#set_property -dict {LOC AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +#set_property -dict {LOC AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +#set_property -dict {LOC AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +#set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +#set_property -dict {LOC BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +#set_property -dict {LOC BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +#set_property -dict {LOC BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +#set_property -dict {LOC BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +#set_property -dict {LOC AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +#set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +#set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +#set_property -dict {LOC AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +#set_property -dict {LOC BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +#set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +#set_property -dict {LOC BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] +#set_property -dict {LOC BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] +#set_property -dict {LOC BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}] +#set_property -dict {LOC BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}] +#set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}] +#set_property -dict {LOC BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}] +#set_property -dict {LOC AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}] +#set_property -dict {LOC AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}] +#set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}] +#set_property -dict {LOC AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}] +#set_property -dict {LOC AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}] +#set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}] +#set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}] +#set_property -dict {LOC AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}] +#set_property -dict {LOC BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}] +#set_property -dict {LOC BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}] +#set_property -dict {LOC BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}] +#set_property -dict {LOC BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}] + +# DDR4 C2 +#set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +#set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +#set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +#set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +#set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +#set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +#set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +#set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +#set_property -dict {LOC A32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +#set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +#set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +#set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +#set_property -dict {LOC M30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +#set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +#set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +#set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +#set_property -dict {LOC K30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +#set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +#set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +#set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +#set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}] +#set_property -dict {LOC C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[0]}] +#set_property -dict {LOC B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[0]}] +#set_property -dict {LOC D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[1]}] +#set_property -dict {LOC D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[1]}] +#set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}] +#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}] +#set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}] +#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}] +#set_property -dict {LOC L30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}] +#set_property -dict {LOC K31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}] +#set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +#set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}] +#set_property -dict {LOC F34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}] +#set_property -dict {LOC M29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +#set_property -dict {LOC D36 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] + +#set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] +#set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] +#set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] +#set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] +#set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] +#set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] +#set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] +#set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] +#set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] +#set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] +#set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] +#set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] +#set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] +#set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] +#set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] +#set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] +#set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] +#set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] +#set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] +#set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] +#set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] +#set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] +#set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] +#set_property -dict {LOC F29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] +#set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] +#set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] +#set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] +#set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] +#set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] +#set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] +#set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] +#set_property -dict {LOC C28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] +#set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] +#set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] +#set_property -dict {LOC D38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] +#set_property -dict {LOC E35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] +#set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] +#set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] +#set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] +#set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] +#set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] +#set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] +#set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] +#set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] +#set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] +#set_property -dict {LOC M32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] +#set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] +#set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] +#set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] +#set_property -dict {LOC K35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] +#set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] +#set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] +#set_property -dict {LOC J34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] +#set_property -dict {LOC J33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] +#set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] +#set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] +#set_property -dict {LOC H36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] +#set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] +#set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] +#set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] +#set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] +#set_property -dict {LOC K38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] +#set_property -dict {LOC G35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] +#set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] +#set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] +#set_property -dict {LOC B37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] +#set_property -dict {LOC A37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] +#set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] +#set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] +#set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] +#set_property -dict {LOC A40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] +#set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] +#set_property -dict {LOC N26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] +#set_property -dict {LOC M26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] +#set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] +#set_property -dict {LOC P28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] +#set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] +#set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] +#set_property -dict {LOC M27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] +#set_property -dict {LOC L28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] +#set_property -dict {LOC D29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] +#set_property -dict {LOC D30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] +#set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] +#set_property -dict {LOC H27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] +#set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] +#set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] +#set_property -dict {LOC C29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] +#set_property -dict {LOC B29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] +#set_property -dict {LOC E39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] +#set_property -dict {LOC E40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] +#set_property -dict {LOC G37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] +#set_property -dict {LOC F37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] +#set_property -dict {LOC N31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}] +#set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}] +#set_property -dict {LOC T30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}] +#set_property -dict {LOC R31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}] +#set_property -dict {LOC L35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}] +#set_property -dict {LOC L36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}] +#set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}] +#set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}] +#set_property -dict {LOC J38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}] +#set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}] +#set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}] +#set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}] +#set_property -dict {LOC B39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}] +#set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}] +#set_property -dict {LOC C37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}] +#set_property -dict {LOC C38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}] + +# DDR4 C3 +#set_property -dict {LOC K15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}] +#set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}] +#set_property -dict {LOC F14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}] +#set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}] +#set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}] +#set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}] +#set_property -dict {LOC B14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}] +#set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}] +#set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}] +#set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}] +#set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}] +#set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}] +#set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}] +#set_property -dict {LOC K16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}] +#set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}] +#set_property -dict {LOC E15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}] +#set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}] +#set_property -dict {LOC J15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}] +#set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}] +#set_property -dict {LOC D13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}] +#set_property -dict {LOC J13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}] +#set_property -dict {LOC L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[0]}] +#set_property -dict {LOC L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[0]}] +#set_property -dict {LOC G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[1]}] +#set_property -dict {LOC G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[1]}] +#set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}] +#set_property -dict {LOC L15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}] +#set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}] +#set_property -dict {LOC D16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}] +#set_property -dict {LOC M14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}] +#set_property -dict {LOC M13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}] +#set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}] +#set_property -dict {LOC C16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}] +#set_property -dict {LOC E16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}] +#set_property -dict {LOC J14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}] +#set_property -dict {LOC D21 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}] + +#set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}] +#set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}] +#set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}] +#set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}] +#set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}] +#set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}] +#set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}] +#set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}] +#set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}] +#set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}] +#set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}] +#set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}] +#set_property -dict {LOC L24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}] +#set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}] +#set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}] +#set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}] +#set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}] +#set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}] +#set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}] +#set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}] +#set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}] +#set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}] +#set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}] +#set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}] +#set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}] +#set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}] +#set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}] +#set_property -dict {LOC R17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}] +#set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}] +#set_property -dict {LOC T20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}] +#set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}] +#set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}] +#set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}] +#set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}] +#set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}] +#set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}] +#set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}] +#set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}] +#set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}] +#set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}] +#set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}] +#set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}] +#set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}] +#set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}] +#set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}] +#set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}] +#set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}] +#set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}] +#set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}] +#set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}] +#set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}] +#set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}] +#set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}] +#set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}] +#set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}] +#set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}] +#set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}] +#set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}] +#set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}] +#set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}] +#set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}] +#set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}] +#set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}] +#set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}] +#set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}] +#set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}] +#set_property -dict {LOC N13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}] +#set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}] +#set_property -dict {LOC T15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}] +#set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}] +#set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}] +#set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}] +#set_property -dict {LOC T22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}] +#set_property -dict {LOC R22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}] +#set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}] +#set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}] +#set_property -dict {LOC J21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}] +#set_property -dict {LOC H21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}] +#set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}] +#set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}] +#set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}] +#set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}] +#set_property -dict {LOC K18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}] +#set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}] +#set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}] +#set_property -dict {LOC P18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}] +#set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}] +#set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}] +#set_property -dict {LOC A25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}] +#set_property -dict {LOC A24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}] +#set_property -dict {LOC D24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}] +#set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}] +#set_property -dict {LOC C17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}] +#set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}] +#set_property -dict {LOC B19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}] +#set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}] +#set_property -dict {LOC F18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}] +#set_property -dict {LOC F17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}] +#set_property -dict {LOC H19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}] +#set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}] +#set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}] +#set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}] +#set_property -dict {LOC H23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}] +#set_property -dict {LOC H22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}] +#set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}] +#set_property -dict {LOC P15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}] +#set_property -dict {LOC T13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}] +#set_property -dict {LOC R13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}] diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/fpga/Makefile b/fpga/lib/eth/example/VCU1525/fpga_25g/fpga/Makefile similarity index 99% rename from fpga/lib/eth/example/VCU1525/fpga_10g/fpga/Makefile rename to fpga/lib/eth/example/VCU1525/fpga_25g/fpga/Makefile index 151925631..16f015da3 100644 --- a/fpga/lib/eth/example/VCU1525/fpga_10g/fpga/Makefile +++ b/fpga/lib/eth/example/VCU1525/fpga_25g/fpga/Makefile @@ -59,6 +59,9 @@ XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES += ip/eth_xcvr_gt.tcl +# Configuration +CONFIG_TCL_FILES = ./config.tcl + include ../common/vivado.mk program: $(FPGA_TOP).bit diff --git a/fpga/lib/eth/example/VCU1525/fpga_25g/fpga/config.tcl b/fpga/lib/eth/example/VCU1525/fpga_25g/fpga/config.tcl new file mode 100644 index 000000000..756e2b3a1 --- /dev/null +++ b/fpga/lib/eth/example/VCU1525/fpga_25g/fpga/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/VCU1525/fpga_25g/fpga_10g/Makefile b/fpga/lib/eth/example/VCU1525/fpga_25g/fpga_10g/Makefile new file mode 100644 index 000000000..16f015da3 --- /dev/null +++ b/fpga/lib/eth/example/VCU1525/fpga_25g/fpga_10g/Makefile @@ -0,0 +1,114 @@ + +# FPGA settings +FPGA_PART = xcvu9p-fsgd2104-2L-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/debounce_switch.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete_64.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v +SYN_FILES += lib/eth/rtl/udp_64.v +SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v +SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v +SYN_FILES += lib/eth/rtl/ip_complete_64.v +SYN_FILES += lib/eth/rtl/ip_64.v +SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v +SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl + +# IP +IP_TCL_FILES += ip/eth_xcvr_gt.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%.mcs %.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x04000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + diff --git a/fpga/lib/eth/example/VCU1525/fpga_25g/fpga_10g/config.tcl b/fpga/lib/eth/example/VCU1525/fpga_25g/fpga_10g/config.tcl new file mode 100644 index 000000000..90aa4caeb --- /dev/null +++ b/fpga/lib/eth/example/VCU1525/fpga_25g/fpga_10g/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/lib/eth/example/VCU1525/fpga_25g/ip/eth_xcvr_gt.tcl similarity index 100% rename from fpga/lib/eth/example/VCU1525/fpga_10g/ip/eth_xcvr_gt.tcl rename to fpga/lib/eth/example/VCU1525/fpga_25g/ip/eth_xcvr_gt.tcl diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/lib/eth b/fpga/lib/eth/example/VCU1525/fpga_25g/lib/eth similarity index 100% rename from fpga/lib/eth/example/VCU1525/fpga_10g/lib/eth rename to fpga/lib/eth/example/VCU1525/fpga_25g/lib/eth diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/rtl/debounce_switch.v b/fpga/lib/eth/example/VCU1525/fpga_25g/rtl/debounce_switch.v similarity index 100% rename from fpga/lib/eth/example/VCU118/fpga_10g/rtl/debounce_switch.v rename to fpga/lib/eth/example/VCU1525/fpga_25g/rtl/debounce_switch.v diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/fpga/lib/eth/example/VCU1525/fpga_25g/rtl/eth_xcvr_phy_wrapper.v similarity index 100% rename from fpga/lib/eth/example/VCU1525/fpga_10g/rtl/eth_xcvr_phy_wrapper.v rename to fpga/lib/eth/example/VCU1525/fpga_25g/rtl/eth_xcvr_phy_wrapper.v diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/rtl/fpga.v b/fpga/lib/eth/example/VCU1525/fpga_25g/rtl/fpga.v similarity index 100% rename from fpga/lib/eth/example/VCU1525/fpga_10g/rtl/fpga.v rename to fpga/lib/eth/example/VCU1525/fpga_25g/rtl/fpga.v diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/rtl/fpga_core.v b/fpga/lib/eth/example/VCU1525/fpga_25g/rtl/fpga_core.v similarity index 100% rename from fpga/lib/eth/example/VCU1525/fpga_10g/rtl/fpga_core.v rename to fpga/lib/eth/example/VCU1525/fpga_25g/rtl/fpga_core.v diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/rtl/sync_signal.v b/fpga/lib/eth/example/VCU1525/fpga_25g/rtl/sync_signal.v similarity index 100% rename from fpga/lib/eth/example/VCU118/fpga_10g/rtl/sync_signal.v rename to fpga/lib/eth/example/VCU1525/fpga_25g/rtl/sync_signal.v diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/VCU1525/fpga_25g/tb/fpga_core/Makefile similarity index 100% rename from fpga/lib/eth/example/VCU1525/fpga_10g/tb/fpga_core/Makefile rename to fpga/lib/eth/example/VCU1525/fpga_25g/tb/fpga_core/Makefile diff --git a/fpga/lib/eth/example/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py new file mode 100644 index 000000000..d90e185ee --- /dev/null +++ b/fpga/lib/eth/example/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -0,0 +1,229 @@ +""" + +Copyright (c) 2020 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +""" + +import logging +import os + +from scapy.layers.l2 import Ether, ARP +from scapy.layers.inet import IP, UDP + +import cocotb_test.simulator + +import cocotb +from cocotb.log import SimLog +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge + +from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = SimLog("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 2.56, units="ns").start()) + + # Ethernet + self.qsfp_source = [] + self.qsfp_sink = [] + + for x in range(2): + sources = [] + sinks = [] + for y in range(1, 5): + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_rx_clk_{y}"), 2.56, units="ns").start()) + source = XgmiiSource(getattr(dut, f"qsfp{x}_rxd_{y}"), getattr(dut, f"qsfp{x}_rxc_{y}"), getattr(dut, f"qsfp{x}_rx_clk_{y}"), getattr(dut, f"qsfp{x}_rx_rst_{y}")) + sources.append(source) + cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_tx_clk_{y}"), 2.56, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"qsfp{x}_txd_{y}"), getattr(dut, f"qsfp{x}_txc_{y}"), getattr(dut, f"qsfp{x}_tx_clk_{y}"), getattr(dut, f"qsfp{x}_tx_rst_{y}")) + sinks.append(sink) + self.qsfp_source.append(sources) + self.qsfp_sink.append(sinks) + + dut.sw.setimmediatevalue(0) + + async def init(self): + + self.dut.rst.setimmediatevalue(0) + for x in range(2): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(0) + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(0) + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst.value = 1 + for x in range(2): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").value = 1 + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").value = 1 + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst.value = 0 + for x in range(2): + for y in range(1, 5): + getattr(self.dut, f"qsfp{x}_rx_rst_{y}").value = 0 + getattr(self.dut, f"qsfp{x}_tx_rst_{y}").value = 0 + + +@cocotb.test() +async def run_test(dut): + + tb = TB(dut) + + await tb.init() + + tb.log.info("test UDP RX packet") + + payload = bytes([x % 256 for x in range(256)]) + eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00') + ip = IP(src='192.168.1.100', dst='192.168.1.128') + udp = UDP(sport=5678, dport=1234) + test_pkt = eth / ip / udp / payload + + test_frame = XgmiiFrame.from_payload(test_pkt.build()) + + await tb.qsfp_source[0][0].send(test_frame) + + tb.log.info("receive ARP request") + + rx_frame = await tb.qsfp_sink[0][0].recv() + + rx_pkt = Ether(bytes(rx_frame.get_payload())) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + assert rx_pkt.dst == 'ff:ff:ff:ff:ff:ff' + assert rx_pkt.src == test_pkt.dst + assert rx_pkt[ARP].hwtype == 1 + assert rx_pkt[ARP].ptype == 0x0800 + assert rx_pkt[ARP].hwlen == 6 + assert rx_pkt[ARP].plen == 4 + assert rx_pkt[ARP].op == 1 + assert rx_pkt[ARP].hwsrc == test_pkt.dst + assert rx_pkt[ARP].psrc == test_pkt[IP].dst + assert rx_pkt[ARP].hwdst == '00:00:00:00:00:00' + assert rx_pkt[ARP].pdst == test_pkt[IP].src + + tb.log.info("send ARP response") + + eth = Ether(src=test_pkt.src, dst=test_pkt.dst) + arp = ARP(hwtype=1, ptype=0x0800, hwlen=6, plen=4, op=2, + hwsrc=test_pkt.src, psrc=test_pkt[IP].src, + hwdst=test_pkt.dst, pdst=test_pkt[IP].dst) + resp_pkt = eth / arp + + resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) + + await tb.qsfp_source[0][0].send(resp_frame) + + tb.log.info("receive UDP packet") + + rx_frame = await tb.qsfp_sink[0][0].recv() + + rx_pkt = Ether(bytes(rx_frame.get_payload())) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + assert rx_pkt.dst == test_pkt.src + assert rx_pkt.src == test_pkt.dst + assert rx_pkt[IP].dst == test_pkt[IP].src + assert rx_pkt[IP].src == test_pkt[IP].dst + assert rx_pkt[UDP].dport == test_pkt[UDP].sport + assert rx_pkt[UDP].sport == test_pkt[UDP].dport + assert rx_pkt[UDP].payload == test_pkt[UDP].payload + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'lib', 'axis', 'rtl')) +eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) + + +def test_fpga_core(request): + dut = "fpga_core" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, f"{dut}.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g_fifo.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), + os.path.join(eth_rtl_dir, "lfsr.v"), + os.path.join(eth_rtl_dir, "eth_axis_rx.v"), + os.path.join(eth_rtl_dir, "eth_axis_tx.v"), + os.path.join(eth_rtl_dir, "udp_complete_64.v"), + os.path.join(eth_rtl_dir, "udp_checksum_gen_64.v"), + os.path.join(eth_rtl_dir, "udp_64.v"), + os.path.join(eth_rtl_dir, "udp_ip_rx_64.v"), + os.path.join(eth_rtl_dir, "udp_ip_tx_64.v"), + os.path.join(eth_rtl_dir, "ip_complete_64.v"), + os.path.join(eth_rtl_dir, "ip_64.v"), + os.path.join(eth_rtl_dir, "ip_eth_rx_64.v"), + os.path.join(eth_rtl_dir, "ip_eth_tx_64.v"), + os.path.join(eth_rtl_dir, "ip_arb_mux.v"), + os.path.join(eth_rtl_dir, "arp.v"), + os.path.join(eth_rtl_dir, "arp_cache.v"), + os.path.join(eth_rtl_dir, "arp_eth_rx.v"), + os.path.join(eth_rtl_dir, "arp_eth_tx.v"), + os.path.join(eth_rtl_dir, "eth_arb_mux.v"), + os.path.join(axis_rtl_dir, "arbiter.v"), + os.path.join(axis_rtl_dir, "priority_encoder.v"), + os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + ] + + parameters = {} + + # parameters['A'] = val + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/fpga/lib/eth/example/ZCU102/fpga/common/vivado.mk b/fpga/lib/eth/example/ZCU102/fpga/common/vivado.mk index 21e6a5fed..1402e2382 100644 --- a/fpga/lib/eth/example/ZCU102/fpga/common/vivado.mk +++ b/fpga/lib/eth/example/ZCU102/fpga/common/vivado.mk @@ -28,7 +28,7 @@ ################################################################### # phony targets -.PHONY: clean fpga +.PHONY: fpga vivado tmpclean clean distclean # prevent make from deleting intermediate files and reports .PRECIOUS: %.xpr %.bit %.mcs %.prm @@ -40,15 +40,16 @@ CONFIG ?= config.mk FPGA_TOP ?= fpga PROJECT ?= $(FPGA_TOP) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else - XDC_FILES_REL = $(FPGA_TOP).xdc + XDC_FILES_REL = $(PROJECT).xdc endif ################################################################### @@ -60,20 +61,20 @@ endif all: fpga -fpga: $(FPGA_TOP).bit +fpga: $(PROJECT).bit -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr -tmpclean: +tmpclean:: -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt -distclean: clean +distclean:: clean -rm -rf rev ################################################################### @@ -91,12 +92,17 @@ create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done -$(PROJECT).xpr: create_project.tcl +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) # synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr echo "open_project $(PROJECT).xpr" > run_synth.tcl echo "reset_run synth_1" >> run_synth.tcl echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl diff --git a/fpga/lib/eth/example/ZCU102/fpga/fpga.xdc b/fpga/lib/eth/example/ZCU102/fpga/fpga.xdc index 4393baeeb..6b37d6b6e 100644 --- a/fpga/lib/eth/example/ZCU102/fpga/fpga.xdc +++ b/fpga/lib/eth/example/ZCU102/fpga/fpga.xdc @@ -108,3 +108,57 @@ create_clock -period 6.400 -name sfp_mgt_refclk_0 [get_ports sfp_mgt_refclk_0_p] set_false_path -to [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b sfp2_tx_disable_b sfp3_tx_disable_b}] set_output_delay 0 [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b sfp2_tx_disable_b sfp3_tx_disable_b}] + +# DDR4 +# 1x MT40A256M16GE-075E +#set_property -dict {LOC AM8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[0]}] +#set_property -dict {LOC AM9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[1]}] +#set_property -dict {LOC AP8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[2]}] +#set_property -dict {LOC AN8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[3]}] +#set_property -dict {LOC AK10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[4]}] +#set_property -dict {LOC AJ10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[5]}] +#set_property -dict {LOC AP9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[6]}] +#set_property -dict {LOC AN9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[7]}] +#set_property -dict {LOC AP10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[8]}] +#set_property -dict {LOC AP11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[9]}] +#set_property -dict {LOC AM10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[10]}] +#set_property -dict {LOC AL10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[11]}] +#set_property -dict {LOC AM11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[12]}] +#set_property -dict {LOC AL11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[13]}] +#set_property -dict {LOC AJ7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[14]}] +#set_property -dict {LOC AL5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[15]}] +#set_property -dict {LOC AJ9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[16]}] +#set_property -dict {LOC AK12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[0]}] +#set_property -dict {LOC AJ12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[1]}] +#set_property -dict {LOC AK7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[0]}] +#set_property -dict {LOC AN7 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_t}] +#set_property -dict {LOC AP7 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_c}] +#set_property -dict {LOC AM3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cke}] +#set_property -dict {LOC AP2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cs_n}] +#set_property -dict {LOC AK8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_act_n}] +#set_property -dict {LOC AK9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_odt}] +#set_property -dict {LOC AP1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_par}] +#set_property -dict {LOC AH9 IOSTANDARD LVCMOS12 } [get_ports {ddr4_reset_n}] + +#set_property -dict {LOC AK4 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[0]}] ;# U2.G2 DQL0 +#set_property -dict {LOC AK5 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[1]}] ;# U2.F7 DQL1 +#set_property -dict {LOC AN4 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[2]}] ;# U2.H3 DQL2 +#set_property -dict {LOC AM4 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[3]}] ;# U2.H7 DQL3 +#set_property -dict {LOC AP4 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[4]}] ;# U2.H2 DQL4 +#set_property -dict {LOC AP5 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[5]}] ;# U2.H8 DQL5 +#set_property -dict {LOC AM5 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[6]}] ;# U2.J3 DQL6 +#set_property -dict {LOC AM6 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[7]}] ;# U2.J7 DQL7 +#set_property -dict {LOC AK2 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[8]}] ;# U2.A3 DQU0 +#set_property -dict {LOC AK3 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[9]}] ;# U2.B8 DQU1 +#set_property -dict {LOC AL1 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[10]}] ;# U2.C3 DQU2 +#set_property -dict {LOC AK1 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[11]}] ;# U2.C7 DQU3 +#set_property -dict {LOC AN1 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[12]}] ;# U2.C2 DQU4 +#set_property -dict {LOC AM1 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[13]}] ;# U2.C8 DQU5 +#set_property -dict {LOC AP3 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[14]}] ;# U2.D3 DQU6 +#set_property -dict {LOC AN3 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[15]}] ;# U2.D7 DQU7 +#set_property -dict {LOC AN6 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[0]}] ;# U2.G3 DQSL_T +#set_property -dict {LOC AP6 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[0]}] ;# U2.F3 DQSL_C +#set_property -dict {LOC AL3 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[1]}] ;# U2.B7 DQSU_T +#set_property -dict {LOC AL2 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[1]}] ;# U2.A7 DQSU_C +#set_property -dict {LOC AL6 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[0]}] ;# U2.E7 DML_B/DBIL_B +#set_property -dict {LOC AN2 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[1]}] ;# U2.E2 DMU_B/DBIU_B diff --git a/fpga/lib/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py index 78aca5d74..3986ebb17 100644 --- a/fpga/lib/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py @@ -48,25 +48,16 @@ class TB: cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) # Ethernet - cocotb.start_soon(Clock(dut.sfp0_rx_clk, 6.4, units="ns").start()) - self.sfp0_source = XgmiiSource(dut.sfp0_rxd, dut.sfp0_rxc, dut.sfp0_rx_clk, dut.sfp0_rx_rst) - cocotb.start_soon(Clock(dut.sfp0_tx_clk, 6.4, units="ns").start()) - self.sfp0_sink = XgmiiSink(dut.sfp0_txd, dut.sfp0_txc, dut.sfp0_tx_clk, dut.sfp0_tx_rst) + self.sfp_source = [] + self.sfp_sink = [] - cocotb.start_soon(Clock(dut.sfp1_rx_clk, 6.4, units="ns").start()) - self.sfp1_source = XgmiiSource(dut.sfp1_rxd, dut.sfp1_rxc, dut.sfp1_rx_clk, dut.sfp1_rx_rst) - cocotb.start_soon(Clock(dut.sfp1_tx_clk, 6.4, units="ns").start()) - self.sfp1_sink = XgmiiSink(dut.sfp1_txd, dut.sfp1_txc, dut.sfp1_tx_clk, dut.sfp1_tx_rst) - - cocotb.start_soon(Clock(dut.sfp2_rx_clk, 6.4, units="ns").start()) - self.sfp2_source = XgmiiSource(dut.sfp2_rxd, dut.sfp2_rxc, dut.sfp2_rx_clk, dut.sfp2_rx_rst) - cocotb.start_soon(Clock(dut.sfp2_tx_clk, 6.4, units="ns").start()) - self.sfp2_sink = XgmiiSink(dut.sfp2_txd, dut.sfp2_txc, dut.sfp2_tx_clk, dut.sfp2_tx_rst) - - cocotb.start_soon(Clock(dut.sfp3_rx_clk, 6.4, units="ns").start()) - self.sfp3_source = XgmiiSource(dut.sfp3_rxd, dut.sfp3_rxc, dut.sfp3_rx_clk, dut.sfp3_rx_rst) - cocotb.start_soon(Clock(dut.sfp3_tx_clk, 6.4, units="ns").start()) - self.sfp3_sink = XgmiiSink(dut.sfp3_txd, dut.sfp3_txc, dut.sfp3_tx_clk, dut.sfp3_tx_rst) + for y in range(4): + cocotb.start_soon(Clock(getattr(dut, f"sfp{y}_rx_clk"), 6.4, units="ns").start()) + source = XgmiiSource(getattr(dut, f"sfp{y}_rxd"), getattr(dut, f"sfp{y}_rxc"), getattr(dut, f"sfp{y}_rx_clk"), getattr(dut, f"sfp{y}_rx_rst")) + self.sfp_source.append(source) + cocotb.start_soon(Clock(getattr(dut, f"sfp{y}_tx_clk"), 6.4, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"sfp{y}_txd"), getattr(dut, f"sfp{y}_txc"), getattr(dut, f"sfp{y}_tx_clk"), getattr(dut, f"sfp{y}_tx_rst")) + self.sfp_sink.append(sink) dut.btnu.setimmediatevalue(0) dut.btnl.setimmediatevalue(0) @@ -80,40 +71,25 @@ class TB: async def init(self): self.dut.rst.setimmediatevalue(0) - self.dut.sfp0_rx_rst.setimmediatevalue(0) - self.dut.sfp0_tx_rst.setimmediatevalue(0) - self.dut.sfp1_rx_rst.setimmediatevalue(0) - self.dut.sfp1_tx_rst.setimmediatevalue(0) - self.dut.sfp2_rx_rst.setimmediatevalue(0) - self.dut.sfp2_tx_rst.setimmediatevalue(0) - self.dut.sfp3_rx_rst.setimmediatevalue(0) - self.dut.sfp3_tx_rst.setimmediatevalue(0) + for y in range(4): + getattr(self.dut, f"sfp{y}_rx_rst").setimmediatevalue(0) + getattr(self.dut, f"sfp{y}_tx_rst").setimmediatevalue(0) for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 1 - self.dut.sfp0_rx_rst.value = 1 - self.dut.sfp0_tx_rst.value = 1 - self.dut.sfp1_rx_rst.value = 1 - self.dut.sfp1_tx_rst.value = 1 - self.dut.sfp2_rx_rst.value = 1 - self.dut.sfp2_tx_rst.value = 1 - self.dut.sfp3_rx_rst.value = 1 - self.dut.sfp3_tx_rst.value = 1 + for y in range(4): + getattr(self.dut, f"sfp{y}_rx_rst").value = 1 + getattr(self.dut, f"sfp{y}_tx_rst").value = 1 for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 0 - self.dut.sfp0_rx_rst.value = 0 - self.dut.sfp0_tx_rst.value = 0 - self.dut.sfp1_rx_rst.value = 0 - self.dut.sfp1_tx_rst.value = 0 - self.dut.sfp2_rx_rst.value = 0 - self.dut.sfp2_tx_rst.value = 0 - self.dut.sfp3_rx_rst.value = 0 - self.dut.sfp3_tx_rst.value = 0 + for y in range(4): + getattr(self.dut, f"sfp{y}_rx_rst").value = 0 + getattr(self.dut, f"sfp{y}_tx_rst").value = 0 @cocotb.test() @@ -133,11 +109,11 @@ async def run_test(dut): test_frame = XgmiiFrame.from_payload(test_pkt.build()) - await tb.sfp0_source.send(test_frame) + await tb.sfp_source[0].send(test_frame) tb.log.info("receive ARP request") - rx_frame = await tb.sfp0_sink.recv() + rx_frame = await tb.sfp_sink[0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -165,11 +141,11 @@ async def run_test(dut): resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - await tb.sfp0_source.send(resp_frame) + await tb.sfp_source[0].send(resp_frame) tb.log.info("receive UDP packet") - rx_frame = await tb.sfp0_sink.recv() + rx_frame = await tb.sfp_sink[0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) diff --git a/fpga/lib/eth/example/ZCU106/fpga/common/vivado.mk b/fpga/lib/eth/example/ZCU106/fpga/common/vivado.mk index 21e6a5fed..1402e2382 100644 --- a/fpga/lib/eth/example/ZCU106/fpga/common/vivado.mk +++ b/fpga/lib/eth/example/ZCU106/fpga/common/vivado.mk @@ -28,7 +28,7 @@ ################################################################### # phony targets -.PHONY: clean fpga +.PHONY: fpga vivado tmpclean clean distclean # prevent make from deleting intermediate files and reports .PRECIOUS: %.xpr %.bit %.mcs %.prm @@ -40,15 +40,16 @@ CONFIG ?= config.mk FPGA_TOP ?= fpga PROJECT ?= $(FPGA_TOP) -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) else - XDC_FILES_REL = $(FPGA_TOP).xdc + XDC_FILES_REL = $(PROJECT).xdc endif ################################################################### @@ -60,20 +61,20 @@ endif all: fpga -fpga: $(FPGA_TOP).bit +fpga: $(PROJECT).bit -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr -tmpclean: +tmpclean:: -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl -clean: tmpclean +clean:: tmpclean -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt -distclean: clean +distclean:: clean -rm -rf rev ################################################################### @@ -91,12 +92,17 @@ create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done -$(PROJECT).xpr: create_project.tcl +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) # synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr echo "open_project $(PROJECT).xpr" > run_synth.tcl echo "reset_run synth_1" >> run_synth.tcl echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl diff --git a/fpga/lib/eth/example/ZCU106/fpga/fpga.xdc b/fpga/lib/eth/example/ZCU106/fpga/fpga.xdc index 64ff67e22..6e2a588ce 100644 --- a/fpga/lib/eth/example/ZCU106/fpga/fpga.xdc +++ b/fpga/lib/eth/example/ZCU106/fpga/fpga.xdc @@ -125,4 +125,125 @@ set_output_delay 0 [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b}] #set_false_path -from [get_ports {pcie_reset_n}] #set_input_delay 0 [get_ports {pcie_reset_n}] +# DDR4 +# 4x MT40A256M16GE-075E +#set_property -dict {LOC AK9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[0]}] +#set_property -dict {LOC AG11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[1]}] +#set_property -dict {LOC AJ10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[2]}] +#set_property -dict {LOC AL8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[3]}] +#set_property -dict {LOC AK10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[4]}] +#set_property -dict {LOC AH8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[5]}] +#set_property -dict {LOC AJ9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[6]}] +#set_property -dict {LOC AG8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[7]}] +#set_property -dict {LOC AH9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[8]}] +#set_property -dict {LOC AG10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[9]}] +#set_property -dict {LOC AH13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[10]}] +#set_property -dict {LOC AG9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[11]}] +#set_property -dict {LOC AM13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[12]}] +#set_property -dict {LOC AF8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[13]}] +#set_property -dict {LOC AC12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[14]}] +#set_property -dict {LOC AE12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[15]}] +#set_property -dict {LOC AF11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[16]}] +#set_property -dict {LOC AK8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[0]}] +#set_property -dict {LOC AL12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[1]}] +#set_property -dict {LOC AE14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[0]}] +#set_property -dict {LOC AH11 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_t}] +#set_property -dict {LOC AJ11 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_c}] +#set_property -dict {LOC AB13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cke}] +#set_property -dict {LOC AD12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cs_n}] +#set_property -dict {LOC AD14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_act_n}] +#set_property -dict {LOC AF10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_odt}] +#set_property -dict {LOC AC13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_par}] +#set_property -dict {LOC AF12 IOSTANDARD LVCMOS12 } [get_ports {ddr4_reset_n}] +#set_property -dict {LOC AF16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[0]}] ;# U101.G2 DQL0 +#set_property -dict {LOC AF18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[1]}] ;# U101.F7 DQL1 +#set_property -dict {LOC AG15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[2]}] ;# U101.H3 DQL2 +#set_property -dict {LOC AF17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[3]}] ;# U101.H7 DQL3 +#set_property -dict {LOC AF15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[4]}] ;# U101.H2 DQL4 +#set_property -dict {LOC AG18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[5]}] ;# U101.H8 DQL5 +#set_property -dict {LOC AG14 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[6]}] ;# U101.J3 DQL6 +#set_property -dict {LOC AE17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[7]}] ;# U101.J7 DQL7 +#set_property -dict {LOC AA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[8]}] ;# U101.A3 DQU0 +#set_property -dict {LOC AC16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[9]}] ;# U101.B8 DQU1 +#set_property -dict {LOC AB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[10]}] ;# U101.C3 DQU2 +#set_property -dict {LOC AD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[11]}] ;# U101.C7 DQU3 +#set_property -dict {LOC AB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[12]}] ;# U101.C2 DQU4 +#set_property -dict {LOC AC17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[13]}] ;# U101.C8 DQU5 +#set_property -dict {LOC AB14 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[14]}] ;# U101.D3 DQU6 +#set_property -dict {LOC AD17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[15]}] ;# U101.D7 DQU7 +#set_property -dict {LOC AH14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[0]}] ;# U101.G3 DQSL_T +#set_property -dict {LOC AJ14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[0]}] ;# U101.F3 DQSL_C +#set_property -dict {LOC AA16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[1]}] ;# U101.B7 DQSU_T +#set_property -dict {LOC AA15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[1]}] ;# U101.A7 DQSU_C +#set_property -dict {LOC AH18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[0]}] ;# U101.E7 DML_B/DBIL_B +#set_property -dict {LOC AD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[1]}] ;# U101.E2 DMU_B/DBIU_B + +#set_property -dict {LOC AJ16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[16]}] ;# U99.G2 DQL0 +#set_property -dict {LOC AJ17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[17]}] ;# U99.F7 DQL1 +#set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[18]}] ;# U99.H3 DQL2 +#set_property -dict {LOC AK17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[19]}] ;# U99.H7 DQL3 +#set_property -dict {LOC AJ15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[20]}] ;# U99.H2 DQL4 +#set_property -dict {LOC AK18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[21]}] ;# U99.H8 DQL5 +#set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[22]}] ;# U99.J3 DQL6 +#set_property -dict {LOC AL18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[23]}] ;# U99.J7 DQL7 +#set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[24]}] ;# U99.A3 DQU0 +#set_property -dict {LOC AP16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[25]}] ;# U99.B8 DQU1 +#set_property -dict {LOC AP15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[26]}] ;# U99.C3 DQU2 +#set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[27]}] ;# U99.C7 DQU3 +#set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[28]}] ;# U99.C2 DQU4 +#set_property -dict {LOC AM18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[29]}] ;# U99.C8 DQU5 +#set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[30]}] ;# U99.D3 DQU6 +#set_property -dict {LOC AN18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[31]}] ;# U99.D7 DQU7 +#set_property -dict {LOC AK15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[2]}] ;# U99.G3 DQSL_T +#set_property -dict {LOC AK14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[2]}] ;# U99.F3 DQSL_C +#set_property -dict {LOC AM14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[3]}] ;# U99.B7 DQSU_T +#set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[3]}] ;# U99.A7 DQSU_C +#set_property -dict {LOC AM16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[2]}] ;# U99.E7 DML_B/DBIL_B +#set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[3]}] ;# U99.E2 DMU_B/DBIU_B + +#set_property -dict {LOC AB19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[32]}] ;# U100.G2 DQL0 +#set_property -dict {LOC AD19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[33]}] ;# U100.F7 DQL1 +#set_property -dict {LOC AC18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[34]}] ;# U100.H3 DQL2 +#set_property -dict {LOC AC19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[35]}] ;# U100.H7 DQL3 +#set_property -dict {LOC AA20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[36]}] ;# U100.H2 DQL4 +#set_property -dict {LOC AE20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[37]}] ;# U100.H8 DQL5 +#set_property -dict {LOC AA19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[38]}] ;# U100.J3 DQL6 +#set_property -dict {LOC AD20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[39]}] ;# U100.J7 DQL7 +#set_property -dict {LOC AF22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[40]}] ;# U100.A3 DQU0 +#set_property -dict {LOC AH21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[41]}] ;# U100.B8 DQU1 +#set_property -dict {LOC AG19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[42]}] ;# U100.C3 DQU2 +#set_property -dict {LOC AG21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[43]}] ;# U100.C7 DQU3 +#set_property -dict {LOC AE24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[44]}] ;# U100.C2 DQU4 +#set_property -dict {LOC AG20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[45]}] ;# U100.C8 DQU5 +#set_property -dict {LOC AE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[46]}] ;# U100.D3 DQU6 +#set_property -dict {LOC AF21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[47]}] ;# U100.D7 DQU7 +#set_property -dict {LOC AA18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[4]}] ;# U100.G3 DQSL_T +#set_property -dict {LOC AB18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[4]}] ;# U100.F3 DQSL_C +#set_property -dict {LOC AF23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[5]}] ;# U100.B7 DQSU_T +#set_property -dict {LOC AG23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[5]}] ;# U100.A7 DQSU_C +#set_property -dict {LOC AE18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[4]}] ;# U100.E7 DML_B/DBIL_B +#set_property -dict {LOC AH22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[5]}] ;# U100.E2 DMU_B/DBIU_B + +#set_property -dict {LOC AL22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[48]}] ;# U2.G2 DQL0 +#set_property -dict {LOC AJ22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[49]}] ;# U2.F7 DQL1 +#set_property -dict {LOC AL23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[50]}] ;# U2.H3 DQL2 +#set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[51]}] ;# U2.H7 DQL3 +#set_property -dict {LOC AK20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[52]}] ;# U2.H2 DQL4 +#set_property -dict {LOC AJ19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[53]}] ;# U2.H8 DQL5 +#set_property -dict {LOC AK19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[54]}] ;# U2.J3 DQL6 +#set_property -dict {LOC AJ20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[55]}] ;# U2.J7 DQL7 +#set_property -dict {LOC AP22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[56]}] ;# U2.A3 DQU0 +#set_property -dict {LOC AN22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[57]}] ;# U2.B8 DQU1 +#set_property -dict {LOC AP21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[58]}] ;# U2.C3 DQU2 +#set_property -dict {LOC AP23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[59]}] ;# U2.C7 DQU3 +#set_property -dict {LOC AM19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[60]}] ;# U2.C2 DQU4 +#set_property -dict {LOC AM23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[61]}] ;# U2.C8 DQU5 +#set_property -dict {LOC AN19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[62]}] ;# U2.D3 DQU6 +#set_property -dict {LOC AN23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[63]}] ;# U2.D7 DQU7 +#set_property -dict {LOC AK22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[6]}] ;# U2.G3 DQSL_T +#set_property -dict {LOC AK23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[6]}] ;# U2.F3 DQSL_C +#set_property -dict {LOC AM21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[7]}] ;# U2.B7 DQSU_T +#set_property -dict {LOC AN21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[7]}] ;# U2.A7 DQSU_C +#set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[6]}] ;# U2.E7 DML_B/DBIL_B +#set_property -dict {LOC AP19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[7]}] ;# U2.E2 DMU_B/DBIU_B diff --git a/fpga/lib/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py index 14a213b12..91d58d39d 100644 --- a/fpga/lib/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/lib/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py @@ -48,15 +48,16 @@ class TB: cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) # Ethernet - cocotb.start_soon(Clock(dut.sfp0_rx_clk, 6.4, units="ns").start()) - self.sfp0_source = XgmiiSource(dut.sfp0_rxd, dut.sfp0_rxc, dut.sfp0_rx_clk, dut.sfp0_rx_rst) - cocotb.start_soon(Clock(dut.sfp0_tx_clk, 6.4, units="ns").start()) - self.sfp0_sink = XgmiiSink(dut.sfp0_txd, dut.sfp0_txc, dut.sfp0_tx_clk, dut.sfp0_tx_rst) + self.sfp_source = [] + self.sfp_sink = [] - cocotb.start_soon(Clock(dut.sfp1_rx_clk, 6.4, units="ns").start()) - self.sfp1_source = XgmiiSource(dut.sfp1_rxd, dut.sfp1_rxc, dut.sfp1_rx_clk, dut.sfp1_rx_rst) - cocotb.start_soon(Clock(dut.sfp1_tx_clk, 6.4, units="ns").start()) - self.sfp1_sink = XgmiiSink(dut.sfp1_txd, dut.sfp1_txc, dut.sfp1_tx_clk, dut.sfp1_tx_rst) + for y in range(2): + cocotb.start_soon(Clock(getattr(dut, f"sfp{y}_rx_clk"), 6.4, units="ns").start()) + source = XgmiiSource(getattr(dut, f"sfp{y}_rxd"), getattr(dut, f"sfp{y}_rxc"), getattr(dut, f"sfp{y}_rx_clk"), getattr(dut, f"sfp{y}_rx_rst")) + self.sfp_source.append(source) + cocotb.start_soon(Clock(getattr(dut, f"sfp{y}_tx_clk"), 6.4, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"sfp{y}_txd"), getattr(dut, f"sfp{y}_txc"), getattr(dut, f"sfp{y}_tx_clk"), getattr(dut, f"sfp{y}_tx_rst")) + self.sfp_sink.append(sink) dut.btnu.setimmediatevalue(0) dut.btnl.setimmediatevalue(0) @@ -70,28 +71,25 @@ class TB: async def init(self): self.dut.rst.setimmediatevalue(0) - self.dut.sfp0_rx_rst.setimmediatevalue(0) - self.dut.sfp0_tx_rst.setimmediatevalue(0) - self.dut.sfp1_rx_rst.setimmediatevalue(0) - self.dut.sfp1_tx_rst.setimmediatevalue(0) + for y in range(2): + getattr(self.dut, f"sfp{y}_rx_rst").setimmediatevalue(0) + getattr(self.dut, f"sfp{y}_tx_rst").setimmediatevalue(0) for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 1 - self.dut.sfp0_rx_rst.value = 1 - self.dut.sfp0_tx_rst.value = 1 - self.dut.sfp1_rx_rst.value = 1 - self.dut.sfp1_tx_rst.value = 1 + for y in range(2): + getattr(self.dut, f"sfp{y}_rx_rst").value = 1 + getattr(self.dut, f"sfp{y}_tx_rst").value = 1 for k in range(10): await RisingEdge(self.dut.clk) self.dut.rst.value = 0 - self.dut.sfp0_rx_rst.value = 0 - self.dut.sfp0_tx_rst.value = 0 - self.dut.sfp1_rx_rst.value = 0 - self.dut.sfp1_tx_rst.value = 0 + for y in range(2): + getattr(self.dut, f"sfp{y}_rx_rst").value = 0 + getattr(self.dut, f"sfp{y}_tx_rst").value = 0 @cocotb.test() @@ -111,11 +109,11 @@ async def run_test(dut): test_frame = XgmiiFrame.from_payload(test_pkt.build()) - await tb.sfp0_source.send(test_frame) + await tb.sfp_source[0].send(test_frame) tb.log.info("receive ARP request") - rx_frame = await tb.sfp0_sink.recv() + rx_frame = await tb.sfp_sink[0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) @@ -143,11 +141,11 @@ async def run_test(dut): resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - await tb.sfp0_source.send(resp_frame) + await tb.sfp_source[0].send(resp_frame) tb.log.info("receive UDP packet") - rx_frame = await tb.sfp0_sink.recv() + rx_frame = await tb.sfp_sink[0].recv() rx_pkt = Ether(bytes(rx_frame.get_payload())) diff --git a/fpga/lib/eth/example/fb2CG/fpga_10g/Makefile b/fpga/lib/eth/example/fb2CG/fpga_10g/Makefile deleted file mode 100644 index f504bd06f..000000000 --- a/fpga/lib/eth/example/fb2CG/fpga_10g/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# Targets -TARGETS:= - -# Subdirectories -SUBDIRS = fpga -SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) - -# Rules -.PHONY: all -all: $(SUBDIRS) $(TARGETS) - -.PHONY: $(SUBDIRS) -$(SUBDIRS): - cd $@ && $(MAKE) - -.PHONY: $(SUBDIRS_CLEAN) -$(SUBDIRS_CLEAN): - cd $(@:.clean=) && $(MAKE) clean - -.PHONY: clean -clean: $(SUBDIRS_CLEAN) - -rm -rf $(TARGETS) - -program: - #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit diff --git a/fpga/lib/eth/example/fb2CG/fpga_10g/common/vivado.mk b/fpga/lib/eth/example/fb2CG/fpga_10g/common/vivado.mk deleted file mode 100644 index 21e6a5fed..000000000 --- a/fpga/lib/eth/example/fb2CG/fpga_10g/common/vivado.mk +++ /dev/null @@ -1,131 +0,0 @@ -################################################################### -# -# Xilinx Vivado FPGA Makefile -# -# Copyright (c) 2016 Alex Forencich -# -################################################################### -# -# Parameters: -# FPGA_TOP - Top module name -# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) -# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) -# SYN_FILES - space-separated list of source files -# INC_FILES - space-separated list of include files -# XDC_FILES - space-separated list of timing constraint files -# XCI_FILES - space-separated list of IP XCI files -# -# Example: -# -# FPGA_TOP = fpga -# FPGA_FAMILY = VirtexUltrascale -# FPGA_DEVICE = xcvu095-ffva2104-2-e -# SYN_FILES = rtl/fpga.v -# XDC_FILES = fpga.xdc -# XCI_FILES = ip/pcspma.xci -# include ../common/vivado.mk -# -################################################################### - -# phony targets -.PHONY: clean fpga - -# prevent make from deleting intermediate files and reports -.PRECIOUS: %.xpr %.bit %.mcs %.prm -.SECONDARY: - -CONFIG ?= config.mk --include ../$(CONFIG) - -FPGA_TOP ?= fpga -PROJECT ?= $(FPGA_TOP) - -SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) -INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) -XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) - -ifdef XDC_FILES - XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) -else - XDC_FILES_REL = $(FPGA_TOP).xdc -endif - -################################################################### -# Main Targets -# -# all: build everything -# clean: remove output files and project files -################################################################### - -all: fpga - -fpga: $(FPGA_TOP).bit - -vivado: $(FPGA_TOP).xpr - vivado $(FPGA_TOP).xpr - -tmpclean: - -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl - -clean: tmpclean - -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl - -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt - -distclean: clean - -rm -rf rev - -################################################################### -# Target implementations -################################################################### - -# Vivado project file -create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) - rm -rf defines.v - touch defines.v - for x in $(DEFS); do echo '`define' $$x >> defines.v; done - echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ - echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ - echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ - echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ - for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done - for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done - -$(PROJECT).xpr: create_project.tcl - vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) - -# synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) - echo "open_project $(PROJECT).xpr" > run_synth.tcl - echo "reset_run synth_1" >> run_synth.tcl - echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl - echo "wait_on_run synth_1" >> run_synth.tcl - vivado -nojournal -nolog -mode batch -source run_synth.tcl - -# implementation run -$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp - echo "open_project $(PROJECT).xpr" > run_impl.tcl - echo "reset_run impl_1" >> run_impl.tcl - echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl - echo "wait_on_run impl_1" >> run_impl.tcl - echo "open_run impl_1" >> run_impl.tcl - echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl - echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl - vivado -nojournal -nolog -mode batch -source run_impl.tcl - -# bit file -$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp - echo "open_project $(PROJECT).xpr" > generate_bit.tcl - echo "open_run impl_1" >> generate_bit.tcl - echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl - echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl - vivado -nojournal -nolog -mode batch -source generate_bit.tcl - ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi - mkdir -p rev - COUNT=100; \ - while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ - do COUNT=$$((COUNT+1)); done; \ - cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/lib/eth/example/fb2CG/fpga_10g/fpga.xdc b/fpga/lib/eth/example/fb2CG/fpga_10g/fpga.xdc deleted file mode 100644 index e4e426737..000000000 --- a/fpga/lib/eth/example/fb2CG/fpga_10g/fpga.xdc +++ /dev/null @@ -1,266 +0,0 @@ -# XDC constraints for the fb2CG@KU15P -# part: xcku15p-ffve1760-2-e - -# General configuration -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design] -set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] -set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] -set_property CONFIG_MODE SPIx4 [current_design] -set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] - -# System clocks -# init clock 50 MHz -set_property -dict {LOC E7 IOSTANDARD LVCMOS18} [get_ports init_clk] -create_clock -period 20.000 -name init_clk [get_ports init_clk] - -# E7 is not a global clock capable input, so need to set CLOCK_DEDICATED_ROUTE to satisfy DRC -#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets init_clk_ibuf_inst/O] -set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets init_clk_bufg] - -# DDR4 refclk1 -#set_property -dict {LOC AT32 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1_p] -#set_property -dict {LOC AU32 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1_n] -#create_clock -period 3.750 -name clk_ddr4_refclk1 [get_ports clk_ddr4_refclk1_p] - -# DDR4 refclk2 -#set_property -dict {LOC G29 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_p] -#set_property -dict {LOC G28 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_n] -#create_clock -period 3.750 -name clk_ddr4_refclk2 [get_ports clk_ddr4_refclk1_p] - -# LEDs -set_property -dict {LOC C4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports led_sreg_d] -set_property -dict {LOC B3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports led_sreg_ld] -set_property -dict {LOC G3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports led_sreg_clk] -set_property -dict {LOC C5 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_bmc[0]}] -set_property -dict {LOC C6 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_bmc[1]}] -set_property -dict {LOC D3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {led_exp[0]}] -set_property -dict {LOC D4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {led_exp[1]}] - -set_false_path -to [get_ports {led_sreg_d led_sreg_ld led_sreg_clk led_bmc[*] led_exp[*]}] -set_output_delay 0 [get_ports {led_sreg_d led_sreg_ld led_sreg_clk led_bmc[*] led_exp[*]}] - -# GPIO -#set_property -dict {LOC B4 IOSTANDARD LVCMOS33} [get_ports pps_in] ;# from SMA J6 via Q1 (inverted) -#set_property -dict {LOC A4 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 4} [get_ports pps_out] ;# to SMA J6 via U4 and U5, and u.FL J7 (PPS OUT) via U3 -#set_property -dict {LOC A3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports pps_out_en] ; # to U5 IN (connects pps_out to SMA J6 when high) -#set_property -dict {LOC H2 IOSTANDARD LVCMOS33} [get_ports misc_ucoax] ; from u.FL J5 (PPS IN) - -#set_false_path -to [get_ports {pps_out pps_out_en}] -#set_output_delay 0 [get_ports {pps_out pps_out_en}] -#set_false_path -from [get_ports {pps_in}] -#set_input_delay 0 [get_ports {pps_in}] - -# BMC interface -#set_property -dict {LOC D7 IOSTANDARD LVCMOS18} [get_ports bmc_miso] -#set_property -dict {LOC J4 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports bmc_nss] -#set_property -dict {LOC B6 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports bmc_clk] -#set_property -dict {LOC D5 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports bmc_mosi] -#set_property -dict {LOC H4 IOSTANDARD LVCMOS18} [get_ports bmc_int] - -#set_false_path -to [get_ports {bmc_nss bmc_clk bmc_mosi}] -#set_output_delay 0 [get_ports {bmc_nss bmc_clk bmc_mosi}] -#set_false_path -from [get_ports {bmc_miso bmc_int}] -#set_input_delay 0 [get_ports {bmc_miso bmc_int}] - -# Board status -#set_property -dict {LOC J2 IOSTANDARD LVCMOS33} [get_ports {fan_tacho[0]}] -#set_property -dict {LOC J3 IOSTANDARD LVCMOS33} [get_ports {fan_tacho[1]}] -set_property -dict {LOC A6 IOSTANDARD LVCMOS18} [get_ports {pg[0]}] -set_property -dict {LOC C7 IOSTANDARD LVCMOS18} [get_ports {pg[1]}] -#set_property -dict {LOC E2 IOSTANDARD LVCMOS33} [get_ports pwrbrk] - -set_false_path -from [get_ports {pg[*]}] -set_input_delay 0 [get_ports {pg[*]}] - -# QSFP28 Interfaces -set_property -dict {LOC Y39 } [get_ports qsfp_0_rx_0_p] ;# MGTYRXP0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC Y40 } [get_ports qsfp_0_rx_0_n] ;# MGTYRXN0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC Y34 } [get_ports qsfp_0_tx_0_p] ;# MGTYTXP0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC Y35 } [get_ports qsfp_0_tx_0_n] ;# MGTYTXN0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC W41 } [get_ports qsfp_0_rx_1_p] ;# MGTYRXP1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC W42 } [get_ports qsfp_0_rx_1_n] ;# MGTYRXN1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC W36 } [get_ports qsfp_0_tx_1_p] ;# MGTYTXP1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC W37 } [get_ports qsfp_0_tx_1_n] ;# MGTYTXN1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC V39 } [get_ports qsfp_0_rx_2_p] ;# MGTYRXP2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC V40 } [get_ports qsfp_0_rx_2_n] ;# MGTYRXN2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC V34 } [get_ports qsfp_0_tx_2_p] ;# MGTYTXP2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC V35 } [get_ports qsfp_0_tx_2_n] ;# MGTYTXN2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC U41 } [get_ports qsfp_0_rx_3_p] ;# MGTYRXP3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC U42 } [get_ports qsfp_0_rx_3_n] ;# MGTYRXN3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC U36 } [get_ports qsfp_0_tx_3_p] ;# MGTYTXP3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC U37 } [get_ports qsfp_0_tx_3_n] ;# MGTYTXN3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 -set_property -dict {LOC W32 } [get_ports qsfp_0_mgt_refclk_p] ;# MGTREFCLK0P_130 from U28 -set_property -dict {LOC W33 } [get_ports qsfp_0_mgt_refclk_n] ;# MGTREFCLK0N_130 from U28 -set_property -dict {LOC B9 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_0_mod_prsnt_n] -set_property -dict {LOC A8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports qsfp_0_reset_n] -set_property -dict {LOC A9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports qsfp_0_lp_mode] -set_property -dict {LOC A10 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_0_intr_n] -#set_property -dict {LOC B8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports qsfp_0_i2c_scl] -#set_property -dict {LOC B7 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports qsfp_0_i2c_sda] - -# 161.1328125 MHz MGT reference clock -create_clock -period 6.206 -name qsfp_0_mgt_refclk [get_ports qsfp_0_mgt_refclk_p] - -set_false_path -to [get_ports {qsfp_0_reset_n qsfp_0_lp_mode}] -set_output_delay 0 [get_ports {qsfp_0_reset_n qsfp_0_lp_mode}] -set_false_path -from [get_ports {qsfp_0_mod_prsnt_n qsfp_0_intr_n}] -set_input_delay 0 [get_ports {qsfp_0_mod_prsnt_n qsfp_0_intr_n}] - -#set_false_path -to [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}] -#set_output_delay 0 [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}] -#set_false_path -from [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}] -#set_input_delay 0 [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}] - -set_property -dict {LOC M39 } [get_ports qsfp_1_rx_0_p] ;# MGTYRXP0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC M40 } [get_ports qsfp_1_rx_0_n] ;# MGTYRXN0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC M34 } [get_ports qsfp_1_tx_0_p] ;# MGTYTXP0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC M35 } [get_ports qsfp_1_tx_0_n] ;# MGTYTXN0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC L41 } [get_ports qsfp_1_rx_1_p] ;# MGTYRXP1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC L42 } [get_ports qsfp_1_rx_1_n] ;# MGTYRXN1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC L36 } [get_ports qsfp_1_tx_1_p] ;# MGTYTXP1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC L37 } [get_ports qsfp_1_tx_1_n] ;# MGTYTXN1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC K39 } [get_ports qsfp_1_rx_2_p] ;# MGTYRXP2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC K40 } [get_ports qsfp_1_rx_2_n] ;# MGTYRXN2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC K34 } [get_ports qsfp_1_tx_2_p] ;# MGTYTXP2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC K35 } [get_ports qsfp_1_tx_2_n] ;# MGTYTXN2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC J41 } [get_ports qsfp_1_rx_3_p] ;# MGTYRXP3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC J42 } [get_ports qsfp_1_rx_3_n] ;# MGTYRXN3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC J36 } [get_ports qsfp_1_tx_3_p] ;# MGTYTXP3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC J37 } [get_ports qsfp_1_tx_3_n] ;# MGTYTXN3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 -set_property -dict {LOC P30 } [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_132 from U28 -set_property -dict {LOC P31 } [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_132 from U28 -set_property -dict {LOC E10 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_1_mod_prsnt_n] -set_property -dict {LOC C10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports qsfp_1_reset_n] -set_property -dict {LOC D9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports qsfp_1_lp_mode] -set_property -dict {LOC D10 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_1_intr_n] -#set_property -dict {LOC C9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports qsfp_1_i2c_scl] -#set_property -dict {LOC D8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports qsfp_1_i2c_sda] - -# 161.1328125 MHz MGT reference clock -create_clock -period 6.206 -name qsfp_1_mgt_refclk [get_ports qsfp_1_mgt_refclk_p] - -set_false_path -to [get_ports {qsfp_1_reset_n qsfp_1_lp_mode}] -set_output_delay 0 [get_ports {qsfp_1_reset_n qsfp_1_lp_mode}] -set_false_path -from [get_ports {qsfp_1_mod_prsnt_n qsfp_1_intr_n}] -set_input_delay 0 [get_ports {qsfp_1_mod_prsnt_n qsfp_1_intr_n}] - -#set_false_path -to [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}] -#set_output_delay 0 [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}] -#set_false_path -from [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}] -#set_input_delay 0 [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}] - -# Expansion connector -#set_property -dict {LOC AG41} [get_ports {exp_rx_p[0]}] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 -#set_property -dict {LOC AG42} [get_ports {exp_rx_n[0]}] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 -#set_property -dict {LOC AG36} [get_ports {exp_tx_p[0]}] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 -#set_property -dict {LOC AG37} [get_ports {exp_tx_n[0]}] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 -#set_property -dict {LOC AH39} [get_ports {exp_rx_p[1]}] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 -#set_property -dict {LOC AH40} [get_ports {exp_rx_n[1]}] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 -#set_property -dict {LOC AH34} [get_ports {exp_tx_p[1]}] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 -#set_property -dict {LOC AH35} [get_ports {exp_tx_n[1]}] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 -#set_property -dict {LOC AJ41} [get_ports {exp_rx_p[2]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0 -#set_property -dict {LOC AJ42} [get_ports {exp_rx_n[2]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0 -#set_property -dict {LOC AJ36} [get_ports {exp_tx_p[2]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0 -#set_property -dict {LOC AJ37} [get_ports {exp_tx_n[2]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0 -#set_property -dict {LOC AK39} [get_ports {exp_rx_p[3]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0 -#set_property -dict {LOC AK40} [get_ports {exp_rx_n[3]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0 -#set_property -dict {LOC AK34} [get_ports {exp_tx_p[3]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0 -#set_property -dict {LOC AK35} [get_ports {exp_tx_n[3]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0 -#set_property -dict {LOC AL41} [get_ports {exp_rx_p[4]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0 -#set_property -dict {LOC AL42} [get_ports {exp_rx_n[4]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0 -#set_property -dict {LOC AL36} [get_ports {exp_tx_p[4]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0 -#set_property -dict {LOC AL37} [get_ports {exp_tx_n[4]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0 -#set_property -dict {LOC AM39} [get_ports {exp_rx_p[5]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0 -#set_property -dict {LOC AM40} [get_ports {exp_rx_n[5]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0 -#set_property -dict {LOC AM34} [get_ports {exp_tx_p[5]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0 -#set_property -dict {LOC AM35} [get_ports {exp_tx_n[5]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0 -#set_property -dict {LOC AL32} [get_ports exp_refclk_0_p] ;# MGTREFCLK0P_128 from U28 -#set_property -dict {LOC AL33} [get_ports exp_refclk_0_n] ;# MGTREFCLK0N_128 from U28 -#set_property -dict {LOC AG32} [get_ports exp_refclk_1_p] ;# MGTREFCLK0P_127 from U28 -#set_property -dict {LOC AG33} [get_ports exp_refclk_1_n] ;# MGTREFCLK0N_127 from U28 -#set_property -dict {LOC E3 IOSTANDARD LVCMOS33} [get_ports {exp_gpio[0]}] -#set_property -dict {LOC F3 IOSTANDARD LVCMOS33} [get_ports {exp_gpio[1]}] - -# 161.1328125 MHz MGT reference clock -#create_clock -period 6.206 -name exp_refclk_0 [get_ports exp_refclk_0_p] -#create_clock -period 6.206 -name exp_refclk_1 [get_ports exp_refclk_1_p] - -# PCIe Interface -#set_property -dict {LOC AG2 } [get_ports {pcie_rx_p[0]}] ;# MGTHRXP3_227 GTHE4_CHANNEL_X0Y15 / GTHE4_COMMON_X0Y3 -#set_property -dict {LOC AG1 } [get_ports {pcie_rx_n[0]}] ;# MGTHRXN3_227 GTHE4_CHANNEL_X0Y15 / GTHE4_COMMON_X0Y3 -#set_property -dict {LOC AG6 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_227 GTHE4_CHANNEL_X0Y15 / GTHE4_COMMON_X0Y3 -#set_property -dict {LOC AG5 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_227 GTHE4_CHANNEL_X0Y15 / GTHE4_COMMON_X0Y3 -#set_property -dict {LOC AH4 } [get_ports {pcie_rx_p[1]}] ;# MGTHRXP2_227 GTHE4_CHANNEL_X0Y14 / GTHE4_COMMON_X0Y3 -#set_property -dict {LOC AH3 } [get_ports {pcie_rx_n[1]}] ;# MGTHRXN2_227 GTHE4_CHANNEL_X0Y14 / GTHE4_COMMON_X0Y3 -#set_property -dict {LOC AH8 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_227 GTHE4_CHANNEL_X0Y14 / GTHE4_COMMON_X0Y3 -#set_property -dict {LOC AH7 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_227 GTHE4_CHANNEL_X0Y14 / GTHE4_COMMON_X0Y3 -#set_property -dict {LOC AJ2 } [get_ports {pcie_rx_p[2]}] ;# MGTHRXP1_227 GTHE4_CHANNEL_X0Y13 / GTHE4_COMMON_X0Y3 -#set_property -dict {LOC AJ1 } [get_ports {pcie_rx_n[2]}] ;# MGTHRXN1_227 GTHE4_CHANNEL_X0Y13 / GTHE4_COMMON_X0Y3 -#set_property -dict {LOC AJ6 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_227 GTHE4_CHANNEL_X0Y13 / GTHE4_COMMON_X0Y3 -#set_property -dict {LOC AJ5 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_227 GTHE4_CHANNEL_X0Y13 / GTHE4_COMMON_X0Y3 -#set_property -dict {LOC AK4 } [get_ports {pcie_rx_p[3]}] ;# MGTHRXP0_227 GTHE4_CHANNEL_X0Y12 / GTHE4_COMMON_X0Y3 -#set_property -dict {LOC AK3 } [get_ports {pcie_rx_n[3]}] ;# MGTHRXN0_227 GTHE4_CHANNEL_X0Y12 / GTHE4_COMMON_X0Y3 -#set_property -dict {LOC AK8 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_227 GTHE4_CHANNEL_X0Y12 / GTHE4_COMMON_X0Y3 -#set_property -dict {LOC AK7 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_227 GTHE4_CHANNEL_X0Y12 / GTHE4_COMMON_X0Y3 -#set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[4]}] ;# MGTHRXP3_226 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y2 -#set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[4]}] ;# MGTHRXN3_226 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y2 -#set_property -dict {LOC AL6 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_226 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y2 -#set_property -dict {LOC AL5 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_226 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y2 -#set_property -dict {LOC AM4 } [get_ports {pcie_rx_p[5]}] ;# MGTHRXP2_226 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y2 -#set_property -dict {LOC AM3 } [get_ports {pcie_rx_n[5]}] ;# MGTHRXN2_226 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y2 -#set_property -dict {LOC AM8 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_226 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y2 -#set_property -dict {LOC AM7 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_226 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y2 -#set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[6]}] ;# MGTHRXP1_226 GTHE4_CHANNEL_X0Y9 / GTHE4_COMMON_X0Y2 -#set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[6]}] ;# MGTHRXN1_226 GTHE4_CHANNEL_X0Y9 / GTHE4_COMMON_X0Y2 -#set_property -dict {LOC AN6 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_226 GTHE4_CHANNEL_X0Y9 / GTHE4_COMMON_X0Y2 -#set_property -dict {LOC AN5 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_226 GTHE4_CHANNEL_X0Y9 / GTHE4_COMMON_X0Y2 -#set_property -dict {LOC AP4 } [get_ports {pcie_rx_p[7]}] ;# MGTHRXP0_226 GTHE4_CHANNEL_X0Y8 / GTHE4_COMMON_X0Y2 -#set_property -dict {LOC AP3 } [get_ports {pcie_rx_n[7]}] ;# MGTHRXN0_226 GTHE4_CHANNEL_X0Y8 / GTHE4_COMMON_X0Y2 -#set_property -dict {LOC AP8 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_226 GTHE4_CHANNEL_X0Y8 / GTHE4_COMMON_X0Y2 -#set_property -dict {LOC AP7 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_226 GTHE4_CHANNEL_X0Y8 / GTHE4_COMMON_X0Y2 -#set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[8]}] ;# MGTHRXP3_225 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1 -#set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[8]}] ;# MGTHRXN3_225 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1 -#set_property -dict {LOC AR6 } [get_ports {pcie_tx_p[8]}] ;# MGTHTXP3_225 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1 -#set_property -dict {LOC AR5 } [get_ports {pcie_tx_n[8]}] ;# MGTHTXN3_225 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1 -#set_property -dict {LOC AT4 } [get_ports {pcie_rx_p[9]}] ;# MGTHRXP2_225 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1 -#set_property -dict {LOC AT3 } [get_ports {pcie_rx_n[9]}] ;# MGTHRXN2_225 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1 -#set_property -dict {LOC AT8 } [get_ports {pcie_tx_p[9]}] ;# MGTHTXP2_225 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1 -#set_property -dict {LOC AT7 } [get_ports {pcie_tx_n[9]}] ;# MGTHTXN2_225 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1 -#set_property -dict {LOC AU2 } [get_ports {pcie_rx_p[10]}] ;# MGTHRXP1_225 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1 -#set_property -dict {LOC AU1 } [get_ports {pcie_rx_n[10]}] ;# MGTHRXN1_225 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1 -#set_property -dict {LOC AU6 } [get_ports {pcie_tx_p[10]}] ;# MGTHTXP1_225 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1 -#set_property -dict {LOC AU5 } [get_ports {pcie_tx_n[10]}] ;# MGTHTXN1_225 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1 -#set_property -dict {LOC AV4 } [get_ports {pcie_rx_p[11]}] ;# MGTHRXP0_225 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1 -#set_property -dict {LOC AV3 } [get_ports {pcie_rx_n[11]}] ;# MGTHRXN0_225 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1 -#set_property -dict {LOC AV8 } [get_ports {pcie_tx_p[11]}] ;# MGTHTXP0_225 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1 -#set_property -dict {LOC AV7 } [get_ports {pcie_tx_n[11]}] ;# MGTHTXN0_225 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1 -#set_property -dict {LOC AW2 } [get_ports {pcie_rx_p[12]}] ;# MGTHRXP3_224 GTHE4_CHANNEL_X0Y3 / GTHE4_COMMON_X0Y0 -#set_property -dict {LOC AW1 } [get_ports {pcie_rx_n[12]}] ;# MGTHRXN3_224 GTHE4_CHANNEL_X0Y3 / GTHE4_COMMON_X0Y0 -#set_property -dict {LOC AW6 } [get_ports {pcie_tx_p[12]}] ;# MGTHTXP3_224 GTHE4_CHANNEL_X0Y3 / GTHE4_COMMON_X0Y0 -#set_property -dict {LOC AW5 } [get_ports {pcie_tx_n[12]}] ;# MGTHTXN3_224 GTHE4_CHANNEL_X0Y3 / GTHE4_COMMON_X0Y0 -#set_property -dict {LOC AY4 } [get_ports {pcie_rx_p[13]}] ;# MGTHRXP2_224 GTHE4_CHANNEL_X0Y2 / GTHE4_COMMON_X0Y0 -#set_property -dict {LOC AY3 } [get_ports {pcie_rx_n[13]}] ;# MGTHRXN2_224 GTHE4_CHANNEL_X0Y2 / GTHE4_COMMON_X0Y0 -#set_property -dict {LOC AY8 } [get_ports {pcie_tx_p[13]}] ;# MGTHTXP2_224 GTHE4_CHANNEL_X0Y2 / GTHE4_COMMON_X0Y0 -#set_property -dict {LOC AY7 } [get_ports {pcie_tx_n[13]}] ;# MGTHTXN2_224 GTHE4_CHANNEL_X0Y2 / GTHE4_COMMON_X0Y0 -#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[14]}] ;# MGTHRXP1_224 GTHE4_CHANNEL_X0Y1 / GTHE4_COMMON_X0Y0 -#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[14]}] ;# MGTHRXN1_224 GTHE4_CHANNEL_X0Y1 / GTHE4_COMMON_X0Y0 -#set_property -dict {LOC BA6 } [get_ports {pcie_tx_p[14]}] ;# MGTHTXP1_224 GTHE4_CHANNEL_X0Y1 / GTHE4_COMMON_X0Y0 -#set_property -dict {LOC BA5 } [get_ports {pcie_tx_n[14]}] ;# MGTHTXN1_224 GTHE4_CHANNEL_X0Y1 / GTHE4_COMMON_X0Y0 -#set_property -dict {LOC BB4 } [get_ports {pcie_rx_p[15]}] ;# MGTHRXP0_224 GTHE4_CHANNEL_X0Y0 / GTHE4_COMMON_X0Y0 -#set_property -dict {LOC BB3 } [get_ports {pcie_rx_n[15]}] ;# MGTHRXN0_224 GTHE4_CHANNEL_X0Y0 / GTHE4_COMMON_X0Y0 -#set_property -dict {LOC BB8 } [get_ports {pcie_tx_p[15]}] ;# MGTHTXP0_224 GTHE4_CHANNEL_X0Y0 / GTHE4_COMMON_X0Y0 -#set_property -dict {LOC BB7 } [get_ports {pcie_tx_n[15]}] ;# MGTHTXN0_224 GTHE4_CHANNEL_X0Y0 / GTHE4_COMMON_X0Y0 -#set_property -dict {LOC AN10} [get_ports pcie_refclk_p] ;# MGTREFCLK0P_226 -#set_property -dict {LOC AN9 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_226 -#set_property -dict {LOC G1 IOSTANDARD LVCMOS33 PULLUP true} [get_ports pcie_rst_n] - -# 100 MHz MGT reference clock -#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_p] - -#set_false_path -from [get_ports {pcie_rst_n}] -#set_input_delay 0 [get_ports {pcie_rst_n}] diff --git a/fpga/lib/eth/example/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py deleted file mode 100644 index 9dcbf1323..000000000 --- a/fpga/lib/eth/example/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py +++ /dev/null @@ -1,287 +0,0 @@ -""" - -Copyright (c) 2020 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -""" - -import logging -import os - -from scapy.layers.l2 import Ether, ARP -from scapy.layers.inet import IP, UDP - -import cocotb_test.simulator - -import cocotb -from cocotb.log import SimLog -from cocotb.clock import Clock -from cocotb.triggers import RisingEdge - -from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink - - -class TB: - def __init__(self, dut): - self.dut = dut - - self.log = SimLog("cocotb.tb") - self.log.setLevel(logging.DEBUG) - - cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) - - # Ethernet - cocotb.start_soon(Clock(dut.qsfp_0_rx_clk_0, 6.4, units="ns").start()) - self.qsfp_0_0_source = XgmiiSource(dut.qsfp_0_rxd_0, dut.qsfp_0_rxc_0, dut.qsfp_0_rx_clk_0, dut.qsfp_0_rx_rst_0) - cocotb.start_soon(Clock(dut.qsfp_0_tx_clk_0, 6.4, units="ns").start()) - self.qsfp_0_0_sink = XgmiiSink(dut.qsfp_0_txd_0, dut.qsfp_0_txc_0, dut.qsfp_0_tx_clk_0, dut.qsfp_0_tx_rst_0) - - cocotb.start_soon(Clock(dut.qsfp_0_rx_clk_1, 6.4, units="ns").start()) - self.qsfp_0_1_source = XgmiiSource(dut.qsfp_0_rxd_1, dut.qsfp_0_rxc_1, dut.qsfp_0_rx_clk_1, dut.qsfp_0_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp_0_tx_clk_1, 6.4, units="ns").start()) - self.qsfp_0_1_sink = XgmiiSink(dut.qsfp_0_txd_1, dut.qsfp_0_txc_1, dut.qsfp_0_tx_clk_1, dut.qsfp_0_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp_0_rx_clk_2, 6.4, units="ns").start()) - self.qsfp_0_2_source = XgmiiSource(dut.qsfp_0_rxd_2, dut.qsfp_0_rxc_2, dut.qsfp_0_rx_clk_2, dut.qsfp_0_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp_0_tx_clk_2, 6.4, units="ns").start()) - self.qsfp_0_2_sink = XgmiiSink(dut.qsfp_0_txd_2, dut.qsfp_0_txc_2, dut.qsfp_0_tx_clk_2, dut.qsfp_0_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp_0_rx_clk_3, 6.4, units="ns").start()) - self.qsfp_0_3_source = XgmiiSource(dut.qsfp_0_rxd_3, dut.qsfp_0_rxc_3, dut.qsfp_0_rx_clk_3, dut.qsfp_0_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp_0_tx_clk_3, 6.4, units="ns").start()) - self.qsfp_0_3_sink = XgmiiSink(dut.qsfp_0_txd_3, dut.qsfp_0_txc_3, dut.qsfp_0_tx_clk_3, dut.qsfp_0_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_0, 6.4, units="ns").start()) - self.qsfp_1_0_source = XgmiiSource(dut.qsfp_1_rxd_0, dut.qsfp_1_rxc_0, dut.qsfp_1_rx_clk_0, dut.qsfp_1_rx_rst_0) - cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_0, 6.4, units="ns").start()) - self.qsfp_1_0_sink = XgmiiSink(dut.qsfp_1_txd_0, dut.qsfp_1_txc_0, dut.qsfp_1_tx_clk_0, dut.qsfp_1_tx_rst_0) - - cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_1, 6.4, units="ns").start()) - self.qsfp_1_1_source = XgmiiSource(dut.qsfp_1_rxd_1, dut.qsfp_1_rxc_1, dut.qsfp_1_rx_clk_1, dut.qsfp_1_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_1, 6.4, units="ns").start()) - self.qsfp_1_1_sink = XgmiiSink(dut.qsfp_1_txd_1, dut.qsfp_1_txc_1, dut.qsfp_1_tx_clk_1, dut.qsfp_1_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_2, 6.4, units="ns").start()) - self.qsfp_1_2_source = XgmiiSource(dut.qsfp_1_rxd_2, dut.qsfp_1_rxc_2, dut.qsfp_1_rx_clk_2, dut.qsfp_1_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_2, 6.4, units="ns").start()) - self.qsfp_1_2_sink = XgmiiSink(dut.qsfp_1_txd_2, dut.qsfp_1_txc_2, dut.qsfp_1_tx_clk_2, dut.qsfp_1_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_3, 6.4, units="ns").start()) - self.qsfp_1_3_source = XgmiiSource(dut.qsfp_1_rxd_3, dut.qsfp_1_rxc_3, dut.qsfp_1_rx_clk_3, dut.qsfp_1_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_3, 6.4, units="ns").start()) - self.qsfp_1_3_sink = XgmiiSink(dut.qsfp_1_txd_3, dut.qsfp_1_txc_3, dut.qsfp_1_tx_clk_3, dut.qsfp_1_tx_rst_3) - - async def init(self): - - self.dut.rst.setimmediatevalue(0) - self.dut.qsfp_0_rx_rst_0.setimmediatevalue(0) - self.dut.qsfp_0_tx_rst_0.setimmediatevalue(0) - self.dut.qsfp_0_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp_0_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp_0_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp_0_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp_0_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp_0_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp_1_rx_rst_0.setimmediatevalue(0) - self.dut.qsfp_1_tx_rst_0.setimmediatevalue(0) - self.dut.qsfp_1_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp_1_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp_1_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp_1_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp_1_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp_1_tx_rst_3.setimmediatevalue(0) - - for k in range(10): - await RisingEdge(self.dut.clk) - - self.dut.rst.value = 1 - self.dut.qsfp_0_rx_rst_0.value = 1 - self.dut.qsfp_0_tx_rst_0.value = 1 - self.dut.qsfp_0_rx_rst_1.value = 1 - self.dut.qsfp_0_tx_rst_1.value = 1 - self.dut.qsfp_0_rx_rst_2.value = 1 - self.dut.qsfp_0_tx_rst_2.value = 1 - self.dut.qsfp_0_rx_rst_3.value = 1 - self.dut.qsfp_0_tx_rst_3.value = 1 - self.dut.qsfp_1_rx_rst_0.value = 1 - self.dut.qsfp_1_tx_rst_0.value = 1 - self.dut.qsfp_1_rx_rst_1.value = 1 - self.dut.qsfp_1_tx_rst_1.value = 1 - self.dut.qsfp_1_rx_rst_2.value = 1 - self.dut.qsfp_1_tx_rst_2.value = 1 - self.dut.qsfp_1_rx_rst_3.value = 1 - self.dut.qsfp_1_tx_rst_3.value = 1 - - for k in range(10): - await RisingEdge(self.dut.clk) - - self.dut.rst.value = 0 - self.dut.qsfp_0_rx_rst_0.value = 0 - self.dut.qsfp_0_tx_rst_0.value = 0 - self.dut.qsfp_0_rx_rst_1.value = 0 - self.dut.qsfp_0_tx_rst_1.value = 0 - self.dut.qsfp_0_rx_rst_2.value = 0 - self.dut.qsfp_0_tx_rst_2.value = 0 - self.dut.qsfp_0_rx_rst_3.value = 0 - self.dut.qsfp_0_tx_rst_3.value = 0 - self.dut.qsfp_1_rx_rst_0.value = 0 - self.dut.qsfp_1_tx_rst_0.value = 0 - self.dut.qsfp_1_rx_rst_1.value = 0 - self.dut.qsfp_1_tx_rst_1.value = 0 - self.dut.qsfp_1_rx_rst_2.value = 0 - self.dut.qsfp_1_tx_rst_2.value = 0 - self.dut.qsfp_1_rx_rst_3.value = 0 - self.dut.qsfp_1_tx_rst_3.value = 0 - - -@cocotb.test() -async def run_test(dut): - - tb = TB(dut) - - await tb.init() - - tb.log.info("test UDP RX packet") - - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00') - ip = IP(src='192.168.1.100', dst='192.168.1.128') - udp = UDP(sport=5678, dport=1234) - test_pkt = eth / ip / udp / payload - - test_frame = XgmiiFrame.from_payload(test_pkt.build()) - - await tb.qsfp_0_0_source.send(test_frame) - - tb.log.info("receive ARP request") - - rx_frame = await tb.qsfp_0_0_sink.recv() - - rx_pkt = Ether(bytes(rx_frame.get_payload())) - - tb.log.info("RX packet: %s", repr(rx_pkt)) - - assert rx_pkt.dst == 'ff:ff:ff:ff:ff:ff' - assert rx_pkt.src == test_pkt.dst - assert rx_pkt[ARP].hwtype == 1 - assert rx_pkt[ARP].ptype == 0x0800 - assert rx_pkt[ARP].hwlen == 6 - assert rx_pkt[ARP].plen == 4 - assert rx_pkt[ARP].op == 1 - assert rx_pkt[ARP].hwsrc == test_pkt.dst - assert rx_pkt[ARP].psrc == test_pkt[IP].dst - assert rx_pkt[ARP].hwdst == '00:00:00:00:00:00' - assert rx_pkt[ARP].pdst == test_pkt[IP].src - - tb.log.info("send ARP response") - - eth = Ether(src=test_pkt.src, dst=test_pkt.dst) - arp = ARP(hwtype=1, ptype=0x0800, hwlen=6, plen=4, op=2, - hwsrc=test_pkt.src, psrc=test_pkt[IP].src, - hwdst=test_pkt.dst, pdst=test_pkt[IP].dst) - resp_pkt = eth / arp - - resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - - await tb.qsfp_0_0_source.send(resp_frame) - - tb.log.info("receive UDP packet") - - rx_frame = await tb.qsfp_0_0_sink.recv() - - rx_pkt = Ether(bytes(rx_frame.get_payload())) - - tb.log.info("RX packet: %s", repr(rx_pkt)) - - assert rx_pkt.dst == test_pkt.src - assert rx_pkt.src == test_pkt.dst - assert rx_pkt[IP].dst == test_pkt[IP].src - assert rx_pkt[IP].src == test_pkt[IP].dst - assert rx_pkt[UDP].dport == test_pkt[UDP].sport - assert rx_pkt[UDP].sport == test_pkt[UDP].dport - assert rx_pkt[UDP].payload == test_pkt[UDP].payload - - await RisingEdge(dut.clk) - await RisingEdge(dut.clk) - - -# cocotb-test - -tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) -axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'lib', 'axis', 'rtl')) -eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) - - -def test_fpga_core(request): - dut = "fpga_core" - module = os.path.splitext(os.path.basename(__file__))[0] - toplevel = dut - - verilog_sources = [ - os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g_fifo.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), - os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "eth_axis_rx.v"), - os.path.join(eth_rtl_dir, "eth_axis_tx.v"), - os.path.join(eth_rtl_dir, "udp_complete_64.v"), - os.path.join(eth_rtl_dir, "udp_checksum_gen_64.v"), - os.path.join(eth_rtl_dir, "udp_64.v"), - os.path.join(eth_rtl_dir, "udp_ip_rx_64.v"), - os.path.join(eth_rtl_dir, "udp_ip_tx_64.v"), - os.path.join(eth_rtl_dir, "ip_complete_64.v"), - os.path.join(eth_rtl_dir, "ip_64.v"), - os.path.join(eth_rtl_dir, "ip_eth_rx_64.v"), - os.path.join(eth_rtl_dir, "ip_eth_tx_64.v"), - os.path.join(eth_rtl_dir, "ip_arb_mux.v"), - os.path.join(eth_rtl_dir, "arp.v"), - os.path.join(eth_rtl_dir, "arp_cache.v"), - os.path.join(eth_rtl_dir, "arp_eth_rx.v"), - os.path.join(eth_rtl_dir, "arp_eth_tx.v"), - os.path.join(eth_rtl_dir, "eth_arb_mux.v"), - os.path.join(axis_rtl_dir, "arbiter.v"), - os.path.join(axis_rtl_dir, "priority_encoder.v"), - os.path.join(axis_rtl_dir, "axis_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), - ] - - parameters = {} - - # parameters['A'] = val - - extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} - - sim_build = os.path.join(tests_dir, "sim_build", - request.node.name.replace('[', '-').replace(']', '')) - - cocotb_test.simulator.run( - python_search=[tests_dir], - verilog_sources=verilog_sources, - toplevel=toplevel, - module=module, - parameters=parameters, - sim_build=sim_build, - extra_env=extra_env, - ) diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/Makefile b/fpga/lib/eth/example/fb2CG/fpga_25g/Makefile similarity index 100% rename from fpga/lib/eth/example/VCU118/fpga_10g/Makefile rename to fpga/lib/eth/example/fb2CG/fpga_25g/Makefile diff --git a/fpga/lib/eth/example/fb2CG/fpga_10g/README.md b/fpga/lib/eth/example/fb2CG/fpga_25g/README.md similarity index 100% rename from fpga/lib/eth/example/fb2CG/fpga_10g/README.md rename to fpga/lib/eth/example/fb2CG/fpga_25g/README.md diff --git a/fpga/lib/eth/example/fb2CG/fpga_25g/common/vivado.mk b/fpga/lib/eth/example/fb2CG/fpga_25g/common/vivado.mk new file mode 100644 index 000000000..1402e2382 --- /dev/null +++ b/fpga/lib/eth/example/fb2CG/fpga_25g/common/vivado.mk @@ -0,0 +1,137 @@ +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - space-separated list of source files +# INC_FILES - space-separated list of include files +# XDC_FILES - space-separated list of timing constraint files +# XCI_FILES - space-separated list of IP XCI files +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: fpga vivado tmpclean clean distclean + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include ../$(CONFIG) + +FPGA_TOP ?= fpga +PROJECT ?= $(FPGA_TOP) + +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) + +ifdef XDC_FILES + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +else + XDC_FILES_REL = $(PROJECT).xdc +endif + +################################################################### +# Main Targets +# +# all: build everything +# clean: remove output files and project files +################################################################### + +all: fpga + +fpga: $(PROJECT).bit + +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr + +tmpclean:: + -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean:: tmpclean + -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt + +distclean:: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file +create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ + echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ + echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ + echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ + for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl + vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) + +# synthesis run +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr + echo "open_project $(PROJECT).xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp + echo "open_project $(PROJECT).xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + echo "open_run impl_1" >> run_impl.tcl + echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl + echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# bit file +$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp + echo "open_project $(PROJECT).xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl + echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi + mkdir -p rev + COUNT=100; \ + while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/lib/eth/example/fb2CG/fpga_25g/fpga.xdc b/fpga/lib/eth/example/fb2CG/fpga_25g/fpga.xdc new file mode 100644 index 000000000..13f9b1390 --- /dev/null +++ b/fpga/lib/eth/example/fb2CG/fpga_25g/fpga.xdc @@ -0,0 +1,802 @@ +# XDC constraints for the fb2CG@KU15P +# part: xcku15p-ffve1760-2-e + +# General configuration +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] + +# System clocks +# init clock 50 MHz +set_property -dict {LOC E7 IOSTANDARD LVCMOS18} [get_ports init_clk] +create_clock -period 20.000 -name init_clk [get_ports init_clk] + +# E7 is not a global clock capable input, so need to set CLOCK_DEDICATED_ROUTE to satisfy DRC +#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets init_clk_ibuf_inst/O] +set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets init_clk_bufg] + +# DDR4 refclk1 +#set_property -dict {LOC AT32 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1_p] +#set_property -dict {LOC AU32 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1_n] +#create_clock -period 3.750 -name clk_ddr4_refclk1 [get_ports clk_ddr4_refclk1_p] + +# DDR4 refclk2 +#set_property -dict {LOC G29 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_p] +#set_property -dict {LOC G28 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_n] +#create_clock -period 3.750 -name clk_ddr4_refclk2 [get_ports clk_ddr4_refclk1_p] + +# LEDs +set_property -dict {LOC C4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports led_sreg_d] +set_property -dict {LOC B3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports led_sreg_ld] +set_property -dict {LOC G3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports led_sreg_clk] +set_property -dict {LOC C5 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_bmc[0]}] +set_property -dict {LOC C6 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_bmc[1]}] +set_property -dict {LOC D3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {led_exp[0]}] +set_property -dict {LOC D4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {led_exp[1]}] + +set_false_path -to [get_ports {led_sreg_d led_sreg_ld led_sreg_clk led_bmc[*] led_exp[*]}] +set_output_delay 0 [get_ports {led_sreg_d led_sreg_ld led_sreg_clk led_bmc[*] led_exp[*]}] + +# GPIO +#set_property -dict {LOC B4 IOSTANDARD LVCMOS33} [get_ports pps_in] ;# from SMA J6 via Q1 (inverted) +#set_property -dict {LOC A4 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 4} [get_ports pps_out] ;# to SMA J6 via U4 and U5, and u.FL J7 (PPS OUT) via U3 +#set_property -dict {LOC A3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports pps_out_en] ; # to U5 IN (connects pps_out to SMA J6 when high) +#set_property -dict {LOC H2 IOSTANDARD LVCMOS33} [get_ports misc_ucoax] ; from u.FL J5 (PPS IN) + +#set_false_path -to [get_ports {pps_out pps_out_en}] +#set_output_delay 0 [get_ports {pps_out pps_out_en}] +#set_false_path -from [get_ports {pps_in}] +#set_input_delay 0 [get_ports {pps_in}] + +# BMC interface +#set_property -dict {LOC D7 IOSTANDARD LVCMOS18} [get_ports bmc_miso] +#set_property -dict {LOC J4 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports bmc_nss] +#set_property -dict {LOC B6 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports bmc_clk] +#set_property -dict {LOC D5 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports bmc_mosi] +#set_property -dict {LOC H4 IOSTANDARD LVCMOS18} [get_ports bmc_int] + +#set_false_path -to [get_ports {bmc_nss bmc_clk bmc_mosi}] +#set_output_delay 0 [get_ports {bmc_nss bmc_clk bmc_mosi}] +#set_false_path -from [get_ports {bmc_miso bmc_int}] +#set_input_delay 0 [get_ports {bmc_miso bmc_int}] + +# Board status +#set_property -dict {LOC J2 IOSTANDARD LVCMOS33} [get_ports {fan_tacho[0]}] +#set_property -dict {LOC J3 IOSTANDARD LVCMOS33} [get_ports {fan_tacho[1]}] +set_property -dict {LOC A6 IOSTANDARD LVCMOS18} [get_ports {pg[0]}] +set_property -dict {LOC C7 IOSTANDARD LVCMOS18} [get_ports {pg[1]}] +#set_property -dict {LOC E2 IOSTANDARD LVCMOS33} [get_ports pwrbrk] + +set_false_path -from [get_ports {pg[*]}] +set_input_delay 0 [get_ports {pg[*]}] + +# QSFP28 Interfaces +set_property -dict {LOC Y39 } [get_ports qsfp_0_rx_0_p] ;# MGTYRXP0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC Y40 } [get_ports qsfp_0_rx_0_n] ;# MGTYRXN0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC Y34 } [get_ports qsfp_0_tx_0_p] ;# MGTYTXP0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC Y35 } [get_ports qsfp_0_tx_0_n] ;# MGTYTXN0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC W41 } [get_ports qsfp_0_rx_1_p] ;# MGTYRXP1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC W42 } [get_ports qsfp_0_rx_1_n] ;# MGTYRXN1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC W36 } [get_ports qsfp_0_tx_1_p] ;# MGTYTXP1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC W37 } [get_ports qsfp_0_tx_1_n] ;# MGTYTXN1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC V39 } [get_ports qsfp_0_rx_2_p] ;# MGTYRXP2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC V40 } [get_ports qsfp_0_rx_2_n] ;# MGTYRXN2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC V34 } [get_ports qsfp_0_tx_2_p] ;# MGTYTXP2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC V35 } [get_ports qsfp_0_tx_2_n] ;# MGTYTXN2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC U41 } [get_ports qsfp_0_rx_3_p] ;# MGTYRXP3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC U42 } [get_ports qsfp_0_rx_3_n] ;# MGTYRXN3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC U36 } [get_ports qsfp_0_tx_3_p] ;# MGTYTXP3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC U37 } [get_ports qsfp_0_tx_3_n] ;# MGTYTXN3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC W32 } [get_ports qsfp_0_mgt_refclk_p] ;# MGTREFCLK0P_130 from U28 +set_property -dict {LOC W33 } [get_ports qsfp_0_mgt_refclk_n] ;# MGTREFCLK0N_130 from U28 +set_property -dict {LOC B9 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_0_mod_prsnt_n] +set_property -dict {LOC A8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports qsfp_0_reset_n] +set_property -dict {LOC A9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports qsfp_0_lp_mode] +set_property -dict {LOC A10 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_0_intr_n] +#set_property -dict {LOC B8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports qsfp_0_i2c_scl] +#set_property -dict {LOC B7 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports qsfp_0_i2c_sda] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_0_mgt_refclk [get_ports qsfp_0_mgt_refclk_p] + +set_false_path -to [get_ports {qsfp_0_reset_n qsfp_0_lp_mode}] +set_output_delay 0 [get_ports {qsfp_0_reset_n qsfp_0_lp_mode}] +set_false_path -from [get_ports {qsfp_0_mod_prsnt_n qsfp_0_intr_n}] +set_input_delay 0 [get_ports {qsfp_0_mod_prsnt_n qsfp_0_intr_n}] + +#set_false_path -to [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}] +#set_output_delay 0 [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}] +#set_false_path -from [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}] +#set_input_delay 0 [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}] + +set_property -dict {LOC M39 } [get_ports qsfp_1_rx_0_p] ;# MGTYRXP0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC M40 } [get_ports qsfp_1_rx_0_n] ;# MGTYRXN0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC M34 } [get_ports qsfp_1_tx_0_p] ;# MGTYTXP0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC M35 } [get_ports qsfp_1_tx_0_n] ;# MGTYTXN0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC L41 } [get_ports qsfp_1_rx_1_p] ;# MGTYRXP1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC L42 } [get_ports qsfp_1_rx_1_n] ;# MGTYRXN1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC L36 } [get_ports qsfp_1_tx_1_p] ;# MGTYTXP1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC L37 } [get_ports qsfp_1_tx_1_n] ;# MGTYTXN1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC K39 } [get_ports qsfp_1_rx_2_p] ;# MGTYRXP2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC K40 } [get_ports qsfp_1_rx_2_n] ;# MGTYRXN2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC K34 } [get_ports qsfp_1_tx_2_p] ;# MGTYTXP2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC K35 } [get_ports qsfp_1_tx_2_n] ;# MGTYTXN2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC J41 } [get_ports qsfp_1_rx_3_p] ;# MGTYRXP3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC J42 } [get_ports qsfp_1_rx_3_n] ;# MGTYRXN3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC J36 } [get_ports qsfp_1_tx_3_p] ;# MGTYTXP3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC J37 } [get_ports qsfp_1_tx_3_n] ;# MGTYTXN3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC P30 } [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_132 from U28 +set_property -dict {LOC P31 } [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_132 from U28 +set_property -dict {LOC E10 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_1_mod_prsnt_n] +set_property -dict {LOC C10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports qsfp_1_reset_n] +set_property -dict {LOC D9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports qsfp_1_lp_mode] +set_property -dict {LOC D10 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_1_intr_n] +#set_property -dict {LOC C9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports qsfp_1_i2c_scl] +#set_property -dict {LOC D8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports qsfp_1_i2c_sda] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_1_mgt_refclk [get_ports qsfp_1_mgt_refclk_p] + +set_false_path -to [get_ports {qsfp_1_reset_n qsfp_1_lp_mode}] +set_output_delay 0 [get_ports {qsfp_1_reset_n qsfp_1_lp_mode}] +set_false_path -from [get_ports {qsfp_1_mod_prsnt_n qsfp_1_intr_n}] +set_input_delay 0 [get_ports {qsfp_1_mod_prsnt_n qsfp_1_intr_n}] + +#set_false_path -to [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}] +#set_output_delay 0 [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}] +#set_false_path -from [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}] +#set_input_delay 0 [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}] + +# Expansion connector +#set_property -dict {LOC AG41} [get_ports {exp_rx_p[0]}] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +#set_property -dict {LOC AG42} [get_ports {exp_rx_n[0]}] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +#set_property -dict {LOC AG36} [get_ports {exp_tx_p[0]}] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +#set_property -dict {LOC AG37} [get_ports {exp_tx_n[0]}] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +#set_property -dict {LOC AH39} [get_ports {exp_rx_p[1]}] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +#set_property -dict {LOC AH40} [get_ports {exp_rx_n[1]}] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +#set_property -dict {LOC AH34} [get_ports {exp_tx_p[1]}] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +#set_property -dict {LOC AH35} [get_ports {exp_tx_n[1]}] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +#set_property -dict {LOC AJ41} [get_ports {exp_rx_p[2]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0 +#set_property -dict {LOC AJ42} [get_ports {exp_rx_n[2]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0 +#set_property -dict {LOC AJ36} [get_ports {exp_tx_p[2]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0 +#set_property -dict {LOC AJ37} [get_ports {exp_tx_n[2]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0 +#set_property -dict {LOC AK39} [get_ports {exp_rx_p[3]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0 +#set_property -dict {LOC AK40} [get_ports {exp_rx_n[3]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0 +#set_property -dict {LOC AK34} [get_ports {exp_tx_p[3]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0 +#set_property -dict {LOC AK35} [get_ports {exp_tx_n[3]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0 +#set_property -dict {LOC AL41} [get_ports {exp_rx_p[4]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0 +#set_property -dict {LOC AL42} [get_ports {exp_rx_n[4]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0 +#set_property -dict {LOC AL36} [get_ports {exp_tx_p[4]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0 +#set_property -dict {LOC AL37} [get_ports {exp_tx_n[4]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0 +#set_property -dict {LOC AM39} [get_ports {exp_rx_p[5]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0 +#set_property -dict {LOC AM40} [get_ports {exp_rx_n[5]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0 +#set_property -dict {LOC AM34} [get_ports {exp_tx_p[5]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0 +#set_property -dict {LOC AM35} [get_ports {exp_tx_n[5]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0 +#set_property -dict {LOC AL32} [get_ports exp_refclk_0_p] ;# MGTREFCLK0P_128 from U28 +#set_property -dict {LOC AL33} [get_ports exp_refclk_0_n] ;# MGTREFCLK0N_128 from U28 +#set_property -dict {LOC AG32} [get_ports exp_refclk_1_p] ;# MGTREFCLK0P_127 from U28 +#set_property -dict {LOC AG33} [get_ports exp_refclk_1_n] ;# MGTREFCLK0N_127 from U28 +#set_property -dict {LOC E3 IOSTANDARD LVCMOS33} [get_ports {exp_gpio[0]}] +#set_property -dict {LOC F3 IOSTANDARD LVCMOS33} [get_ports {exp_gpio[1]}] + +# 161.1328125 MHz MGT reference clock +#create_clock -period 6.206 -name exp_refclk_0 [get_ports exp_refclk_0_p] +#create_clock -period 6.206 -name exp_refclk_1 [get_ports exp_refclk_1_p] + +# PCIe Interface +#set_property -dict {LOC AG2 } [get_ports {pcie_rx_p[0]}] ;# MGTHRXP3_227 GTHE4_CHANNEL_X0Y15 / GTHE4_COMMON_X0Y3 +#set_property -dict {LOC AG1 } [get_ports {pcie_rx_n[0]}] ;# MGTHRXN3_227 GTHE4_CHANNEL_X0Y15 / GTHE4_COMMON_X0Y3 +#set_property -dict {LOC AG6 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_227 GTHE4_CHANNEL_X0Y15 / GTHE4_COMMON_X0Y3 +#set_property -dict {LOC AG5 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_227 GTHE4_CHANNEL_X0Y15 / GTHE4_COMMON_X0Y3 +#set_property -dict {LOC AH4 } [get_ports {pcie_rx_p[1]}] ;# MGTHRXP2_227 GTHE4_CHANNEL_X0Y14 / GTHE4_COMMON_X0Y3 +#set_property -dict {LOC AH3 } [get_ports {pcie_rx_n[1]}] ;# MGTHRXN2_227 GTHE4_CHANNEL_X0Y14 / GTHE4_COMMON_X0Y3 +#set_property -dict {LOC AH8 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_227 GTHE4_CHANNEL_X0Y14 / GTHE4_COMMON_X0Y3 +#set_property -dict {LOC AH7 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_227 GTHE4_CHANNEL_X0Y14 / GTHE4_COMMON_X0Y3 +#set_property -dict {LOC AJ2 } [get_ports {pcie_rx_p[2]}] ;# MGTHRXP1_227 GTHE4_CHANNEL_X0Y13 / GTHE4_COMMON_X0Y3 +#set_property -dict {LOC AJ1 } [get_ports {pcie_rx_n[2]}] ;# MGTHRXN1_227 GTHE4_CHANNEL_X0Y13 / GTHE4_COMMON_X0Y3 +#set_property -dict {LOC AJ6 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_227 GTHE4_CHANNEL_X0Y13 / GTHE4_COMMON_X0Y3 +#set_property -dict {LOC AJ5 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_227 GTHE4_CHANNEL_X0Y13 / GTHE4_COMMON_X0Y3 +#set_property -dict {LOC AK4 } [get_ports {pcie_rx_p[3]}] ;# MGTHRXP0_227 GTHE4_CHANNEL_X0Y12 / GTHE4_COMMON_X0Y3 +#set_property -dict {LOC AK3 } [get_ports {pcie_rx_n[3]}] ;# MGTHRXN0_227 GTHE4_CHANNEL_X0Y12 / GTHE4_COMMON_X0Y3 +#set_property -dict {LOC AK8 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_227 GTHE4_CHANNEL_X0Y12 / GTHE4_COMMON_X0Y3 +#set_property -dict {LOC AK7 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_227 GTHE4_CHANNEL_X0Y12 / GTHE4_COMMON_X0Y3 +#set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[4]}] ;# MGTHRXP3_226 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y2 +#set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[4]}] ;# MGTHRXN3_226 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y2 +#set_property -dict {LOC AL6 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_226 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y2 +#set_property -dict {LOC AL5 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_226 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y2 +#set_property -dict {LOC AM4 } [get_ports {pcie_rx_p[5]}] ;# MGTHRXP2_226 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y2 +#set_property -dict {LOC AM3 } [get_ports {pcie_rx_n[5]}] ;# MGTHRXN2_226 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y2 +#set_property -dict {LOC AM8 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_226 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y2 +#set_property -dict {LOC AM7 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_226 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y2 +#set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[6]}] ;# MGTHRXP1_226 GTHE4_CHANNEL_X0Y9 / GTHE4_COMMON_X0Y2 +#set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[6]}] ;# MGTHRXN1_226 GTHE4_CHANNEL_X0Y9 / GTHE4_COMMON_X0Y2 +#set_property -dict {LOC AN6 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_226 GTHE4_CHANNEL_X0Y9 / GTHE4_COMMON_X0Y2 +#set_property -dict {LOC AN5 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_226 GTHE4_CHANNEL_X0Y9 / GTHE4_COMMON_X0Y2 +#set_property -dict {LOC AP4 } [get_ports {pcie_rx_p[7]}] ;# MGTHRXP0_226 GTHE4_CHANNEL_X0Y8 / GTHE4_COMMON_X0Y2 +#set_property -dict {LOC AP3 } [get_ports {pcie_rx_n[7]}] ;# MGTHRXN0_226 GTHE4_CHANNEL_X0Y8 / GTHE4_COMMON_X0Y2 +#set_property -dict {LOC AP8 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_226 GTHE4_CHANNEL_X0Y8 / GTHE4_COMMON_X0Y2 +#set_property -dict {LOC AP7 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_226 GTHE4_CHANNEL_X0Y8 / GTHE4_COMMON_X0Y2 +#set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[8]}] ;# MGTHRXP3_225 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[8]}] ;# MGTHRXN3_225 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AR6 } [get_ports {pcie_tx_p[8]}] ;# MGTHTXP3_225 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AR5 } [get_ports {pcie_tx_n[8]}] ;# MGTHTXN3_225 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AT4 } [get_ports {pcie_rx_p[9]}] ;# MGTHRXP2_225 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AT3 } [get_ports {pcie_rx_n[9]}] ;# MGTHRXN2_225 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AT8 } [get_ports {pcie_tx_p[9]}] ;# MGTHTXP2_225 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AT7 } [get_ports {pcie_tx_n[9]}] ;# MGTHTXN2_225 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AU2 } [get_ports {pcie_rx_p[10]}] ;# MGTHRXP1_225 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AU1 } [get_ports {pcie_rx_n[10]}] ;# MGTHRXN1_225 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AU6 } [get_ports {pcie_tx_p[10]}] ;# MGTHTXP1_225 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AU5 } [get_ports {pcie_tx_n[10]}] ;# MGTHTXN1_225 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AV4 } [get_ports {pcie_rx_p[11]}] ;# MGTHRXP0_225 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AV3 } [get_ports {pcie_rx_n[11]}] ;# MGTHRXN0_225 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AV8 } [get_ports {pcie_tx_p[11]}] ;# MGTHTXP0_225 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AV7 } [get_ports {pcie_tx_n[11]}] ;# MGTHTXN0_225 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AW2 } [get_ports {pcie_rx_p[12]}] ;# MGTHRXP3_224 GTHE4_CHANNEL_X0Y3 / GTHE4_COMMON_X0Y0 +#set_property -dict {LOC AW1 } [get_ports {pcie_rx_n[12]}] ;# MGTHRXN3_224 GTHE4_CHANNEL_X0Y3 / GTHE4_COMMON_X0Y0 +#set_property -dict {LOC AW6 } [get_ports {pcie_tx_p[12]}] ;# MGTHTXP3_224 GTHE4_CHANNEL_X0Y3 / GTHE4_COMMON_X0Y0 +#set_property -dict {LOC AW5 } [get_ports {pcie_tx_n[12]}] ;# MGTHTXN3_224 GTHE4_CHANNEL_X0Y3 / GTHE4_COMMON_X0Y0 +#set_property -dict {LOC AY4 } [get_ports {pcie_rx_p[13]}] ;# MGTHRXP2_224 GTHE4_CHANNEL_X0Y2 / GTHE4_COMMON_X0Y0 +#set_property -dict {LOC AY3 } [get_ports {pcie_rx_n[13]}] ;# MGTHRXN2_224 GTHE4_CHANNEL_X0Y2 / GTHE4_COMMON_X0Y0 +#set_property -dict {LOC AY8 } [get_ports {pcie_tx_p[13]}] ;# MGTHTXP2_224 GTHE4_CHANNEL_X0Y2 / GTHE4_COMMON_X0Y0 +#set_property -dict {LOC AY7 } [get_ports {pcie_tx_n[13]}] ;# MGTHTXN2_224 GTHE4_CHANNEL_X0Y2 / GTHE4_COMMON_X0Y0 +#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[14]}] ;# MGTHRXP1_224 GTHE4_CHANNEL_X0Y1 / GTHE4_COMMON_X0Y0 +#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[14]}] ;# MGTHRXN1_224 GTHE4_CHANNEL_X0Y1 / GTHE4_COMMON_X0Y0 +#set_property -dict {LOC BA6 } [get_ports {pcie_tx_p[14]}] ;# MGTHTXP1_224 GTHE4_CHANNEL_X0Y1 / GTHE4_COMMON_X0Y0 +#set_property -dict {LOC BA5 } [get_ports {pcie_tx_n[14]}] ;# MGTHTXN1_224 GTHE4_CHANNEL_X0Y1 / GTHE4_COMMON_X0Y0 +#set_property -dict {LOC BB4 } [get_ports {pcie_rx_p[15]}] ;# MGTHRXP0_224 GTHE4_CHANNEL_X0Y0 / GTHE4_COMMON_X0Y0 +#set_property -dict {LOC BB3 } [get_ports {pcie_rx_n[15]}] ;# MGTHRXN0_224 GTHE4_CHANNEL_X0Y0 / GTHE4_COMMON_X0Y0 +#set_property -dict {LOC BB8 } [get_ports {pcie_tx_p[15]}] ;# MGTHTXP0_224 GTHE4_CHANNEL_X0Y0 / GTHE4_COMMON_X0Y0 +#set_property -dict {LOC BB7 } [get_ports {pcie_tx_n[15]}] ;# MGTHTXN0_224 GTHE4_CHANNEL_X0Y0 / GTHE4_COMMON_X0Y0 +#set_property -dict {LOC AN10} [get_ports pcie_refclk_p] ;# MGTREFCLK0P_226 +#set_property -dict {LOC AN9 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_226 +#set_property -dict {LOC G1 IOSTANDARD LVCMOS33 PULLUP true} [get_ports pcie_rst_n] + +# 100 MHz MGT reference clock +#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_p] + +#set_false_path -from [get_ports {pcie_rst_n}] +#set_input_delay 0 [get_ports {pcie_rst_n}] + +# DDR4 C0 +# 5x K4A8G165WB-BCTD / MT40A512M16HA-075E +#set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +#set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +#set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +#set_property -dict {LOC AY24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +#set_property -dict {LOC AK23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +#set_property -dict {LOC AV21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +#set_property -dict {LOC AV22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +#set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +#set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +#set_property -dict {LOC AY21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +#set_property -dict {LOC AT22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +#set_property -dict {LOC BA21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +#set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +#set_property -dict {LOC AL22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +#set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +#set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +#set_property -dict {LOC AW21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +#set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +#set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +#set_property -dict {LOC BB23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +#set_property -dict {LOC BA24 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t}] +#set_property -dict {LOC BB24 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c}] +#set_property -dict {LOC AL21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke}] +#set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n}] +#set_property -dict {LOC AR21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +#set_property -dict {LOC AT21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt}] +#set_property -dict {LOC AK17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +#set_property -dict {LOC BB20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] +#set_property -dict {LOC AV20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_alert_n}] +#set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_ten}] + +#set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +#set_property -dict {LOC AJ16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +#set_property -dict {LOC AK19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +#set_property -dict {LOC AK16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +#set_property -dict {LOC AL19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +#set_property -dict {LOC AH16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +#set_property -dict {LOC AM17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +#set_property -dict {LOC AH17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +#set_property -dict {LOC AL24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +#set_property -dict {LOC AH21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +#set_property -dict {LOC AK24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +#set_property -dict {LOC AJ24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +#set_property -dict {LOC AK21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +#set_property -dict {LOC AH22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +#set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +#set_property -dict {LOC AJ23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +#set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +#set_property -dict {LOC BB13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +#set_property -dict {LOC AY13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +#set_property -dict {LOC BB14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +#set_property -dict {LOC AY14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +#set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +#set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +#set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +#set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +#set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +#set_property -dict {LOC AU15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +#set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +#set_property -dict {LOC AT16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +#set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +#set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +#set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +#set_property -dict {LOC BB18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +#set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +#set_property -dict {LOC BA19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +#set_property -dict {LOC AW19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +#set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +#set_property -dict {LOC AW18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +#set_property -dict {LOC BB19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +#set_property -dict {LOC AY19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +#set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +#set_property -dict {LOC AT19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +#set_property -dict {LOC AU18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +#set_property -dict {LOC AU19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +#set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +#set_property -dict {LOC AR19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +#set_property -dict {LOC AV18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +#set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +#set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +#set_property -dict {LOC AM20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +#set_property -dict {LOC AN18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +#set_property -dict {LOC AN20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +#set_property -dict {LOC AP16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +#set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +#set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +#set_property -dict {LOC AP20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +#set_property -dict {LOC AR23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +#set_property -dict {LOC AM23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +#set_property -dict {LOC AR24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +#set_property -dict {LOC AM24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +#set_property -dict {LOC AR22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +#set_property -dict {LOC AN22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +#set_property -dict {LOC AP24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +#set_property -dict {LOC AM22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +#set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +#set_property -dict {LOC AR12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +#set_property -dict {LOC AP15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +#set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +#set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +#set_property -dict {LOC AT12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +#set_property -dict {LOC AP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +#set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +#set_property -dict {LOC AJ19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +#set_property -dict {LOC AJ18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +#set_property -dict {LOC AH20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +#set_property -dict {LOC AJ20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +#set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +#set_property -dict {LOC BA12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +#set_property -dict {LOC AU12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +#set_property -dict {LOC AV12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +#set_property -dict {LOC AY17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +#set_property -dict {LOC BA17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +#set_property -dict {LOC AR17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +#set_property -dict {LOC AT17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +#set_property -dict {LOC AM19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +#set_property -dict {LOC AM18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +#set_property -dict {LOC AN21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +#set_property -dict {LOC AP21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +#set_property -dict {LOC AN13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +#set_property -dict {LOC AN12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +#set_property -dict {LOC AK18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[0]}] +#set_property -dict {LOC AK22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[1]}] +#set_property -dict {LOC AY16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[2]}] +#set_property -dict {LOC AV15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[3]}] +#set_property -dict {LOC BA20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[4]}] +#set_property -dict {LOC AT20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[5]}] +#set_property -dict {LOC AP19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[6]}] +#set_property -dict {LOC AN23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[7]}] +#set_property -dict {LOC AR14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[8]}] + +# DDR4 C1 +# 5x K4A8G165WB-BCTD / MT40A512M16HA-075E +#set_property -dict {LOC AT30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +#set_property -dict {LOC AR29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +#set_property -dict {LOC AP30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +#set_property -dict {LOC AR32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +#set_property -dict {LOC AU30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +#set_property -dict {LOC AP28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +#set_property -dict {LOC AW31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +#set_property -dict {LOC AM30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +#set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +#set_property -dict {LOC AN28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +#set_property -dict {LOC AV31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +#set_property -dict {LOC AP29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +#set_property -dict {LOC AR31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +#set_property -dict {LOC AN30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +#set_property -dict {LOC AN32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +#set_property -dict {LOC AV32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +#set_property -dict {LOC BA34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +#set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +#set_property -dict {LOC AT31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +#set_property -dict {LOC AV33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +#set_property -dict {LOC AT34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}] +#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}] +#set_property -dict {LOC AP31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}] +#set_property -dict {LOC AR34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}] +#set_property -dict {LOC AU33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +#set_property -dict {LOC AN31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}] +#set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +#set_property -dict {LOC AV25 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] +#set_property -dict {LOC BA31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}] +#set_property -dict {LOC AT27 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}] + +#set_property -dict {LOC AV41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +#set_property -dict {LOC BB39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +#set_property -dict {LOC AY42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +#set_property -dict {LOC BA40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +#set_property -dict {LOC AV42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +#set_property -dict {LOC BA39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +#set_property -dict {LOC AW41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +#set_property -dict {LOC BB40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +#set_property -dict {LOC AV38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +#set_property -dict {LOC BA37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +#set_property -dict {LOC AW38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +#set_property -dict {LOC AV37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +#set_property -dict {LOC AU37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +#set_property -dict {LOC AW36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +#set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +#set_property -dict {LOC AV36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +#set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +#set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +#set_property -dict {LOC BB33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +#set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +#set_property -dict {LOC BA36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +#set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +#set_property -dict {LOC BB37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +#set_property -dict {LOC AW33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +#set_property -dict {LOC BA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +#set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +#set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +#set_property -dict {LOC AY29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +#set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +#set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +#set_property -dict {LOC BB28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +#set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +#set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +#set_property -dict {LOC AV26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +#set_property -dict {LOC BA26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +#set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +#set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +#set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +#set_property -dict {LOC AY26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +#set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +#set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +#set_property -dict {LOC AP25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +#set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +#set_property -dict {LOC AP26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +#set_property -dict {LOC AU28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +#set_property -dict {LOC AN25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +#set_property -dict {LOC AR26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +#set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +#set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +#set_property -dict {LOC AK30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +#set_property -dict {LOC AL29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +#set_property -dict {LOC AH30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +#set_property -dict {LOC AM28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +#set_property -dict {LOC AJ30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +#set_property -dict {LOC AK29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +#set_property -dict {LOC AJ29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +#set_property -dict {LOC AL25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +#set_property -dict {LOC AH26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +#set_property -dict {LOC AL27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +#set_property -dict {LOC AJ25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +#set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +#set_property -dict {LOC AH27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +#set_property -dict {LOC AM25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +#set_property -dict {LOC AJ26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +#set_property -dict {LOC AK13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +#set_property -dict {LOC AJ13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +#set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +#set_property -dict {LOC AH13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +#set_property -dict {LOC AK14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +#set_property -dict {LOC AH12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +#set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +#set_property -dict {LOC AK12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +#set_property -dict {LOC AY41 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +#set_property -dict {LOC BA41 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +#set_property -dict {LOC AY37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +#set_property -dict {LOC AY38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +#set_property -dict {LOC BA35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +#set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +#set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +#set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +#set_property -dict {LOC BA27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +#set_property -dict {LOC BB27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +#set_property -dict {LOC AT29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +#set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +#set_property -dict {LOC AJ28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +#set_property -dict {LOC AK28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +#set_property -dict {LOC AN26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +#set_property -dict {LOC AN27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +#set_property -dict {LOC AJ15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +#set_property -dict {LOC AJ14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +#set_property -dict {LOC AW39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] +#set_property -dict {LOC AU35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] +#set_property -dict {LOC AY34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] +#set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] +#set_property -dict {LOC AU25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] +#set_property -dict {LOC AT26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] +#set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] +#set_property -dict {LOC AK26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] +#set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}] + +# DDR4 C2 +# 5x K4A8G165WB-BCTD / MT40A512M16HA-075E +#set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +#set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +#set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +#set_property -dict {LOC F31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +#set_property -dict {LOC H29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +#set_property -dict {LOC F28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +#set_property -dict {LOC J28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +#set_property -dict {LOC H32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +#set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +#set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +#set_property -dict {LOC F30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +#set_property -dict {LOC J32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +#set_property -dict {LOC B28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +#set_property -dict {LOC K32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +#set_property -dict {LOC F29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +#set_property -dict {LOC D29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +#set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +#set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +#set_property -dict {LOC H30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +#set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +#set_property -dict {LOC D30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}] +#set_property -dict {LOC E32 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t}] +#set_property -dict {LOC D32 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c}] +#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke}] +#set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n}] +#set_property -dict {LOC E28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +#set_property -dict {LOC D28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt}] +#set_property -dict {LOC J18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +#set_property -dict {LOC L19 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] +#set_property -dict {LOC F19 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_alert_n}] +#set_property -dict {LOC E15 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_ten}] + +#set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] +#set_property -dict {LOC D42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] +#set_property -dict {LOC F39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] +#set_property -dict {LOC G41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] +#set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] +#set_property -dict {LOC G42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] +#set_property -dict {LOC G39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] +#set_property -dict {LOC E42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] +#set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] +#set_property -dict {LOC B41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] +#set_property -dict {LOC B39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] +#set_property -dict {LOC C41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] +#set_property -dict {LOC B38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] +#set_property -dict {LOC C42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] +#set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] +#set_property -dict {LOC C40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] +#set_property -dict {LOC AT36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] +#set_property -dict {LOC AR38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] +#set_property -dict {LOC AP36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] +#set_property -dict {LOC AR37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] +#set_property -dict {LOC AR36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] +#set_property -dict {LOC AP39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] +#set_property -dict {LOC AP37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] +#set_property -dict {LOC AP40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] +#set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] +#set_property -dict {LOC M26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] +#set_property -dict {LOC N26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] +#set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] +#set_property -dict {LOC N25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] +#set_property -dict {LOC L26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] +#set_property -dict {LOC M23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] +#set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] +#set_property -dict {LOC AP41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] +#set_property -dict {LOC AT41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] +#set_property -dict {LOC AP42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] +#set_property -dict {LOC AU40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] +#set_property -dict {LOC AR41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] +#set_property -dict {LOC AV40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] +#set_property -dict {LOC AR42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] +#set_property -dict {LOC AT40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] +#set_property -dict {LOC K28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] +#set_property -dict {LOC K31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] +#set_property -dict {LOC P28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] +#set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] +#set_property -dict {LOC M27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] +#set_property -dict {LOC L31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] +#set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] +#set_property -dict {LOC L28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] +#set_property -dict {LOC D34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] +#set_property -dict {LOC A34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] +#set_property -dict {LOC C34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] +#set_property -dict {LOC A35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] +#set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] +#set_property -dict {LOC A36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] +#set_property -dict {LOC C37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] +#set_property -dict {LOC B34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] +#set_property -dict {LOC B29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] +#set_property -dict {LOC B33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] +#set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] +#set_property -dict {LOC B32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] +#set_property -dict {LOC A28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] +#set_property -dict {LOC A33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] +#set_property -dict {LOC C29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] +#set_property -dict {LOC B31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] +#set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] +#set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] +#set_property -dict {LOC F36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] +#set_property -dict {LOC D37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] +#set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] +#set_property -dict {LOC F33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] +#set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] +#set_property -dict {LOC E33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] +#set_property -dict {LOC F41 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] +#set_property -dict {LOC E41 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] +#set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] +#set_property -dict {LOC A40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] +#set_property -dict {LOC AT37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] +#set_property -dict {LOC AU38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] +#set_property -dict {LOC M24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] +#set_property -dict {LOC L24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] +#set_property -dict {LOC AT42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] +#set_property -dict {LOC AU42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] +#set_property -dict {LOC L30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] +#set_property -dict {LOC K30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] +#set_property -dict {LOC B36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] +#set_property -dict {LOC B37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] +#set_property -dict {LOC A30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] +#set_property -dict {LOC A31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] +#set_property -dict {LOC F35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] +#set_property -dict {LOC E35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] +#set_property -dict {LOC G40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[0]}] +#set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[1]}] +#set_property -dict {LOC AP38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[2]}] +#set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[3]}] +#set_property -dict {LOC AT39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[4]}] +#set_property -dict {LOC M28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[5]}] +#set_property -dict {LOC D35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[6]}] +#set_property -dict {LOC C30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[7]}] +#set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[8]}] + +# DDR4 C3 +# 5x K4A8G165WB-BCTD / MT40A512M16HA-075E +#set_property -dict {LOC F23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}] +#set_property -dict {LOC G23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}] +#set_property -dict {LOC H24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}] +#set_property -dict {LOC F25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}] +#set_property -dict {LOC F26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}] +#set_property -dict {LOC F24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}] +#set_property -dict {LOC K26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}] +#set_property -dict {LOC G27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}] +#set_property -dict {LOC J27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}] +#set_property -dict {LOC G24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}] +#set_property -dict {LOC E25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}] +#set_property -dict {LOC H27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}] +#set_property -dict {LOC E23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}] +#set_property -dict {LOC G26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}] +#set_property -dict {LOC J23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}] +#set_property -dict {LOC D23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}] +#set_property -dict {LOC B27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}] +#set_property -dict {LOC J25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}] +#set_property -dict {LOC K25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}] +#set_property -dict {LOC J24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}] +#set_property -dict {LOC D25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}] +#set_property -dict {LOC E27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t}] +#set_property -dict {LOC D27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c}] +#set_property -dict {LOC E26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke}] +#set_property -dict {LOC H25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n}] +#set_property -dict {LOC D24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}] +#set_property -dict {LOC B22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt}] +#set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}] +#set_property -dict {LOC M16 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}] +#set_property -dict {LOC F20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_alert_n}] +#set_property -dict {LOC J17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_ten}] + +#set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}] +#set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}] +#set_property -dict {LOC F16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}] +#set_property -dict {LOC G16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}] +#set_property -dict {LOC E16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}] +#set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}] +#set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}] +#set_property -dict {LOC F18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}] +#set_property -dict {LOC N12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}] +#set_property -dict {LOC P15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}] +#set_property -dict {LOC M13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}] +#set_property -dict {LOC P12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}] +#set_property -dict {LOC M12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}] +#set_property -dict {LOC N15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}] +#set_property -dict {LOC M14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}] +#set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}] +#set_property -dict {LOC C17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}] +#set_property -dict {LOC C15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}] +#set_property -dict {LOC A16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}] +#set_property -dict {LOC A15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}] +#set_property -dict {LOC B17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}] +#set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}] +#set_property -dict {LOC D18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}] +#set_property -dict {LOC D17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}] +#set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}] +#set_property -dict {LOC L16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}] +#set_property -dict {LOC H15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}] +#set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}] +#set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}] +#set_property -dict {LOC K16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}] +#set_property -dict {LOC K15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}] +#set_property -dict {LOC H16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}] +#set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}] +#set_property -dict {LOC H19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}] +#set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}] +#set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}] +#set_property -dict {LOC K20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}] +#set_property -dict {LOC K18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}] +#set_property -dict {LOC H20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}] +#set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}] +#set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}] +#set_property -dict {LOC B19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}] +#set_property -dict {LOC A21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}] +#set_property -dict {LOC A19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}] +#set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}] +#set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}] +#set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}] +#set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}] +#set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}] +#set_property -dict {LOC N22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}] +#set_property -dict {LOC P20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}] +#set_property -dict {LOC N21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}] +#set_property -dict {LOC P19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}] +#set_property -dict {LOC N20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}] +#set_property -dict {LOC P18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}] +#set_property -dict {LOC P22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}] +#set_property -dict {LOC C25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}] +#set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}] +#set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}] +#set_property -dict {LOC A26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}] +#set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}] +#set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}] +#set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}] +#set_property -dict {LOC A25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}] +#set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}] +#set_property -dict {LOC E21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}] +#set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}] +#set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}] +#set_property -dict {LOC H21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}] +#set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}] +#set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}] +#set_property -dict {LOC D22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}] +#set_property -dict {LOC G14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}] +#set_property -dict {LOC F14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}] +#set_property -dict {LOC P14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}] +#set_property -dict {LOC N14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}] +#set_property -dict {LOC C16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}] +#set_property -dict {LOC B16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}] +#set_property -dict {LOC L15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}] +#set_property -dict {LOC L14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}] +#set_property -dict {LOC K22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}] +#set_property -dict {LOC J22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}] +#set_property -dict {LOC C20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}] +#set_property -dict {LOC C19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}] +#set_property -dict {LOC M21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}] +#set_property -dict {LOC L21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}] +#set_property -dict {LOC B23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}] +#set_property -dict {LOC B24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}] +#set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}] +#set_property -dict {LOC G18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}] +#set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[0]}] +#set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[1]}] +#set_property -dict {LOC B14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[2]}] +#set_property -dict {LOC K17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[3]}] +#set_property -dict {LOC L20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[4]}] +#set_property -dict {LOC B18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[5]}] +#set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[6]}] +#set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[7]}] +#set_property -dict {LOC F21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[8]}] diff --git a/fpga/lib/eth/example/fb2CG/fpga_10g/fpga/Makefile b/fpga/lib/eth/example/fb2CG/fpga_25g/fpga/Makefile similarity index 99% rename from fpga/lib/eth/example/fb2CG/fpga_10g/fpga/Makefile rename to fpga/lib/eth/example/fb2CG/fpga_25g/fpga/Makefile index 046468b34..4efc48e93 100644 --- a/fpga/lib/eth/example/fb2CG/fpga_10g/fpga/Makefile +++ b/fpga/lib/eth/example/fb2CG/fpga_25g/fpga/Makefile @@ -59,6 +59,9 @@ XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl # IP IP_TCL_FILES = ip/eth_xcvr_gt.tcl +# Configuration +CONFIG_TCL_FILES = ./config.tcl + include ../common/vivado.mk program: $(FPGA_TOP).bit diff --git a/fpga/lib/eth/example/fb2CG/fpga_25g/fpga/config.tcl b/fpga/lib/eth/example/fb2CG/fpga_25g/fpga/config.tcl new file mode 100644 index 000000000..756e2b3a1 --- /dev/null +++ b/fpga/lib/eth/example/fb2CG/fpga_25g/fpga/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/fb2CG/fpga_25g/fpga_10g/Makefile b/fpga/lib/eth/example/fb2CG/fpga_25g/fpga_10g/Makefile new file mode 100644 index 000000000..4efc48e93 --- /dev/null +++ b/fpga/lib/eth/example/fb2CG/fpga_25g/fpga_10g/Makefile @@ -0,0 +1,114 @@ + +# FPGA settings +FPGA_PART = xcku15p-ffve1760-2-e +FPGA_TOP = fpga +FPGA_ARCH = kintexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/led_sreg_driver.v +SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete_64.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v +SYN_FILES += lib/eth/rtl/udp_64.v +SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v +SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v +SYN_FILES += lib/eth/rtl/ip_complete_64.v +SYN_FILES += lib/eth/rtl/ip_64.v +SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v +SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += led.tcl +XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl + +# IP +IP_TCL_FILES = ip/eth_xcvr_gt.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%.mcs %.prm: %.bit + echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu512-spi-x1_x2_x4}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + diff --git a/fpga/lib/eth/example/fb2CG/fpga_25g/fpga_10g/config.tcl b/fpga/lib/eth/example/fb2CG/fpga_25g/fpga_10g/config.tcl new file mode 100644 index 000000000..90aa4caeb --- /dev/null +++ b/fpga/lib/eth/example/fb2CG/fpga_25g/fpga_10g/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/fpga/lib/eth/example/fb2CG/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/lib/eth/example/fb2CG/fpga_25g/ip/eth_xcvr_gt.tcl similarity index 100% rename from fpga/lib/eth/example/fb2CG/fpga_10g/ip/eth_xcvr_gt.tcl rename to fpga/lib/eth/example/fb2CG/fpga_25g/ip/eth_xcvr_gt.tcl diff --git a/fpga/lib/eth/example/fb2CG/fpga_10g/led.tcl b/fpga/lib/eth/example/fb2CG/fpga_25g/led.tcl similarity index 100% rename from fpga/lib/eth/example/fb2CG/fpga_10g/led.tcl rename to fpga/lib/eth/example/fb2CG/fpga_25g/led.tcl diff --git a/fpga/lib/eth/example/fb2CG/fpga_10g/lib/eth b/fpga/lib/eth/example/fb2CG/fpga_25g/lib/eth similarity index 100% rename from fpga/lib/eth/example/fb2CG/fpga_10g/lib/eth rename to fpga/lib/eth/example/fb2CG/fpga_25g/lib/eth diff --git a/fpga/lib/eth/example/fb2CG/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/fpga/lib/eth/example/fb2CG/fpga_25g/rtl/eth_xcvr_phy_wrapper.v similarity index 100% rename from fpga/lib/eth/example/fb2CG/fpga_10g/rtl/eth_xcvr_phy_wrapper.v rename to fpga/lib/eth/example/fb2CG/fpga_25g/rtl/eth_xcvr_phy_wrapper.v diff --git a/fpga/lib/eth/example/fb2CG/fpga_10g/rtl/fpga.v b/fpga/lib/eth/example/fb2CG/fpga_25g/rtl/fpga.v similarity index 100% rename from fpga/lib/eth/example/fb2CG/fpga_10g/rtl/fpga.v rename to fpga/lib/eth/example/fb2CG/fpga_25g/rtl/fpga.v diff --git a/fpga/lib/eth/example/fb2CG/fpga_10g/rtl/fpga_core.v b/fpga/lib/eth/example/fb2CG/fpga_25g/rtl/fpga_core.v similarity index 100% rename from fpga/lib/eth/example/fb2CG/fpga_10g/rtl/fpga_core.v rename to fpga/lib/eth/example/fb2CG/fpga_25g/rtl/fpga_core.v diff --git a/fpga/lib/eth/example/fb2CG/fpga_10g/rtl/led_sreg_driver.v b/fpga/lib/eth/example/fb2CG/fpga_25g/rtl/led_sreg_driver.v similarity index 100% rename from fpga/lib/eth/example/fb2CG/fpga_10g/rtl/led_sreg_driver.v rename to fpga/lib/eth/example/fb2CG/fpga_25g/rtl/led_sreg_driver.v diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/rtl/sync_signal.v b/fpga/lib/eth/example/fb2CG/fpga_25g/rtl/sync_signal.v similarity index 100% rename from fpga/lib/eth/example/VCU1525/fpga_10g/rtl/sync_signal.v rename to fpga/lib/eth/example/fb2CG/fpga_25g/rtl/sync_signal.v diff --git a/fpga/lib/eth/example/fb2CG/fpga_10g/tb/fpga_core/Makefile b/fpga/lib/eth/example/fb2CG/fpga_25g/tb/fpga_core/Makefile similarity index 100% rename from fpga/lib/eth/example/fb2CG/fpga_10g/tb/fpga_core/Makefile rename to fpga/lib/eth/example/fb2CG/fpga_25g/tb/fpga_core/Makefile diff --git a/fpga/lib/eth/example/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/lib/eth/example/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py new file mode 100644 index 000000000..25b22280c --- /dev/null +++ b/fpga/lib/eth/example/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -0,0 +1,227 @@ +""" + +Copyright (c) 2020 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +""" + +import logging +import os + +from scapy.layers.l2 import Ether, ARP +from scapy.layers.inet import IP, UDP + +import cocotb_test.simulator + +import cocotb +from cocotb.log import SimLog +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge + +from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = SimLog("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 2.56, units="ns").start()) + + # Ethernet + self.qsfp_source = [] + self.qsfp_sink = [] + + for x in range(2): + sources = [] + sinks = [] + for y in range(4): + cocotb.start_soon(Clock(getattr(dut, f"qsfp_{x}_rx_clk_{y}"), 2.56, units="ns").start()) + source = XgmiiSource(getattr(dut, f"qsfp_{x}_rxd_{y}"), getattr(dut, f"qsfp_{x}_rxc_{y}"), getattr(dut, f"qsfp_{x}_rx_clk_{y}"), getattr(dut, f"qsfp_{x}_rx_rst_{y}")) + sources.append(source) + cocotb.start_soon(Clock(getattr(dut, f"qsfp_{x}_tx_clk_{y}"), 2.56, units="ns").start()) + sink = XgmiiSink(getattr(dut, f"qsfp_{x}_txd_{y}"), getattr(dut, f"qsfp_{x}_txc_{y}"), getattr(dut, f"qsfp_{x}_tx_clk_{y}"), getattr(dut, f"qsfp_{x}_tx_rst_{y}")) + sinks.append(sink) + self.qsfp_source.append(sources) + self.qsfp_sink.append(sinks) + + async def init(self): + + self.dut.rst.setimmediatevalue(0) + for x in range(2): + for y in range(4): + getattr(self.dut, f"qsfp_{x}_rx_rst_{y}").setimmediatevalue(0) + getattr(self.dut, f"qsfp_{x}_tx_rst_{y}").setimmediatevalue(0) + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst.value = 1 + for x in range(2): + for y in range(4): + getattr(self.dut, f"qsfp_{x}_rx_rst_{y}").value = 1 + getattr(self.dut, f"qsfp_{x}_tx_rst_{y}").value = 1 + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst.value = 0 + for x in range(2): + for y in range(4): + getattr(self.dut, f"qsfp_{x}_rx_rst_{y}").value = 0 + getattr(self.dut, f"qsfp_{x}_tx_rst_{y}").value = 0 + + +@cocotb.test() +async def run_test(dut): + + tb = TB(dut) + + await tb.init() + + tb.log.info("test UDP RX packet") + + payload = bytes([x % 256 for x in range(256)]) + eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00') + ip = IP(src='192.168.1.100', dst='192.168.1.128') + udp = UDP(sport=5678, dport=1234) + test_pkt = eth / ip / udp / payload + + test_frame = XgmiiFrame.from_payload(test_pkt.build()) + + await tb.qsfp_source[0][0].send(test_frame) + + tb.log.info("receive ARP request") + + rx_frame = await tb.qsfp_sink[0][0].recv() + + rx_pkt = Ether(bytes(rx_frame.get_payload())) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + assert rx_pkt.dst == 'ff:ff:ff:ff:ff:ff' + assert rx_pkt.src == test_pkt.dst + assert rx_pkt[ARP].hwtype == 1 + assert rx_pkt[ARP].ptype == 0x0800 + assert rx_pkt[ARP].hwlen == 6 + assert rx_pkt[ARP].plen == 4 + assert rx_pkt[ARP].op == 1 + assert rx_pkt[ARP].hwsrc == test_pkt.dst + assert rx_pkt[ARP].psrc == test_pkt[IP].dst + assert rx_pkt[ARP].hwdst == '00:00:00:00:00:00' + assert rx_pkt[ARP].pdst == test_pkt[IP].src + + tb.log.info("send ARP response") + + eth = Ether(src=test_pkt.src, dst=test_pkt.dst) + arp = ARP(hwtype=1, ptype=0x0800, hwlen=6, plen=4, op=2, + hwsrc=test_pkt.src, psrc=test_pkt[IP].src, + hwdst=test_pkt.dst, pdst=test_pkt[IP].dst) + resp_pkt = eth / arp + + resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) + + await tb.qsfp_source[0][0].send(resp_frame) + + tb.log.info("receive UDP packet") + + rx_frame = await tb.qsfp_sink[0][0].recv() + + rx_pkt = Ether(bytes(rx_frame.get_payload())) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + assert rx_pkt.dst == test_pkt.src + assert rx_pkt.src == test_pkt.dst + assert rx_pkt[IP].dst == test_pkt[IP].src + assert rx_pkt[IP].src == test_pkt[IP].dst + assert rx_pkt[UDP].dport == test_pkt[UDP].sport + assert rx_pkt[UDP].sport == test_pkt[UDP].dport + assert rx_pkt[UDP].payload == test_pkt[UDP].payload + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'lib', 'axis', 'rtl')) +eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) + + +def test_fpga_core(request): + dut = "fpga_core" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, f"{dut}.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g_fifo.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), + os.path.join(eth_rtl_dir, "lfsr.v"), + os.path.join(eth_rtl_dir, "eth_axis_rx.v"), + os.path.join(eth_rtl_dir, "eth_axis_tx.v"), + os.path.join(eth_rtl_dir, "udp_complete_64.v"), + os.path.join(eth_rtl_dir, "udp_checksum_gen_64.v"), + os.path.join(eth_rtl_dir, "udp_64.v"), + os.path.join(eth_rtl_dir, "udp_ip_rx_64.v"), + os.path.join(eth_rtl_dir, "udp_ip_tx_64.v"), + os.path.join(eth_rtl_dir, "ip_complete_64.v"), + os.path.join(eth_rtl_dir, "ip_64.v"), + os.path.join(eth_rtl_dir, "ip_eth_rx_64.v"), + os.path.join(eth_rtl_dir, "ip_eth_tx_64.v"), + os.path.join(eth_rtl_dir, "ip_arb_mux.v"), + os.path.join(eth_rtl_dir, "arp.v"), + os.path.join(eth_rtl_dir, "arp_cache.v"), + os.path.join(eth_rtl_dir, "arp_eth_rx.v"), + os.path.join(eth_rtl_dir, "arp_eth_tx.v"), + os.path.join(eth_rtl_dir, "eth_arb_mux.v"), + os.path.join(axis_rtl_dir, "arbiter.v"), + os.path.join(axis_rtl_dir, "priority_encoder.v"), + os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + ] + + parameters = {} + + # parameters['A'] = val + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/fpga/lib/eth/lib/axis/rtl/axis_adapter.v b/fpga/lib/eth/lib/axis/rtl/axis_adapter.v index 288fa16c6..0dedfac0f 100644 --- a/fpga/lib/eth/lib/axis/rtl/axis_adapter.v +++ b/fpga/lib/eth/lib/axis/rtl/axis_adapter.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2014-2018 Alex Forencich +Copyright (c) 2014-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -90,468 +90,235 @@ module axis_adapter # ); // force keep width to 1 when disabled -parameter S_KEEP_WIDTH_INT = S_KEEP_ENABLE ? S_KEEP_WIDTH : 1; -parameter M_KEEP_WIDTH_INT = M_KEEP_ENABLE ? M_KEEP_WIDTH : 1; +localparam S_BYTE_LANES = S_KEEP_ENABLE ? S_KEEP_WIDTH : 1; +localparam M_BYTE_LANES = M_KEEP_ENABLE ? M_KEEP_WIDTH : 1; -// bus word sizes (must be identical) -parameter S_DATA_WORD_SIZE = S_DATA_WIDTH / S_KEEP_WIDTH_INT; -parameter M_DATA_WORD_SIZE = M_DATA_WIDTH / M_KEEP_WIDTH_INT; -// output bus is wider -parameter EXPAND_BUS = M_KEEP_WIDTH_INT > S_KEEP_WIDTH_INT; -// total data and keep widths -parameter DATA_WIDTH = EXPAND_BUS ? M_DATA_WIDTH : S_DATA_WIDTH; -parameter KEEP_WIDTH = EXPAND_BUS ? M_KEEP_WIDTH_INT : S_KEEP_WIDTH_INT; -// required number of segments in wider bus -parameter SEGMENT_COUNT = EXPAND_BUS ? (M_KEEP_WIDTH_INT / S_KEEP_WIDTH_INT) : (S_KEEP_WIDTH_INT / M_KEEP_WIDTH_INT); -parameter SEGMENT_COUNT_WIDTH = SEGMENT_COUNT == 1 ? 1 : $clog2(SEGMENT_COUNT); -// data width and keep width per segment -parameter SEGMENT_DATA_WIDTH = DATA_WIDTH / SEGMENT_COUNT; -parameter SEGMENT_KEEP_WIDTH = KEEP_WIDTH / SEGMENT_COUNT; +// bus byte sizes (must be identical) +localparam S_BYTE_SIZE = S_DATA_WIDTH / S_BYTE_LANES; +localparam M_BYTE_SIZE = M_DATA_WIDTH / M_BYTE_LANES; // bus width assertions initial begin - if (S_DATA_WORD_SIZE * S_KEEP_WIDTH_INT != S_DATA_WIDTH) begin - $error("Error: input data width not evenly divisble (instance %m)"); + if (S_BYTE_SIZE * S_BYTE_LANES != S_DATA_WIDTH) begin + $error("Error: input data width not evenly divisible (instance %m)"); $finish; end - if (M_DATA_WORD_SIZE * M_KEEP_WIDTH_INT != M_DATA_WIDTH) begin - $error("Error: output data width not evenly divisble (instance %m)"); + if (M_BYTE_SIZE * M_BYTE_LANES != M_DATA_WIDTH) begin + $error("Error: output data width not evenly divisible (instance %m)"); $finish; end - if (S_DATA_WORD_SIZE != M_DATA_WORD_SIZE) begin - $error("Error: word size mismatch (instance %m)"); + if (S_BYTE_SIZE != M_BYTE_SIZE) begin + $error("Error: byte size mismatch (instance %m)"); $finish; end end -// state register -localparam [2:0] - STATE_IDLE = 3'd0, - STATE_TRANSFER_IN = 3'd1, - STATE_TRANSFER_OUT = 3'd2; +generate -reg [2:0] state_reg = STATE_IDLE, state_next; +if (M_BYTE_LANES == S_BYTE_LANES) begin : bypass + // same width; bypass -reg [SEGMENT_COUNT_WIDTH-1:0] segment_count_reg = 0, segment_count_next; + assign s_axis_tready = m_axis_tready; -reg last_segment; + assign m_axis_tdata = s_axis_tdata; + assign m_axis_tkeep = M_KEEP_ENABLE ? s_axis_tkeep : {M_KEEP_WIDTH{1'b1}}; + assign m_axis_tvalid = s_axis_tvalid; + assign m_axis_tlast = s_axis_tlast; + assign m_axis_tid = ID_ENABLE ? s_axis_tid : {ID_WIDTH{1'b0}}; + assign m_axis_tdest = DEST_ENABLE ? s_axis_tdest : {DEST_WIDTH{1'b0}}; + assign m_axis_tuser = USER_ENABLE ? s_axis_tuser : {USER_WIDTH{1'b0}}; -reg [DATA_WIDTH-1:0] temp_tdata_reg = {DATA_WIDTH{1'b0}}, temp_tdata_next; -reg [KEEP_WIDTH-1:0] temp_tkeep_reg = {KEEP_WIDTH{1'b0}}, temp_tkeep_next; -reg temp_tlast_reg = 1'b0, temp_tlast_next; -reg [ID_WIDTH-1:0] temp_tid_reg = {ID_WIDTH{1'b0}}, temp_tid_next; -reg [DEST_WIDTH-1:0] temp_tdest_reg = {DEST_WIDTH{1'b0}}, temp_tdest_next; -reg [USER_WIDTH-1:0] temp_tuser_reg = {USER_WIDTH{1'b0}}, temp_tuser_next; +end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize + // output is wider; upsize -// internal datapath -reg [M_DATA_WIDTH-1:0] m_axis_tdata_int; -reg [M_KEEP_WIDTH-1:0] m_axis_tkeep_int; -reg m_axis_tvalid_int; -reg m_axis_tready_int_reg = 1'b0; -reg m_axis_tlast_int; -reg [ID_WIDTH-1:0] m_axis_tid_int; -reg [DEST_WIDTH-1:0] m_axis_tdest_int; -reg [USER_WIDTH-1:0] m_axis_tuser_int; -wire m_axis_tready_int_early; + // required number of segments in wider bus + localparam SEG_COUNT = M_BYTE_LANES / S_BYTE_LANES; + // data width and keep width per segment + localparam SEG_DATA_WIDTH = M_DATA_WIDTH / SEG_COUNT; + localparam SEG_KEEP_WIDTH = M_BYTE_LANES / SEG_COUNT; -reg s_axis_tready_reg = 1'b0, s_axis_tready_next; + reg [$clog2(SEG_COUNT)-1:0] seg_reg = 0; -assign s_axis_tready = s_axis_tready_reg; + reg [S_DATA_WIDTH-1:0] s_axis_tdata_reg = {S_DATA_WIDTH{1'b0}}; + reg [S_KEEP_WIDTH-1:0] s_axis_tkeep_reg = {S_KEEP_WIDTH{1'b0}}; + reg s_axis_tvalid_reg = 1'b0; + reg s_axis_tlast_reg = 1'b0; + reg [ID_WIDTH-1:0] s_axis_tid_reg = {ID_WIDTH{1'b0}}; + reg [DEST_WIDTH-1:0] s_axis_tdest_reg = {DEST_WIDTH{1'b0}}; + reg [USER_WIDTH-1:0] s_axis_tuser_reg = {USER_WIDTH{1'b0}}; -always @* begin - state_next = STATE_IDLE; + reg [M_DATA_WIDTH-1:0] m_axis_tdata_reg = {M_DATA_WIDTH{1'b0}}; + reg [M_KEEP_WIDTH-1:0] m_axis_tkeep_reg = {M_KEEP_WIDTH{1'b0}}; + reg m_axis_tvalid_reg = 1'b0; + reg m_axis_tlast_reg = 1'b0; + reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}}; + reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; + reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}}; - segment_count_next = segment_count_reg; + assign s_axis_tready = !s_axis_tvalid_reg; - last_segment = 0; + assign m_axis_tdata = m_axis_tdata_reg; + assign m_axis_tkeep = M_KEEP_ENABLE ? m_axis_tkeep_reg : {M_KEEP_WIDTH{1'b1}}; + assign m_axis_tvalid = m_axis_tvalid_reg; + assign m_axis_tlast = m_axis_tlast_reg; + assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; + assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; + assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; - temp_tdata_next = temp_tdata_reg; - temp_tkeep_next = temp_tkeep_reg; - temp_tlast_next = temp_tlast_reg; - temp_tid_next = temp_tid_reg; - temp_tdest_next = temp_tdest_reg; - temp_tuser_next = temp_tuser_reg; + always @(posedge clk) begin + m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready; - if (EXPAND_BUS) begin - m_axis_tdata_int = temp_tdata_reg; - m_axis_tkeep_int = temp_tkeep_reg; - m_axis_tlast_int = temp_tlast_reg; - end else begin - m_axis_tdata_int = {M_DATA_WIDTH{1'b0}}; - m_axis_tkeep_int = {M_KEEP_WIDTH{1'b0}}; - m_axis_tlast_int = 1'b0; - end - m_axis_tvalid_int = 1'b0; - m_axis_tid_int = temp_tid_reg; - m_axis_tdest_int = temp_tdest_reg; - m_axis_tuser_int = temp_tuser_reg; + if (!m_axis_tvalid_reg || m_axis_tready) begin + // output register empty - s_axis_tready_next = 1'b0; - - case (state_reg) - STATE_IDLE: begin - // idle state - no data in registers - if (SEGMENT_COUNT == 1) begin - // output and input same width - just act like a register - - // accept data next cycle if output register ready next cycle - s_axis_tready_next = m_axis_tready_int_early; - - // transfer through - m_axis_tdata_int = s_axis_tdata; - m_axis_tkeep_int = S_KEEP_ENABLE ? s_axis_tkeep : 1'b1; - m_axis_tvalid_int = s_axis_tvalid; - m_axis_tlast_int = s_axis_tlast; - m_axis_tid_int = s_axis_tid; - m_axis_tdest_int = s_axis_tdest; - m_axis_tuser_int = s_axis_tuser; - - state_next = STATE_IDLE; - end else if (EXPAND_BUS) begin - // output bus is wider - - // accept new data - s_axis_tready_next = 1'b1; - - if (s_axis_tready && s_axis_tvalid) begin - // word transfer in - store it in data register - - // pass complete input word, zero-extended to temp register - temp_tdata_next = s_axis_tdata; - temp_tkeep_next = S_KEEP_ENABLE ? s_axis_tkeep : 1'b1; - temp_tlast_next = s_axis_tlast; - temp_tid_next = s_axis_tid; - temp_tdest_next = s_axis_tdest; - temp_tuser_next = s_axis_tuser; - - // first input segment complete - segment_count_next = 1; - - if (s_axis_tlast) begin - // got last signal on first segment, so output it - s_axis_tready_next = 1'b0; - state_next = STATE_TRANSFER_OUT; - end else begin - // otherwise, transfer in the rest of the words - s_axis_tready_next = 1'b1; - state_next = STATE_TRANSFER_IN; - end - end else begin - state_next = STATE_IDLE; - end + if (seg_reg == 0) begin + m_axis_tdata_reg[seg_reg*SEG_DATA_WIDTH +: SEG_DATA_WIDTH] <= s_axis_tvalid_reg ? s_axis_tdata_reg : s_axis_tdata; + m_axis_tkeep_reg <= s_axis_tvalid_reg ? s_axis_tkeep_reg : s_axis_tkeep; end else begin - // output bus is narrower + m_axis_tdata_reg[seg_reg*SEG_DATA_WIDTH +: SEG_DATA_WIDTH] <= s_axis_tdata; + m_axis_tkeep_reg[seg_reg*SEG_KEEP_WIDTH +: SEG_KEEP_WIDTH] <= s_axis_tkeep; + end + m_axis_tlast_reg <= s_axis_tvalid_reg ? s_axis_tlast_reg : s_axis_tlast; + m_axis_tid_reg <= s_axis_tvalid_reg ? s_axis_tid_reg : s_axis_tid; + m_axis_tdest_reg <= s_axis_tvalid_reg ? s_axis_tdest_reg : s_axis_tdest; + m_axis_tuser_reg <= s_axis_tvalid_reg ? s_axis_tuser_reg : s_axis_tuser; - // accept new data - s_axis_tready_next = 1'b1; + if (s_axis_tvalid_reg) begin + // consume data from buffer + s_axis_tvalid_reg <= 1'b0; - if (s_axis_tready && s_axis_tvalid) begin - // word transfer in - store it in data register - segment_count_next = 0; - - // is this the last segment? - if (SEGMENT_COUNT == 1) begin - // last segment by counter value - last_segment = 1'b1; - end else if (S_KEEP_ENABLE && s_axis_tkeep[SEGMENT_KEEP_WIDTH-1:0] != {SEGMENT_KEEP_WIDTH{1'b1}}) begin - // last segment by tkeep fall in current segment - last_segment = 1'b1; - end else if (S_KEEP_ENABLE && s_axis_tkeep[(SEGMENT_KEEP_WIDTH*2)-1:SEGMENT_KEEP_WIDTH] == {SEGMENT_KEEP_WIDTH{1'b0}}) begin - // last segment by tkeep fall at end of current segment - last_segment = 1'b1; - end else begin - last_segment = 1'b0; - end - - // pass complete input word, zero-extended to temp register - temp_tdata_next = s_axis_tdata; - temp_tkeep_next = S_KEEP_ENABLE ? s_axis_tkeep : 1'b1; - temp_tlast_next = s_axis_tlast; - temp_tid_next = s_axis_tid; - temp_tdest_next = s_axis_tdest; - temp_tuser_next = s_axis_tuser; - - // short-circuit and get first word out the door - m_axis_tdata_int = s_axis_tdata[SEGMENT_DATA_WIDTH-1:0]; - m_axis_tkeep_int = s_axis_tkeep[SEGMENT_KEEP_WIDTH-1:0]; - m_axis_tvalid_int = 1'b1; - m_axis_tlast_int = s_axis_tlast & last_segment; - m_axis_tid_int = s_axis_tid; - m_axis_tdest_int = s_axis_tdest; - m_axis_tuser_int = s_axis_tuser; - - if (m_axis_tready_int_reg) begin - // if output register is ready for first word, then move on to the next one - segment_count_next = 1; - end - - if (!last_segment || !m_axis_tready_int_reg) begin - // continue outputting words - s_axis_tready_next = 1'b0; - state_next = STATE_TRANSFER_OUT; - end else begin - state_next = STATE_IDLE; - end + if (s_axis_tlast_reg || seg_reg == SEG_COUNT-1) begin + seg_reg <= 0; + m_axis_tvalid_reg <= 1'b1; end else begin - state_next = STATE_IDLE; + seg_reg <= seg_reg + 1; + end + end else if (s_axis_tvalid) begin + // data direct from input + if (s_axis_tlast || seg_reg == SEG_COUNT-1) begin + seg_reg <= 0; + m_axis_tvalid_reg <= 1'b1; + end else begin + seg_reg <= seg_reg + 1; end end + end else if (s_axis_tvalid && s_axis_tready) begin + // store input data in skid buffer + s_axis_tdata_reg <= s_axis_tdata; + s_axis_tkeep_reg <= s_axis_tkeep; + s_axis_tvalid_reg <= 1'b1; + s_axis_tlast_reg <= s_axis_tlast; + s_axis_tid_reg <= s_axis_tid; + s_axis_tdest_reg <= s_axis_tdest; + s_axis_tuser_reg <= s_axis_tuser; end - STATE_TRANSFER_IN: begin - // transfer word to temp registers - // only used when output is wider - // accept new data - s_axis_tready_next = 1'b1; - - if (s_axis_tready && s_axis_tvalid) begin - // word transfer in - store in data register - - temp_tdata_next[segment_count_reg*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = s_axis_tdata; - temp_tkeep_next[segment_count_reg*SEGMENT_KEEP_WIDTH +: SEGMENT_KEEP_WIDTH] = S_KEEP_ENABLE ? s_axis_tkeep : 1'b1; - temp_tlast_next = s_axis_tlast; - temp_tid_next = s_axis_tid; - temp_tdest_next = s_axis_tdest; - temp_tuser_next = s_axis_tuser; - - segment_count_next = segment_count_reg + 1; - - if ((segment_count_reg == SEGMENT_COUNT-1) || s_axis_tlast) begin - // terminated by counter or tlast signal, output complete word - // read input word next cycle if output will be ready - s_axis_tready_next = m_axis_tready_int_early; - state_next = STATE_TRANSFER_OUT; - end else begin - // more words to read - s_axis_tready_next = 1'b1; - state_next = STATE_TRANSFER_IN; - end - end else begin - state_next = STATE_TRANSFER_IN; - end + if (rst) begin + seg_reg <= 0; + s_axis_tvalid_reg <= 1'b0; + m_axis_tvalid_reg <= 1'b0; end - STATE_TRANSFER_OUT: begin - // transfer word to output registers + end - if (EXPAND_BUS) begin - // output bus is wider +end else begin : downsize + // output is narrower; downsize - // do not accept new data - s_axis_tready_next = 1'b0; + // required number of segments in wider bus + localparam SEG_COUNT = S_BYTE_LANES / M_BYTE_LANES; + // data width and keep width per segment + localparam SEG_DATA_WIDTH = S_DATA_WIDTH / SEG_COUNT; + localparam SEG_KEEP_WIDTH = S_BYTE_LANES / SEG_COUNT; - // single-cycle output of entire stored word (output wider) - m_axis_tdata_int = temp_tdata_reg; - m_axis_tkeep_int = temp_tkeep_reg; - m_axis_tvalid_int = 1'b1; - m_axis_tlast_int = temp_tlast_reg; - m_axis_tid_int = temp_tid_reg; - m_axis_tdest_int = temp_tdest_reg; - m_axis_tuser_int = temp_tuser_reg; + reg [S_DATA_WIDTH-1:0] s_axis_tdata_reg = {S_DATA_WIDTH{1'b0}}; + reg [S_KEEP_WIDTH-1:0] s_axis_tkeep_reg = {S_KEEP_WIDTH{1'b0}}; + reg s_axis_tvalid_reg = 1'b0; + reg s_axis_tlast_reg = 1'b0; + reg [ID_WIDTH-1:0] s_axis_tid_reg = {ID_WIDTH{1'b0}}; + reg [DEST_WIDTH-1:0] s_axis_tdest_reg = {DEST_WIDTH{1'b0}}; + reg [USER_WIDTH-1:0] s_axis_tuser_reg = {USER_WIDTH{1'b0}}; - if (m_axis_tready_int_reg) begin - // word transfer out + reg [M_DATA_WIDTH-1:0] m_axis_tdata_reg = {M_DATA_WIDTH{1'b0}}; + reg [M_KEEP_WIDTH-1:0] m_axis_tkeep_reg = {M_KEEP_WIDTH{1'b0}}; + reg m_axis_tvalid_reg = 1'b0; + reg m_axis_tlast_reg = 1'b0; + reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}}; + reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; + reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}}; - if (s_axis_tready && s_axis_tvalid) begin - // word transfer in + assign s_axis_tready = !s_axis_tvalid_reg; - // pass complete input word, zero-extended to temp register - temp_tdata_next = s_axis_tdata; - temp_tkeep_next = S_KEEP_ENABLE ? s_axis_tkeep : 1'b1; - temp_tlast_next = s_axis_tlast; - temp_tid_next = s_axis_tid; - temp_tdest_next = s_axis_tdest; - temp_tuser_next = s_axis_tuser; + assign m_axis_tdata = m_axis_tdata_reg; + assign m_axis_tkeep = M_KEEP_ENABLE ? m_axis_tkeep_reg : {M_KEEP_WIDTH{1'b1}}; + assign m_axis_tvalid = m_axis_tvalid_reg; + assign m_axis_tlast = m_axis_tlast_reg; + assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; + assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; + assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; - // first input segment complete - segment_count_next = 1; + always @(posedge clk) begin + m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready; - if (s_axis_tlast) begin - // got last signal on first segment, so output it - s_axis_tready_next = 1'b0; - state_next = STATE_TRANSFER_OUT; - end else begin - // otherwise, transfer in the rest of the words - s_axis_tready_next = 1'b1; - state_next = STATE_TRANSFER_IN; - end - end else begin - s_axis_tready_next = 1'b1; - state_next = STATE_IDLE; - end - end else begin - state_next = STATE_TRANSFER_OUT; + if (!m_axis_tvalid_reg || m_axis_tready) begin + // output register empty + + m_axis_tdata_reg <= s_axis_tvalid_reg ? s_axis_tdata_reg : s_axis_tdata; + m_axis_tkeep_reg <= s_axis_tvalid_reg ? s_axis_tkeep_reg : s_axis_tkeep; + m_axis_tlast_reg <= 1'b0; + m_axis_tid_reg <= s_axis_tvalid_reg ? s_axis_tid_reg : s_axis_tid; + m_axis_tdest_reg <= s_axis_tvalid_reg ? s_axis_tdest_reg : s_axis_tdest; + m_axis_tuser_reg <= s_axis_tvalid_reg ? s_axis_tuser_reg : s_axis_tuser; + + if (s_axis_tvalid_reg) begin + // buffer has data; shift out from buffer + s_axis_tdata_reg <= s_axis_tdata_reg >> SEG_DATA_WIDTH; + s_axis_tkeep_reg <= s_axis_tkeep_reg >> SEG_KEEP_WIDTH; + + m_axis_tvalid_reg <= 1'b1; + + if ((s_axis_tkeep_reg >> SEG_KEEP_WIDTH) == 0) begin + s_axis_tvalid_reg <= 1'b0; + m_axis_tlast_reg <= s_axis_tlast_reg; end - end else begin - // output bus is narrower + end else if (s_axis_tvalid && s_axis_tready) begin + // buffer is empty; store from input + s_axis_tdata_reg <= s_axis_tdata >> SEG_DATA_WIDTH; + s_axis_tkeep_reg <= s_axis_tkeep >> SEG_KEEP_WIDTH; + s_axis_tlast_reg <= s_axis_tlast; + s_axis_tid_reg <= s_axis_tid; + s_axis_tdest_reg <= s_axis_tdest; + s_axis_tuser_reg <= s_axis_tuser; - // do not accept new data - s_axis_tready_next = 1'b0; + m_axis_tvalid_reg <= 1'b1; - // is this the last segment? - if (segment_count_reg == SEGMENT_COUNT-1) begin - // last segment by counter value - last_segment = 1'b1; - end else if (temp_tkeep_reg[segment_count_reg*SEGMENT_KEEP_WIDTH +: SEGMENT_KEEP_WIDTH] != {SEGMENT_KEEP_WIDTH{1'b1}}) begin - // last segment by tkeep fall in current segment - last_segment = 1'b1; - end else if (temp_tkeep_reg[(segment_count_reg+1)*SEGMENT_KEEP_WIDTH +: SEGMENT_KEEP_WIDTH] == {SEGMENT_KEEP_WIDTH{1'b0}}) begin - // last segment by tkeep fall at end of current segment - last_segment = 1'b1; + if ((s_axis_tkeep >> SEG_KEEP_WIDTH) == 0) begin + s_axis_tvalid_reg <= 1'b0; + m_axis_tlast_reg <= s_axis_tlast; end else begin - last_segment = 1'b0; - end - - // output current part of stored word (output narrower) - m_axis_tdata_int = temp_tdata_reg[segment_count_reg*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH]; - m_axis_tkeep_int = temp_tkeep_reg[segment_count_reg*SEGMENT_KEEP_WIDTH +: SEGMENT_KEEP_WIDTH]; - m_axis_tvalid_int = 1'b1; - m_axis_tlast_int = temp_tlast_reg && last_segment; - m_axis_tid_int = temp_tid_reg; - m_axis_tdest_int = temp_tdest_reg; - m_axis_tuser_int = temp_tuser_reg; - - if (m_axis_tready_int_reg) begin - // word transfer out - - segment_count_next = segment_count_reg + 1; - - if (last_segment) begin - // terminated by counter or tlast signal - - s_axis_tready_next = 1'b1; - state_next = STATE_IDLE; - end else begin - // more words to write - state_next = STATE_TRANSFER_OUT; - end - end else begin - state_next = STATE_TRANSFER_OUT; + s_axis_tvalid_reg <= 1'b1; end end + end else if (s_axis_tvalid && s_axis_tready) begin + // store input data + s_axis_tdata_reg <= s_axis_tdata; + s_axis_tkeep_reg <= s_axis_tkeep; + s_axis_tvalid_reg <= 1'b1; + s_axis_tlast_reg <= s_axis_tlast; + s_axis_tid_reg <= s_axis_tid; + s_axis_tdest_reg <= s_axis_tdest; + s_axis_tuser_reg <= s_axis_tuser; end - endcase -end -always @(posedge clk) begin - if (rst) begin - state_reg <= STATE_IDLE; - s_axis_tready_reg <= 1'b0; - end else begin - state_reg <= state_next; - - s_axis_tready_reg <= s_axis_tready_next; - end - - segment_count_reg <= segment_count_next; - - temp_tdata_reg <= temp_tdata_next; - temp_tkeep_reg <= temp_tkeep_next; - temp_tlast_reg <= temp_tlast_next; - temp_tid_reg <= temp_tid_next; - temp_tdest_reg <= temp_tdest_next; - temp_tuser_reg <= temp_tuser_next; -end - -// output datapath logic -reg [M_DATA_WIDTH-1:0] m_axis_tdata_reg = {M_DATA_WIDTH{1'b0}}; -reg [M_KEEP_WIDTH-1:0] m_axis_tkeep_reg = {M_KEEP_WIDTH{1'b0}}; -reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next; -reg m_axis_tlast_reg = 1'b0; -reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}}; -reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; -reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}}; - -reg [M_DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {M_DATA_WIDTH{1'b0}}; -reg [M_KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {M_KEEP_WIDTH{1'b0}}; -reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next; -reg temp_m_axis_tlast_reg = 1'b0; -reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}}; -reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; -reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}}; - -// datapath control -reg store_axis_int_to_output; -reg store_axis_int_to_temp; -reg store_axis_temp_to_output; - -assign m_axis_tdata = m_axis_tdata_reg; -assign m_axis_tkeep = M_KEEP_ENABLE ? m_axis_tkeep_reg : {M_KEEP_WIDTH{1'b1}}; -assign m_axis_tvalid = m_axis_tvalid_reg; -assign m_axis_tlast = m_axis_tlast_reg; -assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; -assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; -assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; - -// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) -assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int)); - -always @* begin - // transfer sink ready state to source - m_axis_tvalid_next = m_axis_tvalid_reg; - temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg; - - store_axis_int_to_output = 1'b0; - store_axis_int_to_temp = 1'b0; - store_axis_temp_to_output = 1'b0; - - if (m_axis_tready_int_reg) begin - // input is ready - if (m_axis_tready || !m_axis_tvalid_reg) begin - // output is ready or currently not valid, transfer data to output - m_axis_tvalid_next = m_axis_tvalid_int; - store_axis_int_to_output = 1'b1; - end else begin - // output is not ready, store input in temp - temp_m_axis_tvalid_next = m_axis_tvalid_int; - store_axis_int_to_temp = 1'b1; + if (rst) begin + s_axis_tvalid_reg <= 1'b0; + m_axis_tvalid_reg <= 1'b0; end - end else if (m_axis_tready) begin - // input is not ready, but output is ready - m_axis_tvalid_next = temp_m_axis_tvalid_reg; - temp_m_axis_tvalid_next = 1'b0; - store_axis_temp_to_output = 1'b1; end + end -always @(posedge clk) begin - m_axis_tvalid_reg <= m_axis_tvalid_next; - m_axis_tready_int_reg <= m_axis_tready_int_early; - temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next; - - // datapath - if (store_axis_int_to_output) begin - m_axis_tdata_reg <= m_axis_tdata_int; - m_axis_tkeep_reg <= m_axis_tkeep_int; - m_axis_tlast_reg <= m_axis_tlast_int; - m_axis_tid_reg <= m_axis_tid_int; - m_axis_tdest_reg <= m_axis_tdest_int; - m_axis_tuser_reg <= m_axis_tuser_int; - end else if (store_axis_temp_to_output) begin - m_axis_tdata_reg <= temp_m_axis_tdata_reg; - m_axis_tkeep_reg <= temp_m_axis_tkeep_reg; - m_axis_tlast_reg <= temp_m_axis_tlast_reg; - m_axis_tid_reg <= temp_m_axis_tid_reg; - m_axis_tdest_reg <= temp_m_axis_tdest_reg; - m_axis_tuser_reg <= temp_m_axis_tuser_reg; - end - - if (store_axis_int_to_temp) begin - temp_m_axis_tdata_reg <= m_axis_tdata_int; - temp_m_axis_tkeep_reg <= m_axis_tkeep_int; - temp_m_axis_tlast_reg <= m_axis_tlast_int; - temp_m_axis_tid_reg <= m_axis_tid_int; - temp_m_axis_tdest_reg <= m_axis_tdest_int; - temp_m_axis_tuser_reg <= m_axis_tuser_int; - end - - if (rst) begin - m_axis_tvalid_reg <= 1'b0; - m_axis_tready_int_reg <= 1'b0; - temp_m_axis_tvalid_reg <= 1'b0; - end -end +endgenerate endmodule diff --git a/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v b/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v index fbe9c891e..76eeb8d85 100644 --- a/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v +++ b/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2014-2021 Alex Forencich +Copyright (c) 2014-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -80,7 +80,15 @@ module axis_async_fifo # // Drop incoming frames when full // When set, s_axis_tready is always asserted // Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set - parameter DROP_WHEN_FULL = 0 + parameter DROP_WHEN_FULL = 0, + // Mark incoming frames as bad frames when full + // When set, s_axis_tready is always asserted + // Requires FRAME_FIFO to be clear + parameter MARK_WHEN_FULL = 0, + // Enable pause request input + parameter PAUSE_ENABLE = 0, + // Pause between frames + parameter FRAME_PAUSE = FRAME_FIFO ) ( /* @@ -111,12 +119,24 @@ module axis_async_fifo # output wire [DEST_WIDTH-1:0] m_axis_tdest, output wire [USER_WIDTH-1:0] m_axis_tuser, + /* + * Pause + */ + input wire s_pause_req, + output wire s_pause_ack, + input wire m_pause_req, + output wire m_pause_ack, + /* * Status */ + output wire [$clog2(DEPTH):0] s_status_depth, + output wire [$clog2(DEPTH):0] s_status_depth_commit, output wire s_status_overflow, output wire s_status_bad_frame, output wire s_status_good_frame, + output wire [$clog2(DEPTH):0] m_status_depth, + output wire [$clog2(DEPTH):0] m_status_depth_commit, output wire m_status_overflow, output wire m_status_bad_frame, output wire m_status_good_frame @@ -148,10 +168,20 @@ initial begin $finish; end - if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin + if ((DROP_BAD_FRAME || MARK_WHEN_FULL) && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin $error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)"); $finish; end + + if (MARK_WHEN_FULL && FRAME_FIFO) begin + $error("Error: MARK_WHEN_FULL is not compatible with FRAME_FIFO (instance %m)"); + $finish; + end + + if (MARK_WHEN_FULL && !LAST_ENABLE) begin + $error("Error: MARK_WHEN_FULL set requires LAST_ENABLE set (instance %m)"); + $finish; + end end localparam KEEP_OFFSET = DATA_WIDTH; @@ -161,13 +191,25 @@ localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0); localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0); localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0); +function [ADDR_WIDTH:0] bin2gray(input [ADDR_WIDTH:0] b); + bin2gray = b ^ (b >> 1); +endfunction + +function [ADDR_WIDTH:0] gray2bin(input [ADDR_WIDTH:0] g); + integer i; + for (i = 0; i <= ADDR_WIDTH; i = i + 1) begin + gray2bin[i] = ^(g >> i); + end +endfunction + reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}; -reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}; +reg [ADDR_WIDTH:0] wr_ptr_commit_reg = {ADDR_WIDTH+1{1'b0}}; reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}; -reg [ADDR_WIDTH:0] wr_ptr_sync_gray_reg = {ADDR_WIDTH+1{1'b0}}; -reg [ADDR_WIDTH:0] wr_ptr_cur_gray_reg = {ADDR_WIDTH+1{1'b0}}; +reg [ADDR_WIDTH:0] wr_ptr_sync_commit_reg = {ADDR_WIDTH+1{1'b0}}; reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}; reg [ADDR_WIDTH:0] rd_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}; +reg [ADDR_WIDTH:0] wr_ptr_conv_reg = {ADDR_WIDTH+1{1'b0}}; +reg [ADDR_WIDTH:0] rd_ptr_conv_reg = {ADDR_WIDTH+1{1'b0}}; reg [ADDR_WIDTH:0] wr_ptr_temp; reg [ADDR_WIDTH:0] rd_ptr_temp; @@ -177,6 +219,8 @@ reg [ADDR_WIDTH:0] wr_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}}; (* SHREG_EXTRACT = "NO" *) reg [ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}}; (* SHREG_EXTRACT = "NO" *) +reg [ADDR_WIDTH:0] wr_ptr_commit_sync_reg = {ADDR_WIDTH+1{1'b0}}; +(* SHREG_EXTRACT = "NO" *) reg [ADDR_WIDTH:0] rd_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}}; (* SHREG_EXTRACT = "NO" *) reg [ADDR_WIDTH:0] rd_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}}; @@ -218,11 +262,10 @@ reg [RAM_PIPELINE+1-1:0] m_axis_tvalid_pipe_reg = 0; // full when first TWO MSBs do NOT match, but rest matches // (gray code equivalent of first MSB different but rest same) wire full = wr_ptr_gray_reg == (rd_ptr_gray_sync2_reg ^ {2'b11, {ADDR_WIDTH-1{1'b0}}}); -wire full_cur = wr_ptr_cur_gray_reg == (rd_ptr_gray_sync2_reg ^ {2'b11, {ADDR_WIDTH-1{1'b0}}}); // empty when pointers match exactly -wire empty = rd_ptr_gray_reg == (FRAME_FIFO ? wr_ptr_gray_sync1_reg : wr_ptr_gray_sync2_reg); +wire empty = FRAME_FIFO ? (rd_ptr_reg == wr_ptr_commit_sync_reg) : (rd_ptr_gray_reg == wr_ptr_gray_sync2_reg); // overflow within packet -wire full_wr = wr_ptr_reg == (wr_ptr_cur_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}}); +wire full_wr = wr_ptr_reg == (wr_ptr_commit_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}}); // control signals reg write; @@ -233,6 +276,7 @@ reg s_frame_reg = 1'b0; reg m_frame_reg = 1'b0; reg drop_frame_reg = 1'b0; +reg mark_frame_reg = 1'b0; reg send_frame_reg = 1'b0; reg overflow_reg = 1'b0; reg bad_frame_reg = 1'b0; @@ -241,6 +285,11 @@ reg good_frame_reg = 1'b0; reg m_drop_frame_reg = 1'b0; reg m_terminate_frame_reg = 1'b0; +reg [ADDR_WIDTH:0] s_depth_reg = 0; +reg [ADDR_WIDTH:0] s_depth_commit_reg = 0; +reg [ADDR_WIDTH:0] m_depth_reg = 0; +reg [ADDR_WIDTH:0] m_depth_commit_reg = 0; + reg overflow_sync1_reg = 1'b0; reg overflow_sync2_reg = 1'b0; reg overflow_sync3_reg = 1'b0; @@ -254,21 +303,22 @@ reg good_frame_sync2_reg = 1'b0; reg good_frame_sync3_reg = 1'b0; reg good_frame_sync4_reg = 1'b0; -assign s_axis_tready = (FRAME_FIFO ? (!full_cur || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : !full) && !s_rst_sync3_reg; +assign s_axis_tready = (FRAME_FIFO ? (!full || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : (!full || MARK_WHEN_FULL)) && !s_rst_sync3_reg; wire [WIDTH-1:0] s_axis; generate assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata; if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET +: KEEP_WIDTH] = s_axis_tkeep; - if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast; + if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast | mark_frame_reg; if (ID_ENABLE) assign s_axis[ID_OFFSET +: ID_WIDTH] = s_axis_tid; if (DEST_ENABLE) assign s_axis[DEST_OFFSET +: DEST_WIDTH] = s_axis_tdest; - if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = s_axis_tuser; + if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = mark_frame_reg ? USER_BAD_FRAME_VALUE : s_axis_tuser; endgenerate wire [WIDTH-1:0] m_axis = m_axis_pipe_reg[RAM_PIPELINE+1-1]; +wire m_axis_tready_pipe; wire m_axis_tvalid_pipe = m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1]; wire [DATA_WIDTH-1:0] m_axis_tdata_pipe = m_axis[DATA_WIDTH-1:0]; @@ -278,12 +328,26 @@ wire [ID_WIDTH-1:0] m_axis_tid_pipe = ID_ENABLE ? m_axis[ID_OFFSET +: ID wire [DEST_WIDTH-1:0] m_axis_tdest_pipe = DEST_ENABLE ? m_axis[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}}; wire [USER_WIDTH-1:0] m_axis_tuser_pipe = USER_ENABLE ? (m_terminate_frame_reg ? USER_BAD_FRAME_VALUE : m_axis[USER_OFFSET +: USER_WIDTH]) : {USER_WIDTH{1'b0}}; +wire m_axis_tready_out; +wire m_axis_tvalid_out; + +wire [DATA_WIDTH-1:0] m_axis_tdata_out; +wire [KEEP_WIDTH-1:0] m_axis_tkeep_out; +wire m_axis_tlast_out; +wire [ID_WIDTH-1:0] m_axis_tid_out; +wire [DEST_WIDTH-1:0] m_axis_tdest_out; +wire [USER_WIDTH-1:0] m_axis_tuser_out; + wire pipe_ready; +assign s_status_depth = (KEEP_ENABLE && KEEP_WIDTH > 1) ? {s_depth_reg, {$clog2(KEEP_WIDTH){1'b0}}} : s_depth_reg; +assign s_status_depth_commit = (KEEP_ENABLE && KEEP_WIDTH > 1) ? {s_depth_commit_reg, {$clog2(KEEP_WIDTH){1'b0}}} : s_depth_commit_reg; assign s_status_overflow = overflow_reg; assign s_status_bad_frame = bad_frame_reg; assign s_status_good_frame = good_frame_reg; +assign m_status_depth = (KEEP_ENABLE && KEEP_WIDTH > 1) ? {m_depth_reg, {$clog2(KEEP_WIDTH){1'b0}}} : m_depth_reg; +assign m_status_depth_commit = (KEEP_ENABLE && KEEP_WIDTH > 1) ? {m_depth_commit_reg, {$clog2(KEEP_WIDTH){1'b0}}} : m_depth_commit_reg; assign m_status_overflow = overflow_sync3_reg ^ overflow_sync4_reg; assign m_status_bad_frame = bad_frame_sync3_reg ^ bad_frame_sync4_reg; assign m_status_good_frame = good_frame_sync3_reg ^ good_frame_sync4_reg; @@ -326,7 +390,7 @@ always @(posedge s_clk) begin if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin // no sync in progress; sync update wr_ptr_update_valid_reg <= 1'b0; - wr_ptr_sync_gray_reg <= wr_ptr_gray_reg; + wr_ptr_sync_commit_reg <= wr_ptr_commit_reg; wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg; end end @@ -346,95 +410,129 @@ always @(posedge s_clk) begin end end - if (s_axis_tready && s_axis_tvalid) begin - // transfer in - if (!FRAME_FIFO) begin - // normal FIFO mode - mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis; - if (drop_frame_reg && LAST_ENABLE) begin - // currently dropping frame - // (only for frame transfers interrupted by sink reset) + if (FRAME_FIFO) begin + // frame FIFO mode + if (s_axis_tready && s_axis_tvalid) begin + // transfer in + if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin + // full, packet overflow, or currently dropping frame + // drop frame + drop_frame_reg <= 1'b1; if (s_axis_tlast) begin - // end of frame, clear drop flag + // end of frame, reset write pointer + wr_ptr_temp = wr_ptr_commit_reg; + wr_ptr_reg <= wr_ptr_temp; + wr_ptr_gray_reg <= bin2gray(wr_ptr_temp); drop_frame_reg <= 1'b0; + overflow_reg <= 1'b1; end end else begin - // update pointers + mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis; wr_ptr_temp = wr_ptr_reg + 1; wr_ptr_reg <= wr_ptr_temp; - wr_ptr_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1); - end - end else if ((full_cur && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin - // full, packet overflow, or currently dropping frame - // drop frame - drop_frame_reg <= 1'b1; - if (s_axis_tlast) begin - // end of frame, reset write pointer - wr_ptr_temp = wr_ptr_reg; - wr_ptr_cur_reg <= wr_ptr_temp; - wr_ptr_cur_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1); - drop_frame_reg <= 1'b0; - overflow_reg <= 1'b1; - end - end else begin - mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= s_axis; - wr_ptr_temp = wr_ptr_cur_reg + 1; - wr_ptr_cur_reg <= wr_ptr_temp; - wr_ptr_cur_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1); - if (s_axis_tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin - // end of frame or send frame - send_frame_reg <= !s_axis_tlast; - if (s_axis_tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin - // bad packet, reset write pointer - wr_ptr_temp = wr_ptr_reg; - wr_ptr_cur_reg <= wr_ptr_temp; - wr_ptr_cur_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1); - bad_frame_reg <= 1'b1; - end else begin - // good packet or packet overflow, update write pointer - wr_ptr_temp = wr_ptr_cur_reg + 1; - wr_ptr_reg <= wr_ptr_temp; - wr_ptr_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1); - - if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin - // no sync in progress; sync update - wr_ptr_update_valid_reg <= 1'b0; - wr_ptr_sync_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1); - wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg; + wr_ptr_gray_reg <= bin2gray(wr_ptr_temp); + if (s_axis_tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin + // end of frame or send frame + send_frame_reg <= !s_axis_tlast; + if (s_axis_tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin + // bad packet, reset write pointer + wr_ptr_temp = wr_ptr_commit_reg; + wr_ptr_reg <= wr_ptr_temp; + wr_ptr_gray_reg <= bin2gray(wr_ptr_temp); + bad_frame_reg <= 1'b1; end else begin - // sync in progress; flag it for later - wr_ptr_update_valid_reg <= 1'b1; - end + // good packet or packet overflow, update write pointer + wr_ptr_temp = wr_ptr_reg + 1; + wr_ptr_reg <= wr_ptr_temp; + wr_ptr_commit_reg <= wr_ptr_temp; + wr_ptr_gray_reg <= bin2gray(wr_ptr_temp); - good_frame_reg <= s_axis_tlast; + if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin + // no sync in progress; sync update + wr_ptr_update_valid_reg <= 1'b0; + wr_ptr_sync_commit_reg <= wr_ptr_temp; + wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg; + end else begin + // sync in progress; flag it for later + wr_ptr_update_valid_reg <= 1'b1; + end + + good_frame_reg <= s_axis_tlast; + end end end - end - end else if (s_axis_tvalid && full_wr && FRAME_FIFO && !DROP_OVERSIZE_FRAME) begin - // data valid with packet overflow - // update write pointer - send_frame_reg <= 1'b1; - wr_ptr_temp = wr_ptr_cur_reg; - wr_ptr_reg <= wr_ptr_temp; - wr_ptr_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1); + end else if (s_axis_tvalid && full_wr && FRAME_FIFO && !DROP_OVERSIZE_FRAME) begin + // data valid with packet overflow + // update write pointer + send_frame_reg <= 1'b1; + wr_ptr_temp = wr_ptr_reg; + wr_ptr_reg <= wr_ptr_temp; + wr_ptr_commit_reg <= wr_ptr_temp; + wr_ptr_gray_reg <= bin2gray(wr_ptr_temp); - if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin - // no sync in progress; sync update - wr_ptr_update_valid_reg <= 1'b0; - wr_ptr_sync_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1); - wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg; - end else begin - // sync in progress; flag it for later - wr_ptr_update_valid_reg <= 1'b1; + if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin + // no sync in progress; sync update + wr_ptr_update_valid_reg <= 1'b0; + wr_ptr_sync_commit_reg <= wr_ptr_temp; + wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg; + end else begin + // sync in progress; flag it for later + wr_ptr_update_valid_reg <= 1'b1; + end + end + end else begin + // normal FIFO mode + if (s_axis_tready && s_axis_tvalid) begin + if (drop_frame_reg && LAST_ENABLE) begin + // currently dropping frame + if (s_axis_tlast) begin + // end of frame + if (!full && mark_frame_reg && MARK_WHEN_FULL) begin + // terminate marked frame + mark_frame_reg <= 1'b0; + mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis; + wr_ptr_temp = wr_ptr_reg + 1; + wr_ptr_reg <= wr_ptr_temp; + wr_ptr_commit_reg <= wr_ptr_temp; + wr_ptr_gray_reg <= bin2gray(wr_ptr_temp); + end + // end of frame, clear drop flag + drop_frame_reg <= 1'b0; + overflow_reg <= 1'b1; + end + end else if ((full || mark_frame_reg) && MARK_WHEN_FULL) begin + // full or marking frame + // drop frame; mark if this isn't the first cycle + drop_frame_reg <= 1'b1; + mark_frame_reg <= mark_frame_reg || s_frame_reg; + if (s_axis_tlast) begin + drop_frame_reg <= 1'b0; + overflow_reg <= 1'b1; + end + end else begin + // transfer in + mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis; + wr_ptr_temp = wr_ptr_reg + 1; + wr_ptr_reg <= wr_ptr_temp; + wr_ptr_commit_reg <= wr_ptr_temp; + wr_ptr_gray_reg <= bin2gray(wr_ptr_temp); + end + end else if ((!full && !drop_frame_reg && mark_frame_reg) && MARK_WHEN_FULL) begin + // terminate marked frame + mark_frame_reg <= 1'b0; + mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis; + wr_ptr_temp = wr_ptr_reg + 1; + wr_ptr_reg <= wr_ptr_temp; + wr_ptr_commit_reg <= wr_ptr_temp; + wr_ptr_gray_reg <= bin2gray(wr_ptr_temp); end end if (s_rst_sync3_reg) begin wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}}; - wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_commit_reg <= {ADDR_WIDTH+1{1'b0}}; wr_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}}; - wr_ptr_sync_gray_reg <= {ADDR_WIDTH+1{1'b0}}; - wr_ptr_cur_gray_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_sync_commit_reg <= {ADDR_WIDTH+1{1'b0}}; wr_ptr_update_valid_reg <= 1'b0; wr_ptr_update_reg <= 1'b0; @@ -442,10 +540,9 @@ always @(posedge s_clk) begin if (s_rst) begin wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}}; - wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_commit_reg <= {ADDR_WIDTH+1{1'b0}}; wr_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}}; - wr_ptr_sync_gray_reg <= {ADDR_WIDTH+1{1'b0}}; - wr_ptr_cur_gray_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_sync_commit_reg <= {ADDR_WIDTH+1{1'b0}}; wr_ptr_update_valid_reg <= 1'b0; wr_ptr_update_reg <= 1'b0; @@ -453,6 +550,7 @@ always @(posedge s_clk) begin s_frame_reg <= 1'b0; drop_frame_reg <= 1'b0; + mark_frame_reg <= 1'b0; send_frame_reg <= 1'b0; overflow_reg <= 1'b0; bad_frame_reg <= 1'b0; @@ -460,6 +558,13 @@ always @(posedge s_clk) begin end end +// Write-side status +always @(posedge s_clk) begin + rd_ptr_conv_reg <= gray2bin(rd_ptr_gray_sync2_reg); + s_depth_reg <= wr_ptr_reg - rd_ptr_conv_reg; + s_depth_commit_reg <= wr_ptr_commit_reg - rd_ptr_conv_reg; +end + // pointer synchronization always @(posedge s_clk) begin rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg; @@ -476,12 +581,11 @@ always @(posedge s_clk) begin end always @(posedge m_clk) begin - if (!FRAME_FIFO) begin - wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg; - end else if (wr_ptr_update_sync2_reg ^ wr_ptr_update_sync3_reg) begin - wr_ptr_gray_sync1_reg <= wr_ptr_sync_gray_reg; - end + wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg; wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg; + if (FRAME_FIFO && wr_ptr_update_sync2_reg ^ wr_ptr_update_sync3_reg) begin + wr_ptr_commit_sync_reg <= wr_ptr_sync_commit_reg; + end wr_ptr_update_sync1_reg <= wr_ptr_update_reg; wr_ptr_update_sync2_reg <= wr_ptr_update_sync1_reg; wr_ptr_update_sync3_reg <= wr_ptr_update_sync2_reg; @@ -493,6 +597,7 @@ always @(posedge m_clk) begin if (m_rst) begin wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}}; wr_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_commit_sync_reg <= {ADDR_WIDTH+1{1'b0}}; wr_ptr_update_sync1_reg <= 1'b0; wr_ptr_update_sync2_reg <= 1'b0; wr_ptr_update_sync3_reg <= 1'b0; @@ -540,14 +645,14 @@ end integer j; always @(posedge m_clk) begin - if (OUTPUT_FIFO_ENABLE || m_axis_tready) begin + if (m_axis_tready_pipe) begin // output ready; invalidate stage m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b0; m_terminate_frame_reg <= 1'b0; end for (j = RAM_PIPELINE+1-1; j > 0; j = j - 1) begin - if (OUTPUT_FIFO_ENABLE || m_axis_tready || ((~m_axis_tvalid_pipe_reg) >> j)) begin + if (m_axis_tready_pipe || ((~m_axis_tvalid_pipe_reg) >> j)) begin // output ready or bubble in pipeline; transfer down pipeline m_axis_tvalid_pipe_reg[j] <= m_axis_tvalid_pipe_reg[j-1]; m_axis_pipe_reg[j] <= m_axis_pipe_reg[j-1]; @@ -555,7 +660,7 @@ always @(posedge m_clk) begin end end - if (OUTPUT_FIFO_ENABLE || m_axis_tready || ~m_axis_tvalid_pipe_reg) begin + if (m_axis_tready_pipe || ~m_axis_tvalid_pipe_reg) begin // output ready or bubble in pipeline; read new data from FIFO m_axis_tvalid_pipe_reg[0] <= 1'b0; m_axis_pipe_reg[0] <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]]; @@ -570,14 +675,14 @@ always @(posedge m_clk) begin if (m_axis_tvalid_pipe && LAST_ENABLE) begin // track output frame status - if (m_axis_tlast_pipe && (OUTPUT_FIFO_ENABLE || m_axis_tready)) begin + if (m_axis_tlast_pipe && m_axis_tready_pipe) begin m_frame_reg <= 1'b0; end else begin m_frame_reg <= 1'b1; end end - if (m_drop_frame_reg && (OUTPUT_FIFO_ENABLE ? pipe_ready : m_axis_tready || !m_axis_tvalid_pipe) && LAST_ENABLE) begin + if (m_drop_frame_reg && (OUTPUT_FIFO_ENABLE ? pipe_ready : m_axis_tready_pipe || !m_axis_tvalid_pipe) && LAST_ENABLE) begin // terminate frame // (only for frame transfers interrupted by source reset) m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b1; @@ -615,22 +720,30 @@ always @(posedge m_clk) begin end end +// Read-side status +always @(posedge m_clk) begin + wr_ptr_conv_reg <= gray2bin(wr_ptr_gray_sync2_reg); + m_depth_reg <= wr_ptr_conv_reg - rd_ptr_reg; + m_depth_commit_reg <= FRAME_FIFO ? wr_ptr_commit_sync_reg - rd_ptr_reg : wr_ptr_conv_reg - rd_ptr_reg; +end + generate if (!OUTPUT_FIFO_ENABLE) begin assign pipe_ready = 1'b1; - assign m_axis_tvalid = m_axis_tvalid_pipe; + assign m_axis_tready_pipe = m_axis_tready_out; + assign m_axis_tvalid_out = m_axis_tvalid_pipe; - assign m_axis_tdata = m_axis_tdata_pipe; - assign m_axis_tkeep = m_axis_tkeep_pipe; - assign m_axis_tlast = m_axis_tlast_pipe; - assign m_axis_tid = m_axis_tid_pipe; - assign m_axis_tdest = m_axis_tdest_pipe; - assign m_axis_tuser = m_axis_tuser_pipe; + assign m_axis_tdata_out = m_axis_tdata_pipe; + assign m_axis_tkeep_out = m_axis_tkeep_pipe; + assign m_axis_tlast_out = m_axis_tlast_pipe; + assign m_axis_tid_out = m_axis_tid_pipe; + assign m_axis_tdest_out = m_axis_tdest_pipe; + assign m_axis_tuser_out = m_axis_tuser_pipe; -end else begin +end else begin : output_fifo // output datapath logic reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; @@ -663,16 +776,18 @@ end else begin assign pipe_ready = !out_fifo_half_full_reg; - assign m_axis_tdata = m_axis_tdata_reg; - assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}}; - assign m_axis_tvalid = m_axis_tvalid_reg; - assign m_axis_tlast = LAST_ENABLE ? m_axis_tlast_reg : 1'b1; - assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; - assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; - assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; + assign m_axis_tready_pipe = 1'b1; + + assign m_axis_tdata_out = m_axis_tdata_reg; + assign m_axis_tkeep_out = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}}; + assign m_axis_tvalid_out = m_axis_tvalid_reg; + assign m_axis_tlast_out = LAST_ENABLE ? m_axis_tlast_reg : 1'b1; + assign m_axis_tid_out = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; + assign m_axis_tdest_out = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; + assign m_axis_tuser_out = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; always @(posedge m_clk) begin - m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready; + m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready_out; out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1); @@ -686,7 +801,7 @@ end else begin out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1; end - if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready)) begin + if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready_out)) begin m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; m_axis_tvalid_reg <= 1'b1; @@ -706,6 +821,85 @@ end else begin end +if (PAUSE_ENABLE) begin : pause + + // Pause logic + reg pause_reg = 1'b0; + reg pause_frame_reg = 1'b0; + + reg s_pause_req_sync1_reg; + reg s_pause_req_sync2_reg; + reg s_pause_req_sync3_reg; + reg s_pause_ack_sync1_reg; + reg s_pause_ack_sync2_reg; + reg s_pause_ack_sync3_reg; + + always @(posedge s_clk) begin + s_pause_req_sync1_reg <= s_pause_req; + s_pause_ack_sync2_reg <= s_pause_ack_sync1_reg; + s_pause_ack_sync3_reg <= s_pause_ack_sync2_reg; + end + + always @(posedge m_clk) begin + s_pause_req_sync2_reg <= s_pause_req_sync1_reg; + s_pause_req_sync3_reg <= s_pause_req_sync2_reg; + s_pause_ack_sync1_reg <= pause_reg; + end + + assign m_axis_tready_out = m_axis_tready && !pause_reg; + assign m_axis_tvalid = m_axis_tvalid_out && !pause_reg; + + assign m_axis_tdata = m_axis_tdata_out; + assign m_axis_tkeep = m_axis_tkeep_out; + assign m_axis_tlast = m_axis_tlast_out; + assign m_axis_tid = m_axis_tid_out; + assign m_axis_tdest = m_axis_tdest_out; + assign m_axis_tuser = m_axis_tuser_out; + + assign s_pause_ack = s_pause_ack_sync3_reg; + assign m_pause_ack = pause_reg; + + always @(posedge m_clk) begin + if (FRAME_PAUSE) begin + if (m_axis_tvalid && m_axis_tready) begin + if (m_axis_tlast) begin + pause_frame_reg <= 1'b0; + pause_reg <= m_pause_req || s_pause_req_sync3_reg; + end else begin + pause_frame_reg <= 1'b1; + end + end else begin + if (!pause_frame_reg) begin + pause_reg <= m_pause_req || s_pause_req_sync3_reg; + end + end + end else begin + pause_reg <= m_pause_req || s_pause_req_sync3_reg; + end + + if (m_rst) begin + pause_frame_reg <= 1'b0; + pause_reg <= 1'b0; + end + end + +end else begin + + assign m_axis_tready_out = m_axis_tready; + assign m_axis_tvalid = m_axis_tvalid_out; + + assign m_axis_tdata = m_axis_tdata_out; + assign m_axis_tkeep = m_axis_tkeep_out; + assign m_axis_tlast = m_axis_tlast_out; + assign m_axis_tid = m_axis_tid_out; + assign m_axis_tdest = m_axis_tdest_out; + assign m_axis_tuser = m_axis_tuser_out; + + assign s_pause_ack = 1'b0; + assign m_pause_ack = 1'b0; + +end + endgenerate endmodule diff --git a/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v b/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v index c8d1692be..77969960a 100644 --- a/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +++ b/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v @@ -85,7 +85,15 @@ module axis_async_fifo_adapter # // Drop incoming frames when full // When set, s_axis_tready is always asserted // Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set - parameter DROP_WHEN_FULL = 0 + parameter DROP_WHEN_FULL = 0, + // Mark incoming frames as bad frames when full + // When set, s_axis_tready is always asserted + // Requires FRAME_FIFO to be clear + parameter MARK_WHEN_FULL = 0, + // Enable pause request input + parameter PAUSE_ENABLE = 0, + // Pause between frames + parameter FRAME_PAUSE = FRAME_FIFO ) ( /* @@ -116,44 +124,56 @@ module axis_async_fifo_adapter # output wire [DEST_WIDTH-1:0] m_axis_tdest, output wire [USER_WIDTH-1:0] m_axis_tuser, + /* + * Pause + */ + input wire s_pause_req, + output wire s_pause_ack, + input wire m_pause_req, + output wire m_pause_ack, + /* * Status */ + output wire [$clog2(DEPTH):0] s_status_depth, + output wire [$clog2(DEPTH):0] s_status_depth_commit, output wire s_status_overflow, output wire s_status_bad_frame, output wire s_status_good_frame, + output wire [$clog2(DEPTH):0] m_status_depth, + output wire [$clog2(DEPTH):0] m_status_depth_commit, output wire m_status_overflow, output wire m_status_bad_frame, output wire m_status_good_frame ); // force keep width to 1 when disabled -parameter S_KEEP_WIDTH_INT = S_KEEP_ENABLE ? S_KEEP_WIDTH : 1; -parameter M_KEEP_WIDTH_INT = M_KEEP_ENABLE ? M_KEEP_WIDTH : 1; +localparam S_BYTE_LANES = S_KEEP_ENABLE ? S_KEEP_WIDTH : 1; +localparam M_BYTE_LANES = M_KEEP_ENABLE ? M_KEEP_WIDTH : 1; -// bus word sizes (must be identical) -parameter S_DATA_WORD_SIZE = S_DATA_WIDTH / S_KEEP_WIDTH_INT; -parameter M_DATA_WORD_SIZE = M_DATA_WIDTH / M_KEEP_WIDTH_INT; +// bus byte sizes (must be identical) +localparam S_BYTE_SIZE = S_DATA_WIDTH / S_BYTE_LANES; +localparam M_BYTE_SIZE = M_DATA_WIDTH / M_BYTE_LANES; // output bus is wider -parameter EXPAND_BUS = M_KEEP_WIDTH_INT > S_KEEP_WIDTH_INT; +localparam EXPAND_BUS = M_BYTE_LANES > S_BYTE_LANES; // total data and keep widths -parameter DATA_WIDTH = EXPAND_BUS ? M_DATA_WIDTH : S_DATA_WIDTH; -parameter KEEP_WIDTH = EXPAND_BUS ? M_KEEP_WIDTH_INT : S_KEEP_WIDTH_INT; +localparam DATA_WIDTH = EXPAND_BUS ? M_DATA_WIDTH : S_DATA_WIDTH; +localparam KEEP_WIDTH = EXPAND_BUS ? M_BYTE_LANES : S_BYTE_LANES; // bus width assertions initial begin - if (S_DATA_WORD_SIZE * S_KEEP_WIDTH_INT != S_DATA_WIDTH) begin - $error("Error: input data width not evenly divisble (instance %m)"); + if (S_BYTE_SIZE * S_BYTE_LANES != S_DATA_WIDTH) begin + $error("Error: input data width not evenly divisible (instance %m)"); $finish; end - if (M_DATA_WORD_SIZE * M_KEEP_WIDTH_INT != M_DATA_WIDTH) begin - $error("Error: output data width not evenly divisble (instance %m)"); + if (M_BYTE_SIZE * M_BYTE_LANES != M_DATA_WIDTH) begin + $error("Error: output data width not evenly divisible (instance %m)"); $finish; end - if (S_DATA_WORD_SIZE != M_DATA_WORD_SIZE) begin - $error("Error: word size mismatch (instance %m)"); + if (S_BYTE_SIZE != M_BYTE_SIZE) begin + $error("Error: byte size mismatch (instance %m)"); $finish; end end @@ -178,30 +198,7 @@ wire [USER_WIDTH-1:0] post_fifo_axis_tuser; generate -if (M_KEEP_WIDTH == S_KEEP_WIDTH) begin - - // same width, no adapter needed - - assign pre_fifo_axis_tdata = s_axis_tdata; - assign pre_fifo_axis_tkeep = s_axis_tkeep; - assign pre_fifo_axis_tvalid = s_axis_tvalid; - assign s_axis_tready = pre_fifo_axis_tready; - assign pre_fifo_axis_tlast = s_axis_tlast; - assign pre_fifo_axis_tid = s_axis_tid; - assign pre_fifo_axis_tdest = s_axis_tdest; - assign pre_fifo_axis_tuser = s_axis_tuser; - - assign m_axis_tdata = post_fifo_axis_tdata; - assign m_axis_tkeep = post_fifo_axis_tkeep; - assign m_axis_tvalid = post_fifo_axis_tvalid; - assign post_fifo_axis_tready = m_axis_tready; - assign m_axis_tlast = post_fifo_axis_tlast; - assign m_axis_tid = post_fifo_axis_tid; - assign m_axis_tdest = post_fifo_axis_tdest; - assign m_axis_tuser = post_fifo_axis_tuser; - - -end else if (EXPAND_BUS) begin +if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize_pre // output wider, adapt width before FIFO @@ -242,19 +239,8 @@ end else if (EXPAND_BUS) begin .m_axis_tuser(pre_fifo_axis_tuser) ); - assign m_axis_tdata = post_fifo_axis_tdata; - assign m_axis_tkeep = post_fifo_axis_tkeep; - assign m_axis_tvalid = post_fifo_axis_tvalid; - assign post_fifo_axis_tready = m_axis_tready; - assign m_axis_tlast = post_fifo_axis_tlast; - assign m_axis_tid = post_fifo_axis_tid; - assign m_axis_tdest = post_fifo_axis_tdest; - assign m_axis_tuser = post_fifo_axis_tuser; - -end else begin +end else begin : bypass_pre - // input wider, adapt width after FIFO - assign pre_fifo_axis_tdata = s_axis_tdata; assign pre_fifo_axis_tkeep = s_axis_tkeep; assign pre_fifo_axis_tvalid = s_axis_tvalid; @@ -264,6 +250,77 @@ end else begin assign pre_fifo_axis_tdest = s_axis_tdest; assign pre_fifo_axis_tuser = s_axis_tuser; +end + +axis_async_fifo #( + .DEPTH(DEPTH), + .DATA_WIDTH(DATA_WIDTH), + .KEEP_ENABLE(EXPAND_BUS ? M_KEEP_ENABLE : S_KEEP_ENABLE), + .KEEP_WIDTH(KEEP_WIDTH), + .LAST_ENABLE(1), + .ID_ENABLE(ID_ENABLE), + .ID_WIDTH(ID_WIDTH), + .DEST_ENABLE(DEST_ENABLE), + .DEST_WIDTH(DEST_WIDTH), + .USER_ENABLE(USER_ENABLE), + .USER_WIDTH(USER_WIDTH), + .RAM_PIPELINE(RAM_PIPELINE), + .OUTPUT_FIFO_ENABLE(OUTPUT_FIFO_ENABLE), + .FRAME_FIFO(FRAME_FIFO), + .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE), + .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK), + .DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME), + .DROP_BAD_FRAME(DROP_BAD_FRAME), + .DROP_WHEN_FULL(DROP_WHEN_FULL), + .MARK_WHEN_FULL(MARK_WHEN_FULL), + .PAUSE_ENABLE(PAUSE_ENABLE), + .FRAME_PAUSE(FRAME_PAUSE) +) +fifo_inst ( + // AXI input + .s_clk(s_clk), + .s_rst(s_rst), + .s_axis_tdata(pre_fifo_axis_tdata), + .s_axis_tkeep(pre_fifo_axis_tkeep), + .s_axis_tvalid(pre_fifo_axis_tvalid), + .s_axis_tready(pre_fifo_axis_tready), + .s_axis_tlast(pre_fifo_axis_tlast), + .s_axis_tid(pre_fifo_axis_tid), + .s_axis_tdest(pre_fifo_axis_tdest), + .s_axis_tuser(pre_fifo_axis_tuser), + // AXI output + .m_clk(m_clk), + .m_rst(m_rst), + .m_axis_tdata(post_fifo_axis_tdata), + .m_axis_tkeep(post_fifo_axis_tkeep), + .m_axis_tvalid(post_fifo_axis_tvalid), + .m_axis_tready(post_fifo_axis_tready), + .m_axis_tlast(post_fifo_axis_tlast), + .m_axis_tid(post_fifo_axis_tid), + .m_axis_tdest(post_fifo_axis_tdest), + .m_axis_tuser(post_fifo_axis_tuser), + // Pause + .s_pause_req(s_pause_req), + .s_pause_ack(s_pause_ack), + .m_pause_req(m_pause_req), + .m_pause_ack(m_pause_ack), + // Status + .s_status_depth(s_status_depth), + .s_status_depth_commit(s_status_depth_commit), + .s_status_overflow(s_status_overflow), + .s_status_bad_frame(s_status_bad_frame), + .s_status_good_frame(s_status_good_frame), + .m_status_depth(m_status_depth), + .m_status_depth_commit(m_status_depth_commit), + .m_status_overflow(m_status_overflow), + .m_status_bad_frame(m_status_bad_frame), + .m_status_good_frame(m_status_good_frame) +); + +if (M_BYTE_LANES < S_BYTE_LANES) begin : downsize_post + + // input wider, adapt width after FIFO + axis_adapter #( .S_DATA_WIDTH(S_DATA_WIDTH), .S_KEEP_ENABLE(S_KEEP_ENABLE), @@ -301,63 +358,21 @@ end else begin .m_axis_tuser(m_axis_tuser) ); +end else begin : bypass_post + + assign m_axis_tdata = post_fifo_axis_tdata; + assign m_axis_tkeep = post_fifo_axis_tkeep; + assign m_axis_tvalid = post_fifo_axis_tvalid; + assign post_fifo_axis_tready = m_axis_tready; + assign m_axis_tlast = post_fifo_axis_tlast; + assign m_axis_tid = post_fifo_axis_tid; + assign m_axis_tdest = post_fifo_axis_tdest; + assign m_axis_tuser = post_fifo_axis_tuser; + end endgenerate -axis_async_fifo #( - .DEPTH(DEPTH), - .DATA_WIDTH(DATA_WIDTH), - .KEEP_ENABLE(EXPAND_BUS ? M_KEEP_ENABLE : S_KEEP_ENABLE), - .KEEP_WIDTH(KEEP_WIDTH), - .LAST_ENABLE(1), - .ID_ENABLE(ID_ENABLE), - .ID_WIDTH(ID_WIDTH), - .DEST_ENABLE(DEST_ENABLE), - .DEST_WIDTH(DEST_WIDTH), - .USER_ENABLE(USER_ENABLE), - .USER_WIDTH(USER_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - .OUTPUT_FIFO_ENABLE(OUTPUT_FIFO_ENABLE), - .FRAME_FIFO(FRAME_FIFO), - .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE), - .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK), - .DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME), - .DROP_BAD_FRAME(DROP_BAD_FRAME), - .DROP_WHEN_FULL(DROP_WHEN_FULL) -) -fifo_inst ( - // AXI input - .s_clk(s_clk), - .s_rst(s_rst), - .s_axis_tdata(pre_fifo_axis_tdata), - .s_axis_tkeep(pre_fifo_axis_tkeep), - .s_axis_tvalid(pre_fifo_axis_tvalid), - .s_axis_tready(pre_fifo_axis_tready), - .s_axis_tlast(pre_fifo_axis_tlast), - .s_axis_tid(pre_fifo_axis_tid), - .s_axis_tdest(pre_fifo_axis_tdest), - .s_axis_tuser(pre_fifo_axis_tuser), - // AXI output - .m_clk(m_clk), - .m_rst(m_rst), - .m_axis_tdata(post_fifo_axis_tdata), - .m_axis_tkeep(post_fifo_axis_tkeep), - .m_axis_tvalid(post_fifo_axis_tvalid), - .m_axis_tready(post_fifo_axis_tready), - .m_axis_tlast(post_fifo_axis_tlast), - .m_axis_tid(post_fifo_axis_tid), - .m_axis_tdest(post_fifo_axis_tdest), - .m_axis_tuser(post_fifo_axis_tuser), - // Status - .s_status_overflow(s_status_overflow), - .s_status_bad_frame(s_status_bad_frame), - .s_status_good_frame(s_status_good_frame), - .m_status_overflow(m_status_overflow), - .m_status_bad_frame(m_status_bad_frame), - .m_status_good_frame(m_status_good_frame) -); - endmodule `resetall diff --git a/fpga/lib/eth/lib/axis/rtl/axis_fifo.v b/fpga/lib/eth/lib/axis/rtl/axis_fifo.v index b6bd49a6c..e9c9258eb 100644 --- a/fpga/lib/eth/lib/axis/rtl/axis_fifo.v +++ b/fpga/lib/eth/lib/axis/rtl/axis_fifo.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2013-2021 Alex Forencich +Copyright (c) 2013-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -80,7 +80,15 @@ module axis_fifo # // Drop incoming frames when full // When set, s_axis_tready is always asserted // Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set - parameter DROP_WHEN_FULL = 0 + parameter DROP_WHEN_FULL = 0, + // Mark incoming frames as bad frames when full + // When set, s_axis_tready is always asserted + // Requires FRAME_FIFO to be clear + parameter MARK_WHEN_FULL = 0, + // Enable pause request input + parameter PAUSE_ENABLE = 0, + // Pause between frames + parameter FRAME_PAUSE = FRAME_FIFO ) ( input wire clk, @@ -110,9 +118,17 @@ module axis_fifo # output wire [DEST_WIDTH-1:0] m_axis_tdest, output wire [USER_WIDTH-1:0] m_axis_tuser, + /* + * Pause + */ + input wire pause_req, + output wire pause_ack, + /* * Status */ + output wire [$clog2(DEPTH):0] status_depth, + output wire [$clog2(DEPTH):0] status_depth_commit, output wire status_overflow, output wire status_bad_frame, output wire status_good_frame @@ -144,10 +160,20 @@ initial begin $finish; end - if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin + if ((DROP_BAD_FRAME || MARK_WHEN_FULL) && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin $error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)"); $finish; end + + if (MARK_WHEN_FULL && FRAME_FIFO) begin + $error("Error: MARK_WHEN_FULL is not compatible with FRAME_FIFO (instance %m)"); + $finish; + end + + if (MARK_WHEN_FULL && !LAST_ENABLE) begin + $error("Error: MARK_WHEN_FULL set requires LAST_ENABLE set (instance %m)"); + $finish; + end end localparam KEEP_OFFSET = DATA_WIDTH; @@ -158,7 +184,7 @@ localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0); localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0); reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}; -reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}; +reg [ADDR_WIDTH:0] wr_ptr_commit_reg = {ADDR_WIDTH+1{1'b0}}; reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}; (* ramstyle = "no_rw_check" *) @@ -171,33 +197,38 @@ reg [RAM_PIPELINE+1-1:0] m_axis_tvalid_pipe_reg = 0; // full when first MSB different but rest same wire full = wr_ptr_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}}); -wire full_cur = wr_ptr_cur_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}}); // empty when pointers match exactly -wire empty = wr_ptr_reg == rd_ptr_reg; +wire empty = wr_ptr_commit_reg == rd_ptr_reg; // overflow within packet -wire full_wr = wr_ptr_reg == (wr_ptr_cur_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}}); +wire full_wr = wr_ptr_reg == (wr_ptr_commit_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}}); + +reg s_frame_reg = 1'b0; reg drop_frame_reg = 1'b0; +reg mark_frame_reg = 1'b0; reg send_frame_reg = 1'b0; +reg [ADDR_WIDTH:0] depth_reg = 0; +reg [ADDR_WIDTH:0] depth_commit_reg = 0; reg overflow_reg = 1'b0; reg bad_frame_reg = 1'b0; reg good_frame_reg = 1'b0; -assign s_axis_tready = FRAME_FIFO ? (!full_cur || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : !full; +assign s_axis_tready = FRAME_FIFO ? (!full || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : (!full || MARK_WHEN_FULL); wire [WIDTH-1:0] s_axis; generate assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata; if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET +: KEEP_WIDTH] = s_axis_tkeep; - if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast; + if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast | mark_frame_reg; if (ID_ENABLE) assign s_axis[ID_OFFSET +: ID_WIDTH] = s_axis_tid; if (DEST_ENABLE) assign s_axis[DEST_OFFSET +: DEST_WIDTH] = s_axis_tdest; - if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = s_axis_tuser; + if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = mark_frame_reg ? USER_BAD_FRAME_VALUE : s_axis_tuser; endgenerate wire [WIDTH-1:0] m_axis = m_axis_pipe_reg[RAM_PIPELINE+1-1]; +wire m_axis_tready_pipe; wire m_axis_tvalid_pipe = m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1]; wire [DATA_WIDTH-1:0] m_axis_tdata_pipe = m_axis[DATA_WIDTH-1:0]; @@ -207,8 +238,20 @@ wire [ID_WIDTH-1:0] m_axis_tid_pipe = ID_ENABLE ? m_axis[ID_OFFSET +: ID wire [DEST_WIDTH-1:0] m_axis_tdest_pipe = DEST_ENABLE ? m_axis[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}}; wire [USER_WIDTH-1:0] m_axis_tuser_pipe = USER_ENABLE ? m_axis[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}}; +wire m_axis_tready_out; +wire m_axis_tvalid_out; + +wire [DATA_WIDTH-1:0] m_axis_tdata_out; +wire [KEEP_WIDTH-1:0] m_axis_tkeep_out; +wire m_axis_tlast_out; +wire [ID_WIDTH-1:0] m_axis_tid_out; +wire [DEST_WIDTH-1:0] m_axis_tdest_out; +wire [USER_WIDTH-1:0] m_axis_tuser_out; + wire pipe_ready; +assign status_depth = (KEEP_ENABLE && KEEP_WIDTH > 1) ? {depth_reg, {$clog2(KEEP_WIDTH){1'b0}}} : depth_reg; +assign status_depth_commit = (KEEP_ENABLE && KEEP_WIDTH > 1) ? {depth_commit_reg, {$clog2(KEEP_WIDTH){1'b0}}} : depth_commit_reg; assign status_overflow = overflow_reg; assign status_bad_frame = bad_frame_reg; assign status_good_frame = good_frame_reg; @@ -219,52 +262,99 @@ always @(posedge clk) begin bad_frame_reg <= 1'b0; good_frame_reg <= 1'b0; - if (s_axis_tready && s_axis_tvalid) begin - // transfer in - if (!FRAME_FIFO) begin - // normal FIFO mode - mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis; - wr_ptr_reg <= wr_ptr_reg + 1; - end else if ((full_cur && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin - // full, packet overflow, or currently dropping frame - // drop frame - drop_frame_reg <= 1'b1; - if (s_axis_tlast) begin - // end of frame, reset write pointer - wr_ptr_cur_reg <= wr_ptr_reg; - drop_frame_reg <= 1'b0; - overflow_reg <= 1'b1; - end - end else begin - // store it - mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= s_axis; - wr_ptr_cur_reg <= wr_ptr_cur_reg + 1; - if (s_axis_tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin - // end of frame or send frame - send_frame_reg <= !s_axis_tlast; - if (s_axis_tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin - // bad packet, reset write pointer - wr_ptr_cur_reg <= wr_ptr_reg; - bad_frame_reg <= 1'b1; - end else begin - // good packet or packet overflow, update write pointer - wr_ptr_reg <= wr_ptr_cur_reg + 1; - good_frame_reg <= s_axis_tlast; + if (s_axis_tready && s_axis_tvalid && LAST_ENABLE) begin + // track input frame status + s_frame_reg <= !s_axis_tlast; + end + + if (FRAME_FIFO) begin + // frame FIFO mode + if (s_axis_tready && s_axis_tvalid) begin + // transfer in + if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin + // full, packet overflow, or currently dropping frame + // drop frame + drop_frame_reg <= 1'b1; + if (s_axis_tlast) begin + // end of frame, reset write pointer + wr_ptr_reg <= wr_ptr_commit_reg; + drop_frame_reg <= 1'b0; + overflow_reg <= 1'b1; + end + end else begin + // store it + mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis; + wr_ptr_reg <= wr_ptr_reg + 1; + if (s_axis_tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin + // end of frame or send frame + send_frame_reg <= !s_axis_tlast; + if (s_axis_tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin + // bad packet, reset write pointer + wr_ptr_reg <= wr_ptr_commit_reg; + bad_frame_reg <= 1'b1; + end else begin + // good packet or packet overflow, update write pointer + wr_ptr_commit_reg <= wr_ptr_reg + 1; + good_frame_reg <= s_axis_tlast; + end end end + end else if (s_axis_tvalid && full_wr && !DROP_OVERSIZE_FRAME) begin + // data valid with packet overflow + // update write pointer + send_frame_reg <= 1'b1; + wr_ptr_commit_reg <= wr_ptr_reg; + end + end else begin + // normal FIFO mode + if (s_axis_tready && s_axis_tvalid) begin + if (drop_frame_reg && MARK_WHEN_FULL) begin + // currently dropping frame + if (s_axis_tlast) begin + // end of frame + if (!full && mark_frame_reg) begin + // terminate marked frame + mark_frame_reg <= 1'b0; + mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis; + wr_ptr_reg <= wr_ptr_reg + 1; + wr_ptr_commit_reg <= wr_ptr_reg + 1; + end + // end of frame, clear drop flag + drop_frame_reg <= 1'b0; + overflow_reg <= 1'b1; + end + end else if ((full || mark_frame_reg) && MARK_WHEN_FULL) begin + // full or marking frame + // drop frame; mark if this isn't the first cycle + drop_frame_reg <= 1'b1; + mark_frame_reg <= mark_frame_reg || s_frame_reg; + if (s_axis_tlast) begin + drop_frame_reg <= 1'b0; + overflow_reg <= 1'b1; + end + end else begin + // transfer in + mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis; + wr_ptr_reg <= wr_ptr_reg + 1; + wr_ptr_commit_reg <= wr_ptr_reg + 1; + end + end else if ((!full && !drop_frame_reg && mark_frame_reg) && MARK_WHEN_FULL) begin + // terminate marked frame + mark_frame_reg <= 1'b0; + mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis; + wr_ptr_reg <= wr_ptr_reg + 1; + wr_ptr_commit_reg <= wr_ptr_reg + 1; end - end else if (s_axis_tvalid && full_wr && FRAME_FIFO && !DROP_OVERSIZE_FRAME) begin - // data valid with packet overflow - // update write pointer - send_frame_reg <= 1'b1; - wr_ptr_reg <= wr_ptr_cur_reg; end if (rst) begin wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}}; - wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_commit_reg <= {ADDR_WIDTH+1{1'b0}}; + + s_frame_reg <= 1'b0; drop_frame_reg <= 1'b0; + mark_frame_reg <= 1'b0; send_frame_reg <= 1'b0; overflow_reg <= 1'b0; bad_frame_reg <= 1'b0; @@ -272,17 +362,23 @@ always @(posedge clk) begin end end +// Status +always @(posedge clk) begin + depth_reg <= wr_ptr_reg - rd_ptr_reg; + depth_commit_reg <= wr_ptr_commit_reg - rd_ptr_reg; +end + // Read logic integer j; always @(posedge clk) begin - if (OUTPUT_FIFO_ENABLE || m_axis_tready) begin + if (m_axis_tready_pipe) begin // output ready; invalidate stage m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b0; end for (j = RAM_PIPELINE+1-1; j > 0; j = j - 1) begin - if (OUTPUT_FIFO_ENABLE || m_axis_tready || ((~m_axis_tvalid_pipe_reg) >> j)) begin + if (m_axis_tready_pipe || ((~m_axis_tvalid_pipe_reg) >> j)) begin // output ready or bubble in pipeline; transfer down pipeline m_axis_tvalid_pipe_reg[j] <= m_axis_tvalid_pipe_reg[j-1]; m_axis_pipe_reg[j] <= m_axis_pipe_reg[j-1]; @@ -290,7 +386,7 @@ always @(posedge clk) begin end end - if (OUTPUT_FIFO_ENABLE || m_axis_tready || ~m_axis_tvalid_pipe_reg) begin + if (m_axis_tready_pipe || ~m_axis_tvalid_pipe_reg) begin // output ready or bubble in pipeline; read new data from FIFO m_axis_tvalid_pipe_reg[0] <= 1'b0; m_axis_pipe_reg[0] <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]]; @@ -313,16 +409,17 @@ if (!OUTPUT_FIFO_ENABLE) begin assign pipe_ready = 1'b1; - assign m_axis_tvalid = m_axis_tvalid_pipe; + assign m_axis_tready_pipe = m_axis_tready_out; + assign m_axis_tvalid_out = m_axis_tvalid_pipe; - assign m_axis_tdata = m_axis_tdata_pipe; - assign m_axis_tkeep = m_axis_tkeep_pipe; - assign m_axis_tlast = m_axis_tlast_pipe; - assign m_axis_tid = m_axis_tid_pipe; - assign m_axis_tdest = m_axis_tdest_pipe; - assign m_axis_tuser = m_axis_tuser_pipe; + assign m_axis_tdata_out = m_axis_tdata_pipe; + assign m_axis_tkeep_out = m_axis_tkeep_pipe; + assign m_axis_tlast_out = m_axis_tlast_pipe; + assign m_axis_tid_out = m_axis_tid_pipe; + assign m_axis_tdest_out = m_axis_tdest_pipe; + assign m_axis_tuser_out = m_axis_tuser_pipe; -end else begin +end else begin : output_fifo // output datapath logic reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; @@ -355,16 +452,18 @@ end else begin assign pipe_ready = !out_fifo_half_full_reg; - assign m_axis_tdata = m_axis_tdata_reg; - assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}}; - assign m_axis_tvalid = m_axis_tvalid_reg; - assign m_axis_tlast = LAST_ENABLE ? m_axis_tlast_reg : 1'b1; - assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; - assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; - assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; + assign m_axis_tready_pipe = 1'b1; + + assign m_axis_tdata_out = m_axis_tdata_reg; + assign m_axis_tkeep_out = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}}; + assign m_axis_tvalid_out = m_axis_tvalid_reg; + assign m_axis_tlast_out = LAST_ENABLE ? m_axis_tlast_reg : 1'b1; + assign m_axis_tid_out = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; + assign m_axis_tdest_out = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; + assign m_axis_tuser_out = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; always @(posedge clk) begin - m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready; + m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready_out; out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1); @@ -378,7 +477,7 @@ end else begin out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1; end - if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready)) begin + if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready_out)) begin m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; m_axis_tvalid_reg <= 1'b1; @@ -398,6 +497,64 @@ end else begin end +if (PAUSE_ENABLE) begin : pause + + // Pause logic + reg pause_reg = 1'b0; + reg pause_frame_reg = 1'b0; + + assign m_axis_tready_out = m_axis_tready && !pause_reg; + assign m_axis_tvalid = m_axis_tvalid_out && !pause_reg; + + assign m_axis_tdata = m_axis_tdata_out; + assign m_axis_tkeep = m_axis_tkeep_out; + assign m_axis_tlast = m_axis_tlast_out; + assign m_axis_tid = m_axis_tid_out; + assign m_axis_tdest = m_axis_tdest_out; + assign m_axis_tuser = m_axis_tuser_out; + + assign pause_ack = pause_reg; + + always @(posedge clk) begin + if (FRAME_PAUSE) begin + if (m_axis_tvalid && m_axis_tready) begin + if (m_axis_tlast) begin + pause_frame_reg <= 1'b0; + pause_reg <= pause_req; + end else begin + pause_frame_reg <= 1'b1; + end + end else begin + if (!pause_frame_reg) begin + pause_reg <= pause_req; + end + end + end else begin + pause_reg <= pause_req; + end + + if (rst) begin + pause_frame_reg <= 1'b0; + pause_reg <= 1'b0; + end + end + +end else begin + + assign m_axis_tready_out = m_axis_tready; + assign m_axis_tvalid = m_axis_tvalid_out; + + assign m_axis_tdata = m_axis_tdata_out; + assign m_axis_tkeep = m_axis_tkeep_out; + assign m_axis_tlast = m_axis_tlast_out; + assign m_axis_tid = m_axis_tid_out; + assign m_axis_tdest = m_axis_tdest_out; + assign m_axis_tuser = m_axis_tuser_out; + + assign pause_ack = 1'b0; + +end + endgenerate endmodule diff --git a/fpga/lib/eth/lib/axis/rtl/axis_fifo_adapter.v b/fpga/lib/eth/lib/axis/rtl/axis_fifo_adapter.v index 88d4d9547..44ecc5c66 100644 --- a/fpga/lib/eth/lib/axis/rtl/axis_fifo_adapter.v +++ b/fpga/lib/eth/lib/axis/rtl/axis_fifo_adapter.v @@ -85,7 +85,15 @@ module axis_fifo_adapter # // Drop incoming frames when full // When set, s_axis_tready is always asserted // Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set - parameter DROP_WHEN_FULL = 0 + parameter DROP_WHEN_FULL = 0, + // Mark incoming frames as bad frames when full + // When set, s_axis_tready is always asserted + // Requires FRAME_FIFO to be clear + parameter MARK_WHEN_FULL = 0, + // Enable pause request input + parameter PAUSE_ENABLE = 0, + // Pause between frames + parameter FRAME_PAUSE = FRAME_FIFO ) ( input wire clk, @@ -115,41 +123,49 @@ module axis_fifo_adapter # output wire [DEST_WIDTH-1:0] m_axis_tdest, output wire [USER_WIDTH-1:0] m_axis_tuser, + /* + * Pause + */ + input wire pause_req, + output wire pause_ack, + /* * Status */ + output wire [$clog2(DEPTH):0] status_depth, + output wire [$clog2(DEPTH):0] status_depth_commit, output wire status_overflow, output wire status_bad_frame, output wire status_good_frame ); // force keep width to 1 when disabled -parameter S_KEEP_WIDTH_INT = S_KEEP_ENABLE ? S_KEEP_WIDTH : 1; -parameter M_KEEP_WIDTH_INT = M_KEEP_ENABLE ? M_KEEP_WIDTH : 1; +localparam S_BYTE_LANES = S_KEEP_ENABLE ? S_KEEP_WIDTH : 1; +localparam M_BYTE_LANES = M_KEEP_ENABLE ? M_KEEP_WIDTH : 1; -// bus word sizes (must be identical) -parameter S_DATA_WORD_SIZE = S_DATA_WIDTH / S_KEEP_WIDTH_INT; -parameter M_DATA_WORD_SIZE = M_DATA_WIDTH / M_KEEP_WIDTH_INT; +// bus byte sizes (must be identical) +localparam S_BYTE_SIZE = S_DATA_WIDTH / S_BYTE_LANES; +localparam M_BYTE_SIZE = M_DATA_WIDTH / M_BYTE_LANES; // output bus is wider -parameter EXPAND_BUS = M_KEEP_WIDTH_INT > S_KEEP_WIDTH_INT; +localparam EXPAND_BUS = M_BYTE_LANES > S_BYTE_LANES; // total data and keep widths -parameter DATA_WIDTH = EXPAND_BUS ? M_DATA_WIDTH : S_DATA_WIDTH; -parameter KEEP_WIDTH = EXPAND_BUS ? M_KEEP_WIDTH_INT : S_KEEP_WIDTH_INT; +localparam DATA_WIDTH = EXPAND_BUS ? M_DATA_WIDTH : S_DATA_WIDTH; +localparam KEEP_WIDTH = EXPAND_BUS ? M_BYTE_LANES : S_BYTE_LANES; // bus width assertions initial begin - if (S_DATA_WORD_SIZE * S_KEEP_WIDTH_INT != S_DATA_WIDTH) begin - $error("Error: input data width not evenly divisble (instance %m)"); + if (S_BYTE_SIZE * S_BYTE_LANES != S_DATA_WIDTH) begin + $error("Error: input data width not evenly divisible (instance %m)"); $finish; end - if (M_DATA_WORD_SIZE * M_KEEP_WIDTH_INT != M_DATA_WIDTH) begin - $error("Error: output data width not evenly divisble (instance %m)"); + if (M_BYTE_SIZE * M_BYTE_LANES != M_DATA_WIDTH) begin + $error("Error: output data width not evenly divisible (instance %m)"); $finish; end - if (S_DATA_WORD_SIZE != M_DATA_WORD_SIZE) begin - $error("Error: word size mismatch (instance %m)"); + if (S_BYTE_SIZE != M_BYTE_SIZE) begin + $error("Error: byte size mismatch (instance %m)"); $finish; end end @@ -174,29 +190,7 @@ wire [USER_WIDTH-1:0] post_fifo_axis_tuser; generate -if (M_KEEP_WIDTH_INT == S_KEEP_WIDTH_INT) begin - - // same width, no adapter needed - - assign pre_fifo_axis_tdata = s_axis_tdata; - assign pre_fifo_axis_tkeep = s_axis_tkeep; - assign pre_fifo_axis_tvalid = s_axis_tvalid; - assign s_axis_tready = pre_fifo_axis_tready; - assign pre_fifo_axis_tlast = s_axis_tlast; - assign pre_fifo_axis_tid = s_axis_tid; - assign pre_fifo_axis_tdest = s_axis_tdest; - assign pre_fifo_axis_tuser = s_axis_tuser; - - assign m_axis_tdata = post_fifo_axis_tdata; - assign m_axis_tkeep = post_fifo_axis_tkeep; - assign m_axis_tvalid = post_fifo_axis_tvalid; - assign post_fifo_axis_tready = m_axis_tready; - assign m_axis_tlast = post_fifo_axis_tlast; - assign m_axis_tid = post_fifo_axis_tid; - assign m_axis_tdest = post_fifo_axis_tdest; - assign m_axis_tuser = post_fifo_axis_tuser; - -end else if (EXPAND_BUS) begin +if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize_pre // output wider, adapt width before FIFO @@ -237,19 +231,8 @@ end else if (EXPAND_BUS) begin .m_axis_tuser(pre_fifo_axis_tuser) ); - assign m_axis_tdata = post_fifo_axis_tdata; - assign m_axis_tkeep = post_fifo_axis_tkeep; - assign m_axis_tvalid = post_fifo_axis_tvalid; - assign post_fifo_axis_tready = m_axis_tready; - assign m_axis_tlast = post_fifo_axis_tlast; - assign m_axis_tid = post_fifo_axis_tid; - assign m_axis_tdest = post_fifo_axis_tdest; - assign m_axis_tuser = post_fifo_axis_tuser; - -end else begin +end else begin : bypass_pre - // input wider, adapt width after FIFO - assign pre_fifo_axis_tdata = s_axis_tdata; assign pre_fifo_axis_tkeep = s_axis_tkeep; assign pre_fifo_axis_tvalid = s_axis_tvalid; @@ -259,6 +242,68 @@ end else begin assign pre_fifo_axis_tdest = s_axis_tdest; assign pre_fifo_axis_tuser = s_axis_tuser; +end + +axis_fifo #( + .DEPTH(DEPTH), + .DATA_WIDTH(DATA_WIDTH), + .KEEP_ENABLE(EXPAND_BUS ? M_KEEP_ENABLE : S_KEEP_ENABLE), + .KEEP_WIDTH(KEEP_WIDTH), + .LAST_ENABLE(1), + .ID_ENABLE(ID_ENABLE), + .ID_WIDTH(ID_WIDTH), + .DEST_ENABLE(DEST_ENABLE), + .DEST_WIDTH(DEST_WIDTH), + .USER_ENABLE(USER_ENABLE), + .USER_WIDTH(USER_WIDTH), + .RAM_PIPELINE(RAM_PIPELINE), + .OUTPUT_FIFO_ENABLE(OUTPUT_FIFO_ENABLE), + .FRAME_FIFO(FRAME_FIFO), + .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE), + .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK), + .DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME), + .DROP_BAD_FRAME(DROP_BAD_FRAME), + .DROP_WHEN_FULL(DROP_WHEN_FULL), + .MARK_WHEN_FULL(MARK_WHEN_FULL), + .PAUSE_ENABLE(PAUSE_ENABLE), + .FRAME_PAUSE(FRAME_PAUSE) +) +fifo_inst ( + .clk(clk), + .rst(rst), + // AXI input + .s_axis_tdata(pre_fifo_axis_tdata), + .s_axis_tkeep(pre_fifo_axis_tkeep), + .s_axis_tvalid(pre_fifo_axis_tvalid), + .s_axis_tready(pre_fifo_axis_tready), + .s_axis_tlast(pre_fifo_axis_tlast), + .s_axis_tid(pre_fifo_axis_tid), + .s_axis_tdest(pre_fifo_axis_tdest), + .s_axis_tuser(pre_fifo_axis_tuser), + // AXI output + .m_axis_tdata(post_fifo_axis_tdata), + .m_axis_tkeep(post_fifo_axis_tkeep), + .m_axis_tvalid(post_fifo_axis_tvalid), + .m_axis_tready(post_fifo_axis_tready), + .m_axis_tlast(post_fifo_axis_tlast), + .m_axis_tid(post_fifo_axis_tid), + .m_axis_tdest(post_fifo_axis_tdest), + .m_axis_tuser(post_fifo_axis_tuser), + // Pause + .pause_req(pause_req), + .pause_ack(pause_ack), + // Status + .status_depth(status_depth), + .status_depth_commit(status_depth_commit), + .status_overflow(status_overflow), + .status_bad_frame(status_bad_frame), + .status_good_frame(status_good_frame) +); + +if (M_BYTE_LANES < S_BYTE_LANES) begin : downsize_post + + // input wider, adapt width after FIFO + axis_adapter #( .S_DATA_WIDTH(S_DATA_WIDTH), .S_KEEP_ENABLE(S_KEEP_ENABLE), @@ -296,58 +341,21 @@ end else begin .m_axis_tuser(m_axis_tuser) ); +end else begin : bypass_post + + assign m_axis_tdata = post_fifo_axis_tdata; + assign m_axis_tkeep = post_fifo_axis_tkeep; + assign m_axis_tvalid = post_fifo_axis_tvalid; + assign post_fifo_axis_tready = m_axis_tready; + assign m_axis_tlast = post_fifo_axis_tlast; + assign m_axis_tid = post_fifo_axis_tid; + assign m_axis_tdest = post_fifo_axis_tdest; + assign m_axis_tuser = post_fifo_axis_tuser; + end endgenerate -axis_fifo #( - .DEPTH(DEPTH), - .DATA_WIDTH(DATA_WIDTH), - .KEEP_ENABLE(EXPAND_BUS ? M_KEEP_ENABLE : S_KEEP_ENABLE), - .KEEP_WIDTH(KEEP_WIDTH), - .LAST_ENABLE(1), - .ID_ENABLE(ID_ENABLE), - .ID_WIDTH(ID_WIDTH), - .DEST_ENABLE(DEST_ENABLE), - .DEST_WIDTH(DEST_WIDTH), - .USER_ENABLE(USER_ENABLE), - .USER_WIDTH(USER_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - .OUTPUT_FIFO_ENABLE(OUTPUT_FIFO_ENABLE), - .FRAME_FIFO(FRAME_FIFO), - .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE), - .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK), - .DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME), - .DROP_BAD_FRAME(DROP_BAD_FRAME), - .DROP_WHEN_FULL(DROP_WHEN_FULL) -) -fifo_inst ( - .clk(clk), - .rst(rst), - // AXI input - .s_axis_tdata(pre_fifo_axis_tdata), - .s_axis_tkeep(pre_fifo_axis_tkeep), - .s_axis_tvalid(pre_fifo_axis_tvalid), - .s_axis_tready(pre_fifo_axis_tready), - .s_axis_tlast(pre_fifo_axis_tlast), - .s_axis_tid(pre_fifo_axis_tid), - .s_axis_tdest(pre_fifo_axis_tdest), - .s_axis_tuser(pre_fifo_axis_tuser), - // AXI output - .m_axis_tdata(post_fifo_axis_tdata), - .m_axis_tkeep(post_fifo_axis_tkeep), - .m_axis_tvalid(post_fifo_axis_tvalid), - .m_axis_tready(post_fifo_axis_tready), - .m_axis_tlast(post_fifo_axis_tlast), - .m_axis_tid(post_fifo_axis_tid), - .m_axis_tdest(post_fifo_axis_tdest), - .m_axis_tuser(post_fifo_axis_tuser), - // Status - .status_overflow(status_overflow), - .status_bad_frame(status_bad_frame), - .status_good_frame(status_good_frame) -); - endmodule `resetall diff --git a/fpga/lib/eth/lib/axis/rtl/axis_pipeline_fifo.v b/fpga/lib/eth/lib/axis/rtl/axis_pipeline_fifo.v index 4c194bf7e..0f74adae3 100644 --- a/fpga/lib/eth/lib/axis/rtl/axis_pipeline_fifo.v +++ b/fpga/lib/eth/lib/axis/rtl/axis_pipeline_fifo.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -87,85 +87,89 @@ module axis_pipeline_fifo # parameter FIFO_ADDR_WIDTH = LENGTH < 2 ? 3 : $clog2(LENGTH*4+1); +wire [DATA_WIDTH-1:0] axis_tdata_pipe[0:LENGTH]; +wire [KEEP_WIDTH-1:0] axis_tkeep_pipe[0:LENGTH]; +wire axis_tvalid_pipe[0:LENGTH]; +wire axis_tready_pipe[0:LENGTH]; +wire axis_tlast_pipe[0:LENGTH]; +wire [ID_WIDTH-1:0] axis_tid_pipe[0:LENGTH]; +wire [DEST_WIDTH-1:0] axis_tdest_pipe[0:LENGTH]; +wire [USER_WIDTH-1:0] axis_tuser_pipe[0:LENGTH]; + generate -if (LENGTH > 0) begin +genvar n; - // pipeline - (* shreg_extract = "no" *) - reg [DATA_WIDTH-1:0] axis_tdata_reg[0:LENGTH-1]; - (* shreg_extract = "no" *) - reg [KEEP_WIDTH-1:0] axis_tkeep_reg[0:LENGTH-1]; - (* shreg_extract = "no" *) - reg axis_tvalid_reg[0:LENGTH-1]; - (* shreg_extract = "no" *) - reg axis_tready_reg[0:LENGTH-1]; - (* shreg_extract = "no" *) - reg axis_tlast_reg[0:LENGTH-1]; - (* shreg_extract = "no" *) - reg [ID_WIDTH-1:0] axis_tid_reg[0:LENGTH-1]; - (* shreg_extract = "no" *) - reg [DEST_WIDTH-1:0] axis_tdest_reg[0:LENGTH-1]; - (* shreg_extract = "no" *) - reg [USER_WIDTH-1:0] axis_tuser_reg[0:LENGTH-1]; +for (n = 0; n < LENGTH; n = n + 1) begin : stage - wire [DATA_WIDTH-1:0] m_axis_tdata_int = axis_tdata_reg[LENGTH-1]; - wire [KEEP_WIDTH-1:0] m_axis_tkeep_int = axis_tkeep_reg[LENGTH-1]; - wire m_axis_tvalid_int = axis_tvalid_reg[LENGTH-1]; - wire m_axis_tready_int; - wire m_axis_tlast_int = axis_tlast_reg[LENGTH-1]; - wire [ID_WIDTH-1:0] m_axis_tid_int = axis_tid_reg[LENGTH-1]; - wire [DEST_WIDTH-1:0] m_axis_tdest_int = axis_tdest_reg[LENGTH-1]; - wire [USER_WIDTH-1:0] m_axis_tuser_int = axis_tuser_reg[LENGTH-1]; + (* shreg_extract = "no" *) + reg [DATA_WIDTH-1:0] axis_tdata_reg = 0; + (* shreg_extract = "no" *) + reg [KEEP_WIDTH-1:0] axis_tkeep_reg = 0; + (* shreg_extract = "no" *) + reg axis_tvalid_reg = 0; + (* shreg_extract = "no" *) + reg axis_tready_reg = 0; + (* shreg_extract = "no" *) + reg axis_tlast_reg = 0; + (* shreg_extract = "no" *) + reg [ID_WIDTH-1:0] axis_tid_reg = 0; + (* shreg_extract = "no" *) + reg [DEST_WIDTH-1:0] axis_tdest_reg = 0; + (* shreg_extract = "no" *) + reg [USER_WIDTH-1:0] axis_tuser_reg = 0; - assign s_axis_tready = axis_tready_reg[0]; + assign axis_tdata_pipe[n+1] = axis_tdata_reg; + assign axis_tkeep_pipe[n+1] = axis_tkeep_reg; + assign axis_tvalid_pipe[n+1] = axis_tvalid_reg; + assign axis_tlast_pipe[n+1] = axis_tlast_reg; + assign axis_tid_pipe[n+1] = axis_tid_reg; + assign axis_tdest_pipe[n+1] = axis_tdest_reg; + assign axis_tuser_pipe[n+1] = axis_tuser_reg; - integer i; - - initial begin - for (i = 0; i < LENGTH; i = i + 1) begin - axis_tdata_reg[i] = {DATA_WIDTH{1'b0}}; - axis_tkeep_reg[i] = {KEEP_WIDTH{1'b0}}; - axis_tvalid_reg[i] = 1'b0; - axis_tready_reg[i] = 1'b0; - axis_tlast_reg[i] = 1'b0; - axis_tid_reg[i] = {ID_WIDTH{1'b0}}; - axis_tdest_reg[i] = {DEST_WIDTH{1'b0}}; - axis_tuser_reg[i] = {USER_WIDTH{1'b0}}; - end - end + assign axis_tready_pipe[n] = axis_tready_reg; always @(posedge clk) begin - axis_tdata_reg[0] <= s_axis_tdata; - axis_tkeep_reg[0] <= s_axis_tkeep; - axis_tvalid_reg[0] <= s_axis_tvalid && s_axis_tready; - axis_tlast_reg[0] <= s_axis_tlast; - axis_tid_reg[0] <= s_axis_tid; - axis_tdest_reg[0] <= s_axis_tdest; - axis_tuser_reg[0] <= s_axis_tuser; + axis_tdata_reg <= axis_tdata_pipe[n]; + axis_tkeep_reg <= axis_tkeep_pipe[n]; + axis_tvalid_reg <= axis_tvalid_pipe[n]; + axis_tlast_reg <= axis_tlast_pipe[n]; + axis_tid_reg <= axis_tid_pipe[n]; + axis_tdest_reg <= axis_tdest_pipe[n]; + axis_tuser_reg <= axis_tuser_pipe[n]; - axis_tready_reg[LENGTH-1] <= m_axis_tready_int; - - for (i = 0; i < LENGTH-1; i = i + 1) begin - axis_tdata_reg[i+1] <= axis_tdata_reg[i]; - axis_tkeep_reg[i+1] <= axis_tkeep_reg[i]; - axis_tvalid_reg[i+1] <= axis_tvalid_reg[i]; - axis_tlast_reg[i+1] <= axis_tlast_reg[i]; - axis_tid_reg[i+1] <= axis_tid_reg[i]; - axis_tdest_reg[i+1] <= axis_tdest_reg[i]; - axis_tuser_reg[i+1] <= axis_tuser_reg[i]; - - axis_tready_reg[i] <= axis_tready_reg[i+1]; - end + axis_tready_reg <= axis_tready_pipe[n+1]; if (rst) begin - for (i = 0; i < LENGTH; i = i + 1) begin - axis_tvalid_reg[i] <= 1'b0; - axis_tready_reg[i] <= 1'b0; - end + axis_tvalid_reg <= 1'b0; + axis_tready_reg <= 1'b0; end end +end + +if (LENGTH > 0) begin : fifo + + assign axis_tdata_pipe[0] = s_axis_tdata; + assign axis_tkeep_pipe[0] = s_axis_tkeep; + assign axis_tvalid_pipe[0] = s_axis_tvalid & s_axis_tready; + assign axis_tlast_pipe[0] = s_axis_tlast; + assign axis_tid_pipe[0] = s_axis_tid; + assign axis_tdest_pipe[0] = s_axis_tdest; + assign axis_tuser_pipe[0] = s_axis_tuser; + assign s_axis_tready = axis_tready_pipe[0]; + + wire [DATA_WIDTH-1:0] m_axis_tdata_int = axis_tdata_pipe[LENGTH]; + wire [KEEP_WIDTH-1:0] m_axis_tkeep_int = axis_tkeep_pipe[LENGTH]; + wire m_axis_tvalid_int = axis_tvalid_pipe[LENGTH]; + wire m_axis_tready_int; + wire m_axis_tlast_int = axis_tlast_pipe[LENGTH]; + wire [ID_WIDTH-1:0] m_axis_tid_int = axis_tid_pipe[LENGTH]; + wire [DEST_WIDTH-1:0] m_axis_tdest_int = axis_tdest_pipe[LENGTH]; + wire [USER_WIDTH-1:0] m_axis_tuser_int = axis_tuser_pipe[LENGTH]; + + assign axis_tready_pipe[LENGTH] = m_axis_tready_int; + // output datapath logic reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; diff --git a/fpga/lib/eth/lib/axis/syn/quartus/axis_async_fifo.sdc b/fpga/lib/eth/lib/axis/syn/quartus/axis_async_fifo.sdc index 9de844537..13813b714 100644 --- a/fpga/lib/eth/lib/axis/syn/quartus/axis_async_fifo.sdc +++ b/fpga/lib/eth/lib/axis/syn/quartus/axis_async_fifo.sdc @@ -1,4 +1,4 @@ -# Copyright (c) 2020 Alex Forencich +# Copyright (c) 2020-2023 Alex Forencich # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal @@ -36,7 +36,8 @@ proc constrain_axis_async_fifo_inst { inst } { # pointer synchronization set_max_delay -from [get_registers "$inst|rd_ptr_reg[*] $inst|rd_ptr_gray_reg[*]"] -to [get_registers "$inst|rd_ptr_gray_sync1_reg[*]"] 8.000 - set_max_delay -from [get_registers "$inst|wr_ptr_reg[*] $inst|wr_ptr_gray_reg[*] $inst|wr_ptr_sync_gray_reg[*]"] -to [get_registers "$inst|wr_ptr_gray_sync1_reg[*]"] 8.000 + set_max_delay -from [get_registers "$inst|wr_ptr_reg[*] $inst|wr_ptr_gray_reg[*]"] -to [get_registers "$inst|wr_ptr_gray_sync1_reg[*]"] 8.000 + set_max_delay -from [get_registers "$inst|wr_ptr_sync_commit_reg[*]"] -to [get_registers "$inst|wr_ptr_commit_sync_reg[*]"] 8.000 # frame FIFO pointer update synchronization set_max_delay -from [get_registers "$inst|wr_ptr_update_reg"] -to [get_registers "$inst|wr_ptr_update_sync1_reg"] 8.000 diff --git a/fpga/lib/eth/lib/axis/syn/quartus_pro/axis_async_fifo.sdc b/fpga/lib/eth/lib/axis/syn/quartus_pro/axis_async_fifo.sdc index e718d7005..9152f1608 100644 --- a/fpga/lib/eth/lib/axis/syn/quartus_pro/axis_async_fifo.sdc +++ b/fpga/lib/eth/lib/axis/syn/quartus_pro/axis_async_fifo.sdc @@ -1,4 +1,4 @@ -# Copyright (c) 2021 Alex Forencich +# Copyright (c) 2021-2023 Alex Forencich # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal @@ -37,8 +37,10 @@ proc constrain_axis_async_fifo_inst { inst } { # pointer synchronization set_data_delay -from [get_registers "$inst|rd_ptr_reg[*] $inst|rd_ptr_gray_reg[*]"] -to [get_registers "$inst|rd_ptr_gray_sync1_reg[*]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 set_max_skew -from [get_keepers "$inst|rd_ptr_reg[*] $inst|rd_ptr_gray_reg[*]"] -to [get_keepers "$inst|rd_ptr_gray_sync1_reg[*]"] -get_skew_value_from_clock_period min_clock_period -skew_value_multiplier 0.8 - set_data_delay -from [get_registers "$inst|wr_ptr_reg[*] $inst|wr_ptr_gray_reg[*] $inst|wr_ptr_sync_gray_reg[*]"] -to [get_registers "$inst|wr_ptr_gray_sync1_reg[*]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 - set_max_skew -from [get_keepers "$inst|wr_ptr_reg[*] $inst|wr_ptr_gray_reg[*] $inst|wr_ptr_sync_gray_reg[*]"] -to [get_keepers "$inst|wr_ptr_gray_sync1_reg[*]"] -get_skew_value_from_clock_period min_clock_period -skew_value_multiplier 0.8 + set_data_delay -from [get_registers "$inst|wr_ptr_reg[*] $inst|wr_ptr_gray_reg[*]"] -to [get_registers "$inst|wr_ptr_gray_sync1_reg[*]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 + set_max_skew -from [get_keepers "$inst|wr_ptr_reg[*] $inst|wr_ptr_gray_reg[*]"] -to [get_keepers "$inst|wr_ptr_gray_sync1_reg[*]"] -get_skew_value_from_clock_period min_clock_period -skew_value_multiplier 0.8 + set_data_delay -from [get_registers "$inst|wr_ptr_sync_commit_reg[*]"] -to [get_registers "$inst|wr_ptr_commit_sync_reg[*]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 + set_max_skew -from [get_keepers "$inst|wr_ptr_sync_commit_reg[*]"] -to [get_keepers "$inst|wr_ptr_commit_sync_reg[*]"] -get_skew_value_from_clock_period min_clock_period -skew_value_multiplier 0.8 # frame FIFO pointer update synchronization set_data_delay -from [get_registers "$inst|wr_ptr_update_reg"] -to [get_registers "$inst|wr_ptr_update_sync1_reg"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 diff --git a/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl b/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl index 817ac33bb..5654295e0 100644 --- a/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl +++ b/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl @@ -1,4 +1,4 @@ -# Copyright (c) 2019 Alex Forencich +# Copyright (c) 2019-2023 Alex Forencich # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal @@ -78,15 +78,26 @@ foreach fifo_inst [get_cells -hier -filter {(ORIG_REF_NAME == axis_async_fifo || if {[llength $sync_ffs]} { set_property ASYNC_REG TRUE $sync_ffs - set_max_delay -from [get_cells -quiet "$fifo_inst/wr_ptr_reg_reg[*] $fifo_inst/wr_ptr_gray_reg_reg[*] $fifo_inst/wr_ptr_sync_gray_reg_reg[*]"] -to [get_cells "$fifo_inst/wr_ptr_gray_sync1_reg_reg[*]"] -datapath_only $write_clk_period - set_bus_skew -from [get_cells -quiet "$fifo_inst/wr_ptr_reg_reg[*] $fifo_inst/wr_ptr_gray_reg_reg[*] $fifo_inst/wr_ptr_sync_gray_reg_reg[*]"] -to [get_cells "$fifo_inst/wr_ptr_gray_sync1_reg_reg[*]"] $read_clk_period + set_max_delay -from [get_cells -quiet "$fifo_inst/wr_ptr_reg_reg[*] $fifo_inst/wr_ptr_gray_reg_reg[*]"] -to [get_cells "$fifo_inst/wr_ptr_gray_sync1_reg_reg[*]"] -datapath_only $write_clk_period + set_bus_skew -from [get_cells -quiet "$fifo_inst/wr_ptr_reg_reg[*] $fifo_inst/wr_ptr_gray_reg_reg[*]"] -to [get_cells "$fifo_inst/wr_ptr_gray_sync1_reg_reg[*]"] $read_clk_period + } + + set sync_ffs [get_cells -quiet -hier -regexp ".*/wr_ptr_commit_sync_reg_reg\\\[\\d+\\\]" -filter "PARENT == $fifo_inst"] + + if {[llength $sync_ffs]} { + set_property ASYNC_REG TRUE $sync_ffs + + set_max_delay -from [get_cells -quiet "$fifo_inst/wr_ptr_sync_commit_reg_reg[*]"] -to [get_cells "$fifo_inst/wr_ptr_commit_sync_reg_reg[*]"] -datapath_only $write_clk_period + set_bus_skew -from [get_cells -quiet "$fifo_inst/wr_ptr_sync_commit_reg_reg[*]"] -to [get_cells "$fifo_inst/wr_ptr_commit_sync_reg_reg[*]"] $read_clk_period } # output register (needed for distributed RAM sync write/async read) set output_reg_ffs [get_cells -quiet "$fifo_inst/m_axis_pipe_reg_reg[0][*]"] if {[llength $output_reg_ffs]} { - set_false_path -from $write_clk -to $output_reg_ffs + if {[llength $write_clk]} { + set_false_path -from $write_clk -to $output_reg_ffs + } } # frame FIFO pointer update synchronization @@ -109,4 +120,21 @@ foreach fifo_inst [get_cells -hier -filter {(ORIG_REF_NAME == axis_async_fifo || set_max_delay -from [get_cells "$fifo_inst/${i}_sync1_reg_reg"] -to [get_cells "$fifo_inst/${i}_sync2_reg_reg"] -datapath_only $read_clk_period } } + + # pause sync + set sync_ffs [get_cells -quiet -hier -regexp ".*/pause.s_pause_req_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"] + + if {[llength $sync_ffs]} { + set_property ASYNC_REG TRUE $sync_ffs + + set_max_delay -from [get_cells "$fifo_inst/pause.s_pause_req_sync1_reg_reg"] -to [get_cells "$fifo_inst/pause.s_pause_req_sync2_reg_reg"] -datapath_only $read_clk_period + } + + set sync_ffs [get_cells -quiet -hier -regexp ".*/pause.s_pause_ack_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"] + + if {[llength $sync_ffs]} { + set_property ASYNC_REG TRUE $sync_ffs + + set_max_delay -from [get_cells "$fifo_inst/pause.s_pause_ack_sync1_reg_reg"] -to [get_cells "$fifo_inst/pause.s_pause_ack_sync2_reg_reg"] -datapath_only $write_clk_period + } } diff --git a/fpga/lib/eth/lib/axis/tb/axis_async_fifo/Makefile b/fpga/lib/eth/lib/axis/tb/axis_async_fifo/Makefile index 70c29fd77..10ffd633f 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_async_fifo/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_async_fifo/Makefile @@ -32,10 +32,10 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DEPTH := 1024 export PARAM_DATA_WIDTH := 8 -export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_KEEP_ENABLE := $(shell echo $$(( $(PARAM_DATA_WIDTH) > 8 ))) +export PARAM_KEEP_WIDTH := $(shell echo $$(( ( $(PARAM_DATA_WIDTH) + 7 ) / 8 ))) +export PARAM_DEPTH := $(shell echo $$(( 1024 * $(PARAM_KEEP_WIDTH) ))) export PARAM_LAST_ENABLE := 1 export PARAM_ID_ENABLE := 1 export PARAM_ID_WIDTH := 8 @@ -51,6 +51,9 @@ export PARAM_USER_BAD_FRAME_MASK := 1 export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO) export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME) export PARAM_DROP_WHEN_FULL := 0 +export PARAM_MARK_WHEN_FULL := 0 +export PARAM_PAUSE_ENABLE := 1 +export PARAM_FRAME_PAUSE := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py b/fpga/lib/eth/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py index c4f13e5f1..4b126a793 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py +++ b/fpga/lib/eth/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py @@ -55,6 +55,9 @@ class TB(object): self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis"), dut.s_clk, dut.s_rst) self.sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis"), dut.m_clk, dut.m_rst) + dut.s_pause_req.setimmediatevalue(0) + dut.m_pause_req.setimmediatevalue(0) + def set_idle_generator(self, generator=None): if generator: self.source.set_pause_generator(generator()) @@ -149,7 +152,7 @@ async def run_test_tuser_assert(dut): test_frame = AxiStreamFrame(test_data, tuser=1) await tb.source.send(test_frame) - if int(os.getenv("PARAM_DROP_BAD_FRAME")): + if dut.DROP_BAD_FRAME.value: for k in range(64): await RisingEdge(dut.s_clk) @@ -299,7 +302,7 @@ async def run_test_shift_in_source_reset(dut): for k in range(64): await RisingEdge(dut.s_clk) - if int(os.getenv("PARAM_FRAME_FIFO")): + if dut.FRAME_FIFO.value: assert tb.sink.empty() else: rx_frame = await tb.sink.recv() @@ -393,32 +396,149 @@ async def run_test_shift_out_sink_reset(dut): await RisingEdge(dut.s_clk) +async def run_test_pause(dut): + + tb = TB(dut) + + byte_lanes = tb.source.byte_lanes + + await tb.reset() + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 16*byte_lanes)) + test_frame = AxiStreamFrame(test_data) + + for k in range(16): + await tb.source.send(test_frame) + + for k in range(60): + await RisingEdge(dut.s_clk) + + dut.m_pause_req.value = 1 + + for k in range(64): + await RisingEdge(dut.s_clk) + + assert tb.sink.idle() + + dut.m_pause_req.value = 0 + + for k in range(60): + await RisingEdge(dut.s_clk) + + dut.s_pause_req.value = 1 + + for k in range(64): + await RisingEdge(dut.s_clk) + + assert tb.sink.idle() + + dut.s_pause_req.value = 0 + + for k in range(16): + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_data + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.s_clk) + await RisingEdge(dut.s_clk) + + async def run_test_overflow(dut): tb = TB(dut) + depth = dut.DEPTH.value + byte_lanes = tb.source.byte_lanes + await tb.reset() tb.sink.pause = True - test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 2048)) + size = (16*byte_lanes) + count = depth*2 // size + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), size)) + test_frame = AxiStreamFrame(test_data) + for k in range(count): + await tb.source.send(test_frame) + + for k in range((depth//byte_lanes)*3): + await RisingEdge(dut.s_clk) + + if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value: + assert tb.source.idle() + else: + assert not tb.source.idle() + + tb.sink.pause = False + + if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value: + for k in range((depth//byte_lanes)*3): + await RisingEdge(dut.s_clk) + + rx_count = 0 + + while not tb.sink.empty(): + rx_frame = await tb.sink.recv() + + if dut.MARK_WHEN_FULL.value and rx_frame.tuser: + continue + + assert rx_frame.tdata == test_data + assert not rx_frame.tuser + + rx_count += 1 + + assert rx_count < count + + else: + for k in range(count): + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_data + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.s_clk) + await RisingEdge(dut.s_clk) + + +async def run_test_oversize(dut): + + tb = TB(dut) + + depth = dut.DEPTH.value + byte_lanes = tb.source.byte_lanes + + await tb.reset() + + tb.sink.pause = True + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), depth*2)) test_frame = AxiStreamFrame(test_data) await tb.source.send(test_frame) - for k in range(2048): + for k in range((depth//byte_lanes)*2): await RisingEdge(dut.s_clk) tb.sink.pause = False - if int(os.getenv("PARAM_DROP_OVERSIZE_FRAME")): - for k in range(2048): + if dut.DROP_OVERSIZE_FRAME.value: + for k in range((depth//byte_lanes)*2): await RisingEdge(dut.s_clk) else: rx_frame = await tb.sink.recv() - assert rx_frame.tdata == test_data - assert not rx_frame.tuser + if dut.MARK_WHEN_FULL.value: + assert rx_frame.tuser + else: + assert rx_frame.tdata == test_data + assert not rx_frame.tuser assert tb.sink.empty() @@ -442,7 +562,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): test_frames = [] - for k in range(128): + for k in range(512): length = random.randint(1, byte_lanes*16) test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length)) test_frame = AxiStreamFrame(test_data) @@ -454,13 +574,37 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): cur_id = (cur_id + 1) % id_count - for test_frame in test_frames: - rx_frame = await tb.sink.recv() + if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value: + cycles = 0 + while cycles < 100: + cycles += 1 + if not tb.source.idle() or dut.s_axis_tvalid.value.integer or dut.m_axis_tvalid.value.integer or dut.m_status_depth.value.integer: + cycles = 0 + await RisingEdge(dut.m_clk) - assert rx_frame.tdata == test_frame.tdata - assert rx_frame.tid == test_frame.tid - assert rx_frame.tdest == test_frame.tdest - assert not rx_frame.tuser + while not tb.sink.empty(): + rx_frame = await tb.sink.recv() + + if dut.MARK_WHEN_FULL.value and rx_frame.tuser: + continue + + assert not rx_frame.tuser + + while True: + test_frame = test_frames.pop(0) + if rx_frame.tid == test_frame.tid and rx_frame.tdest == test_frame.tdest and rx_frame.tdata == test_frame.tdata: + break + + assert len(test_frames) < 512 + + else: + for test_frame in test_frames: + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_frame.tdata + assert rx_frame.tid == test_frame.tid + assert rx_frame.tdest == test_frame.tdest + assert not rx_frame.tuser assert tb.sink.empty() @@ -501,7 +645,9 @@ if cocotb.SIM_NAME: run_test_shift_in_sink_reset, run_test_shift_out_source_reset, run_test_shift_out_sink_reset, - run_test_overflow + run_test_pause, + run_test_overflow, + run_test_oversize ]: factory = TestFactory(test) @@ -520,13 +666,16 @@ rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) @pytest.mark.parametrize(("s_clk", "m_clk"), [(10, 10), (10, 11), (11, 10)]) -@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame", "drop_when_full"), - [(0, 0, 0, 0), (1, 0, 0, 0), (1, 1, 0, 0), (1, 1, 1, 0)]) +@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame", + "drop_when_full", "mark_when_full"), + [(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0), + (1, 1, 1, 1, 0), (0, 0, 0, 0, 1)]) @pytest.mark.parametrize(("ram_pipeline", "output_fifo"), [(0, 0), (1, 0), (4, 0), (0, 1), (1, 1), (4, 1)]) @pytest.mark.parametrize("data_width", [8, 16, 32, 64]) def test_axis_async_fifo(request, data_width, ram_pipeline, output_fifo, - frame_fifo, drop_oversize_frame, drop_bad_frame, drop_when_full, s_clk, m_clk): + frame_fifo, drop_oversize_frame, drop_bad_frame, + drop_when_full, mark_when_full, s_clk, m_clk): dut = "axis_async_fifo" module = os.path.splitext(os.path.basename(__file__))[0] @@ -538,10 +687,10 @@ def test_axis_async_fifo(request, data_width, ram_pipeline, output_fifo, parameters = {} - parameters['DEPTH'] = 1024 parameters['DATA_WIDTH'] = data_width parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8 + parameters['DEPTH'] = 1024 * parameters['KEEP_WIDTH'] parameters['LAST_ENABLE'] = 1 parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 @@ -557,6 +706,9 @@ def test_axis_async_fifo(request, data_width, ram_pipeline, output_fifo, parameters['DROP_OVERSIZE_FRAME'] = drop_oversize_frame parameters['DROP_BAD_FRAME'] = drop_bad_frame parameters['DROP_WHEN_FULL'] = drop_when_full + parameters['MARK_WHEN_FULL'] = mark_when_full + parameters['PAUSE_ENABLE'] = 1 + parameters['FRAME_PAUSE'] = 1 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/fpga/lib/eth/lib/axis/tb/axis_async_fifo_adapter/Makefile b/fpga/lib/eth/lib/axis/tb/axis_async_fifo_adapter/Makefile index 90cca22fe..e70946194 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_async_fifo_adapter/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_async_fifo_adapter/Makefile @@ -34,14 +34,13 @@ VERILOG_SOURCES += ../../rtl/axis_async_fifo.v VERILOG_SOURCES += ../../rtl/axis_adapter.v # module parameters -export PARAM_DEPTH := 1024 export PARAM_S_DATA_WIDTH := 8 -export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 ) -export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_S_KEEP_ENABLE := $(shell echo $$(( $(PARAM_S_DATA_WIDTH) > 8 ))) +export PARAM_S_KEEP_WIDTH := $(shell echo $$(( ( $(PARAM_S_DATA_WIDTH) + 7 ) / 8 ))) export PARAM_M_DATA_WIDTH := 8 -export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 ) -export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_LAST_ENABLE := 1 +export PARAM_M_KEEP_ENABLE := $(shell echo $$(( $(PARAM_M_DATA_WIDTH) > 8 ))) +export PARAM_M_KEEP_WIDTH := $(shell echo $$(( ( $(PARAM_M_DATA_WIDTH) + 7 ) / 8 ))) +export PARAM_DEPTH := $(shell echo $$(( 1024 * ($(PARAM_S_KEEP_WIDTH) > $(PARAM_M_KEEP_WIDTH) ? $(PARAM_S_KEEP_WIDTH) : $(PARAM_M_KEEP_WIDTH)) ))) export PARAM_ID_ENABLE := 1 export PARAM_ID_WIDTH := 8 export PARAM_DEST_ENABLE := 1 @@ -56,6 +55,9 @@ export PARAM_USER_BAD_FRAME_MASK := 1 export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO) export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME) export PARAM_DROP_WHEN_FULL := 0 +export PARAM_MARK_WHEN_FULL := 0 +export PARAM_PAUSE_ENABLE := 1 +export PARAM_FRAME_PAUSE := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py b/fpga/lib/eth/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py index 0e62fcbd8..5d09b0703 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py +++ b/fpga/lib/eth/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py @@ -52,6 +52,9 @@ class TB(object): self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis"), dut.s_clk, dut.s_rst) self.sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis"), dut.m_clk, dut.m_rst) + dut.s_pause_req.setimmediatevalue(0) + dut.m_pause_req.setimmediatevalue(0) + def set_idle_generator(self, generator=None): if generator: self.source.set_pause_generator(generator()) @@ -146,7 +149,7 @@ async def run_test_tuser_assert(dut): test_frame = AxiStreamFrame(test_data, tuser=1) await tb.source.send(test_frame) - if int(os.getenv("PARAM_DROP_BAD_FRAME")): + if dut.DROP_BAD_FRAME.value: for k in range(64): await RisingEdge(dut.s_clk) @@ -296,7 +299,7 @@ async def run_test_shift_in_source_reset(dut): for k in range(64): await RisingEdge(dut.s_clk) - if int(os.getenv("PARAM_FRAME_FIFO")): + if dut.FRAME_FIFO.value: assert tb.sink.empty() else: rx_frame = await tb.sink.recv() @@ -390,32 +393,149 @@ async def run_test_shift_out_sink_reset(dut): await RisingEdge(dut.s_clk) +async def run_test_pause(dut): + + tb = TB(dut) + + byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes) + + await tb.reset() + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 16*byte_lanes)) + test_frame = AxiStreamFrame(test_data) + + for k in range(16): + await tb.source.send(test_frame) + + for k in range(60): + await RisingEdge(dut.s_clk) + + dut.m_pause_req.value = 1 + + for k in range(64): + await RisingEdge(dut.s_clk) + + assert tb.sink.idle() + + dut.m_pause_req.value = 0 + + for k in range(60): + await RisingEdge(dut.s_clk) + + dut.s_pause_req.value = 1 + + for k in range(64): + await RisingEdge(dut.s_clk) + + assert tb.sink.idle() + + dut.s_pause_req.value = 0 + + for k in range(16): + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_data + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.s_clk) + await RisingEdge(dut.s_clk) + + async def run_test_overflow(dut): tb = TB(dut) + depth = dut.DEPTH.value + byte_lanes = min(tb.source.byte_lanes, tb.sink.byte_lanes) + await tb.reset() tb.sink.pause = True - test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 2048)) + size = (16*byte_lanes) + count = depth*2 // size + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), size)) + test_frame = AxiStreamFrame(test_data) + for k in range(count): + await tb.source.send(test_frame) + + for k in range((depth//byte_lanes)*3): + await RisingEdge(dut.s_clk) + + if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value: + assert tb.source.idle() + else: + assert not tb.source.idle() + + tb.sink.pause = False + + if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value: + for k in range((depth//byte_lanes)*3): + await RisingEdge(dut.s_clk) + + rx_count = 0 + + while not tb.sink.empty(): + rx_frame = await tb.sink.recv() + + if dut.MARK_WHEN_FULL.value and rx_frame.tuser: + continue + + assert rx_frame.tdata == test_data + assert not rx_frame.tuser + + rx_count += 1 + + assert rx_count < count + + else: + for k in range(count): + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_data + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.s_clk) + await RisingEdge(dut.s_clk) + + +async def run_test_oversize(dut): + + tb = TB(dut) + + depth = dut.DEPTH.value + byte_lanes = min(tb.source.byte_lanes, tb.sink.byte_lanes) + + await tb.reset() + + tb.sink.pause = True + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), depth*2)) test_frame = AxiStreamFrame(test_data) await tb.source.send(test_frame) - for k in range(2048): + for k in range((depth//byte_lanes)*2): await RisingEdge(dut.s_clk) tb.sink.pause = False - if int(os.getenv("PARAM_DROP_OVERSIZE_FRAME")): - for k in range(2048): + if dut.DROP_OVERSIZE_FRAME.value: + for k in range((depth//byte_lanes)*2): await RisingEdge(dut.s_clk) else: rx_frame = await tb.sink.recv() - assert rx_frame.tdata == test_data - assert not rx_frame.tuser + if dut.MARK_WHEN_FULL.value: + assert rx_frame.tuser + else: + assert rx_frame.tdata == test_data + assert not rx_frame.tuser assert tb.sink.empty() @@ -439,7 +559,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): test_frames = [] - for k in range(128): + for k in range(512): length = random.randint(1, byte_lanes*16) test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length)) test_frame = AxiStreamFrame(test_data) @@ -451,13 +571,37 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): cur_id = (cur_id + 1) % id_count - for test_frame in test_frames: - rx_frame = await tb.sink.recv() + if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value: + cycles = 0 + while cycles < 100: + cycles += 1 + if not tb.source.idle() or dut.s_axis_tvalid.value.integer or dut.m_axis_tvalid.value.integer or dut.m_status_depth.value.integer: + cycles = 0 + await RisingEdge(dut.m_clk) - assert rx_frame.tdata == test_frame.tdata - assert rx_frame.tid == test_frame.tid - assert rx_frame.tdest == test_frame.tdest - assert not rx_frame.tuser + while not tb.sink.empty(): + rx_frame = await tb.sink.recv() + + if dut.MARK_WHEN_FULL.value and rx_frame.tuser: + continue + + assert not rx_frame.tuser + + while True: + test_frame = test_frames.pop(0) + if rx_frame.tid == test_frame.tid and rx_frame.tdest == test_frame.tdest and rx_frame.tdata == test_frame.tdata: + break + + assert len(test_frames) < 512 + + else: + for test_frame in test_frames: + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_frame.tdata + assert rx_frame.tid == test_frame.tid + assert rx_frame.tdest == test_frame.tdest + assert not rx_frame.tuser assert tb.sink.empty() @@ -498,7 +642,9 @@ if cocotb.SIM_NAME: run_test_shift_in_sink_reset, run_test_shift_out_source_reset, run_test_shift_out_sink_reset, - run_test_overflow + run_test_pause, + run_test_overflow, + run_test_oversize ]: factory = TestFactory(test) @@ -516,11 +662,15 @@ tests_dir = os.path.dirname(__file__) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame", "drop_when_full"), - [(0, 0, 0, 0), (1, 0, 0, 0), (1, 1, 0, 0), (1, 1, 1, 0)]) +@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame", + "drop_when_full", "mark_when_full"), + [(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0), + (1, 1, 1, 1, 0), (0, 0, 0, 0, 1)]) @pytest.mark.parametrize("m_data_width", [8, 16, 32]) @pytest.mark.parametrize("s_data_width", [8, 16, 32]) -def test_axis_async_fifo_adapter(request, s_data_width, m_data_width, frame_fifo, drop_oversize_frame, drop_bad_frame, drop_when_full): +def test_axis_async_fifo_adapter(request, s_data_width, m_data_width, + frame_fifo, drop_oversize_frame, drop_bad_frame, + drop_when_full, mark_when_full): dut = "axis_async_fifo_adapter" module = os.path.splitext(os.path.basename(__file__))[0] toplevel = dut @@ -533,13 +683,13 @@ def test_axis_async_fifo_adapter(request, s_data_width, m_data_width, frame_fifo parameters = {} - parameters['DEPTH'] = 1024 parameters['S_DATA_WIDTH'] = s_data_width parameters['S_KEEP_ENABLE'] = int(parameters['S_DATA_WIDTH'] > 8) parameters['S_KEEP_WIDTH'] = (parameters['S_DATA_WIDTH'] + 7) // 8 parameters['M_DATA_WIDTH'] = m_data_width parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8) parameters['M_KEEP_WIDTH'] = (parameters['M_DATA_WIDTH'] + 7) // 8 + parameters['DEPTH'] = 1024 * max(parameters['S_KEEP_WIDTH'], parameters['M_KEEP_WIDTH']) parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 parameters['DEST_ENABLE'] = 1 @@ -554,6 +704,9 @@ def test_axis_async_fifo_adapter(request, s_data_width, m_data_width, frame_fifo parameters['DROP_OVERSIZE_FRAME'] = drop_oversize_frame parameters['DROP_BAD_FRAME'] = drop_bad_frame parameters['DROP_WHEN_FULL'] = drop_when_full + parameters['MARK_WHEN_FULL'] = mark_when_full + parameters['PAUSE_ENABLE'] = 1 + parameters['FRAME_PAUSE'] = 1 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/fpga/lib/eth/lib/axis/tb/axis_fifo/Makefile b/fpga/lib/eth/lib/axis/tb/axis_fifo/Makefile index d22bb2aa8..c10508ee8 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_fifo/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_fifo/Makefile @@ -32,10 +32,10 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters -export PARAM_DEPTH := 1024 export PARAM_DATA_WIDTH := 8 -export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH := $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_KEEP_ENABLE := $(shell echo $$(( $(PARAM_DATA_WIDTH) > 8 ))) +export PARAM_KEEP_WIDTH := $(shell echo $$(( ( $(PARAM_DATA_WIDTH) + 7 ) / 8 ))) +export PARAM_DEPTH := $(shell echo $$(( 1024 * $(PARAM_KEEP_WIDTH) ))) export PARAM_LAST_ENABLE := 1 export PARAM_ID_ENABLE := 1 export PARAM_ID_WIDTH := 8 @@ -51,6 +51,9 @@ export PARAM_USER_BAD_FRAME_MASK := 1 export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO) export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME) export PARAM_DROP_WHEN_FULL := 0 +export PARAM_MARK_WHEN_FULL := 0 +export PARAM_PAUSE_ENABLE := 1 +export PARAM_FRAME_PAUSE := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_fifo/test_axis_fifo.py b/fpga/lib/eth/lib/axis/tb/axis_fifo/test_axis_fifo.py index 5a5fc6fd7..e89c0a5ff 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_fifo/test_axis_fifo.py +++ b/fpga/lib/eth/lib/axis/tb/axis_fifo/test_axis_fifo.py @@ -51,6 +51,8 @@ class TB(object): self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis"), dut.clk, dut.rst) self.sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis"), dut.clk, dut.rst) + dut.pause_req.setimmediatevalue(0) + def set_idle_generator(self, generator=None): if generator: self.source.set_pause_generator(generator()) @@ -120,7 +122,7 @@ async def run_test_tuser_assert(dut): test_frame = AxiStreamFrame(test_data, tuser=1) await tb.source.send(test_frame) - if int(os.getenv("PARAM_DROP_BAD_FRAME")): + if dut.DROP_BAD_FRAME.value: for k in range(64): await RisingEdge(dut.clk) @@ -192,32 +194,137 @@ async def run_test_init_sink_pause_reset(dut): await RisingEdge(dut.clk) +async def run_test_pause(dut): + + tb = TB(dut) + + byte_lanes = tb.source.byte_lanes + + await tb.reset() + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 16*byte_lanes)) + test_frame = AxiStreamFrame(test_data) + + for k in range(16): + await tb.source.send(test_frame) + + for k in range(60): + await RisingEdge(dut.clk) + + dut.pause_req.value = 1 + + for k in range(64): + await RisingEdge(dut.clk) + + assert tb.sink.idle() + + dut.pause_req.value = 0 + + for k in range(16): + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_data + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + async def run_test_overflow(dut): tb = TB(dut) + depth = dut.DEPTH.value + byte_lanes = tb.source.byte_lanes + await tb.reset() tb.sink.pause = True - test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 2048)) + size = (16*byte_lanes) + count = depth*2 // size + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), size)) + test_frame = AxiStreamFrame(test_data) + for k in range(count): + await tb.source.send(test_frame) + + for k in range((depth//byte_lanes)*3): + await RisingEdge(dut.clk) + + if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value: + assert tb.source.idle() + else: + assert not tb.source.idle() + + tb.sink.pause = False + + if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value: + for k in range((depth//byte_lanes)*3): + await RisingEdge(dut.clk) + + rx_count = 0 + + while not tb.sink.empty(): + rx_frame = await tb.sink.recv() + + if dut.MARK_WHEN_FULL.value and rx_frame.tuser: + continue + + assert rx_frame.tdata == test_data + assert not rx_frame.tuser + + rx_count += 1 + + assert rx_count < count + + else: + for k in range(count): + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_data + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_oversize(dut): + + tb = TB(dut) + + depth = dut.DEPTH.value + byte_lanes = tb.source.byte_lanes + + await tb.reset() + + tb.sink.pause = True + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), depth*2)) test_frame = AxiStreamFrame(test_data) await tb.source.send(test_frame) - for k in range(2048): + for k in range((depth//byte_lanes)*2): await RisingEdge(dut.clk) tb.sink.pause = False - if int(os.getenv("PARAM_DROP_OVERSIZE_FRAME")): - for k in range(2048): + if dut.DROP_OVERSIZE_FRAME.value: + for k in range((depth//byte_lanes)*2): await RisingEdge(dut.clk) else: rx_frame = await tb.sink.recv() - assert rx_frame.tdata == test_data - assert not rx_frame.tuser + if dut.MARK_WHEN_FULL.value: + assert rx_frame.tuser + else: + assert rx_frame.tdata == test_data + assert not rx_frame.tuser assert tb.sink.empty() @@ -241,7 +348,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): test_frames = [] - for k in range(128): + for k in range(512): length = random.randint(1, byte_lanes*16) test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length)) test_frame = AxiStreamFrame(test_data) @@ -253,13 +360,39 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): cur_id = (cur_id + 1) % id_count - for test_frame in test_frames: - rx_frame = await tb.sink.recv() + if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value: + cycles = 0 + while cycles < 100: + cycles += 1 + if not tb.source.idle() or dut.s_axis_tvalid.value.integer or dut.m_axis_tvalid.value.integer or dut.status_depth.value.integer: + cycles = 0 + await RisingEdge(dut.clk) - assert rx_frame.tdata == test_frame.tdata - assert rx_frame.tid == test_frame.tid - assert rx_frame.tdest == test_frame.tdest - assert not rx_frame.tuser + while not tb.sink.empty(): + rx_frame = await tb.sink.recv() + + if dut.MARK_WHEN_FULL.value and rx_frame.tuser: + continue + + assert not rx_frame.tuser + + assert len(test_frames) > 0 + + while True: + test_frame = test_frames.pop(0) + if rx_frame.tid == test_frame.tid and rx_frame.tdest == test_frame.tdest and rx_frame.tdata == test_frame.tdata: + break + + assert len(test_frames) < 512 + + else: + for test_frame in test_frames: + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_frame.tdata + assert rx_frame.tid == test_frame.tid + assert rx_frame.tdest == test_frame.tdest + assert not rx_frame.tuser assert tb.sink.empty() @@ -294,7 +427,9 @@ if cocotb.SIM_NAME: run_test_tuser_assert, run_test_init_sink_pause, run_test_init_sink_pause_reset, - run_test_overflow + run_test_pause, + run_test_overflow, + run_test_oversize ]: factory = TestFactory(test) @@ -312,13 +447,16 @@ tests_dir = os.path.dirname(__file__) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame", "drop_when_full"), - [(0, 0, 0, 0), (1, 0, 0, 0), (1, 1, 0, 0), (1, 1, 1, 0)]) +@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame", + "drop_when_full", "mark_when_full"), + [(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0), + (1, 1, 1, 1, 0), (0, 0, 0, 0, 1)]) @pytest.mark.parametrize(("ram_pipeline", "output_fifo"), [(0, 0), (1, 0), (4, 0), (0, 1), (1, 1), (4, 1)]) @pytest.mark.parametrize("data_width", [8, 16, 32, 64]) def test_axis_fifo(request, data_width, ram_pipeline, output_fifo, - frame_fifo, drop_oversize_frame, drop_bad_frame, drop_when_full): + frame_fifo, drop_oversize_frame, drop_bad_frame, + drop_when_full, mark_when_full): dut = "axis_fifo" module = os.path.splitext(os.path.basename(__file__))[0] @@ -330,10 +468,10 @@ def test_axis_fifo(request, data_width, ram_pipeline, output_fifo, parameters = {} - parameters['DEPTH'] = 1024 parameters['DATA_WIDTH'] = data_width parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8 + parameters['DEPTH'] = 1024 * parameters['KEEP_WIDTH'] parameters['LAST_ENABLE'] = 1 parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 @@ -349,6 +487,9 @@ def test_axis_fifo(request, data_width, ram_pipeline, output_fifo, parameters['DROP_OVERSIZE_FRAME'] = drop_oversize_frame parameters['DROP_BAD_FRAME'] = drop_bad_frame parameters['DROP_WHEN_FULL'] = drop_when_full + parameters['MARK_WHEN_FULL'] = mark_when_full + parameters['PAUSE_ENABLE'] = 1 + parameters['FRAME_PAUSE'] = 1 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/fpga/lib/eth/lib/axis/tb/axis_fifo_adapter/Makefile b/fpga/lib/eth/lib/axis/tb/axis_fifo_adapter/Makefile index e53ca10b3..65234e80b 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_fifo_adapter/Makefile +++ b/fpga/lib/eth/lib/axis/tb/axis_fifo_adapter/Makefile @@ -34,14 +34,13 @@ VERILOG_SOURCES += ../../rtl/axis_fifo.v VERILOG_SOURCES += ../../rtl/axis_adapter.v # module parameters -export PARAM_DEPTH := 1024 export PARAM_S_DATA_WIDTH := 8 -export PARAM_S_KEEP_ENABLE := $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 ) -export PARAM_S_KEEP_WIDTH := $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 ) +export PARAM_S_KEEP_ENABLE := $(shell echo $$(( $(PARAM_S_DATA_WIDTH) > 8 ))) +export PARAM_S_KEEP_WIDTH := $(shell echo $$(( ( $(PARAM_S_DATA_WIDTH) + 7 ) / 8 ))) export PARAM_M_DATA_WIDTH := 8 -export PARAM_M_KEEP_ENABLE := $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 ) -export PARAM_M_KEEP_WIDTH := $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 ) -export PARAM_LAST_ENABLE := 1 +export PARAM_M_KEEP_ENABLE := $(shell echo $$(( $(PARAM_M_DATA_WIDTH) > 8 ))) +export PARAM_M_KEEP_WIDTH := $(shell echo $$(( ( $(PARAM_M_DATA_WIDTH) + 7 ) / 8 ))) +export PARAM_DEPTH := $(shell echo $$(( 1024 * ($(PARAM_S_KEEP_WIDTH) > $(PARAM_M_KEEP_WIDTH) ? $(PARAM_S_KEEP_WIDTH) : $(PARAM_M_KEEP_WIDTH)) ))) export PARAM_ID_ENABLE := 1 export PARAM_ID_WIDTH := 8 export PARAM_DEST_ENABLE := 1 @@ -56,6 +55,9 @@ export PARAM_USER_BAD_FRAME_MASK := 1 export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO) export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME) export PARAM_DROP_WHEN_FULL := 0 +export PARAM_MARK_WHEN_FULL := 0 +export PARAM_PAUSE_ENABLE := 1 +export PARAM_FRAME_PAUSE := 1 ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py b/fpga/lib/eth/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py index b22310634..5b4b992ad 100644 --- a/fpga/lib/eth/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py +++ b/fpga/lib/eth/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py @@ -51,6 +51,8 @@ class TB(object): self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis"), dut.clk, dut.rst) self.sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis"), dut.clk, dut.rst) + dut.pause_req.setimmediatevalue(0) + def set_idle_generator(self, generator=None): if generator: self.source.set_pause_generator(generator()) @@ -120,7 +122,7 @@ async def run_test_tuser_assert(dut): test_frame = AxiStreamFrame(test_data, tuser=1) await tb.source.send(test_frame) - if int(os.getenv("PARAM_DROP_BAD_FRAME")): + if dut.DROP_BAD_FRAME.value: for k in range(64): await RisingEdge(dut.clk) @@ -192,32 +194,137 @@ async def run_test_init_sink_pause_reset(dut): await RisingEdge(dut.clk) +async def run_test_pause(dut): + + tb = TB(dut) + + byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes) + + await tb.reset() + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 16*byte_lanes)) + test_frame = AxiStreamFrame(test_data) + + for k in range(16): + await tb.source.send(test_frame) + + for k in range(60): + await RisingEdge(dut.clk) + + dut.pause_req.value = 1 + + for k in range(64): + await RisingEdge(dut.clk) + + assert tb.sink.idle() + + dut.pause_req.value = 0 + + for k in range(16): + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_data + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + async def run_test_overflow(dut): tb = TB(dut) + depth = dut.DEPTH.value + byte_lanes = min(tb.source.byte_lanes, tb.sink.byte_lanes) + await tb.reset() tb.sink.pause = True - test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 2048)) + size = (16*byte_lanes) + count = depth*2 // size + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), size)) + test_frame = AxiStreamFrame(test_data) + for k in range(count): + await tb.source.send(test_frame) + + for k in range((depth//byte_lanes)*3): + await RisingEdge(dut.clk) + + if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value: + assert tb.source.idle() + else: + assert not tb.source.idle() + + tb.sink.pause = False + + if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value: + for k in range((depth//byte_lanes)*3): + await RisingEdge(dut.clk) + + rx_count = 0 + + while not tb.sink.empty(): + rx_frame = await tb.sink.recv() + + if dut.MARK_WHEN_FULL.value and rx_frame.tuser: + continue + + assert rx_frame.tdata == test_data + assert not rx_frame.tuser + + rx_count += 1 + + assert rx_count < count + + else: + for k in range(count): + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_data + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_oversize(dut): + + tb = TB(dut) + + depth = dut.DEPTH.value + byte_lanes = min(tb.source.byte_lanes, tb.sink.byte_lanes) + + await tb.reset() + + tb.sink.pause = True + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), depth*2)) test_frame = AxiStreamFrame(test_data) await tb.source.send(test_frame) - for k in range(2048): + for k in range((depth//byte_lanes)*2): await RisingEdge(dut.clk) tb.sink.pause = False - if int(os.getenv("PARAM_DROP_OVERSIZE_FRAME")): - for k in range(2048): + if dut.DROP_OVERSIZE_FRAME.value: + for k in range((depth//byte_lanes)*2): await RisingEdge(dut.clk) else: rx_frame = await tb.sink.recv() - assert rx_frame.tdata == test_data - assert not rx_frame.tuser + if dut.MARK_WHEN_FULL.value: + assert rx_frame.tuser + else: + assert rx_frame.tdata == test_data + assert not rx_frame.tuser assert tb.sink.empty() @@ -241,7 +348,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): test_frames = [] - for k in range(128): + for k in range(512): length = random.randint(1, byte_lanes*16) test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length)) test_frame = AxiStreamFrame(test_data) @@ -253,13 +360,37 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): cur_id = (cur_id + 1) % id_count - for test_frame in test_frames: - rx_frame = await tb.sink.recv() + if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value: + cycles = 0 + while cycles < 100: + cycles += 1 + if not tb.source.idle() or dut.s_axis_tvalid.value.integer or dut.m_axis_tvalid.value.integer or dut.status_depth.value.integer: + cycles = 0 + await RisingEdge(dut.clk) - assert rx_frame.tdata == test_frame.tdata - assert rx_frame.tid == test_frame.tid - assert rx_frame.tdest == test_frame.tdest - assert not rx_frame.tuser + while not tb.sink.empty(): + rx_frame = await tb.sink.recv() + + if dut.MARK_WHEN_FULL.value and rx_frame.tuser: + continue + + assert not rx_frame.tuser + + while True: + test_frame = test_frames.pop(0) + if rx_frame.tid == test_frame.tid and rx_frame.tdest == test_frame.tdest and rx_frame.tdata == test_frame.tdata: + break + + assert len(test_frames) < 512 + + else: + for test_frame in test_frames: + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_frame.tdata + assert rx_frame.tid == test_frame.tid + assert rx_frame.tdest == test_frame.tdest + assert not rx_frame.tuser assert tb.sink.empty() @@ -294,7 +425,9 @@ if cocotb.SIM_NAME: run_test_tuser_assert, run_test_init_sink_pause, run_test_init_sink_pause_reset, - run_test_overflow + run_test_pause, + run_test_overflow, + run_test_oversize ]: factory = TestFactory(test) @@ -312,11 +445,15 @@ tests_dir = os.path.dirname(__file__) rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame", "drop_when_full"), - [(0, 0, 0, 0), (1, 0, 0, 0), (1, 1, 0, 0), (1, 1, 1, 0)]) +@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame", + "drop_when_full", "mark_when_full"), + [(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0), + (1, 1, 1, 1, 0), (0, 0, 0, 0, 1)]) @pytest.mark.parametrize("m_data_width", [8, 16, 32]) @pytest.mark.parametrize("s_data_width", [8, 16, 32]) -def test_axis_fifo_adapter(request, s_data_width, m_data_width, frame_fifo, drop_oversize_frame, drop_bad_frame, drop_when_full): +def test_axis_fifo_adapter(request, s_data_width, m_data_width, + frame_fifo, drop_oversize_frame, drop_bad_frame, + drop_when_full, mark_when_full): dut = "axis_fifo_adapter" module = os.path.splitext(os.path.basename(__file__))[0] toplevel = dut @@ -329,13 +466,13 @@ def test_axis_fifo_adapter(request, s_data_width, m_data_width, frame_fifo, drop parameters = {} - parameters['DEPTH'] = 1024 parameters['S_DATA_WIDTH'] = s_data_width parameters['S_KEEP_ENABLE'] = int(parameters['S_DATA_WIDTH'] > 8) parameters['S_KEEP_WIDTH'] = (parameters['S_DATA_WIDTH'] + 7) // 8 parameters['M_DATA_WIDTH'] = m_data_width parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8) parameters['M_KEEP_WIDTH'] = (parameters['M_DATA_WIDTH'] + 7) // 8 + parameters['DEPTH'] = 1024 * max(parameters['S_KEEP_WIDTH'], parameters['M_KEEP_WIDTH']) parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 parameters['DEST_ENABLE'] = 1 @@ -350,6 +487,9 @@ def test_axis_fifo_adapter(request, s_data_width, m_data_width, frame_fifo, drop parameters['DROP_OVERSIZE_FRAME'] = drop_oversize_frame parameters['DROP_BAD_FRAME'] = drop_bad_frame parameters['DROP_WHEN_FULL'] = drop_when_full + parameters['MARK_WHEN_FULL'] = mark_when_full + parameters['PAUSE_ENABLE'] = 1 + parameters['FRAME_PAUSE'] = 1 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/fpga/lib/eth/rtl/arp_eth_rx.v b/fpga/lib/eth/rtl/arp_eth_rx.v index 1bac60c6f..bfc74b1ef 100644 --- a/fpga/lib/eth/rtl/arp_eth_rx.v +++ b/fpga/lib/eth/rtl/arp_eth_rx.v @@ -86,15 +86,19 @@ module arp_eth_rx # output wire error_invalid_header ); -parameter CYCLE_COUNT = (28+KEEP_WIDTH-1)/KEEP_WIDTH; +parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1; + +parameter HDR_SIZE = 28; + +parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES; parameter PTR_WIDTH = $clog2(CYCLE_COUNT); -parameter OFFSET = 28 % KEEP_WIDTH; +parameter OFFSET = HDR_SIZE % BYTE_LANES; // bus width assertions initial begin - if (KEEP_WIDTH * 8 != DATA_WIDTH) begin + if (BYTE_LANES * 8 != DATA_WIDTH) begin $error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)"); $finish; end @@ -213,8 +217,8 @@ always @* begin ptr_next = ptr_reg + 1; `define _HEADER_FIELD_(offset, field) \ - if (ptr_reg == offset/KEEP_WIDTH && (!KEEP_ENABLE || s_eth_payload_axis_tkeep[offset%KEEP_WIDTH])) begin \ - field = s_eth_payload_axis_tdata[(offset%KEEP_WIDTH)*8 +: 8]; \ + if (ptr_reg == offset/BYTE_LANES && (!KEEP_ENABLE || s_eth_payload_axis_tkeep[offset%BYTE_LANES])) begin \ + field = s_eth_payload_axis_tdata[(offset%BYTE_LANES)*8 +: 8]; \ end `_HEADER_FIELD_(0, m_arp_htype_next[1*8 +: 8]) @@ -246,7 +250,7 @@ always @* begin `_HEADER_FIELD_(26, m_arp_tpa_next[1*8 +: 8]) `_HEADER_FIELD_(27, m_arp_tpa_next[0*8 +: 8]) - if (ptr_reg == 27/KEEP_WIDTH && (!KEEP_ENABLE || s_eth_payload_axis_tkeep[27%KEEP_WIDTH])) begin + if (ptr_reg == 27/BYTE_LANES && (!KEEP_ENABLE || s_eth_payload_axis_tkeep[27%BYTE_LANES])) begin read_arp_header_next = 1'b0; end diff --git a/fpga/lib/eth/rtl/arp_eth_tx.v b/fpga/lib/eth/rtl/arp_eth_tx.v index cd5400505..4fde08a5f 100644 --- a/fpga/lib/eth/rtl/arp_eth_tx.v +++ b/fpga/lib/eth/rtl/arp_eth_tx.v @@ -82,15 +82,19 @@ module arp_eth_tx # output wire busy ); -parameter CYCLE_COUNT = (28+KEEP_WIDTH-1)/KEEP_WIDTH; +parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1; + +parameter HDR_SIZE = 28; + +parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES; parameter PTR_WIDTH = $clog2(CYCLE_COUNT); -parameter OFFSET = 28 % KEEP_WIDTH; +parameter OFFSET = HDR_SIZE % BYTE_LANES; // bus width assertions initial begin - if (KEEP_WIDTH * 8 != DATA_WIDTH) begin + if (BYTE_LANES * 8 != DATA_WIDTH) begin $error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)"); $finish; end @@ -194,9 +198,9 @@ always @* begin m_eth_payload_axis_tuser_int = 1'b0; `define _HEADER_FIELD_(offset, field) \ - if (ptr_reg == offset/KEEP_WIDTH) begin \ - m_eth_payload_axis_tdata_int[(offset%KEEP_WIDTH)*8 +: 8] = field; \ - m_eth_payload_axis_tkeep_int[offset%KEEP_WIDTH] = 1'b1; \ + if (ptr_reg == offset/BYTE_LANES) begin \ + m_eth_payload_axis_tdata_int[(offset%BYTE_LANES)*8 +: 8] = field; \ + m_eth_payload_axis_tkeep_int[offset%BYTE_LANES] = 1'b1; \ end `_HEADER_FIELD_(0, arp_htype_reg[1*8 +: 8]) @@ -228,7 +232,7 @@ always @* begin `_HEADER_FIELD_(26, arp_tpa_reg[1*8 +: 8]) `_HEADER_FIELD_(27, arp_tpa_reg[0*8 +: 8]) - if (ptr_reg == 27/KEEP_WIDTH) begin + if (ptr_reg == 27/BYTE_LANES) begin m_eth_payload_axis_tlast_int = 1'b1; send_arp_header_next = 1'b0; end diff --git a/fpga/lib/eth/rtl/axis_baser_tx_64.v b/fpga/lib/eth/rtl/axis_baser_tx_64.v index d79bfe8f3..3a2523655 100644 --- a/fpga/lib/eth/rtl/axis_baser_tx_64.v +++ b/fpga/lib/eth/rtl/axis_baser_tx_64.v @@ -43,9 +43,10 @@ module axis_baser_tx_64 # parameter PTP_PERIOD_FNS = 16'h6666, parameter PTP_TS_ENABLE = 0, parameter PTP_TS_WIDTH = 96, + parameter PTP_TS_CTRL_IN_TUSER = 0, parameter PTP_TAG_ENABLE = PTP_TS_ENABLE, parameter PTP_TAG_WIDTH = 16, - parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1 + parameter USER_WIDTH = (PTP_TS_ENABLE ? (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + (PTP_TS_CTRL_IN_TUSER ? 1 : 0) : 0) + 1 ) ( input wire clk, @@ -400,31 +401,44 @@ always @* begin // XGMII start and preamble if (swap_lanes_reg) begin // lanes swapped - if (PTP_TS_WIDTH == 96) begin - m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1); - m_axis_ptp_ts_next[95:48] = ptp_ts[95:48]; - m_axis_ptp_ts_tag_next = s_axis_tuser >> 1; - m_axis_ptp_ts_valid_int_next = 1'b1; - end else begin - m_axis_ptp_ts_next = ptp_ts + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1); - m_axis_ptp_ts_tag_next = s_axis_tuser >> 1; - m_axis_ptp_ts_valid_next = 1'b1; + if (PTP_TS_ENABLE) begin + if (PTP_TS_WIDTH == 96) begin + m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1); + m_axis_ptp_ts_next[95:48] = ptp_ts[95:48]; + end else begin + m_axis_ptp_ts_next = ptp_ts + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1); + end end start_packet_next = 2'b10; end else begin // lanes not swapped - if (PTP_TS_WIDTH == 96) begin - m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS); - m_axis_ptp_ts_next[95:48] = ptp_ts[95:48]; - m_axis_ptp_ts_tag_next = s_axis_tuser >> 1; - m_axis_ptp_ts_valid_int_next = 1'b1; - end else begin - m_axis_ptp_ts_next = ptp_ts + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS); - m_axis_ptp_ts_tag_next = s_axis_tuser >> 1; - m_axis_ptp_ts_valid_next = 1'b1; + if (PTP_TS_ENABLE) begin + if (PTP_TS_WIDTH == 96) begin + m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS); + m_axis_ptp_ts_next[95:48] = ptp_ts[95:48]; + end else begin + m_axis_ptp_ts_next = ptp_ts + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS); + end end start_packet_next = 2'b01; end + if (PTP_TS_ENABLE) begin + if (PTP_TS_CTRL_IN_TUSER) begin + m_axis_ptp_ts_tag_next = s_axis_tuser >> 2; + if (PTP_TS_WIDTH == 96) begin + m_axis_ptp_ts_valid_int_next = s_axis_tuser[1]; + end else begin + m_axis_ptp_ts_valid_next = s_axis_tuser[1]; + end + end else begin + m_axis_ptp_ts_tag_next = s_axis_tuser >> 1; + if (PTP_TS_WIDTH == 96) begin + m_axis_ptp_ts_valid_int_next = 1'b1; + end else begin + m_axis_ptp_ts_valid_next = 1'b1; + end + end + end output_data_next = {ETH_SFD, {7{ETH_PRE}}}; output_type_next = OUTPUT_TYPE_START_0; s_axis_tready_next = 1'b1; diff --git a/fpga/lib/eth/rtl/axis_gmii_rx.v b/fpga/lib/eth/rtl/axis_gmii_rx.v index 6203b2b27..64ff1d77f 100644 --- a/fpga/lib/eth/rtl/axis_gmii_rx.v +++ b/fpga/lib/eth/rtl/axis_gmii_rx.v @@ -100,7 +100,7 @@ reg reset_crc; reg update_crc; reg mii_odd = 1'b0; -reg mii_locked = 1'b0; +reg in_frame = 1'b0; reg [DATA_WIDTH-1:0] gmii_rxd_d0 = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] gmii_rxd_d1 = {DATA_WIDTH{1'b0}}; @@ -125,11 +125,12 @@ reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next; reg m_axis_tlast_reg = 1'b0, m_axis_tlast_next; reg m_axis_tuser_reg = 1'b0, m_axis_tuser_next; -reg start_packet_reg = 1'b0, start_packet_next; +reg start_packet_int_reg = 1'b0; +reg start_packet_reg = 1'b0; reg error_bad_frame_reg = 1'b0, error_bad_frame_next; reg error_bad_fcs_reg = 1'b0, error_bad_fcs_next; -reg [PTP_TS_WIDTH-1:0] ptp_ts_reg = 0, ptp_ts_next; +reg [PTP_TS_WIDTH-1:0] ptp_ts_reg = 0; reg [31:0] crc_state = 32'hFFFFFFFF; wire [31:0] crc_next; @@ -170,12 +171,9 @@ always @* begin m_axis_tlast_next = 1'b0; m_axis_tuser_next = 1'b0; - start_packet_next = 1'b0; error_bad_frame_next = 1'b0; error_bad_fcs_next = 1'b0; - ptp_ts_next = ptp_ts_reg; - if (!clk_enable) begin // clock disabled - hold state state_next = state_reg; @@ -189,8 +187,6 @@ always @* begin reset_crc = 1'b1; if (gmii_rx_dv_d4 && !gmii_rx_er_d4 && gmii_rxd_d4 == ETH_SFD) begin - ptp_ts_next = ptp_ts; - start_packet_next = 1'b1; state_next = STATE_PAYLOAD; end else begin state_next = STATE_IDLE; @@ -246,21 +242,28 @@ end always @(posedge clk) begin state_reg <= state_next; - ptp_ts_reg <= ptp_ts_next; - m_axis_tdata_reg <= m_axis_tdata_next; m_axis_tvalid_reg <= m_axis_tvalid_next; m_axis_tlast_reg <= m_axis_tlast_next; m_axis_tuser_reg <= m_axis_tuser_next; + start_packet_int_reg <= 1'b0; + start_packet_reg <= 1'b0; + + if (start_packet_int_reg) begin + ptp_ts_reg <= ptp_ts; + start_packet_reg <= 1'b1; + end + if (clk_enable) begin if (mii_select) begin mii_odd <= !mii_odd; - if (mii_locked) begin - mii_locked <= gmii_rx_dv; + if (in_frame) begin + in_frame <= gmii_rx_dv; end else if (gmii_rx_dv && {gmii_rxd[3:0], gmii_rxd_d0[7:4]} == ETH_SFD) begin - mii_locked <= 1'b1; + in_frame <= 1'b1; + start_packet_int_reg <= 1'b1; mii_odd <= 1'b1; end @@ -288,6 +291,13 @@ always @(posedge clk) begin gmii_rx_er_d0 <= gmii_rx_er; end end else begin + if (in_frame) begin + in_frame <= gmii_rx_dv; + end else if (gmii_rx_dv && gmii_rxd == ETH_SFD) begin + in_frame <= 1'b1; + start_packet_int_reg <= 1'b1; + end + gmii_rxd_d0 <= gmii_rxd; gmii_rxd_d1 <= gmii_rxd_d0; gmii_rxd_d2 <= gmii_rxd_d1; @@ -314,7 +324,6 @@ always @(posedge clk) begin crc_state <= crc_next; end - start_packet_reg <= start_packet_next; error_bad_frame_reg <= error_bad_frame_next; error_bad_fcs_reg <= error_bad_fcs_next; @@ -323,11 +332,12 @@ always @(posedge clk) begin m_axis_tvalid_reg <= 1'b0; + start_packet_int_reg <= 1'b0; start_packet_reg <= 1'b0; error_bad_frame_reg <= 1'b0; error_bad_fcs_reg <= 1'b0; - mii_locked <= 1'b0; + in_frame <= 1'b0; mii_odd <= 1'b0; gmii_rx_dv_d0 <= 1'b0; diff --git a/fpga/lib/eth/rtl/axis_gmii_tx.v b/fpga/lib/eth/rtl/axis_gmii_tx.v index b731ebd90..36c4c210c 100644 --- a/fpga/lib/eth/rtl/axis_gmii_tx.v +++ b/fpga/lib/eth/rtl/axis_gmii_tx.v @@ -38,9 +38,10 @@ module axis_gmii_tx # parameter MIN_FRAME_LENGTH = 64, parameter PTP_TS_ENABLE = 0, parameter PTP_TS_WIDTH = 96, + parameter PTP_TS_CTRL_IN_TUSER = 0, parameter PTP_TAG_ENABLE = PTP_TS_ENABLE, parameter PTP_TAG_WIDTH = 16, - parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1 + parameter USER_WIDTH = (PTP_TS_ENABLE ? (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + (PTP_TS_CTRL_IN_TUSER ? 1 : 0) : 0) + 1 ) ( input wire clk, @@ -136,6 +137,7 @@ reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_reg = 0, m_axis_ptp_ts_next; reg [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag_reg = 0, m_axis_ptp_ts_tag_next; reg m_axis_ptp_ts_valid_reg = 1'b0, m_axis_ptp_ts_valid_next; +reg start_packet_int_reg = 1'b0, start_packet_int_next; reg start_packet_reg = 1'b0, start_packet_next; reg error_underflow_reg = 1'b0, error_underflow_next; @@ -195,6 +197,18 @@ always @* begin gmii_tx_en_next = 1'b0; gmii_tx_er_next = 1'b0; + if (start_packet_reg && PTP_TS_ENABLE) begin + m_axis_ptp_ts_next = ptp_ts; + if (PTP_TS_CTRL_IN_TUSER) begin + m_axis_ptp_ts_tag_next = s_axis_tuser >> 2; + m_axis_ptp_ts_valid_next = s_axis_tuser[1]; + end else begin + m_axis_ptp_ts_tag_next = s_axis_tuser >> 1; + m_axis_ptp_ts_valid_next = 1'b1; + end + end + + start_packet_int_next = start_packet_int_reg; start_packet_next = 1'b0; error_underflow_next = 1'b0; @@ -211,6 +225,10 @@ always @* begin gmii_tx_en_next = gmii_tx_en_reg; gmii_tx_er_next = gmii_tx_er_reg; state_next = state_reg; + if (start_packet_int_reg) begin + start_packet_int_next = 1'b0; + start_packet_next = 1'b1; + end end else begin case (state_reg) STATE_IDLE: begin @@ -253,10 +271,11 @@ always @* begin s_tdata_next = s_axis_tdata; end gmii_txd_next = ETH_SFD; - m_axis_ptp_ts_next = ptp_ts; - m_axis_ptp_ts_tag_next = s_axis_tuser >> 1; - m_axis_ptp_ts_valid_next = 1'b1; - start_packet_next = 1'b1; + if (mii_select) begin + start_packet_int_next = 1'b1; + end else begin + start_packet_next = 1'b1; + end state_next = STATE_PAYLOAD; end else begin state_next = STATE_PREAMBLE; @@ -427,6 +446,7 @@ always @(posedge clk) begin crc_state <= crc_next; end + start_packet_int_reg <= start_packet_int_next; start_packet_reg <= start_packet_next; error_underflow_reg <= error_underflow_next; @@ -440,6 +460,7 @@ always @(posedge clk) begin gmii_tx_en_reg <= 1'b0; gmii_tx_er_reg <= 1'b0; + start_packet_int_reg <= 1'b0; start_packet_reg <= 1'b0; error_underflow_reg <= 1'b0; end diff --git a/fpga/lib/eth/rtl/axis_xgmii_tx_32.v b/fpga/lib/eth/rtl/axis_xgmii_tx_32.v index 1f87cef24..673438662 100644 --- a/fpga/lib/eth/rtl/axis_xgmii_tx_32.v +++ b/fpga/lib/eth/rtl/axis_xgmii_tx_32.v @@ -41,9 +41,10 @@ module axis_xgmii_tx_32 # parameter MIN_FRAME_LENGTH = 64, parameter PTP_TS_ENABLE = 0, parameter PTP_TS_WIDTH = 96, + parameter PTP_TS_CTRL_IN_TUSER = 0, parameter PTP_TAG_ENABLE = PTP_TS_ENABLE, parameter PTP_TAG_WIDTH = 16, - parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1 + parameter USER_WIDTH = (PTP_TS_ENABLE ? (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + (PTP_TS_CTRL_IN_TUSER ? 1 : 0) : 0) + 1 ) ( input wire clk, @@ -276,10 +277,15 @@ always @* begin m_axis_ptp_ts_tag_next = m_axis_ptp_ts_tag_reg; m_axis_ptp_ts_valid_next = 1'b0; - if (start_packet_reg) begin + if (start_packet_reg && PTP_TS_ENABLE) begin m_axis_ptp_ts_next = ptp_ts; - m_axis_ptp_ts_tag_next = s_axis_tuser >> 1; - m_axis_ptp_ts_valid_next = 1'b1; + if (PTP_TS_CTRL_IN_TUSER) begin + m_axis_ptp_ts_tag_next = s_axis_tuser >> 2; + m_axis_ptp_ts_valid_next = s_axis_tuser[1]; + end else begin + m_axis_ptp_ts_tag_next = s_axis_tuser >> 1; + m_axis_ptp_ts_valid_next = 1'b1; + end end // XGMII idle diff --git a/fpga/lib/eth/rtl/axis_xgmii_tx_64.v b/fpga/lib/eth/rtl/axis_xgmii_tx_64.v index 4372c75c8..060ec412d 100644 --- a/fpga/lib/eth/rtl/axis_xgmii_tx_64.v +++ b/fpga/lib/eth/rtl/axis_xgmii_tx_64.v @@ -43,9 +43,10 @@ module axis_xgmii_tx_64 # parameter PTP_PERIOD_FNS = 16'h6666, parameter PTP_TS_ENABLE = 0, parameter PTP_TS_WIDTH = 96, + parameter PTP_TS_CTRL_IN_TUSER = 0, parameter PTP_TAG_ENABLE = PTP_TS_ENABLE, parameter PTP_TAG_WIDTH = 16, - parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1 + parameter USER_WIDTH = (PTP_TS_ENABLE ? (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + (PTP_TS_CTRL_IN_TUSER ? 1 : 0) : 0) + 1 ) ( input wire clk, @@ -347,31 +348,44 @@ always @* begin // XGMII start and preamble if (swap_lanes_reg) begin // lanes swapped - if (PTP_TS_WIDTH == 96) begin - m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1); - m_axis_ptp_ts_next[95:48] = ptp_ts[95:48]; - m_axis_ptp_ts_tag_next = s_axis_tuser >> 1; - m_axis_ptp_ts_valid_int_next = 1'b1; - end else begin - m_axis_ptp_ts_next = ptp_ts + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1); - m_axis_ptp_ts_tag_next = s_axis_tuser >> 1; - m_axis_ptp_ts_valid_next = 1'b1; + if (PTP_TS_ENABLE) begin + if (PTP_TS_WIDTH == 96) begin + m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1); + m_axis_ptp_ts_next[95:48] = ptp_ts[95:48]; + end else begin + m_axis_ptp_ts_next = ptp_ts + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1); + end end start_packet_next = 2'b10; end else begin // lanes not swapped - if (PTP_TS_WIDTH == 96) begin - m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS); - m_axis_ptp_ts_next[95:48] = ptp_ts[95:48]; - m_axis_ptp_ts_tag_next = s_axis_tuser >> 1; - m_axis_ptp_ts_valid_int_next = 1'b1; - end else begin - m_axis_ptp_ts_next = ptp_ts + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS); - m_axis_ptp_ts_tag_next = s_axis_tuser >> 1; - m_axis_ptp_ts_valid_next = 1'b1; + if (PTP_TS_ENABLE) begin + if (PTP_TS_WIDTH == 96) begin + m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS); + m_axis_ptp_ts_next[95:48] = ptp_ts[95:48]; + end else begin + m_axis_ptp_ts_next = ptp_ts + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS); + end end start_packet_next = 2'b01; end + if (PTP_TS_ENABLE) begin + if (PTP_TS_CTRL_IN_TUSER) begin + m_axis_ptp_ts_tag_next = s_axis_tuser >> 2; + if (PTP_TS_WIDTH == 96) begin + m_axis_ptp_ts_valid_int_next = s_axis_tuser[1]; + end else begin + m_axis_ptp_ts_valid_next = s_axis_tuser[1]; + end + end else begin + m_axis_ptp_ts_tag_next = s_axis_tuser >> 1; + if (PTP_TS_WIDTH == 96) begin + m_axis_ptp_ts_valid_int_next = 1'b1; + end else begin + m_axis_ptp_ts_valid_next = 1'b1; + end + end + end xgmii_txd_next = {ETH_SFD, {6{ETH_PRE}}, XGMII_START}; xgmii_txc_next = 8'b00000001; s_axis_tready_next = 1'b1; diff --git a/fpga/lib/eth/rtl/eth_axis_rx.v b/fpga/lib/eth/rtl/eth_axis_rx.v index 3501841d1..bd56e28e4 100644 --- a/fpga/lib/eth/rtl/eth_axis_rx.v +++ b/fpga/lib/eth/rtl/eth_axis_rx.v @@ -77,15 +77,19 @@ module eth_axis_rx # output wire error_header_early_termination ); -parameter CYCLE_COUNT = (14+KEEP_WIDTH-1)/KEEP_WIDTH; +parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1; + +parameter HDR_SIZE = 14; + +parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES; parameter PTR_WIDTH = $clog2(CYCLE_COUNT); -parameter OFFSET = 14 % KEEP_WIDTH; +parameter OFFSET = HDR_SIZE % BYTE_LANES; // bus width assertions initial begin - if (KEEP_WIDTH * 8 != DATA_WIDTH) begin + if (BYTE_LANES * 8 != DATA_WIDTH) begin $error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)"); $finish; end @@ -213,8 +217,8 @@ always @* begin ptr_next = ptr_reg + 1; `define _HEADER_FIELD_(offset, field) \ - if (ptr_reg == offset/KEEP_WIDTH && (!KEEP_ENABLE || s_axis_tkeep[offset%KEEP_WIDTH])) begin \ - field = s_axis_tdata[(offset%KEEP_WIDTH)*8 +: 8]; \ + if (ptr_reg == offset/BYTE_LANES && (!KEEP_ENABLE || s_axis_tkeep[offset%BYTE_LANES])) begin \ + field = s_axis_tdata[(offset%BYTE_LANES)*8 +: 8]; \ end `_HEADER_FIELD_(0, m_eth_dest_mac_next[5*8 +: 8]) @@ -232,7 +236,7 @@ always @* begin `_HEADER_FIELD_(12, m_eth_type_next[1*8 +: 8]) `_HEADER_FIELD_(13, m_eth_type_next[0*8 +: 8]) - if (ptr_reg == 13/KEEP_WIDTH && (!KEEP_ENABLE || s_axis_tkeep[13%KEEP_WIDTH])) begin + if (ptr_reg == 13/BYTE_LANES && (!KEEP_ENABLE || s_axis_tkeep[13%BYTE_LANES])) begin if (!shift_axis_tlast) begin m_eth_hdr_valid_next = 1'b1; read_eth_header_next = 1'b0; diff --git a/fpga/lib/eth/rtl/eth_axis_tx.v b/fpga/lib/eth/rtl/eth_axis_tx.v index fa742a62b..28c73b73b 100644 --- a/fpga/lib/eth/rtl/eth_axis_tx.v +++ b/fpga/lib/eth/rtl/eth_axis_tx.v @@ -76,15 +76,19 @@ module eth_axis_tx # output wire busy ); -parameter CYCLE_COUNT = (14+KEEP_WIDTH-1)/KEEP_WIDTH; +parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1; + +parameter HDR_SIZE = 14; + +parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES; parameter PTR_WIDTH = $clog2(CYCLE_COUNT); -parameter OFFSET = 14 % KEEP_WIDTH; +parameter OFFSET = HDR_SIZE % BYTE_LANES; // bus width assertions initial begin - if (KEEP_WIDTH * 8 != DATA_WIDTH) begin + if (BYTE_LANES * 8 != DATA_WIDTH) begin $error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)"); $finish; end @@ -238,9 +242,9 @@ always @* begin m_axis_tvalid_int = 1'b1; `define _HEADER_FIELD_(offset, field) \ - if (ptr_reg == offset/KEEP_WIDTH) begin \ - m_axis_tdata_int[(offset%KEEP_WIDTH)*8 +: 8] = field; \ - m_axis_tkeep_int[offset%KEEP_WIDTH] = 1'b1; \ + if (ptr_reg == offset/BYTE_LANES) begin \ + m_axis_tdata_int[(offset%BYTE_LANES)*8 +: 8] = field; \ + m_axis_tkeep_int[offset%BYTE_LANES] = 1'b1; \ end `_HEADER_FIELD_(0, eth_dest_mac_reg[5*8 +: 8]) @@ -258,7 +262,7 @@ always @* begin `_HEADER_FIELD_(12, eth_type_reg[1*8 +: 8]) `_HEADER_FIELD_(13, eth_type_reg[0*8 +: 8]) - if (ptr_reg == 13/KEEP_WIDTH) begin + if (ptr_reg == 13/BYTE_LANES) begin if (!send_eth_payload_reg) begin s_eth_payload_axis_tready_next = m_axis_tready_int_early; send_eth_payload_next = 1'b1; diff --git a/fpga/lib/eth/rtl/eth_mac_10g.v b/fpga/lib/eth/rtl/eth_mac_10g.v index 46a57433d..b34b91d2b 100644 --- a/fpga/lib/eth/rtl/eth_mac_10g.v +++ b/fpga/lib/eth/rtl/eth_mac_10g.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2015-2018 Alex Forencich +Copyright (c) 2015-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -43,12 +43,15 @@ module eth_mac_10g # parameter PTP_PERIOD_FNS = 16'h6666, parameter TX_PTP_TS_ENABLE = 0, parameter TX_PTP_TS_WIDTH = 96, + parameter TX_PTP_TS_CTRL_IN_TUSER = 0, parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE, parameter TX_PTP_TAG_WIDTH = 16, - parameter RX_PTP_TS_ENABLE = 0, + parameter RX_PTP_TS_ENABLE = TX_PTP_TS_ENABLE, parameter RX_PTP_TS_WIDTH = 96, - parameter TX_USER_WIDTH = (TX_PTP_TS_ENABLE && TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1, - parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1 + parameter TX_USER_WIDTH = (TX_PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + (TX_PTP_TS_CTRL_IN_TUSER ? 1 : 0) : 0) + 1, + parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1, + parameter PFC_ENABLE = 0, + parameter PAUSE_ENABLE = PFC_ENABLE ) ( input wire rx_clk, @@ -92,6 +95,31 @@ module eth_mac_10g # output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag, output wire tx_axis_ptp_ts_valid, + /* + * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) + */ + input wire tx_lfc_req, + input wire tx_lfc_resend, + input wire rx_lfc_en, + output wire rx_lfc_req, + input wire rx_lfc_ack, + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC) + */ + input wire [7:0] tx_pfc_req, + input wire tx_pfc_resend, + input wire [7:0] rx_pfc_en, + output wire [7:0] rx_pfc_req, + input wire [7:0] rx_pfc_ack, + + /* + * Pause interface + */ + input wire tx_lfc_pause_en, + input wire tx_pause_req, + output wire tx_pause_ack, + /* * Status */ @@ -100,13 +128,65 @@ module eth_mac_10g # output wire [1:0] rx_start_packet, output wire rx_error_bad_frame, output wire rx_error_bad_fcs, + output wire stat_tx_mcf, + output wire stat_rx_mcf, + output wire stat_tx_lfc_pkt, + output wire stat_tx_lfc_xon, + output wire stat_tx_lfc_xoff, + output wire stat_tx_lfc_paused, + output wire stat_tx_pfc_pkt, + output wire [7:0] stat_tx_pfc_xon, + output wire [7:0] stat_tx_pfc_xoff, + output wire [7:0] stat_tx_pfc_paused, + output wire stat_rx_lfc_pkt, + output wire stat_rx_lfc_xon, + output wire stat_rx_lfc_xoff, + output wire stat_rx_lfc_paused, + output wire stat_rx_pfc_pkt, + output wire [7:0] stat_rx_pfc_xon, + output wire [7:0] stat_rx_pfc_xoff, + output wire [7:0] stat_rx_pfc_paused, /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] ifg_delay, + input wire [47:0] cfg_mcf_rx_eth_dst_mcast, + input wire cfg_mcf_rx_check_eth_dst_mcast, + input wire [47:0] cfg_mcf_rx_eth_dst_ucast, + input wire cfg_mcf_rx_check_eth_dst_ucast, + input wire [47:0] cfg_mcf_rx_eth_src, + input wire cfg_mcf_rx_check_eth_src, + input wire [15:0] cfg_mcf_rx_eth_type, + input wire [15:0] cfg_mcf_rx_opcode_lfc, + input wire cfg_mcf_rx_check_opcode_lfc, + input wire [15:0] cfg_mcf_rx_opcode_pfc, + input wire cfg_mcf_rx_check_opcode_pfc, + input wire cfg_mcf_rx_forward, + input wire cfg_mcf_rx_enable, + input wire [47:0] cfg_tx_lfc_eth_dst, + input wire [47:0] cfg_tx_lfc_eth_src, + input wire [15:0] cfg_tx_lfc_eth_type, + input wire [15:0] cfg_tx_lfc_opcode, + input wire cfg_tx_lfc_en, + input wire [15:0] cfg_tx_lfc_quanta, + input wire [15:0] cfg_tx_lfc_refresh, + input wire [47:0] cfg_tx_pfc_eth_dst, + input wire [47:0] cfg_tx_pfc_eth_src, + input wire [15:0] cfg_tx_pfc_eth_type, + input wire [15:0] cfg_tx_pfc_opcode, + input wire cfg_tx_pfc_en, + input wire [8*16-1:0] cfg_tx_pfc_quanta, + input wire [8*16-1:0] cfg_tx_pfc_refresh, + input wire [15:0] cfg_rx_lfc_opcode, + input wire cfg_rx_lfc_en, + input wire [15:0] cfg_rx_pfc_opcode, + input wire cfg_rx_pfc_en ); +parameter MAC_CTRL_ENABLE = PAUSE_ENABLE || PFC_ENABLE; +parameter TX_USER_WIDTH_INT = MAC_CTRL_ENABLE ? (TX_PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1 : 0) + 1 : TX_USER_WIDTH; + // bus width assertions initial begin if (DATA_WIDTH != 32 && DATA_WIDTH != 64) begin @@ -120,6 +200,19 @@ initial begin end end +wire [DATA_WIDTH-1:0] tx_axis_tdata_int; +wire [KEEP_WIDTH-1:0] tx_axis_tkeep_int; +wire tx_axis_tvalid_int; +wire tx_axis_tready_int; +wire tx_axis_tlast_int; +wire [TX_USER_WIDTH_INT-1:0] tx_axis_tuser_int; + +wire [DATA_WIDTH-1:0] rx_axis_tdata_int; +wire [KEEP_WIDTH-1:0] rx_axis_tkeep_int; +wire rx_axis_tvalid_int; +wire rx_axis_tlast_int; +wire [RX_USER_WIDTH-1:0] rx_axis_tuser_int; + generate if (DATA_WIDTH == 64) begin @@ -139,11 +232,11 @@ axis_xgmii_rx_inst ( .rst(rx_rst), .xgmii_rxd(xgmii_rxd), .xgmii_rxc(xgmii_rxc), - .m_axis_tdata(rx_axis_tdata), - .m_axis_tkeep(rx_axis_tkeep), - .m_axis_tvalid(rx_axis_tvalid), - .m_axis_tlast(rx_axis_tlast), - .m_axis_tuser(rx_axis_tuser), + .m_axis_tdata(rx_axis_tdata_int), + .m_axis_tkeep(rx_axis_tkeep_int), + .m_axis_tvalid(rx_axis_tvalid_int), + .m_axis_tlast(rx_axis_tlast_int), + .m_axis_tuser(rx_axis_tuser_int), .ptp_ts(rx_ptp_ts), .start_packet(rx_start_packet), .error_bad_frame(rx_error_bad_frame), @@ -161,19 +254,20 @@ axis_xgmii_tx_64 #( .PTP_PERIOD_FNS(PTP_PERIOD_FNS), .PTP_TS_ENABLE(TX_PTP_TS_ENABLE), .PTP_TS_WIDTH(TX_PTP_TS_WIDTH), + .PTP_TS_CTRL_IN_TUSER(MAC_CTRL_ENABLE ? TX_PTP_TS_ENABLE : TX_PTP_TS_CTRL_IN_TUSER), .PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE), .PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH), - .USER_WIDTH(TX_USER_WIDTH) + .USER_WIDTH(TX_USER_WIDTH_INT) ) axis_xgmii_tx_inst ( .clk(tx_clk), .rst(tx_rst), - .s_axis_tdata(tx_axis_tdata), - .s_axis_tkeep(tx_axis_tkeep), - .s_axis_tvalid(tx_axis_tvalid), - .s_axis_tready(tx_axis_tready), - .s_axis_tlast(tx_axis_tlast), - .s_axis_tuser(tx_axis_tuser), + .s_axis_tdata(tx_axis_tdata_int), + .s_axis_tkeep(tx_axis_tkeep_int), + .s_axis_tvalid(tx_axis_tvalid_int), + .s_axis_tready(tx_axis_tready_int), + .s_axis_tlast(tx_axis_tlast_int), + .s_axis_tuser(tx_axis_tuser_int), .xgmii_txd(xgmii_txd), .xgmii_txc(xgmii_txc), .ptp_ts(tx_ptp_ts), @@ -200,11 +294,11 @@ axis_xgmii_rx_inst ( .rst(rx_rst), .xgmii_rxd(xgmii_rxd), .xgmii_rxc(xgmii_rxc), - .m_axis_tdata(rx_axis_tdata), - .m_axis_tkeep(rx_axis_tkeep), - .m_axis_tvalid(rx_axis_tvalid), - .m_axis_tlast(rx_axis_tlast), - .m_axis_tuser(rx_axis_tuser), + .m_axis_tdata(rx_axis_tdata_int), + .m_axis_tkeep(rx_axis_tkeep_int), + .m_axis_tvalid(rx_axis_tvalid_int), + .m_axis_tlast(rx_axis_tlast_int), + .m_axis_tuser(rx_axis_tuser_int), .ptp_ts(rx_ptp_ts), .start_packet(rx_start_packet[0]), .error_bad_frame(rx_error_bad_frame), @@ -222,19 +316,20 @@ axis_xgmii_tx_32 #( .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .PTP_TS_ENABLE(TX_PTP_TS_ENABLE), .PTP_TS_WIDTH(TX_PTP_TS_WIDTH), + .PTP_TS_CTRL_IN_TUSER(MAC_CTRL_ENABLE ? TX_PTP_TS_ENABLE : TX_PTP_TS_CTRL_IN_TUSER), .PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE), .PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH), - .USER_WIDTH(TX_USER_WIDTH) + .USER_WIDTH(TX_USER_WIDTH_INT) ) axis_xgmii_tx_inst ( .clk(tx_clk), .rst(tx_rst), - .s_axis_tdata(tx_axis_tdata), - .s_axis_tkeep(tx_axis_tkeep), - .s_axis_tvalid(tx_axis_tvalid), - .s_axis_tready(tx_axis_tready), - .s_axis_tlast(tx_axis_tlast), - .s_axis_tuser(tx_axis_tuser), + .s_axis_tdata(tx_axis_tdata_int), + .s_axis_tkeep(tx_axis_tkeep_int), + .s_axis_tvalid(tx_axis_tvalid_int), + .s_axis_tready(tx_axis_tready_int), + .s_axis_tlast(tx_axis_tlast_int), + .s_axis_tuser(tx_axis_tuser_int), .xgmii_txd(xgmii_txd), .xgmii_txc(xgmii_txc), .ptp_ts(tx_ptp_ts), @@ -242,13 +337,392 @@ axis_xgmii_tx_inst ( .m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag), .m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid), .ifg_delay(ifg_delay), - .start_packet(tx_start_packet[0]) + .start_packet(tx_start_packet[0]), + .error_underflow(tx_error_underflow) ); assign tx_start_packet[1] = 1'b0; end +if (MAC_CTRL_ENABLE) begin : mac_ctrl + + localparam MCF_PARAMS_SIZE = PFC_ENABLE ? 18 : 2; + + wire tx_mcf_valid; + wire tx_mcf_ready; + wire [47:0] tx_mcf_eth_dst; + wire [47:0] tx_mcf_eth_src; + wire [15:0] tx_mcf_eth_type; + wire [15:0] tx_mcf_opcode; + wire [MCF_PARAMS_SIZE*8-1:0] tx_mcf_params; + + wire rx_mcf_valid; + wire [47:0] rx_mcf_eth_dst; + wire [47:0] rx_mcf_eth_src; + wire [15:0] rx_mcf_eth_type; + wire [15:0] rx_mcf_opcode; + wire [MCF_PARAMS_SIZE*8-1:0] rx_mcf_params; + + // terminate LFC pause requests from RX internally on TX side + wire tx_pause_req_int; + wire rx_lfc_ack_int; + + reg tx_lfc_req_sync_reg_1 = 1'b0; + reg tx_lfc_req_sync_reg_2 = 1'b0; + reg tx_lfc_req_sync_reg_3 = 1'b0; + + always @(posedge rx_clk or posedge rx_rst) begin + if (rx_rst) begin + tx_lfc_req_sync_reg_1 <= 1'b0; + end else begin + tx_lfc_req_sync_reg_1 <= rx_lfc_req; + end + end + + always @(posedge tx_clk or posedge tx_rst) begin + if (tx_rst) begin + tx_lfc_req_sync_reg_2 <= 1'b0; + tx_lfc_req_sync_reg_3 <= 1'b0; + end else begin + tx_lfc_req_sync_reg_2 <= tx_lfc_req_sync_reg_1; + tx_lfc_req_sync_reg_3 <= tx_lfc_req_sync_reg_2; + end + end + + reg rx_lfc_ack_sync_reg_1 = 1'b0; + reg rx_lfc_ack_sync_reg_2 = 1'b0; + reg rx_lfc_ack_sync_reg_3 = 1'b0; + + always @(posedge tx_clk or posedge tx_rst) begin + if (tx_rst) begin + rx_lfc_ack_sync_reg_1 <= 1'b0; + end else begin + rx_lfc_ack_sync_reg_1 <= tx_lfc_pause_en ? tx_pause_ack : 0; + end + end + + always @(posedge rx_clk or posedge rx_rst) begin + if (rx_rst) begin + rx_lfc_ack_sync_reg_2 <= 1'b0; + rx_lfc_ack_sync_reg_3 <= 1'b0; + end else begin + rx_lfc_ack_sync_reg_2 <= rx_lfc_ack_sync_reg_1; + rx_lfc_ack_sync_reg_3 <= rx_lfc_ack_sync_reg_2; + end + end + + assign tx_pause_req_int = tx_pause_req || (tx_lfc_pause_en ? tx_lfc_req_sync_reg_3 : 0); + + assign rx_lfc_ack_int = rx_lfc_ack || rx_lfc_ack_sync_reg_3; + + // handle PTP TS enable bit in tuser + wire [TX_USER_WIDTH_INT-1:0] tx_axis_tuser_in; + + if (TX_PTP_TS_ENABLE && !TX_PTP_TS_CTRL_IN_TUSER) begin + assign tx_axis_tuser_in = {tx_axis_tuser[TX_USER_WIDTH-1:1], 1'b1, tx_axis_tuser[0]}; + end else begin + assign tx_axis_tuser_in = tx_axis_tuser; + end + + mac_ctrl_tx #( + .DATA_WIDTH(DATA_WIDTH), + .KEEP_ENABLE(1), + .KEEP_WIDTH(KEEP_WIDTH), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(TX_USER_WIDTH_INT), + .MCF_PARAMS_SIZE(MCF_PARAMS_SIZE) + ) + mac_ctrl_tx_inst ( + .clk(tx_clk), + .rst(tx_rst), + + /* + * AXI stream input + */ + .s_axis_tdata(tx_axis_tdata), + .s_axis_tkeep(tx_axis_tkeep), + .s_axis_tvalid(tx_axis_tvalid), + .s_axis_tready(tx_axis_tready), + .s_axis_tlast(tx_axis_tlast), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(tx_axis_tuser_in), + + /* + * AXI stream output + */ + .m_axis_tdata(tx_axis_tdata_int), + .m_axis_tkeep(tx_axis_tkeep_int), + .m_axis_tvalid(tx_axis_tvalid_int), + .m_axis_tready(tx_axis_tready_int), + .m_axis_tlast(tx_axis_tlast_int), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(tx_axis_tuser_int), + + /* + * MAC control frame interface + */ + .mcf_valid(tx_mcf_valid), + .mcf_ready(tx_mcf_ready), + .mcf_eth_dst(tx_mcf_eth_dst), + .mcf_eth_src(tx_mcf_eth_src), + .mcf_eth_type(tx_mcf_eth_type), + .mcf_opcode(tx_mcf_opcode), + .mcf_params(tx_mcf_params), + .mcf_id(0), + .mcf_dest(0), + .mcf_user(0), + + /* + * Pause interface + */ + .tx_pause_req(tx_pause_req_int), + .tx_pause_ack(tx_pause_ack), + + /* + * Status + */ + .stat_tx_mcf(stat_tx_mcf) + ); + + mac_ctrl_rx #( + .DATA_WIDTH(DATA_WIDTH), + .KEEP_ENABLE(1), + .KEEP_WIDTH(KEEP_WIDTH), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(RX_USER_WIDTH), + .USE_READY(0), + .MCF_PARAMS_SIZE(MCF_PARAMS_SIZE) + ) + mac_ctrl_rx_inst ( + .clk(rx_clk), + .rst(rx_rst), + + /* + * AXI stream input + */ + .s_axis_tdata(rx_axis_tdata_int), + .s_axis_tkeep(rx_axis_tkeep_int), + .s_axis_tvalid(rx_axis_tvalid_int), + .s_axis_tready(), + .s_axis_tlast(rx_axis_tlast_int), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(rx_axis_tuser_int), + + /* + * AXI stream output + */ + .m_axis_tdata(rx_axis_tdata), + .m_axis_tkeep(rx_axis_tkeep), + .m_axis_tvalid(rx_axis_tvalid), + .m_axis_tready(1'b1), + .m_axis_tlast(rx_axis_tlast), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(rx_axis_tuser), + + /* + * MAC control frame interface + */ + .mcf_valid(rx_mcf_valid), + .mcf_eth_dst(rx_mcf_eth_dst), + .mcf_eth_src(rx_mcf_eth_src), + .mcf_eth_type(rx_mcf_eth_type), + .mcf_opcode(rx_mcf_opcode), + .mcf_params(rx_mcf_params), + .mcf_id(), + .mcf_dest(), + .mcf_user(), + + /* + * Configuration + */ + .cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast), + .cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast), + .cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast), + .cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast), + .cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src), + .cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src), + .cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type), + .cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc), + .cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc), + .cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc), + .cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc && PFC_ENABLE), + .cfg_mcf_rx_forward(cfg_mcf_rx_forward), + .cfg_mcf_rx_enable(cfg_mcf_rx_enable), + + /* + * Status + */ + .stat_rx_mcf(stat_rx_mcf) + ); + + mac_pause_ctrl_tx #( + .MCF_PARAMS_SIZE(MCF_PARAMS_SIZE), + .PFC_ENABLE(PFC_ENABLE) + ) + mac_pause_ctrl_tx_inst ( + .clk(tx_clk), + .rst(tx_rst), + + /* + * MAC control frame interface + */ + .mcf_valid(tx_mcf_valid), + .mcf_ready(tx_mcf_ready), + .mcf_eth_dst(tx_mcf_eth_dst), + .mcf_eth_src(tx_mcf_eth_src), + .mcf_eth_type(tx_mcf_eth_type), + .mcf_opcode(tx_mcf_opcode), + .mcf_params(tx_mcf_params), + + /* + * Pause (IEEE 802.3 annex 31B) + */ + .tx_lfc_req(tx_lfc_req), + .tx_lfc_resend(tx_lfc_resend), + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D) + */ + .tx_pfc_req(tx_pfc_req), + .tx_pfc_resend(tx_pfc_resend), + + /* + * Configuration + */ + .cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst), + .cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src), + .cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type), + .cfg_tx_lfc_opcode(cfg_tx_lfc_opcode), + .cfg_tx_lfc_en(cfg_tx_lfc_en), + .cfg_tx_lfc_quanta(cfg_tx_lfc_quanta), + .cfg_tx_lfc_refresh(cfg_tx_lfc_refresh), + .cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst), + .cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src), + .cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type), + .cfg_tx_pfc_opcode(cfg_tx_pfc_opcode), + .cfg_tx_pfc_en(cfg_tx_pfc_en), + .cfg_tx_pfc_quanta(cfg_tx_pfc_quanta), + .cfg_tx_pfc_refresh(cfg_tx_pfc_refresh), + .cfg_quanta_step((DATA_WIDTH*256)/512), + .cfg_quanta_clk_en(1'b1), + + /* + * Status + */ + .stat_tx_lfc_pkt(stat_tx_lfc_pkt), + .stat_tx_lfc_xon(stat_tx_lfc_xon), + .stat_tx_lfc_xoff(stat_tx_lfc_xoff), + .stat_tx_lfc_paused(stat_tx_lfc_paused), + .stat_tx_pfc_pkt(stat_tx_pfc_pkt), + .stat_tx_pfc_xon(stat_tx_pfc_xon), + .stat_tx_pfc_xoff(stat_tx_pfc_xoff), + .stat_tx_pfc_paused(stat_tx_pfc_paused) + ); + + mac_pause_ctrl_rx #( + .MCF_PARAMS_SIZE(18), + .PFC_ENABLE(PFC_ENABLE) + ) + mac_pause_ctrl_rx_inst ( + .clk(rx_clk), + .rst(rx_rst), + + /* + * MAC control frame interface + */ + .mcf_valid(rx_mcf_valid), + .mcf_eth_dst(rx_mcf_eth_dst), + .mcf_eth_src(rx_mcf_eth_src), + .mcf_eth_type(rx_mcf_eth_type), + .mcf_opcode(rx_mcf_opcode), + .mcf_params(rx_mcf_params), + + /* + * Pause (IEEE 802.3 annex 31B) + */ + .rx_lfc_en(rx_lfc_en), + .rx_lfc_req(rx_lfc_req), + .rx_lfc_ack(rx_lfc_ack_int), + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D) + */ + .rx_pfc_en(rx_pfc_en), + .rx_pfc_req(rx_pfc_req), + .rx_pfc_ack(rx_pfc_ack), + + /* + * Configuration + */ + .cfg_rx_lfc_opcode(cfg_rx_lfc_opcode), + .cfg_rx_lfc_en(cfg_rx_lfc_en), + .cfg_rx_pfc_opcode(cfg_rx_pfc_opcode), + .cfg_rx_pfc_en(cfg_rx_pfc_en), + .cfg_quanta_step((DATA_WIDTH*256)/512), + .cfg_quanta_clk_en(1'b1), + + /* + * Status + */ + .stat_rx_lfc_pkt(stat_rx_lfc_pkt), + .stat_rx_lfc_xon(stat_rx_lfc_xon), + .stat_rx_lfc_xoff(stat_rx_lfc_xoff), + .stat_rx_lfc_paused(stat_rx_lfc_paused), + .stat_rx_pfc_pkt(stat_rx_pfc_pkt), + .stat_rx_pfc_xon(stat_rx_pfc_xon), + .stat_rx_pfc_xoff(stat_rx_pfc_xoff), + .stat_rx_pfc_paused(stat_rx_pfc_paused) + ); + +end else begin + + assign tx_axis_tdata_int = tx_axis_tdata; + assign tx_axis_tkeep_int = tx_axis_tkeep; + assign tx_axis_tvalid_int = tx_axis_tvalid; + assign tx_axis_tready = tx_axis_tready_int; + assign tx_axis_tlast_int = tx_axis_tlast; + assign tx_axis_tuser_int = tx_axis_tuser; + + assign rx_axis_tdata = rx_axis_tdata_int; + assign rx_axis_tkeep = rx_axis_tkeep_int; + assign rx_axis_tvalid = rx_axis_tvalid_int; + assign rx_axis_tlast = rx_axis_tlast_int; + assign rx_axis_tuser = rx_axis_tuser_int; + + assign rx_lfc_req = 0; + assign rx_pfc_req = 0; + assign tx_pause_ack = 0; + + assign stat_tx_mcf = 0; + assign stat_rx_mcf = 0; + assign stat_tx_lfc_pkt = 0; + assign stat_tx_lfc_xon = 0; + assign stat_tx_lfc_xoff = 0; + assign stat_tx_lfc_paused = 0; + assign stat_tx_pfc_pkt = 0; + assign stat_tx_pfc_xon = 0; + assign stat_tx_pfc_xoff = 0; + assign stat_tx_pfc_paused = 0; + assign stat_rx_lfc_pkt = 0; + assign stat_rx_lfc_xon = 0; + assign stat_rx_lfc_xoff = 0; + assign stat_rx_lfc_paused = 0; + assign stat_rx_pfc_pkt = 0; + assign stat_rx_pfc_xon = 0; + assign stat_rx_pfc_xoff = 0; + assign stat_rx_pfc_paused = 0; + +end + endgenerate endmodule diff --git a/fpga/lib/eth/rtl/eth_mac_10g_fifo.v b/fpga/lib/eth/rtl/eth_mac_10g_fifo.v index f98fff1ac..a99b968b8 100644 --- a/fpga/lib/eth/rtl/eth_mac_10g_fifo.v +++ b/fpga/lib/eth/rtl/eth_mac_10g_fifo.v @@ -57,12 +57,13 @@ module eth_mac_10g_fifo # parameter PTP_PERIOD_FNS = 16'h6666, parameter PTP_USE_SAMPLE_CLOCK = 0, parameter TX_PTP_TS_ENABLE = 0, - parameter RX_PTP_TS_ENABLE = 0, + parameter RX_PTP_TS_ENABLE = TX_PTP_TS_ENABLE, + parameter TX_PTP_TS_CTRL_IN_TUSER = 0, parameter TX_PTP_TS_FIFO_DEPTH = 64, parameter PTP_TS_WIDTH = 96, - parameter TX_PTP_TAG_ENABLE = 0, + parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE, parameter PTP_TAG_WIDTH = 16, - parameter TX_USER_WIDTH = (TX_PTP_TS_ENABLE && TX_PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1, + parameter TX_USER_WIDTH = (TX_PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + (TX_PTP_TS_CTRL_IN_TUSER ? 1 : 0) : 0) + 1, parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1 ) ( @@ -339,6 +340,7 @@ eth_mac_10g #( .PTP_PERIOD_FNS(PTP_PERIOD_FNS), .TX_PTP_TS_ENABLE(TX_PTP_TS_ENABLE), .TX_PTP_TS_WIDTH(PTP_TS_WIDTH), + .TX_PTP_TS_CTRL_IN_TUSER(TX_PTP_TS_CTRL_IN_TUSER), .TX_PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE), .TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH), .RX_PTP_TS_ENABLE(RX_PTP_TS_ENABLE), diff --git a/fpga/lib/eth/rtl/eth_mac_1g.v b/fpga/lib/eth/rtl/eth_mac_1g.v index d94f77472..2f3c3605f 100644 --- a/fpga/lib/eth/rtl/eth_mac_1g.v +++ b/fpga/lib/eth/rtl/eth_mac_1g.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2015-2018 Alex Forencich +Copyright (c) 2015-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -38,12 +38,15 @@ module eth_mac_1g # parameter MIN_FRAME_LENGTH = 64, parameter TX_PTP_TS_ENABLE = 0, parameter TX_PTP_TS_WIDTH = 96, + parameter TX_PTP_TS_CTRL_IN_TUSER = 0, parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE, parameter TX_PTP_TAG_WIDTH = 16, - parameter RX_PTP_TS_ENABLE = 0, + parameter RX_PTP_TS_ENABLE = TX_PTP_TS_ENABLE, parameter RX_PTP_TS_WIDTH = 96, - parameter TX_USER_WIDTH = (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1, - parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1 + parameter TX_USER_WIDTH = (TX_PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + (TX_PTP_TS_CTRL_IN_TUSER ? 1 : 0) : 0) + 1, + parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1, + parameter PFC_ENABLE = 0, + parameter PAUSE_ENABLE = PFC_ENABLE ) ( input wire rx_clk, @@ -87,6 +90,31 @@ module eth_mac_1g # output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag, output wire tx_axis_ptp_ts_valid, + /* + * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) + */ + input wire tx_lfc_req, + input wire tx_lfc_resend, + input wire rx_lfc_en, + output wire rx_lfc_req, + input wire rx_lfc_ack, + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC) + */ + input wire [7:0] tx_pfc_req, + input wire tx_pfc_resend, + input wire [7:0] rx_pfc_en, + output wire [7:0] rx_pfc_req, + input wire [7:0] rx_pfc_ack, + + /* + * Pause interface + */ + input wire tx_lfc_pause_en, + input wire tx_pause_req, + output wire tx_pause_ack, + /* * Control */ @@ -103,13 +131,76 @@ module eth_mac_1g # output wire rx_start_packet, output wire rx_error_bad_frame, output wire rx_error_bad_fcs, + output wire stat_tx_mcf, + output wire stat_rx_mcf, + output wire stat_tx_lfc_pkt, + output wire stat_tx_lfc_xon, + output wire stat_tx_lfc_xoff, + output wire stat_tx_lfc_paused, + output wire stat_tx_pfc_pkt, + output wire [7:0] stat_tx_pfc_xon, + output wire [7:0] stat_tx_pfc_xoff, + output wire [7:0] stat_tx_pfc_paused, + output wire stat_rx_lfc_pkt, + output wire stat_rx_lfc_xon, + output wire stat_rx_lfc_xoff, + output wire stat_rx_lfc_paused, + output wire stat_rx_pfc_pkt, + output wire [7:0] stat_rx_pfc_xon, + output wire [7:0] stat_rx_pfc_xoff, + output wire [7:0] stat_rx_pfc_paused, /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] ifg_delay, + input wire [47:0] cfg_mcf_rx_eth_dst_mcast, + input wire cfg_mcf_rx_check_eth_dst_mcast, + input wire [47:0] cfg_mcf_rx_eth_dst_ucast, + input wire cfg_mcf_rx_check_eth_dst_ucast, + input wire [47:0] cfg_mcf_rx_eth_src, + input wire cfg_mcf_rx_check_eth_src, + input wire [15:0] cfg_mcf_rx_eth_type, + input wire [15:0] cfg_mcf_rx_opcode_lfc, + input wire cfg_mcf_rx_check_opcode_lfc, + input wire [15:0] cfg_mcf_rx_opcode_pfc, + input wire cfg_mcf_rx_check_opcode_pfc, + input wire cfg_mcf_rx_forward, + input wire cfg_mcf_rx_enable, + input wire [47:0] cfg_tx_lfc_eth_dst, + input wire [47:0] cfg_tx_lfc_eth_src, + input wire [15:0] cfg_tx_lfc_eth_type, + input wire [15:0] cfg_tx_lfc_opcode, + input wire cfg_tx_lfc_en, + input wire [15:0] cfg_tx_lfc_quanta, + input wire [15:0] cfg_tx_lfc_refresh, + input wire [47:0] cfg_tx_pfc_eth_dst, + input wire [47:0] cfg_tx_pfc_eth_src, + input wire [15:0] cfg_tx_pfc_eth_type, + input wire [15:0] cfg_tx_pfc_opcode, + input wire cfg_tx_pfc_en, + input wire [8*16-1:0] cfg_tx_pfc_quanta, + input wire [8*16-1:0] cfg_tx_pfc_refresh, + input wire [15:0] cfg_rx_lfc_opcode, + input wire cfg_rx_lfc_en, + input wire [15:0] cfg_rx_pfc_opcode, + input wire cfg_rx_pfc_en ); +parameter MAC_CTRL_ENABLE = PAUSE_ENABLE || PFC_ENABLE; +parameter TX_USER_WIDTH_INT = MAC_CTRL_ENABLE ? (TX_PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1 : 0) + 1 : TX_USER_WIDTH; + +wire [DATA_WIDTH-1:0] tx_axis_tdata_int; +wire tx_axis_tvalid_int; +wire tx_axis_tready_int; +wire tx_axis_tlast_int; +wire [TX_USER_WIDTH_INT-1:0] tx_axis_tuser_int; + +wire [DATA_WIDTH-1:0] rx_axis_tdata_int; +wire rx_axis_tvalid_int; +wire rx_axis_tlast_int; +wire [RX_USER_WIDTH-1:0] rx_axis_tuser_int; + axis_gmii_rx #( .DATA_WIDTH(DATA_WIDTH), .PTP_TS_ENABLE(RX_PTP_TS_ENABLE), @@ -122,10 +213,10 @@ axis_gmii_rx_inst ( .gmii_rxd(gmii_rxd), .gmii_rx_dv(gmii_rx_dv), .gmii_rx_er(gmii_rx_er), - .m_axis_tdata(rx_axis_tdata), - .m_axis_tvalid(rx_axis_tvalid), - .m_axis_tlast(rx_axis_tlast), - .m_axis_tuser(rx_axis_tuser), + .m_axis_tdata(rx_axis_tdata_int), + .m_axis_tvalid(rx_axis_tvalid_int), + .m_axis_tlast(rx_axis_tlast_int), + .m_axis_tuser(rx_axis_tuser_int), .ptp_ts(rx_ptp_ts), .clk_enable(rx_clk_enable), .mii_select(rx_mii_select), @@ -140,18 +231,19 @@ axis_gmii_tx #( .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .PTP_TS_ENABLE(TX_PTP_TS_ENABLE), .PTP_TS_WIDTH(TX_PTP_TS_WIDTH), + .PTP_TS_CTRL_IN_TUSER(MAC_CTRL_ENABLE ? TX_PTP_TS_ENABLE : TX_PTP_TS_CTRL_IN_TUSER), .PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE), .PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH), - .USER_WIDTH(TX_USER_WIDTH) + .USER_WIDTH(TX_USER_WIDTH_INT) ) axis_gmii_tx_inst ( .clk(tx_clk), .rst(tx_rst), - .s_axis_tdata(tx_axis_tdata), - .s_axis_tvalid(tx_axis_tvalid), - .s_axis_tready(tx_axis_tready), - .s_axis_tlast(tx_axis_tlast), - .s_axis_tuser(tx_axis_tuser), + .s_axis_tdata(tx_axis_tdata_int), + .s_axis_tvalid(tx_axis_tvalid_int), + .s_axis_tready(tx_axis_tready_int), + .s_axis_tlast(tx_axis_tlast_int), + .s_axis_tuser(tx_axis_tuser_int), .gmii_txd(gmii_txd), .gmii_tx_en(gmii_tx_en), .gmii_tx_er(gmii_tx_er), @@ -166,6 +258,384 @@ axis_gmii_tx_inst ( .error_underflow(tx_error_underflow) ); +generate + +if (MAC_CTRL_ENABLE) begin : mac_ctrl + + localparam MCF_PARAMS_SIZE = PFC_ENABLE ? 18 : 2; + + wire tx_mcf_valid; + wire tx_mcf_ready; + wire [47:0] tx_mcf_eth_dst; + wire [47:0] tx_mcf_eth_src; + wire [15:0] tx_mcf_eth_type; + wire [15:0] tx_mcf_opcode; + wire [MCF_PARAMS_SIZE*8-1:0] tx_mcf_params; + + wire rx_mcf_valid; + wire [47:0] rx_mcf_eth_dst; + wire [47:0] rx_mcf_eth_src; + wire [15:0] rx_mcf_eth_type; + wire [15:0] rx_mcf_opcode; + wire [MCF_PARAMS_SIZE*8-1:0] rx_mcf_params; + + // terminate LFC pause requests from RX internally on TX side + wire tx_pause_req_int; + wire rx_lfc_ack_int; + + reg tx_lfc_req_sync_reg_1 = 1'b0; + reg tx_lfc_req_sync_reg_2 = 1'b0; + reg tx_lfc_req_sync_reg_3 = 1'b0; + + always @(posedge rx_clk or posedge rx_rst) begin + if (rx_rst) begin + tx_lfc_req_sync_reg_1 <= 1'b0; + end else begin + tx_lfc_req_sync_reg_1 <= rx_lfc_req; + end + end + + always @(posedge tx_clk or posedge tx_rst) begin + if (tx_rst) begin + tx_lfc_req_sync_reg_2 <= 1'b0; + tx_lfc_req_sync_reg_3 <= 1'b0; + end else begin + tx_lfc_req_sync_reg_2 <= tx_lfc_req_sync_reg_1; + tx_lfc_req_sync_reg_3 <= tx_lfc_req_sync_reg_2; + end + end + + reg rx_lfc_ack_sync_reg_1 = 1'b0; + reg rx_lfc_ack_sync_reg_2 = 1'b0; + reg rx_lfc_ack_sync_reg_3 = 1'b0; + + always @(posedge tx_clk or posedge tx_rst) begin + if (tx_rst) begin + rx_lfc_ack_sync_reg_1 <= 1'b0; + end else begin + rx_lfc_ack_sync_reg_1 <= tx_lfc_pause_en ? tx_pause_ack : 0; + end + end + + always @(posedge rx_clk or posedge rx_rst) begin + if (rx_rst) begin + rx_lfc_ack_sync_reg_2 <= 1'b0; + rx_lfc_ack_sync_reg_3 <= 1'b0; + end else begin + rx_lfc_ack_sync_reg_2 <= rx_lfc_ack_sync_reg_1; + rx_lfc_ack_sync_reg_3 <= rx_lfc_ack_sync_reg_2; + end + end + + assign tx_pause_req_int = tx_pause_req || (tx_lfc_pause_en ? tx_lfc_req_sync_reg_3 : 0); + + assign rx_lfc_ack_int = rx_lfc_ack || rx_lfc_ack_sync_reg_3; + + // handle PTP TS enable bit in tuser + wire [TX_USER_WIDTH_INT-1:0] tx_axis_tuser_in; + + if (TX_PTP_TS_ENABLE && !TX_PTP_TS_CTRL_IN_TUSER) begin + assign tx_axis_tuser_in = {tx_axis_tuser[TX_USER_WIDTH-1:1], 1'b1, tx_axis_tuser[0]}; + end else begin + assign tx_axis_tuser_in = tx_axis_tuser; + end + + mac_ctrl_tx #( + .DATA_WIDTH(DATA_WIDTH), + .KEEP_ENABLE(0), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(TX_USER_WIDTH_INT), + .MCF_PARAMS_SIZE(MCF_PARAMS_SIZE) + ) + mac_ctrl_tx_inst ( + .clk(tx_clk), + .rst(tx_rst), + + /* + * AXI stream input + */ + .s_axis_tdata(tx_axis_tdata), + .s_axis_tkeep(1'b1), + .s_axis_tvalid(tx_axis_tvalid), + .s_axis_tready(tx_axis_tready), + .s_axis_tlast(tx_axis_tlast), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(tx_axis_tuser_in), + + /* + * AXI stream output + */ + .m_axis_tdata(tx_axis_tdata_int), + .m_axis_tkeep(), + .m_axis_tvalid(tx_axis_tvalid_int), + .m_axis_tready(tx_axis_tready_int), + .m_axis_tlast(tx_axis_tlast_int), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(tx_axis_tuser_int), + + /* + * MAC control frame interface + */ + .mcf_valid(tx_mcf_valid), + .mcf_ready(tx_mcf_ready), + .mcf_eth_dst(tx_mcf_eth_dst), + .mcf_eth_src(tx_mcf_eth_src), + .mcf_eth_type(tx_mcf_eth_type), + .mcf_opcode(tx_mcf_opcode), + .mcf_params(tx_mcf_params), + .mcf_id(0), + .mcf_dest(0), + .mcf_user(0), + + /* + * Pause interface + */ + .tx_pause_req(tx_pause_req_int), + .tx_pause_ack(tx_pause_ack), + + /* + * Status + */ + .stat_tx_mcf(stat_tx_mcf) + ); + + mac_ctrl_rx #( + .DATA_WIDTH(DATA_WIDTH), + .KEEP_ENABLE(0), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(RX_USER_WIDTH), + .USE_READY(0), + .MCF_PARAMS_SIZE(MCF_PARAMS_SIZE) + ) + mac_ctrl_rx_inst ( + .clk(rx_clk), + .rst(rx_rst), + + /* + * AXI stream input + */ + .s_axis_tdata(rx_axis_tdata_int), + .s_axis_tkeep(1'b1), + .s_axis_tvalid(rx_axis_tvalid_int), + .s_axis_tready(), + .s_axis_tlast(rx_axis_tlast_int), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(rx_axis_tuser_int), + + /* + * AXI stream output + */ + .m_axis_tdata(rx_axis_tdata), + .m_axis_tkeep(), + .m_axis_tvalid(rx_axis_tvalid), + .m_axis_tready(1'b1), + .m_axis_tlast(rx_axis_tlast), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(rx_axis_tuser), + + /* + * MAC control frame interface + */ + .mcf_valid(rx_mcf_valid), + .mcf_eth_dst(rx_mcf_eth_dst), + .mcf_eth_src(rx_mcf_eth_src), + .mcf_eth_type(rx_mcf_eth_type), + .mcf_opcode(rx_mcf_opcode), + .mcf_params(rx_mcf_params), + .mcf_id(), + .mcf_dest(), + .mcf_user(), + + /* + * Configuration + */ + .cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast), + .cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast), + .cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast), + .cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast), + .cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src), + .cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src), + .cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type), + .cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc), + .cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc), + .cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc), + .cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc), + .cfg_mcf_rx_forward(cfg_mcf_rx_forward), + .cfg_mcf_rx_enable(cfg_mcf_rx_enable), + + /* + * Status + */ + .stat_rx_mcf(stat_rx_mcf) + ); + + mac_pause_ctrl_tx #( + .MCF_PARAMS_SIZE(MCF_PARAMS_SIZE), + .PFC_ENABLE(PFC_ENABLE) + ) + mac_pause_ctrl_tx_inst ( + .clk(tx_clk), + .rst(tx_rst), + + /* + * MAC control frame interface + */ + .mcf_valid(tx_mcf_valid), + .mcf_ready(tx_mcf_ready), + .mcf_eth_dst(tx_mcf_eth_dst), + .mcf_eth_src(tx_mcf_eth_src), + .mcf_eth_type(tx_mcf_eth_type), + .mcf_opcode(tx_mcf_opcode), + .mcf_params(tx_mcf_params), + + /* + * Pause (IEEE 802.3 annex 31B) + */ + .tx_lfc_req(tx_lfc_req), + .tx_lfc_resend(tx_lfc_resend), + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D) + */ + .tx_pfc_req(tx_pfc_req), + .tx_pfc_resend(tx_pfc_resend), + + /* + * Configuration + */ + .cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst), + .cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src), + .cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type), + .cfg_tx_lfc_opcode(cfg_tx_lfc_opcode), + .cfg_tx_lfc_en(cfg_tx_lfc_en), + .cfg_tx_lfc_quanta(cfg_tx_lfc_quanta), + .cfg_tx_lfc_refresh(cfg_tx_lfc_refresh), + .cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst), + .cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src), + .cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type), + .cfg_tx_pfc_opcode(cfg_tx_pfc_opcode), + .cfg_tx_pfc_en(cfg_tx_pfc_en), + .cfg_tx_pfc_quanta(cfg_tx_pfc_quanta), + .cfg_tx_pfc_refresh(cfg_tx_pfc_refresh), + .cfg_quanta_step(tx_mii_select ? (4*256)/512 : (8*256)/512), + .cfg_quanta_clk_en(tx_clk_enable), + + /* + * Status + */ + .stat_tx_lfc_pkt(stat_tx_lfc_pkt), + .stat_tx_lfc_xon(stat_tx_lfc_xon), + .stat_tx_lfc_xoff(stat_tx_lfc_xoff), + .stat_tx_lfc_paused(stat_tx_lfc_paused), + .stat_tx_pfc_pkt(stat_tx_pfc_pkt), + .stat_tx_pfc_xon(stat_tx_pfc_xon), + .stat_tx_pfc_xoff(stat_tx_pfc_xoff), + .stat_tx_pfc_paused(stat_tx_pfc_paused) + ); + + mac_pause_ctrl_rx #( + .MCF_PARAMS_SIZE(18), + .PFC_ENABLE(PFC_ENABLE) + ) + mac_pause_ctrl_rx_inst ( + .clk(rx_clk), + .rst(rx_rst), + + /* + * MAC control frame interface + */ + .mcf_valid(rx_mcf_valid), + .mcf_eth_dst(rx_mcf_eth_dst), + .mcf_eth_src(rx_mcf_eth_src), + .mcf_eth_type(rx_mcf_eth_type), + .mcf_opcode(rx_mcf_opcode), + .mcf_params(rx_mcf_params), + + /* + * Pause (IEEE 802.3 annex 31B) + */ + .rx_lfc_en(rx_lfc_en), + .rx_lfc_req(rx_lfc_req), + .rx_lfc_ack(rx_lfc_ack_int), + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D) + */ + .rx_pfc_en(rx_pfc_en), + .rx_pfc_req(rx_pfc_req), + .rx_pfc_ack(rx_pfc_ack), + + /* + * Configuration + */ + .cfg_rx_lfc_opcode(cfg_rx_lfc_opcode), + .cfg_rx_lfc_en(cfg_rx_lfc_en), + .cfg_rx_pfc_opcode(cfg_rx_pfc_opcode), + .cfg_rx_pfc_en(cfg_rx_pfc_en), + .cfg_quanta_step(rx_mii_select ? (4*256)/512 : (8*256)/512), + .cfg_quanta_clk_en(rx_clk_enable), + + /* + * Status + */ + .stat_rx_lfc_pkt(stat_rx_lfc_pkt), + .stat_rx_lfc_xon(stat_rx_lfc_xon), + .stat_rx_lfc_xoff(stat_rx_lfc_xoff), + .stat_rx_lfc_paused(stat_rx_lfc_paused), + .stat_rx_pfc_pkt(stat_rx_pfc_pkt), + .stat_rx_pfc_xon(stat_rx_pfc_xon), + .stat_rx_pfc_xoff(stat_rx_pfc_xoff), + .stat_rx_pfc_paused(stat_rx_pfc_paused) + ); + +end else begin + + assign tx_axis_tdata_int = tx_axis_tdata; + assign tx_axis_tvalid_int = tx_axis_tvalid; + assign tx_axis_tready = tx_axis_tready_int; + assign tx_axis_tlast_int = tx_axis_tlast; + assign tx_axis_tuser_int = tx_axis_tuser; + + assign rx_axis_tdata = rx_axis_tdata_int; + assign rx_axis_tvalid = rx_axis_tvalid_int; + assign rx_axis_tlast = rx_axis_tlast_int; + assign rx_axis_tuser = rx_axis_tuser_int; + + assign rx_lfc_req = 0; + assign rx_pfc_req = 0; + assign tx_pause_ack = 0; + + assign stat_tx_mcf = 0; + assign stat_rx_mcf = 0; + assign stat_tx_lfc_pkt = 0; + assign stat_tx_lfc_xon = 0; + assign stat_tx_lfc_xoff = 0; + assign stat_tx_lfc_paused = 0; + assign stat_tx_pfc_pkt = 0; + assign stat_tx_pfc_xon = 0; + assign stat_tx_pfc_xoff = 0; + assign stat_tx_pfc_paused = 0; + assign stat_rx_lfc_pkt = 0; + assign stat_rx_lfc_xon = 0; + assign stat_rx_lfc_xoff = 0; + assign stat_rx_lfc_paused = 0; + assign stat_rx_pfc_pkt = 0; + assign stat_rx_pfc_xon = 0; + assign stat_rx_pfc_xoff = 0; + assign stat_rx_pfc_paused = 0; + +end + +endgenerate + endmodule `resetall diff --git a/fpga/lib/eth/rtl/eth_mac_phy_10g.v b/fpga/lib/eth/rtl/eth_mac_phy_10g.v index 6145b60e5..46267b7f6 100644 --- a/fpga/lib/eth/rtl/eth_mac_phy_10g.v +++ b/fpga/lib/eth/rtl/eth_mac_phy_10g.v @@ -43,11 +43,12 @@ module eth_mac_phy_10g # parameter PTP_PERIOD_FNS = 16'h6666, parameter TX_PTP_TS_ENABLE = 0, parameter TX_PTP_TS_WIDTH = 96, + parameter TX_PTP_TS_CTRL_IN_TUSER = 0, parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE, parameter TX_PTP_TAG_WIDTH = 16, - parameter RX_PTP_TS_ENABLE = 0, + parameter RX_PTP_TS_ENABLE = TX_PTP_TS_ENABLE, parameter RX_PTP_TS_WIDTH = 96, - parameter TX_USER_WIDTH = (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1, + parameter TX_USER_WIDTH = (TX_PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + (TX_PTP_TS_CTRL_IN_TUSER ? 1 : 0) : 0) + 1, parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1, parameter BIT_REVERSE = 0, parameter SCRAMBLER_DISABLE = 0, @@ -176,6 +177,7 @@ eth_mac_phy_10g_tx #( .PTP_PERIOD_FNS(PTP_PERIOD_FNS), .PTP_TS_ENABLE(TX_PTP_TS_ENABLE), .PTP_TS_WIDTH(TX_PTP_TS_WIDTH), + .PTP_TS_CTRL_IN_TUSER(TX_PTP_TS_CTRL_IN_TUSER), .PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE), .PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH), .USER_WIDTH(TX_USER_WIDTH), diff --git a/fpga/lib/eth/rtl/eth_mac_phy_10g_fifo.v b/fpga/lib/eth/rtl/eth_mac_phy_10g_fifo.v index e56c26814..6205cdca1 100644 --- a/fpga/lib/eth/rtl/eth_mac_phy_10g_fifo.v +++ b/fpga/lib/eth/rtl/eth_mac_phy_10g_fifo.v @@ -65,12 +65,13 @@ module eth_mac_phy_10g_fifo # parameter PTP_PERIOD_FNS = 16'h6666, parameter PTP_USE_SAMPLE_CLOCK = 0, parameter TX_PTP_TS_ENABLE = 0, - parameter RX_PTP_TS_ENABLE = 0, + parameter RX_PTP_TS_ENABLE = TX_PTP_TS_ENABLE, + parameter TX_PTP_TS_CTRL_IN_TUSER = 0, parameter TX_PTP_TS_FIFO_DEPTH = 64, parameter PTP_TS_WIDTH = 96, - parameter TX_PTP_TAG_ENABLE = 0, + parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE, parameter PTP_TAG_WIDTH = 16, - parameter TX_USER_WIDTH = (TX_PTP_TS_ENABLE && TX_PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1, + parameter TX_USER_WIDTH = (TX_PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + (TX_PTP_TS_CTRL_IN_TUSER ? 1 : 0) : 0) + 1, parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1 ) ( @@ -368,6 +369,7 @@ eth_mac_phy_10g #( .PTP_PERIOD_FNS(PTP_PERIOD_FNS), .TX_PTP_TS_ENABLE(TX_PTP_TS_ENABLE), .TX_PTP_TS_WIDTH(PTP_TS_WIDTH), + .TX_PTP_TS_CTRL_IN_TUSER(TX_PTP_TS_CTRL_IN_TUSER), .TX_PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE), .TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH), .RX_PTP_TS_ENABLE(RX_PTP_TS_ENABLE), diff --git a/fpga/lib/eth/rtl/eth_mac_phy_10g_tx.v b/fpga/lib/eth/rtl/eth_mac_phy_10g_tx.v index 4e6f55710..38d39c3db 100644 --- a/fpga/lib/eth/rtl/eth_mac_phy_10g_tx.v +++ b/fpga/lib/eth/rtl/eth_mac_phy_10g_tx.v @@ -43,9 +43,10 @@ module eth_mac_phy_10g_tx # parameter PTP_PERIOD_FNS = 16'h6666, parameter PTP_TS_ENABLE = 0, parameter PTP_TS_WIDTH = 96, + parameter PTP_TS_CTRL_IN_TUSER = 0, parameter PTP_TAG_ENABLE = PTP_TS_ENABLE, parameter PTP_TAG_WIDTH = 16, - parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1, + parameter USER_WIDTH = (PTP_TS_ENABLE ? (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + (PTP_TS_CTRL_IN_TUSER ? 1 : 0) : 0) + 1, parameter BIT_REVERSE = 0, parameter SCRAMBLER_DISABLE = 0, parameter PRBS31_ENABLE = 0, @@ -124,6 +125,7 @@ axis_baser_tx_64 #( .PTP_PERIOD_FNS(PTP_PERIOD_FNS), .PTP_TS_ENABLE(PTP_TS_ENABLE), .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_TS_CTRL_IN_TUSER(PTP_TS_CTRL_IN_TUSER), .PTP_TAG_ENABLE(PTP_TAG_ENABLE), .PTP_TAG_WIDTH(PTP_TAG_WIDTH), .USER_WIDTH(USER_WIDTH) diff --git a/fpga/lib/eth/rtl/mac_ctrl_rx.v b/fpga/lib/eth/rtl/mac_ctrl_rx.v new file mode 100644 index 000000000..d0de0dab4 --- /dev/null +++ b/fpga/lib/eth/rtl/mac_ctrl_rx.v @@ -0,0 +1,448 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * MAC control receive + */ +module mac_ctrl_rx # +( + parameter DATA_WIDTH = 8, + parameter KEEP_ENABLE = DATA_WIDTH>8, + parameter KEEP_WIDTH = DATA_WIDTH/8, + parameter ID_ENABLE = 0, + parameter ID_WIDTH = 8, + parameter DEST_ENABLE = 0, + parameter DEST_WIDTH = 8, + parameter USER_ENABLE = 1, + parameter USER_WIDTH = 1, + parameter USE_READY = 0, + parameter MCF_PARAMS_SIZE = 18 +) +( + input wire clk, + input wire rst, + + /* + * AXI stream input + */ + input wire [DATA_WIDTH-1:0] s_axis_tdata, + input wire [KEEP_WIDTH-1:0] s_axis_tkeep, + input wire s_axis_tvalid, + output wire s_axis_tready, + input wire s_axis_tlast, + input wire [ID_WIDTH-1:0] s_axis_tid, + input wire [DEST_WIDTH-1:0] s_axis_tdest, + input wire [USER_WIDTH-1:0] s_axis_tuser, + + /* + * AXI stream output + */ + output wire [DATA_WIDTH-1:0] m_axis_tdata, + output wire [KEEP_WIDTH-1:0] m_axis_tkeep, + output wire m_axis_tvalid, + input wire m_axis_tready, + output wire m_axis_tlast, + output wire [ID_WIDTH-1:0] m_axis_tid, + output wire [DEST_WIDTH-1:0] m_axis_tdest, + output wire [USER_WIDTH-1:0] m_axis_tuser, + + /* + * MAC control frame interface + */ + output wire mcf_valid, + output wire [47:0] mcf_eth_dst, + output wire [47:0] mcf_eth_src, + output wire [15:0] mcf_eth_type, + output wire [15:0] mcf_opcode, + output wire [MCF_PARAMS_SIZE*8-1:0] mcf_params, + output wire [ID_WIDTH-1:0] mcf_id, + output wire [DEST_WIDTH-1:0] mcf_dest, + output wire [USER_WIDTH-1:0] mcf_user, + + /* + * Configuration + */ + input wire [47:0] cfg_mcf_rx_eth_dst_mcast, + input wire cfg_mcf_rx_check_eth_dst_mcast, + input wire [47:0] cfg_mcf_rx_eth_dst_ucast, + input wire cfg_mcf_rx_check_eth_dst_ucast, + input wire [47:0] cfg_mcf_rx_eth_src, + input wire cfg_mcf_rx_check_eth_src, + input wire [15:0] cfg_mcf_rx_eth_type, + input wire [15:0] cfg_mcf_rx_opcode_lfc, + input wire cfg_mcf_rx_check_opcode_lfc, + input wire [15:0] cfg_mcf_rx_opcode_pfc, + input wire cfg_mcf_rx_check_opcode_pfc, + input wire cfg_mcf_rx_forward, + input wire cfg_mcf_rx_enable, + + /* + * Status + */ + output wire stat_rx_mcf +); + +parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1; + +parameter HDR_SIZE = 60; + +parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES; + +parameter PTR_WIDTH = $clog2(CYCLE_COUNT); + +parameter OFFSET = HDR_SIZE % BYTE_LANES; + +// check configuration +initial begin + if (BYTE_LANES * 8 != DATA_WIDTH) begin + $error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)"); + $finish; + end + + if (MCF_PARAMS_SIZE > 44) begin + $error("Error: Maximum MCF_PARAMS_SIZE is 44 bytes (instance %m)"); + $finish; + end +end + +/* + +MAC control frame + + Field Length + Destination MAC address 6 octets [01:80:C2:00:00:01] + Source MAC address 6 octets + Ethertype 2 octets [0x8808] + Opcode 2 octets + Parameters 0-44 octets + +This module manages the reception of MAC control frames. Incoming frames are +checked based on the ethertype and (optionally) MAC addresses. Matching control +frames are marked by setting tuser[0] on the data output and forwarded through +a separate interface for processing. + +*/ + +reg read_mcf_reg = 1'b1, read_mcf_next; +reg mcf_frame_reg = 1'b0, mcf_frame_next; +reg [PTR_WIDTH-1:0] ptr_reg = 0, ptr_next; + +reg s_axis_tready_reg = 1'b0, s_axis_tready_next; + +// internal datapath +reg [DATA_WIDTH-1:0] m_axis_tdata_int; +reg [KEEP_WIDTH-1:0] m_axis_tkeep_int; +reg m_axis_tvalid_int; +reg m_axis_tready_int_reg = 1'b0; +reg m_axis_tlast_int; +reg [ID_WIDTH-1:0] m_axis_tid_int; +reg [DEST_WIDTH-1:0] m_axis_tdest_int; +reg [USER_WIDTH-1:0] m_axis_tuser_int; +wire m_axis_tready_int_early; + +reg mcf_valid_reg = 0, mcf_valid_next; +reg [47:0] mcf_eth_dst_reg = 0, mcf_eth_dst_next; +reg [47:0] mcf_eth_src_reg = 0, mcf_eth_src_next; +reg [15:0] mcf_eth_type_reg = 0, mcf_eth_type_next; +reg [15:0] mcf_opcode_reg = 0, mcf_opcode_next; +reg [MCF_PARAMS_SIZE*8-1:0] mcf_params_reg = 0, mcf_params_next; +reg [ID_WIDTH-1:0] mcf_id_reg = 0, mcf_id_next; +reg [DEST_WIDTH-1:0] mcf_dest_reg = 0, mcf_dest_next; +reg [USER_WIDTH-1:0] mcf_user_reg = 0, mcf_user_next; + +reg stat_rx_mcf_reg = 1'b0, stat_rx_mcf_next; + +assign s_axis_tready = s_axis_tready_reg; + +assign mcf_valid = mcf_valid_reg; +assign mcf_eth_dst = mcf_eth_dst_reg; +assign mcf_eth_src = mcf_eth_src_reg; +assign mcf_eth_type = mcf_eth_type_reg; +assign mcf_opcode = mcf_opcode_reg; +assign mcf_params = mcf_params_reg; +assign mcf_id = mcf_id_reg; +assign mcf_dest = mcf_dest_reg; +assign mcf_user = mcf_user_reg; + +assign stat_rx_mcf = stat_rx_mcf_reg; + +wire mcf_eth_dst_mcast_match = mcf_eth_dst_next == cfg_mcf_rx_eth_dst_mcast; +wire mcf_eth_dst_ucast_match = mcf_eth_dst_next == cfg_mcf_rx_eth_dst_ucast; +wire mcf_eth_src_match = mcf_eth_src_next == cfg_mcf_rx_eth_src; +wire mcf_eth_type_match = mcf_eth_type_next == cfg_mcf_rx_eth_type; +wire mcf_opcode_lfc_match = mcf_opcode_next == cfg_mcf_rx_opcode_lfc; +wire mcf_opcode_pfc_match = mcf_opcode_next == cfg_mcf_rx_opcode_pfc; + +wire mcf_eth_dst_match = ((mcf_eth_dst_mcast_match && cfg_mcf_rx_check_eth_dst_mcast) || + (mcf_eth_dst_ucast_match && cfg_mcf_rx_check_eth_dst_ucast) || + (!cfg_mcf_rx_check_eth_dst_mcast && !cfg_mcf_rx_check_eth_dst_ucast)); + +wire mcf_opcode_match = ((mcf_opcode_lfc_match && cfg_mcf_rx_check_opcode_lfc) || + (mcf_opcode_pfc_match && cfg_mcf_rx_check_opcode_pfc) || + (!cfg_mcf_rx_check_opcode_lfc && !cfg_mcf_rx_check_opcode_pfc)); + +wire mcf_match = (mcf_eth_dst_match && + (mcf_eth_src_match || !cfg_mcf_rx_check_eth_src) && + mcf_eth_type_match && mcf_opcode_match); + +integer k; + +always @* begin + read_mcf_next = read_mcf_reg; + mcf_frame_next = mcf_frame_reg; + ptr_next = ptr_reg; + + // pass through data + m_axis_tdata_int = s_axis_tdata; + m_axis_tkeep_int = s_axis_tkeep; + m_axis_tvalid_int = s_axis_tvalid; + m_axis_tlast_int = s_axis_tlast; + m_axis_tid_int = s_axis_tid; + m_axis_tdest_int = s_axis_tdest; + m_axis_tuser_int = s_axis_tuser; + + s_axis_tready_next = m_axis_tready_int_early || !USE_READY; + + mcf_valid_next = 1'b0; + mcf_eth_dst_next = mcf_eth_dst_reg; + mcf_eth_src_next = mcf_eth_src_reg; + mcf_eth_type_next = mcf_eth_type_reg; + mcf_opcode_next = mcf_opcode_reg; + mcf_params_next = mcf_params_reg; + mcf_id_next = mcf_id_reg; + mcf_dest_next = mcf_dest_reg; + mcf_user_next = mcf_user_reg; + + stat_rx_mcf_next = 1'b0; + + if ((s_axis_tready || !USE_READY) && s_axis_tvalid) begin + if (read_mcf_reg) begin + ptr_next = ptr_reg + 1; + + mcf_id_next = s_axis_tid; + mcf_dest_next = s_axis_tdest; + mcf_user_next = s_axis_tuser; + + `define _HEADER_FIELD_(offset, field) \ + if (ptr_reg == offset/BYTE_LANES) begin \ + field = s_axis_tdata[(offset%BYTE_LANES)*8 +: 8]; \ + end + + `_HEADER_FIELD_(0, mcf_eth_dst_next[5*8 +: 8]) + `_HEADER_FIELD_(1, mcf_eth_dst_next[4*8 +: 8]) + `_HEADER_FIELD_(2, mcf_eth_dst_next[3*8 +: 8]) + `_HEADER_FIELD_(3, mcf_eth_dst_next[2*8 +: 8]) + `_HEADER_FIELD_(4, mcf_eth_dst_next[1*8 +: 8]) + `_HEADER_FIELD_(5, mcf_eth_dst_next[0*8 +: 8]) + `_HEADER_FIELD_(6, mcf_eth_src_next[5*8 +: 8]) + `_HEADER_FIELD_(7, mcf_eth_src_next[4*8 +: 8]) + `_HEADER_FIELD_(8, mcf_eth_src_next[3*8 +: 8]) + `_HEADER_FIELD_(9, mcf_eth_src_next[2*8 +: 8]) + `_HEADER_FIELD_(10, mcf_eth_src_next[1*8 +: 8]) + `_HEADER_FIELD_(11, mcf_eth_src_next[0*8 +: 8]) + `_HEADER_FIELD_(12, mcf_eth_type_next[1*8 +: 8]) + `_HEADER_FIELD_(13, mcf_eth_type_next[0*8 +: 8]) + `_HEADER_FIELD_(14, mcf_opcode_next[1*8 +: 8]) + `_HEADER_FIELD_(15, mcf_opcode_next[0*8 +: 8]) + + if (ptr_reg == 0/BYTE_LANES) begin + // ensure params field gets cleared + mcf_params_next = 0; + end + + for (k = 0; k < MCF_PARAMS_SIZE; k = k + 1) begin + if (ptr_reg == (16+k)/BYTE_LANES) begin + mcf_params_next[k*8 +: 8] = s_axis_tdata[((16+k)%BYTE_LANES)*8 +: 8]; + end + end + + if (ptr_reg == 15/BYTE_LANES && (!KEEP_ENABLE || s_axis_tkeep[13%BYTE_LANES])) begin + // record match at end of opcode field + mcf_frame_next = mcf_match && cfg_mcf_rx_enable; + end + + if (ptr_reg == (HDR_SIZE-1)/BYTE_LANES) begin + read_mcf_next = 1'b0; + end + + `undef _HEADER_FIELD_ + end + + if (s_axis_tlast) begin + if (s_axis_tuser[0]) begin + // frame marked invalid + end else if (mcf_frame_next) begin + if (!cfg_mcf_rx_forward) begin + // mark frame invalid + m_axis_tuser_int[0] = 1'b1; + end + // transfer out MAC control frame + mcf_valid_next = 1'b1; + stat_rx_mcf_next = 1'b1; + end + + read_mcf_next = 1'b1; + mcf_frame_next = 1'b0; + ptr_next = 0; + end + end +end + +always @(posedge clk) begin + read_mcf_reg <= read_mcf_next; + mcf_frame_reg <= mcf_frame_next; + ptr_reg <= ptr_next; + + s_axis_tready_reg <= s_axis_tready_next; + + mcf_valid_reg <= mcf_valid_next; + mcf_eth_dst_reg <= mcf_eth_dst_next; + mcf_eth_src_reg <= mcf_eth_src_next; + mcf_eth_type_reg <= mcf_eth_type_next; + mcf_opcode_reg <= mcf_opcode_next; + mcf_params_reg <= mcf_params_next; + mcf_id_reg <= mcf_id_next; + mcf_dest_reg <= mcf_dest_next; + mcf_user_reg <= mcf_user_next; + + stat_rx_mcf_reg <= stat_rx_mcf_next; + + if (rst) begin + read_mcf_reg <= 1'b1; + mcf_frame_reg <= 1'b0; + ptr_reg <= 0; + s_axis_tready_reg <= 1'b0; + mcf_valid_reg <= 1'b0; + stat_rx_mcf_reg <= 1'b0; + end +end + +// output datapath logic +reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; +reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; +reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next; +reg m_axis_tlast_reg = 1'b0; +reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}}; +reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; +reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}}; + +reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; +reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; +reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next; +reg temp_m_axis_tlast_reg = 1'b0; +reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}}; +reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; +reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}}; + +// datapath control +reg store_axis_int_to_output; +reg store_axis_int_to_temp; +reg store_axis_temp_to_output; + +assign m_axis_tdata = m_axis_tdata_reg; +assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}}; +assign m_axis_tvalid = m_axis_tvalid_reg; +assign m_axis_tlast = m_axis_tlast_reg; +assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; +assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; +assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; + +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_axis_tready_int_early = m_axis_tready || !USE_READY || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int)); + +always @* begin + // transfer sink ready state to source + m_axis_tvalid_next = m_axis_tvalid_reg; + temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg; + + store_axis_int_to_output = 1'b0; + store_axis_int_to_temp = 1'b0; + store_axis_temp_to_output = 1'b0; + + if (m_axis_tready_int_reg) begin + // input is ready + if (m_axis_tready || !USE_READY || !m_axis_tvalid_reg) begin + // output is ready or currently not valid, transfer data to output + m_axis_tvalid_next = m_axis_tvalid_int; + store_axis_int_to_output = 1'b1; + end else begin + // output is not ready, store input in temp + temp_m_axis_tvalid_next = m_axis_tvalid_int; + store_axis_int_to_temp = 1'b1; + end + end else if (m_axis_tready || !USE_READY) begin + // input is not ready, but output is ready + m_axis_tvalid_next = temp_m_axis_tvalid_reg; + temp_m_axis_tvalid_next = 1'b0; + store_axis_temp_to_output = 1'b1; + end +end + +always @(posedge clk) begin + m_axis_tvalid_reg <= m_axis_tvalid_next; + m_axis_tready_int_reg <= m_axis_tready_int_early; + temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next; + + // datapath + if (store_axis_int_to_output) begin + m_axis_tdata_reg <= m_axis_tdata_int; + m_axis_tkeep_reg <= m_axis_tkeep_int; + m_axis_tlast_reg <= m_axis_tlast_int; + m_axis_tid_reg <= m_axis_tid_int; + m_axis_tdest_reg <= m_axis_tdest_int; + m_axis_tuser_reg <= m_axis_tuser_int; + end else if (store_axis_temp_to_output) begin + m_axis_tdata_reg <= temp_m_axis_tdata_reg; + m_axis_tkeep_reg <= temp_m_axis_tkeep_reg; + m_axis_tlast_reg <= temp_m_axis_tlast_reg; + m_axis_tid_reg <= temp_m_axis_tid_reg; + m_axis_tdest_reg <= temp_m_axis_tdest_reg; + m_axis_tuser_reg <= temp_m_axis_tuser_reg; + end + + if (store_axis_int_to_temp) begin + temp_m_axis_tdata_reg <= m_axis_tdata_int; + temp_m_axis_tkeep_reg <= m_axis_tkeep_int; + temp_m_axis_tlast_reg <= m_axis_tlast_int; + temp_m_axis_tid_reg <= m_axis_tid_int; + temp_m_axis_tdest_reg <= m_axis_tdest_int; + temp_m_axis_tuser_reg <= m_axis_tuser_int; + end + + if (rst) begin + m_axis_tvalid_reg <= 1'b0; + m_axis_tready_int_reg <= 1'b0; + temp_m_axis_tvalid_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/fpga/lib/eth/rtl/mac_ctrl_tx.v b/fpga/lib/eth/rtl/mac_ctrl_tx.v new file mode 100644 index 000000000..c06d50aad --- /dev/null +++ b/fpga/lib/eth/rtl/mac_ctrl_tx.v @@ -0,0 +1,421 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * MAC control transmit + */ +module mac_ctrl_tx # +( + parameter DATA_WIDTH = 8, + parameter KEEP_ENABLE = DATA_WIDTH>8, + parameter KEEP_WIDTH = DATA_WIDTH/8, + parameter ID_ENABLE = 0, + parameter ID_WIDTH = 8, + parameter DEST_ENABLE = 0, + parameter DEST_WIDTH = 8, + parameter USER_ENABLE = 1, + parameter USER_WIDTH = 1, + parameter MCF_PARAMS_SIZE = 18 +) +( + input wire clk, + input wire rst, + + /* + * AXI stream input + */ + input wire [DATA_WIDTH-1:0] s_axis_tdata, + input wire [KEEP_WIDTH-1:0] s_axis_tkeep, + input wire s_axis_tvalid, + output wire s_axis_tready, + input wire s_axis_tlast, + input wire [ID_WIDTH-1:0] s_axis_tid, + input wire [DEST_WIDTH-1:0] s_axis_tdest, + input wire [USER_WIDTH-1:0] s_axis_tuser, + + /* + * AXI stream output + */ + output wire [DATA_WIDTH-1:0] m_axis_tdata, + output wire [KEEP_WIDTH-1:0] m_axis_tkeep, + output wire m_axis_tvalid, + input wire m_axis_tready, + output wire m_axis_tlast, + output wire [ID_WIDTH-1:0] m_axis_tid, + output wire [DEST_WIDTH-1:0] m_axis_tdest, + output wire [USER_WIDTH-1:0] m_axis_tuser, + + /* + * MAC control frame interface + */ + input wire mcf_valid, + output wire mcf_ready, + input wire [47:0] mcf_eth_dst, + input wire [47:0] mcf_eth_src, + input wire [15:0] mcf_eth_type, + input wire [15:0] mcf_opcode, + input wire [MCF_PARAMS_SIZE*8-1:0] mcf_params, + input wire [ID_WIDTH-1:0] mcf_id, + input wire [DEST_WIDTH-1:0] mcf_dest, + input wire [USER_WIDTH-1:0] mcf_user, + + /* + * Pause interface + */ + input wire tx_pause_req, + output wire tx_pause_ack, + + /* + * Status + */ + output wire stat_tx_mcf +); + +parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1; + +parameter HDR_SIZE = 60; + +parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES; + +parameter PTR_WIDTH = $clog2(CYCLE_COUNT); + +parameter OFFSET = HDR_SIZE % BYTE_LANES; + +// check configuration +initial begin + if (BYTE_LANES * 8 != DATA_WIDTH) begin + $error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)"); + $finish; + end + + if (MCF_PARAMS_SIZE > 44) begin + $error("Error: Maximum MCF_PARAMS_SIZE is 44 bytes (instance %m)"); + $finish; + end +end + +/* + +MAC control frame + + Field Length + Destination MAC address 6 octets [01:80:C2:00:00:01] + Source MAC address 6 octets + Ethertype 2 octets [0x8808] + Opcode 2 octets + Parameters 0-44 octets + +This module manages the transmission of MAC control frames. Control frames +are accepted in parallel, serialized, and merged at a higher priority with +data traffic. + +*/ + +reg send_data_reg = 1'b0, send_data_next; +reg send_mcf_reg = 1'b0, send_mcf_next; +reg [PTR_WIDTH-1:0] ptr_reg = 0, ptr_next; + +reg s_axis_tready_reg = 1'b0, s_axis_tready_next; +reg mcf_ready_reg = 1'b0, mcf_ready_next; +reg tx_pause_ack_reg = 1'b0, tx_pause_ack_next; +reg stat_tx_mcf_reg = 1'b0, stat_tx_mcf_next; + +// internal datapath +reg [DATA_WIDTH-1:0] m_axis_tdata_int; +reg [KEEP_WIDTH-1:0] m_axis_tkeep_int; +reg m_axis_tvalid_int; +reg m_axis_tready_int_reg = 1'b0; +reg m_axis_tlast_int; +reg [ID_WIDTH-1:0] m_axis_tid_int; +reg [DEST_WIDTH-1:0] m_axis_tdest_int; +reg [USER_WIDTH-1:0] m_axis_tuser_int; +wire m_axis_tready_int_early; + +assign s_axis_tready = s_axis_tready_reg; +assign mcf_ready = mcf_ready_reg; +assign tx_pause_ack = tx_pause_ack_reg; +assign stat_tx_mcf = stat_tx_mcf_reg; + +integer k; + +always @* begin + send_data_next = send_data_reg; + send_mcf_next = send_mcf_reg; + ptr_next = ptr_reg; + + s_axis_tready_next = 1'b0; + mcf_ready_next = 1'b0; + tx_pause_ack_next = tx_pause_ack_reg; + stat_tx_mcf_next = 1'b0; + + m_axis_tdata_int = 0; + m_axis_tkeep_int = 0; + m_axis_tvalid_int = 1'b0; + m_axis_tlast_int = 1'b0; + m_axis_tid_int = 0; + m_axis_tdest_int = 0; + m_axis_tuser_int = 0; + + if (!send_data_reg && !send_mcf_reg) begin + m_axis_tdata_int = s_axis_tdata; + m_axis_tkeep_int = s_axis_tkeep; + m_axis_tvalid_int = 1'b0; + m_axis_tlast_int = s_axis_tlast; + m_axis_tid_int = s_axis_tid; + m_axis_tdest_int = s_axis_tdest; + m_axis_tuser_int = s_axis_tuser; + s_axis_tready_next = m_axis_tready_int_early && !tx_pause_req; + tx_pause_ack_next = tx_pause_req; + if (s_axis_tvalid && s_axis_tready) begin + s_axis_tready_next = m_axis_tready_int_early; + tx_pause_ack_next = 1'b0; + m_axis_tvalid_int = 1'b1; + if (s_axis_tlast) begin + s_axis_tready_next = m_axis_tready_int_early && !mcf_valid && !mcf_ready; + send_data_next = 1'b0; + end else begin + send_data_next = 1'b1; + end + end else if (mcf_valid) begin + s_axis_tready_next = 1'b0; + ptr_next = 0; + send_mcf_next = 1'b1; + mcf_ready_next = (CYCLE_COUNT == 1) && m_axis_tready_int_early; + end + end + + if (send_data_reg) begin + m_axis_tdata_int = s_axis_tdata; + m_axis_tkeep_int = s_axis_tkeep; + m_axis_tvalid_int = 1'b0; + m_axis_tlast_int = s_axis_tlast; + m_axis_tid_int = s_axis_tid; + m_axis_tdest_int = s_axis_tdest; + m_axis_tuser_int = s_axis_tuser; + s_axis_tready_next = m_axis_tready_int_early; + if (s_axis_tvalid && s_axis_tready) begin + m_axis_tvalid_int = 1'b1; + if (s_axis_tlast) begin + s_axis_tready_next = m_axis_tready_int_early && !tx_pause_req; + send_data_next = 1'b0; + if (mcf_valid) begin + s_axis_tready_next = 1'b0; + ptr_next = 0; + send_mcf_next = 1'b1; + mcf_ready_next = (CYCLE_COUNT == 1) && m_axis_tready_int_early; + end + end else begin + send_data_next = 1'b1; + end + end + end + + if (send_mcf_reg) begin + mcf_ready_next = (CYCLE_COUNT == 1 || ptr_reg == CYCLE_COUNT-1) && m_axis_tready_int_early; + if (m_axis_tready_int_reg) begin + ptr_next = ptr_reg + 1; + + m_axis_tvalid_int = 1'b1; + m_axis_tid_int = mcf_id; + m_axis_tdest_int = mcf_dest; + m_axis_tuser_int = mcf_user; + + `define _HEADER_FIELD_(offset, field) \ + if (ptr_reg == offset/BYTE_LANES) begin \ + m_axis_tdata_int[(offset%BYTE_LANES)*8 +: 8] = field; \ + m_axis_tkeep_int[offset%BYTE_LANES] = 1'b1; \ + end + + `_HEADER_FIELD_(0, mcf_eth_dst[5*8 +: 8]) + `_HEADER_FIELD_(1, mcf_eth_dst[4*8 +: 8]) + `_HEADER_FIELD_(2, mcf_eth_dst[3*8 +: 8]) + `_HEADER_FIELD_(3, mcf_eth_dst[2*8 +: 8]) + `_HEADER_FIELD_(4, mcf_eth_dst[1*8 +: 8]) + `_HEADER_FIELD_(5, mcf_eth_dst[0*8 +: 8]) + `_HEADER_FIELD_(6, mcf_eth_src[5*8 +: 8]) + `_HEADER_FIELD_(7, mcf_eth_src[4*8 +: 8]) + `_HEADER_FIELD_(8, mcf_eth_src[3*8 +: 8]) + `_HEADER_FIELD_(9, mcf_eth_src[2*8 +: 8]) + `_HEADER_FIELD_(10, mcf_eth_src[1*8 +: 8]) + `_HEADER_FIELD_(11, mcf_eth_src[0*8 +: 8]) + `_HEADER_FIELD_(12, mcf_eth_type[1*8 +: 8]) + `_HEADER_FIELD_(13, mcf_eth_type[0*8 +: 8]) + `_HEADER_FIELD_(14, mcf_opcode[1*8 +: 8]) + `_HEADER_FIELD_(15, mcf_opcode[0*8 +: 8]) + + for (k = 0; k < HDR_SIZE-16; k = k + 1) begin + if (ptr_reg == (16+k)/BYTE_LANES) begin + if (k < MCF_PARAMS_SIZE) begin + m_axis_tdata_int[((16+k)%BYTE_LANES)*8 +: 8] = mcf_params[k*8 +: 8]; + end else begin + m_axis_tdata_int[((16+k)%BYTE_LANES)*8 +: 8] = 0; + end + m_axis_tkeep_int[(16+k)%BYTE_LANES] = 1'b1; + end + end + + if (ptr_reg == (HDR_SIZE-1)/BYTE_LANES) begin + s_axis_tready_next = m_axis_tready_int_early && !tx_pause_req; + mcf_ready_next = 1'b0; + m_axis_tlast_int = 1'b1; + send_mcf_next = 1'b0; + stat_tx_mcf_next = 1'b1; + end else begin + mcf_ready_next = (ptr_next == CYCLE_COUNT-1) && m_axis_tready_int_early; + end + + `undef _HEADER_FIELD_ + end + end +end + +always @(posedge clk) begin + send_data_reg <= send_data_next; + send_mcf_reg <= send_mcf_next; + ptr_reg <= ptr_next; + + s_axis_tready_reg <= s_axis_tready_next; + mcf_ready_reg <= mcf_ready_next; + tx_pause_ack_reg <= tx_pause_ack_next; + stat_tx_mcf_reg <= stat_tx_mcf_next; + + if (rst) begin + send_data_reg <= 1'b0; + send_mcf_reg <= 1'b0; + ptr_reg <= 0; + s_axis_tready_reg <= 1'b0; + mcf_ready_reg <= 1'b0; + tx_pause_ack_reg <= 1'b0; + stat_tx_mcf_reg <= 1'b0; + end +end + +// output datapath logic +reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; +reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; +reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next; +reg m_axis_tlast_reg = 1'b0; +reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}}; +reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; +reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}}; + +reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; +reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; +reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next; +reg temp_m_axis_tlast_reg = 1'b0; +reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}}; +reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; +reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}}; + +// datapath control +reg store_axis_int_to_output; +reg store_axis_int_to_temp; +reg store_axis_temp_to_output; + +assign m_axis_tdata = m_axis_tdata_reg; +assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}}; +assign m_axis_tvalid = m_axis_tvalid_reg; +assign m_axis_tlast = m_axis_tlast_reg; +assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; +assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; +assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; + +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int)); + +always @* begin + // transfer sink ready state to source + m_axis_tvalid_next = m_axis_tvalid_reg; + temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg; + + store_axis_int_to_output = 1'b0; + store_axis_int_to_temp = 1'b0; + store_axis_temp_to_output = 1'b0; + + if (m_axis_tready_int_reg) begin + // input is ready + if (m_axis_tready || !m_axis_tvalid_reg) begin + // output is ready or currently not valid, transfer data to output + m_axis_tvalid_next = m_axis_tvalid_int; + store_axis_int_to_output = 1'b1; + end else begin + // output is not ready, store input in temp + temp_m_axis_tvalid_next = m_axis_tvalid_int; + store_axis_int_to_temp = 1'b1; + end + end else if (m_axis_tready) begin + // input is not ready, but output is ready + m_axis_tvalid_next = temp_m_axis_tvalid_reg; + temp_m_axis_tvalid_next = 1'b0; + store_axis_temp_to_output = 1'b1; + end +end + +always @(posedge clk) begin + m_axis_tvalid_reg <= m_axis_tvalid_next; + m_axis_tready_int_reg <= m_axis_tready_int_early; + temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next; + + // datapath + if (store_axis_int_to_output) begin + m_axis_tdata_reg <= m_axis_tdata_int; + m_axis_tkeep_reg <= m_axis_tkeep_int; + m_axis_tlast_reg <= m_axis_tlast_int; + m_axis_tid_reg <= m_axis_tid_int; + m_axis_tdest_reg <= m_axis_tdest_int; + m_axis_tuser_reg <= m_axis_tuser_int; + end else if (store_axis_temp_to_output) begin + m_axis_tdata_reg <= temp_m_axis_tdata_reg; + m_axis_tkeep_reg <= temp_m_axis_tkeep_reg; + m_axis_tlast_reg <= temp_m_axis_tlast_reg; + m_axis_tid_reg <= temp_m_axis_tid_reg; + m_axis_tdest_reg <= temp_m_axis_tdest_reg; + m_axis_tuser_reg <= temp_m_axis_tuser_reg; + end + + if (store_axis_int_to_temp) begin + temp_m_axis_tdata_reg <= m_axis_tdata_int; + temp_m_axis_tkeep_reg <= m_axis_tkeep_int; + temp_m_axis_tlast_reg <= m_axis_tlast_int; + temp_m_axis_tid_reg <= m_axis_tid_int; + temp_m_axis_tdest_reg <= m_axis_tdest_int; + temp_m_axis_tuser_reg <= m_axis_tuser_int; + end + + if (rst) begin + m_axis_tvalid_reg <= 1'b0; + m_axis_tready_int_reg <= 1'b0; + temp_m_axis_tvalid_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/fpga/lib/eth/rtl/mac_pause_ctrl_rx.v b/fpga/lib/eth/rtl/mac_pause_ctrl_rx.v new file mode 100644 index 000000000..5bff45f7b --- /dev/null +++ b/fpga/lib/eth/rtl/mac_pause_ctrl_rx.v @@ -0,0 +1,221 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * PFC and pause frame receive handling + */ +module mac_pause_ctrl_rx # +( + parameter MCF_PARAMS_SIZE = 18, + parameter PFC_ENABLE = 1 +) +( + input wire clk, + input wire rst, + + /* + * MAC control frame interface + */ + input wire mcf_valid, + input wire [47:0] mcf_eth_dst, + input wire [47:0] mcf_eth_src, + input wire [15:0] mcf_eth_type, + input wire [15:0] mcf_opcode, + input wire [MCF_PARAMS_SIZE*8-1:0] mcf_params, + + /* + * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) + */ + input wire rx_lfc_en, + output wire rx_lfc_req, + input wire rx_lfc_ack, + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC) + */ + input wire [7:0] rx_pfc_en, + output wire [7:0] rx_pfc_req, + input wire [7:0] rx_pfc_ack, + + /* + * Configuration + */ + input wire [15:0] cfg_rx_lfc_opcode, + input wire cfg_rx_lfc_en, + input wire [15:0] cfg_rx_pfc_opcode, + input wire cfg_rx_pfc_en, + input wire [9:0] cfg_quanta_step, + input wire cfg_quanta_clk_en, + + /* + * Status + */ + output wire stat_rx_lfc_pkt, + output wire stat_rx_lfc_xon, + output wire stat_rx_lfc_xoff, + output wire stat_rx_lfc_paused, + output wire stat_rx_pfc_pkt, + output wire [7:0] stat_rx_pfc_xon, + output wire [7:0] stat_rx_pfc_xoff, + output wire [7:0] stat_rx_pfc_paused +); + +localparam QFB = 8; + +// check configuration +initial begin + if (MCF_PARAMS_SIZE < (PFC_ENABLE ? 18 : 2)) begin + $error("Error: MCF_PARAMS_SIZE too small for requested configuration (instance %m)"); + $finish; + end +end + +reg lfc_req_reg = 1'b0, lfc_req_next; +reg [7:0] pfc_req_reg = 8'd0, pfc_req_next; + +reg [16+QFB-1:0] lfc_quanta_reg = 0, lfc_quanta_next; +reg [16+QFB-1:0] pfc_quanta_reg[0:7], pfc_quanta_next[0:7]; + +reg stat_rx_lfc_pkt_reg = 1'b0, stat_rx_lfc_pkt_next; +reg stat_rx_lfc_xon_reg = 1'b0, stat_rx_lfc_xon_next; +reg stat_rx_lfc_xoff_reg = 1'b0, stat_rx_lfc_xoff_next; +reg stat_rx_pfc_pkt_reg = 1'b0, stat_rx_pfc_pkt_next; +reg [7:0] stat_rx_pfc_xon_reg = 0, stat_rx_pfc_xon_next; +reg [7:0] stat_rx_pfc_xoff_reg = 0, stat_rx_pfc_xoff_next; + +assign rx_lfc_req = lfc_req_reg; +assign rx_pfc_req = pfc_req_reg; + +assign stat_rx_lfc_pkt = stat_rx_lfc_pkt_reg; +assign stat_rx_lfc_xon = stat_rx_lfc_xon_reg; +assign stat_rx_lfc_xoff = stat_rx_lfc_xoff_reg; +assign stat_rx_lfc_paused = lfc_req_reg; +assign stat_rx_pfc_pkt = stat_rx_pfc_pkt_reg; +assign stat_rx_pfc_xon = stat_rx_pfc_xon_reg; +assign stat_rx_pfc_xoff = stat_rx_pfc_xoff_reg; +assign stat_rx_pfc_paused = pfc_req_reg; + +integer k; + +initial begin + for (k = 0; k < 8; k = k + 1) begin + pfc_quanta_reg[k] = 0; + end +end + +always @* begin + stat_rx_lfc_pkt_next = 1'b0; + stat_rx_lfc_xon_next = 1'b0; + stat_rx_lfc_xoff_next = 1'b0; + stat_rx_pfc_pkt_next = 1'b0; + stat_rx_pfc_xon_next = 0; + stat_rx_pfc_xoff_next = 0; + + if (cfg_quanta_clk_en && rx_lfc_ack) begin + if (lfc_quanta_reg > cfg_quanta_step) begin + lfc_quanta_next = lfc_quanta_reg - cfg_quanta_step; + end else begin + lfc_quanta_next = 0; + end + end else begin + lfc_quanta_next = lfc_quanta_reg; + end + + lfc_req_next = (lfc_quanta_reg != 0) && rx_lfc_en && cfg_rx_lfc_en; + + for (k = 0; k < 8; k = k + 1) begin + if (cfg_quanta_clk_en && rx_pfc_ack[k]) begin + if (pfc_quanta_reg[k] > cfg_quanta_step) begin + pfc_quanta_next[k] = pfc_quanta_reg[k] - cfg_quanta_step; + end else begin + pfc_quanta_next[k] = 0; + end + end else begin + pfc_quanta_next[k] = pfc_quanta_reg[k]; + end + + pfc_req_next[k] = (pfc_quanta_reg[k] != 0) && rx_pfc_en[k] && cfg_rx_pfc_en; + end + + if (mcf_valid) begin + if (mcf_opcode == cfg_rx_lfc_opcode && cfg_rx_lfc_en) begin + stat_rx_lfc_pkt_next = 1'b1; + stat_rx_lfc_xon_next = {mcf_params[7:0], mcf_params[15:8]} == 0; + stat_rx_lfc_xoff_next = {mcf_params[7:0], mcf_params[15:8]} != 0; + lfc_quanta_next = {mcf_params[7:0], mcf_params[15:8], {QFB{1'b0}}}; + end else if (PFC_ENABLE && mcf_opcode == cfg_rx_pfc_opcode && cfg_rx_pfc_en) begin + stat_rx_pfc_pkt_next = 1'b1; + for (k = 0; k < 8; k = k + 1) begin + if (mcf_params[k+8]) begin + stat_rx_pfc_xon_next[k] = {mcf_params[16+(k*16)+0 +: 8], mcf_params[16+(k*16)+8 +: 8]} == 0; + stat_rx_pfc_xoff_next[k] = {mcf_params[16+(k*16)+0 +: 8], mcf_params[16+(k*16)+8 +: 8]} != 0; + pfc_quanta_next[k] = {mcf_params[16+(k*16)+0 +: 8], mcf_params[16+(k*16)+8 +: 8], {QFB{1'b0}}}; + end + end + end + end +end + +always @(posedge clk) begin + lfc_req_reg <= lfc_req_next; + pfc_req_reg <= pfc_req_next; + + lfc_quanta_reg <= lfc_quanta_next; + for (k = 0; k < 8; k = k + 1) begin + pfc_quanta_reg[k] <= pfc_quanta_next[k]; + end + + stat_rx_lfc_pkt_reg <= stat_rx_lfc_pkt_next; + stat_rx_lfc_xon_reg <= stat_rx_lfc_xon_next; + stat_rx_lfc_xoff_reg <= stat_rx_lfc_xoff_next; + stat_rx_pfc_pkt_reg <= stat_rx_pfc_pkt_next; + stat_rx_pfc_xon_reg <= stat_rx_pfc_xon_next; + stat_rx_pfc_xoff_reg <= stat_rx_pfc_xoff_next; + + if (rst) begin + lfc_req_reg <= 1'b0; + pfc_req_reg <= 8'd0; + lfc_quanta_reg <= 0; + for (k = 0; k < 8; k = k + 1) begin + pfc_quanta_reg[k] <= 0; + end + + stat_rx_lfc_pkt_reg <= 1'b0; + stat_rx_lfc_xon_reg <= 1'b0; + stat_rx_lfc_xoff_reg <= 1'b0; + stat_rx_pfc_pkt_reg <= 1'b0; + stat_rx_pfc_xon_reg <= 0; + stat_rx_pfc_xoff_reg <= 0; + end +end + +endmodule + +`resetall diff --git a/fpga/lib/eth/rtl/mac_pause_ctrl_tx.v b/fpga/lib/eth/rtl/mac_pause_ctrl_tx.v new file mode 100644 index 000000000..7a56f594e --- /dev/null +++ b/fpga/lib/eth/rtl/mac_pause_ctrl_tx.v @@ -0,0 +1,313 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * PFC and pause frame transmit handling + */ +module mac_pause_ctrl_tx # +( + parameter MCF_PARAMS_SIZE = 18, + parameter PFC_ENABLE = 1 +) +( + input wire clk, + input wire rst, + + /* + * MAC control frame interface + */ + output wire mcf_valid, + input wire mcf_ready, + output wire [47:0] mcf_eth_dst, + output wire [47:0] mcf_eth_src, + output wire [15:0] mcf_eth_type, + output wire [15:0] mcf_opcode, + output wire [MCF_PARAMS_SIZE*8-1:0] mcf_params, + + /* + * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) + */ + input wire tx_lfc_req, + input wire tx_lfc_resend, + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D) + */ + input wire [7:0] tx_pfc_req, + input wire tx_pfc_resend, + + /* + * Configuration + */ + input wire [47:0] cfg_tx_lfc_eth_dst, + input wire [47:0] cfg_tx_lfc_eth_src, + input wire [15:0] cfg_tx_lfc_eth_type, + input wire [15:0] cfg_tx_lfc_opcode, + input wire cfg_tx_lfc_en, + input wire [15:0] cfg_tx_lfc_quanta, + input wire [15:0] cfg_tx_lfc_refresh, + input wire [47:0] cfg_tx_pfc_eth_dst, + input wire [47:0] cfg_tx_pfc_eth_src, + input wire [15:0] cfg_tx_pfc_eth_type, + input wire [15:0] cfg_tx_pfc_opcode, + input wire cfg_tx_pfc_en, + input wire [8*16-1:0] cfg_tx_pfc_quanta, + input wire [8*16-1:0] cfg_tx_pfc_refresh, + input wire [9:0] cfg_quanta_step, + input wire cfg_quanta_clk_en, + + /* + * Status + */ + output wire stat_tx_lfc_pkt, + output wire stat_tx_lfc_xon, + output wire stat_tx_lfc_xoff, + output wire stat_tx_lfc_paused, + output wire stat_tx_pfc_pkt, + output wire [7:0] stat_tx_pfc_xon, + output wire [7:0] stat_tx_pfc_xoff, + output wire [7:0] stat_tx_pfc_paused +); + +localparam QFB = 8; + +// check configuration +initial begin + if (MCF_PARAMS_SIZE < (PFC_ENABLE ? 18 : 2)) begin + $error("Error: MCF_PARAMS_SIZE too small for requested configuration (instance %m)"); + $finish; + end +end + +reg lfc_req_reg = 1'b0, lfc_req_next; +reg lfc_act_reg = 1'b0, lfc_act_next; +reg lfc_send_reg = 1'b0, lfc_send_next; +reg [7:0] pfc_req_reg = 8'd0, pfc_req_next; +reg [7:0] pfc_act_reg = 8'd0, pfc_act_next; +reg [7:0] pfc_en_reg = 8'd0, pfc_en_next; +reg pfc_send_reg = 1'b0, pfc_send_next; + +reg [16+QFB-1:0] lfc_refresh_reg = 0, lfc_refresh_next; +reg [16+QFB-1:0] pfc_refresh_reg[0:7], pfc_refresh_next[0:7]; + +reg stat_tx_lfc_pkt_reg = 1'b0, stat_tx_lfc_pkt_next; +reg stat_tx_lfc_xon_reg = 1'b0, stat_tx_lfc_xon_next; +reg stat_tx_lfc_xoff_reg = 1'b0, stat_tx_lfc_xoff_next; +reg stat_tx_pfc_pkt_reg = 1'b0, stat_tx_pfc_pkt_next; +reg [7:0] stat_tx_pfc_xon_reg = 0, stat_tx_pfc_xon_next; +reg [7:0] stat_tx_pfc_xoff_reg = 0, stat_tx_pfc_xoff_next; + +// MAC control interface +reg mcf_pfc_sel_reg = PFC_ENABLE != 0, mcf_pfc_sel_next; +reg mcf_valid_reg = 1'b0, mcf_valid_next; + +wire [2*8-1:0] mcf_lfc_params; +assign mcf_lfc_params[16*0 +: 16] = lfc_req_reg ? {cfg_tx_lfc_quanta[0 +: 8], cfg_tx_lfc_quanta[8 +: 8]} : 0; + +wire [18*8-1:0] mcf_pfc_params; +assign mcf_pfc_params[16*0 +: 16] = {pfc_en_reg, 8'd0}; +assign mcf_pfc_params[16*1 +: 16] = pfc_req_reg[0] ? {cfg_tx_pfc_quanta[16*0+0 +: 8], cfg_tx_pfc_quanta[16*0+8 +: 8]} : 0; +assign mcf_pfc_params[16*2 +: 16] = pfc_req_reg[1] ? {cfg_tx_pfc_quanta[16*1+0 +: 8], cfg_tx_pfc_quanta[16*1+8 +: 8]} : 0; +assign mcf_pfc_params[16*3 +: 16] = pfc_req_reg[2] ? {cfg_tx_pfc_quanta[16*2+0 +: 8], cfg_tx_pfc_quanta[16*2+8 +: 8]} : 0; +assign mcf_pfc_params[16*4 +: 16] = pfc_req_reg[3] ? {cfg_tx_pfc_quanta[16*3+0 +: 8], cfg_tx_pfc_quanta[16*3+8 +: 8]} : 0; +assign mcf_pfc_params[16*5 +: 16] = pfc_req_reg[4] ? {cfg_tx_pfc_quanta[16*4+0 +: 8], cfg_tx_pfc_quanta[16*4+8 +: 8]} : 0; +assign mcf_pfc_params[16*6 +: 16] = pfc_req_reg[5] ? {cfg_tx_pfc_quanta[16*5+0 +: 8], cfg_tx_pfc_quanta[16*5+8 +: 8]} : 0; +assign mcf_pfc_params[16*7 +: 16] = pfc_req_reg[6] ? {cfg_tx_pfc_quanta[16*6+0 +: 8], cfg_tx_pfc_quanta[16*6+8 +: 8]} : 0; +assign mcf_pfc_params[16*8 +: 16] = pfc_req_reg[7] ? {cfg_tx_pfc_quanta[16*7+0 +: 8], cfg_tx_pfc_quanta[16*7+8 +: 8]} : 0; + +assign mcf_valid = mcf_valid_reg; +assign mcf_eth_dst = (PFC_ENABLE && mcf_pfc_sel_reg) ? cfg_tx_pfc_eth_dst : cfg_tx_lfc_eth_dst; +assign mcf_eth_src = (PFC_ENABLE && mcf_pfc_sel_reg) ? cfg_tx_pfc_eth_src : cfg_tx_lfc_eth_src; +assign mcf_eth_type = (PFC_ENABLE && mcf_pfc_sel_reg) ? cfg_tx_pfc_eth_type : cfg_tx_lfc_eth_type; +assign mcf_opcode = (PFC_ENABLE && mcf_pfc_sel_reg) ? cfg_tx_pfc_opcode : cfg_tx_lfc_opcode; +assign mcf_params = (PFC_ENABLE && mcf_pfc_sel_reg) ? mcf_pfc_params : mcf_lfc_params; + +assign stat_tx_lfc_pkt = stat_tx_lfc_pkt_reg; +assign stat_tx_lfc_xon = stat_tx_lfc_xon_reg; +assign stat_tx_lfc_xoff = stat_tx_lfc_xoff_reg; +assign stat_tx_lfc_paused = lfc_req_reg; +assign stat_tx_pfc_pkt = stat_tx_pfc_pkt_reg; +assign stat_tx_pfc_xon = stat_tx_pfc_xon_reg; +assign stat_tx_pfc_xoff = stat_tx_pfc_xoff_reg; +assign stat_tx_pfc_paused = pfc_req_reg; + +integer k; + +initial begin + for (k = 0; k < 8; k = k + 1) begin + pfc_refresh_reg[k] = 0; + end +end + +always @* begin + lfc_req_next = lfc_req_reg; + lfc_act_next = lfc_act_reg; + lfc_send_next = lfc_send_reg | tx_lfc_resend; + pfc_req_next = pfc_req_reg; + pfc_act_next = pfc_act_reg; + pfc_en_next = pfc_en_reg; + pfc_send_next = pfc_send_reg | tx_pfc_resend; + + mcf_pfc_sel_next = mcf_pfc_sel_reg; + mcf_valid_next = mcf_valid_reg && !mcf_ready; + + stat_tx_lfc_pkt_next = 1'b0; + stat_tx_lfc_xon_next = 1'b0; + stat_tx_lfc_xoff_next = 1'b0; + stat_tx_pfc_pkt_next = 1'b0; + stat_tx_pfc_xon_next = 0; + stat_tx_pfc_xoff_next = 0; + + if (cfg_quanta_clk_en) begin + if (lfc_refresh_reg > cfg_quanta_step) begin + lfc_refresh_next = lfc_refresh_reg - cfg_quanta_step; + end else begin + lfc_refresh_next = 0; + if (lfc_req_reg) begin + lfc_send_next = 1'b1; + end + end + end else begin + lfc_refresh_next = lfc_refresh_reg; + end + + for (k = 0; k < 8; k = k + 1) begin + if (cfg_quanta_clk_en) begin + if (pfc_refresh_reg[k] > cfg_quanta_step) begin + pfc_refresh_next[k] = pfc_refresh_reg[k] - cfg_quanta_step; + end else begin + pfc_refresh_next[k] = 0; + if (pfc_req_reg[k]) begin + pfc_send_next = 1'b1; + end + end + end else begin + pfc_refresh_next[k] = pfc_refresh_reg[k]; + end + end + + if (cfg_tx_lfc_en) begin + if (!mcf_valid_reg) begin + if (lfc_req_reg != tx_lfc_req) begin + lfc_req_next = tx_lfc_req; + lfc_act_next = lfc_act_reg | tx_lfc_req; + lfc_send_next = 1'b1; + end + + if (lfc_send_reg && !(PFC_ENABLE && cfg_tx_pfc_en && pfc_send_reg)) begin + mcf_pfc_sel_next = 1'b0; + mcf_valid_next = lfc_act_reg; + lfc_act_next = lfc_req_reg; + lfc_refresh_next = lfc_req_reg ? {cfg_tx_lfc_refresh, {QFB{1'b0}}} : 0; + lfc_send_next = 1'b0; + + stat_tx_lfc_pkt_next = lfc_act_reg; + stat_tx_lfc_xon_next = lfc_act_reg && !lfc_req_reg; + stat_tx_lfc_xoff_next = lfc_act_reg && lfc_req_reg; + end + end + end + + if (PFC_ENABLE && cfg_tx_pfc_en) begin + if (!mcf_valid_reg) begin + if (pfc_req_reg != tx_pfc_req) begin + pfc_req_next = tx_pfc_req; + pfc_act_next = pfc_act_reg | tx_pfc_req; + pfc_send_next = 1'b1; + end + + if (pfc_send_reg) begin + mcf_pfc_sel_next = 1'b1; + mcf_valid_next = pfc_act_reg != 0; + pfc_en_next = pfc_act_reg; + pfc_act_next = pfc_req_reg; + for (k = 0; k < 8; k = k + 1) begin + pfc_refresh_next[k] = pfc_req_reg[k] ? {cfg_tx_pfc_refresh[16*k +: 16], {QFB{1'b0}}} : 0; + end + pfc_send_next = 1'b0; + + stat_tx_pfc_pkt_next = pfc_act_reg != 0; + stat_tx_pfc_xon_next = pfc_act_reg & ~pfc_req_reg; + stat_tx_pfc_xoff_next = pfc_act_reg & pfc_req_reg; + end + end + end +end + +always @(posedge clk) begin + lfc_req_reg <= lfc_req_next; + lfc_act_reg <= lfc_act_next; + lfc_send_reg <= lfc_send_next; + pfc_req_reg <= pfc_req_next; + pfc_act_reg <= pfc_act_next; + pfc_en_reg <= pfc_en_next; + pfc_send_reg <= pfc_send_next; + + mcf_pfc_sel_reg <= mcf_pfc_sel_next; + mcf_valid_reg <= mcf_valid_next; + + lfc_refresh_reg <= lfc_refresh_next; + for (k = 0; k < 8; k = k + 1) begin + pfc_refresh_reg[k] <= pfc_refresh_next[k]; + end + + stat_tx_lfc_pkt_reg <= stat_tx_lfc_pkt_next; + stat_tx_lfc_xon_reg <= stat_tx_lfc_xon_next; + stat_tx_lfc_xoff_reg <= stat_tx_lfc_xoff_next; + stat_tx_pfc_pkt_reg <= stat_tx_pfc_pkt_next; + stat_tx_pfc_xon_reg <= stat_tx_pfc_xon_next; + stat_tx_pfc_xoff_reg <= stat_tx_pfc_xoff_next; + + if (rst) begin + lfc_req_reg <= 1'b0; + lfc_act_reg <= 1'b0; + lfc_send_reg <= 1'b0; + pfc_req_reg <= 0; + pfc_act_reg <= 0; + pfc_send_reg <= 0; + mcf_pfc_sel_reg <= PFC_ENABLE != 0; + mcf_valid_reg <= 1'b0; + lfc_refresh_reg <= 0; + for (k = 0; k < 8; k = k + 1) begin + pfc_refresh_reg[k] <= 0; + end + + stat_tx_lfc_pkt_reg <= 1'b0; + stat_tx_lfc_xon_reg <= 1'b0; + stat_tx_lfc_xoff_reg <= 1'b0; + stat_tx_pfc_pkt_reg <= 1'b0; + stat_tx_pfc_xon_reg <= 0; + stat_tx_pfc_xoff_reg <= 0; + end +end + +endmodule + +`resetall diff --git a/fpga/lib/eth/syn/vivado/eth_mac.tcl b/fpga/lib/eth/syn/vivado/eth_mac.tcl new file mode 100644 index 000000000..0bebff5ab --- /dev/null +++ b/fpga/lib/eth/syn/vivado/eth_mac.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2019 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Ethernet MAC timing constraints + +foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == eth_mac_1g || REF_NAME == eth_mac_1g || \ + ORIG_REF_NAME == eth_mac_10g || REF_NAME == eth_mac_10g)}] { + puts "Inserting timing constraints for Ethernet MAC instance $inst" + + set sync_ffs [get_cells -quiet -hier -regexp ".*/mac_ctrl.tx_lfc_req_sync_reg_\[1234\]_reg" -filter "PARENT == $inst"] + + if {[llength $sync_ffs]} { + set_property ASYNC_REG TRUE $sync_ffs + + set src_clk [get_clocks -of_objects [get_pins $inst/mac_ctrl.tx_lfc_req_sync_reg_1_reg/C]] + + set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 1.0}] + + set_max_delay -from [get_cells $inst/mac_ctrl.tx_lfc_req_sync_reg_1_reg] -to [get_cells $inst/mac_ctrl.tx_lfc_req_sync_reg_2_reg] -datapath_only $src_clk_period + } + + set sync_ffs [get_cells -quiet -hier -regexp ".*/mac_ctrl.rx_lfc_ack_sync_reg_\[1234\]_reg" -filter "PARENT == $inst"] + + if {[llength $sync_ffs]} { + set_property ASYNC_REG TRUE $sync_ffs + + set src_clk [get_clocks -of_objects [get_pins $inst/mac_ctrl.rx_lfc_ack_sync_reg_1_reg/C]] + + set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 1.0}] + + set_max_delay -from [get_cells $inst/mac_ctrl.rx_lfc_ack_sync_reg_1_reg] -to [get_cells $inst/mac_ctrl.rx_lfc_ack_sync_reg_2_reg] -datapath_only $src_clk_period + } +} diff --git a/fpga/lib/eth/syn/vivado/eth_mac_1g_gmii.tcl b/fpga/lib/eth/syn/vivado/eth_mac_1g_gmii.tcl index 65c637c78..3c1232a92 100644 --- a/fpga/lib/eth/syn/vivado/eth_mac_1g_gmii.tcl +++ b/fpga/lib/eth/syn/vivado/eth_mac_1g_gmii.tcl @@ -30,7 +30,9 @@ foreach mac_inst [get_cells -hier -filter {(ORIG_REF_NAME == eth_mac_1g_gmii || set src_clk [get_clocks -of_objects [get_pins $mac_inst/mii_select_reg_reg/C]] - set_max_delay -from [get_cells $mac_inst/mii_select_reg_reg] -to [get_cells $mac_inst/tx_mii_select_sync_reg[0]] -datapath_only [get_property -min PERIOD $src_clk] + set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}] + + set_max_delay -from [get_cells $mac_inst/mii_select_reg_reg] -to [get_cells $mac_inst/tx_mii_select_sync_reg[0]] -datapath_only $src_clk_period } set select_ffs [get_cells -hier -regexp ".*/rx_mii_select_sync_reg\\\[\\d\\\]" -filter "PARENT == $mac_inst"] @@ -40,7 +42,9 @@ foreach mac_inst [get_cells -hier -filter {(ORIG_REF_NAME == eth_mac_1g_gmii || set src_clk [get_clocks -of_objects [get_pins $mac_inst/mii_select_reg_reg/C]] - set_max_delay -from [get_cells $mac_inst/mii_select_reg_reg] -to [get_cells $mac_inst/rx_mii_select_sync_reg[0]] -datapath_only [get_property -min PERIOD $src_clk] + set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}] + + set_max_delay -from [get_cells $mac_inst/mii_select_reg_reg] -to [get_cells $mac_inst/rx_mii_select_sync_reg[0]] -datapath_only $src_clk_period } set prescale_ffs [get_cells -hier -regexp ".*/rx_prescale_sync_reg\\\[\\d\\\]" -filter "PARENT == $mac_inst"] @@ -50,6 +54,8 @@ foreach mac_inst [get_cells -hier -filter {(ORIG_REF_NAME == eth_mac_1g_gmii || set src_clk [get_clocks -of_objects [get_pins $mac_inst/rx_prescale_reg[2]/C]] - set_max_delay -from [get_cells $mac_inst/rx_prescale_reg[2]] -to [get_cells $mac_inst/rx_prescale_sync_reg[0]] -datapath_only [get_property -min PERIOD $src_clk] + set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}] + + set_max_delay -from [get_cells $mac_inst/rx_prescale_reg[2]] -to [get_cells $mac_inst/rx_prescale_sync_reg[0]] -datapath_only $src_clk_period } } diff --git a/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl b/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl index 7f8d0e273..84a3c5538 100644 --- a/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl +++ b/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl @@ -30,7 +30,9 @@ foreach mac_inst [get_cells -hier -filter {(ORIG_REF_NAME == eth_mac_1g_rgmii || set src_clk [get_clocks -of_objects [get_pins $mac_inst/mii_select_reg_reg/C]] - set_max_delay -from [get_cells $mac_inst/mii_select_reg_reg] -to [get_cells $mac_inst/tx_mii_select_sync_reg[0]] -datapath_only [get_property -min PERIOD $src_clk] + set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}] + + set_max_delay -from [get_cells $mac_inst/mii_select_reg_reg] -to [get_cells $mac_inst/tx_mii_select_sync_reg[0]] -datapath_only $src_clk_period } set select_ffs [get_cells -hier -regexp ".*/rx_mii_select_sync_reg\\\[\\d\\\]" -filter "PARENT == $mac_inst"] @@ -40,7 +42,9 @@ foreach mac_inst [get_cells -hier -filter {(ORIG_REF_NAME == eth_mac_1g_rgmii || set src_clk [get_clocks -of_objects [get_pins $mac_inst/mii_select_reg_reg/C]] - set_max_delay -from [get_cells $mac_inst/mii_select_reg_reg] -to [get_cells $mac_inst/rx_mii_select_sync_reg[0]] -datapath_only [get_property -min PERIOD $src_clk] + set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}] + + set_max_delay -from [get_cells $mac_inst/mii_select_reg_reg] -to [get_cells $mac_inst/rx_mii_select_sync_reg[0]] -datapath_only $src_clk_period } set prescale_ffs [get_cells -hier -regexp ".*/rx_prescale_sync_reg\\\[\\d\\\]" -filter "PARENT == $mac_inst"] @@ -50,6 +54,8 @@ foreach mac_inst [get_cells -hier -filter {(ORIG_REF_NAME == eth_mac_1g_rgmii || set src_clk [get_clocks -of_objects [get_pins $mac_inst/rx_prescale_reg[2]/C]] - set_max_delay -from [get_cells $mac_inst/rx_prescale_reg[2]] -to [get_cells $mac_inst/rx_prescale_sync_reg[0]] -datapath_only [get_property -min PERIOD $src_clk] + set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}] + + set_max_delay -from [get_cells $mac_inst/rx_prescale_reg[2]] -to [get_cells $mac_inst/rx_prescale_sync_reg[0]] -datapath_only $src_clk_period } } diff --git a/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl b/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl index 69a06318e..39689a31f 100644 --- a/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl +++ b/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl @@ -34,7 +34,9 @@ foreach mac_inst [get_cells -hier -filter {(ORIG_REF_NAME == eth_mac_1g_fifo || set src_clk [get_clocks -of_objects [get_pins $mac_inst/rx_sync_reg_1_reg[*]/C]] - set_max_delay -from [get_cells $mac_inst/rx_sync_reg_1_reg[*]] -to [get_cells $mac_inst/rx_sync_reg_2_reg[*]] -datapath_only [get_property -min PERIOD $src_clk] + set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}] + + set_max_delay -from [get_cells $mac_inst/rx_sync_reg_1_reg[*]] -to [get_cells $mac_inst/rx_sync_reg_2_reg[*]] -datapath_only $src_clk_period } set sync_ffs [get_cells -hier -regexp ".*/tx_sync_reg_\[1234\]_reg\\\[\\d+\\\]" -filter "PARENT == $mac_inst"] @@ -44,6 +46,8 @@ foreach mac_inst [get_cells -hier -filter {(ORIG_REF_NAME == eth_mac_1g_fifo || set src_clk [get_clocks -of_objects [get_pins $mac_inst/tx_sync_reg_1_reg[*]/C]] - set_max_delay -from [get_cells $mac_inst/tx_sync_reg_1_reg[*]] -to [get_cells $mac_inst/tx_sync_reg_2_reg[*]] -datapath_only [get_property -min PERIOD $src_clk] + set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}] + + set_max_delay -from [get_cells $mac_inst/tx_sync_reg_1_reg[*]] -to [get_cells $mac_inst/tx_sync_reg_2_reg[*]] -datapath_only $src_clk_period } } diff --git a/fpga/lib/eth/syn/vivado/ptp_clock_cdc.tcl b/fpga/lib/eth/syn/vivado/ptp_clock_cdc.tcl index f87f4635d..a51364781 100644 --- a/fpga/lib/eth/syn/vivado/ptp_clock_cdc.tcl +++ b/fpga/lib/eth/syn/vivado/ptp_clock_cdc.tcl @@ -27,8 +27,8 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == ptp_clock_cdc || REF_NA set input_clk [get_clocks -of_objects [get_pins "$inst/src_sync_reg_reg/C"]] set output_clk [get_clocks -of_objects [get_pins "$inst/dest_sync_reg_reg/C"]] - set input_clk_period [get_property -min PERIOD $input_clk] - set output_clk_period [get_property -min PERIOD $output_clk] + set input_clk_period [if {[llength $input_clk]} {get_property -min PERIOD $input_clk} {expr 1.0}] + set output_clk_period [if {[llength $output_clk]} {get_property -min PERIOD $output_clk} {expr 1.0}] # timestamp synchronization set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/ts_(s|ns|fns|step)_sync_reg_reg(\\\[\\d+\\\])?" -filter "PARENT == $inst"] @@ -55,10 +55,7 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == ptp_clock_cdc || REF_NA if {[llength $sync_ffs]} { set_property ASYNC_REG TRUE $sync_ffs - set src_clk [get_clocks -of_objects [get_pins "$inst/src_sync_reg_reg/C"]] - set dest_clk [get_clocks -of_objects [get_pins "$inst/src_sync_sample_sync1_reg_reg/C"]] - - set_max_delay -from [get_cells "$inst/src_sync_reg_reg"] -to [get_cells "$inst/src_sync_sample_sync1_reg_reg"] -datapath_only [get_property -min PERIOD $src_clk] + set_max_delay -from [get_cells "$inst/src_sync_reg_reg"] -to [get_cells "$inst/src_sync_sample_sync1_reg_reg"] -datapath_only $input_clk_period } set sync_ffs [get_cells -quiet -hier -regexp ".*/dest_sync_sample_sync\[12\]_reg_reg" -filter "PARENT == $inst"] @@ -66,10 +63,7 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == ptp_clock_cdc || REF_NA if {[llength $sync_ffs]} { set_property ASYNC_REG TRUE $sync_ffs - set src_clk [get_clocks -of_objects [get_pins "$inst/dest_sync_reg_reg/C"]] - set dest_clk [get_clocks -of_objects [get_pins "$inst/dest_sync_sample_sync1_reg_reg/C"]] - - set_max_delay -from [get_cells "$inst/dest_sync_reg_reg"] -to [get_cells "$inst/dest_sync_sample_sync1_reg_reg"] -datapath_only [get_property -min PERIOD $src_clk] + set_max_delay -from [get_cells "$inst/dest_sync_reg_reg"] -to [get_cells "$inst/dest_sync_sample_sync1_reg_reg"] -datapath_only $output_clk_period } # sample update sync @@ -79,12 +73,13 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == ptp_clock_cdc || REF_NA set_property ASYNC_REG TRUE $sync_ffs set src_clk [get_clocks -of_objects [get_pins "$inst/sample_update_reg_reg/C"]] - set dest_clk [get_clocks -of_objects [get_pins "$inst/sample_update_sync1_reg_reg/C"]] - set_max_delay -from [get_cells "$inst/sample_update_reg_reg"] -to [get_cells "$inst/sample_update_sync1_reg_reg"] -datapath_only [get_property -min PERIOD $src_clk] + set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 1.0}] - set_max_delay -from [get_cells "$inst/sample_acc_out_reg_reg[*]"] -to [get_cells $inst/sample_acc_sync_reg_reg[*]] -datapath_only [get_property -min PERIOD $src_clk] - set_bus_skew -from [get_cells "$inst/sample_acc_out_reg_reg[*]"] -to [get_cells $inst/sample_acc_sync_reg_reg[*]] [get_property -min PERIOD $dest_clk] + set_max_delay -from [get_cells "$inst/sample_update_reg_reg"] -to [get_cells "$inst/sample_update_sync1_reg_reg"] -datapath_only $src_clk_period + + set_max_delay -from [get_cells "$inst/sample_acc_out_reg_reg[*]"] -to [get_cells $inst/sample_acc_sync_reg_reg[*]] -datapath_only $src_clk_period + set_bus_skew -from [get_cells "$inst/sample_acc_out_reg_reg[*]"] -to [get_cells $inst/sample_acc_sync_reg_reg[*]] $output_clk_period } # no sample clock @@ -93,9 +88,6 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == ptp_clock_cdc || REF_NA if {[llength $sync_ffs]} { set_property ASYNC_REG TRUE $sync_ffs - set src_clk [get_clocks -of_objects [get_pins "$inst/src_sync_reg_reg/C"]] - set dest_clk [get_clocks -of_objects [get_pins "$inst/src_sync_sync1_reg_reg/C"]] - - set_max_delay -from [get_cells "$inst/src_sync_reg_reg"] -to [get_cells "$inst/src_sync_sync1_reg_reg"] -datapath_only [get_property -min PERIOD $src_clk] + set_max_delay -from [get_cells "$inst/src_sync_reg_reg"] -to [get_cells "$inst/src_sync_sync1_reg_reg"] -datapath_only $input_clk_period } } diff --git a/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl b/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl index 57105081d..d64bf2d5b 100644 --- a/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl +++ b/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl @@ -34,6 +34,8 @@ foreach if_inst [get_cells -hier -filter {(ORIG_REF_NAME == rgmii_phy_if || REF_ set src_clk [get_clocks -of_objects [get_pins $if_inst/rgmii_tx_clk_1_reg/C]] - set_max_delay -from [get_cells $if_inst/rgmii_tx_clk_1_reg] -to [get_cells $if_inst/clk_oddr_inst/oddr[0].oddr_inst] -datapath_only [expr [get_property -min PERIOD $src_clk]/4] - set_max_delay -from [get_cells $if_inst/rgmii_tx_clk_2_reg] -to [get_cells $if_inst/clk_oddr_inst/oddr[0].oddr_inst] -datapath_only [expr [get_property -min PERIOD $src_clk]/4] + set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}] + + set_max_delay -from [get_cells $if_inst/rgmii_tx_clk_1_reg] -to [get_cells $if_inst/clk_oddr_inst/oddr[0].oddr_inst] -datapath_only [expr $src_clk_period/4] + set_max_delay -from [get_cells $if_inst/rgmii_tx_clk_2_reg] -to [get_cells $if_inst/clk_oddr_inst/oddr[0].oddr_inst] -datapath_only [expr $src_clk_period/4] } diff --git a/fpga/lib/eth/tb/axis_baser_rx_64/test_axis_baser_rx_64.py b/fpga/lib/eth/tb/axis_baser_rx_64/test_axis_baser_rx_64.py index da1fa16a9..38a2e29c3 100644 --- a/fpga/lib/eth/tb/axis_baser_rx_64/test_axis_baser_rx_64.py +++ b/fpga/lib/eth/tb/axis_baser_rx_64/test_axis_baser_rx_64.py @@ -107,6 +107,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns)) assert rx_frame.tdata == test_data assert frame_error == 0 diff --git a/fpga/lib/eth/tb/axis_baser_tx_64/Makefile b/fpga/lib/eth/tb/axis_baser_tx_64/Makefile index 26b54659c..a5d23facd 100644 --- a/fpga/lib/eth/tb/axis_baser_tx_64/Makefile +++ b/fpga/lib/eth/tb/axis_baser_tx_64/Makefile @@ -41,9 +41,10 @@ export PARAM_ENABLE_DIC := 1 export PARAM_MIN_FRAME_LENGTH := 64 export PARAM_PTP_TS_ENABLE := 1 export PARAM_PTP_TS_WIDTH := 96 +export PARAM_PTP_TS_CTRL_IN_TUSER := $(PARAM_PTP_TS_ENABLE) export PARAM_PTP_TAG_ENABLE := $(PARAM_PTP_TS_ENABLE) export PARAM_PTP_TAG_WIDTH := 16 -export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) +export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(if $(filter-out 1,$(PARAM_PTP_TAG_ENABLE)),0,$(PARAM_PTP_TAG_WIDTH)) + $(if $(filter-out 1,$(PTP_TS_CTRL_IN_TUSER)),0,1) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/axis_baser_tx_64/test_axis_baser_tx_64.py b/fpga/lib/eth/tb/axis_baser_tx_64/test_axis_baser_tx_64.py index e8b6b77f0..7888712a5 100644 --- a/fpga/lib/eth/tb/axis_baser_tx_64/test_axis_baser_tx_64.py +++ b/fpga/lib/eth/tb/axis_baser_tx_64/test_axis_baser_tx_64.py @@ -38,7 +38,7 @@ from cocotb.utils import get_time_from_sim_steps from cocotb.regression import TestFactory from cocotbext.eth import PtpClockSimTime -from cocotbext.axi import AxiStreamBus, AxiStreamSource +from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamFrame from cocotbext.axi.stream import define_stream try: @@ -98,7 +98,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): test_frames = [payload_data(x) for x in payload_lengths()] for test_data in test_frames: - await tb.source.send(test_data) + await tb.source.send(AxiStreamFrame(test_data, tuser=2)) for test_data in test_frames: rx_frame = await tb.sink.recv() @@ -114,6 +114,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns)) assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() @@ -136,15 +137,18 @@ async def run_test_alignment(dut, payload_data=None, ifg=12): tb.dut.ifg_delay.value = ifg + await tb.reset() + for length in range(60, 92): - await tb.reset() + for k in range(10): + await RisingEdge(dut.clk) test_frames = [payload_data(length) for k in range(10)] start_lane = [] for test_data in test_frames: - await tb.source.send(test_data) + await tb.source.send(AxiStreamFrame(test_data, tuser=2)) for test_data in test_frames: rx_frame = await tb.sink.recv() @@ -160,6 +164,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12): tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns)) assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() @@ -263,9 +268,10 @@ def test_axis_baser_tx_64(request, enable_dic): parameters['MIN_FRAME_LENGTH'] = 64 parameters['PTP_TS_ENABLE'] = 1 parameters['PTP_TS_WIDTH'] = 96 + parameters['PTP_TS_CTRL_IN_TUSER'] = parameters['PTP_TS_ENABLE'] parameters['PTP_TAG_ENABLE'] = parameters['PTP_TS_ENABLE'] parameters['PTP_TAG_WIDTH'] = 16 - parameters['USER_WIDTH'] = (parameters['PTP_TAG_WIDTH'] if parameters['PTP_TAG_ENABLE'] else 0) + 1 + parameters['USER_WIDTH'] = ((parameters['PTP_TAG_WIDTH'] if parameters['PTP_TAG_ENABLE'] else 0) + (1 if parameters['PTP_TS_CTRL_IN_TUSER'] else 0) if parameters['PTP_TS_ENABLE'] else 0) + 1 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/fpga/lib/eth/tb/axis_gmii_rx/Makefile b/fpga/lib/eth/tb/axis_gmii_rx/Makefile index 1fbe4ebbb..a2d70373b 100644 --- a/fpga/lib/eth/tb/axis_gmii_rx/Makefile +++ b/fpga/lib/eth/tb/axis_gmii_rx/Makefile @@ -34,10 +34,9 @@ VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters export PARAM_DATA_WIDTH := 8 -export PARAM_PTP_TS_ENABLE := 0 +export PARAM_PTP_TS_ENABLE := 1 export PARAM_PTP_TS_WIDTH := 96 -#export PARAM_USER_WIDTH := (parameters['PTP_TS_WIDTH'] if parameters['PTP_TS_ENABLE'] else 0) + 1 -export PARAM_USER_WIDTH := 1 +export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/axis_gmii_rx/test_axis_gmii_rx.py b/fpga/lib/eth/tb/axis_gmii_rx/test_axis_gmii_rx.py index ade49c5ae..07605cf7e 100644 --- a/fpga/lib/eth/tb/axis_gmii_rx/test_axis_gmii_rx.py +++ b/fpga/lib/eth/tb/axis_gmii_rx/test_axis_gmii_rx.py @@ -32,9 +32,10 @@ import cocotb_test.simulator import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge +from cocotb.utils import get_time_from_sim_steps from cocotb.regression import TestFactory -from cocotbext.eth import GmiiFrame, GmiiSource +from cocotbext.eth import GmiiFrame, GmiiSource, PtpClockSimTime from cocotbext.axi import AxiStreamBus, AxiStreamSink @@ -54,9 +55,10 @@ class TB: dut.clk, dut.rst, dut.clk_enable, dut.mii_select) self.sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis"), dut.clk, dut.rst) + self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk) + dut.clk_enable.setimmediatevalue(1) dut.mii_select.setimmediatevalue(0) - dut.ptp_ts.setimmediatevalue(0) async def reset(self): self.dut.rst.setimmediatevalue(0) @@ -101,16 +103,29 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_ await tb.reset() test_frames = [payload_data(x) for x in payload_lengths()] + tx_frames = [] for test_data in test_frames: - test_frame = GmiiFrame.from_payload(test_data) + test_frame = GmiiFrame.from_payload(test_data, tx_complete=tx_frames.append) await tb.source.send(test_frame) for test_data in test_frames: rx_frame = await tb.sink.recv() + tx_frame = tx_frames.pop(0) + + frame_error = rx_frame.tuser & 1 + ptp_ts = rx_frame.tuser >> 1 + ptp_ts_ns = ptp_ts / 2**16 + + tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns") + + tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns) + tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns)) assert rx_frame.tdata == test_data - assert rx_frame.tuser == 0 + assert frame_error == 0 + assert abs(ptp_ts_ns - tx_frame_sfd_ns - (32 if enable_gen else 8)) < 0.01 assert tb.sink.empty() @@ -162,7 +177,7 @@ def test_axis_gmii_rx(request): parameters = {} parameters['DATA_WIDTH'] = 8 - parameters['PTP_TS_ENABLE'] = 0 + parameters['PTP_TS_ENABLE'] = 1 parameters['PTP_TS_WIDTH'] = 96 parameters['USER_WIDTH'] = (parameters['PTP_TS_WIDTH'] if parameters['PTP_TS_ENABLE'] else 0) + 1 diff --git a/fpga/lib/eth/tb/axis_gmii_tx/Makefile b/fpga/lib/eth/tb/axis_gmii_tx/Makefile index a1aebdac3..8686c13d3 100644 --- a/fpga/lib/eth/tb/axis_gmii_tx/Makefile +++ b/fpga/lib/eth/tb/axis_gmii_tx/Makefile @@ -36,12 +36,12 @@ VERILOG_SOURCES += ../../rtl/lfsr.v export PARAM_DATA_WIDTH := 8 export PARAM_ENABLE_PADDING := 1 export PARAM_MIN_FRAME_LENGTH := 64 -export PARAM_PTP_TS_ENABLE := 0 +export PARAM_PTP_TS_ENABLE := 1 export PARAM_PTP_TS_WIDTH := 96 -export PARAM_PTP_TAG_ENABLE := PTP_TS_ENABLE +export PARAM_PTP_TS_CTRL_IN_TUSER := $(PARAM_PTP_TS_ENABLE) +export PARAM_PTP_TAG_ENABLE := $(PARAM_PTP_TS_ENABLE) export PARAM_PTP_TAG_WIDTH := 16 -#export PARAM_USER_WIDTH := (parameters['PTP_TS_WIDTH'] if parameters['PTP_TS_ENABLE'] else 0) + 1 -export PARAM_USER_WIDTH := 1 +export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(if $(filter-out 1,$(PARAM_PTP_TAG_ENABLE)),0,$(PARAM_PTP_TAG_WIDTH)) + $(if $(filter-out 1,$(PTP_TS_CTRL_IN_TUSER)),0,1) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/axis_gmii_tx/test_axis_gmii_tx.py b/fpga/lib/eth/tb/axis_gmii_tx/test_axis_gmii_tx.py index b4b5a196b..93fad4bd9 100644 --- a/fpga/lib/eth/tb/axis_gmii_tx/test_axis_gmii_tx.py +++ b/fpga/lib/eth/tb/axis_gmii_tx/test_axis_gmii_tx.py @@ -32,10 +32,18 @@ import cocotb_test.simulator import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge +from cocotb.utils import get_time_from_sim_steps from cocotb.regression import TestFactory -from cocotbext.eth import GmiiSink -from cocotbext.axi import AxiStreamBus, AxiStreamSource +from cocotbext.eth import GmiiSink, PtpClockSimTime +from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamFrame +from cocotbext.axi.stream import define_stream + + +PtpTsBus, PtpTsTransaction, PtpTsSource, PtpTsSink, PtpTsMonitor = define_stream("PtpTs", + signals=["ts", "ts_valid"], + optional_signals=["ts_tag", "ts_ready"] +) class TB: @@ -54,9 +62,11 @@ class TB: self.sink = GmiiSink(dut.gmii_txd, dut.gmii_tx_er, dut.gmii_tx_en, dut.clk, dut.rst, dut.clk_enable, dut.mii_select) + self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk) + self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst) + dut.clk_enable.setimmediatevalue(1) dut.mii_select.setimmediatevalue(0) - dut.ptp_ts.setimmediatevalue(0) dut.ifg_delay.setimmediatevalue(0) async def reset(self): @@ -104,14 +114,24 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_ test_frames = [payload_data(x) for x in payload_lengths()] for test_data in test_frames: - await tb.source.send(test_data) + await tb.source.send(AxiStreamFrame(test_data, tuser=2)) for test_data in test_frames: rx_frame = await tb.sink.recv() + ptp_ts = await tb.ptp_ts_sink.recv() + + ptp_ts_ns = int(ptp_ts.ts) / 2**16 + + rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns") + + tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) + tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns)) assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() assert rx_frame.error is None + assert abs(rx_frame_sfd_ns - ptp_ts_ns - (32 if enable_gen else 8)) < 0.01 assert tb.sink.empty() @@ -165,11 +185,12 @@ def test_axis_gmii_tx(request): parameters['DATA_WIDTH'] = 8 parameters['ENABLE_PADDING'] = 1 parameters['MIN_FRAME_LENGTH'] = 64 - parameters['PTP_TS_ENABLE'] = 0 + parameters['PTP_TS_ENABLE'] = 1 parameters['PTP_TS_WIDTH'] = 96 + parameters['PTP_TS_CTRL_IN_TUSER'] = parameters['PTP_TS_ENABLE'] parameters['PTP_TAG_ENABLE'] = parameters['PTP_TS_ENABLE'] parameters['PTP_TAG_WIDTH'] = 16 - parameters['USER_WIDTH'] = (parameters['PTP_TS_WIDTH'] if parameters['PTP_TS_ENABLE'] else 0) + 1 + parameters['USER_WIDTH'] = ((parameters['PTP_TAG_WIDTH'] if parameters['PTP_TAG_ENABLE'] else 0) + (1 if parameters['PTP_TS_CTRL_IN_TUSER'] else 0) if parameters['PTP_TS_ENABLE'] else 0) + 1 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/fpga/lib/eth/tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py b/fpga/lib/eth/tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py index 753920696..d77a31310 100644 --- a/fpga/lib/eth/tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py +++ b/fpga/lib/eth/tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py @@ -92,6 +92,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns)) assert rx_frame.tdata == test_data assert frame_error == 0 diff --git a/fpga/lib/eth/tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py b/fpga/lib/eth/tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py index 804c13325..0bd4cf6b9 100644 --- a/fpga/lib/eth/tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py +++ b/fpga/lib/eth/tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py @@ -96,6 +96,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns)) assert rx_frame.tdata == test_data assert frame_error == 0 diff --git a/fpga/lib/eth/tb/axis_xgmii_tx_32/Makefile b/fpga/lib/eth/tb/axis_xgmii_tx_32/Makefile index e24b2f9a1..ceef12de3 100644 --- a/fpga/lib/eth/tb/axis_xgmii_tx_32/Makefile +++ b/fpga/lib/eth/tb/axis_xgmii_tx_32/Makefile @@ -41,9 +41,10 @@ export PARAM_ENABLE_DIC := 1 export PARAM_MIN_FRAME_LENGTH := 64 export PARAM_PTP_TS_ENABLE := 1 export PARAM_PTP_TS_WIDTH := 96 +export PARAM_PTP_TS_CTRL_IN_TUSER := $(PARAM_PTP_TS_ENABLE) export PARAM_PTP_TAG_ENABLE := $(PARAM_PTP_TS_ENABLE) export PARAM_PTP_TAG_WIDTH := 16 -export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) +export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(if $(filter-out 1,$(PARAM_PTP_TAG_ENABLE)),0,$(PARAM_PTP_TAG_WIDTH)) + $(if $(filter-out 1,$(PTP_TS_CTRL_IN_TUSER)),0,1) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py b/fpga/lib/eth/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py index b6b3ab900..da8c52f3d 100644 --- a/fpga/lib/eth/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py +++ b/fpga/lib/eth/tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py @@ -37,7 +37,7 @@ from cocotb.utils import get_time_from_sim_steps from cocotb.regression import TestFactory from cocotbext.eth import XgmiiSink, PtpClockSimTime -from cocotbext.axi import AxiStreamBus, AxiStreamSource +from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamFrame from cocotbext.axi.stream import define_stream @@ -87,7 +87,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): test_frames = [payload_data(x) for x in payload_lengths()] for test_data in test_frames: - await tb.source.send(test_data) + await tb.source.send(AxiStreamFrame(test_data, tuser=2)) for test_data in test_frames: rx_frame = await tb.sink.recv() @@ -99,6 +99,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns)) assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() @@ -121,15 +122,18 @@ async def run_test_alignment(dut, payload_data=None, ifg=12): tb.dut.ifg_delay.value = ifg + await tb.reset() + for length in range(60, 92): - await tb.reset() + for k in range(10): + await RisingEdge(dut.clk) test_frames = [payload_data(length) for k in range(10)] start_lane = [] for test_data in test_frames: - await tb.source.send(test_data) + await tb.source.send(AxiStreamFrame(test_data, tuser=2)) for test_data in test_frames: rx_frame = await tb.sink.recv() @@ -141,6 +145,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12): tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns)) assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() @@ -244,9 +249,10 @@ def test_axis_xgmii_tx_32(request, enable_dic): parameters['MIN_FRAME_LENGTH'] = 64 parameters['PTP_TS_ENABLE'] = 1 parameters['PTP_TS_WIDTH'] = 96 + parameters['PTP_TS_CTRL_IN_TUSER'] = parameters['PTP_TS_ENABLE'] parameters['PTP_TAG_ENABLE'] = parameters['PTP_TS_ENABLE'] parameters['PTP_TAG_WIDTH'] = 16 - parameters['USER_WIDTH'] = (parameters['PTP_TAG_WIDTH'] if parameters['PTP_TAG_ENABLE'] else 0) + 1 + parameters['USER_WIDTH'] = ((parameters['PTP_TAG_WIDTH'] if parameters['PTP_TAG_ENABLE'] else 0) + (1 if parameters['PTP_TS_CTRL_IN_TUSER'] else 0) if parameters['PTP_TS_ENABLE'] else 0) + 1 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/fpga/lib/eth/tb/axis_xgmii_tx_64/Makefile b/fpga/lib/eth/tb/axis_xgmii_tx_64/Makefile index 7743dd38b..0ade45058 100644 --- a/fpga/lib/eth/tb/axis_xgmii_tx_64/Makefile +++ b/fpga/lib/eth/tb/axis_xgmii_tx_64/Makefile @@ -41,9 +41,10 @@ export PARAM_ENABLE_DIC := 1 export PARAM_MIN_FRAME_LENGTH := 64 export PARAM_PTP_TS_ENABLE := 1 export PARAM_PTP_TS_WIDTH := 96 +export PARAM_PTP_TS_CTRL_IN_TUSER := $(PARAM_PTP_TS_ENABLE) export PARAM_PTP_TAG_ENABLE := $(PARAM_PTP_TS_ENABLE) export PARAM_PTP_TAG_WIDTH := 16 -export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) +export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(if $(filter-out 1,$(PARAM_PTP_TAG_ENABLE)),0,$(PARAM_PTP_TAG_WIDTH)) + $(if $(filter-out 1,$(PTP_TS_CTRL_IN_TUSER)),0,1) + 1 )) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py b/fpga/lib/eth/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py index cdc18de49..29189b382 100644 --- a/fpga/lib/eth/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py +++ b/fpga/lib/eth/tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py @@ -37,7 +37,7 @@ from cocotb.utils import get_time_from_sim_steps from cocotb.regression import TestFactory from cocotbext.eth import XgmiiSink, PtpClockSimTime -from cocotbext.axi import AxiStreamBus, AxiStreamSource +from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamFrame from cocotbext.axi.stream import define_stream @@ -87,7 +87,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): test_frames = [payload_data(x) for x in payload_lengths()] for test_data in test_frames: - await tb.source.send(test_data) + await tb.source.send(AxiStreamFrame(test_data, tuser=2)) for test_data in test_frames: rx_frame = await tb.sink.recv() @@ -103,6 +103,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns)) assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() @@ -125,15 +126,18 @@ async def run_test_alignment(dut, payload_data=None, ifg=12): tb.dut.ifg_delay.value = ifg + await tb.reset() + for length in range(60, 92): - await tb.reset() + for k in range(10): + await RisingEdge(dut.clk) test_frames = [payload_data(length) for k in range(10)] start_lane = [] for test_data in test_frames: - await tb.source.send(test_data) + await tb.source.send(AxiStreamFrame(test_data, tuser=2)) for test_data in test_frames: rx_frame = await tb.sink.recv() @@ -149,6 +153,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12): tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns)) assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() @@ -252,9 +257,10 @@ def test_axis_xgmii_tx_64(request, enable_dic): parameters['MIN_FRAME_LENGTH'] = 64 parameters['PTP_TS_ENABLE'] = 1 parameters['PTP_TS_WIDTH'] = 96 + parameters['PTP_TS_CTRL_IN_TUSER'] = parameters['PTP_TS_ENABLE'] parameters['PTP_TAG_ENABLE'] = parameters['PTP_TS_ENABLE'] parameters['PTP_TAG_WIDTH'] = 16 - parameters['USER_WIDTH'] = (parameters['PTP_TAG_WIDTH'] if parameters['PTP_TAG_ENABLE'] else 0) + 1 + parameters['USER_WIDTH'] = ((parameters['PTP_TAG_WIDTH'] if parameters['PTP_TAG_ENABLE'] else 0) + (1 if parameters['PTP_TS_CTRL_IN_TUSER'] else 0) if parameters['PTP_TS_ENABLE'] else 0) + 1 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/fpga/lib/eth/tb/eth_axis_rx/test_eth_axis_rx.py b/fpga/lib/eth/tb/eth_axis_rx/test_eth_axis_rx.py index d31e4f248..e474011cc 100644 --- a/fpga/lib/eth/tb/eth_axis_rx/test_eth_axis_rx.py +++ b/fpga/lib/eth/tb/eth_axis_rx/test_eth_axis_rx.py @@ -136,7 +136,7 @@ def cycle_pause(): def size_list(): - return list(range(1, 128)) + [512, 1514, 9214] + [60]*10 + return list(range(1, 128)) + [512, 1500, 9200] + [60-14]*10 def incrementing_payload(length): diff --git a/fpga/lib/eth/tb/eth_axis_tx/test_eth_axis_tx.py b/fpga/lib/eth/tb/eth_axis_tx/test_eth_axis_tx.py index 8a2358c35..7e3512b06 100644 --- a/fpga/lib/eth/tb/eth_axis_tx/test_eth_axis_tx.py +++ b/fpga/lib/eth/tb/eth_axis_tx/test_eth_axis_tx.py @@ -134,7 +134,7 @@ def cycle_pause(): def size_list(): - return list(range(1, 128)) + [512, 1514, 9214] + [60]*10 + return list(range(1, 128)) + [512, 1500, 9200] + [60-14]*10 def incrementing_payload(length): diff --git a/fpga/lib/eth/tb/eth_mac_10g/Makefile b/fpga/lib/eth/tb/eth_mac_10g/Makefile index d9df95bc9..b7144265d 100644 --- a/fpga/lib/eth/tb/eth_mac_10g/Makefile +++ b/fpga/lib/eth/tb/eth_mac_10g/Makefile @@ -1,4 +1,4 @@ -# Copyright (c) 2020 Alex Forencich +# Copyright (c) 2020-2023 Alex Forencich # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal @@ -34,6 +34,10 @@ VERILOG_SOURCES += ../../rtl/axis_xgmii_rx_32.v VERILOG_SOURCES += ../../rtl/axis_xgmii_tx_32.v VERILOG_SOURCES += ../../rtl/axis_xgmii_rx_64.v VERILOG_SOURCES += ../../rtl/axis_xgmii_tx_64.v +VERILOG_SOURCES += ../../rtl/mac_ctrl_rx.v +VERILOG_SOURCES += ../../rtl/mac_ctrl_tx.v +VERILOG_SOURCES += ../../rtl/mac_pause_ctrl_rx.v +VERILOG_SOURCES += ../../rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters @@ -49,10 +53,12 @@ export PARAM_TX_PTP_TS_ENABLE := 1 export PARAM_TX_PTP_TS_WIDTH := 96 export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) export PARAM_TX_PTP_TAG_WIDTH := 16 -export PARAM_RX_PTP_TS_ENABLE := 1 +export PARAM_RX_PTP_TS_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) export PARAM_RX_PTP_TS_WIDTH := 96 -export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_TX_PTP_TAG_WIDTH) + 1 )) +export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TS_ENABLE)),1,$(shell expr $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),0,$(PARAM_TX_PTP_TAG_WIDTH)) + $(if $(filter-out 1,$(TX_PTP_TS_CTRL_IN_TUSER)),0,1) + 1 )) export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_RX_PTP_TS_WIDTH) + 1 )) +export PARAM_PFC_ENABLE := 1 +export PARAM_PAUSE_ENABLE := $(PARAM_PFC_ENABLE) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/eth_mac_10g/test_eth_mac_10g.py b/fpga/lib/eth/tb/eth_mac_10g/test_eth_mac_10g.py index a5fa3a2b3..c4363d464 100644 --- a/fpga/lib/eth/tb/eth_mac_10g/test_eth_mac_10g.py +++ b/fpga/lib/eth/tb/eth_mac_10g/test_eth_mac_10g.py @@ -1,7 +1,7 @@ #!/usr/bin/env python """ -Copyright (c) 2020 Alex Forencich +Copyright (c) 2020-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -25,8 +25,11 @@ THE SOFTWARE. import itertools import logging +import struct import os +from scapy.layers.l2 import Ether + import pytest import cocotb_test.simulator @@ -37,7 +40,7 @@ from cocotb.utils import get_time_from_sim_steps from cocotb.regression import TestFactory from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink, PtpClockSimTime -from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink +from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame from cocotbext.axi.stream import define_stream @@ -72,6 +75,52 @@ class TB: self.tx_ptp_clock = PtpClockSimTime(ts_64=dut.tx_ptp_ts, clock=dut.tx_clk) self.tx_ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "tx_axis_ptp"), dut.tx_clk, dut.tx_rst) + dut.tx_lfc_req.setimmediatevalue(0) + dut.tx_lfc_resend.setimmediatevalue(0) + dut.rx_lfc_en.setimmediatevalue(0) + dut.rx_lfc_ack.setimmediatevalue(0) + + dut.tx_pfc_req.setimmediatevalue(0) + dut.tx_pfc_resend.setimmediatevalue(0) + dut.rx_pfc_en.setimmediatevalue(0) + dut.rx_pfc_ack.setimmediatevalue(0) + + dut.tx_lfc_pause_en.setimmediatevalue(0) + dut.tx_pause_req.setimmediatevalue(0) + + dut.ifg_delay.setimmediatevalue(0) + dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0) + dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0) + dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0) + dut.cfg_mcf_rx_check_eth_dst_ucast.setimmediatevalue(0) + dut.cfg_mcf_rx_eth_src.setimmediatevalue(0) + dut.cfg_mcf_rx_check_eth_src.setimmediatevalue(0) + dut.cfg_mcf_rx_eth_type.setimmediatevalue(0) + dut.cfg_mcf_rx_opcode_lfc.setimmediatevalue(0) + dut.cfg_mcf_rx_check_opcode_lfc.setimmediatevalue(0) + dut.cfg_mcf_rx_opcode_pfc.setimmediatevalue(0) + dut.cfg_mcf_rx_check_opcode_pfc.setimmediatevalue(0) + dut.cfg_mcf_rx_forward.setimmediatevalue(0) + dut.cfg_mcf_rx_enable.setimmediatevalue(0) + dut.cfg_tx_lfc_eth_dst.setimmediatevalue(0) + dut.cfg_tx_lfc_eth_src.setimmediatevalue(0) + dut.cfg_tx_lfc_eth_type.setimmediatevalue(0) + dut.cfg_tx_lfc_opcode.setimmediatevalue(0) + dut.cfg_tx_lfc_en.setimmediatevalue(0) + dut.cfg_tx_lfc_quanta.setimmediatevalue(0) + dut.cfg_tx_lfc_refresh.setimmediatevalue(0) + dut.cfg_tx_pfc_eth_dst.setimmediatevalue(0) + dut.cfg_tx_pfc_eth_src.setimmediatevalue(0) + dut.cfg_tx_pfc_eth_type.setimmediatevalue(0) + dut.cfg_tx_pfc_opcode.setimmediatevalue(0) + dut.cfg_tx_pfc_en.setimmediatevalue(0) + dut.cfg_tx_pfc_quanta.setimmediatevalue(0) + dut.cfg_tx_pfc_refresh.setimmediatevalue(0) + dut.cfg_rx_lfc_opcode.setimmediatevalue(0) + dut.cfg_rx_lfc_en.setimmediatevalue(0) + dut.cfg_rx_pfc_opcode.setimmediatevalue(0) + dut.cfg_rx_pfc_en.setimmediatevalue(0) + async def reset(self): self.dut.rx_rst.setimmediatevalue(0) self.dut.tx_rst.setimmediatevalue(0) @@ -119,6 +168,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns)) assert rx_frame.tdata == test_data assert frame_error == 0 @@ -142,7 +192,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): test_frames = [payload_data(x) for x in payload_lengths()] for test_data in test_frames: - await tb.axis_source.send(test_data) + await tb.axis_source.send(AxiStreamFrame(test_data, tuser=2)) for test_data in test_frames: rx_frame = await tb.xgmii_sink.recv() @@ -158,6 +208,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns)) assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() @@ -181,22 +232,39 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): tb.xgmii_source.ifg = ifg tb.dut.ifg_delay.value = ifg + await tb.reset() + for length in range(60, 92): - await tb.reset() + for k in range(10): + await RisingEdge(dut.tx_clk) test_frames = [payload_data(length) for k in range(10)] start_lane = [] for test_data in test_frames: - await tb.axis_source.send(test_data) + await tb.axis_source.send(AxiStreamFrame(test_data, tuser=2)) for test_data in test_frames: rx_frame = await tb.xgmii_sink.recv() + ptp_ts = await tb.tx_ptp_ts_sink.recv() + + ptp_ts_ns = int(ptp_ts.ts) / 2**16 + + rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns") + + if rx_frame.start_lane == 4: + # start in lane 4 reports 1 full cycle delay, so subtract half clock period + rx_frame_sfd_ns -= 3.2 + + tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) + tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns)) assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() assert rx_frame.ctrl is None + assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period) < 0.01 start_lane.append(rx_frame.start_lane) @@ -240,6 +308,280 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): await RisingEdge(dut.tx_clk) +async def run_test_lfc(dut, ifg=12): + + tb = TB(dut) + + tb.xgmii_source.ifg = ifg + tb.dut.ifg_delay.value = ifg + + await tb.reset() + + dut.tx_lfc_req.value = 0 + dut.tx_lfc_resend.value = 0 + dut.rx_lfc_en.value = 1 + dut.rx_lfc_ack.value = 0 + + dut.tx_lfc_pause_en.value = 1 + dut.tx_pause_req.value = 0 + + dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001 + dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1 + dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5 + dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0 + dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455 + dut.cfg_mcf_rx_check_eth_src.value = 0 + dut.cfg_mcf_rx_eth_type.value = 0x8808 + dut.cfg_mcf_rx_opcode_lfc.value = 0x0001 + dut.cfg_mcf_rx_check_opcode_lfc.value = 1 + dut.cfg_mcf_rx_opcode_pfc.value = 0x0101 + dut.cfg_mcf_rx_check_opcode_pfc.value = 1 + + dut.cfg_mcf_rx_forward.value = 0 + dut.cfg_mcf_rx_enable.value = 1 + + dut.cfg_tx_lfc_eth_dst.value = 0x0180C2000001 + dut.cfg_tx_lfc_eth_src.value = 0x5A5152535455 + dut.cfg_tx_lfc_eth_type.value = 0x8808 + dut.cfg_tx_lfc_opcode.value = 0x0001 + dut.cfg_tx_lfc_en.value = 1 + dut.cfg_tx_lfc_quanta.value = 0xFFFF + dut.cfg_tx_lfc_refresh.value = 0x7F00 + + dut.cfg_rx_lfc_opcode.value = 0x0001 + dut.cfg_rx_lfc_en.value = 1 + + test_tx_pkts = [] + test_rx_pkts = [] + + for k in range(32): + length = 512 + payload = bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000) + test_pkt = eth / payload + test_tx_pkts.append(test_pkt.copy()) + + await tb.axis_source.send(bytes(test_pkt)) + + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000) + test_pkt = eth / payload + test_rx_pkts.append(test_pkt.copy()) + + test_frame = XgmiiFrame.from_payload(bytes(test_pkt)) + await tb.xgmii_source.send(test_frame) + + if k == 16: + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH', 0x0001, 100) + test_rx_pkts.append(test_pkt.copy()) + + test_frame = XgmiiFrame.from_payload(bytes(test_pkt)) + await tb.xgmii_source.send(test_frame) + + for k in range(200): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 1 + + for k in range(200): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 0 + + while not dut.rx_lfc_req.value.integer: + await RisingEdge(dut.tx_clk) + + for k in range(200): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 1 + + for k in range(200): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 0 + + while test_rx_pkts: + rx_frame = await tb.axis_sink.recv() + + rx_pkt = Ether(bytes(rx_frame)) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + if rx_pkt.type == 0x8808: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert rx_frame.tuser[-1] & 1 + else: + assert rx_frame.tuser & 1 + else: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert not rx_frame.tuser[-1] & 1 + else: + assert not rx_frame.tuser & 1 + + tx_lfc_cnt = 0 + + while test_tx_pkts: + tx_frame = await tb.xgmii_sink.recv() + + tx_pkt = Ether(bytes(tx_frame.get_payload())) + + tb.log.info("TX packet: %s", repr(tx_pkt)) + + if tx_pkt.type == 0x8808: + tx_lfc_cnt += 1 + else: + test_pkt = test_tx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(tx_pkt).find(bytes(test_pkt)) == 0 + + assert tx_lfc_cnt == 4 + + assert tb.axis_sink.empty() + assert tb.xgmii_sink.empty() + + await RisingEdge(dut.tx_clk) + await RisingEdge(dut.tx_clk) + + +async def run_test_pfc(dut, ifg=12): + + tb = TB(dut) + + tb.xgmii_source.ifg = ifg + tb.dut.ifg_delay.value = ifg + + await tb.reset() + + dut.tx_pfc_req.value = 0x00 + dut.tx_pfc_resend.value = 0 + dut.rx_pfc_en.value = 0xff + dut.rx_pfc_ack.value = 0x00 + + dut.tx_lfc_pause_en.value = 0 + dut.tx_pause_req.value = 0 + + dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001 + dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1 + dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5 + dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0 + dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455 + dut.cfg_mcf_rx_check_eth_src.value = 0 + dut.cfg_mcf_rx_eth_type.value = 0x8808 + dut.cfg_mcf_rx_opcode_lfc.value = 0x0001 + dut.cfg_mcf_rx_check_opcode_lfc.value = 1 + dut.cfg_mcf_rx_opcode_pfc.value = 0x0101 + dut.cfg_mcf_rx_check_opcode_pfc.value = 1 + + dut.cfg_mcf_rx_forward.value = 0 + dut.cfg_mcf_rx_enable.value = 1 + + dut.cfg_tx_pfc_eth_dst.value = 0x0180C2000001 + dut.cfg_tx_pfc_eth_src.value = 0x5A5152535455 + dut.cfg_tx_pfc_eth_type.value = 0x8808 + dut.cfg_tx_pfc_opcode.value = 0x0101 + dut.cfg_tx_pfc_en.value = 1 + dut.cfg_tx_pfc_quanta.value = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + dut.cfg_tx_pfc_refresh.value = 0x7F007F007F007F007F007F007F007F00 + + dut.cfg_rx_pfc_opcode.value = 0x0101 + dut.cfg_rx_pfc_en.value = 1 + + test_tx_pkts = [] + test_rx_pkts = [] + + for k in range(32): + length = 512 + payload = bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000) + test_pkt = eth / payload + test_tx_pkts.append(test_pkt.copy()) + + await tb.axis_source.send(bytes(test_pkt)) + + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000) + test_pkt = eth / payload + test_rx_pkts.append(test_pkt.copy()) + + test_frame = XgmiiFrame.from_payload(bytes(test_pkt)) + await tb.xgmii_source.send(test_frame) + + if k == 16: + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x00FF, 10, 20, 30, 40, 50, 60, 70, 80) + test_rx_pkts.append(test_pkt.copy()) + + test_frame = XgmiiFrame.from_payload(bytes(test_pkt)) + await tb.xgmii_source.send(test_frame) + + for i in range(8): + for k in range(200): + await RisingEdge(dut.tx_clk) + + dut.tx_pfc_req.value = 0xff >> (7-i) + + for k in range(200): + await RisingEdge(dut.tx_clk) + + dut.tx_pfc_req.value = 0x00 + + while test_rx_pkts: + rx_frame = await tb.axis_sink.recv() + + rx_pkt = Ether(bytes(rx_frame)) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + if rx_pkt.type == 0x8808: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert rx_frame.tuser[-1] & 1 + else: + assert rx_frame.tuser & 1 + else: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert not rx_frame.tuser[-1] & 1 + else: + assert not rx_frame.tuser & 1 + + tx_pfc_cnt = 0 + + while test_tx_pkts: + tx_frame = await tb.xgmii_sink.recv() + + tx_pkt = Ether(bytes(tx_frame.get_payload())) + + tb.log.info("TX packet: %s", repr(tx_pkt)) + + if tx_pkt.type == 0x8808: + tx_pfc_cnt += 1 + else: + test_pkt = test_tx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(tx_pkt).find(bytes(test_pkt)) == 0 + + assert tx_pfc_cnt == 9 + + assert tb.axis_sink.empty() + assert tb.xgmii_sink.empty() + + await RisingEdge(dut.tx_clk) + await RisingEdge(dut.tx_clk) + + def size_list(): return list(range(60, 128)) + [512, 1514, 9214] + [60]*10 @@ -267,6 +609,12 @@ if cocotb.SIM_NAME: factory.add_option("ifg", [12]) factory.generate_tests() + if cocotb.top.PFC_ENABLE.value: + for test in [run_test_lfc, run_test_pfc]: + factory = TestFactory(test) + factory.add_option("ifg", [12]) + factory.generate_tests() + # cocotb-test @@ -276,9 +624,9 @@ lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) -@pytest.mark.parametrize("enable_dic", [1, 0]) +@pytest.mark.parametrize(("enable_dic", "pfc_en"), [(1, 1), (1, 0), (0, 0)]) @pytest.mark.parametrize("data_width", [32, 64]) -def test_eth_mac_10g(request, data_width, enable_dic): +def test_eth_mac_10g(request, data_width, enable_dic, pfc_en): dut = "eth_mac_10g" module = os.path.splitext(os.path.basename(__file__))[0] toplevel = dut @@ -289,6 +637,10 @@ def test_eth_mac_10g(request, data_width, enable_dic): os.path.join(rtl_dir, "axis_xgmii_rx_64.v"), os.path.join(rtl_dir, "axis_xgmii_tx_32.v"), os.path.join(rtl_dir, "axis_xgmii_tx_64.v"), + os.path.join(rtl_dir, "mac_ctrl_rx.v"), + os.path.join(rtl_dir, "mac_ctrl_tx.v"), + os.path.join(rtl_dir, "mac_pause_ctrl_rx.v"), + os.path.join(rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(rtl_dir, "lfsr.v"), ] @@ -304,12 +656,15 @@ def test_eth_mac_10g(request, data_width, enable_dic): parameters['PTP_PERIOD_FNS'] = 0x6666 if parameters['DATA_WIDTH'] == 64 else 0x3333 parameters['TX_PTP_TS_ENABLE'] = 1 parameters['TX_PTP_TS_WIDTH'] = 96 + parameters['TX_PTP_TS_CTRL_IN_TUSER'] = parameters['TX_PTP_TS_ENABLE'] parameters['TX_PTP_TAG_ENABLE'] = parameters['TX_PTP_TS_ENABLE'] parameters['TX_PTP_TAG_WIDTH'] = 16 - parameters['RX_PTP_TS_ENABLE'] = 1 + parameters['RX_PTP_TS_ENABLE'] = parameters['TX_PTP_TS_ENABLE'] parameters['RX_PTP_TS_WIDTH'] = 96 - parameters['TX_USER_WIDTH'] = (parameters['TX_PTP_TAG_WIDTH'] if parameters['TX_PTP_TS_ENABLE'] and parameters['TX_PTP_TAG_ENABLE'] else 0) + 1 + parameters['TX_USER_WIDTH'] = ((parameters['TX_PTP_TAG_WIDTH'] if parameters['TX_PTP_TAG_ENABLE'] else 0) + (1 if parameters['TX_PTP_TS_CTRL_IN_TUSER'] else 0) if parameters['TX_PTP_TS_ENABLE'] else 0) + 1 parameters['RX_USER_WIDTH'] = (parameters['RX_PTP_TS_WIDTH'] if parameters['RX_PTP_TS_ENABLE'] else 0) + 1 + parameters['PFC_ENABLE'] = pfc_en + parameters['PAUSE_ENABLE'] = parameters['PFC_ENABLE'] extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/fpga/lib/eth/tb/eth_mac_10g_fifo/Makefile b/fpga/lib/eth/tb/eth_mac_10g_fifo/Makefile index b7c4c1bf1..ae8109a08 100644 --- a/fpga/lib/eth/tb/eth_mac_10g_fifo/Makefile +++ b/fpga/lib/eth/tb/eth_mac_10g_fifo/Makefile @@ -66,12 +66,13 @@ export PARAM_PTP_PERIOD_NS := 6 export PARAM_PTP_PERIOD_FNS := 26214 export PARAM_PTP_USE_SAMPLE_CLOCK := 0 export PARAM_TX_PTP_TS_ENABLE := 1 -export PARAM_RX_PTP_TS_ENABLE := 1 +export PARAM_RX_PTP_TS_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) +export PARAM_TX_PTP_TS_CTRL_IN_TUSER := $(PARAM_TX_PTP_TS_ENABLE) export PARAM_TX_PTP_TS_FIFO_DEPTH := 64 export PARAM_PTP_TS_WIDTH := 96 export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) export PARAM_PTP_TAG_WIDTH := 16 -export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) +export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TS_ENABLE)),1,$(shell expr $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),0,$(PARAM_PTP_TAG_WIDTH)) + $(if $(filter-out 1,$(TX_PTP_TS_CTRL_IN_TUSER)),0,1) + 1 )) export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) ifeq ($(SIM), icarus) diff --git a/fpga/lib/eth/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py b/fpga/lib/eth/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py index 36338f5a2..eadfe14fa 100644 --- a/fpga/lib/eth/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py +++ b/fpga/lib/eth/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py @@ -37,7 +37,7 @@ from cocotb.utils import get_time_from_sim_steps from cocotb.regression import TestFactory from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink, PtpClockSimTime -from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink +from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame from cocotbext.axi.stream import define_stream @@ -129,6 +129,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns)) assert rx_frame.tdata == test_data assert frame_error == 0 @@ -156,7 +157,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): test_frames = [payload_data(x) for x in payload_lengths()] for test_data in test_frames: - await tb.axis_source.send(test_data) + await tb.axis_source.send(AxiStreamFrame(test_data, tuser=2)) for test_data in test_frames: rx_frame = await tb.xgmii_sink.recv() @@ -172,6 +173,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns)) assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() @@ -195,22 +197,43 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): tb.xgmii_source.ifg = ifg tb.dut.ifg_delay.value = ifg + await tb.reset() + + tb.log.info("Wait for PTP CDC lock") + while not dut.tx_ptp.tx_ptp_cdc.locked.value.integer: + await RisingEdge(dut.tx_clk) + for length in range(60, 92): - await tb.reset() + for k in range(10): + await RisingEdge(dut.tx_clk) test_frames = [payload_data(length) for k in range(10)] start_lane = [] for test_data in test_frames: - await tb.axis_source.send(test_data) + await tb.axis_source.send(AxiStreamFrame(test_data, tuser=2)) for test_data in test_frames: rx_frame = await tb.xgmii_sink.recv() + ptp_ts = await tb.tx_ptp_ts_sink.recv() + + ptp_ts_ns = int(ptp_ts.ts_96) / 2**16 + + rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns") + + if rx_frame.start_lane == 4: + # start in lane 4 reports 1 full cycle delay, so subtract half clock period + rx_frame_sfd_ns -= 3.2 + + tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) + tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns)) assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() assert rx_frame.ctrl is None + assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period) < tb.clk_period start_lane.append(rx_frame.start_lane) @@ -337,12 +360,13 @@ def test_eth_mac_10g_fifo(request, data_width, enable_dic): parameters['PTP_PERIOD_FNS'] = 0x6666 if parameters['DATA_WIDTH'] == 64 else 0x3333 parameters['PTP_USE_SAMPLE_CLOCK'] = 0 parameters['TX_PTP_TS_ENABLE'] = 1 - parameters['RX_PTP_TS_ENABLE'] = 1 + parameters['RX_PTP_TS_ENABLE'] = parameters['TX_PTP_TS_ENABLE'] + parameters['TX_PTP_TS_CTRL_IN_TUSER'] = parameters['TX_PTP_TS_ENABLE'] parameters['TX_PTP_TS_FIFO_DEPTH'] = 64 parameters['PTP_TS_WIDTH'] = 96 parameters['TX_PTP_TAG_ENABLE'] = parameters['TX_PTP_TS_ENABLE'] parameters['PTP_TAG_WIDTH'] = 16 - parameters['TX_USER_WIDTH'] = (parameters['PTP_TAG_WIDTH'] if parameters['TX_PTP_TS_ENABLE'] and parameters['TX_PTP_TAG_ENABLE'] else 0) + 1 + parameters['TX_USER_WIDTH'] = ((parameters['PTP_TAG_WIDTH'] if parameters['TX_PTP_TAG_ENABLE'] else 0) + (1 if parameters['TX_PTP_TS_CTRL_IN_TUSER'] else 0) if parameters['TX_PTP_TS_ENABLE'] else 0) + 1 parameters['RX_USER_WIDTH'] = (parameters['PTP_TS_WIDTH'] if parameters['RX_PTP_TS_ENABLE'] else 0) + 1 extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/fpga/lib/eth/tb/eth_mac_1g/Makefile b/fpga/lib/eth/tb/eth_mac_1g/Makefile index 3c8e9186c..b3475f7cd 100644 --- a/fpga/lib/eth/tb/eth_mac_1g/Makefile +++ b/fpga/lib/eth/tb/eth_mac_1g/Makefile @@ -1,4 +1,4 @@ -# Copyright (c) 2020 Alex Forencich +# Copyright (c) 2020-2023 Alex Forencich # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal @@ -32,22 +32,27 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/axis_gmii_rx.v VERILOG_SOURCES += ../../rtl/axis_gmii_tx.v +VERILOG_SOURCES += ../../rtl/mac_ctrl_rx.v +VERILOG_SOURCES += ../../rtl/mac_ctrl_tx.v +VERILOG_SOURCES += ../../rtl/mac_pause_ctrl_rx.v +VERILOG_SOURCES += ../../rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters export PARAM_DATA_WIDTH := 8 export PARAM_ENABLE_PADDING := 1 export PARAM_MIN_FRAME_LENGTH := 64 -export PARAM_TX_PTP_TS_ENABLE := 0 +export PARAM_TX_PTP_TS_ENABLE := 1 export PARAM_TX_PTP_TS_WIDTH := 96 +export PARAM_TX_PTP_TS_CTRL_IN_TUSER := $(PARAM_TX_PTP_TS_ENABLE) export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) export PARAM_TX_PTP_TAG_WIDTH := 16 -export PARAM_RX_PTP_TS_ENABLE := 0 +export PARAM_RX_PTP_TS_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) export PARAM_RX_PTP_TS_WIDTH := 96 -# export PARAM_TX_USER_WIDTH := (TX_PTP_TAG_WIDTH if TX_PTP_TAG_ENABLE else 0) + 1 -export PARAM_TX_USER_WIDTH := 1 -# export PARAM_RX_USER_WIDTH := (RX_PTP_TS_WIDTH if RX_PTP_TS_ENABLE else 0) + 1 -export PARAM_RX_USER_WIDTH := 1 +export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TS_ENABLE)),1,$(shell expr $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),0,$(PARAM_TX_PTP_TAG_WIDTH)) + $(if $(filter-out 1,$(TX_PTP_TS_CTRL_IN_TUSER)),0,1) + 1 )) +export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_TX_PTP_TS_WIDTH) + 1 )) +export PARAM_PFC_ENABLE := 1 +export PARAM_PAUSE_ENABLE := $(PARAM_PFC_ENABLE) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/fpga/lib/eth/tb/eth_mac_1g/test_eth_mac_1g.py b/fpga/lib/eth/tb/eth_mac_1g/test_eth_mac_1g.py index 24b15ed27..ab0a48919 100644 --- a/fpga/lib/eth/tb/eth_mac_1g/test_eth_mac_1g.py +++ b/fpga/lib/eth/tb/eth_mac_1g/test_eth_mac_1g.py @@ -1,7 +1,7 @@ #!/usr/bin/env python """ -Copyright (c) 2020 Alex Forencich +Copyright (c) 2020-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -25,17 +25,29 @@ THE SOFTWARE. import itertools import logging +import struct import os +from scapy.layers.l2 import Ether + +import pytest import cocotb_test.simulator import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge +from cocotb.utils import get_time_from_sim_steps from cocotb.regression import TestFactory -from cocotbext.eth import GmiiFrame, GmiiSource, GmiiSink -from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink +from cocotbext.eth import GmiiFrame, GmiiSource, GmiiSink, PtpClockSimTime +from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame +from cocotbext.axi.stream import define_stream + + +PtpTsBus, PtpTsTransaction, PtpTsSource, PtpTsSink, PtpTsMonitor = define_stream("PtpTs", + signals=["ts", "ts_valid"], + optional_signals=["ts_tag", "ts_ready"] +) class TB: @@ -61,13 +73,60 @@ class TB: self.axis_source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "tx_axis"), dut.tx_clk, dut.tx_rst) self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst) + self.rx_ptp_clock = PtpClockSimTime(ts_64=dut.rx_ptp_ts, clock=dut.rx_clk) + self.tx_ptp_clock = PtpClockSimTime(ts_64=dut.tx_ptp_ts, clock=dut.tx_clk) + self.tx_ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "tx_axis_ptp"), dut.tx_clk, dut.tx_rst) + + dut.tx_lfc_req.setimmediatevalue(0) + dut.tx_lfc_resend.setimmediatevalue(0) + dut.rx_lfc_en.setimmediatevalue(0) + dut.rx_lfc_ack.setimmediatevalue(0) + + dut.tx_pfc_req.setimmediatevalue(0) + dut.tx_pfc_resend.setimmediatevalue(0) + dut.rx_pfc_en.setimmediatevalue(0) + dut.rx_pfc_ack.setimmediatevalue(0) + + dut.tx_lfc_pause_en.setimmediatevalue(0) + dut.tx_pause_req.setimmediatevalue(0) + dut.rx_clk_enable.setimmediatevalue(1) dut.tx_clk_enable.setimmediatevalue(1) dut.rx_mii_select.setimmediatevalue(0) dut.tx_mii_select.setimmediatevalue(0) - dut.rx_ptp_ts.setimmediatevalue(0) - dut.tx_ptp_ts.setimmediatevalue(0) + dut.ifg_delay.setimmediatevalue(0) + dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0) + dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0) + dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0) + dut.cfg_mcf_rx_check_eth_dst_ucast.setimmediatevalue(0) + dut.cfg_mcf_rx_eth_src.setimmediatevalue(0) + dut.cfg_mcf_rx_check_eth_src.setimmediatevalue(0) + dut.cfg_mcf_rx_eth_type.setimmediatevalue(0) + dut.cfg_mcf_rx_opcode_lfc.setimmediatevalue(0) + dut.cfg_mcf_rx_check_opcode_lfc.setimmediatevalue(0) + dut.cfg_mcf_rx_opcode_pfc.setimmediatevalue(0) + dut.cfg_mcf_rx_check_opcode_pfc.setimmediatevalue(0) + dut.cfg_mcf_rx_forward.setimmediatevalue(0) + dut.cfg_mcf_rx_enable.setimmediatevalue(0) + dut.cfg_tx_lfc_eth_dst.setimmediatevalue(0) + dut.cfg_tx_lfc_eth_src.setimmediatevalue(0) + dut.cfg_tx_lfc_eth_type.setimmediatevalue(0) + dut.cfg_tx_lfc_opcode.setimmediatevalue(0) + dut.cfg_tx_lfc_en.setimmediatevalue(0) + dut.cfg_tx_lfc_quanta.setimmediatevalue(0) + dut.cfg_tx_lfc_refresh.setimmediatevalue(0) + dut.cfg_tx_pfc_eth_dst.setimmediatevalue(0) + dut.cfg_tx_pfc_eth_src.setimmediatevalue(0) + dut.cfg_tx_pfc_eth_type.setimmediatevalue(0) + dut.cfg_tx_pfc_opcode.setimmediatevalue(0) + dut.cfg_tx_pfc_en.setimmediatevalue(0) + dut.cfg_tx_pfc_quanta.setimmediatevalue(0) + dut.cfg_tx_pfc_refresh.setimmediatevalue(0) + dut.cfg_rx_lfc_opcode.setimmediatevalue(0) + dut.cfg_rx_lfc_en.setimmediatevalue(0) + dut.cfg_rx_pfc_opcode.setimmediatevalue(0) + dut.cfg_rx_pfc_en.setimmediatevalue(0) async def reset(self): self.dut.rx_rst.setimmediatevalue(0) @@ -136,16 +195,29 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enab await tb.reset() test_frames = [payload_data(x) for x in payload_lengths()] + tx_frames = [] for test_data in test_frames: - test_frame = GmiiFrame.from_payload(test_data) + test_frame = GmiiFrame.from_payload(test_data, tx_complete=tx_frames.append) await tb.gmii_source.send(test_frame) for test_data in test_frames: rx_frame = await tb.axis_sink.recv() + tx_frame = tx_frames.pop(0) + + frame_error = rx_frame.tuser & 1 + ptp_ts = rx_frame.tuser >> 1 + ptp_ts_ns = ptp_ts / 2**16 + + tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns") + + tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns) + tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns)) assert rx_frame.tdata == test_data - assert rx_frame.tuser == 0 + assert frame_error == 0 + assert abs(ptp_ts_ns - tx_frame_sfd_ns - (32 if enable_gen else 8)) < 0.01 assert tb.axis_sink.empty() @@ -171,14 +243,24 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enab test_frames = [payload_data(x) for x in payload_lengths()] for test_data in test_frames: - await tb.axis_source.send(test_data) + await tb.axis_source.send(AxiStreamFrame(test_data, tuser=2)) for test_data in test_frames: rx_frame = await tb.gmii_sink.recv() + ptp_ts = await tb.tx_ptp_ts_sink.recv() + + ptp_ts_ns = int(ptp_ts.ts) / 2**16 + + rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns") + + tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) + tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns)) assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() assert rx_frame.error is None + assert abs(rx_frame_sfd_ns - ptp_ts_ns - (32 if enable_gen else 8)) < 0.01 assert tb.gmii_sink.empty() @@ -186,6 +268,292 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enab await RisingEdge(dut.tx_clk) +async def run_test_lfc(dut, ifg=12, enable_gen=None, mii_sel=True): + + tb = TB(dut) + + tb.gmii_source.ifg = ifg + tb.dut.ifg_delay.value = ifg + tb.dut.rx_mii_select.value = mii_sel + tb.dut.tx_mii_select.value = mii_sel + + if enable_gen is not None: + tb.set_enable_generator_rx(enable_gen()) + tb.set_enable_generator_tx(enable_gen()) + + await tb.reset() + + dut.tx_lfc_req.value = 0 + dut.tx_lfc_resend.value = 0 + dut.rx_lfc_en.value = 1 + dut.rx_lfc_ack.value = 0 + + dut.tx_lfc_pause_en.value = 1 + dut.tx_pause_req.value = 0 + + dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001 + dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1 + dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5 + dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0 + dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455 + dut.cfg_mcf_rx_check_eth_src.value = 0 + dut.cfg_mcf_rx_eth_type.value = 0x8808 + dut.cfg_mcf_rx_opcode_lfc.value = 0x0001 + dut.cfg_mcf_rx_check_opcode_lfc.value = 1 + dut.cfg_mcf_rx_opcode_pfc.value = 0x0101 + dut.cfg_mcf_rx_check_opcode_pfc.value = 1 + + dut.cfg_mcf_rx_forward.value = 0 + dut.cfg_mcf_rx_enable.value = 1 + + dut.cfg_tx_lfc_eth_dst.value = 0x0180C2000001 + dut.cfg_tx_lfc_eth_src.value = 0x5A5152535455 + dut.cfg_tx_lfc_eth_type.value = 0x8808 + dut.cfg_tx_lfc_opcode.value = 0x0001 + dut.cfg_tx_lfc_en.value = 1 + dut.cfg_tx_lfc_quanta.value = 0xFFFF + dut.cfg_tx_lfc_refresh.value = 0x7F00 + + dut.cfg_rx_lfc_opcode.value = 0x0001 + dut.cfg_rx_lfc_en.value = 1 + + test_tx_pkts = [] + test_rx_pkts = [] + + for k in range(32): + length = 128 + payload = bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000) + test_pkt = eth / payload + test_tx_pkts.append(test_pkt.copy()) + + await tb.axis_source.send(bytes(test_pkt)) + + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000) + test_pkt = eth / payload + test_rx_pkts.append(test_pkt.copy()) + + test_frame = GmiiFrame.from_payload(bytes(test_pkt)) + await tb.gmii_source.send(test_frame) + + if k == 16: + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH', 0x0001, 100) + test_rx_pkts.append(test_pkt.copy()) + + test_frame = GmiiFrame.from_payload(bytes(test_pkt)) + await tb.gmii_source.send(test_frame) + + for k in range(1000): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 1 + + for k in range(1000): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 0 + + while not dut.rx_lfc_req.value.integer: + await RisingEdge(dut.tx_clk) + + for k in range(1000): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 1 + + for k in range(1000): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 0 + + while test_rx_pkts: + rx_frame = await tb.axis_sink.recv() + + rx_pkt = Ether(bytes(rx_frame)) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + if rx_pkt.type == 0x8808: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert rx_frame.tuser[-1] & 1 + else: + assert rx_frame.tuser & 1 + else: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert not rx_frame.tuser[-1] & 1 + else: + assert not rx_frame.tuser & 1 + + tx_lfc_cnt = 0 + + while test_tx_pkts: + tx_frame = await tb.gmii_sink.recv() + + tx_pkt = Ether(bytes(tx_frame.get_payload())) + + tb.log.info("TX packet: %s", repr(tx_pkt)) + + if tx_pkt.type == 0x8808: + tx_lfc_cnt += 1 + else: + test_pkt = test_tx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(tx_pkt).find(bytes(test_pkt)) == 0 + + assert tx_lfc_cnt == 4 + + assert tb.axis_sink.empty() + assert tb.gmii_sink.empty() + + await RisingEdge(dut.tx_clk) + await RisingEdge(dut.tx_clk) + + +async def run_test_pfc(dut, ifg=12, enable_gen=None, mii_sel=True): + + tb = TB(dut) + + tb.gmii_source.ifg = ifg + tb.dut.ifg_delay.value = ifg + tb.dut.rx_mii_select.value = mii_sel + tb.dut.tx_mii_select.value = mii_sel + + if enable_gen is not None: + tb.set_enable_generator_rx(enable_gen()) + tb.set_enable_generator_tx(enable_gen()) + + await tb.reset() + + dut.tx_pfc_req.value = 0x00 + dut.tx_pfc_resend.value = 0 + dut.rx_pfc_en.value = 0xff + dut.rx_pfc_ack.value = 0 + + dut.tx_lfc_pause_en.value = 0 + dut.tx_pause_req.value = 0 + + dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001 + dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1 + dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5 + dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0 + dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455 + dut.cfg_mcf_rx_check_eth_src.value = 0 + dut.cfg_mcf_rx_eth_type.value = 0x8808 + dut.cfg_mcf_rx_opcode_lfc.value = 0x0001 + dut.cfg_mcf_rx_check_opcode_lfc.value = 1 + dut.cfg_mcf_rx_opcode_pfc.value = 0x0101 + dut.cfg_mcf_rx_check_opcode_pfc.value = 1 + + dut.cfg_mcf_rx_forward.value = 0 + dut.cfg_mcf_rx_enable.value = 1 + + dut.cfg_tx_pfc_eth_dst.value = 0x0180C2000001 + dut.cfg_tx_pfc_eth_src.value = 0x5A5152535455 + dut.cfg_tx_pfc_eth_type.value = 0x8808 + dut.cfg_tx_pfc_opcode.value = 0x0101 + dut.cfg_tx_pfc_en.value = 1 + dut.cfg_tx_pfc_quanta.value = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + dut.cfg_tx_pfc_refresh.value = 0x7F007F007F007F007F007F007F007F00 + + dut.cfg_rx_pfc_opcode.value = 0x0101 + dut.cfg_rx_pfc_en.value = 1 + + test_tx_pkts = [] + test_rx_pkts = [] + + for k in range(32): + length = 128 + payload = bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000) + test_pkt = eth / payload + test_tx_pkts.append(test_pkt.copy()) + + await tb.axis_source.send(bytes(test_pkt)) + + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000) + test_pkt = eth / payload + test_rx_pkts.append(test_pkt.copy()) + + test_frame = GmiiFrame.from_payload(bytes(test_pkt)) + await tb.gmii_source.send(test_frame) + + if k == 16: + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x00FF, 10, 20, 30, 40, 50, 60, 70, 80) + test_rx_pkts.append(test_pkt.copy()) + + test_frame = GmiiFrame.from_payload(bytes(test_pkt)) + await tb.gmii_source.send(test_frame) + + for i in range(8): + for k in range(500): + await RisingEdge(dut.tx_clk) + + dut.tx_pfc_req.value = 0xff >> (7-i) + + for k in range(500): + await RisingEdge(dut.tx_clk) + + dut.tx_pfc_req.value = 0x00 + + while test_rx_pkts: + rx_frame = await tb.axis_sink.recv() + + rx_pkt = Ether(bytes(rx_frame)) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + if rx_pkt.type == 0x8808: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert rx_frame.tuser[-1] & 1 + else: + assert rx_frame.tuser & 1 + else: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert not rx_frame.tuser[-1] & 1 + else: + assert not rx_frame.tuser & 1 + + tx_pfc_cnt = 0 + + while test_tx_pkts: + tx_frame = await tb.gmii_sink.recv() + + tx_pkt = Ether(bytes(tx_frame.get_payload())) + + tb.log.info("TX packet: %s", repr(tx_pkt)) + + if tx_pkt.type == 0x8808: + tx_pfc_cnt += 1 + else: + test_pkt = test_tx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(tx_pkt).find(bytes(test_pkt)) == 0 + + assert tx_pfc_cnt > 2 and tx_pfc_cnt <= 9 + + assert tb.axis_sink.empty() + assert tb.gmii_sink.empty() + + await RisingEdge(dut.tx_clk) + await RisingEdge(dut.tx_clk) + + def size_list(): return list(range(60, 128)) + [512, 1514] + [60]*10 @@ -210,6 +578,14 @@ if cocotb.SIM_NAME: factory.add_option("mii_sel", [False, True]) factory.generate_tests() + if cocotb.top.PFC_ENABLE.value: + for test in [run_test_lfc, run_test_pfc]: + factory = TestFactory(test) + factory.add_option("ifg", [12]) + factory.add_option("enable_gen", [None, cycle_en]) + factory.add_option("mii_sel", [False, True]) + factory.generate_tests() + # cocotb-test @@ -219,7 +595,8 @@ lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) -def test_eth_mac_1g(request): +@pytest.mark.parametrize("pfc_en", [1, 0]) +def test_eth_mac_1g(request, pfc_en): dut = "eth_mac_1g" module = os.path.splitext(os.path.basename(__file__))[0] toplevel = dut @@ -228,6 +605,10 @@ def test_eth_mac_1g(request): os.path.join(rtl_dir, f"{dut}.v"), os.path.join(rtl_dir, "axis_gmii_rx.v"), os.path.join(rtl_dir, "axis_gmii_tx.v"), + os.path.join(rtl_dir, "mac_ctrl_rx.v"), + os.path.join(rtl_dir, "mac_ctrl_tx.v"), + os.path.join(rtl_dir, "mac_pause_ctrl_rx.v"), + os.path.join(rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(rtl_dir, "lfsr.v"), ] @@ -236,14 +617,17 @@ def test_eth_mac_1g(request): parameters['DATA_WIDTH'] = 8 parameters['ENABLE_PADDING'] = 1 parameters['MIN_FRAME_LENGTH'] = 64 - parameters['TX_PTP_TS_ENABLE'] = 0 + parameters['TX_PTP_TS_ENABLE'] = 1 parameters['TX_PTP_TS_WIDTH'] = 96 + parameters['TX_PTP_TS_CTRL_IN_TUSER'] = parameters['TX_PTP_TS_ENABLE'] parameters['TX_PTP_TAG_ENABLE'] = parameters['TX_PTP_TS_ENABLE'] parameters['TX_PTP_TAG_WIDTH'] = 16 - parameters['RX_PTP_TS_ENABLE'] = 0 + parameters['RX_PTP_TS_ENABLE'] = parameters['TX_PTP_TS_ENABLE'] parameters['RX_PTP_TS_WIDTH'] = 96 - parameters['TX_USER_WIDTH'] = (parameters['TX_PTP_TAG_WIDTH'] if parameters['TX_PTP_TAG_ENABLE'] else 0) + 1 + parameters['TX_USER_WIDTH'] = ((parameters['TX_PTP_TAG_WIDTH'] if parameters['TX_PTP_TAG_ENABLE'] else 0) + (1 if parameters['TX_PTP_TS_CTRL_IN_TUSER'] else 0) if parameters['TX_PTP_TS_ENABLE'] else 0) + 1 parameters['RX_USER_WIDTH'] = (parameters['RX_PTP_TS_WIDTH'] if parameters['RX_PTP_TS_ENABLE'] else 0) + 1 + parameters['PFC_ENABLE'] = pfc_en + parameters['PAUSE_ENABLE'] = parameters['PFC_ENABLE'] extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/fpga/lib/eth/tb/eth_mac_phy_10g/Makefile b/fpga/lib/eth/tb/eth_mac_phy_10g/Makefile index a6747924b..e5dec6fd2 100644 --- a/fpga/lib/eth/tb/eth_mac_phy_10g/Makefile +++ b/fpga/lib/eth/tb/eth_mac_phy_10g/Makefile @@ -52,11 +52,12 @@ export PARAM_PTP_PERIOD_NS := 6 export PARAM_PTP_PERIOD_FNS := 26214 export PARAM_TX_PTP_TS_ENABLE := 1 export PARAM_TX_PTP_TS_WIDTH := 96 +export PARAM_TX_PTP_TS_CTRL_IN_TUSER := $(PARAM_TX_PTP_TS_ENABLE) export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) export PARAM_TX_PTP_TAG_WIDTH := 16 -export PARAM_RX_PTP_TS_ENABLE := 1 +export PARAM_RX_PTP_TS_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) export PARAM_RX_PTP_TS_WIDTH := 96 -export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_TX_PTP_TAG_WIDTH) + 1 )) +export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TS_ENABLE)),1,$(shell expr $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),0,$(PARAM_TX_PTP_TAG_WIDTH)) + $(if $(filter-out 1,$(TX_PTP_TS_CTRL_IN_TUSER)),0,1) + 1 )) export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_RX_PTP_TS_WIDTH) + 1 )) export PARAM_BIT_REVERSE := 0 export PARAM_SCRAMBLER_DISABLE := 0 diff --git a/fpga/lib/eth/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py b/fpga/lib/eth/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py index f5a65d80d..bda5fec48 100644 --- a/fpga/lib/eth/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py +++ b/fpga/lib/eth/tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py @@ -38,7 +38,7 @@ from cocotb.utils import get_time_from_sim_steps from cocotb.regression import TestFactory from cocotbext.eth import XgmiiFrame, PtpClockSimTime -from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink +from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame from cocotbext.axi.stream import define_stream try: @@ -142,6 +142,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns)) assert rx_frame.tdata == test_data assert frame_error == 0 @@ -165,7 +166,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): test_frames = [payload_data(x) for x in payload_lengths()] for test_data in test_frames: - await tb.axis_source.send(test_data) + await tb.axis_source.send(AxiStreamFrame(test_data, tuser=2)) for test_data in test_frames: rx_frame = await tb.serdes_sink.recv() @@ -181,6 +182,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns)) assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() @@ -204,22 +206,39 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): tb.serdes_source.ifg = ifg tb.dut.ifg_delay.value = ifg + await tb.reset() + for length in range(60, 92): - await tb.reset() + for k in range(10): + await RisingEdge(dut.tx_clk) test_frames = [payload_data(length) for k in range(10)] start_lane = [] for test_data in test_frames: - await tb.axis_source.send(test_data) + await tb.axis_source.send(AxiStreamFrame(test_data, tuser=2)) for test_data in test_frames: rx_frame = await tb.serdes_sink.recv() + ptp_ts = await tb.tx_ptp_ts_sink.recv() + + ptp_ts_ns = int(ptp_ts.ts) / 2**16 + + rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns") + + if rx_frame.start_lane == 4: + # start in lane 4 reports 1 full cycle delay, so subtract half clock period + rx_frame_sfd_ns -= 3.2 + + tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) + tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns)) assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() assert rx_frame.ctrl is None + assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*5) < 0.01 start_lane.append(rx_frame.start_lane) @@ -373,11 +392,12 @@ def test_eth_mac_phy_10g(request, data_width, enable_dic): parameters['PTP_PERIOD_FNS'] = 0x6666 if parameters['DATA_WIDTH'] == 64 else 0x3333 parameters['TX_PTP_TS_ENABLE'] = 1 parameters['TX_PTP_TS_WIDTH'] = 96 + parameters['TX_PTP_TS_CTRL_IN_TUSER'] = parameters['TX_PTP_TS_ENABLE'] parameters['TX_PTP_TAG_ENABLE'] = parameters['TX_PTP_TS_ENABLE'] parameters['TX_PTP_TAG_WIDTH'] = 16 - parameters['RX_PTP_TS_ENABLE'] = 1 + parameters['RX_PTP_TS_ENABLE'] = parameters['TX_PTP_TS_ENABLE'] parameters['RX_PTP_TS_WIDTH'] = 96 - parameters['TX_USER_WIDTH'] = (parameters['TX_PTP_TAG_WIDTH'] if parameters['TX_PTP_TS_ENABLE'] and parameters['TX_PTP_TAG_ENABLE'] else 0) + 1 + parameters['TX_USER_WIDTH'] = ((parameters['TX_PTP_TAG_WIDTH'] if parameters['TX_PTP_TAG_ENABLE'] else 0) + (1 if parameters['TX_PTP_TS_CTRL_IN_TUSER'] else 0) if parameters['TX_PTP_TS_ENABLE'] else 0) + 1 parameters['RX_USER_WIDTH'] = (parameters['RX_PTP_TS_WIDTH'] if parameters['RX_PTP_TS_ENABLE'] else 0) + 1 parameters['BIT_REVERSE'] = 0 parameters['SCRAMBLER_DISABLE'] = 0 diff --git a/fpga/lib/eth/tb/eth_mac_phy_10g_fifo/Makefile b/fpga/lib/eth/tb/eth_mac_phy_10g_fifo/Makefile index c74477c68..c44570970 100644 --- a/fpga/lib/eth/tb/eth_mac_phy_10g_fifo/Makefile +++ b/fpga/lib/eth/tb/eth_mac_phy_10g_fifo/Makefile @@ -71,12 +71,13 @@ export PARAM_PTP_PERIOD_NS := 6 export PARAM_PTP_PERIOD_FNS := 26214 export PARAM_PTP_USE_SAMPLE_CLOCK := 0 export PARAM_TX_PTP_TS_ENABLE := 1 -export PARAM_RX_PTP_TS_ENABLE := 1 +export PARAM_RX_PTP_TS_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) +export PARAM_TX_PTP_TS_CTRL_IN_TUSER := $(PARAM_TX_PTP_TS_ENABLE) export PARAM_TX_PTP_TS_FIFO_DEPTH := 64 export PARAM_PTP_TS_WIDTH := 96 export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) export PARAM_PTP_TAG_WIDTH := 16 -export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),1,$(shell expr $(PARAM_PTP_TAG_WIDTH) + 1 )) +export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TS_ENABLE)),1,$(shell expr $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),0,$(PARAM_PTP_TAG_WIDTH)) + $(if $(filter-out 1,$(TX_PTP_TS_CTRL_IN_TUSER)),0,1) + 1 )) export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 )) export PARAM_BIT_REVERSE := 0 export PARAM_SCRAMBLER_DISABLE := 0 diff --git a/fpga/lib/eth/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py b/fpga/lib/eth/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py index 1c553227f..70abb425b 100644 --- a/fpga/lib/eth/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py +++ b/fpga/lib/eth/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py @@ -38,7 +38,7 @@ from cocotb.utils import get_time_from_sim_steps from cocotb.regression import TestFactory from cocotbext.eth import XgmiiFrame, PtpClockSimTime -from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink +from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame from cocotbext.axi.stream import define_stream try: @@ -150,6 +150,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns)) assert rx_frame.tdata == test_data assert frame_error == 0 @@ -177,7 +178,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): test_frames = [payload_data(x) for x in payload_lengths()] for test_data in test_frames: - await tb.axis_source.send(test_data) + await tb.axis_source.send(AxiStreamFrame(test_data, tuser=2)) for test_data in test_frames: rx_frame = await tb.serdes_sink.recv() @@ -193,6 +194,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns)) assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() @@ -216,22 +218,43 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): tb.serdes_source.ifg = ifg tb.dut.ifg_delay.value = ifg + await tb.reset() + + tb.log.info("Wait for PTP CDC lock") + while not dut.tx_ptp.tx_ptp_cdc.locked.value.integer: + await RisingEdge(dut.tx_clk) + for length in range(60, 92): - await tb.reset() + for k in range(10): + await RisingEdge(dut.tx_clk) test_frames = [payload_data(length) for k in range(10)] start_lane = [] for test_data in test_frames: - await tb.axis_source.send(test_data) + await tb.axis_source.send(AxiStreamFrame(test_data, tuser=2)) for test_data in test_frames: rx_frame = await tb.serdes_sink.recv() + ptp_ts = await tb.tx_ptp_ts_sink.recv() + + ptp_ts_ns = int(ptp_ts.ts_96) / 2**16 + + rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns") + + if rx_frame.start_lane == 4: + # start in lane 4 reports 1 full cycle delay, so subtract half clock period + rx_frame_sfd_ns -= 3.2 + + tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns) + tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns)) assert rx_frame.get_payload() == test_data assert rx_frame.check_fcs() assert rx_frame.ctrl is None + assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*5) < tb.clk_period start_lane.append(rx_frame.start_lane) @@ -404,12 +427,13 @@ def test_eth_mac_phy_10g_fifo(request, data_width, enable_dic): parameters['PTP_PERIOD_FNS'] = 0x6666 if parameters['DATA_WIDTH'] == 64 else 0x3333 parameters['PTP_USE_SAMPLE_CLOCK'] = 0 parameters['TX_PTP_TS_ENABLE'] = 1 - parameters['RX_PTP_TS_ENABLE'] = 1 + parameters['RX_PTP_TS_ENABLE'] = parameters['TX_PTP_TS_ENABLE'] + parameters['TX_PTP_TS_CTRL_IN_TUSER'] = parameters['TX_PTP_TS_ENABLE'] parameters['TX_PTP_TS_FIFO_DEPTH'] = 64 parameters['PTP_TS_WIDTH'] = 96 parameters['TX_PTP_TAG_ENABLE'] = parameters['TX_PTP_TS_ENABLE'] parameters['PTP_TAG_WIDTH'] = 16 - parameters['TX_USER_WIDTH'] = (parameters['PTP_TAG_WIDTH'] if parameters['TX_PTP_TS_ENABLE'] and parameters['TX_PTP_TAG_ENABLE'] else 0) + 1 + parameters['TX_USER_WIDTH'] = ((parameters['PTP_TAG_WIDTH'] if parameters['TX_PTP_TAG_ENABLE'] else 0) + (1 if parameters['TX_PTP_TS_CTRL_IN_TUSER'] else 0) if parameters['TX_PTP_TS_ENABLE'] else 0) + 1 parameters['RX_USER_WIDTH'] = (parameters['PTP_TS_WIDTH'] if parameters['RX_PTP_TS_ENABLE'] else 0) + 1 parameters['BIT_REVERSE'] = 0 parameters['SCRAMBLER_DISABLE'] = 0 diff --git a/fpga/lib/eth/tb/mac_ctrl_rx/Makefile b/fpga/lib/eth/tb/mac_ctrl_rx/Makefile new file mode 100644 index 000000000..da1157add --- /dev/null +++ b/fpga/lib/eth/tb/mac_ctrl_rx/Makefile @@ -0,0 +1,78 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +TOPLEVEL_LANG = verilog + +SIM ?= icarus +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = mac_ctrl_rx +TOPLEVEL = $(DUT) +MODULE = test_$(DUT) +VERILOG_SOURCES += ../../rtl/$(DUT).v + +# module parameters +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_ID_ENABLE := 1 +export PARAM_ID_WIDTH := 8 +export PARAM_DEST_ENABLE := 1 +export PARAM_DEST_WIDTH := 8 +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 +export PARAM_USE_READY := 1 +export PARAM_MCF_PARAMS_SIZE := 18 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + VERILOG_SOURCES += iverilog_dump.v + COMPILE_ARGS += -s iverilog_dump + endif +else ifeq ($(SIM), verilator) + COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim + +iverilog_dump.v: + echo 'module iverilog_dump();' > $@ + echo 'initial begin' >> $@ + echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ + echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ + echo 'end' >> $@ + echo 'endmodule' >> $@ + +clean:: + @rm -rf iverilog_dump.v + @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/fpga/lib/eth/tb/mac_ctrl_rx/test_mac_ctrl_rx.py b/fpga/lib/eth/tb/mac_ctrl_rx/test_mac_ctrl_rx.py new file mode 100644 index 000000000..241c897b5 --- /dev/null +++ b/fpga/lib/eth/tb/mac_ctrl_rx/test_mac_ctrl_rx.py @@ -0,0 +1,594 @@ +#!/usr/bin/env python +""" + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +""" + +import itertools +import logging +import os +import random + +from scapy.layers.l2 import Ether + +import pytest +import cocotb_test.simulator + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge +from cocotb.regression import TestFactory + +from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame +from cocotbext.axi.stream import define_stream + + +McfBus, McfTransaction, McfSource, McfSink, McfMonitor = define_stream("Mcf", + signals=["valid", "eth_dst", "eth_src", "eth_type", "opcode", "params"], + optional_signals=["ready", "id", "dest", "user"] +) + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 8, units="ns").start()) + + self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis"), dut.clk, dut.rst) + self.sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis"), dut.clk, dut.rst) + self.mcf_sink = McfSink(McfBus.from_prefix(dut, "mcf"), dut.clk, dut.rst) + + dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0) + dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0) + dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0) + dut.cfg_mcf_rx_check_eth_dst_ucast.setimmediatevalue(0) + dut.cfg_mcf_rx_eth_src.setimmediatevalue(0) + dut.cfg_mcf_rx_check_eth_src.setimmediatevalue(0) + dut.cfg_mcf_rx_eth_type.setimmediatevalue(0) + dut.cfg_mcf_rx_opcode_lfc.setimmediatevalue(0) + dut.cfg_mcf_rx_check_opcode_lfc.setimmediatevalue(0) + dut.cfg_mcf_rx_opcode_pfc.setimmediatevalue(0) + dut.cfg_mcf_rx_check_opcode_pfc.setimmediatevalue(0) + + dut.cfg_mcf_rx_forward.setimmediatevalue(0) + dut.cfg_mcf_rx_enable.setimmediatevalue(0) + + def set_idle_generator(self, generator=None): + if generator: + self.source.set_pause_generator(generator()) + + def set_backpressure_generator(self, generator=None): + if generator: + self.sink.set_pause_generator(generator()) + + async def reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + async def send(self, pkt): + await self.source.send(bytes(pkt)) + + async def recv(self): + rx_frame = await self.sink.recv() + + assert not rx_frame.tuser + + return Ether(bytes(rx_frame)) + + async def recv_mcf(self): + rx_frame = await self.mcf_sink.recv() + + data = bytearray() + data.extend(rx_frame.eth_dst.integer.to_bytes(6, 'big')) + data.extend(rx_frame.eth_src.integer.to_bytes(6, 'big')) + data.extend(rx_frame.eth_type.integer.to_bytes(2, 'big')) + data.extend(rx_frame.opcode.integer.to_bytes(2, 'big')) + data.extend(rx_frame.params.integer.to_bytes(44, 'little')) + + return Ether(data) + + +async def run_test_data(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + id_width = len(tb.source.bus.tid) + id_count = 2**id_width + id_mask = id_count-1 + + src_width = 1 + src_mask = 2**src_width-1 if src_width else 0 + src_shift = id_width-src_width + max_count = 2**src_shift + count_mask = max_count-1 + + cur_id = 1 + + await tb.reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + test_frames = [] + + for test_data in [payload_data(x) for x in payload_lengths()]: + test_frame = AxiStreamFrame(test_data) + test_frame.tid = cur_id + test_frame.tdest = cur_id | (0 << src_shift) + + test_frames.append(test_frame) + await tb.source.send(test_frame) + + cur_id = (cur_id + 1) % max_count + + for test_frame in test_frames: + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_frame.tdata + assert rx_frame.tid == test_frame.tid + assert rx_frame.tdest == test_frame.tdest + assert not rx_frame.tuser + + assert tb.sink.empty() + assert tb.mcf_sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_mcf(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + id_width = len(tb.source.bus.tid) + id_count = 2**id_width + id_mask = id_count-1 + + src_width = 1 + src_mask = 2**src_width-1 if src_width else 0 + src_shift = id_width-src_width + max_count = 2**src_shift + count_mask = max_count-1 + + cur_id = 1 + + await tb.reset() + + dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001 + dut.cfg_mcf_rx_check_eth_dst_mcast.value = 0 + dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5 + dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0 + dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455 + dut.cfg_mcf_rx_check_eth_src.value = 0 + dut.cfg_mcf_rx_eth_type.value = 0x8808 + dut.cfg_mcf_rx_opcode_lfc.value = 0x0001 + dut.cfg_mcf_rx_check_opcode_lfc.value = 0 + dut.cfg_mcf_rx_opcode_pfc.value = 0x0101 + dut.cfg_mcf_rx_check_opcode_pfc.value = 0 + + dut.cfg_mcf_rx_forward.value = 0 + dut.cfg_mcf_rx_enable.value = 1 + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + test_pkts = [] + + for payload in [payload_data(x) for x in payload_lengths()]: + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / (cur_id.to_bytes(2, 'big') + payload) + test_pkts.append((cur_id, test_pkt.copy())) + + test_frame = AxiStreamFrame(bytes(test_pkt)) + test_frame.tid = cur_id + test_frame.tdest = cur_id | (1 << src_shift) + + await tb.source.send(test_frame) + + cur_id = (cur_id + 1) % max_count + + for cur_id, test_pkt in test_pkts: + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == bytes(test_pkt) + assert rx_frame.tid == cur_id + assert rx_frame.tdest == cur_id | (1 << src_shift) + assert rx_frame.tuser + + rx_pkt = await tb.recv_mcf() + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + # check prefix as padding may be different + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + + assert tb.sink.empty() + assert tb.mcf_sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_tuser_assert(dut): + + tb = TB(dut) + + byte_lanes = tb.source.byte_lanes + + await tb.reset() + + dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001 + dut.cfg_mcf_rx_check_eth_dst_mcast.value = 0 + dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5 + dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0 + dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455 + dut.cfg_mcf_rx_check_eth_src.value = 0 + dut.cfg_mcf_rx_eth_type.value = 0x8808 + dut.cfg_mcf_rx_opcode_lfc.value = 0x0001 + dut.cfg_mcf_rx_check_opcode_lfc.value = 0 + dut.cfg_mcf_rx_opcode_pfc.value = 0x0101 + dut.cfg_mcf_rx_check_opcode_pfc.value = 0 + + dut.cfg_mcf_rx_forward.value = 0 + dut.cfg_mcf_rx_enable.value = 1 + + # data + payload = bytearray(itertools.islice(itertools.cycle(range(256)), byte_lanes*16)) + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000) + test_pkt = eth / payload + test_frame = AxiStreamFrame(bytes(test_pkt), tuser=1) + await tb.source.send(test_frame) + + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_frame.tdata + assert rx_frame.tuser + + # MAC control + payload = bytearray(itertools.islice(itertools.cycle(range(256)), 18)) + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / (b'\x00\x00' + payload) + test_frame = AxiStreamFrame(bytes(test_pkt), tuser=1) + await tb.source.send(test_frame) + + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_frame.tdata + assert rx_frame.tuser + + assert tb.sink.empty() + assert tb.mcf_sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_mcf_filter(dut): + + tb = TB(dut) + + await tb.reset() + + dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001 + dut.cfg_mcf_rx_check_eth_dst_mcast.value = 0 + dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5 + dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0 + dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455 + dut.cfg_mcf_rx_check_eth_src.value = 0 + dut.cfg_mcf_rx_eth_type.value = 0x8808 + dut.cfg_mcf_rx_opcode_lfc.value = 0x0001 + dut.cfg_mcf_rx_check_opcode_lfc.value = 0 + dut.cfg_mcf_rx_opcode_pfc.value = 0x0101 + dut.cfg_mcf_rx_check_opcode_pfc.value = 0 + + dut.cfg_mcf_rx_forward.value = 0 + dut.cfg_mcf_rx_enable.value = 1 + + async def check(tb, pkt, should_match): + await tb.source.send(bytes(pkt)) + + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == bytes(pkt) + + if should_match: + assert rx_frame.tuser + + rx_pkt = await tb.recv_mcf() + + assert bytes(rx_pkt).find(bytes(pkt)) == 0 + else: + assert not rx_frame.tuser + + assert tb.sink.empty() + assert tb.mcf_sink.empty() + + payload = bytearray(itertools.islice(itertools.cycle(range(256)), 18)) + + # Multicast destination address + dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1 + + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / (b'\x00\x00' + payload) + await check(tb, test_pkt, True) + + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8808) + test_pkt = eth / (b'\x00\x00' + payload) + await check(tb, test_pkt, False) + + dut.cfg_mcf_rx_check_eth_dst_mcast.value = 0 + + # Unicast destination address + dut.cfg_mcf_rx_check_eth_dst_ucast.value = 1 + + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8808) + test_pkt = eth / (b'\x00\x00' + payload) + await check(tb, test_pkt, True) + + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / (b'\x00\x00' + payload) + await check(tb, test_pkt, False) + + dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0 + + # Source address + dut.cfg_mcf_rx_check_eth_src.value = 1 + + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / (b'\x00\x00' + payload) + await check(tb, test_pkt, True) + + eth = Ether(src='5A:51:52:AA:AA:AA', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / (b'\x00\x00' + payload) + await check(tb, test_pkt, False) + + dut.cfg_mcf_rx_check_eth_src.value = 0 + + # Ethertype + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / (b'\x00\x00' + payload) + await check(tb, test_pkt, True) + + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8880) + test_pkt = eth / (b'\x00\x00' + payload) + await check(tb, test_pkt, False) + + # Opcode + dut.cfg_mcf_rx_check_opcode_lfc.value = 1 + dut.cfg_mcf_rx_check_opcode_pfc.value = 1 + + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / (b'\x00\x01' + payload) + await check(tb, test_pkt, True) + + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / (b'\x01\x01' + payload) + await check(tb, test_pkt, True) + + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / (b'\x00\x00' + payload) + await check(tb, test_pkt, False) + + dut.cfg_mcf_rx_check_opcode_lfc.value = 0 + dut.cfg_mcf_rx_check_opcode_pfc.value = 0 + + assert tb.sink.empty() + assert tb.mcf_sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + byte_lanes = tb.source.byte_lanes + id_width = len(tb.source.bus.tid) + id_count = 2**id_width + id_mask = id_count-1 + + src_width = 1 + src_mask = 2**src_width-1 if src_width else 0 + src_shift = id_width-src_width + max_count = 2**src_shift + count_mask = max_count-1 + + cur_id = 1 + + await tb.reset() + + dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001 + dut.cfg_mcf_rx_check_eth_dst_mcast.value = 0 + dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5 + dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0 + dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455 + dut.cfg_mcf_rx_check_eth_src.value = 0 + dut.cfg_mcf_rx_eth_type.value = 0x8808 + dut.cfg_mcf_rx_opcode_lfc.value = 0x0001 + dut.cfg_mcf_rx_check_opcode_lfc.value = 0 + dut.cfg_mcf_rx_opcode_pfc.value = 0x0101 + dut.cfg_mcf_rx_check_opcode_pfc.value = 0 + + dut.cfg_mcf_rx_forward.value = 0 + dut.cfg_mcf_rx_enable.value = 1 + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + test_pkts = [] + + for k in range(256): + if random.randrange(8) != 0: + length = random.randint(1, byte_lanes*16) + payload = bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000) + test_pkt = eth / (cur_id.to_bytes(2, 'big') + payload) + test_pkts.append((cur_id, test_pkt.copy())) + dest = cur_id | (0 << src_shift) + else: + length = random.randint(1, 18) + payload = bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / (cur_id.to_bytes(2, 'big') + payload) + test_pkts.append((cur_id, test_pkt.copy())) + dest = cur_id | (1 << src_shift) + + test_frame = AxiStreamFrame(bytes(test_pkt)) + test_frame.tid = cur_id + test_frame.tdest = dest + + await tb.source.send(test_frame) + + cur_id = (cur_id + 1) % max_count + + for cur_id, test_pkt in test_pkts: + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == bytes(test_pkt) + assert rx_frame.tid == cur_id + assert (rx_frame.tdest & count_mask) == cur_id + + if rx_frame.tdest >> src_shift: + assert rx_frame.tuser + + rx_pkt = await tb.recv_mcf() + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + # check prefix as padding may be different + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + else: + assert not rx_frame.tuser + + for k in range(1000): + await RisingEdge(dut.clk) + + assert tb.sink.empty() + assert tb.mcf_sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +def size_list(): + return list(range(1, 128)) + [512, 1514, 9214] + [60]*10 + + +def mcf_size_list(): + return list(range(1, 19)) + + +def incrementing_payload(length): + return bytes(itertools.islice(itertools.cycle(range(256)), length)) + + +if cocotb.SIM_NAME: + + factory = TestFactory(run_test_data) + factory.add_option("payload_lengths", [size_list]) + factory.add_option("payload_data", [incrementing_payload]) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.generate_tests() + + factory = TestFactory(run_test_mcf) + factory.add_option("payload_lengths", [mcf_size_list]) + factory.add_option("payload_data", [incrementing_payload]) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.generate_tests() + + factory = TestFactory(run_test_tuser_assert) + factory.generate_tests() + + factory = TestFactory(run_test_mcf_filter) + factory.generate_tests() + + factory = TestFactory(run_stress_test) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) + + +@pytest.mark.parametrize("data_width", [8, 16, 32, 64, 128, 256, 512]) +def test_mac_ctrl_rx(request, data_width): + dut = "mac_ctrl_rx" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, f"{dut}.v"), + ] + + parameters = {} + + parameters['DATA_WIDTH'] = data_width + parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) + parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8 + parameters['ID_ENABLE'] = 1 + parameters['ID_WIDTH'] = 8 + parameters['DEST_ENABLE'] = 1 + parameters['DEST_WIDTH'] = 8 + parameters['USER_WIDTH'] = 1 + parameters['USE_READY'] = 1 + parameters['MCF_PARAMS_SIZE'] = 18 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/fpga/lib/eth/tb/mac_ctrl_tx/Makefile b/fpga/lib/eth/tb/mac_ctrl_tx/Makefile new file mode 100644 index 000000000..c97e953aa --- /dev/null +++ b/fpga/lib/eth/tb/mac_ctrl_tx/Makefile @@ -0,0 +1,77 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +TOPLEVEL_LANG = verilog + +SIM ?= icarus +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = mac_ctrl_tx +TOPLEVEL = $(DUT) +MODULE = test_$(DUT) +VERILOG_SOURCES += ../../rtl/$(DUT).v + +# module parameters +export PARAM_DATA_WIDTH := 8 +export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) +export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_ID_ENABLE := 1 +export PARAM_ID_WIDTH := 8 +export PARAM_DEST_ENABLE := 1 +export PARAM_DEST_WIDTH := 8 +export PARAM_USER_ENABLE := 1 +export PARAM_USER_WIDTH := 1 +export PARAM_MCF_PARAMS_SIZE := 18 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + VERILOG_SOURCES += iverilog_dump.v + COMPILE_ARGS += -s iverilog_dump + endif +else ifeq ($(SIM), verilator) + COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim + +iverilog_dump.v: + echo 'module iverilog_dump();' > $@ + echo 'initial begin' >> $@ + echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ + echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ + echo 'end' >> $@ + echo 'endmodule' >> $@ + +clean:: + @rm -rf iverilog_dump.v + @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/fpga/lib/eth/tb/mac_ctrl_tx/test_mac_ctrl_tx.py b/fpga/lib/eth/tb/mac_ctrl_tx/test_mac_ctrl_tx.py new file mode 100644 index 000000000..243fc242f --- /dev/null +++ b/fpga/lib/eth/tb/mac_ctrl_tx/test_mac_ctrl_tx.py @@ -0,0 +1,475 @@ +#!/usr/bin/env python +""" + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +""" + +import itertools +import logging +import os +import random + +from scapy.layers.l2 import Ether +from scapy.utils import mac2str + +import pytest +import cocotb_test.simulator + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import FallingEdge, RisingEdge, Event +from cocotb.regression import TestFactory + +from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame +from cocotbext.axi.stream import define_stream + + +McfBus, McfTransaction, McfSource, McfSink, McfMonitor = define_stream("Mcf", + signals=["valid", "eth_dst", "eth_src", "eth_type", "opcode", "params"], + optional_signals=["ready", "id", "dest", "user"] +) + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 8, units="ns").start()) + + self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis"), dut.clk, dut.rst) + self.sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis"), dut.clk, dut.rst) + self.mcf_source = McfSource(McfBus.from_prefix(dut, "mcf"), dut.clk, dut.rst) + + dut.tx_pause_req.setimmediatevalue(0) + + def set_idle_generator(self, generator=None): + if generator: + self.source.set_pause_generator(generator()) + self.mcf_source.set_pause_generator(generator()) + + def set_backpressure_generator(self, generator=None): + if generator: + self.sink.set_pause_generator(generator()) + + async def reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + async def send(self, pkt): + await self.source.send(bytes(pkt)) + + async def send_mcf(self, pkt): + mcf = McfTransaction() + mcf.eth_dst = int.from_bytes(mac2str(pkt[Ether].dst), 'big') + mcf.eth_src = int.from_bytes(mac2str(pkt[Ether].src), 'big') + mcf.eth_type = pkt[Ether].type + mcf.opcode = int.from_bytes(bytes(pkt[Ether].payload)[0:2], 'big') + mcf.params = int.from_bytes(bytes(pkt[Ether].payload)[2:], 'little') + + await self.mcf_source.send(mcf) + + async def recv(self): + rx_frame = await self.sink.recv() + + assert not rx_frame.tuser + + return Ether(bytes(rx_frame)) + + +async def run_test_data(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + id_width = len(tb.source.bus.tid) + id_count = 2**id_width + id_mask = id_count-1 + + src_width = 1 + src_mask = 2**src_width-1 if src_width else 0 + src_shift = id_width-src_width + max_count = 2**src_shift + count_mask = max_count-1 + + cur_id = 1 + + await tb.reset() + + dut.tx_pause_req.value = 0 + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + test_frames = [] + + for test_data in [payload_data(x) for x in payload_lengths()]: + test_frame = AxiStreamFrame(test_data) + test_frame.tid = cur_id | (0 << src_shift) + test_frame.tdest = cur_id + + test_frames.append(test_frame) + await tb.source.send(test_frame) + + cur_id = (cur_id + 1) % max_count + + for test_frame in test_frames: + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_frame.tdata + assert rx_frame.tid == test_frame.tid + assert rx_frame.tdest == test_frame.tdest + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_mcf(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + await tb.reset() + + dut.tx_pause_req.value = 0 + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + test_pkts = [] + + opcode = 1 + + for payload in [payload_data(x) for x in payload_lengths()]: + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / (opcode.to_bytes(2, 'big') + payload) + test_pkts.append(test_pkt.copy()) + + await tb.send_mcf(test_pkt) + + opcode += 1 + + for test_pkt in test_pkts: + rx_pkt = await tb.recv() + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + + assert tb.sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_tuser_assert(dut): + + tb = TB(dut) + + await tb.reset() + + dut.tx_pause_req.value = 0 + + test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32)) + test_frame = AxiStreamFrame(test_data, tuser=1) + await tb.source.send(test_frame) + + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_frame.tdata + assert rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_arb_test(dut): + + tb = TB(dut) + + byte_lanes = tb.source.byte_lanes + id_width = len(tb.source.bus.tid) + id_count = 2**id_width + id_mask = id_count-1 + + src_width = 1 + src_mask = 2**src_width-1 if src_width else 0 + src_shift = id_width-src_width + max_count = 2**src_shift + count_mask = max_count-1 + + cur_id = 1 + + await tb.reset() + + dut.tx_pause_req.value = 0 + + test_pkts = [] + test_frames = [] + + for k in range(4): + length = byte_lanes*16 + payload = bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000) + test_pkt = eth / (cur_id.to_bytes(2, 'big') + payload) + test_pkts.append((cur_id, test_pkt.copy())) + + test_frame = AxiStreamFrame(bytes(test_pkt), tx_complete=Event()) + test_frame.tid = cur_id | (0 << src_shift) + test_frame.tdest = cur_id + test_frames.append(test_frame) + + await tb.source.send(test_frame) + + cur_id = (cur_id + 1) % max_count + + length = random.randint(1, 18) + payload = bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / (cur_id.to_bytes(2, 'big') + payload) + test_pkts.append((cur_id, test_pkt.copy())) + + # start transmit in the middle of frame 2 + await test_frames[1].tx_complete.wait() + for j in range(8): + await RisingEdge(dut.clk) + await tb.send_mcf(test_pkt) + await FallingEdge(dut.mcf_valid) + + cur_id = (cur_id + 1) % max_count + + for k in [0, 1, 2, 4, 3]: + rx_frame = await tb.sink.recv() + + rx_pkt = Ether(bytes(rx_frame)) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + cur_id, test_pkt = test_pkts[k] + + if rx_pkt.type == 0x8808: + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + assert rx_frame.tid == 0 + assert rx_frame.tdest == 0 + else: + assert bytes(rx_pkt) == bytes(test_pkt) + assert rx_frame.tid == cur_id | (0 << src_shift) + assert rx_frame.tdest == cur_id + + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + byte_lanes = tb.source.byte_lanes + id_width = len(tb.source.bus.tid) + id_count = 2**id_width + id_mask = id_count-1 + + src_width = 1 + src_mask = 2**src_width-1 if src_width else 0 + src_shift = id_width-src_width + max_count = 2**src_shift + count_mask = max_count-1 + + cur_id = 1 + + await tb.reset() + + dut.tx_pause_req.value = 0 + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + test_pkts = [list() for x in range(2)] + + for k in range(256): + length = random.randint(1, byte_lanes*16) + payload = bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000) + test_pkt = eth / (cur_id.to_bytes(2, 'big') + payload) + test_pkts[0].append((cur_id, test_pkt.copy())) + + test_frame = AxiStreamFrame(bytes(test_pkt)) + test_frame.tid = cur_id | (0 << src_shift) + test_frame.tdest = cur_id + + await tb.source.send(test_frame) + + cur_id = (cur_id + 1) % max_count + + for k in range(16): + length = random.randint(1, 18) + payload = bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / (cur_id.to_bytes(2, 'big') + payload) + test_pkts[1].append((cur_id, test_pkt.copy())) + + for c in range(random.randint(8, 64)): + await RisingEdge(dut.clk) + await tb.send_mcf(test_pkt) + await FallingEdge(dut.mcf_valid) + + cur_id = (cur_id + 1) % max_count + + while any(test_pkts): + rx_frame = await tb.sink.recv() + + rx_pkt = Ether(bytes(rx_frame)) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + test_pkt = None + + if rx_pkt.type == 0x8808: + cur_id, test_pkt = test_pkts[1].pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + assert rx_frame.tid == 0 + assert rx_frame.tdest == 0 + else: + cur_id, test_pkt = test_pkts[0].pop(0) + assert bytes(rx_pkt) == bytes(test_pkt) + assert rx_frame.tid == cur_id | (0 << src_shift) + assert rx_frame.tdest == cur_id + + assert not rx_frame.tuser + + assert tb.sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +def size_list(): + return list(range(1, 128)) + [512, 1514, 9214] + [60]*10 + + +def mcf_size_list(): + return list(range(1, 19)) + + +def incrementing_payload(length): + return bytes(itertools.islice(itertools.cycle(range(256)), length)) + + +if cocotb.SIM_NAME: + + factory = TestFactory(run_test_data) + factory.add_option("payload_lengths", [size_list]) + factory.add_option("payload_data", [incrementing_payload]) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.generate_tests() + + factory = TestFactory(run_test_mcf) + factory.add_option("payload_lengths", [mcf_size_list]) + factory.add_option("payload_data", [incrementing_payload]) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.generate_tests() + + factory = TestFactory(run_test_tuser_assert) + factory.generate_tests() + + factory = TestFactory(run_arb_test) + factory.generate_tests() + + factory = TestFactory(run_stress_test) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) + + +@pytest.mark.parametrize("data_width", [8, 16, 32, 64, 128, 256, 512]) +def test_mac_ctrl_tx(request, data_width): + dut = "mac_ctrl_tx" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, f"{dut}.v"), + ] + + parameters = {} + + parameters['DATA_WIDTH'] = data_width + parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) + parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8 + parameters['ID_ENABLE'] = 1 + parameters['ID_WIDTH'] = 8 + parameters['DEST_ENABLE'] = 1 + parameters['DEST_WIDTH'] = 8 + parameters['USER_WIDTH'] = 1 + parameters['MCF_PARAMS_SIZE'] = 18 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/fpga/lib/eth/tb/mac_pause_ctrl_rx/Makefile b/fpga/lib/eth/tb/mac_pause_ctrl_rx/Makefile new file mode 100644 index 000000000..656f74333 --- /dev/null +++ b/fpga/lib/eth/tb/mac_pause_ctrl_rx/Makefile @@ -0,0 +1,69 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +TOPLEVEL_LANG = verilog + +SIM ?= icarus +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = mac_pause_ctrl_rx +TOPLEVEL = $(DUT) +MODULE = test_$(DUT) +VERILOG_SOURCES += ../../rtl/$(DUT).v + +# module parameters +export PARAM_MCF_PARAMS_SIZE := 18 +export PARAM_PFC_ENABLE := 1 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + VERILOG_SOURCES += iverilog_dump.v + COMPILE_ARGS += -s iverilog_dump + endif +else ifeq ($(SIM), verilator) + COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim + +iverilog_dump.v: + echo 'module iverilog_dump();' > $@ + echo 'initial begin' >> $@ + echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ + echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ + echo 'end' >> $@ + echo 'endmodule' >> $@ + +clean:: + @rm -rf iverilog_dump.v + @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/fpga/lib/eth/tb/mac_pause_ctrl_rx/test_mac_pause_ctrl_rx.py b/fpga/lib/eth/tb/mac_pause_ctrl_rx/test_mac_pause_ctrl_rx.py new file mode 100644 index 000000000..e19b73a00 --- /dev/null +++ b/fpga/lib/eth/tb/mac_pause_ctrl_rx/test_mac_pause_ctrl_rx.py @@ -0,0 +1,424 @@ +#!/usr/bin/env python +""" + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +""" + +import logging +import os +import struct + +from scapy.layers.l2 import Ether +from scapy.utils import mac2str + +import cocotb_test.simulator + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge +from cocotb.regression import TestFactory +from cocotb.utils import get_sim_time + +from cocotbext.axi.stream import define_stream + + +McfBus, McfTransaction, McfSource, McfSink, McfMonitor = define_stream("Mcf", + signals=["valid", "eth_dst", "eth_src", "eth_type", "opcode", "params"], + optional_signals=["ready", "id", "dest", "user"] +) + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) + + self.mcf_source = McfSource(McfBus.from_prefix(dut, "mcf"), dut.clk, dut.rst) + + dut.rx_lfc_en.setimmediatevalue(0) + dut.rx_lfc_ack.setimmediatevalue(0) + + dut.rx_pfc_en.setimmediatevalue(0) + dut.rx_pfc_ack.setimmediatevalue(0) + + dut.cfg_rx_lfc_opcode.setimmediatevalue(0) + dut.cfg_rx_lfc_en.setimmediatevalue(0) + dut.cfg_rx_pfc_opcode.setimmediatevalue(0) + dut.cfg_rx_pfc_en.setimmediatevalue(0) + dut.cfg_quanta_step.setimmediatevalue(256) + dut.cfg_quanta_clk_en.setimmediatevalue(1) + + async def reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + async def send_mcf(self, pkt): + mcf = McfTransaction() + mcf.eth_dst = int.from_bytes(mac2str(pkt[Ether].dst), 'big') + mcf.eth_src = int.from_bytes(mac2str(pkt[Ether].src), 'big') + mcf.eth_type = pkt[Ether].type + mcf.opcode = int.from_bytes(bytes(pkt[Ether].payload)[0:2], 'big') + mcf.params = int.from_bytes(bytes(pkt[Ether].payload)[2:], 'little') + + await self.mcf_source.send(mcf) + + +async def run_test_lfc(dut): + + tb = TB(dut) + + await tb.reset() + + dut.rx_lfc_en.value = 1 + dut.rx_lfc_ack.value = 0 + + dut.rx_pfc_en.value = 0 + dut.rx_pfc_ack.value = 0 + + dut.cfg_rx_lfc_opcode.value = 0x0001 + dut.cfg_rx_lfc_en.value = 1 + dut.cfg_rx_pfc_opcode.value = 0x0101 + dut.cfg_rx_pfc_en.value = 0 + dut.cfg_quanta_step.value = int(10000*256 / (512*156.25)) + dut.cfg_quanta_clk_en.value = 1 + + tb.log.info("Test release time accuracy") + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH', 0x0001, 100) + + await tb.send_mcf(test_pkt) + + while dut.rx_lfc_req.value == 0: + await RisingEdge(dut.clk) + dut.rx_lfc_ack.value = 1 + + start_time = get_sim_time('sec') + while dut.rx_lfc_req.value: + await RisingEdge(dut.clk) + stop_time = get_sim_time('sec') + + dut.rx_lfc_ack.value = 0 + + pause_time = stop_time-start_time + pause_quanta = pause_time / (512 * 1/10e9) + + tb.log.info("pause time : %g s", pause_time) + tb.log.info("pause quanta : %f", pause_quanta) + + assert round(pause_quanta) == 100 + + tb.log.info("Test release time accuracy (with refresh)") + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH', 0x0001, 100) + + await tb.send_mcf(test_pkt) + + while dut.rx_lfc_req.value == 0: + await RisingEdge(dut.clk) + dut.rx_lfc_ack.value = 1 + + for k in range(400): + await RisingEdge(dut.clk) + + await tb.send_mcf(test_pkt) + + start_time = get_sim_time('sec') + while dut.rx_lfc_req.value: + await RisingEdge(dut.clk) + stop_time = get_sim_time('sec') + + dut.rx_lfc_ack.value = 0 + + pause_time = stop_time-start_time + pause_quanta = pause_time / (512 * 1/10e9) + + tb.log.info("pause time : %g s", pause_time) + tb.log.info("pause quanta : %f", pause_quanta) + + assert round(pause_quanta) == 100 + + tb.log.info("Test explicit release") + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH', 0x0001, 100) + + await tb.send_mcf(test_pkt) + + while dut.rx_lfc_req.value == 0: + await RisingEdge(dut.clk) + dut.rx_lfc_ack.value = 1 + + start_time = get_sim_time('sec') + + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH', 0x0001, 0) + + await tb.send_mcf(test_pkt) + + while dut.rx_lfc_req.value: + await RisingEdge(dut.clk) + stop_time = get_sim_time('sec') + + dut.rx_lfc_ack.value = 0 + + pause_time = stop_time-start_time + pause_quanta = pause_time / (512 * 1/10e9) + + tb.log.info("pause time : %g s", pause_time) + tb.log.info("pause quanta : %f", pause_quanta) + + assert round(pause_quanta) < 50 + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_pfc(dut): + + tb = TB(dut) + + await tb.reset() + + dut.rx_lfc_en.value = 0 + dut.rx_lfc_ack.value = 0 + + dut.rx_pfc_en.value = 0xFF + dut.rx_pfc_ack.value = 0 + + dut.cfg_rx_lfc_opcode.value = 0x0001 + dut.cfg_rx_lfc_en.value = 0 + dut.cfg_rx_pfc_opcode.value = 0x0101 + dut.cfg_rx_pfc_en.value = 1 + dut.cfg_quanta_step.value = int(10000*256 / (512*156.25)) + dut.cfg_quanta_clk_en.value = 1 + + tb.log.info("Test release time accuracy") + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0001, 100, 0, 0, 0, 0, 0, 0, 0) + + await tb.send_mcf(test_pkt) + + while dut.rx_pfc_req.value == 0x00: + await RisingEdge(dut.clk) + dut.rx_pfc_ack.value = 0x01 + + start_time = get_sim_time('sec') + while dut.rx_pfc_req.value: + await RisingEdge(dut.clk) + stop_time = get_sim_time('sec') + + dut.rx_pfc_ack.value = 0x00 + + pause_time = stop_time-start_time + pause_quanta = pause_time / (512 * 1/10e9) + + tb.log.info("pause time : %g s", pause_time) + tb.log.info("pause quanta : %f", pause_quanta) + + assert round(pause_quanta) == 100 + + tb.log.info("Test release time accuracy (with refresh)") + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0001, 100, 0, 0, 0, 0, 0, 0, 0) + + await tb.send_mcf(test_pkt) + + while dut.rx_pfc_req.value == 0x00: + await RisingEdge(dut.clk) + dut.rx_pfc_ack.value = 0x01 + + for k in range(400): + await RisingEdge(dut.clk) + + await tb.send_mcf(test_pkt) + + start_time = get_sim_time('sec') + while dut.rx_pfc_req.value: + await RisingEdge(dut.clk) + stop_time = get_sim_time('sec') + + dut.rx_pfc_ack.value = 0x00 + + pause_time = stop_time-start_time + pause_quanta = pause_time / (512 * 1/10e9) + + tb.log.info("pause time : %g s", pause_time) + tb.log.info("pause quanta : %f", pause_quanta) + + assert round(pause_quanta) == 100 + + tb.log.info("Test explicit release") + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0001, 100, 0, 0, 0, 0, 0, 0, 0) + + await tb.send_mcf(test_pkt) + + while dut.rx_pfc_req.value == 0x00: + await RisingEdge(dut.clk) + dut.rx_pfc_ack.value = 0x01 + + start_time = get_sim_time('sec') + + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0001, 0, 0, 0, 0, 0, 0, 0, 0) + + await tb.send_mcf(test_pkt) + + while dut.rx_pfc_req.value: + await RisingEdge(dut.clk) + stop_time = get_sim_time('sec') + + dut.rx_pfc_ack.value = 0x00 + + pause_time = stop_time-start_time + pause_quanta = pause_time / (512 * 1/10e9) + + tb.log.info("pause time : %g s", pause_time) + tb.log.info("pause quanta : %f", pause_quanta) + + assert round(pause_quanta) < 50 + + tb.log.info("Test all channels") + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x00FF, 10, 20, 30, 40, 50, 60, 70, 80) + + await tb.send_mcf(test_pkt) + + while dut.rx_pfc_req.value != 0xff: + await RisingEdge(dut.clk) + dut.rx_pfc_ack.value = 0xff + + start_time = get_sim_time('sec') + + for k in range(8): + while dut.rx_pfc_req.value & (1 << k) != 0x00: + await RisingEdge(dut.clk) + stop_time = get_sim_time('sec') + + pause_time = stop_time-start_time + pause_quanta = pause_time / (512 * 1/10e9) + + tb.log.info("pause time : %g s", pause_time) + tb.log.info("pause quanta : %f", pause_quanta) + + assert round(pause_quanta) == (k+1)*10 + + dut.rx_pfc_ack.value = 0 + + tb.log.info("Test isolation") + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0001, 100, 0, 0, 0, 0, 0, 0, 0) + + await tb.send_mcf(test_pkt) + + while dut.rx_pfc_req.value & 0x01 == 0x00: + await RisingEdge(dut.clk) + dut.rx_pfc_ack.value = 0x01 + + start_time = get_sim_time('sec') + + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0002, 0, 200, 0, 0, 0, 0, 0, 0) + + await tb.send_mcf(test_pkt) + + while dut.rx_pfc_req.value & 0x02 == 0x00: + await RisingEdge(dut.clk) + dut.rx_pfc_ack.value = 0x03 + + eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0002, 0, 0, 0, 0, 0, 0, 0, 0) + + await tb.send_mcf(test_pkt) + + while dut.rx_pfc_req.value: + await RisingEdge(dut.clk) + stop_time = get_sim_time('sec') + + dut.rx_pfc_ack.value = 0x00 + + pause_time = stop_time-start_time + pause_quanta = pause_time / (512 * 1/10e9) + + tb.log.info("pause time : %g s", pause_time) + tb.log.info("pause quanta : %f", pause_quanta) + + assert round(pause_quanta) == 100 + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +if cocotb.SIM_NAME: + + for test in [run_test_lfc, run_test_pfc]: + + factory = TestFactory(test) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) + + +def test_mac_pause_ctrl_rx(request): + dut = "mac_pause_ctrl_rx" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, f"{dut}.v"), + ] + + parameters = {} + + parameters['MCF_PARAMS_SIZE'] = 18 + parameters['PFC_ENABLE'] = 1 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/fpga/lib/eth/tb/mac_pause_ctrl_tx/Makefile b/fpga/lib/eth/tb/mac_pause_ctrl_tx/Makefile new file mode 100644 index 000000000..5daad7157 --- /dev/null +++ b/fpga/lib/eth/tb/mac_pause_ctrl_tx/Makefile @@ -0,0 +1,69 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +TOPLEVEL_LANG = verilog + +SIM ?= icarus +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = mac_pause_ctrl_tx +TOPLEVEL = $(DUT) +MODULE = test_$(DUT) +VERILOG_SOURCES += ../../rtl/$(DUT).v + +# module parameters +export PARAM_MCF_PARAMS_SIZE := 18 +export PARAM_PFC_ENABLE := 1 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + VERILOG_SOURCES += iverilog_dump.v + COMPILE_ARGS += -s iverilog_dump + endif +else ifeq ($(SIM), verilator) + COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim + +iverilog_dump.v: + echo 'module iverilog_dump();' > $@ + echo 'initial begin' >> $@ + echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ + echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ + echo 'end' >> $@ + echo 'endmodule' >> $@ + +clean:: + @rm -rf iverilog_dump.v + @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/fpga/lib/eth/tb/mac_pause_ctrl_tx/test_mac_pause_ctrl_tx.py b/fpga/lib/eth/tb/mac_pause_ctrl_tx/test_mac_pause_ctrl_tx.py new file mode 100644 index 000000000..5d3f38f8d --- /dev/null +++ b/fpga/lib/eth/tb/mac_pause_ctrl_tx/test_mac_pause_ctrl_tx.py @@ -0,0 +1,395 @@ +#!/usr/bin/env python +""" + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +""" + +import logging +import os +import struct + +from scapy.layers.l2 import Ether + +import cocotb_test.simulator + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge +from cocotb.regression import TestFactory +from cocotb.utils import get_sim_time + +from cocotbext.axi.stream import define_stream + + +McfBus, McfTransaction, McfSource, McfSink, McfMonitor = define_stream("Mcf", + signals=["valid", "eth_dst", "eth_src", "eth_type", "opcode", "params"], + optional_signals=["ready", "id", "dest", "user"] +) + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) + + self.mcf_sink = McfSink(McfBus.from_prefix(dut, "mcf"), dut.clk, dut.rst) + + dut.tx_lfc_req.setimmediatevalue(0) + dut.tx_lfc_resend.setimmediatevalue(0) + + dut.tx_pfc_req.setimmediatevalue(0) + dut.tx_pfc_resend.setimmediatevalue(0) + + dut.cfg_tx_lfc_eth_dst.setimmediatevalue(0) + dut.cfg_tx_lfc_eth_src.setimmediatevalue(0) + dut.cfg_tx_lfc_eth_type.setimmediatevalue(0) + dut.cfg_tx_lfc_opcode.setimmediatevalue(0) + dut.cfg_tx_lfc_en.setimmediatevalue(0) + dut.cfg_tx_lfc_quanta.setimmediatevalue(0) + dut.cfg_tx_lfc_refresh.setimmediatevalue(0) + dut.cfg_tx_pfc_eth_dst.setimmediatevalue(0) + dut.cfg_tx_pfc_eth_src.setimmediatevalue(0) + dut.cfg_tx_pfc_eth_type.setimmediatevalue(0) + dut.cfg_tx_pfc_opcode.setimmediatevalue(0) + dut.cfg_tx_pfc_en.setimmediatevalue(0) + dut.cfg_tx_pfc_quanta.setimmediatevalue(0) + dut.cfg_tx_pfc_refresh.setimmediatevalue(0) + dut.cfg_quanta_step.setimmediatevalue(256) + dut.cfg_quanta_clk_en.setimmediatevalue(1) + + async def reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + async def recv_mcf(self): + rx_frame = await self.mcf_sink.recv() + + data = bytearray() + data.extend(rx_frame.eth_dst.integer.to_bytes(6, 'big')) + data.extend(rx_frame.eth_src.integer.to_bytes(6, 'big')) + data.extend(rx_frame.eth_type.integer.to_bytes(2, 'big')) + data.extend(rx_frame.opcode.integer.to_bytes(2, 'big')) + data.extend(rx_frame.params.integer.to_bytes(44, 'little')) + + return Ether(data) + + +def check_lfc_frame(tb, pkt, quanta): + tb.log.info("Pause frame: %s", repr(pkt)) + + op, q = struct.unpack_from('!HH', bytes(pkt[Ether].payload), 0) + tb.log.info("opcode: 0x%x", op) + tb.log.info("quanta: %d", q) + + assert pkt[Ether].dst == '01:80:c2:00:00:01' + assert pkt[Ether].src == '5a:51:52:53:54:55' + assert pkt[Ether].type == 0x8808 + assert op == 0x0001 + assert q == quanta + + +async def run_test_lfc(dut): + + tb = TB(dut) + + await tb.reset() + + dut.tx_lfc_req.value = 0 + dut.tx_lfc_resend.value = 0 + + dut.tx_pfc_req.value = 0x00 + dut.tx_pfc_resend.value = 0 + + dut.cfg_tx_lfc_eth_dst.value = 0x0180C2000001 + dut.cfg_tx_lfc_eth_src.value = 0x5A5152535455 + dut.cfg_tx_lfc_eth_type.value = 0x8808 + dut.cfg_tx_lfc_opcode.value = 0x0001 + dut.cfg_tx_lfc_en.value = 1 + dut.cfg_tx_lfc_quanta.value = 0xFFFF + dut.cfg_tx_lfc_refresh.value = 0x7F00 + dut.cfg_tx_pfc_eth_dst.value = 0x0180C2000001 + dut.cfg_tx_pfc_eth_src.value = 0x5A5152535455 + dut.cfg_tx_pfc_eth_type.value = 0x8808 + dut.cfg_tx_pfc_opcode.value = 0x0101 + dut.cfg_tx_pfc_en.value = 0 + dut.cfg_tx_pfc_quanta.value = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + dut.cfg_tx_pfc_refresh.value = 0x7F007F007F007F007F007F007F007F00 + dut.cfg_quanta_step.value = int(10000*256 / (512*156.25)) + dut.cfg_quanta_clk_en.value = 1 + + tb.log.info("Test pause") + + dut.cfg_tx_lfc_refresh.value = 100 + + dut.tx_lfc_req.value = 1 + start_time = None + + for k in range(4): + rx_pkt = await tb.recv_mcf() + stop_time = get_sim_time('sec') + + check_lfc_frame(tb, rx_pkt, 0xFFFF) + + if start_time: + refresh_time = stop_time-start_time + refresh_quanta = refresh_time / (512 * 1/10e9) + + tb.log.info("refresh time : %g s", refresh_time) + tb.log.info("refresh quanta : %f", refresh_quanta) + + assert round(refresh_quanta) == 100 + + start_time = get_sim_time('sec') + + dut.tx_lfc_req.value = 0 + + rx_pkt = await tb.recv_mcf() + + check_lfc_frame(tb, rx_pkt, 0x0) + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +def check_pfc_frame(tb, pkt, enable_mask, quanta_mask, quanta): + tb.log.info("PFC frame: %s", repr(pkt)) + + op, enable, *q = struct.unpack_from('!HH8H', bytes(pkt[Ether].payload), 0) + tb.log.info("opcode: 0x%x", op) + tb.log.info("enable: 0x%x", enable) + tb.log.info("quanta: %r", q) + + assert pkt[Ether].dst == '01:80:c2:00:00:01' + assert pkt[Ether].src == '5a:51:52:53:54:55' + assert pkt[Ether].type == 0x8808 + assert op == 0x0101 + assert enable == enable_mask + for k in range(8): + if quanta_mask & (1 << k): + assert q[k] == quanta + else: + assert q[k] == 0 + + +async def run_test_pfc(dut): + + tb = TB(dut) + + await tb.reset() + + dut.tx_lfc_req.value = 0 + dut.tx_lfc_resend.value = 0 + + dut.tx_pfc_req.value = 0x00 + dut.tx_pfc_resend.value = 0 + + dut.cfg_tx_lfc_eth_dst.value = 0x0180C2000001 + dut.cfg_tx_lfc_eth_src.value = 0x5A5152535455 + dut.cfg_tx_lfc_eth_type.value = 0x8808 + dut.cfg_tx_lfc_opcode.value = 0x0001 + dut.cfg_tx_lfc_en.value = 0 + dut.cfg_tx_lfc_quanta.value = 0xFFFF + dut.cfg_tx_lfc_refresh.value = 0x7F00 + dut.cfg_tx_pfc_eth_dst.value = 0x0180C2000001 + dut.cfg_tx_pfc_eth_src.value = 0x5A5152535455 + dut.cfg_tx_pfc_eth_type.value = 0x8808 + dut.cfg_tx_pfc_opcode.value = 0x0101 + dut.cfg_tx_pfc_en.value = 1 + dut.cfg_tx_pfc_quanta.value = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + dut.cfg_tx_pfc_refresh.value = 0x7F007F007F007F007F007F007F007F00 + dut.cfg_quanta_step.value = int(10000*256 / (512*156.25)) + dut.cfg_quanta_clk_en.value = 1 + + tb.log.info("Test pause") + + dut.cfg_tx_pfc_refresh.value = 0x00640064006400640064006400640064 + + dut.tx_pfc_req.value = 0x01 + start_time = None + + for k in range(4): + rx_pkt = await tb.recv_mcf() + stop_time = get_sim_time('sec') + + check_pfc_frame(tb, rx_pkt, 0x01, 0x01, 0xFFFF) + + if start_time: + refresh_time = stop_time-start_time + refresh_quanta = refresh_time / (512 * 1/10e9) + + tb.log.info("refresh time : %g s", refresh_time) + tb.log.info("refresh quanta : %f", refresh_quanta) + + assert round(refresh_quanta) == 100 + + start_time = get_sim_time('sec') + + dut.tx_pfc_req.value = 0x00 + + rx_pkt = await tb.recv_mcf() + + check_pfc_frame(tb, rx_pkt, 0x01, 0x00, 0xFFFF) + + tb.log.info("Test all channels") + + dut.cfg_tx_pfc_refresh.value = 0x00640064006400640064006400640064 + + for ch in range(8): + + dut.tx_pfc_req.value = 0xFF >> (7-ch) + start_time = None + + for k in range(3): + rx_pkt = await tb.recv_mcf() + stop_time = get_sim_time('sec') + + check_pfc_frame(tb, rx_pkt, 0xFF >> (7-ch), 0xFF >> (7-ch), 0xFFFF) + + if start_time: + refresh_time = stop_time-start_time + refresh_quanta = refresh_time / (512 * 1/10e9) + + tb.log.info("refresh time : %g s", refresh_time) + tb.log.info("refresh quanta : %f", refresh_quanta) + + assert round(refresh_quanta) == 100 + + start_time = get_sim_time('sec') + + dut.tx_pfc_req.value = 0x00 + + rx_pkt = await tb.recv_mcf() + + check_pfc_frame(tb, rx_pkt, 0xFF, 0x00, 0xFFFF) + + tb.log.info("Test isolation") + + dut.cfg_tx_pfc_refresh.value = 0x00640064006400640064006400640064 + + dut.tx_pfc_req.value = 0x01 + start_time = None + + rx_pkt = await tb.recv_mcf() + stop_time = get_sim_time('sec') + + check_pfc_frame(tb, rx_pkt, 0x01, 0x01, 0xFFFF) + + dut.tx_pfc_req.value = 0x03 + start_time = None + + rx_pkt = await tb.recv_mcf() + stop_time = get_sim_time('sec') + + check_pfc_frame(tb, rx_pkt, 0x03, 0x03, 0xFFFF) + + dut.tx_pfc_req.value = 0x01 + start_time = None + + rx_pkt = await tb.recv_mcf() + stop_time = get_sim_time('sec') + + check_pfc_frame(tb, rx_pkt, 0x03, 0x01, 0xFFFF) + + start_time = get_sim_time('sec') + + for k in range(4): + rx_pkt = await tb.recv_mcf() + stop_time = get_sim_time('sec') + + check_pfc_frame(tb, rx_pkt, 0x01, 0x01, 0xFFFF) + + if start_time: + refresh_time = stop_time-start_time + refresh_quanta = refresh_time / (512 * 1/10e9) + + tb.log.info("refresh time : %g s", refresh_time) + tb.log.info("refresh quanta : %f", refresh_quanta) + + assert round(refresh_quanta) == 100 + + start_time = get_sim_time('sec') + + dut.tx_pfc_req.value = 0x00 + + rx_pkt = await tb.recv_mcf() + + check_pfc_frame(tb, rx_pkt, 0x01, 0x00, 0xFFFF) + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +if cocotb.SIM_NAME: + + for test in [run_test_lfc, run_test_pfc]: + + factory = TestFactory(test) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) + + +def test_mac_pause_ctrl_tx(request): + dut = "mac_pause_ctrl_tx" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, f"{dut}.v"), + ] + + parameters = {} + + parameters['MCF_PARAMS_SIZE'] = 18 + parameters['PFC_ENABLE'] = 1 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + )