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merged changes in pcie

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This commit is contained in:
Alex Forencich 2022-08-03 14:14:48 -07:00
commit 053c08f027
35 changed files with 12 additions and 227 deletions
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2
fpga/lib/pcie/example/520N_MX/fpga/rtl/fpga_core.v
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@ -104,10 +104,8 @@ example_core_pcie_s10 #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**TX_SEQ_NUM_WIDTH),
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(2**TX_SEQ_NUM_WIDTH),
.WRITE_TX_LIMIT(2**TX_SEQ_NUM_WIDTH),
.WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE),
.BAR4_APERTURE(BAR4_APERTURE)

2
fpga/lib/pcie/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.v
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@ -158,10 +158,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE),
.BAR4_APERTURE(BAR4_APERTURE)

2
fpga/lib/pcie/example/AU200/fpga/rtl/fpga_core.v
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@ -155,10 +155,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE),
.BAR4_APERTURE(BAR4_APERTURE)

2
fpga/lib/pcie/example/AU250/fpga/rtl/fpga_core.v
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@ -155,10 +155,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE),
.BAR4_APERTURE(BAR4_APERTURE)

2
fpga/lib/pcie/example/AU280/fpga/rtl/fpga_core.v
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@ -147,10 +147,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE),
.BAR4_APERTURE(BAR4_APERTURE)

2
fpga/lib/pcie/example/AU50/fpga/rtl/fpga_core.v
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@ -158,10 +158,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE),
.BAR4_APERTURE(BAR4_APERTURE)

2
fpga/lib/pcie/example/DE10_Agilex/fpga/rtl/fpga_core.v
View File

@ -109,10 +109,8 @@ example_core_pcie_ptile #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**TX_SEQ_NUM_WIDTH),
.READ_TX_FC_ENABLE(0),
.WRITE_OP_TABLE_SIZE(2**TX_SEQ_NUM_WIDTH),
.WRITE_TX_LIMIT(2**TX_SEQ_NUM_WIDTH),
.WRITE_TX_FC_ENABLE(0),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE),
.BAR4_APERTURE(BAR4_APERTURE)

2
fpga/lib/pcie/example/ExaNIC_X10/fpga/rtl/fpga_core.v
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@ -153,10 +153,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE),
.BAR4_APERTURE(BAR4_APERTURE)

2
fpga/lib/pcie/example/ExaNIC_X25/fpga/rtl/fpga_core.v
View File

@ -158,10 +158,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE),
.BAR4_APERTURE(BAR4_APERTURE)

2
fpga/lib/pcie/example/S10DX_DK/fpga/rtl/fpga_core.v
View File

@ -106,10 +106,8 @@ example_core_pcie_ptile #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**TX_SEQ_NUM_WIDTH),
.READ_TX_FC_ENABLE(0),
.WRITE_OP_TABLE_SIZE(2**TX_SEQ_NUM_WIDTH),
.WRITE_TX_LIMIT(2**TX_SEQ_NUM_WIDTH),
.WRITE_TX_FC_ENABLE(0),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE),
.BAR4_APERTURE(BAR4_APERTURE)

2
fpga/lib/pcie/example/S10MX_DK/fpga/rtl/fpga_core.v
View File

@ -100,10 +100,8 @@ example_core_pcie_s10 #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**TX_SEQ_NUM_WIDTH),
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(2**TX_SEQ_NUM_WIDTH),
.WRITE_TX_LIMIT(2**TX_SEQ_NUM_WIDTH),
.WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE),
.BAR4_APERTURE(BAR4_APERTURE)

2
fpga/lib/pcie/example/VCU108/fpga/rtl/fpga_core.v
View File

@ -155,10 +155,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE),
.BAR4_APERTURE(BAR4_APERTURE)

2
fpga/lib/pcie/example/VCU118/fpga/rtl/fpga_core.v
View File

@ -160,10 +160,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE),
.BAR4_APERTURE(BAR4_APERTURE)

2
fpga/lib/pcie/example/VCU1525/fpga/rtl/fpga_core.v
View File

@ -155,10 +155,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE),
.BAR4_APERTURE(BAR4_APERTURE)

2
fpga/lib/pcie/example/ZCU106/fpga/rtl/fpga_core.v
View File

@ -160,10 +160,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE),
.BAR4_APERTURE(BAR4_APERTURE)

20
fpga/lib/pcie/example/common/rtl/example_core_pcie.v
View File

@ -57,14 +57,10 @@ module example_core_pcie #
parameter READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
// In-flight transmit limit (read)
parameter READ_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Transmit flow control (read)
parameter READ_TX_FC_ENABLE = 1,
// Operation table size (write)
parameter WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH,
// In-flight transmit limit (write)
parameter WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Transmit flow control (write)
parameter WRITE_TX_FC_ENABLE = 1,
// Force 64 bit address
parameter TLP_FORCE_64_BIT_ADDR = 0,
// Requester ID mash
@ -157,13 +153,6 @@ module example_core_pcie #
output wire tx_msix_wr_req_tlp_eop,
input wire tx_msix_wr_req_tlp_ready,
/*
* Transmit flow control
*/
input wire [7:0] pcie_tx_fc_ph_av,
input wire [11:0] pcie_tx_fc_pd_av,
input wire [7:0] pcie_tx_fc_nph_av,
/*
* Configuration
*/
@ -795,10 +784,8 @@ dma_if_pcie #(
.TAG_WIDTH(DMA_TAG_WIDTH),
.READ_OP_TABLE_SIZE(READ_OP_TABLE_SIZE),
.READ_TX_LIMIT(READ_TX_LIMIT),
.READ_TX_FC_ENABLE(READ_TX_FC_ENABLE),
.WRITE_OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE),
.WRITE_TX_LIMIT(WRITE_TX_LIMIT),
.WRITE_TX_FC_ENABLE(WRITE_TX_FC_ENABLE),
.TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR),
.CHECK_BUS_NUMBER(CHECK_BUS_NUMBER)
)
@ -847,13 +834,6 @@ dma_if_pcie_inst (
.s_axis_wr_req_tx_seq_num(s_axis_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(s_axis_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
*/
.pcie_tx_fc_ph_av(pcie_tx_fc_ph_av),
.pcie_tx_fc_pd_av(pcie_tx_fc_pd_av),
.pcie_tx_fc_nph_av(pcie_tx_fc_nph_av),
/*
* AXI read descriptor input
*/

23
fpga/lib/pcie/example/common/rtl/example_core_pcie_ptile.v
View File

@ -57,14 +57,10 @@ module example_core_pcie_ptile #
parameter READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
// In-flight transmit limit (read)
parameter READ_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Transmit flow control (read)
parameter READ_TX_FC_ENABLE = 1,
// Operation table size (write)
parameter WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH,
// In-flight transmit limit (write)
parameter WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Transmit flow control (write)
parameter WRITE_TX_FC_ENABLE = 1,
// BAR0 aperture (log2 size)
parameter BAR0_APERTURE = 24,
// BAR2 aperture (log2 size)
@ -192,10 +188,6 @@ wire pcie_tx_msix_wr_req_tlp_sop;
wire pcie_tx_msix_wr_req_tlp_eop;
wire pcie_tx_msix_wr_req_tlp_ready;
wire [7:0] pcie_tx_fc_ph_av;
wire [11:0] pcie_tx_fc_pd_av;
wire [7:0] pcie_tx_fc_nph_av;
wire ext_tag_enable;
wire [7:0] bus_num;
wire [2:0] max_read_request_size;
@ -353,9 +345,9 @@ pcie_ptile_if_inst (
/*
* Flow control
*/
.tx_fc_ph_av(pcie_tx_fc_ph_av),
.tx_fc_pd_av(pcie_tx_fc_pd_av),
.tx_fc_nph_av(pcie_tx_fc_nph_av),
.tx_fc_ph_av(),
.tx_fc_pd_av(),
.tx_fc_nph_av(),
.tx_fc_npd_av(),
.tx_fc_cplh_av(),
.tx_fc_cpld_av(),
@ -384,10 +376,8 @@ example_core_pcie #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(READ_OP_TABLE_SIZE),
.READ_TX_LIMIT(READ_TX_LIMIT),
.READ_TX_FC_ENABLE(0),
.WRITE_OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE),
.WRITE_TX_LIMIT(WRITE_TX_LIMIT),
.WRITE_TX_FC_ENABLE(0),
.TLP_FORCE_64_BIT_ADDR(0),
.CHECK_BUS_NUMBER(1),
.BAR0_APERTURE(BAR0_APERTURE),
@ -464,13 +454,6 @@ core_pcie_inst (
.s_axis_wr_req_tx_seq_num(axis_pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(axis_pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
*/
.pcie_tx_fc_ph_av(pcie_tx_fc_ph_av),
.pcie_tx_fc_pd_av(pcie_tx_fc_pd_av),
.pcie_tx_fc_nph_av(pcie_tx_fc_nph_av),
/*
* TLP output (MSI-X write request)
*/

23
fpga/lib/pcie/example/common/rtl/example_core_pcie_s10.v
View File

@ -55,14 +55,10 @@ module example_core_pcie_s10 #
parameter READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
// In-flight transmit limit (read)
parameter READ_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Transmit flow control (read)
parameter READ_TX_FC_ENABLE = 1,
// Operation table size (write)
parameter WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH,
// In-flight transmit limit (write)
parameter WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Transmit flow control (write)
parameter WRITE_TX_FC_ENABLE = 1,
// BAR0 aperture (log2 size)
parameter BAR0_APERTURE = 24,
// BAR2 aperture (log2 size)
@ -186,10 +182,6 @@ wire pcie_tx_msix_wr_req_tlp_sop;
wire pcie_tx_msix_wr_req_tlp_eop;
wire pcie_tx_msix_wr_req_tlp_ready;
wire [7:0] pcie_tx_fc_ph_av;
wire [11:0] pcie_tx_fc_pd_av;
wire [7:0] pcie_tx_fc_nph_av;
wire ext_tag_enable;
wire [7:0] bus_num;
wire [2:0] max_read_request_size;
@ -355,9 +347,9 @@ pcie_s10_if_inst (
/*
* Flow control
*/
.tx_fc_ph_av(pcie_tx_fc_ph_av),
.tx_fc_pd_av(pcie_tx_fc_pd_av),
.tx_fc_nph_av(pcie_tx_fc_nph_av),
.tx_fc_ph_av(),
.tx_fc_pd_av(),
.tx_fc_nph_av(),
.tx_fc_npd_av(),
.tx_fc_cplh_av(),
.tx_fc_cpld_av(),
@ -391,10 +383,8 @@ example_core_pcie #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(READ_OP_TABLE_SIZE),
.READ_TX_LIMIT(READ_TX_LIMIT),
.READ_TX_FC_ENABLE(READ_TX_FC_ENABLE),
.WRITE_OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE),
.WRITE_TX_LIMIT(WRITE_TX_LIMIT),
.WRITE_TX_FC_ENABLE(WRITE_TX_FC_ENABLE),
.TLP_FORCE_64_BIT_ADDR(0),
.CHECK_BUS_NUMBER(1),
.BAR0_APERTURE(BAR0_APERTURE),
@ -471,13 +461,6 @@ core_pcie_inst (
.s_axis_wr_req_tx_seq_num(axis_pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(axis_pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
*/
.pcie_tx_fc_ph_av(pcie_tx_fc_ph_av),
.pcie_tx_fc_pd_av(pcie_tx_fc_pd_av),
.pcie_tx_fc_nph_av(pcie_tx_fc_nph_av),
/*
* TLP output (MSI-X write request)
*/

23
fpga/lib/pcie/example/common/rtl/example_core_pcie_us.v
View File

@ -67,14 +67,10 @@ module example_core_pcie_us #
parameter READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
// In-flight transmit limit (read)
parameter READ_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1),
// Transmit flow control (read)
parameter READ_TX_FC_ENABLE = 1,
// Operation table size (write)
parameter WRITE_OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1),
// In-flight transmit limit (write)
parameter WRITE_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1),
// Transmit flow control (write)
parameter WRITE_TX_FC_ENABLE = 1,
// BAR0 aperture (log2 size)
parameter BAR0_APERTURE = 24,
// BAR2 aperture (log2 size)
@ -254,10 +250,6 @@ wire pcie_tx_msix_wr_req_tlp_sop;
wire pcie_tx_msix_wr_req_tlp_eop;
wire pcie_tx_msix_wr_req_tlp_ready;
wire [7:0] pcie_tx_fc_ph_av;
wire [11:0] pcie_tx_fc_pd_av;
wire [7:0] pcie_tx_fc_nph_av;
wire ext_tag_enable;
wire msix_enable;
wire msix_mask;
@ -486,9 +478,9 @@ pcie_us_if_inst (
/*
* Flow control
*/
.tx_fc_ph_av(pcie_tx_fc_ph_av),
.tx_fc_pd_av(pcie_tx_fc_pd_av),
.tx_fc_nph_av(pcie_tx_fc_nph_av),
.tx_fc_ph_av(),
.tx_fc_pd_av(),
.tx_fc_nph_av(),
.tx_fc_npd_av(),
.tx_fc_cplh_av(),
.tx_fc_cpld_av(),
@ -521,10 +513,8 @@ example_core_pcie #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(READ_OP_TABLE_SIZE),
.READ_TX_LIMIT(READ_TX_LIMIT),
.READ_TX_FC_ENABLE(READ_TX_FC_ENABLE),
.WRITE_OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE),
.WRITE_TX_LIMIT(WRITE_TX_LIMIT),
.WRITE_TX_FC_ENABLE(WRITE_TX_FC_ENABLE),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0),
.BAR0_APERTURE(BAR0_APERTURE),
@ -601,13 +591,6 @@ core_pcie_inst (
.s_axis_wr_req_tx_seq_num(axis_pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(axis_pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
*/
.pcie_tx_fc_ph_av(pcie_tx_fc_ph_av),
.pcie_tx_fc_pd_av(pcie_tx_fc_pd_av),
.pcie_tx_fc_nph_av(pcie_tx_fc_nph_av),
/*
* TLP output (MSI-X write request)
*/

6
fpga/lib/pcie/example/common/tb/example_core_pcie/Makefile
View File

@ -60,10 +60,8 @@ export PARAM_IMM_ENABLE ?= 1
export PARAM_IMM_WIDTH ?= 32
export PARAM_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
export PARAM_READ_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_READ_TX_FC_ENABLE ?= 1
export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_WRITE_TX_FC_ENABLE ?= 1
export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0
export PARAM_CHECK_BUS_NUMBER ?= 1
export PARAM_BAR0_APERTURE ?= 24
@ -85,10 +83,8 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IMM_WIDTH=$(PARAM_IMM_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).READ_OP_TABLE_SIZE=$(PARAM_READ_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).READ_TX_LIMIT=$(PARAM_READ_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).READ_TX_FC_ENABLE=$(PARAM_READ_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_OP_TABLE_SIZE=$(PARAM_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_TX_LIMIT=$(PARAM_WRITE_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_TX_FC_ENABLE=$(PARAM_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_FORCE_64_BIT_ADDR=$(PARAM_TLP_FORCE_64_BIT_ADDR)
COMPILE_ARGS += -P $(TOPLEVEL).CHECK_BUS_NUMBER=$(PARAM_CHECK_BUS_NUMBER)
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
@ -114,10 +110,8 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIMM_WIDTH=$(PARAM_IMM_WIDTH)
COMPILE_ARGS += -GREAD_OP_TABLE_SIZE=$(PARAM_READ_OP_TABLE_SIZE)
COMPILE_ARGS += -GREAD_TX_LIMIT=$(PARAM_READ_TX_LIMIT)
COMPILE_ARGS += -GREAD_TX_FC_ENABLE=$(PARAM_READ_TX_FC_ENABLE)
COMPILE_ARGS += -GWRITE_OP_TABLE_SIZE=$(PARAM_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GWRITE_TX_LIMIT=$(PARAM_WRITE_TX_LIMIT)
COMPILE_ARGS += -GWRITE_TX_FC_ENABLE=$(PARAM_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -GTLP_FORCE_64_BIT_ADDR=$(PARAM_TLP_FORCE_64_BIT_ADDR)
COMPILE_ARGS += -GCHECK_BUS_NUMBER=$(PARAM_CHECK_BUS_NUMBER)
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)

6
fpga/lib/pcie/example/common/tb/example_core_pcie/test_example_core_pcie.py
View File

@ -121,10 +121,6 @@ class TB(object):
cfg_max_payload=dut.max_payload_size,
cfg_max_read_req=dut.max_read_request_size,
cfg_ext_tag_enable=dut.ext_tag_enable,
tx_fc_ph_av=dut.pcie_tx_fc_ph_av,
tx_fc_pd_av=dut.pcie_tx_fc_pd_av,
tx_fc_nph_av=dut.pcie_tx_fc_nph_av,
)
self.dev.log.setLevel(logging.DEBUG)
@ -426,10 +422,8 @@ def test_example_core_pcie(request, pcie_data_width):
parameters['IMM_WIDTH'] = 32
parameters['READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
parameters['READ_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['READ_TX_FC_ENABLE'] = 1
parameters['WRITE_OP_TABLE_SIZE'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['WRITE_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['WRITE_TX_FC_ENABLE'] = 1
parameters['TLP_FORCE_64_BIT_ADDR'] = 0
parameters['CHECK_BUS_NUMBER'] = 1
parameters['BAR0_APERTURE'] = 24

6
fpga/lib/pcie/example/common/tb/example_core_pcie_ptile/Makefile
View File

@ -70,10 +70,8 @@ export PARAM_IMM_ENABLE ?= 1
export PARAM_IMM_WIDTH ?= 32
export PARAM_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
export PARAM_READ_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_READ_TX_FC_ENABLE ?= 1
export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_WRITE_TX_FC_ENABLE ?= 1
export PARAM_BAR0_APERTURE ?= 24
export PARAM_BAR2_APERTURE ?= 24
export PARAM_BAR4_APERTURE ?= 16
@ -93,10 +91,8 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IMM_WIDTH=$(PARAM_IMM_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).READ_OP_TABLE_SIZE=$(PARAM_READ_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).READ_TX_LIMIT=$(PARAM_READ_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).READ_TX_FC_ENABLE=$(PARAM_READ_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_OP_TABLE_SIZE=$(PARAM_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_TX_LIMIT=$(PARAM_WRITE_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_TX_FC_ENABLE=$(PARAM_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
@ -120,10 +116,8 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIMM_WIDTH=$(PARAM_IMM_WIDTH)
COMPILE_ARGS += -GREAD_OP_TABLE_SIZE=$(PARAM_READ_OP_TABLE_SIZE)
COMPILE_ARGS += -GREAD_TX_LIMIT=$(PARAM_READ_TX_LIMIT)
COMPILE_ARGS += -GREAD_TX_FC_ENABLE=$(PARAM_READ_TX_FC_ENABLE)
COMPILE_ARGS += -GWRITE_OP_TABLE_SIZE=$(PARAM_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GWRITE_TX_LIMIT=$(PARAM_WRITE_TX_LIMIT)
COMPILE_ARGS += -GWRITE_TX_FC_ENABLE=$(PARAM_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)

2
fpga/lib/pcie/example/common/tb/example_core_pcie_ptile/test_example_core_pcie_ptile.py
View File

@ -518,10 +518,8 @@ def test_example_core_pcie_ptile(request, data_width):
parameters['IMM_WIDTH'] = 32
parameters['READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
parameters['READ_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['READ_TX_FC_ENABLE'] = 1
parameters['WRITE_OP_TABLE_SIZE'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['WRITE_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['WRITE_TX_FC_ENABLE'] = 1
parameters['BAR0_APERTURE'] = 24
parameters['BAR2_APERTURE'] = 24
parameters['BAR4_APERTURE'] = 16

6
fpga/lib/pcie/example/common/tb/example_core_pcie_s10/Makefile
View File

@ -68,10 +68,8 @@ export PARAM_IMM_ENABLE ?= 1
export PARAM_IMM_WIDTH ?= 32
export PARAM_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
export PARAM_READ_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_READ_TX_FC_ENABLE ?= 1
export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
export PARAM_WRITE_TX_FC_ENABLE ?= 1
export PARAM_BAR0_APERTURE ?= 24
export PARAM_BAR2_APERTURE ?= 24
export PARAM_BAR4_APERTURE ?= 16
@ -90,10 +88,8 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IMM_WIDTH=$(PARAM_IMM_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).READ_OP_TABLE_SIZE=$(PARAM_READ_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).READ_TX_LIMIT=$(PARAM_READ_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).READ_TX_FC_ENABLE=$(PARAM_READ_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_OP_TABLE_SIZE=$(PARAM_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_TX_LIMIT=$(PARAM_WRITE_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_TX_FC_ENABLE=$(PARAM_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
@ -116,10 +112,8 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIMM_WIDTH=$(PARAM_IMM_WIDTH)
COMPILE_ARGS += -GREAD_OP_TABLE_SIZE=$(PARAM_READ_OP_TABLE_SIZE)
COMPILE_ARGS += -GREAD_TX_LIMIT=$(PARAM_READ_TX_LIMIT)
COMPILE_ARGS += -GREAD_TX_FC_ENABLE=$(PARAM_READ_TX_FC_ENABLE)
COMPILE_ARGS += -GWRITE_OP_TABLE_SIZE=$(PARAM_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GWRITE_TX_LIMIT=$(PARAM_WRITE_TX_LIMIT)
COMPILE_ARGS += -GWRITE_TX_FC_ENABLE=$(PARAM_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)

2
fpga/lib/pcie/example/common/tb/example_core_pcie_s10/test_example_core_pcie_s10.py
View File

@ -465,10 +465,8 @@ def test_example_core_pcie_s10(request, data_width, l_tile):
parameters['IMM_WIDTH'] = 32
parameters['READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
parameters['READ_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['READ_TX_FC_ENABLE'] = 1
parameters['WRITE_OP_TABLE_SIZE'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['WRITE_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH']
parameters['WRITE_TX_FC_ENABLE'] = 1
parameters['BAR0_APERTURE'] = 24
parameters['BAR2_APERTURE'] = 24
parameters['BAR4_APERTURE'] = 16

6
fpga/lib/pcie/example/common/tb/example_core_pcie_us/Makefile
View File

@ -74,10 +74,8 @@ export PARAM_IMM_ENABLE ?= 1
export PARAM_IMM_WIDTH ?= 32
export PARAM_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
export PARAM_READ_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_READ_TX_FC_ENABLE ?= 1
export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_WRITE_TX_FC_ENABLE ?= 1
export PARAM_BAR0_APERTURE ?= 24
export PARAM_BAR2_APERTURE ?= 24
export PARAM_BAR4_APERTURE ?= 16
@ -102,10 +100,8 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IMM_WIDTH=$(PARAM_IMM_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).READ_OP_TABLE_SIZE=$(PARAM_READ_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).READ_TX_LIMIT=$(PARAM_READ_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).READ_TX_FC_ENABLE=$(PARAM_READ_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_OP_TABLE_SIZE=$(PARAM_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_TX_LIMIT=$(PARAM_WRITE_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_TX_FC_ENABLE=$(PARAM_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
@ -134,10 +130,8 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIMM_WIDTH=$(PARAM_IMM_WIDTH)
COMPILE_ARGS += -GREAD_OP_TABLE_SIZE=$(PARAM_READ_OP_TABLE_SIZE)
COMPILE_ARGS += -GREAD_TX_LIMIT=$(PARAM_READ_TX_LIMIT)
COMPILE_ARGS += -GREAD_TX_FC_ENABLE=$(PARAM_READ_TX_FC_ENABLE)
COMPILE_ARGS += -GWRITE_OP_TABLE_SIZE=$(PARAM_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GWRITE_TX_LIMIT=$(PARAM_WRITE_TX_LIMIT)
COMPILE_ARGS += -GWRITE_TX_FC_ENABLE=$(PARAM_WRITE_TX_FC_ENABLE)
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)

2
fpga/lib/pcie/example/common/tb/example_core_pcie_us/test_example_core_pcie_us.py
View File

@ -566,10 +566,8 @@ def test_example_core_pcie_us(request, axis_pcie_data_width, straddle):
parameters['IMM_WIDTH'] = 32
parameters['READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
parameters['READ_TX_LIMIT'] = 2**(parameters['RQ_SEQ_NUM_WIDTH']-1)
parameters['READ_TX_FC_ENABLE'] = 1
parameters['WRITE_OP_TABLE_SIZE'] = 2**(parameters['RQ_SEQ_NUM_WIDTH']-1)
parameters['WRITE_TX_LIMIT'] = 2**(parameters['RQ_SEQ_NUM_WIDTH']-1)
parameters['WRITE_TX_FC_ENABLE'] = 1
parameters['BAR0_APERTURE'] = 24
parameters['BAR2_APERTURE'] = 24
parameters['BAR4_APERTURE'] = 16

2
fpga/lib/pcie/example/fb2CG/fpga/rtl/fpga_core.v
View File

@ -160,10 +160,8 @@ example_core_pcie_us #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE),
.BAR4_APERTURE(BAR4_APERTURE)

28
fpga/lib/pcie/rtl/dma_if_pcie.v
View File

@ -75,14 +75,10 @@ module dma_if_pcie #
parameter READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
// In-flight transmit limit (read)
parameter READ_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Transmit flow control (read)
parameter READ_TX_FC_ENABLE = 0,
// Operation table size (write)
parameter WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH,
// In-flight transmit limit (write)
parameter WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Transmit flow control (write)
parameter WRITE_TX_FC_ENABLE = 0,
// Force 64 bit address
parameter TLP_FORCE_64_BIT_ADDR = 0,
// Requester ID mash
@ -133,13 +129,6 @@ module dma_if_pcie #
input wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] s_axis_wr_req_tx_seq_num,
input wire [TX_SEQ_NUM_COUNT-1:0] s_axis_wr_req_tx_seq_num_valid,
/*
* Transmit flow control
*/
input wire [7:0] pcie_tx_fc_ph_av,
input wire [11:0] pcie_tx_fc_pd_av,
input wire [7:0] pcie_tx_fc_nph_av,
/*
* AXI read descriptor input
*/
@ -230,7 +219,6 @@ module dma_if_pcie #
output wire stat_rd_req_timeout,
output wire stat_rd_op_table_full,
output wire stat_rd_no_tags,
output wire stat_rd_tx_no_credit,
output wire stat_rd_tx_limit,
output wire stat_rd_tx_stall,
output wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_op_start_tag,
@ -246,7 +234,6 @@ module dma_if_pcie #
output wire [3:0] stat_wr_req_finish_status,
output wire stat_wr_req_finish_valid,
output wire stat_wr_op_table_full,
output wire stat_wr_tx_no_credit,
output wire stat_wr_tx_limit,
output wire stat_wr_tx_stall
);
@ -270,7 +257,6 @@ dma_if_pcie_rd #(
.TAG_WIDTH(TAG_WIDTH),
.OP_TABLE_SIZE(READ_OP_TABLE_SIZE),
.TX_LIMIT(READ_TX_LIMIT),
.TX_FC_ENABLE(READ_TX_FC_ENABLE),
.TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR),
.CHECK_BUS_NUMBER(CHECK_BUS_NUMBER)
)
@ -305,11 +291,6 @@ dma_if_pcie_rd_inst (
.s_axis_tx_seq_num(s_axis_rd_req_tx_seq_num),
.s_axis_tx_seq_num_valid(s_axis_rd_req_tx_seq_num_valid),
/*
* Transmit flow control
*/
.pcie_tx_fc_nph_av(pcie_tx_fc_nph_av),
/*
* AXI read descriptor input
*/
@ -371,7 +352,6 @@ dma_if_pcie_rd_inst (
.stat_rd_req_timeout(stat_rd_req_timeout),
.stat_rd_op_table_full(stat_rd_op_table_full),
.stat_rd_no_tags(stat_rd_no_tags),
.stat_rd_tx_no_credit(stat_rd_tx_no_credit),
.stat_rd_tx_limit(stat_rd_tx_limit),
.stat_rd_tx_stall(stat_rd_tx_stall)
);
@ -397,7 +377,6 @@ dma_if_pcie_wr #(
.TAG_WIDTH(TAG_WIDTH),
.OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE),
.TX_LIMIT(WRITE_TX_LIMIT),
.TX_FC_ENABLE(WRITE_TX_FC_ENABLE),
.TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR)
)
dma_if_pcie_wr_inst (
@ -422,12 +401,6 @@ dma_if_pcie_wr_inst (
.s_axis_tx_seq_num(s_axis_wr_req_tx_seq_num),
.s_axis_tx_seq_num_valid(s_axis_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
*/
.pcie_tx_fc_ph_av(pcie_tx_fc_ph_av),
.pcie_tx_fc_pd_av(pcie_tx_fc_pd_av),
/*
* AXI write descriptor input
*/
@ -482,7 +455,6 @@ dma_if_pcie_wr_inst (
.stat_wr_req_finish_status(stat_wr_req_finish_status),
.stat_wr_req_finish_valid(stat_wr_req_finish_valid),
.stat_wr_op_table_full(stat_wr_op_table_full),
.stat_wr_tx_no_credit(stat_wr_tx_no_credit),
.stat_wr_tx_limit(stat_wr_tx_limit),
.stat_wr_tx_stall(stat_wr_tx_stall)
);

19
fpga/lib/pcie/rtl/dma_if_pcie_rd.v
View File

@ -69,8 +69,6 @@ module dma_if_pcie_rd #
parameter OP_TABLE_SIZE = PCIE_TAG_COUNT,
// In-flight transmit limit
parameter TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Transmit flow control
parameter TX_FC_ENABLE = 0,
// Force 64 bit address
parameter TLP_FORCE_64_BIT_ADDR = 0,
// Requester ID mash
@ -107,11 +105,6 @@ module dma_if_pcie_rd #
input wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] s_axis_tx_seq_num,
input wire [TX_SEQ_NUM_COUNT-1:0] s_axis_tx_seq_num_valid,
/*
* Transmit flow control
*/
input wire [7:0] pcie_tx_fc_nph_av,
/*
* AXI read descriptor input
*/
@ -173,7 +166,6 @@ module dma_if_pcie_rd #
output wire stat_rd_req_timeout,
output wire stat_rd_op_table_full,
output wire stat_rd_no_tags,
output wire stat_rd_tx_no_credit,
output wire stat_rd_tx_limit,
output wire stat_rd_tx_stall
);
@ -379,8 +371,6 @@ reg [127:0] tlp_hdr;
reg [10:0] max_read_request_size_dw_reg = 11'd0;
reg have_credit_reg = 1'b0;
reg [STATUS_FIFO_ADDR_WIDTH+1-1:0] status_fifo_wr_ptr_reg = 0;
reg [STATUS_FIFO_ADDR_WIDTH+1-1:0] status_fifo_rd_ptr_reg = 0;
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
@ -441,7 +431,6 @@ reg stat_rd_req_finish_valid_reg = 1'b0, stat_rd_req_finish_valid_next;
reg stat_rd_req_timeout_reg = 1'b0, stat_rd_req_timeout_next;
reg stat_rd_op_table_full_reg = 1'b0, stat_rd_op_table_full_next;
reg stat_rd_no_tags_reg = 1'b0, stat_rd_no_tags_next;
reg stat_rd_tx_no_credit_reg = 1'b0, stat_rd_tx_no_credit_next;
reg stat_rd_tx_limit_reg = 1'b0, stat_rd_tx_limit_next;
reg stat_rd_tx_stall_reg = 1'b0, stat_rd_tx_stall_next;
@ -488,7 +477,6 @@ assign stat_rd_req_finish_valid = stat_rd_req_finish_valid_reg;
assign stat_rd_req_timeout = stat_rd_req_timeout_reg;
assign stat_rd_op_table_full = stat_rd_op_table_full_reg;
assign stat_rd_no_tags = stat_rd_no_tags_reg;
assign stat_rd_tx_no_credit = stat_rd_tx_no_credit_reg;
assign stat_rd_tx_limit = stat_rd_tx_limit_reg;
assign stat_rd_tx_stall = stat_rd_tx_stall_reg;
@ -606,7 +594,6 @@ always @* begin
stat_rd_req_start_valid_next = 1'b0;
stat_rd_op_table_full_next = op_tag_fifo_rd_ptr_reg == op_tag_fifo_wr_ptr_reg;
stat_rd_no_tags_next = !req_pcie_tag_valid_reg;
stat_rd_tx_no_credit_next = !(!TX_FC_ENABLE || have_credit_reg);
stat_rd_tx_limit_next = !(!TX_SEQ_NUM_ENABLE || active_tx_count_av_reg);
stat_rd_tx_stall_next = !(!tx_rd_req_tlp_valid_reg || tx_rd_req_tlp_ready);
@ -755,7 +742,7 @@ always @* begin
tx_rd_req_tlp_hdr_next = tlp_hdr;
end
if ((!tx_rd_req_tlp_valid_reg || tx_rd_req_tlp_ready) && req_pcie_tag_valid_reg && (!TX_FC_ENABLE || have_credit_reg) && (!TX_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin
if ((!tx_rd_req_tlp_valid_reg || tx_rd_req_tlp_ready) && req_pcie_tag_valid_reg && (!TX_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin
tx_rd_req_tlp_valid_next = 1'b1;
inc_active_tx = 1'b1;
@ -1388,14 +1375,11 @@ always @(posedge clk) begin
stat_rd_req_timeout_reg <= stat_rd_req_timeout_next;
stat_rd_op_table_full_reg <= stat_rd_op_table_full_next;
stat_rd_no_tags_reg <= stat_rd_no_tags_next;
stat_rd_tx_no_credit_reg <= stat_rd_tx_no_credit_next;
stat_rd_tx_limit_reg <= stat_rd_tx_limit_next;
stat_rd_tx_stall_reg <= stat_rd_tx_stall_next;
max_read_request_size_dw_reg <= 11'd32 << (max_read_request_size > 5 ? 5 : max_read_request_size);
have_credit_reg <= pcie_tx_fc_nph_av > 4;
if (status_fifo_wr_en) begin
status_fifo_op_tag[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_op_tag;
status_fifo_mask[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_mask;
@ -1535,7 +1519,6 @@ always @(posedge clk) begin
stat_rd_req_timeout_reg <= 1'b0;
stat_rd_op_table_full_reg <= 1'b0;
stat_rd_no_tags_reg <= 1'b0;
stat_rd_tx_no_credit_reg <= 1'b0;
stat_rd_tx_limit_reg <= 1'b0;
stat_rd_tx_stall_reg <= 1'b0;

22
fpga/lib/pcie/rtl/dma_if_pcie_wr.v
View File

@ -73,8 +73,6 @@ module dma_if_pcie_wr #
parameter OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH,
// In-flight transmit limit
parameter TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Transmit flow control
parameter TX_FC_ENABLE = 0,
// Force 64 bit address
parameter TLP_FORCE_64_BIT_ADDR = 0
)
@ -100,12 +98,6 @@ module dma_if_pcie_wr #
input wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] s_axis_tx_seq_num,
input wire [TX_SEQ_NUM_COUNT-1:0] s_axis_tx_seq_num_valid,
/*
* Transmit flow control
*/
input wire [7:0] pcie_tx_fc_ph_av,
input wire [11:0] pcie_tx_fc_pd_av,
/*
* AXI write descriptor input
*/
@ -160,7 +152,6 @@ module dma_if_pcie_wr #
output wire [3:0] stat_wr_req_finish_status,
output wire stat_wr_req_finish_valid,
output wire stat_wr_op_table_full,
output wire stat_wr_tx_no_credit,
output wire stat_wr_tx_limit,
output wire stat_wr_tx_stall
);
@ -332,8 +323,6 @@ wire mask_fifo_full = mask_fifo_wr_ptr_reg == (mask_fifo_rd_ptr_reg ^ (1 << MASK
reg [10:0] max_payload_size_dw_reg = 11'd0;
reg have_credit_reg = 1'b0;
reg [TX_COUNT_WIDTH-1:0] active_tx_count_reg = {TX_COUNT_WIDTH{1'b0}}, active_tx_count_next;
reg active_tx_count_av_reg = 1'b1, active_tx_count_av_next;
reg inc_active_tx;
@ -367,7 +356,6 @@ reg stat_wr_req_start_valid_reg = 1'b0, stat_wr_req_start_valid_next;
reg [OP_TAG_WIDTH-1:0] stat_wr_req_finish_tag_reg = 0, stat_wr_req_finish_tag_next;
reg stat_wr_req_finish_valid_reg = 1'b0, stat_wr_req_finish_valid_next;
reg stat_wr_op_table_full_reg = 1'b0, stat_wr_op_table_full_next;
reg stat_wr_tx_no_credit_reg = 1'b0, stat_wr_tx_no_credit_next;
reg stat_wr_tx_limit_reg = 1'b0, stat_wr_tx_limit_next;
reg stat_wr_tx_stall_reg = 1'b0, stat_wr_tx_stall_next;
@ -403,7 +391,6 @@ assign stat_wr_req_finish_tag = stat_wr_req_finish_tag_reg;
assign stat_wr_req_finish_status = 4'd00;
assign stat_wr_req_finish_valid = stat_wr_req_finish_valid_reg;
assign stat_wr_op_table_full = stat_wr_op_table_full_reg;
assign stat_wr_tx_no_credit = stat_wr_tx_no_credit_reg;
assign stat_wr_tx_limit = stat_wr_tx_limit_reg;
assign stat_wr_tx_stall = stat_wr_tx_stall_reg;
@ -479,7 +466,6 @@ always @* begin
stat_wr_req_start_len_next = stat_wr_req_start_len_reg;
stat_wr_req_start_valid_next = 1'b0;
stat_wr_op_table_full_next = !(!op_table_active[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] && ($unsigned(op_table_start_ptr_reg - op_table_finish_ptr_reg) < 2**OP_TAG_WIDTH));
stat_wr_tx_no_credit_next = !(!TX_FC_ENABLE || have_credit_reg);
stat_wr_tx_limit_next = !(!TX_SEQ_NUM_ENABLE || active_tx_count_av_reg);
stat_wr_tx_stall_next = !(!tx_wr_req_tlp_valid_reg || tx_wr_req_tlp_ready);
@ -891,7 +877,7 @@ always @* begin
cycle_count_next = op_table_cycle_count[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
last_cycle_next = op_table_cycle_count[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] == 0;
if (op_table_active[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_tx_start_ptr_reg != op_table_start_ptr_reg && (!TX_FC_ENABLE || have_credit_reg) && (!TX_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin
if (op_table_active[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_tx_start_ptr_reg != op_table_start_ptr_reg && (!TX_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin
op_table_tx_start_en = 1'b1;
tlp_state_next = TLP_STATE_TRANSFER;
end else begin
@ -949,7 +935,7 @@ always @* begin
cycle_count_next = op_table_cycle_count[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]];
last_cycle_next = op_table_cycle_count[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] == 0;
if (op_table_active[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_tx_start_ptr_reg != op_table_start_ptr_reg && (!TX_FC_ENABLE || have_credit_reg) && (!TX_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin
if (op_table_active[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_tx_start_ptr_reg != op_table_start_ptr_reg && (!TX_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin
op_table_tx_start_en = 1'b1;
tlp_state_next = TLP_STATE_TRANSFER;
end else begin
@ -1097,14 +1083,11 @@ always @(posedge clk) begin
stat_wr_req_finish_tag_reg <= stat_wr_req_finish_tag_next;
stat_wr_req_finish_valid_reg <= stat_wr_req_finish_valid_next;
stat_wr_op_table_full_reg <= stat_wr_op_table_full_next;
stat_wr_tx_no_credit_reg <= stat_wr_tx_no_credit_next;
stat_wr_tx_limit_reg <= stat_wr_tx_limit_next;
stat_wr_tx_stall_reg <= stat_wr_tx_stall_next;
max_payload_size_dw_reg <= 11'd32 << (max_payload_size > 5 ? 5 : max_payload_size);
have_credit_reg <= (pcie_tx_fc_ph_av > 4) && (pcie_tx_fc_pd_av > (max_payload_size_dw_reg >> 1));
active_tx_count_reg <= active_tx_count_next;
active_tx_count_av_reg <= active_tx_count_av_next;
@ -1173,7 +1156,6 @@ always @(posedge clk) begin
stat_wr_req_start_valid_reg <= 1'b0;
stat_wr_req_finish_valid_reg <= 1'b0;
stat_wr_op_table_full_reg <= 1'b0;
stat_wr_tx_no_credit_reg <= 1'b0;
stat_wr_tx_limit_reg <= 1'b0;
stat_wr_tx_stall_reg <= 1'b0;

3
fpga/lib/pcie/tb/dma_if_pcie_rd/Makefile
View File

@ -50,7 +50,6 @@ export PARAM_LEN_WIDTH ?= 20
export PARAM_TAG_WIDTH ?= 8
export PARAM_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
export PARAM_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_TX_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_TX_FC_ENABLE ?= 1
export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0
export PARAM_CHECK_BUS_NUMBER ?= 1
@ -75,7 +74,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).OP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_LIMIT=$(PARAM_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FC_ENABLE=$(PARAM_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_FORCE_64_BIT_ADDR=$(PARAM_TLP_FORCE_64_BIT_ADDR)
COMPILE_ARGS += -P $(TOPLEVEL).CHECK_BUS_NUMBER=$(PARAM_CHECK_BUS_NUMBER)
@ -104,7 +102,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -GOP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE)
COMPILE_ARGS += -GTX_LIMIT=$(PARAM_TX_LIMIT)
COMPILE_ARGS += -GTX_FC_ENABLE=$(PARAM_TX_FC_ENABLE)
COMPILE_ARGS += -GTLP_FORCE_64_BIT_ADDR=$(PARAM_TLP_FORCE_64_BIT_ADDR)
COMPILE_ARGS += -GCHECK_BUS_NUMBER=$(PARAM_CHECK_BUS_NUMBER)

3
fpga/lib/pcie/tb/dma_if_pcie_rd/test_dma_if_pcie_rd.py
View File

@ -85,8 +85,6 @@ class TB(object):
cfg_max_read_req=dut.max_read_request_size,
cfg_ext_tag_enable=dut.ext_tag_enable,
tx_fc_nph_av=dut.pcie_tx_fc_nph_av,
)
self.dev.log.setLevel(logging.DEBUG)
@ -332,7 +330,6 @@ def test_dma_if_pcie_rd(request, pcie_data_width, pcie_offset):
parameters['TAG_WIDTH'] = 8
parameters['OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
parameters['TX_LIMIT'] = 2**(parameters['TX_SEQ_NUM_WIDTH']-1)
parameters['TX_FC_ENABLE'] = 1
parameters['TLP_FORCE_64_BIT_ADDR'] = 0
parameters['CHECK_BUS_NUMBER'] = 0

3
fpga/lib/pcie/tb/dma_if_pcie_wr/Makefile
View File

@ -52,7 +52,6 @@ export PARAM_LEN_WIDTH ?= 20
export PARAM_TAG_WIDTH ?= 8
export PARAM_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << ($(PARAM_TX_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_TX_SEQ_NUM_WIDTH)-1) ))" )
export PARAM_TX_FC_ENABLE ?= 1
export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0
ifeq ($(SIM), icarus)
@ -78,7 +77,6 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).OP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_LIMIT=$(PARAM_TX_LIMIT)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FC_ENABLE=$(PARAM_TX_FC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_FORCE_64_BIT_ADDR=$(PARAM_TLP_FORCE_64_BIT_ADDR)
ifeq ($(WAVES), 1)
@ -108,7 +106,6 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -GOP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE)
COMPILE_ARGS += -GTX_LIMIT=$(PARAM_TX_LIMIT)
COMPILE_ARGS += -GTX_FC_ENABLE=$(PARAM_TX_FC_ENABLE)
COMPILE_ARGS += -GTLP_FORCE_64_BIT_ADDR=$(PARAM_TLP_FORCE_64_BIT_ADDR)
ifeq ($(WAVES), 1)

4
fpga/lib/pcie/tb/dma_if_pcie_wr/test_dma_if_pcie_wr.py
View File

@ -82,9 +82,6 @@ class TB(object):
wr_req_tx_seq_num_valid=dut.s_axis_tx_seq_num_valid,
cfg_max_payload=dut.max_payload_size,
tx_fc_ph_av=dut.pcie_tx_fc_ph_av,
tx_fc_pd_av=dut.pcie_tx_fc_pd_av,
)
self.dev.log.setLevel(logging.DEBUG)
@ -305,7 +302,6 @@ def test_dma_if_pcie_wr(request, pcie_data_width, pcie_offset):
parameters['TAG_WIDTH'] = 8
parameters['OP_TABLE_SIZE'] = 2**(parameters['TX_SEQ_NUM_WIDTH']-1)
parameters['TX_LIMIT'] = 2**(parameters['TX_SEQ_NUM_WIDTH']-1)
parameters['TX_FC_ENABLE'] = 1
parameters['TLP_FORCE_64_BIT_ADDR'] = 0
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}