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Add AXI stream mux module
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Alex Forencich
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061756f667
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rtl/axis_arb_mux.v
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245
rtl/axis_arb_mux.v
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/*
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream arbitrated multiplexer
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*/
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module axis_arb_mux #
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(
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parameter S_COUNT = 4,
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parameter DATA_WIDTH = 8,
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parameter KEEP_ENABLE = (DATA_WIDTH>8),
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parameter KEEP_WIDTH = (DATA_WIDTH/8),
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parameter ID_ENABLE = 0,
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parameter ID_WIDTH = 8,
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parameter DEST_ENABLE = 0,
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parameter DEST_WIDTH = 8,
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parameter USER_ENABLE = 1,
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parameter USER_WIDTH = 1,
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// arbitration type: "PRIORITY" or "ROUND_ROBIN"
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parameter ARB_TYPE = "PRIORITY",
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// LSB priority: "LOW", "HIGH"
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parameter LSB_PRIORITY = "HIGH"
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI Stream inputs
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*/
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input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata,
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input wire [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep,
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input wire [S_COUNT-1:0] s_axis_tvalid,
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output wire [S_COUNT-1:0] s_axis_tready,
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input wire [S_COUNT-1:0] s_axis_tlast,
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input wire [S_COUNT*ID_WIDTH-1:0] s_axis_tid,
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input wire [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest,
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input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser,
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/*
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* AXI Stream output
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*/
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output wire [DATA_WIDTH-1:0] m_axis_tdata,
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output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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output wire m_axis_tlast,
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output wire [ID_WIDTH-1:0] m_axis_tid,
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output wire [DEST_WIDTH-1:0] m_axis_tdest,
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output wire [USER_WIDTH-1:0] m_axis_tuser
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);
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parameter CL_S_COUNT = $clog2(S_COUNT);
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wire [S_COUNT-1:0] request;
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wire [S_COUNT-1:0] acknowledge;
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wire [S_COUNT-1:0] grant;
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wire grant_valid;
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wire [CL_S_COUNT-1:0] grant_encoded;
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// internal datapath
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reg [DATA_WIDTH-1:0] m_axis_tdata_int;
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reg [KEEP_WIDTH-1:0] m_axis_tkeep_int;
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reg m_axis_tvalid_int;
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reg m_axis_tready_int_reg = 1'b0;
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reg m_axis_tlast_int;
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reg [ID_WIDTH-1:0] m_axis_tid_int;
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reg [DEST_WIDTH-1:0] m_axis_tdest_int;
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reg [USER_WIDTH-1:0] m_axis_tuser_int;
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wire m_axis_tready_int_early;
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assign s_axis_tready = (m_axis_tready_int_reg && grant_valid) << grant_encoded;
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// mux for incoming packet
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wire [DATA_WIDTH-1:0] current_s_tdata = s_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH];
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wire [KEEP_WIDTH-1:0] current_s_tkeep = s_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
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wire current_s_tvalid = s_axis_tvalid[grant_encoded];
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wire current_s_tready = s_axis_tready[grant_encoded];
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wire current_s_tlast = s_axis_tlast[grant_encoded];
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wire [ID_WIDTH-1:0] current_s_tid = s_axis_tid[grant_encoded*ID_WIDTH +: ID_WIDTH];
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wire [DEST_WIDTH-1:0] current_s_tdest = s_axis_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH];
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wire [USER_WIDTH-1:0] current_s_tuser = s_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH];
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// arbiter instance
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arbiter #(
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.PORTS(S_COUNT),
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.TYPE(ARB_TYPE),
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.BLOCK("ACKNOWLEDGE"),
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.LSB_PRIORITY(LSB_PRIORITY)
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)
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arb_inst (
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.clk(clk),
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.rst(rst),
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.request(request),
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.acknowledge(acknowledge),
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.grant(grant),
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.grant_valid(grant_valid),
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.grant_encoded(grant_encoded)
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);
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generate
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genvar n;
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for (n = 0; n < S_COUNT; n = n + 1) begin
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assign request[n] = s_axis_tvalid[n] && !grant[n];
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assign acknowledge[n] = grant[n] && s_axis_tvalid[n] && s_axis_tready[n] && s_axis_tlast[n];
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end
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endgenerate
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always @* begin
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// pass through selected packet data
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m_axis_tdata_int = current_s_tdata;
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m_axis_tkeep_int = current_s_tkeep;
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m_axis_tvalid_int = current_s_tvalid && m_axis_tready_int_reg && grant_valid;
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m_axis_tlast_int = current_s_tlast;
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m_axis_tid_int = current_s_tid;
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m_axis_tdest_int = current_s_tdest;
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m_axis_tuser_int = current_s_tuser;
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end
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// output datapath logic
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reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
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reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
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reg m_axis_tlast_reg = 1'b0;
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reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
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reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
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reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
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reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
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reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
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reg temp_m_axis_tlast_reg = 1'b0;
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reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
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reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
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reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
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// datapath control
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reg store_axis_int_to_output;
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reg store_axis_int_to_temp;
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reg store_axis_temp_to_output;
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assign m_axis_tdata = m_axis_tdata_reg;
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assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
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assign m_axis_tvalid = m_axis_tvalid_reg;
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assign m_axis_tlast = m_axis_tlast_reg;
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assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
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assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
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assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
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always @* begin
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// transfer sink ready state to source
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m_axis_tvalid_next = m_axis_tvalid_reg;
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temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
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store_axis_int_to_output = 1'b0;
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store_axis_int_to_temp = 1'b0;
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store_axis_temp_to_output = 1'b0;
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if (m_axis_tready_int_reg) begin
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// input is ready
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if (m_axis_tready || !m_axis_tvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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m_axis_tvalid_next = m_axis_tvalid_int;
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store_axis_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_m_axis_tvalid_next = m_axis_tvalid_int;
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store_axis_int_to_temp = 1'b1;
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end
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end else if (m_axis_tready) begin
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// input is not ready, but output is ready
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m_axis_tvalid_next = temp_m_axis_tvalid_reg;
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temp_m_axis_tvalid_next = 1'b0;
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store_axis_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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m_axis_tvalid_reg <= 1'b0;
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m_axis_tready_int_reg <= 1'b0;
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temp_m_axis_tvalid_reg <= 1'b0;
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end else begin
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m_axis_tvalid_reg <= m_axis_tvalid_next;
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m_axis_tready_int_reg <= m_axis_tready_int_early;
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temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
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end
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// datapath
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if (store_axis_int_to_output) begin
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m_axis_tdata_reg <= m_axis_tdata_int;
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m_axis_tkeep_reg <= m_axis_tkeep_int;
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m_axis_tlast_reg <= m_axis_tlast_int;
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m_axis_tid_reg <= m_axis_tid_int;
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m_axis_tdest_reg <= m_axis_tdest_int;
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m_axis_tuser_reg <= m_axis_tuser_int;
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end else if (store_axis_temp_to_output) begin
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m_axis_tdata_reg <= temp_m_axis_tdata_reg;
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m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
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m_axis_tlast_reg <= temp_m_axis_tlast_reg;
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m_axis_tid_reg <= temp_m_axis_tid_reg;
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m_axis_tdest_reg <= temp_m_axis_tdest_reg;
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m_axis_tuser_reg <= temp_m_axis_tuser_reg;
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end
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if (store_axis_int_to_temp) begin
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temp_m_axis_tdata_reg <= m_axis_tdata_int;
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temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
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temp_m_axis_tlast_reg <= m_axis_tlast_int;
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temp_m_axis_tid_reg <= m_axis_tid_int;
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temp_m_axis_tdest_reg <= m_axis_tdest_int;
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temp_m_axis_tuser_reg <= m_axis_tuser_int;
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end
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end
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endmodule
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