mirror of
https://github.com/corundum/corundum.git
synced 2025-01-16 08:12:53 +08:00
Add AXI stream switch module, generator script, and testbench
This commit is contained in:
Alex Forencich
parent
5fe35a79d2
commit
06bfa1944c
477
rtl/axis_switch.py
Executable file
477
rtl/axis_switch.py
Executable file
@ -0,0 +1,477 @@
|
||||
#!/usr/bin/env python
|
||||
"""
|
||||
Generates an AXI Stream switch with the specified number of ports
|
||||
"""
|
||||
|
||||
from __future__ import print_function
|
||||
|
||||
import argparse
|
||||
import math
|
||||
from jinja2 import Template
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(description=__doc__.strip())
|
||||
parser.add_argument('-p', '--ports', type=int, default=[4], nargs='+', help="number of ports")
|
||||
parser.add_argument('-n', '--name', type=str, help="module name")
|
||||
parser.add_argument('-o', '--output', type=str, help="output file name")
|
||||
|
||||
args = parser.parse_args()
|
||||
|
||||
try:
|
||||
generate(**args.__dict__)
|
||||
except IOError as ex:
|
||||
print(ex)
|
||||
exit(1)
|
||||
|
||||
def generate(ports=4, name=None, output=None):
|
||||
if type(ports) is int:
|
||||
m = n = ports
|
||||
elif len(ports) == 1:
|
||||
m = n = ports[0]
|
||||
else:
|
||||
m, n = ports
|
||||
|
||||
if name is None:
|
||||
name = "axis_switch_{0}x{1}".format(m, n)
|
||||
|
||||
if output is None:
|
||||
output = name + ".v"
|
||||
|
||||
print("Opening file '{0}'...".format(output))
|
||||
|
||||
output_file = open(output, 'w')
|
||||
|
||||
print("Generating {0}x{1} port AXI Stream switch {2}...".format(m, n, name))
|
||||
|
||||
cm = int(math.ceil(math.log(m, 2)))
|
||||
cn = int(math.ceil(math.log(n, 2)))
|
||||
|
||||
t = Template(u"""/*
|
||||
|
||||
Copyright (c) 2016 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* AXI4-Stream {{m}}x{{n}} switch
|
||||
*/
|
||||
module {{name}} #
|
||||
(
|
||||
parameter DATA_WIDTH = 8,
|
||||
parameter DEST_WIDTH = {{cn}},
|
||||
{%- for p in range(n) %}
|
||||
parameter OUT_{{p}}_BASE = {{p}},
|
||||
parameter OUT_{{p}}_TOP = {{p}},
|
||||
parameter OUT_{{p}}_CONNECT = {{m}}'b{% for p in range(m) %}1{% endfor %},
|
||||
{%- endfor %}
|
||||
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
|
||||
parameter ARB_TYPE = "ROUND_ROBIN",
|
||||
// LSB priority: "LOW", "HIGH"
|
||||
parameter LSB_PRIORITY = "HIGH"
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* AXI Stream inputs
|
||||
*/
|
||||
{%- for p in range(m) %}
|
||||
input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata,
|
||||
input wire input_{{p}}_axis_tvalid,
|
||||
output wire input_{{p}}_axis_tready,
|
||||
input wire input_{{p}}_axis_tlast,
|
||||
input wire [DEST_WIDTH-1:0] input_{{p}}_axis_tdest,
|
||||
input wire input_{{p}}_axis_tuser,
|
||||
{% endfor %}
|
||||
/*
|
||||
* AXI Stream outputs
|
||||
*/
|
||||
{%- for p in range(n) %}
|
||||
output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata,
|
||||
output wire output_{{p}}_axis_tvalid,
|
||||
input wire output_{{p}}_axis_tready,
|
||||
output wire output_{{p}}_axis_tlast,
|
||||
output wire [DEST_WIDTH-1:0] output_{{p}}_axis_tdest,
|
||||
output wire output_{{p}}_axis_tuser{% if not loop.last %},{% endif %}
|
||||
{% endfor -%}
|
||||
);
|
||||
|
||||
// check configuration
|
||||
initial begin
|
||||
if (2**DEST_WIDTH < {{n}}) begin
|
||||
$error("Error: DEST_WIDTH too small for port count");
|
||||
$finish;
|
||||
end
|
||||
|
||||
if ({%- for p in range(n) %}(OUT_{{p}}_BASE & 2**DEST_WIDTH-1) != OUT_{{p}}_BASE || (OUT_{{p}}_TOP & 2**DEST_WIDTH-1) != OUT_{{p}}_TOP{% if not loop.last %} ||
|
||||
{% endif %}{% endfor -%}) begin
|
||||
$error("Error: value out of range");
|
||||
$finish;
|
||||
end
|
||||
|
||||
if ({%- for p in range(n) %}OUT_{{p}}_BASE > OUT_{{p}}_TOP{% if not loop.last %} ||
|
||||
{% endif %}{% endfor -%}) begin
|
||||
$error("Error: invalid range");
|
||||
$finish;
|
||||
end
|
||||
|
||||
if ({%- for p in range(n-1) %}{% set outer_loop = loop %}{%- for q in range(p+1,n) %}(OUT_{{p}}_BASE <= OUT_{{q}}_TOP && OUT_{{q}}_BASE <= OUT_{{p}}_TOP){% if not (loop.last and outer_loop.last) %} ||
|
||||
{% endif %}{% endfor -%}{% endfor -%}) begin
|
||||
$error("Error: ranges overlap");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
{%- for p in range(m) %}
|
||||
|
||||
reg [{{n-1}}:0] input_{{p}}_request_reg = {{n}}'d0, input_{{p}}_request_next;
|
||||
reg input_{{p}}_request_valid_reg = 1'b0, input_{{p}}_request_valid_next;
|
||||
reg input_{{p}}_request_error_reg = 1'b0, input_{{p}}_request_error_next;
|
||||
{%- endfor %}
|
||||
{% for p in range(n) %}
|
||||
reg [{{cm-1}}:0] select_{{p}}_reg = {{cm}}'d0, select_{{p}}_next;
|
||||
{%- endfor %}
|
||||
{% for p in range(n) %}
|
||||
reg enable_{{p}}_reg = 1'b0, enable_{{p}}_next;
|
||||
{%- endfor %}
|
||||
{% for p in range(m) %}
|
||||
reg input_{{p}}_axis_tready_reg = 1'b0, input_{{p}}_axis_tready_next;
|
||||
{%- endfor %}
|
||||
|
||||
// internal datapath
|
||||
{%- for p in range(n) %}
|
||||
reg [DATA_WIDTH-1:0] output_{{p}}_axis_tdata_int;
|
||||
reg output_{{p}}_axis_tvalid_int;
|
||||
reg output_{{p}}_axis_tready_int_reg = 1'b0;
|
||||
reg output_{{p}}_axis_tlast_int;
|
||||
reg [DEST_WIDTH-1:0] output_{{p}}_axis_tdest_int;
|
||||
reg output_{{p}}_axis_tuser_int;
|
||||
wire output_{{p}}_axis_tready_int_early;
|
||||
{% endfor %}
|
||||
{%- for p in range(m) %}
|
||||
assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg;
|
||||
{%- endfor %}
|
||||
|
||||
// mux for start of packet detection
|
||||
|
||||
{%- for p in range(n) %}
|
||||
reg selected_input_{{p}}_axis_tvalid;
|
||||
|
||||
always @* begin
|
||||
case (grant_encoded_{{p}})
|
||||
{%- for q in range(m) %}
|
||||
{{cm}}'d{{q}}: selected_input_{{p}}_axis_tvalid = input_{{q}}_axis_tvalid;
|
||||
{%- endfor %}
|
||||
default: selected_input_{{p}}_axis_tvalid = 1'b0;
|
||||
endcase
|
||||
end
|
||||
{% endfor %}
|
||||
// mux for incoming packet
|
||||
{% for p in range(n) %}
|
||||
reg [DATA_WIDTH-1:0] current_input_{{p}}_axis_tdata;
|
||||
reg current_input_{{p}}_axis_tvalid;
|
||||
reg current_input_{{p}}_axis_tready;
|
||||
reg current_input_{{p}}_axis_tlast;
|
||||
reg [DEST_WIDTH-1:0] current_input_{{p}}_axis_tdest;
|
||||
reg current_input_{{p}}_axis_tuser;
|
||||
|
||||
always @* begin
|
||||
case (select_{{p}}_reg)
|
||||
{%- for q in range(m) %}
|
||||
{{cm}}'d{{q}}: begin
|
||||
current_input_{{p}}_axis_tdata = input_{{q}}_axis_tdata;
|
||||
current_input_{{p}}_axis_tvalid = input_{{q}}_axis_tvalid;
|
||||
current_input_{{p}}_axis_tready = input_{{q}}_axis_tready;
|
||||
current_input_{{p}}_axis_tlast = input_{{q}}_axis_tlast;
|
||||
current_input_{{p}}_axis_tdest = input_{{q}}_axis_tdest;
|
||||
current_input_{{p}}_axis_tuser = input_{{q}}_axis_tuser;
|
||||
end
|
||||
{%- endfor %}
|
||||
default: begin
|
||||
current_input_{{p}}_axis_tdata = {DATA_WIDTH{1'b0}};
|
||||
current_input_{{p}}_axis_tvalid = 1'b0;
|
||||
current_input_{{p}}_axis_tready = 1'b0;
|
||||
current_input_{{p}}_axis_tlast = 1'b0;
|
||||
current_input_{{p}}_axis_tdest = {DEST_WIDTH{1'b0}};
|
||||
current_input_{{p}}_axis_tuser = 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
{% endfor %}
|
||||
// arbiter instances
|
||||
{% for p in range(n) %}
|
||||
wire [{{m-1}}:0] request_{{p}};
|
||||
wire [{{m-1}}:0] acknowledge_{{p}};
|
||||
wire [{{m-1}}:0] grant_{{p}};
|
||||
wire grant_valid_{{p}};
|
||||
wire [{{cm-1}}:0] grant_encoded_{{p}};
|
||||
{% endfor %}
|
||||
|
||||
{%- for p in range(n) %}
|
||||
arbiter #(
|
||||
.PORTS({{m}}),
|
||||
.TYPE(ARB_TYPE),
|
||||
.BLOCK("ACKNOWLEDGE"),
|
||||
.LSB_PRIORITY(LSB_PRIORITY)
|
||||
)
|
||||
arb_{{p}}_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.request(request_{{p}}),
|
||||
.acknowledge(acknowledge_{{p}}),
|
||||
.grant(grant_{{p}}),
|
||||
.grant_valid(grant_valid_{{p}}),
|
||||
.grant_encoded(grant_encoded_{{p}})
|
||||
);
|
||||
{% endfor %}
|
||||
// request generation
|
||||
{%- for p in range(n) %}
|
||||
{%- for q in range(m) %}
|
||||
assign request_{{p}}[{{q}}] = input_{{q}}_request_reg[{{p}}] & ~acknowledge_{{p}}[{{q}}];
|
||||
{%- endfor %}
|
||||
{% endfor %}
|
||||
// acknowledge generation
|
||||
{%- for p in range(n) %}
|
||||
{%- for q in range(m) %}
|
||||
assign acknowledge_{{p}}[{{q}}] = grant_{{p}}[{{q}}] & input_{{q}}_axis_tvalid & input_{{q}}_axis_tready & input_{{q}}_axis_tlast;
|
||||
{%- endfor %}
|
||||
{% endfor %}
|
||||
always @* begin
|
||||
{%- for p in range(n) %}
|
||||
select_{{p}}_next = select_{{p}}_reg;
|
||||
{%- endfor %}
|
||||
{% for p in range(n) %}
|
||||
enable_{{p}}_next = enable_{{p}}_reg;
|
||||
{%- endfor %}
|
||||
{% for p in range(m) %}
|
||||
input_{{p}}_request_next = input_{{p}}_request_reg;
|
||||
input_{{p}}_request_valid_next = input_{{p}}_request_valid_reg;
|
||||
input_{{p}}_request_error_next = input_{{p}}_request_error_reg;
|
||||
{% endfor %}
|
||||
{%- for p in range(m) %}
|
||||
input_{{p}}_axis_tready_next = 1'b0;
|
||||
{%- endfor %}
|
||||
{% for p in range(n) %}
|
||||
output_{{p}}_axis_tdata_int = {DATA_WIDTH{1'b0}};
|
||||
output_{{p}}_axis_tvalid_int = 1'b0;
|
||||
output_{{p}}_axis_tlast_int = 1'b0;
|
||||
output_{{p}}_axis_tdest_int = {DEST_WIDTH{1'b0}};
|
||||
output_{{p}}_axis_tuser_int = 1'b0;
|
||||
{% endfor %}
|
||||
// input decoding
|
||||
{% for p in range(m) %}
|
||||
if (input_{{p}}_request_valid_reg | input_{{p}}_request_error_reg) begin
|
||||
if (input_{{p}}_axis_tvalid & input_{{p}}_axis_tready & input_{{p}}_axis_tlast) begin
|
||||
input_{{p}}_request_next = {DEST_WIDTH{1'b0}};
|
||||
input_{{p}}_request_valid_next = 1'b0;
|
||||
input_{{p}}_request_error_next = 1'b0;
|
||||
end
|
||||
end else if (input_{{p}}_axis_tvalid) begin
|
||||
{%- for q in range(n) %}
|
||||
input_{{p}}_request_next[{{q}}] = (input_{{p}}_axis_tdest >= OUT_{{q}}_BASE) & (input_{{p}}_axis_tdest <= OUT_{{q}}_TOP) & OUT_{{q}}_CONNECT[{{p}}];
|
||||
{%- endfor %}
|
||||
|
||||
if (input_{{p}}_request_next) begin
|
||||
input_{{p}}_request_valid_next = 1'b1;
|
||||
end else begin
|
||||
input_{{p}}_request_error_next = 1'b1;
|
||||
end
|
||||
end
|
||||
{% endfor %}
|
||||
// output control
|
||||
{% for p in range(n) %}
|
||||
if (enable_{{p}}_reg) begin
|
||||
if (current_input_{{p}}_axis_tvalid & current_input_{{p}}_axis_tready) begin
|
||||
enable_{{p}}_next = ~current_input_{{p}}_axis_tlast;
|
||||
end
|
||||
end else if (grant_valid_{{p}} & selected_input_{{p}}_axis_tvalid) begin
|
||||
enable_{{p}}_next = 1'b1;
|
||||
select_{{p}}_next = grant_encoded_{{p}};
|
||||
end
|
||||
{% endfor %}
|
||||
// generate ready signal on selected port
|
||||
{% for p in range(n) %}
|
||||
if (enable_{{p}}_next) begin
|
||||
case (select_{{p}}_next)
|
||||
{%- for q in range(m) %}
|
||||
{{cm}}'d{{q}}: input_{{q}}_axis_tready_next = output_{{p}}_axis_tready_int_early;
|
||||
{%- endfor %}
|
||||
endcase
|
||||
end
|
||||
{% endfor %}
|
||||
|
||||
{%- for p in range(m) %}
|
||||
if (input_{{p}}_request_error_next)
|
||||
input_{{p}}_axis_tready_next = 1'b1;
|
||||
{%- endfor %}
|
||||
|
||||
// pass through selected packet data
|
||||
{% for p in range(n) %}
|
||||
output_{{p}}_axis_tdata_int = current_input_{{p}}_axis_tdata;
|
||||
output_{{p}}_axis_tvalid_int = current_input_{{p}}_axis_tvalid & current_input_{{p}}_axis_tready & enable_{{p}}_reg;
|
||||
output_{{p}}_axis_tlast_int = current_input_{{p}}_axis_tlast;
|
||||
output_{{p}}_axis_tdest_int = current_input_{{p}}_axis_tdest;
|
||||
output_{{p}}_axis_tuser_int = current_input_{{p}}_axis_tuser;
|
||||
{% endfor -%}
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
{%- for p in range(m) %}
|
||||
input_{{p}}_request_reg <= {{n}}'d0;
|
||||
input_{{p}}_request_valid_reg <= 1'b0;
|
||||
input_{{p}}_request_error_reg <= 1'b0;
|
||||
{%- endfor %}
|
||||
{%- for p in range(n) %}
|
||||
select_{{p}}_reg <= 2'd0;
|
||||
{%- endfor %}
|
||||
{%- for p in range(n) %}
|
||||
enable_{{p}}_reg <= 1'b0;
|
||||
{%- endfor %}
|
||||
{%- for p in range(m) %}
|
||||
input_{{p}}_axis_tready_reg <= 1'b0;
|
||||
{%- endfor %}
|
||||
end else begin
|
||||
{%- for p in range(m) %}
|
||||
input_{{p}}_request_reg <= input_{{p}}_request_next;
|
||||
input_{{p}}_request_valid_reg <= input_{{p}}_request_valid_next;
|
||||
input_{{p}}_request_error_reg <= input_{{p}}_request_error_next;
|
||||
{%- endfor %}
|
||||
{%- for p in range(n) %}
|
||||
select_{{p}}_reg <= select_{{p}}_next;
|
||||
{%- endfor %}
|
||||
{%- for p in range(n) %}
|
||||
enable_{{p}}_reg <= enable_{{p}}_next;
|
||||
{%- endfor %}
|
||||
{%- for p in range(m) %}
|
||||
input_{{p}}_axis_tready_reg <= input_{{p}}_axis_tready_next;
|
||||
{%- endfor %}
|
||||
end
|
||||
end
|
||||
{% for p in range(n) %}
|
||||
// output {{p}} datapath logic
|
||||
reg [DATA_WIDTH-1:0] output_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}};
|
||||
reg output_{{p}}_axis_tvalid_reg = 1'b0, output_{{p}}_axis_tvalid_next;
|
||||
reg output_{{p}}_axis_tlast_reg = 1'b0;
|
||||
reg [DEST_WIDTH-1:0] output_{{p}}_axis_tdest_reg = {DEST_WIDTH{1'b0}};
|
||||
reg output_{{p}}_axis_tuser_reg = 1'b0;
|
||||
|
||||
reg [DATA_WIDTH-1:0] temp_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}};
|
||||
reg temp_{{p}}_axis_tvalid_reg = 1'b0, temp_{{p}}_axis_tvalid_next;
|
||||
reg temp_{{p}}_axis_tlast_reg = 1'b0;
|
||||
reg [DEST_WIDTH-1:0] temp_{{p}}_axis_tdest_reg = {DEST_WIDTH{1'b0}};
|
||||
reg temp_{{p}}_axis_tuser_reg = 1'b0;
|
||||
|
||||
// datapath control
|
||||
reg store_{{p}}_axis_int_to_output;
|
||||
reg store_{{p}}_axis_int_to_temp;
|
||||
reg store_{{p}}_axis_temp_to_output;
|
||||
|
||||
assign output_{{p}}_axis_tdata = output_{{p}}_axis_tdata_reg;
|
||||
assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg;
|
||||
assign output_{{p}}_axis_tlast = output_{{p}}_axis_tlast_reg;
|
||||
assign output_{{p}}_axis_tdest = output_{{p}}_axis_tdest_reg;
|
||||
assign output_{{p}}_axis_tuser = output_{{p}}_axis_tuser_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign output_{{p}}_axis_tready_int_early = output_{{p}}_axis_tready | (~temp_{{p}}_axis_tvalid_reg & (~output_{{p}}_axis_tvalid_reg | ~output_{{p}}_axis_tvalid_int));
|
||||
|
||||
always @* begin
|
||||
// transfer sink ready state to source
|
||||
output_{{p}}_axis_tvalid_next = output_{{p}}_axis_tvalid_reg;
|
||||
temp_{{p}}_axis_tvalid_next = temp_{{p}}_axis_tvalid_reg;
|
||||
|
||||
store_{{p}}_axis_int_to_output = 1'b0;
|
||||
store_{{p}}_axis_int_to_temp = 1'b0;
|
||||
store_{{p}}_axis_temp_to_output = 1'b0;
|
||||
|
||||
if (output_{{p}}_axis_tready_int_reg) begin
|
||||
// input is ready
|
||||
if (output_{{p}}_axis_tready | ~output_{{p}}_axis_tvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
output_{{p}}_axis_tvalid_next = output_{{p}}_axis_tvalid_int;
|
||||
store_{{p}}_axis_int_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_{{p}}_axis_tvalid_next = output_{{p}}_axis_tvalid_int;
|
||||
store_{{p}}_axis_int_to_temp = 1'b1;
|
||||
end
|
||||
end else if (output_{{p}}_axis_tready) begin
|
||||
// input is not ready, but output is ready
|
||||
output_{{p}}_axis_tvalid_next = temp_{{p}}_axis_tvalid_reg;
|
||||
temp_{{p}}_axis_tvalid_next = 1'b0;
|
||||
store_{{p}}_axis_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
output_{{p}}_axis_tvalid_reg <= 1'b0;
|
||||
output_{{p}}_axis_tready_int_reg <= 1'b0;
|
||||
temp_{{p}}_axis_tvalid_reg <= 1'b0;
|
||||
end else begin
|
||||
output_{{p}}_axis_tvalid_reg <= output_{{p}}_axis_tvalid_next;
|
||||
output_{{p}}_axis_tready_int_reg <= output_{{p}}_axis_tready_int_early;
|
||||
temp_{{p}}_axis_tvalid_reg <= temp_{{p}}_axis_tvalid_next;
|
||||
end
|
||||
|
||||
// datapath
|
||||
if (store_{{p}}_axis_int_to_output) begin
|
||||
output_{{p}}_axis_tdata_reg <= output_{{p}}_axis_tdata_int;
|
||||
output_{{p}}_axis_tlast_reg <= output_{{p}}_axis_tlast_int;
|
||||
output_{{p}}_axis_tdest_reg <= output_{{p}}_axis_tdest_int;
|
||||
output_{{p}}_axis_tuser_reg <= output_{{p}}_axis_tuser_int;
|
||||
end else if (store_{{p}}_axis_temp_to_output) begin
|
||||
output_{{p}}_axis_tdata_reg <= temp_{{p}}_axis_tdata_reg;
|
||||
output_{{p}}_axis_tlast_reg <= temp_{{p}}_axis_tlast_reg;
|
||||
output_{{p}}_axis_tdest_reg <= temp_{{p}}_axis_tdest_reg;
|
||||
output_{{p}}_axis_tuser_reg <= temp_{{p}}_axis_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_{{p}}_axis_int_to_temp) begin
|
||||
temp_{{p}}_axis_tdata_reg <= output_{{p}}_axis_tdata_int;
|
||||
temp_{{p}}_axis_tlast_reg <= output_{{p}}_axis_tlast_int;
|
||||
temp_{{p}}_axis_tdest_reg <= output_{{p}}_axis_tdest_int;
|
||||
temp_{{p}}_axis_tuser_reg <= output_{{p}}_axis_tuser_int;
|
||||
end
|
||||
end
|
||||
{% endfor %}
|
||||
endmodule
|
||||
|
||||
""")
|
||||
|
||||
output_file.write(t.render(
|
||||
m=m,
|
||||
n=n,
|
||||
cm=cm,
|
||||
cn=cn,
|
||||
name=name
|
||||
))
|
||||
|
||||
print("Done")
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
||||
1262
rtl/axis_switch_4x4.v
Normal file
1262
rtl/axis_switch_4x4.v
Normal file
File diff suppressed because it is too large
Load Diff
492
rtl/axis_switch_64.py
Executable file
492
rtl/axis_switch_64.py
Executable file
@ -0,0 +1,492 @@
|
||||
#!/usr/bin/env python
|
||||
"""
|
||||
Generates an AXI Stream switch with the specified number of ports
|
||||
"""
|
||||
|
||||
from __future__ import print_function
|
||||
|
||||
import argparse
|
||||
import math
|
||||
from jinja2 import Template
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(description=__doc__.strip())
|
||||
parser.add_argument('-p', '--ports', type=int, default=[4], nargs='+', help="number of ports")
|
||||
parser.add_argument('-n', '--name', type=str, help="module name")
|
||||
parser.add_argument('-o', '--output', type=str, help="output file name")
|
||||
|
||||
args = parser.parse_args()
|
||||
|
||||
try:
|
||||
generate(**args.__dict__)
|
||||
except IOError as ex:
|
||||
print(ex)
|
||||
exit(1)
|
||||
|
||||
def generate(ports=4, name=None, output=None):
|
||||
if type(ports) is int:
|
||||
m = n = ports
|
||||
elif len(ports) == 1:
|
||||
m = n = ports[0]
|
||||
else:
|
||||
m, n = ports
|
||||
|
||||
if name is None:
|
||||
name = "axis_switch_64_{0}x{1}".format(m, n)
|
||||
|
||||
if output is None:
|
||||
output = name + ".v"
|
||||
|
||||
print("Opening file '{0}'...".format(output))
|
||||
|
||||
output_file = open(output, 'w')
|
||||
|
||||
print("Generating {0}x{1} port AXI Stream switch {2}...".format(m, n, name))
|
||||
|
||||
cm = int(math.ceil(math.log(m, 2)))
|
||||
cn = int(math.ceil(math.log(n, 2)))
|
||||
|
||||
t = Template(u"""/*
|
||||
|
||||
Copyright (c) 2016 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* AXI4-Stream {{m}}x{{n}} switch (64 bit datapath)
|
||||
*/
|
||||
module {{name}} #
|
||||
(
|
||||
parameter DATA_WIDTH = 64,
|
||||
parameter KEEP_WIDTH = (DATA_WIDTH/8),
|
||||
parameter DEST_WIDTH = {{cn}},
|
||||
{%- for p in range(n) %}
|
||||
parameter OUT_{{p}}_BASE = {{p}},
|
||||
parameter OUT_{{p}}_TOP = {{p}},
|
||||
parameter OUT_{{p}}_CONNECT = {{m}}'b{% for p in range(m) %}1{% endfor %},
|
||||
{%- endfor %}
|
||||
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
|
||||
parameter ARB_TYPE = "ROUND_ROBIN",
|
||||
// LSB priority: "LOW", "HIGH"
|
||||
parameter LSB_PRIORITY = "HIGH"
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* AXI Stream inputs
|
||||
*/
|
||||
{%- for p in range(m) %}
|
||||
input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata,
|
||||
input wire [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep,
|
||||
input wire input_{{p}}_axis_tvalid,
|
||||
output wire input_{{p}}_axis_tready,
|
||||
input wire input_{{p}}_axis_tlast,
|
||||
input wire [DEST_WIDTH-1:0] input_{{p}}_axis_tdest,
|
||||
input wire input_{{p}}_axis_tuser,
|
||||
{% endfor %}
|
||||
/*
|
||||
* AXI Stream outputs
|
||||
*/
|
||||
{%- for p in range(n) %}
|
||||
output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata,
|
||||
output wire [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep,
|
||||
output wire output_{{p}}_axis_tvalid,
|
||||
input wire output_{{p}}_axis_tready,
|
||||
output wire output_{{p}}_axis_tlast,
|
||||
output wire [DEST_WIDTH-1:0] output_{{p}}_axis_tdest,
|
||||
output wire output_{{p}}_axis_tuser{% if not loop.last %},{% endif %}
|
||||
{% endfor -%}
|
||||
);
|
||||
|
||||
// check configuration
|
||||
initial begin
|
||||
if (2**DEST_WIDTH < {{n}}) begin
|
||||
$error("Error: DEST_WIDTH too small for port count");
|
||||
$finish;
|
||||
end
|
||||
|
||||
if ({%- for p in range(n) %}(OUT_{{p}}_BASE & 2**DEST_WIDTH-1) != OUT_{{p}}_BASE || (OUT_{{p}}_TOP & 2**DEST_WIDTH-1) != OUT_{{p}}_TOP{% if not loop.last %} ||
|
||||
{% endif %}{% endfor -%}) begin
|
||||
$error("Error: value out of range");
|
||||
$finish;
|
||||
end
|
||||
|
||||
if ({%- for p in range(n) %}OUT_{{p}}_BASE > OUT_{{p}}_TOP{% if not loop.last %} ||
|
||||
{% endif %}{% endfor -%}) begin
|
||||
$error("Error: invalid range");
|
||||
$finish;
|
||||
end
|
||||
|
||||
if ({%- for p in range(n-1) %}{% set outer_loop = loop %}{%- for q in range(p+1,n) %}(OUT_{{p}}_BASE <= OUT_{{q}}_TOP && OUT_{{q}}_BASE <= OUT_{{p}}_TOP){% if not (loop.last and outer_loop.last) %} ||
|
||||
{% endif %}{% endfor -%}{% endfor -%}) begin
|
||||
$error("Error: ranges overlap");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
{%- for p in range(m) %}
|
||||
|
||||
reg [{{n-1}}:0] input_{{p}}_request_reg = {{n}}'d0, input_{{p}}_request_next;
|
||||
reg input_{{p}}_request_valid_reg = 1'b0, input_{{p}}_request_valid_next;
|
||||
reg input_{{p}}_request_error_reg = 1'b0, input_{{p}}_request_error_next;
|
||||
{%- endfor %}
|
||||
{% for p in range(n) %}
|
||||
reg [{{cm-1}}:0] select_{{p}}_reg = {{cm}}'d0, select_{{p}}_next;
|
||||
{%- endfor %}
|
||||
{% for p in range(n) %}
|
||||
reg enable_{{p}}_reg = 1'b0, enable_{{p}}_next;
|
||||
{%- endfor %}
|
||||
{% for p in range(m) %}
|
||||
reg input_{{p}}_axis_tready_reg = 1'b0, input_{{p}}_axis_tready_next;
|
||||
{%- endfor %}
|
||||
|
||||
// internal datapath
|
||||
{%- for p in range(n) %}
|
||||
reg [DATA_WIDTH-1:0] output_{{p}}_axis_tdata_int;
|
||||
reg [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep_int;
|
||||
reg output_{{p}}_axis_tvalid_int;
|
||||
reg output_{{p}}_axis_tready_int_reg = 1'b0;
|
||||
reg output_{{p}}_axis_tlast_int;
|
||||
reg [DEST_WIDTH-1:0] output_{{p}}_axis_tdest_int;
|
||||
reg output_{{p}}_axis_tuser_int;
|
||||
wire output_{{p}}_axis_tready_int_early;
|
||||
{% endfor %}
|
||||
{%- for p in range(m) %}
|
||||
assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg;
|
||||
{%- endfor %}
|
||||
|
||||
// mux for start of packet detection
|
||||
|
||||
{%- for p in range(n) %}
|
||||
reg selected_input_{{p}}_axis_tvalid;
|
||||
|
||||
always @* begin
|
||||
case (grant_encoded_{{p}})
|
||||
{%- for q in range(m) %}
|
||||
{{cm}}'d{{q}}: selected_input_{{p}}_axis_tvalid = input_{{q}}_axis_tvalid;
|
||||
{%- endfor %}
|
||||
default: selected_input_{{p}}_axis_tvalid = 1'b0;
|
||||
endcase
|
||||
end
|
||||
{% endfor %}
|
||||
// mux for incoming packet
|
||||
{% for p in range(n) %}
|
||||
reg [DATA_WIDTH-1:0] current_input_{{p}}_axis_tdata;
|
||||
reg [KEEP_WIDTH-1:0] current_input_{{p}}_axis_tkeep;
|
||||
reg current_input_{{p}}_axis_tvalid;
|
||||
reg current_input_{{p}}_axis_tready;
|
||||
reg current_input_{{p}}_axis_tlast;
|
||||
reg [DEST_WIDTH-1:0] current_input_{{p}}_axis_tdest;
|
||||
reg current_input_{{p}}_axis_tuser;
|
||||
|
||||
always @* begin
|
||||
case (select_{{p}}_reg)
|
||||
{%- for q in range(m) %}
|
||||
{{cm}}'d{{q}}: begin
|
||||
current_input_{{p}}_axis_tdata = input_{{q}}_axis_tdata;
|
||||
current_input_{{p}}_axis_tkeep = input_{{q}}_axis_tkeep;
|
||||
current_input_{{p}}_axis_tvalid = input_{{q}}_axis_tvalid;
|
||||
current_input_{{p}}_axis_tready = input_{{q}}_axis_tready;
|
||||
current_input_{{p}}_axis_tlast = input_{{q}}_axis_tlast;
|
||||
current_input_{{p}}_axis_tdest = input_{{q}}_axis_tdest;
|
||||
current_input_{{p}}_axis_tuser = input_{{q}}_axis_tuser;
|
||||
end
|
||||
{%- endfor %}
|
||||
default: begin
|
||||
current_input_{{p}}_axis_tdata = {DATA_WIDTH{1'b0}};
|
||||
current_input_{{p}}_axis_tkeep = {KEEP_WIDTH{1'b0}};
|
||||
current_input_{{p}}_axis_tvalid = 1'b0;
|
||||
current_input_{{p}}_axis_tready = 1'b0;
|
||||
current_input_{{p}}_axis_tlast = 1'b0;
|
||||
current_input_{{p}}_axis_tdest = {DEST_WIDTH{1'b0}};
|
||||
current_input_{{p}}_axis_tuser = 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
{% endfor %}
|
||||
// arbiter instances
|
||||
{% for p in range(n) %}
|
||||
wire [{{m-1}}:0] request_{{p}};
|
||||
wire [{{m-1}}:0] acknowledge_{{p}};
|
||||
wire [{{m-1}}:0] grant_{{p}};
|
||||
wire grant_valid_{{p}};
|
||||
wire [{{cm-1}}:0] grant_encoded_{{p}};
|
||||
{% endfor %}
|
||||
|
||||
{%- for p in range(n) %}
|
||||
arbiter #(
|
||||
.PORTS({{m}}),
|
||||
.TYPE(ARB_TYPE),
|
||||
.BLOCK("ACKNOWLEDGE"),
|
||||
.LSB_PRIORITY(LSB_PRIORITY)
|
||||
)
|
||||
arb_{{p}}_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.request(request_{{p}}),
|
||||
.acknowledge(acknowledge_{{p}}),
|
||||
.grant(grant_{{p}}),
|
||||
.grant_valid(grant_valid_{{p}}),
|
||||
.grant_encoded(grant_encoded_{{p}})
|
||||
);
|
||||
{% endfor %}
|
||||
// request generation
|
||||
{%- for p in range(n) %}
|
||||
{%- for q in range(m) %}
|
||||
assign request_{{p}}[{{q}}] = input_{{q}}_request_reg[{{p}}] & ~acknowledge_{{p}}[{{q}}];
|
||||
{%- endfor %}
|
||||
{% endfor %}
|
||||
// acknowledge generation
|
||||
{%- for p in range(n) %}
|
||||
{%- for q in range(m) %}
|
||||
assign acknowledge_{{p}}[{{q}}] = grant_{{p}}[{{q}}] & input_{{q}}_axis_tvalid & input_{{q}}_axis_tready & input_{{q}}_axis_tlast;
|
||||
{%- endfor %}
|
||||
{% endfor %}
|
||||
always @* begin
|
||||
{%- for p in range(n) %}
|
||||
select_{{p}}_next = select_{{p}}_reg;
|
||||
{%- endfor %}
|
||||
{% for p in range(n) %}
|
||||
enable_{{p}}_next = enable_{{p}}_reg;
|
||||
{%- endfor %}
|
||||
{% for p in range(m) %}
|
||||
input_{{p}}_request_next = input_{{p}}_request_reg;
|
||||
input_{{p}}_request_valid_next = input_{{p}}_request_valid_reg;
|
||||
input_{{p}}_request_error_next = input_{{p}}_request_error_reg;
|
||||
{% endfor %}
|
||||
{%- for p in range(m) %}
|
||||
input_{{p}}_axis_tready_next = 1'b0;
|
||||
{%- endfor %}
|
||||
{% for p in range(n) %}
|
||||
output_{{p}}_axis_tdata_int = {DATA_WIDTH{1'b0}};
|
||||
output_{{p}}_axis_tkeep_int = {DATA_WIDTH{1'b0}};
|
||||
output_{{p}}_axis_tvalid_int = 1'b0;
|
||||
output_{{p}}_axis_tlast_int = 1'b0;
|
||||
output_{{p}}_axis_tdest_int = {DEST_WIDTH{1'b0}};
|
||||
output_{{p}}_axis_tuser_int = 1'b0;
|
||||
{% endfor %}
|
||||
// input decoding
|
||||
{% for p in range(m) %}
|
||||
if (input_{{p}}_request_valid_reg | input_{{p}}_request_error_reg) begin
|
||||
if (input_{{p}}_axis_tvalid & input_{{p}}_axis_tready & input_{{p}}_axis_tlast) begin
|
||||
input_{{p}}_request_next = {DEST_WIDTH{1'b0}};
|
||||
input_{{p}}_request_valid_next = 1'b0;
|
||||
input_{{p}}_request_error_next = 1'b0;
|
||||
end
|
||||
end else if (input_{{p}}_axis_tvalid) begin
|
||||
{%- for q in range(n) %}
|
||||
input_{{p}}_request_next[{{q}}] = (input_{{p}}_axis_tdest >= OUT_{{q}}_BASE) & (input_{{p}}_axis_tdest <= OUT_{{q}}_TOP) & OUT_{{q}}_CONNECT[{{p}}];
|
||||
{%- endfor %}
|
||||
|
||||
if (input_{{p}}_request_next) begin
|
||||
input_{{p}}_request_valid_next = 1'b1;
|
||||
end else begin
|
||||
input_{{p}}_request_error_next = 1'b1;
|
||||
end
|
||||
end
|
||||
{% endfor %}
|
||||
// output control
|
||||
{% for p in range(n) %}
|
||||
if (enable_{{p}}_reg) begin
|
||||
if (current_input_{{p}}_axis_tvalid & current_input_{{p}}_axis_tready) begin
|
||||
enable_{{p}}_next = ~current_input_{{p}}_axis_tlast;
|
||||
end
|
||||
end else if (grant_valid_{{p}} & selected_input_{{p}}_axis_tvalid) begin
|
||||
enable_{{p}}_next = 1'b1;
|
||||
select_{{p}}_next = grant_encoded_{{p}};
|
||||
end
|
||||
{% endfor %}
|
||||
// generate ready signal on selected port
|
||||
{% for p in range(n) %}
|
||||
if (enable_{{p}}_next) begin
|
||||
case (select_{{p}}_next)
|
||||
{%- for q in range(m) %}
|
||||
{{cm}}'d{{q}}: input_{{q}}_axis_tready_next = output_{{p}}_axis_tready_int_early;
|
||||
{%- endfor %}
|
||||
endcase
|
||||
end
|
||||
{% endfor %}
|
||||
|
||||
{%- for p in range(m) %}
|
||||
if (input_{{p}}_request_error_next)
|
||||
input_{{p}}_axis_tready_next = 1'b1;
|
||||
{%- endfor %}
|
||||
|
||||
// pass through selected packet data
|
||||
{% for p in range(n) %}
|
||||
output_{{p}}_axis_tdata_int = current_input_{{p}}_axis_tdata;
|
||||
output_{{p}}_axis_tkeep_int = current_input_{{p}}_axis_tkeep;
|
||||
output_{{p}}_axis_tvalid_int = current_input_{{p}}_axis_tvalid & current_input_{{p}}_axis_tready & enable_{{p}}_reg;
|
||||
output_{{p}}_axis_tlast_int = current_input_{{p}}_axis_tlast;
|
||||
output_{{p}}_axis_tdest_int = current_input_{{p}}_axis_tdest;
|
||||
output_{{p}}_axis_tuser_int = current_input_{{p}}_axis_tuser;
|
||||
{% endfor -%}
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
{%- for p in range(m) %}
|
||||
input_{{p}}_request_reg <= {{n}}'d0;
|
||||
input_{{p}}_request_valid_reg <= 1'b0;
|
||||
input_{{p}}_request_error_reg <= 1'b0;
|
||||
{%- endfor %}
|
||||
{%- for p in range(n) %}
|
||||
select_{{p}}_reg <= 2'd0;
|
||||
{%- endfor %}
|
||||
{%- for p in range(n) %}
|
||||
enable_{{p}}_reg <= 1'b0;
|
||||
{%- endfor %}
|
||||
{%- for p in range(m) %}
|
||||
input_{{p}}_axis_tready_reg <= 1'b0;
|
||||
{%- endfor %}
|
||||
end else begin
|
||||
{%- for p in range(m) %}
|
||||
input_{{p}}_request_reg <= input_{{p}}_request_next;
|
||||
input_{{p}}_request_valid_reg <= input_{{p}}_request_valid_next;
|
||||
input_{{p}}_request_error_reg <= input_{{p}}_request_error_next;
|
||||
{%- endfor %}
|
||||
{%- for p in range(n) %}
|
||||
select_{{p}}_reg <= select_{{p}}_next;
|
||||
{%- endfor %}
|
||||
{%- for p in range(n) %}
|
||||
enable_{{p}}_reg <= enable_{{p}}_next;
|
||||
{%- endfor %}
|
||||
{%- for p in range(m) %}
|
||||
input_{{p}}_axis_tready_reg <= input_{{p}}_axis_tready_next;
|
||||
{%- endfor %}
|
||||
end
|
||||
end
|
||||
{% for p in range(n) %}
|
||||
// output {{p}} datapath logic
|
||||
reg [DATA_WIDTH-1:0] output_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}};
|
||||
reg [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
|
||||
reg output_{{p}}_axis_tvalid_reg = 1'b0, output_{{p}}_axis_tvalid_next;
|
||||
reg output_{{p}}_axis_tlast_reg = 1'b0;
|
||||
reg [DEST_WIDTH-1:0] output_{{p}}_axis_tdest_reg = {DEST_WIDTH{1'b0}};
|
||||
reg output_{{p}}_axis_tuser_reg = 1'b0;
|
||||
|
||||
reg [DATA_WIDTH-1:0] temp_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}};
|
||||
reg [KEEP_WIDTH-1:0] temp_{{p}}_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
|
||||
reg temp_{{p}}_axis_tvalid_reg = 1'b0, temp_{{p}}_axis_tvalid_next;
|
||||
reg temp_{{p}}_axis_tlast_reg = 1'b0;
|
||||
reg [DEST_WIDTH-1:0] temp_{{p}}_axis_tdest_reg = {DEST_WIDTH{1'b0}};
|
||||
reg temp_{{p}}_axis_tuser_reg = 1'b0;
|
||||
|
||||
// datapath control
|
||||
reg store_{{p}}_axis_int_to_output;
|
||||
reg store_{{p}}_axis_int_to_temp;
|
||||
reg store_{{p}}_axis_temp_to_output;
|
||||
|
||||
assign output_{{p}}_axis_tdata = output_{{p}}_axis_tdata_reg;
|
||||
assign output_{{p}}_axis_tkeep = output_{{p}}_axis_tkeep_reg;
|
||||
assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg;
|
||||
assign output_{{p}}_axis_tlast = output_{{p}}_axis_tlast_reg;
|
||||
assign output_{{p}}_axis_tdest = output_{{p}}_axis_tdest_reg;
|
||||
assign output_{{p}}_axis_tuser = output_{{p}}_axis_tuser_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign output_{{p}}_axis_tready_int_early = output_{{p}}_axis_tready | (~temp_{{p}}_axis_tvalid_reg & (~output_{{p}}_axis_tvalid_reg | ~output_{{p}}_axis_tvalid_int));
|
||||
|
||||
always @* begin
|
||||
// transfer sink ready state to source
|
||||
output_{{p}}_axis_tvalid_next = output_{{p}}_axis_tvalid_reg;
|
||||
temp_{{p}}_axis_tvalid_next = temp_{{p}}_axis_tvalid_reg;
|
||||
|
||||
store_{{p}}_axis_int_to_output = 1'b0;
|
||||
store_{{p}}_axis_int_to_temp = 1'b0;
|
||||
store_{{p}}_axis_temp_to_output = 1'b0;
|
||||
|
||||
if (output_{{p}}_axis_tready_int_reg) begin
|
||||
// input is ready
|
||||
if (output_{{p}}_axis_tready | ~output_{{p}}_axis_tvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
output_{{p}}_axis_tvalid_next = output_{{p}}_axis_tvalid_int;
|
||||
store_{{p}}_axis_int_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_{{p}}_axis_tvalid_next = output_{{p}}_axis_tvalid_int;
|
||||
store_{{p}}_axis_int_to_temp = 1'b1;
|
||||
end
|
||||
end else if (output_{{p}}_axis_tready) begin
|
||||
// input is not ready, but output is ready
|
||||
output_{{p}}_axis_tvalid_next = temp_{{p}}_axis_tvalid_reg;
|
||||
temp_{{p}}_axis_tvalid_next = 1'b0;
|
||||
store_{{p}}_axis_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
output_{{p}}_axis_tvalid_reg <= 1'b0;
|
||||
output_{{p}}_axis_tready_int_reg <= 1'b0;
|
||||
temp_{{p}}_axis_tvalid_reg <= 1'b0;
|
||||
end else begin
|
||||
output_{{p}}_axis_tvalid_reg <= output_{{p}}_axis_tvalid_next;
|
||||
output_{{p}}_axis_tready_int_reg <= output_{{p}}_axis_tready_int_early;
|
||||
temp_{{p}}_axis_tvalid_reg <= temp_{{p}}_axis_tvalid_next;
|
||||
end
|
||||
|
||||
// datapath
|
||||
if (store_{{p}}_axis_int_to_output) begin
|
||||
output_{{p}}_axis_tdata_reg <= output_{{p}}_axis_tdata_int;
|
||||
output_{{p}}_axis_tkeep_reg <= output_{{p}}_axis_tkeep_int;
|
||||
output_{{p}}_axis_tlast_reg <= output_{{p}}_axis_tlast_int;
|
||||
output_{{p}}_axis_tdest_reg <= output_{{p}}_axis_tdest_int;
|
||||
output_{{p}}_axis_tuser_reg <= output_{{p}}_axis_tuser_int;
|
||||
end else if (store_{{p}}_axis_temp_to_output) begin
|
||||
output_{{p}}_axis_tdata_reg <= temp_{{p}}_axis_tdata_reg;
|
||||
output_{{p}}_axis_tkeep_reg <= temp_{{p}}_axis_tkeep_reg;
|
||||
output_{{p}}_axis_tlast_reg <= temp_{{p}}_axis_tlast_reg;
|
||||
output_{{p}}_axis_tdest_reg <= temp_{{p}}_axis_tdest_reg;
|
||||
output_{{p}}_axis_tuser_reg <= temp_{{p}}_axis_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_{{p}}_axis_int_to_temp) begin
|
||||
temp_{{p}}_axis_tdata_reg <= output_{{p}}_axis_tdata_int;
|
||||
temp_{{p}}_axis_tkeep_reg <= output_{{p}}_axis_tkeep_int;
|
||||
temp_{{p}}_axis_tlast_reg <= output_{{p}}_axis_tlast_int;
|
||||
temp_{{p}}_axis_tdest_reg <= output_{{p}}_axis_tdest_int;
|
||||
temp_{{p}}_axis_tuser_reg <= output_{{p}}_axis_tuser_int;
|
||||
end
|
||||
end
|
||||
{% endfor %}
|
||||
endmodule
|
||||
|
||||
""")
|
||||
|
||||
output_file.write(t.render(
|
||||
m=m,
|
||||
n=n,
|
||||
cm=cm,
|
||||
cn=cn,
|
||||
name=name
|
||||
))
|
||||
|
||||
print("Done")
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
||||
1331
rtl/axis_switch_64_4x4.v
Normal file
1331
rtl/axis_switch_64_4x4.v
Normal file
File diff suppressed because it is too large
Load Diff
682
tb/test_axis_switch_4x4.py
Executable file
682
tb/test_axis_switch_4x4.py
Executable file
@ -0,0 +1,682 @@
|
||||
#!/usr/bin/env python
|
||||
"""
|
||||
|
||||
Copyright (c) 2016 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
"""
|
||||
|
||||
from myhdl import *
|
||||
import os
|
||||
|
||||
try:
|
||||
from queue import Queue
|
||||
except ImportError:
|
||||
from Queue import Queue
|
||||
|
||||
import axis_ep
|
||||
|
||||
module = 'axis_switch_4x4'
|
||||
testbench = 'test_axis_switch_4x4'
|
||||
|
||||
srcs = []
|
||||
|
||||
srcs.append("../rtl/%s.v" % module)
|
||||
srcs.append("../rtl/arbiter.v")
|
||||
srcs.append("../rtl/priority_encoder.v")
|
||||
srcs.append("%s.v" % testbench)
|
||||
|
||||
src = ' '.join(srcs)
|
||||
|
||||
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
|
||||
|
||||
def dut_axis_switch_4x4(clk,
|
||||
rst,
|
||||
current_test,
|
||||
|
||||
input_0_axis_tdata,
|
||||
input_0_axis_tvalid,
|
||||
input_0_axis_tready,
|
||||
input_0_axis_tlast,
|
||||
input_0_axis_tdest,
|
||||
input_0_axis_tuser,
|
||||
input_1_axis_tdata,
|
||||
input_1_axis_tvalid,
|
||||
input_1_axis_tready,
|
||||
input_1_axis_tlast,
|
||||
input_1_axis_tdest,
|
||||
input_1_axis_tuser,
|
||||
input_2_axis_tdata,
|
||||
input_2_axis_tvalid,
|
||||
input_2_axis_tready,
|
||||
input_2_axis_tlast,
|
||||
input_2_axis_tdest,
|
||||
input_2_axis_tuser,
|
||||
input_3_axis_tdata,
|
||||
input_3_axis_tvalid,
|
||||
input_3_axis_tready,
|
||||
input_3_axis_tlast,
|
||||
input_3_axis_tdest,
|
||||
input_3_axis_tuser,
|
||||
|
||||
output_0_axis_tdata,
|
||||
output_0_axis_tvalid,
|
||||
output_0_axis_tready,
|
||||
output_0_axis_tlast,
|
||||
output_0_axis_tdest,
|
||||
output_0_axis_tuser,
|
||||
output_1_axis_tdata,
|
||||
output_1_axis_tvalid,
|
||||
output_1_axis_tready,
|
||||
output_1_axis_tlast,
|
||||
output_1_axis_tdest,
|
||||
output_1_axis_tuser,
|
||||
output_2_axis_tdata,
|
||||
output_2_axis_tvalid,
|
||||
output_2_axis_tready,
|
||||
output_2_axis_tlast,
|
||||
output_2_axis_tdest,
|
||||
output_2_axis_tuser,
|
||||
output_3_axis_tdata,
|
||||
output_3_axis_tvalid,
|
||||
output_3_axis_tready,
|
||||
output_3_axis_tlast,
|
||||
output_3_axis_tdest,
|
||||
output_3_axis_tuser):
|
||||
|
||||
if os.system(build_cmd):
|
||||
raise Exception("Error running build command")
|
||||
return Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
|
||||
clk=clk,
|
||||
rst=rst,
|
||||
current_test=current_test,
|
||||
|
||||
input_0_axis_tdata=input_0_axis_tdata,
|
||||
input_0_axis_tvalid=input_0_axis_tvalid,
|
||||
input_0_axis_tready=input_0_axis_tready,
|
||||
input_0_axis_tlast=input_0_axis_tlast,
|
||||
input_0_axis_tdest=input_0_axis_tdest,
|
||||
input_0_axis_tuser=input_0_axis_tuser,
|
||||
input_1_axis_tdata=input_1_axis_tdata,
|
||||
input_1_axis_tvalid=input_1_axis_tvalid,
|
||||
input_1_axis_tready=input_1_axis_tready,
|
||||
input_1_axis_tlast=input_1_axis_tlast,
|
||||
input_1_axis_tdest=input_1_axis_tdest,
|
||||
input_1_axis_tuser=input_1_axis_tuser,
|
||||
input_2_axis_tdata=input_2_axis_tdata,
|
||||
input_2_axis_tvalid=input_2_axis_tvalid,
|
||||
input_2_axis_tready=input_2_axis_tready,
|
||||
input_2_axis_tlast=input_2_axis_tlast,
|
||||
input_2_axis_tdest=input_2_axis_tdest,
|
||||
input_2_axis_tuser=input_2_axis_tuser,
|
||||
input_3_axis_tdata=input_3_axis_tdata,
|
||||
input_3_axis_tvalid=input_3_axis_tvalid,
|
||||
input_3_axis_tready=input_3_axis_tready,
|
||||
input_3_axis_tlast=input_3_axis_tlast,
|
||||
input_3_axis_tdest=input_3_axis_tdest,
|
||||
input_3_axis_tuser=input_3_axis_tuser,
|
||||
|
||||
output_0_axis_tdata=output_0_axis_tdata,
|
||||
output_0_axis_tvalid=output_0_axis_tvalid,
|
||||
output_0_axis_tready=output_0_axis_tready,
|
||||
output_0_axis_tlast=output_0_axis_tlast,
|
||||
output_0_axis_tdest=output_0_axis_tdest,
|
||||
output_0_axis_tuser=output_0_axis_tuser,
|
||||
output_1_axis_tdata=output_1_axis_tdata,
|
||||
output_1_axis_tvalid=output_1_axis_tvalid,
|
||||
output_1_axis_tready=output_1_axis_tready,
|
||||
output_1_axis_tlast=output_1_axis_tlast,
|
||||
output_1_axis_tdest=output_1_axis_tdest,
|
||||
output_1_axis_tuser=output_1_axis_tuser,
|
||||
output_2_axis_tdata=output_2_axis_tdata,
|
||||
output_2_axis_tvalid=output_2_axis_tvalid,
|
||||
output_2_axis_tready=output_2_axis_tready,
|
||||
output_2_axis_tlast=output_2_axis_tlast,
|
||||
output_2_axis_tdest=output_2_axis_tdest,
|
||||
output_2_axis_tuser=output_2_axis_tuser,
|
||||
output_3_axis_tdata=output_3_axis_tdata,
|
||||
output_3_axis_tvalid=output_3_axis_tvalid,
|
||||
output_3_axis_tready=output_3_axis_tready,
|
||||
output_3_axis_tlast=output_3_axis_tlast,
|
||||
output_3_axis_tdest=output_3_axis_tdest,
|
||||
output_3_axis_tuser=output_3_axis_tuser)
|
||||
|
||||
def bench():
|
||||
|
||||
# Parameters
|
||||
DATA_WIDTH = 8
|
||||
DEST_WIDTH = 3
|
||||
OUT_0_BASE = 0
|
||||
OUT_0_TOP = 0
|
||||
OUT_0_CONNECT = 0xf
|
||||
OUT_1_BASE = 1
|
||||
OUT_1_TOP = 1
|
||||
OUT_1_CONNECT = 0xf
|
||||
OUT_2_BASE = 2
|
||||
OUT_2_TOP = 2
|
||||
OUT_2_CONNECT = 0xf
|
||||
OUT_3_BASE = 3
|
||||
OUT_3_TOP = 3
|
||||
OUT_3_CONNECT = 0xf
|
||||
ARB_TYPE = "ROUND_ROBIN"
|
||||
LSB_PRIORITY = "HIGH"
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
current_test = Signal(intbv(0)[8:])
|
||||
|
||||
input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
input_0_axis_tvalid = Signal(bool(0))
|
||||
input_0_axis_tlast = Signal(bool(0))
|
||||
input_0_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
input_0_axis_tuser = Signal(bool(0))
|
||||
input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
input_1_axis_tvalid = Signal(bool(0))
|
||||
input_1_axis_tlast = Signal(bool(0))
|
||||
input_1_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
input_1_axis_tuser = Signal(bool(0))
|
||||
input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
input_2_axis_tvalid = Signal(bool(0))
|
||||
input_2_axis_tlast = Signal(bool(0))
|
||||
input_2_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
input_2_axis_tuser = Signal(bool(0))
|
||||
input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
input_3_axis_tvalid = Signal(bool(0))
|
||||
input_3_axis_tlast = Signal(bool(0))
|
||||
input_3_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
input_3_axis_tuser = Signal(bool(0))
|
||||
output_0_axis_tready = Signal(bool(0))
|
||||
output_1_axis_tready = Signal(bool(0))
|
||||
output_2_axis_tready = Signal(bool(0))
|
||||
output_3_axis_tready = Signal(bool(0))
|
||||
|
||||
# Outputs
|
||||
input_0_axis_tready = Signal(bool(0))
|
||||
input_1_axis_tready = Signal(bool(0))
|
||||
input_2_axis_tready = Signal(bool(0))
|
||||
input_3_axis_tready = Signal(bool(0))
|
||||
output_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
output_0_axis_tvalid = Signal(bool(0))
|
||||
output_0_axis_tlast = Signal(bool(0))
|
||||
output_0_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
output_0_axis_tuser = Signal(bool(0))
|
||||
output_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
output_1_axis_tvalid = Signal(bool(0))
|
||||
output_1_axis_tlast = Signal(bool(0))
|
||||
output_1_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
output_1_axis_tuser = Signal(bool(0))
|
||||
output_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
output_2_axis_tvalid = Signal(bool(0))
|
||||
output_2_axis_tlast = Signal(bool(0))
|
||||
output_2_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
output_2_axis_tuser = Signal(bool(0))
|
||||
output_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
output_3_axis_tvalid = Signal(bool(0))
|
||||
output_3_axis_tlast = Signal(bool(0))
|
||||
output_3_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
output_3_axis_tuser = Signal(bool(0))
|
||||
|
||||
# sources and sinks
|
||||
source_0_queue = Queue()
|
||||
source_0_pause = Signal(bool(0))
|
||||
source_1_queue = Queue()
|
||||
source_1_pause = Signal(bool(0))
|
||||
source_2_queue = Queue()
|
||||
source_2_pause = Signal(bool(0))
|
||||
source_3_queue = Queue()
|
||||
source_3_pause = Signal(bool(0))
|
||||
sink_0_queue = Queue()
|
||||
sink_0_pause = Signal(bool(0))
|
||||
sink_1_queue = Queue()
|
||||
sink_1_pause = Signal(bool(0))
|
||||
sink_2_queue = Queue()
|
||||
sink_2_pause = Signal(bool(0))
|
||||
sink_3_queue = Queue()
|
||||
sink_3_pause = Signal(bool(0))
|
||||
|
||||
source_0 = axis_ep.AXIStreamSource(clk,
|
||||
rst,
|
||||
tdata=input_0_axis_tdata,
|
||||
tvalid=input_0_axis_tvalid,
|
||||
tready=input_0_axis_tready,
|
||||
tlast=input_0_axis_tlast,
|
||||
tdest=input_0_axis_tdest,
|
||||
tuser=input_0_axis_tuser,
|
||||
fifo=source_0_queue,
|
||||
pause=source_0_pause,
|
||||
name='source0')
|
||||
source_1 = axis_ep.AXIStreamSource(clk,
|
||||
rst,
|
||||
tdata=input_1_axis_tdata,
|
||||
tvalid=input_1_axis_tvalid,
|
||||
tready=input_1_axis_tready,
|
||||
tlast=input_1_axis_tlast,
|
||||
tdest=input_1_axis_tdest,
|
||||
tuser=input_1_axis_tuser,
|
||||
fifo=source_1_queue,
|
||||
pause=source_1_pause,
|
||||
name='source1')
|
||||
source_2 = axis_ep.AXIStreamSource(clk,
|
||||
rst,
|
||||
tdata=input_2_axis_tdata,
|
||||
tvalid=input_2_axis_tvalid,
|
||||
tready=input_2_axis_tready,
|
||||
tlast=input_2_axis_tlast,
|
||||
tdest=input_2_axis_tdest,
|
||||
tuser=input_2_axis_tuser,
|
||||
fifo=source_2_queue,
|
||||
pause=source_2_pause,
|
||||
name='source2')
|
||||
source_3 = axis_ep.AXIStreamSource(clk,
|
||||
rst,
|
||||
tdata=input_3_axis_tdata,
|
||||
tvalid=input_3_axis_tvalid,
|
||||
tready=input_3_axis_tready,
|
||||
tlast=input_3_axis_tlast,
|
||||
tdest=input_3_axis_tdest,
|
||||
tuser=input_3_axis_tuser,
|
||||
fifo=source_3_queue,
|
||||
pause=source_3_pause,
|
||||
name='source3')
|
||||
|
||||
sink_0 = axis_ep.AXIStreamSink(clk,
|
||||
rst,
|
||||
tdata=output_0_axis_tdata,
|
||||
tvalid=output_0_axis_tvalid,
|
||||
tready=output_0_axis_tready,
|
||||
tlast=output_0_axis_tlast,
|
||||
tdest=output_0_axis_tdest,
|
||||
tuser=output_0_axis_tuser,
|
||||
fifo=sink_0_queue,
|
||||
pause=sink_0_pause,
|
||||
name='sink0')
|
||||
sink_1 = axis_ep.AXIStreamSink(clk,
|
||||
rst,
|
||||
tdata=output_1_axis_tdata,
|
||||
tvalid=output_1_axis_tvalid,
|
||||
tready=output_1_axis_tready,
|
||||
tlast=output_1_axis_tlast,
|
||||
tdest=output_1_axis_tdest,
|
||||
tuser=output_1_axis_tuser,
|
||||
fifo=sink_1_queue,
|
||||
pause=sink_1_pause,
|
||||
name='sink1')
|
||||
sink_2 = axis_ep.AXIStreamSink(clk,
|
||||
rst,
|
||||
tdata=output_2_axis_tdata,
|
||||
tvalid=output_2_axis_tvalid,
|
||||
tready=output_2_axis_tready,
|
||||
tlast=output_2_axis_tlast,
|
||||
tdest=output_2_axis_tdest,
|
||||
tuser=output_2_axis_tuser,
|
||||
fifo=sink_2_queue,
|
||||
pause=sink_2_pause,
|
||||
name='sink2')
|
||||
sink_3 = axis_ep.AXIStreamSink(clk,
|
||||
rst,
|
||||
tdata=output_3_axis_tdata,
|
||||
tvalid=output_3_axis_tvalid,
|
||||
tready=output_3_axis_tready,
|
||||
tlast=output_3_axis_tlast,
|
||||
tdest=output_3_axis_tdest,
|
||||
tuser=output_3_axis_tuser,
|
||||
fifo=sink_3_queue,
|
||||
pause=sink_3_pause,
|
||||
name='sink3')
|
||||
|
||||
# DUT
|
||||
dut = dut_axis_switch_4x4(clk,
|
||||
rst,
|
||||
current_test,
|
||||
input_0_axis_tdata,
|
||||
input_0_axis_tvalid,
|
||||
input_0_axis_tready,
|
||||
input_0_axis_tlast,
|
||||
input_0_axis_tdest,
|
||||
input_0_axis_tuser,
|
||||
input_1_axis_tdata,
|
||||
input_1_axis_tvalid,
|
||||
input_1_axis_tready,
|
||||
input_1_axis_tlast,
|
||||
input_1_axis_tdest,
|
||||
input_1_axis_tuser,
|
||||
input_2_axis_tdata,
|
||||
input_2_axis_tvalid,
|
||||
input_2_axis_tready,
|
||||
input_2_axis_tlast,
|
||||
input_2_axis_tdest,
|
||||
input_2_axis_tuser,
|
||||
input_3_axis_tdata,
|
||||
input_3_axis_tvalid,
|
||||
input_3_axis_tready,
|
||||
input_3_axis_tlast,
|
||||
input_3_axis_tdest,
|
||||
input_3_axis_tuser,
|
||||
output_0_axis_tdata,
|
||||
output_0_axis_tvalid,
|
||||
output_0_axis_tready,
|
||||
output_0_axis_tlast,
|
||||
output_0_axis_tdest,
|
||||
output_0_axis_tuser,
|
||||
output_1_axis_tdata,
|
||||
output_1_axis_tvalid,
|
||||
output_1_axis_tready,
|
||||
output_1_axis_tlast,
|
||||
output_1_axis_tdest,
|
||||
output_1_axis_tuser,
|
||||
output_2_axis_tdata,
|
||||
output_2_axis_tvalid,
|
||||
output_2_axis_tready,
|
||||
output_2_axis_tlast,
|
||||
output_2_axis_tdest,
|
||||
output_2_axis_tuser,
|
||||
output_3_axis_tdata,
|
||||
output_3_axis_tvalid,
|
||||
output_3_axis_tready,
|
||||
output_3_axis_tlast,
|
||||
output_3_axis_tdest,
|
||||
output_3_axis_tuser)
|
||||
|
||||
@always(delay(4))
|
||||
def clkgen():
|
||||
clk.next = not clk
|
||||
|
||||
def wait_normal():
|
||||
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
|
||||
yield clk.posedge
|
||||
|
||||
def wait_pause_source():
|
||||
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
|
||||
source_0_pause.next = True
|
||||
source_1_pause.next = True
|
||||
source_2_pause.next = True
|
||||
source_3_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
source_0_pause.next = False
|
||||
source_1_pause.next = False
|
||||
source_2_pause.next = False
|
||||
source_3_pause.next = False
|
||||
yield clk.posedge
|
||||
|
||||
def wait_pause_sink():
|
||||
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
|
||||
sink_0_pause.next = True
|
||||
sink_1_pause.next = True
|
||||
sink_2_pause.next = True
|
||||
sink_3_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
sink_0_pause.next = False
|
||||
sink_1_pause.next = False
|
||||
sink_2_pause.next = False
|
||||
sink_3_pause.next = False
|
||||
yield clk.posedge
|
||||
|
||||
@instance
|
||||
def check():
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
rst.next = 1
|
||||
yield clk.posedge
|
||||
rst.next = 0
|
||||
yield clk.posedge
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
|
||||
# testbench stimulus
|
||||
|
||||
yield clk.posedge
|
||||
print("test 1: 0123 -> 0123")
|
||||
current_test.next = 1
|
||||
|
||||
test_frame0 = axis_ep.AXIStreamFrame(b'\x01\x00\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\x01\x01\x01\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=1)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\x01\x02\x02\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=2)
|
||||
test_frame3 = axis_ep.AXIStreamFrame(b'\x01\x03\x03\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=3)
|
||||
|
||||
for wait in wait_normal, wait_pause_source, wait_pause_sink:
|
||||
source_0_queue.put(test_frame0)
|
||||
source_1_queue.put(test_frame1)
|
||||
source_2_queue.put(test_frame2)
|
||||
source_3_queue.put(test_frame3)
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
yield wait()
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame0 = None
|
||||
if not sink_0_queue.empty():
|
||||
rx_frame0 = sink_0_queue.get()
|
||||
|
||||
assert rx_frame0 == test_frame0
|
||||
|
||||
rx_frame1 = None
|
||||
if not sink_1_queue.empty():
|
||||
rx_frame1 = sink_1_queue.get()
|
||||
|
||||
assert rx_frame1 == test_frame1
|
||||
|
||||
rx_frame2 = None
|
||||
if not sink_2_queue.empty():
|
||||
rx_frame2 = sink_2_queue.get()
|
||||
|
||||
assert rx_frame2 == test_frame2
|
||||
|
||||
rx_frame3 = None
|
||||
if not sink_3_queue.empty():
|
||||
rx_frame3 = sink_3_queue.get()
|
||||
|
||||
assert rx_frame3 == test_frame3
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 2: 0123 -> 3210")
|
||||
current_test.next = 2
|
||||
|
||||
test_frame0 = axis_ep.AXIStreamFrame(b'\x02\x00\x03\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=3)
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x01\x02\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=2)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x02\x01\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=1)
|
||||
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x03\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
|
||||
|
||||
for wait in wait_normal, wait_pause_source, wait_pause_sink:
|
||||
source_0_queue.put(test_frame0)
|
||||
source_1_queue.put(test_frame1)
|
||||
source_2_queue.put(test_frame2)
|
||||
source_3_queue.put(test_frame3)
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
yield wait()
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame0 = None
|
||||
if not sink_0_queue.empty():
|
||||
rx_frame0 = sink_0_queue.get()
|
||||
|
||||
assert rx_frame0 == test_frame3
|
||||
|
||||
rx_frame1 = None
|
||||
if not sink_1_queue.empty():
|
||||
rx_frame1 = sink_1_queue.get()
|
||||
|
||||
assert rx_frame1 == test_frame2
|
||||
|
||||
rx_frame2 = None
|
||||
if not sink_2_queue.empty():
|
||||
rx_frame2 = sink_2_queue.get()
|
||||
|
||||
assert rx_frame2 == test_frame1
|
||||
|
||||
rx_frame3 = None
|
||||
if not sink_3_queue.empty():
|
||||
rx_frame3 = sink_3_queue.get()
|
||||
|
||||
assert rx_frame3 == test_frame0
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 3: 0000 -> 0123")
|
||||
current_test.next = 3
|
||||
|
||||
test_frame0 = axis_ep.AXIStreamFrame(b'\x02\x00\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x00\x01\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=1)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x00\x02\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=2)
|
||||
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x00\x03\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=3)
|
||||
|
||||
for wait in wait_normal, wait_pause_source, wait_pause_sink:
|
||||
source_0_queue.put(test_frame0)
|
||||
source_0_queue.put(test_frame1)
|
||||
source_0_queue.put(test_frame2)
|
||||
source_0_queue.put(test_frame3)
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
yield wait()
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame0 = None
|
||||
if not sink_0_queue.empty():
|
||||
rx_frame0 = sink_0_queue.get()
|
||||
|
||||
assert rx_frame0 == test_frame0
|
||||
|
||||
rx_frame1 = None
|
||||
if not sink_1_queue.empty():
|
||||
rx_frame1 = sink_1_queue.get()
|
||||
|
||||
assert rx_frame1 == test_frame1
|
||||
|
||||
rx_frame2 = None
|
||||
if not sink_2_queue.empty():
|
||||
rx_frame2 = sink_2_queue.get()
|
||||
|
||||
assert rx_frame2 == test_frame2
|
||||
|
||||
rx_frame3 = None
|
||||
if not sink_3_queue.empty():
|
||||
rx_frame3 = sink_3_queue.get()
|
||||
|
||||
assert rx_frame3 == test_frame3
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 4: 0123 -> 0000")
|
||||
current_test.next = 4
|
||||
|
||||
test_frame0 = axis_ep.AXIStreamFrame(b'\x02\x00\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x01\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x02\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
|
||||
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x03\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
|
||||
|
||||
for wait in wait_normal, wait_pause_source, wait_pause_sink:
|
||||
source_0_queue.put(test_frame0)
|
||||
yield clk.posedge
|
||||
source_1_queue.put(test_frame1)
|
||||
source_2_queue.put(test_frame2)
|
||||
source_3_queue.put(test_frame3)
|
||||
yield clk.posedge
|
||||
|
||||
yield wait()
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame0 = None
|
||||
if not sink_0_queue.empty():
|
||||
rx_frame0 = sink_0_queue.get()
|
||||
|
||||
assert rx_frame0 == test_frame0
|
||||
|
||||
rx_frame1 = None
|
||||
if not sink_0_queue.empty():
|
||||
rx_frame1 = sink_0_queue.get()
|
||||
|
||||
assert rx_frame1 == test_frame1
|
||||
|
||||
rx_frame2 = None
|
||||
if not sink_0_queue.empty():
|
||||
rx_frame2 = sink_0_queue.get()
|
||||
|
||||
assert rx_frame2 == test_frame2
|
||||
|
||||
rx_frame3 = None
|
||||
if not sink_0_queue.empty():
|
||||
rx_frame3 = sink_0_queue.get()
|
||||
|
||||
assert rx_frame3 == test_frame3
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 1: bad decoding")
|
||||
current_test.next = 1
|
||||
|
||||
test_frame0 = axis_ep.AXIStreamFrame(b'\x01\x00\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\x01\x01\x01\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=1)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\x01\x02\x04\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=4)
|
||||
test_frame3 = axis_ep.AXIStreamFrame(b'\x01\x03\x05\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=5)
|
||||
|
||||
for wait in wait_normal, wait_pause_source, wait_pause_sink:
|
||||
source_0_queue.put(test_frame0)
|
||||
source_1_queue.put(test_frame1)
|
||||
source_2_queue.put(test_frame2)
|
||||
source_3_queue.put(test_frame3)
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
yield wait()
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame0 = None
|
||||
if not sink_0_queue.empty():
|
||||
rx_frame0 = sink_0_queue.get()
|
||||
|
||||
assert rx_frame0 == test_frame0
|
||||
|
||||
rx_frame1 = None
|
||||
if not sink_1_queue.empty():
|
||||
rx_frame1 = sink_1_queue.get()
|
||||
|
||||
assert rx_frame1 == test_frame1
|
||||
|
||||
yield delay(100)
|
||||
|
||||
raise StopSimulation
|
||||
|
||||
return dut, source_0, source_1, source_2, source_3, sink_0, sink_1, sink_2, sink_3, clkgen, check
|
||||
|
||||
def test_bench():
|
||||
sim = Simulation(bench())
|
||||
sim.run()
|
||||
|
||||
if __name__ == '__main__':
|
||||
print("Running test...")
|
||||
test_bench()
|
||||
240
tb/test_axis_switch_4x4.v
Normal file
240
tb/test_axis_switch_4x4.v
Normal file
@ -0,0 +1,240 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2016 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Testbench for axis_switch_4x4
|
||||
*/
|
||||
module test_axis_switch_4x4;
|
||||
|
||||
// Parameters
|
||||
parameter DATA_WIDTH = 8;
|
||||
parameter DEST_WIDTH = 3;
|
||||
parameter OUT_0_BASE = 0;
|
||||
parameter OUT_0_TOP = 0;
|
||||
parameter OUT_0_CONNECT = 4'b1111;
|
||||
parameter OUT_1_BASE = 1;
|
||||
parameter OUT_1_TOP = 1;
|
||||
parameter OUT_1_CONNECT = 4'b1111;
|
||||
parameter OUT_2_BASE = 2;
|
||||
parameter OUT_2_TOP = 2;
|
||||
parameter OUT_2_CONNECT = 4'b1111;
|
||||
parameter OUT_3_BASE = 3;
|
||||
parameter OUT_3_TOP = 3;
|
||||
parameter OUT_3_CONNECT = 4'b1111;
|
||||
parameter ARB_TYPE = "ROUND_ROBIN";
|
||||
parameter LSB_PRIORITY = "HIGH";
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg [DATA_WIDTH-1:0] input_0_axis_tdata = 0;
|
||||
reg input_0_axis_tvalid = 0;
|
||||
reg input_0_axis_tlast = 0;
|
||||
reg [DEST_WIDTH-1:0] input_0_axis_tdest = 0;
|
||||
reg input_0_axis_tuser = 0;
|
||||
reg [DATA_WIDTH-1:0] input_1_axis_tdata = 0;
|
||||
reg input_1_axis_tvalid = 0;
|
||||
reg input_1_axis_tlast = 0;
|
||||
reg [DEST_WIDTH-1:0] input_1_axis_tdest = 0;
|
||||
reg input_1_axis_tuser = 0;
|
||||
reg [DATA_WIDTH-1:0] input_2_axis_tdata = 0;
|
||||
reg input_2_axis_tvalid = 0;
|
||||
reg input_2_axis_tlast = 0;
|
||||
reg [DEST_WIDTH-1:0] input_2_axis_tdest = 0;
|
||||
reg input_2_axis_tuser = 0;
|
||||
reg [DATA_WIDTH-1:0] input_3_axis_tdata = 0;
|
||||
reg input_3_axis_tvalid = 0;
|
||||
reg input_3_axis_tlast = 0;
|
||||
reg [DEST_WIDTH-1:0] input_3_axis_tdest = 0;
|
||||
reg input_3_axis_tuser = 0;
|
||||
reg output_0_axis_tready = 0;
|
||||
reg output_1_axis_tready = 0;
|
||||
reg output_2_axis_tready = 0;
|
||||
reg output_3_axis_tready = 0;
|
||||
|
||||
// Outputs
|
||||
wire input_0_axis_tready;
|
||||
wire input_1_axis_tready;
|
||||
wire input_2_axis_tready;
|
||||
wire input_3_axis_tready;
|
||||
wire [DATA_WIDTH-1:0] output_0_axis_tdata;
|
||||
wire output_0_axis_tvalid;
|
||||
wire output_0_axis_tlast;
|
||||
wire [DEST_WIDTH-1:0] output_0_axis_tdest;
|
||||
wire output_0_axis_tuser;
|
||||
wire [DATA_WIDTH-1:0] output_1_axis_tdata;
|
||||
wire output_1_axis_tvalid;
|
||||
wire output_1_axis_tlast;
|
||||
wire [DEST_WIDTH-1:0] output_1_axis_tdest;
|
||||
wire output_1_axis_tuser;
|
||||
wire [DATA_WIDTH-1:0] output_2_axis_tdata;
|
||||
wire output_2_axis_tvalid;
|
||||
wire output_2_axis_tlast;
|
||||
wire [DEST_WIDTH-1:0] output_2_axis_tdest;
|
||||
wire output_2_axis_tuser;
|
||||
wire [DATA_WIDTH-1:0] output_3_axis_tdata;
|
||||
wire output_3_axis_tvalid;
|
||||
wire output_3_axis_tlast;
|
||||
wire [DEST_WIDTH-1:0] output_3_axis_tdest;
|
||||
wire output_3_axis_tuser;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
$from_myhdl(clk,
|
||||
rst,
|
||||
current_test,
|
||||
input_0_axis_tdata,
|
||||
input_0_axis_tvalid,
|
||||
input_0_axis_tlast,
|
||||
input_0_axis_tdest,
|
||||
input_0_axis_tuser,
|
||||
input_1_axis_tdata,
|
||||
input_1_axis_tvalid,
|
||||
input_1_axis_tlast,
|
||||
input_1_axis_tdest,
|
||||
input_1_axis_tuser,
|
||||
input_2_axis_tdata,
|
||||
input_2_axis_tvalid,
|
||||
input_2_axis_tlast,
|
||||
input_2_axis_tdest,
|
||||
input_2_axis_tuser,
|
||||
input_3_axis_tdata,
|
||||
input_3_axis_tvalid,
|
||||
input_3_axis_tlast,
|
||||
input_3_axis_tdest,
|
||||
input_3_axis_tuser,
|
||||
output_0_axis_tready,
|
||||
output_1_axis_tready,
|
||||
output_2_axis_tready,
|
||||
output_3_axis_tready);
|
||||
$to_myhdl(input_0_axis_tready,
|
||||
input_1_axis_tready,
|
||||
input_2_axis_tready,
|
||||
input_3_axis_tready,
|
||||
output_0_axis_tdata,
|
||||
output_0_axis_tvalid,
|
||||
output_0_axis_tlast,
|
||||
output_0_axis_tdest,
|
||||
output_0_axis_tuser,
|
||||
output_1_axis_tdata,
|
||||
output_1_axis_tvalid,
|
||||
output_1_axis_tlast,
|
||||
output_1_axis_tdest,
|
||||
output_1_axis_tuser,
|
||||
output_2_axis_tdata,
|
||||
output_2_axis_tvalid,
|
||||
output_2_axis_tlast,
|
||||
output_2_axis_tdest,
|
||||
output_2_axis_tuser,
|
||||
output_3_axis_tdata,
|
||||
output_3_axis_tvalid,
|
||||
output_3_axis_tlast,
|
||||
output_3_axis_tdest,
|
||||
output_3_axis_tuser);
|
||||
|
||||
// dump file
|
||||
$dumpfile("test_axis_switch_4x4.lxt");
|
||||
$dumpvars(0, test_axis_switch_4x4);
|
||||
end
|
||||
|
||||
axis_switch_4x4 #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.DEST_WIDTH(DEST_WIDTH),
|
||||
.OUT_0_BASE(OUT_0_BASE),
|
||||
.OUT_0_TOP(OUT_0_TOP),
|
||||
.OUT_0_CONNECT(OUT_0_CONNECT),
|
||||
.OUT_1_BASE(OUT_1_BASE),
|
||||
.OUT_1_TOP(OUT_1_TOP),
|
||||
.OUT_1_CONNECT(OUT_1_CONNECT),
|
||||
.OUT_2_BASE(OUT_2_BASE),
|
||||
.OUT_2_TOP(OUT_2_TOP),
|
||||
.OUT_2_CONNECT(OUT_2_CONNECT),
|
||||
.OUT_3_BASE(OUT_3_BASE),
|
||||
.OUT_3_TOP(OUT_3_TOP),
|
||||
.OUT_3_CONNECT(OUT_3_CONNECT),
|
||||
.ARB_TYPE(ARB_TYPE),
|
||||
.LSB_PRIORITY(LSB_PRIORITY)
|
||||
)
|
||||
UUT (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// AXI inputs
|
||||
.input_0_axis_tdata(input_0_axis_tdata),
|
||||
.input_0_axis_tvalid(input_0_axis_tvalid),
|
||||
.input_0_axis_tready(input_0_axis_tready),
|
||||
.input_0_axis_tlast(input_0_axis_tlast),
|
||||
.input_0_axis_tdest(input_0_axis_tdest),
|
||||
.input_0_axis_tuser(input_0_axis_tuser),
|
||||
.input_1_axis_tdata(input_1_axis_tdata),
|
||||
.input_1_axis_tvalid(input_1_axis_tvalid),
|
||||
.input_1_axis_tready(input_1_axis_tready),
|
||||
.input_1_axis_tlast(input_1_axis_tlast),
|
||||
.input_1_axis_tdest(input_1_axis_tdest),
|
||||
.input_1_axis_tuser(input_1_axis_tuser),
|
||||
.input_2_axis_tdata(input_2_axis_tdata),
|
||||
.input_2_axis_tvalid(input_2_axis_tvalid),
|
||||
.input_2_axis_tready(input_2_axis_tready),
|
||||
.input_2_axis_tlast(input_2_axis_tlast),
|
||||
.input_2_axis_tdest(input_2_axis_tdest),
|
||||
.input_2_axis_tuser(input_2_axis_tuser),
|
||||
.input_3_axis_tdata(input_3_axis_tdata),
|
||||
.input_3_axis_tvalid(input_3_axis_tvalid),
|
||||
.input_3_axis_tready(input_3_axis_tready),
|
||||
.input_3_axis_tlast(input_3_axis_tlast),
|
||||
.input_3_axis_tdest(input_3_axis_tdest),
|
||||
.input_3_axis_tuser(input_3_axis_tuser),
|
||||
// AXI outputs
|
||||
.output_0_axis_tdata(output_0_axis_tdata),
|
||||
.output_0_axis_tvalid(output_0_axis_tvalid),
|
||||
.output_0_axis_tready(output_0_axis_tready),
|
||||
.output_0_axis_tlast(output_0_axis_tlast),
|
||||
.output_0_axis_tdest(output_0_axis_tdest),
|
||||
.output_0_axis_tuser(output_0_axis_tuser),
|
||||
.output_1_axis_tdata(output_1_axis_tdata),
|
||||
.output_1_axis_tvalid(output_1_axis_tvalid),
|
||||
.output_1_axis_tready(output_1_axis_tready),
|
||||
.output_1_axis_tlast(output_1_axis_tlast),
|
||||
.output_1_axis_tdest(output_1_axis_tdest),
|
||||
.output_1_axis_tuser(output_1_axis_tuser),
|
||||
.output_2_axis_tdata(output_2_axis_tdata),
|
||||
.output_2_axis_tvalid(output_2_axis_tvalid),
|
||||
.output_2_axis_tready(output_2_axis_tready),
|
||||
.output_2_axis_tlast(output_2_axis_tlast),
|
||||
.output_2_axis_tdest(output_2_axis_tdest),
|
||||
.output_2_axis_tuser(output_2_axis_tuser),
|
||||
.output_3_axis_tdata(output_3_axis_tdata),
|
||||
.output_3_axis_tvalid(output_3_axis_tvalid),
|
||||
.output_3_axis_tready(output_3_axis_tready),
|
||||
.output_3_axis_tlast(output_3_axis_tlast),
|
||||
.output_3_axis_tdest(output_3_axis_tdest),
|
||||
.output_3_axis_tuser(output_3_axis_tuser)
|
||||
);
|
||||
|
||||
endmodule
|
||||
723
tb/test_axis_switch_64_4x4.py
Executable file
723
tb/test_axis_switch_64_4x4.py
Executable file
@ -0,0 +1,723 @@
|
||||
#!/usr/bin/env python
|
||||
"""
|
||||
|
||||
Copyright (c) 2016 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
"""
|
||||
|
||||
from myhdl import *
|
||||
import os
|
||||
|
||||
try:
|
||||
from queue import Queue
|
||||
except ImportError:
|
||||
from Queue import Queue
|
||||
|
||||
import axis_ep
|
||||
|
||||
module = 'axis_switch_64_4x4'
|
||||
testbench = 'test_axis_switch_64_4x4'
|
||||
|
||||
srcs = []
|
||||
|
||||
srcs.append("../rtl/%s.v" % module)
|
||||
srcs.append("../rtl/arbiter.v")
|
||||
srcs.append("../rtl/priority_encoder.v")
|
||||
srcs.append("%s.v" % testbench)
|
||||
|
||||
src = ' '.join(srcs)
|
||||
|
||||
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
|
||||
|
||||
def dut_axis_switch_64_4x4(clk,
|
||||
rst,
|
||||
current_test,
|
||||
|
||||
input_0_axis_tdata,
|
||||
input_0_axis_tkeep,
|
||||
input_0_axis_tvalid,
|
||||
input_0_axis_tready,
|
||||
input_0_axis_tlast,
|
||||
input_0_axis_tdest,
|
||||
input_0_axis_tuser,
|
||||
input_1_axis_tdata,
|
||||
input_1_axis_tkeep,
|
||||
input_1_axis_tvalid,
|
||||
input_1_axis_tready,
|
||||
input_1_axis_tlast,
|
||||
input_1_axis_tdest,
|
||||
input_1_axis_tuser,
|
||||
input_2_axis_tdata,
|
||||
input_2_axis_tkeep,
|
||||
input_2_axis_tvalid,
|
||||
input_2_axis_tready,
|
||||
input_2_axis_tlast,
|
||||
input_2_axis_tdest,
|
||||
input_2_axis_tuser,
|
||||
input_3_axis_tdata,
|
||||
input_3_axis_tkeep,
|
||||
input_3_axis_tvalid,
|
||||
input_3_axis_tready,
|
||||
input_3_axis_tlast,
|
||||
input_3_axis_tdest,
|
||||
input_3_axis_tuser,
|
||||
|
||||
output_0_axis_tdata,
|
||||
output_0_axis_tkeep,
|
||||
output_0_axis_tvalid,
|
||||
output_0_axis_tready,
|
||||
output_0_axis_tlast,
|
||||
output_0_axis_tdest,
|
||||
output_0_axis_tuser,
|
||||
output_1_axis_tdata,
|
||||
output_1_axis_tkeep,
|
||||
output_1_axis_tvalid,
|
||||
output_1_axis_tready,
|
||||
output_1_axis_tlast,
|
||||
output_1_axis_tdest,
|
||||
output_1_axis_tuser,
|
||||
output_2_axis_tdata,
|
||||
output_2_axis_tkeep,
|
||||
output_2_axis_tvalid,
|
||||
output_2_axis_tready,
|
||||
output_2_axis_tlast,
|
||||
output_2_axis_tdest,
|
||||
output_2_axis_tuser,
|
||||
output_3_axis_tdata,
|
||||
output_3_axis_tkeep,
|
||||
output_3_axis_tvalid,
|
||||
output_3_axis_tready,
|
||||
output_3_axis_tlast,
|
||||
output_3_axis_tdest,
|
||||
output_3_axis_tuser):
|
||||
|
||||
if os.system(build_cmd):
|
||||
raise Exception("Error running build command")
|
||||
return Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
|
||||
clk=clk,
|
||||
rst=rst,
|
||||
current_test=current_test,
|
||||
|
||||
input_0_axis_tdata=input_0_axis_tdata,
|
||||
input_0_axis_tkeep=input_0_axis_tkeep,
|
||||
input_0_axis_tvalid=input_0_axis_tvalid,
|
||||
input_0_axis_tready=input_0_axis_tready,
|
||||
input_0_axis_tlast=input_0_axis_tlast,
|
||||
input_0_axis_tdest=input_0_axis_tdest,
|
||||
input_0_axis_tuser=input_0_axis_tuser,
|
||||
input_1_axis_tdata=input_1_axis_tdata,
|
||||
input_1_axis_tkeep=input_1_axis_tkeep,
|
||||
input_1_axis_tvalid=input_1_axis_tvalid,
|
||||
input_1_axis_tready=input_1_axis_tready,
|
||||
input_1_axis_tlast=input_1_axis_tlast,
|
||||
input_1_axis_tdest=input_1_axis_tdest,
|
||||
input_1_axis_tuser=input_1_axis_tuser,
|
||||
input_2_axis_tdata=input_2_axis_tdata,
|
||||
input_2_axis_tkeep=input_2_axis_tkeep,
|
||||
input_2_axis_tvalid=input_2_axis_tvalid,
|
||||
input_2_axis_tready=input_2_axis_tready,
|
||||
input_2_axis_tlast=input_2_axis_tlast,
|
||||
input_2_axis_tdest=input_2_axis_tdest,
|
||||
input_2_axis_tuser=input_2_axis_tuser,
|
||||
input_3_axis_tdata=input_3_axis_tdata,
|
||||
input_3_axis_tkeep=input_3_axis_tkeep,
|
||||
input_3_axis_tvalid=input_3_axis_tvalid,
|
||||
input_3_axis_tready=input_3_axis_tready,
|
||||
input_3_axis_tlast=input_3_axis_tlast,
|
||||
input_3_axis_tdest=input_3_axis_tdest,
|
||||
input_3_axis_tuser=input_3_axis_tuser,
|
||||
|
||||
output_0_axis_tdata=output_0_axis_tdata,
|
||||
output_0_axis_tkeep=output_0_axis_tkeep,
|
||||
output_0_axis_tvalid=output_0_axis_tvalid,
|
||||
output_0_axis_tready=output_0_axis_tready,
|
||||
output_0_axis_tlast=output_0_axis_tlast,
|
||||
output_0_axis_tdest=output_0_axis_tdest,
|
||||
output_0_axis_tuser=output_0_axis_tuser,
|
||||
output_1_axis_tdata=output_1_axis_tdata,
|
||||
output_1_axis_tkeep=output_1_axis_tkeep,
|
||||
output_1_axis_tvalid=output_1_axis_tvalid,
|
||||
output_1_axis_tready=output_1_axis_tready,
|
||||
output_1_axis_tlast=output_1_axis_tlast,
|
||||
output_1_axis_tdest=output_1_axis_tdest,
|
||||
output_1_axis_tuser=output_1_axis_tuser,
|
||||
output_2_axis_tdata=output_2_axis_tdata,
|
||||
output_2_axis_tkeep=output_2_axis_tkeep,
|
||||
output_2_axis_tvalid=output_2_axis_tvalid,
|
||||
output_2_axis_tready=output_2_axis_tready,
|
||||
output_2_axis_tlast=output_2_axis_tlast,
|
||||
output_2_axis_tdest=output_2_axis_tdest,
|
||||
output_2_axis_tuser=output_2_axis_tuser,
|
||||
output_3_axis_tdata=output_3_axis_tdata,
|
||||
output_3_axis_tkeep=output_3_axis_tkeep,
|
||||
output_3_axis_tvalid=output_3_axis_tvalid,
|
||||
output_3_axis_tready=output_3_axis_tready,
|
||||
output_3_axis_tlast=output_3_axis_tlast,
|
||||
output_3_axis_tdest=output_3_axis_tdest,
|
||||
output_3_axis_tuser=output_3_axis_tuser)
|
||||
|
||||
def bench():
|
||||
|
||||
# Parameters
|
||||
DATA_WIDTH = 64
|
||||
KEEP_WIDTH = int(DATA_WIDTH/8)
|
||||
DEST_WIDTH = 3
|
||||
OUT_0_BASE = 0
|
||||
OUT_0_TOP = 0
|
||||
OUT_0_CONNECT = 0xf
|
||||
OUT_1_BASE = 1
|
||||
OUT_1_TOP = 1
|
||||
OUT_1_CONNECT = 0xf
|
||||
OUT_2_BASE = 2
|
||||
OUT_2_TOP = 2
|
||||
OUT_2_CONNECT = 0xf
|
||||
OUT_3_BASE = 3
|
||||
OUT_3_TOP = 3
|
||||
OUT_3_CONNECT = 0xf
|
||||
ARB_TYPE = "ROUND_ROBIN"
|
||||
LSB_PRIORITY = "HIGH"
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
current_test = Signal(intbv(0)[8:])
|
||||
|
||||
input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
input_0_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
input_0_axis_tvalid = Signal(bool(0))
|
||||
input_0_axis_tlast = Signal(bool(0))
|
||||
input_0_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
input_0_axis_tuser = Signal(bool(0))
|
||||
input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
input_1_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
input_1_axis_tvalid = Signal(bool(0))
|
||||
input_1_axis_tlast = Signal(bool(0))
|
||||
input_1_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
input_1_axis_tuser = Signal(bool(0))
|
||||
input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
input_2_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
input_2_axis_tvalid = Signal(bool(0))
|
||||
input_2_axis_tlast = Signal(bool(0))
|
||||
input_2_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
input_2_axis_tuser = Signal(bool(0))
|
||||
input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
input_3_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
input_3_axis_tvalid = Signal(bool(0))
|
||||
input_3_axis_tlast = Signal(bool(0))
|
||||
input_3_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
input_3_axis_tuser = Signal(bool(0))
|
||||
output_0_axis_tready = Signal(bool(0))
|
||||
output_1_axis_tready = Signal(bool(0))
|
||||
output_2_axis_tready = Signal(bool(0))
|
||||
output_3_axis_tready = Signal(bool(0))
|
||||
|
||||
# Outputs
|
||||
input_0_axis_tready = Signal(bool(0))
|
||||
input_1_axis_tready = Signal(bool(0))
|
||||
input_2_axis_tready = Signal(bool(0))
|
||||
input_3_axis_tready = Signal(bool(0))
|
||||
output_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
output_0_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
output_0_axis_tvalid = Signal(bool(0))
|
||||
output_0_axis_tlast = Signal(bool(0))
|
||||
output_0_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
output_0_axis_tuser = Signal(bool(0))
|
||||
output_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
output_1_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
output_1_axis_tvalid = Signal(bool(0))
|
||||
output_1_axis_tlast = Signal(bool(0))
|
||||
output_1_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
output_1_axis_tuser = Signal(bool(0))
|
||||
output_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
output_2_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
output_2_axis_tvalid = Signal(bool(0))
|
||||
output_2_axis_tlast = Signal(bool(0))
|
||||
output_2_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
output_2_axis_tuser = Signal(bool(0))
|
||||
output_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
output_3_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
output_3_axis_tvalid = Signal(bool(0))
|
||||
output_3_axis_tlast = Signal(bool(0))
|
||||
output_3_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
|
||||
output_3_axis_tuser = Signal(bool(0))
|
||||
|
||||
# sources and sinks
|
||||
source_0_queue = Queue()
|
||||
source_0_pause = Signal(bool(0))
|
||||
source_1_queue = Queue()
|
||||
source_1_pause = Signal(bool(0))
|
||||
source_2_queue = Queue()
|
||||
source_2_pause = Signal(bool(0))
|
||||
source_3_queue = Queue()
|
||||
source_3_pause = Signal(bool(0))
|
||||
sink_0_queue = Queue()
|
||||
sink_0_pause = Signal(bool(0))
|
||||
sink_1_queue = Queue()
|
||||
sink_1_pause = Signal(bool(0))
|
||||
sink_2_queue = Queue()
|
||||
sink_2_pause = Signal(bool(0))
|
||||
sink_3_queue = Queue()
|
||||
sink_3_pause = Signal(bool(0))
|
||||
|
||||
source_0 = axis_ep.AXIStreamSource(clk,
|
||||
rst,
|
||||
tdata=input_0_axis_tdata,
|
||||
tkeep=input_0_axis_tkeep,
|
||||
tvalid=input_0_axis_tvalid,
|
||||
tready=input_0_axis_tready,
|
||||
tlast=input_0_axis_tlast,
|
||||
tdest=input_0_axis_tdest,
|
||||
tuser=input_0_axis_tuser,
|
||||
fifo=source_0_queue,
|
||||
pause=source_0_pause,
|
||||
name='source0')
|
||||
source_1 = axis_ep.AXIStreamSource(clk,
|
||||
rst,
|
||||
tdata=input_1_axis_tdata,
|
||||
tkeep=input_1_axis_tkeep,
|
||||
tvalid=input_1_axis_tvalid,
|
||||
tready=input_1_axis_tready,
|
||||
tlast=input_1_axis_tlast,
|
||||
tdest=input_1_axis_tdest,
|
||||
tuser=input_1_axis_tuser,
|
||||
fifo=source_1_queue,
|
||||
pause=source_1_pause,
|
||||
name='source1')
|
||||
source_2 = axis_ep.AXIStreamSource(clk,
|
||||
rst,
|
||||
tdata=input_2_axis_tdata,
|
||||
tkeep=input_2_axis_tkeep,
|
||||
tvalid=input_2_axis_tvalid,
|
||||
tready=input_2_axis_tready,
|
||||
tlast=input_2_axis_tlast,
|
||||
tdest=input_2_axis_tdest,
|
||||
tuser=input_2_axis_tuser,
|
||||
fifo=source_2_queue,
|
||||
pause=source_2_pause,
|
||||
name='source2')
|
||||
source_3 = axis_ep.AXIStreamSource(clk,
|
||||
rst,
|
||||
tdata=input_3_axis_tdata,
|
||||
tkeep=input_3_axis_tkeep,
|
||||
tvalid=input_3_axis_tvalid,
|
||||
tready=input_3_axis_tready,
|
||||
tlast=input_3_axis_tlast,
|
||||
tdest=input_3_axis_tdest,
|
||||
tuser=input_3_axis_tuser,
|
||||
fifo=source_3_queue,
|
||||
pause=source_3_pause,
|
||||
name='source3')
|
||||
|
||||
sink_0 = axis_ep.AXIStreamSink(clk,
|
||||
rst,
|
||||
tdata=output_0_axis_tdata,
|
||||
tkeep=output_0_axis_tkeep,
|
||||
tvalid=output_0_axis_tvalid,
|
||||
tready=output_0_axis_tready,
|
||||
tlast=output_0_axis_tlast,
|
||||
tdest=output_0_axis_tdest,
|
||||
tuser=output_0_axis_tuser,
|
||||
fifo=sink_0_queue,
|
||||
pause=sink_0_pause,
|
||||
name='sink0')
|
||||
sink_1 = axis_ep.AXIStreamSink(clk,
|
||||
rst,
|
||||
tdata=output_1_axis_tdata,
|
||||
tkeep=output_1_axis_tkeep,
|
||||
tvalid=output_1_axis_tvalid,
|
||||
tready=output_1_axis_tready,
|
||||
tlast=output_1_axis_tlast,
|
||||
tdest=output_1_axis_tdest,
|
||||
tuser=output_1_axis_tuser,
|
||||
fifo=sink_1_queue,
|
||||
pause=sink_1_pause,
|
||||
name='sink1')
|
||||
sink_2 = axis_ep.AXIStreamSink(clk,
|
||||
rst,
|
||||
tdata=output_2_axis_tdata,
|
||||
tkeep=output_2_axis_tkeep,
|
||||
tvalid=output_2_axis_tvalid,
|
||||
tready=output_2_axis_tready,
|
||||
tlast=output_2_axis_tlast,
|
||||
tdest=output_2_axis_tdest,
|
||||
tuser=output_2_axis_tuser,
|
||||
fifo=sink_2_queue,
|
||||
pause=sink_2_pause,
|
||||
name='sink2')
|
||||
sink_3 = axis_ep.AXIStreamSink(clk,
|
||||
rst,
|
||||
tdata=output_3_axis_tdata,
|
||||
tkeep=output_3_axis_tkeep,
|
||||
tvalid=output_3_axis_tvalid,
|
||||
tready=output_3_axis_tready,
|
||||
tlast=output_3_axis_tlast,
|
||||
tdest=output_3_axis_tdest,
|
||||
tuser=output_3_axis_tuser,
|
||||
fifo=sink_3_queue,
|
||||
pause=sink_3_pause,
|
||||
name='sink3')
|
||||
|
||||
# DUT
|
||||
dut = dut_axis_switch_64_4x4(clk,
|
||||
rst,
|
||||
current_test,
|
||||
input_0_axis_tdata,
|
||||
input_0_axis_tkeep,
|
||||
input_0_axis_tvalid,
|
||||
input_0_axis_tready,
|
||||
input_0_axis_tlast,
|
||||
input_0_axis_tdest,
|
||||
input_0_axis_tuser,
|
||||
input_1_axis_tdata,
|
||||
input_1_axis_tkeep,
|
||||
input_1_axis_tvalid,
|
||||
input_1_axis_tready,
|
||||
input_1_axis_tlast,
|
||||
input_1_axis_tdest,
|
||||
input_1_axis_tuser,
|
||||
input_2_axis_tdata,
|
||||
input_2_axis_tkeep,
|
||||
input_2_axis_tvalid,
|
||||
input_2_axis_tready,
|
||||
input_2_axis_tlast,
|
||||
input_2_axis_tdest,
|
||||
input_2_axis_tuser,
|
||||
input_3_axis_tdata,
|
||||
input_3_axis_tkeep,
|
||||
input_3_axis_tvalid,
|
||||
input_3_axis_tready,
|
||||
input_3_axis_tlast,
|
||||
input_3_axis_tdest,
|
||||
input_3_axis_tuser,
|
||||
output_0_axis_tdata,
|
||||
output_0_axis_tkeep,
|
||||
output_0_axis_tvalid,
|
||||
output_0_axis_tready,
|
||||
output_0_axis_tlast,
|
||||
output_0_axis_tdest,
|
||||
output_0_axis_tuser,
|
||||
output_1_axis_tdata,
|
||||
output_1_axis_tkeep,
|
||||
output_1_axis_tvalid,
|
||||
output_1_axis_tready,
|
||||
output_1_axis_tlast,
|
||||
output_1_axis_tdest,
|
||||
output_1_axis_tuser,
|
||||
output_2_axis_tdata,
|
||||
output_2_axis_tkeep,
|
||||
output_2_axis_tvalid,
|
||||
output_2_axis_tready,
|
||||
output_2_axis_tlast,
|
||||
output_2_axis_tdest,
|
||||
output_2_axis_tuser,
|
||||
output_3_axis_tdata,
|
||||
output_3_axis_tkeep,
|
||||
output_3_axis_tvalid,
|
||||
output_3_axis_tready,
|
||||
output_3_axis_tlast,
|
||||
output_3_axis_tdest,
|
||||
output_3_axis_tuser)
|
||||
|
||||
@always(delay(4))
|
||||
def clkgen():
|
||||
clk.next = not clk
|
||||
|
||||
def wait_normal():
|
||||
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
|
||||
yield clk.posedge
|
||||
|
||||
def wait_pause_source():
|
||||
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
|
||||
source_0_pause.next = True
|
||||
source_1_pause.next = True
|
||||
source_2_pause.next = True
|
||||
source_3_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
source_0_pause.next = False
|
||||
source_1_pause.next = False
|
||||
source_2_pause.next = False
|
||||
source_3_pause.next = False
|
||||
yield clk.posedge
|
||||
|
||||
def wait_pause_sink():
|
||||
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
|
||||
sink_0_pause.next = True
|
||||
sink_1_pause.next = True
|
||||
sink_2_pause.next = True
|
||||
sink_3_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
sink_0_pause.next = False
|
||||
sink_1_pause.next = False
|
||||
sink_2_pause.next = False
|
||||
sink_3_pause.next = False
|
||||
yield clk.posedge
|
||||
|
||||
@instance
|
||||
def check():
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
rst.next = 1
|
||||
yield clk.posedge
|
||||
rst.next = 0
|
||||
yield clk.posedge
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
|
||||
# testbench stimulus
|
||||
|
||||
yield clk.posedge
|
||||
print("test 1: 0123 -> 0123")
|
||||
current_test.next = 1
|
||||
|
||||
test_frame0 = axis_ep.AXIStreamFrame(b'\x01\x00\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\x01\x01\x01\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=1)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\x01\x02\x02\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=2)
|
||||
test_frame3 = axis_ep.AXIStreamFrame(b'\x01\x03\x03\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=3)
|
||||
|
||||
for wait in wait_normal, wait_pause_source, wait_pause_sink:
|
||||
source_0_queue.put(test_frame0)
|
||||
source_1_queue.put(test_frame1)
|
||||
source_2_queue.put(test_frame2)
|
||||
source_3_queue.put(test_frame3)
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
yield wait()
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame0 = None
|
||||
if not sink_0_queue.empty():
|
||||
rx_frame0 = sink_0_queue.get()
|
||||
|
||||
assert rx_frame0 == test_frame0
|
||||
|
||||
rx_frame1 = None
|
||||
if not sink_1_queue.empty():
|
||||
rx_frame1 = sink_1_queue.get()
|
||||
|
||||
assert rx_frame1 == test_frame1
|
||||
|
||||
rx_frame2 = None
|
||||
if not sink_2_queue.empty():
|
||||
rx_frame2 = sink_2_queue.get()
|
||||
|
||||
assert rx_frame2 == test_frame2
|
||||
|
||||
rx_frame3 = None
|
||||
if not sink_3_queue.empty():
|
||||
rx_frame3 = sink_3_queue.get()
|
||||
|
||||
assert rx_frame3 == test_frame3
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 2: 0123 -> 3210")
|
||||
current_test.next = 2
|
||||
|
||||
test_frame0 = axis_ep.AXIStreamFrame(b'\x02\x00\x03\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=3)
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x01\x02\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=2)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x02\x01\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=1)
|
||||
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x03\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
|
||||
|
||||
for wait in wait_normal, wait_pause_source, wait_pause_sink:
|
||||
source_0_queue.put(test_frame0)
|
||||
source_1_queue.put(test_frame1)
|
||||
source_2_queue.put(test_frame2)
|
||||
source_3_queue.put(test_frame3)
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
yield wait()
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame0 = None
|
||||
if not sink_0_queue.empty():
|
||||
rx_frame0 = sink_0_queue.get()
|
||||
|
||||
assert rx_frame0 == test_frame3
|
||||
|
||||
rx_frame1 = None
|
||||
if not sink_1_queue.empty():
|
||||
rx_frame1 = sink_1_queue.get()
|
||||
|
||||
assert rx_frame1 == test_frame2
|
||||
|
||||
rx_frame2 = None
|
||||
if not sink_2_queue.empty():
|
||||
rx_frame2 = sink_2_queue.get()
|
||||
|
||||
assert rx_frame2 == test_frame1
|
||||
|
||||
rx_frame3 = None
|
||||
if not sink_3_queue.empty():
|
||||
rx_frame3 = sink_3_queue.get()
|
||||
|
||||
assert rx_frame3 == test_frame0
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 3: 0000 -> 0123")
|
||||
current_test.next = 3
|
||||
|
||||
test_frame0 = axis_ep.AXIStreamFrame(b'\x02\x00\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x00\x01\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=1)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x00\x02\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=2)
|
||||
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x00\x03\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=3)
|
||||
|
||||
for wait in wait_normal, wait_pause_source, wait_pause_sink:
|
||||
source_0_queue.put(test_frame0)
|
||||
source_0_queue.put(test_frame1)
|
||||
source_0_queue.put(test_frame2)
|
||||
source_0_queue.put(test_frame3)
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
yield wait()
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame0 = None
|
||||
if not sink_0_queue.empty():
|
||||
rx_frame0 = sink_0_queue.get()
|
||||
|
||||
assert rx_frame0 == test_frame0
|
||||
|
||||
rx_frame1 = None
|
||||
if not sink_1_queue.empty():
|
||||
rx_frame1 = sink_1_queue.get()
|
||||
|
||||
assert rx_frame1 == test_frame1
|
||||
|
||||
rx_frame2 = None
|
||||
if not sink_2_queue.empty():
|
||||
rx_frame2 = sink_2_queue.get()
|
||||
|
||||
assert rx_frame2 == test_frame2
|
||||
|
||||
rx_frame3 = None
|
||||
if not sink_3_queue.empty():
|
||||
rx_frame3 = sink_3_queue.get()
|
||||
|
||||
assert rx_frame3 == test_frame3
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 4: 0123 -> 0000")
|
||||
current_test.next = 4
|
||||
|
||||
test_frame0 = axis_ep.AXIStreamFrame(b'\x02\x00\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x01\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x02\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
|
||||
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x03\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
|
||||
|
||||
for wait in wait_normal, wait_pause_source, wait_pause_sink:
|
||||
source_0_queue.put(test_frame0)
|
||||
yield clk.posedge
|
||||
source_1_queue.put(test_frame1)
|
||||
source_2_queue.put(test_frame2)
|
||||
source_3_queue.put(test_frame3)
|
||||
yield clk.posedge
|
||||
|
||||
yield wait()
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame0 = None
|
||||
if not sink_0_queue.empty():
|
||||
rx_frame0 = sink_0_queue.get()
|
||||
|
||||
assert rx_frame0 == test_frame0
|
||||
|
||||
rx_frame1 = None
|
||||
if not sink_0_queue.empty():
|
||||
rx_frame1 = sink_0_queue.get()
|
||||
|
||||
assert rx_frame1 == test_frame1
|
||||
|
||||
rx_frame2 = None
|
||||
if not sink_0_queue.empty():
|
||||
rx_frame2 = sink_0_queue.get()
|
||||
|
||||
assert rx_frame2 == test_frame2
|
||||
|
||||
rx_frame3 = None
|
||||
if not sink_0_queue.empty():
|
||||
rx_frame3 = sink_0_queue.get()
|
||||
|
||||
assert rx_frame3 == test_frame3
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 1: bad decoding")
|
||||
current_test.next = 1
|
||||
|
||||
test_frame0 = axis_ep.AXIStreamFrame(b'\x01\x00\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\x01\x01\x01\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=1)
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\x01\x02\x04\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=4)
|
||||
test_frame3 = axis_ep.AXIStreamFrame(b'\x01\x03\x05\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=5)
|
||||
|
||||
for wait in wait_normal, wait_pause_source, wait_pause_sink:
|
||||
source_0_queue.put(test_frame0)
|
||||
source_1_queue.put(test_frame1)
|
||||
source_2_queue.put(test_frame2)
|
||||
source_3_queue.put(test_frame3)
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
yield wait()
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame0 = None
|
||||
if not sink_0_queue.empty():
|
||||
rx_frame0 = sink_0_queue.get()
|
||||
|
||||
assert rx_frame0 == test_frame0
|
||||
|
||||
rx_frame1 = None
|
||||
if not sink_1_queue.empty():
|
||||
rx_frame1 = sink_1_queue.get()
|
||||
|
||||
assert rx_frame1 == test_frame1
|
||||
|
||||
yield delay(100)
|
||||
|
||||
raise StopSimulation
|
||||
|
||||
return dut, source_0, source_1, source_2, source_3, sink_0, sink_1, sink_2, sink_3, clkgen, check
|
||||
|
||||
def test_bench():
|
||||
sim = Simulation(bench())
|
||||
sim.run()
|
||||
|
||||
if __name__ == '__main__':
|
||||
print("Running test...")
|
||||
test_bench()
|
||||
266
tb/test_axis_switch_64_4x4.v
Normal file
266
tb/test_axis_switch_64_4x4.v
Normal file
@ -0,0 +1,266 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2016 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Testbench for axis_switch_64_4x4
|
||||
*/
|
||||
module test_axis_switch_64_4x4;
|
||||
|
||||
// Parameters
|
||||
parameter DATA_WIDTH = 64;
|
||||
parameter KEEP_WIDTH = (DATA_WIDTH/8);
|
||||
parameter DEST_WIDTH = 3;
|
||||
parameter OUT_0_BASE = 0;
|
||||
parameter OUT_0_TOP = 0;
|
||||
parameter OUT_0_CONNECT = 4'b1111;
|
||||
parameter OUT_1_BASE = 1;
|
||||
parameter OUT_1_TOP = 1;
|
||||
parameter OUT_1_CONNECT = 4'b1111;
|
||||
parameter OUT_2_BASE = 2;
|
||||
parameter OUT_2_TOP = 2;
|
||||
parameter OUT_2_CONNECT = 4'b1111;
|
||||
parameter OUT_3_BASE = 3;
|
||||
parameter OUT_3_TOP = 3;
|
||||
parameter OUT_3_CONNECT = 4'b1111;
|
||||
parameter ARB_TYPE = "ROUND_ROBIN";
|
||||
parameter LSB_PRIORITY = "HIGH";
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg [DATA_WIDTH-1:0] input_0_axis_tdata = 0;
|
||||
reg [KEEP_WIDTH-1:0] input_0_axis_tkeep = 0;
|
||||
reg input_0_axis_tvalid = 0;
|
||||
reg input_0_axis_tlast = 0;
|
||||
reg [DEST_WIDTH-1:0] input_0_axis_tdest = 0;
|
||||
reg input_0_axis_tuser = 0;
|
||||
reg [DATA_WIDTH-1:0] input_1_axis_tdata = 0;
|
||||
reg [KEEP_WIDTH-1:0] input_1_axis_tkeep = 0;
|
||||
reg input_1_axis_tvalid = 0;
|
||||
reg input_1_axis_tlast = 0;
|
||||
reg [DEST_WIDTH-1:0] input_1_axis_tdest = 0;
|
||||
reg input_1_axis_tuser = 0;
|
||||
reg [DATA_WIDTH-1:0] input_2_axis_tdata = 0;
|
||||
reg [KEEP_WIDTH-1:0] input_2_axis_tkeep = 0;
|
||||
reg input_2_axis_tvalid = 0;
|
||||
reg input_2_axis_tlast = 0;
|
||||
reg [DEST_WIDTH-1:0] input_2_axis_tdest = 0;
|
||||
reg input_2_axis_tuser = 0;
|
||||
reg [DATA_WIDTH-1:0] input_3_axis_tdata = 0;
|
||||
reg [KEEP_WIDTH-1:0] input_3_axis_tkeep = 0;
|
||||
reg input_3_axis_tvalid = 0;
|
||||
reg input_3_axis_tlast = 0;
|
||||
reg [DEST_WIDTH-1:0] input_3_axis_tdest = 0;
|
||||
reg input_3_axis_tuser = 0;
|
||||
reg output_0_axis_tready = 0;
|
||||
reg output_1_axis_tready = 0;
|
||||
reg output_2_axis_tready = 0;
|
||||
reg output_3_axis_tready = 0;
|
||||
|
||||
// Outputs
|
||||
wire input_0_axis_tready;
|
||||
wire input_1_axis_tready;
|
||||
wire input_2_axis_tready;
|
||||
wire input_3_axis_tready;
|
||||
wire [DATA_WIDTH-1:0] output_0_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] output_0_axis_tkeep;
|
||||
wire output_0_axis_tvalid;
|
||||
wire output_0_axis_tlast;
|
||||
wire [DEST_WIDTH-1:0] output_0_axis_tdest;
|
||||
wire output_0_axis_tuser;
|
||||
wire [DATA_WIDTH-1:0] output_1_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] output_1_axis_tkeep;
|
||||
wire output_1_axis_tvalid;
|
||||
wire output_1_axis_tlast;
|
||||
wire [DEST_WIDTH-1:0] output_1_axis_tdest;
|
||||
wire output_1_axis_tuser;
|
||||
wire [DATA_WIDTH-1:0] output_2_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] output_2_axis_tkeep;
|
||||
wire output_2_axis_tvalid;
|
||||
wire output_2_axis_tlast;
|
||||
wire [DEST_WIDTH-1:0] output_2_axis_tdest;
|
||||
wire output_2_axis_tuser;
|
||||
wire [DATA_WIDTH-1:0] output_3_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] output_3_axis_tkeep;
|
||||
wire output_3_axis_tvalid;
|
||||
wire output_3_axis_tlast;
|
||||
wire [DEST_WIDTH-1:0] output_3_axis_tdest;
|
||||
wire output_3_axis_tuser;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
$from_myhdl(clk,
|
||||
rst,
|
||||
current_test,
|
||||
input_0_axis_tdata,
|
||||
input_0_axis_tkeep,
|
||||
input_0_axis_tvalid,
|
||||
input_0_axis_tlast,
|
||||
input_0_axis_tdest,
|
||||
input_0_axis_tuser,
|
||||
input_1_axis_tdata,
|
||||
input_1_axis_tkeep,
|
||||
input_1_axis_tvalid,
|
||||
input_1_axis_tlast,
|
||||
input_1_axis_tdest,
|
||||
input_1_axis_tuser,
|
||||
input_2_axis_tdata,
|
||||
input_2_axis_tkeep,
|
||||
input_2_axis_tvalid,
|
||||
input_2_axis_tlast,
|
||||
input_2_axis_tdest,
|
||||
input_2_axis_tuser,
|
||||
input_3_axis_tdata,
|
||||
input_3_axis_tkeep,
|
||||
input_3_axis_tvalid,
|
||||
input_3_axis_tlast,
|
||||
input_3_axis_tdest,
|
||||
input_3_axis_tuser,
|
||||
output_0_axis_tready,
|
||||
output_1_axis_tready,
|
||||
output_2_axis_tready,
|
||||
output_3_axis_tready);
|
||||
$to_myhdl(input_0_axis_tready,
|
||||
input_1_axis_tready,
|
||||
input_2_axis_tready,
|
||||
input_3_axis_tready,
|
||||
output_0_axis_tdata,
|
||||
output_0_axis_tkeep,
|
||||
output_0_axis_tvalid,
|
||||
output_0_axis_tlast,
|
||||
output_0_axis_tdest,
|
||||
output_0_axis_tuser,
|
||||
output_1_axis_tdata,
|
||||
output_1_axis_tkeep,
|
||||
output_1_axis_tvalid,
|
||||
output_1_axis_tlast,
|
||||
output_1_axis_tdest,
|
||||
output_1_axis_tuser,
|
||||
output_2_axis_tdata,
|
||||
output_2_axis_tkeep,
|
||||
output_2_axis_tvalid,
|
||||
output_2_axis_tlast,
|
||||
output_2_axis_tdest,
|
||||
output_2_axis_tuser,
|
||||
output_3_axis_tdata,
|
||||
output_3_axis_tkeep,
|
||||
output_3_axis_tvalid,
|
||||
output_3_axis_tlast,
|
||||
output_3_axis_tdest,
|
||||
output_3_axis_tuser);
|
||||
|
||||
// dump file
|
||||
$dumpfile("test_axis_switch_64_4x4.lxt");
|
||||
$dumpvars(0, test_axis_switch_64_4x4);
|
||||
end
|
||||
|
||||
axis_switch_64_4x4 #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.KEEP_WIDTH(KEEP_WIDTH),
|
||||
.DEST_WIDTH(DEST_WIDTH),
|
||||
.OUT_0_BASE(OUT_0_BASE),
|
||||
.OUT_0_TOP(OUT_0_TOP),
|
||||
.OUT_0_CONNECT(OUT_0_CONNECT),
|
||||
.OUT_1_BASE(OUT_1_BASE),
|
||||
.OUT_1_TOP(OUT_1_TOP),
|
||||
.OUT_1_CONNECT(OUT_1_CONNECT),
|
||||
.OUT_2_BASE(OUT_2_BASE),
|
||||
.OUT_2_TOP(OUT_2_TOP),
|
||||
.OUT_2_CONNECT(OUT_2_CONNECT),
|
||||
.OUT_3_BASE(OUT_3_BASE),
|
||||
.OUT_3_TOP(OUT_3_TOP),
|
||||
.OUT_3_CONNECT(OUT_3_CONNECT),
|
||||
.ARB_TYPE(ARB_TYPE),
|
||||
.LSB_PRIORITY(LSB_PRIORITY)
|
||||
)
|
||||
UUT (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// AXI inputs
|
||||
.input_0_axis_tdata(input_0_axis_tdata),
|
||||
.input_0_axis_tkeep(input_0_axis_tkeep),
|
||||
.input_0_axis_tvalid(input_0_axis_tvalid),
|
||||
.input_0_axis_tready(input_0_axis_tready),
|
||||
.input_0_axis_tlast(input_0_axis_tlast),
|
||||
.input_0_axis_tdest(input_0_axis_tdest),
|
||||
.input_0_axis_tuser(input_0_axis_tuser),
|
||||
.input_1_axis_tdata(input_1_axis_tdata),
|
||||
.input_1_axis_tkeep(input_1_axis_tkeep),
|
||||
.input_1_axis_tvalid(input_1_axis_tvalid),
|
||||
.input_1_axis_tready(input_1_axis_tready),
|
||||
.input_1_axis_tlast(input_1_axis_tlast),
|
||||
.input_1_axis_tdest(input_1_axis_tdest),
|
||||
.input_1_axis_tuser(input_1_axis_tuser),
|
||||
.input_2_axis_tdata(input_2_axis_tdata),
|
||||
.input_2_axis_tkeep(input_2_axis_tkeep),
|
||||
.input_2_axis_tvalid(input_2_axis_tvalid),
|
||||
.input_2_axis_tready(input_2_axis_tready),
|
||||
.input_2_axis_tlast(input_2_axis_tlast),
|
||||
.input_2_axis_tdest(input_2_axis_tdest),
|
||||
.input_2_axis_tuser(input_2_axis_tuser),
|
||||
.input_3_axis_tdata(input_3_axis_tdata),
|
||||
.input_3_axis_tkeep(input_3_axis_tkeep),
|
||||
.input_3_axis_tvalid(input_3_axis_tvalid),
|
||||
.input_3_axis_tready(input_3_axis_tready),
|
||||
.input_3_axis_tlast(input_3_axis_tlast),
|
||||
.input_3_axis_tdest(input_3_axis_tdest),
|
||||
.input_3_axis_tuser(input_3_axis_tuser),
|
||||
// AXI outputs
|
||||
.output_0_axis_tdata(output_0_axis_tdata),
|
||||
.output_0_axis_tkeep(output_0_axis_tkeep),
|
||||
.output_0_axis_tvalid(output_0_axis_tvalid),
|
||||
.output_0_axis_tready(output_0_axis_tready),
|
||||
.output_0_axis_tlast(output_0_axis_tlast),
|
||||
.output_0_axis_tdest(output_0_axis_tdest),
|
||||
.output_0_axis_tuser(output_0_axis_tuser),
|
||||
.output_1_axis_tdata(output_1_axis_tdata),
|
||||
.output_1_axis_tkeep(output_1_axis_tkeep),
|
||||
.output_1_axis_tvalid(output_1_axis_tvalid),
|
||||
.output_1_axis_tready(output_1_axis_tready),
|
||||
.output_1_axis_tlast(output_1_axis_tlast),
|
||||
.output_1_axis_tdest(output_1_axis_tdest),
|
||||
.output_1_axis_tuser(output_1_axis_tuser),
|
||||
.output_2_axis_tdata(output_2_axis_tdata),
|
||||
.output_2_axis_tkeep(output_2_axis_tkeep),
|
||||
.output_2_axis_tvalid(output_2_axis_tvalid),
|
||||
.output_2_axis_tready(output_2_axis_tready),
|
||||
.output_2_axis_tlast(output_2_axis_tlast),
|
||||
.output_2_axis_tdest(output_2_axis_tdest),
|
||||
.output_2_axis_tuser(output_2_axis_tuser),
|
||||
.output_3_axis_tdata(output_3_axis_tdata),
|
||||
.output_3_axis_tkeep(output_3_axis_tkeep),
|
||||
.output_3_axis_tvalid(output_3_axis_tvalid),
|
||||
.output_3_axis_tready(output_3_axis_tready),
|
||||
.output_3_axis_tlast(output_3_axis_tlast),
|
||||
.output_3_axis_tdest(output_3_axis_tdest),
|
||||
.output_3_axis_tuser(output_3_axis_tuser)
|
||||
);
|
||||
|
||||
endmodule
|
||||
Loading…
x
Reference in New Issue
Block a user