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Fix clock connections

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This commit is contained in:
Alex Forencich 2021-11-30 16:39:27 -08:00
parent 8674bd1e69
commit 089c405c4f
1 changed files with 6 additions and 6 deletions
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12
fpga/common/rtl/mqnic_core.v
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@ -2350,11 +2350,11 @@ generate
wire port_tx_clk = tx_clk[n*PORTS_PER_IF+m];
wire port_tx_rst = tx_rst[n*PORTS_PER_IF+m];
wire port_rx_clk = tx_clk[n*PORTS_PER_IF+m];
wire port_rx_rst = tx_rst[n*PORTS_PER_IF+m];
wire port_rx_clk = rx_clk[n*PORTS_PER_IF+m];
wire port_rx_rst = rx_rst[n*PORTS_PER_IF+m];
wire port_rx_ptp_clk = PTP_SEPARATE_RX_CLOCK ? rx_ptp_clk[n*PORTS_PER_IF+m] : rx_clk[n*PORTS_PER_IF+m];
wire port_rx_ptp_rst = PTP_SEPARATE_RX_CLOCK ? rx_ptp_rst[n*PORTS_PER_IF+m] : rx_rst[n*PORTS_PER_IF+m];
wire port_rx_ptp_clk = rx_ptp_clk[n*PORTS_PER_IF+m];
wire port_rx_ptp_rst = rx_ptp_rst[n*PORTS_PER_IF+m];
assign app_direct_tx_clk[n*PORTS_PER_IF+m] = port_tx_clk;
assign app_direct_tx_rst[n*PORTS_PER_IF+m] = port_tx_rst;
@ -2394,8 +2394,8 @@ generate
rx_ptp_cdc_inst (
.input_clk(clk),
.input_rst(rst),
.output_clk(port_rx_ptp_clk),
.output_rst(port_rx_ptp_rst),
.output_clk(PTP_SEPARATE_RX_CLOCK ? port_rx_ptp_clk : port_rx_clk),
.output_rst(PTP_SEPARATE_RX_CLOCK ? port_rx_ptp_rst : port_rx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.input_ts_step(ptp_ts_step),