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fpga/mqnic: Add missing DRP frequency parameters

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-12-04 22:07:58 -08:00
parent 3a7343ec6d
commit 08f49d7e17
3 changed files with 3 additions and 0 deletions
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1
fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v
View File

@ -963,6 +963,7 @@ qsfp1_sync_reset_inst (
); );
cmac_gty_wrapper #( cmac_gty_wrapper #(
.DRP_CLK_FREQ_HZ(125000000),
.AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), .AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.TX_SERDES_PIPELINE(0), .TX_SERDES_PIPELINE(0),

1
fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
View File

@ -1357,6 +1357,7 @@ qsfp1_sync_reset_inst (
); );
cmac_gty_wrapper #( cmac_gty_wrapper #(
.DRP_CLK_FREQ_HZ(125000000),
.AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), .AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.TX_SERDES_PIPELINE(0), .TX_SERDES_PIPELINE(0),

1
fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
View File

@ -1236,6 +1236,7 @@ qsfp1_sync_reset_inst (
); );
cmac_gty_wrapper #( cmac_gty_wrapper #(
.DRP_CLK_FREQ_HZ(125000000),
.AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), .AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.TX_SERDES_PIPELINE(0), .TX_SERDES_PIPELINE(0),