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Add SCHED_PER_IF parameter to split scheduler count from port count

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This commit is contained in:
Alex Forencich 2022-03-28 15:20:33 -07:00
parent dfae34ed25
commit 09128df360
142 changed files with 336 additions and 92 deletions
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3
fpga/app/template/tb/mqnic_core_pcie_us/Makefile
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@ -129,6 +129,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# Structural configuration
export PARAM_IF_COUNT ?= 1
export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLOCK_PIPELINE ?= 0
@ -239,6 +240,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
@ -327,6 +329,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)

1
fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
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@ -682,6 +682,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
# Structural configuration
parameters['IF_COUNT'] = if_count
parameters['PORTS_PER_IF'] = ports_per_if
parameters['SCHED_PER_IF'] = ports_per_if
# PTP configuration
parameters['PTP_CLOCK_PIPELINE'] = 0

2
fpga/common/rtl/mqnic_core.v
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@ -55,6 +55,7 @@ module mqnic_core #
// Structural configuration
parameter IF_COUNT = 1,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF,
@ -2161,6 +2162,7 @@ generate
mqnic_interface #(
.PORTS(PORTS_PER_IF),
.SCHEDULERS(SCHED_PER_IF),
.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(IF_DMA_TAG_WIDTH),

2
fpga/common/rtl/mqnic_core_axi.v
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@ -55,6 +55,7 @@ module mqnic_core_axi #
// Structural configuration
parameter IF_COUNT = 1,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF,
@ -572,6 +573,7 @@ mqnic_core #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),

2
fpga/common/rtl/mqnic_core_pcie.v
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@ -55,6 +55,7 @@ module mqnic_core_pcie #
// Structural configuration
parameter IF_COUNT = 1,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF,
@ -1326,6 +1327,7 @@ mqnic_core #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),

2
fpga/common/rtl/mqnic_core_pcie_s10.v
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@ -55,6 +55,7 @@ module mqnic_core_pcie_s10 #
// Structural configuration
parameter IF_COUNT = 1,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF,
@ -596,6 +597,7 @@ mqnic_core_pcie #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),

2
fpga/common/rtl/mqnic_core_pcie_us.v
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@ -55,6 +55,7 @@ module mqnic_core_pcie_us #
// Structural configuration
parameter IF_COUNT = 1,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF,
@ -686,6 +687,7 @@ mqnic_core_pcie #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),

178
fpga/common/rtl/mqnic_interface.v
View File

@ -44,6 +44,8 @@ module mqnic_interface #
(
// Number of ports
parameter PORTS = 1,
// Number of schedulers
parameter SCHEDULERS = 1,
// DMA address width
parameter DMA_ADDR_WIDTH = 64,
// DMA length field width
@ -379,8 +381,8 @@ parameter EVENT_TYPE_WIDTH = 16;
parameter MAX_DESC_TABLE_SIZE = TX_DESC_TABLE_SIZE > RX_DESC_TABLE_SIZE ? TX_DESC_TABLE_SIZE : RX_DESC_TABLE_SIZE;
parameter REQ_TAG_WIDTH = $clog2(MAX_DESC_TABLE_SIZE) + $clog2(PORTS);
parameter REQ_TAG_WIDTH_INT = REQ_TAG_WIDTH - $clog2(PORTS);
parameter REQ_TAG_WIDTH = $clog2(MAX_DESC_TABLE_SIZE) + $clog2(SCHEDULERS);
parameter REQ_TAG_WIDTH_INT = REQ_TAG_WIDTH - $clog2(SCHEDULERS);
parameter DESC_REQ_TAG_WIDTH = $clog2(MAX_DESC_TABLE_SIZE) + 1 + $clog2(PORTS+1);
@ -395,14 +397,14 @@ parameter CPL_QUEUE_INDEX_WIDTH = TX_CPL_QUEUE_INDEX_WIDTH > RX_CPL_QUEUE_INDEX_
parameter DESC_REQ_TAG_WIDTH_INT = DESC_REQ_TAG_WIDTH - $clog2(3);
parameter AXIL_CSR_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((PORTS+3)/8);
parameter AXIL_CTRL_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((PORTS+3)/8);
parameter AXIL_EQM_ADDR_WIDTH = AXIL_ADDR_WIDTH-4-$clog2((PORTS+3)/8);
parameter AXIL_TX_QM_ADDR_WIDTH = AXIL_ADDR_WIDTH-3-$clog2((PORTS+3)/8);
parameter AXIL_TX_CQM_ADDR_WIDTH = AXIL_ADDR_WIDTH-3-$clog2((PORTS+3)/8);
parameter AXIL_RX_QM_ADDR_WIDTH = AXIL_ADDR_WIDTH-4-$clog2((PORTS+3)/8);
parameter AXIL_RX_CQM_ADDR_WIDTH = AXIL_ADDR_WIDTH-4-$clog2((PORTS+3)/8);
parameter AXIL_PORT_ADDR_WIDTH = AXIL_ADDR_WIDTH-3-$clog2((PORTS+3)/8);
parameter AXIL_CSR_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((SCHEDULERS+3)/8);
parameter AXIL_CTRL_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((SCHEDULERS+3)/8);
parameter AXIL_EQM_ADDR_WIDTH = AXIL_ADDR_WIDTH-4-$clog2((SCHEDULERS+3)/8);
parameter AXIL_TX_QM_ADDR_WIDTH = AXIL_ADDR_WIDTH-3-$clog2((SCHEDULERS+3)/8);
parameter AXIL_TX_CQM_ADDR_WIDTH = AXIL_ADDR_WIDTH-3-$clog2((SCHEDULERS+3)/8);
parameter AXIL_RX_QM_ADDR_WIDTH = AXIL_ADDR_WIDTH-4-$clog2((SCHEDULERS+3)/8);
parameter AXIL_RX_CQM_ADDR_WIDTH = AXIL_ADDR_WIDTH-4-$clog2((SCHEDULERS+3)/8);
parameter AXIL_SCHED_ADDR_WIDTH = AXIL_ADDR_WIDTH-3-$clog2((SCHEDULERS+3)/8);
parameter AXIL_CSR_BASE_ADDR = 0;
parameter AXIL_CTRL_BASE_ADDR = AXIL_CSR_BASE_ADDR + 2**AXIL_CSR_ADDR_WIDTH;
@ -411,13 +413,13 @@ parameter AXIL_TX_QM_BASE_ADDR = AXIL_EQM_BASE_ADDR + 2**AXIL_EQM_ADDR_WIDTH;
parameter AXIL_TX_CQM_BASE_ADDR = AXIL_TX_QM_BASE_ADDR + 2**AXIL_TX_QM_ADDR_WIDTH;
parameter AXIL_RX_QM_BASE_ADDR = AXIL_TX_CQM_BASE_ADDR + 2**AXIL_TX_CQM_ADDR_WIDTH;
parameter AXIL_RX_CQM_BASE_ADDR = AXIL_RX_QM_BASE_ADDR + 2**AXIL_RX_QM_ADDR_WIDTH;
parameter AXIL_PORT_BASE_ADDR = AXIL_RX_CQM_BASE_ADDR + 2**AXIL_RX_CQM_ADDR_WIDTH;
parameter AXIL_SCHED_BASE_ADDR = AXIL_RX_CQM_BASE_ADDR + 2**AXIL_RX_CQM_ADDR_WIDTH;
localparam RB_BASE_ADDR = AXIL_CTRL_BASE_ADDR;
localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}};
localparam PORT_RB_BASE_ADDR = RB_BASE_ADDR + 16'h1000;
localparam PORT_RB_STRIDE = 16'h1000;
localparam SCHED_RB_BASE_ADDR = RB_BASE_ADDR + 16'h1000;
localparam SCHED_RB_STRIDE = 16'h1000;
// parameter sizing helpers
function [31:0] w_32(input [31:0] val);
@ -545,25 +547,25 @@ wire [1:0] axil_rx_cpl_queue_manager_rresp;
wire axil_rx_cpl_queue_manager_rvalid;
wire axil_rx_cpl_queue_manager_rready;
wire [PORTS*AXIL_ADDR_WIDTH-1:0] axil_port_awaddr;
wire [PORTS*3-1:0] axil_port_awprot;
wire [PORTS-1:0] axil_port_awvalid;
wire [PORTS-1:0] axil_port_awready;
wire [PORTS*AXIL_DATA_WIDTH-1:0] axil_port_wdata;
wire [PORTS*AXIL_STRB_WIDTH-1:0] axil_port_wstrb;
wire [PORTS-1:0] axil_port_wvalid;
wire [PORTS-1:0] axil_port_wready;
wire [PORTS*2-1:0] axil_port_bresp;
wire [PORTS-1:0] axil_port_bvalid;
wire [PORTS-1:0] axil_port_bready;
wire [PORTS*AXIL_ADDR_WIDTH-1:0] axil_port_araddr;
wire [PORTS*3-1:0] axil_port_arprot;
wire [PORTS-1:0] axil_port_arvalid;
wire [PORTS-1:0] axil_port_arready;
wire [PORTS*AXIL_DATA_WIDTH-1:0] axil_port_rdata;
wire [PORTS*2-1:0] axil_port_rresp;
wire [PORTS-1:0] axil_port_rvalid;
wire [PORTS-1:0] axil_port_rready;
wire [PORTS*AXIL_ADDR_WIDTH-1:0] axil_sched_awaddr;
wire [PORTS*3-1:0] axil_sched_awprot;
wire [PORTS-1:0] axil_sched_awvalid;
wire [PORTS-1:0] axil_sched_awready;
wire [PORTS*AXIL_DATA_WIDTH-1:0] axil_sched_wdata;
wire [PORTS*AXIL_STRB_WIDTH-1:0] axil_sched_wstrb;
wire [PORTS-1:0] axil_sched_wvalid;
wire [PORTS-1:0] axil_sched_wready;
wire [PORTS*2-1:0] axil_sched_bresp;
wire [PORTS-1:0] axil_sched_bvalid;
wire [PORTS-1:0] axil_sched_bready;
wire [PORTS*AXIL_ADDR_WIDTH-1:0] axil_sched_araddr;
wire [PORTS*3-1:0] axil_sched_arprot;
wire [PORTS-1:0] axil_sched_arvalid;
wire [PORTS-1:0] axil_sched_arready;
wire [PORTS*AXIL_DATA_WIDTH-1:0] axil_sched_rdata;
wire [PORTS*2-1:0] axil_sched_rresp;
wire [PORTS-1:0] axil_sched_rvalid;
wire [PORTS-1:0] axil_sched_rready;
// Queue management
wire [CPL_QUEUE_INDEX_WIDTH-1:0] event_enqueue_req_queue;
@ -999,7 +1001,7 @@ always @(posedge clk) begin
// Queue manager (RX CPL)
RBB+8'hC0: ctrl_reg_rd_data_reg <= 32'h0000C031; // RX CPL QM: Type
RBB+8'hC4: ctrl_reg_rd_data_reg <= 32'h00000100; // RX CPL QM: Version
RBB+8'hC8: ctrl_reg_rd_data_reg <= PORT_RB_BASE_ADDR; // RX CPL QM: Next header
RBB+8'hC8: ctrl_reg_rd_data_reg <= SCHED_RB_BASE_ADDR; // RX CPL QM: Next header
RBB+8'hCC: ctrl_reg_rd_data_reg <= AXIL_RX_CQM_BASE_ADDR; // RX CPL QM: Offset
RBB+8'hD0: ctrl_reg_rd_data_reg <= 2**RX_CPL_QUEUE_INDEX_WIDTH; // RX CPL QM: Count
RBB+8'hD4: ctrl_reg_rd_data_reg <= 32; // RX CPL QM: Stride
@ -1020,7 +1022,7 @@ end
// AXI lite crossbar
parameter AXIL_S_COUNT = 1;
parameter AXIL_M_COUNT = 7+PORTS;
parameter AXIL_M_COUNT = 7+SCHEDULERS;
axil_crossbar #(
.DATA_WIDTH(AXIL_DATA_WIDTH),
@ -1028,7 +1030,7 @@ axil_crossbar #(
.STRB_WIDTH(AXIL_STRB_WIDTH),
.S_COUNT(AXIL_S_COUNT),
.M_COUNT(AXIL_M_COUNT),
.M_ADDR_WIDTH({{PORTS{w_32(AXIL_PORT_ADDR_WIDTH)}}, w_32(AXIL_RX_CQM_ADDR_WIDTH), w_32(AXIL_RX_QM_ADDR_WIDTH), w_32(AXIL_TX_CQM_ADDR_WIDTH), w_32(AXIL_TX_QM_ADDR_WIDTH), w_32(AXIL_EQM_ADDR_WIDTH), w_32(AXIL_CTRL_ADDR_WIDTH), w_32(AXIL_CSR_ADDR_WIDTH)}),
.M_ADDR_WIDTH({{SCHEDULERS{w_32(AXIL_SCHED_ADDR_WIDTH)}}, w_32(AXIL_RX_CQM_ADDR_WIDTH), w_32(AXIL_RX_QM_ADDR_WIDTH), w_32(AXIL_TX_CQM_ADDR_WIDTH), w_32(AXIL_TX_QM_ADDR_WIDTH), w_32(AXIL_EQM_ADDR_WIDTH), w_32(AXIL_CTRL_ADDR_WIDTH), w_32(AXIL_CSR_ADDR_WIDTH)}),
.M_CONNECT_READ({AXIL_M_COUNT{{AXIL_S_COUNT{1'b1}}}}),
.M_CONNECT_WRITE({AXIL_M_COUNT{{AXIL_S_COUNT{1'b1}}}})
)
@ -1054,25 +1056,25 @@ axil_crossbar_inst (
.s_axil_rresp(s_axil_rresp),
.s_axil_rvalid(s_axil_rvalid),
.s_axil_rready(s_axil_rready),
.m_axil_awaddr( {axil_port_awaddr, axil_rx_cpl_queue_manager_awaddr, axil_rx_queue_manager_awaddr, axil_tx_cpl_queue_manager_awaddr, axil_tx_queue_manager_awaddr, axil_event_queue_manager_awaddr, axil_ctrl_awaddr, m_axil_csr_awaddr}),
.m_axil_awprot( {axil_port_awprot, axil_rx_cpl_queue_manager_awprot, axil_rx_queue_manager_awprot, axil_tx_cpl_queue_manager_awprot, axil_tx_queue_manager_awprot, axil_event_queue_manager_awprot, axil_ctrl_awprot, m_axil_csr_awprot}),
.m_axil_awvalid({axil_port_awvalid, axil_rx_cpl_queue_manager_awvalid, axil_rx_queue_manager_awvalid, axil_tx_cpl_queue_manager_awvalid, axil_tx_queue_manager_awvalid, axil_event_queue_manager_awvalid, axil_ctrl_awvalid, m_axil_csr_awvalid}),
.m_axil_awready({axil_port_awready, axil_rx_cpl_queue_manager_awready, axil_rx_queue_manager_awready, axil_tx_cpl_queue_manager_awready, axil_tx_queue_manager_awready, axil_event_queue_manager_awready, axil_ctrl_awready, m_axil_csr_awready}),
.m_axil_wdata( {axil_port_wdata, axil_rx_cpl_queue_manager_wdata, axil_rx_queue_manager_wdata, axil_tx_cpl_queue_manager_wdata, axil_tx_queue_manager_wdata, axil_event_queue_manager_wdata, axil_ctrl_wdata, m_axil_csr_wdata}),
.m_axil_wstrb( {axil_port_wstrb, axil_rx_cpl_queue_manager_wstrb, axil_rx_queue_manager_wstrb, axil_tx_cpl_queue_manager_wstrb, axil_tx_queue_manager_wstrb, axil_event_queue_manager_wstrb, axil_ctrl_wstrb, m_axil_csr_wstrb}),
.m_axil_wvalid( {axil_port_wvalid, axil_rx_cpl_queue_manager_wvalid, axil_rx_queue_manager_wvalid, axil_tx_cpl_queue_manager_wvalid, axil_tx_queue_manager_wvalid, axil_event_queue_manager_wvalid, axil_ctrl_wvalid, m_axil_csr_wvalid}),
.m_axil_wready( {axil_port_wready, axil_rx_cpl_queue_manager_wready, axil_rx_queue_manager_wready, axil_tx_cpl_queue_manager_wready, axil_tx_queue_manager_wready, axil_event_queue_manager_wready, axil_ctrl_wready, m_axil_csr_wready}),
.m_axil_bresp( {axil_port_bresp, axil_rx_cpl_queue_manager_bresp, axil_rx_queue_manager_bresp, axil_tx_cpl_queue_manager_bresp, axil_tx_queue_manager_bresp, axil_event_queue_manager_bresp, axil_ctrl_bresp, m_axil_csr_bresp}),
.m_axil_bvalid( {axil_port_bvalid, axil_rx_cpl_queue_manager_bvalid, axil_rx_queue_manager_bvalid, axil_tx_cpl_queue_manager_bvalid, axil_tx_queue_manager_bvalid, axil_event_queue_manager_bvalid, axil_ctrl_bvalid, m_axil_csr_bvalid}),
.m_axil_bready( {axil_port_bready, axil_rx_cpl_queue_manager_bready, axil_rx_queue_manager_bready, axil_tx_cpl_queue_manager_bready, axil_tx_queue_manager_bready, axil_event_queue_manager_bready, axil_ctrl_bready, m_axil_csr_bready}),
.m_axil_araddr( {axil_port_araddr, axil_rx_cpl_queue_manager_araddr, axil_rx_queue_manager_araddr, axil_tx_cpl_queue_manager_araddr, axil_tx_queue_manager_araddr, axil_event_queue_manager_araddr, axil_ctrl_araddr, m_axil_csr_araddr}),
.m_axil_arprot( {axil_port_arprot, axil_rx_cpl_queue_manager_arprot, axil_rx_queue_manager_arprot, axil_tx_cpl_queue_manager_arprot, axil_tx_queue_manager_arprot, axil_event_queue_manager_arprot, axil_ctrl_arprot, m_axil_csr_arprot}),
.m_axil_arvalid({axil_port_arvalid, axil_rx_cpl_queue_manager_arvalid, axil_rx_queue_manager_arvalid, axil_tx_cpl_queue_manager_arvalid, axil_tx_queue_manager_arvalid, axil_event_queue_manager_arvalid, axil_ctrl_arvalid, m_axil_csr_arvalid}),
.m_axil_arready({axil_port_arready, axil_rx_cpl_queue_manager_arready, axil_rx_queue_manager_arready, axil_tx_cpl_queue_manager_arready, axil_tx_queue_manager_arready, axil_event_queue_manager_arready, axil_ctrl_arready, m_axil_csr_arready}),
.m_axil_rdata( {axil_port_rdata, axil_rx_cpl_queue_manager_rdata, axil_rx_queue_manager_rdata, axil_tx_cpl_queue_manager_rdata, axil_tx_queue_manager_rdata, axil_event_queue_manager_rdata, axil_ctrl_rdata, m_axil_csr_rdata}),
.m_axil_rresp( {axil_port_rresp, axil_rx_cpl_queue_manager_rresp, axil_rx_queue_manager_rresp, axil_tx_cpl_queue_manager_rresp, axil_tx_queue_manager_rresp, axil_event_queue_manager_rresp, axil_ctrl_rresp, m_axil_csr_rresp}),
.m_axil_rvalid( {axil_port_rvalid, axil_rx_cpl_queue_manager_rvalid, axil_rx_queue_manager_rvalid, axil_tx_cpl_queue_manager_rvalid, axil_tx_queue_manager_rvalid, axil_event_queue_manager_rvalid, axil_ctrl_rvalid, m_axil_csr_rvalid}),
.m_axil_rready( {axil_port_rready, axil_rx_cpl_queue_manager_rready, axil_rx_queue_manager_rready, axil_tx_cpl_queue_manager_rready, axil_tx_queue_manager_rready, axil_event_queue_manager_rready, axil_ctrl_rready, m_axil_csr_rready})
.m_axil_awaddr( {axil_sched_awaddr, axil_rx_cpl_queue_manager_awaddr, axil_rx_queue_manager_awaddr, axil_tx_cpl_queue_manager_awaddr, axil_tx_queue_manager_awaddr, axil_event_queue_manager_awaddr, axil_ctrl_awaddr, m_axil_csr_awaddr}),
.m_axil_awprot( {axil_sched_awprot, axil_rx_cpl_queue_manager_awprot, axil_rx_queue_manager_awprot, axil_tx_cpl_queue_manager_awprot, axil_tx_queue_manager_awprot, axil_event_queue_manager_awprot, axil_ctrl_awprot, m_axil_csr_awprot}),
.m_axil_awvalid({axil_sched_awvalid, axil_rx_cpl_queue_manager_awvalid, axil_rx_queue_manager_awvalid, axil_tx_cpl_queue_manager_awvalid, axil_tx_queue_manager_awvalid, axil_event_queue_manager_awvalid, axil_ctrl_awvalid, m_axil_csr_awvalid}),
.m_axil_awready({axil_sched_awready, axil_rx_cpl_queue_manager_awready, axil_rx_queue_manager_awready, axil_tx_cpl_queue_manager_awready, axil_tx_queue_manager_awready, axil_event_queue_manager_awready, axil_ctrl_awready, m_axil_csr_awready}),
.m_axil_wdata( {axil_sched_wdata, axil_rx_cpl_queue_manager_wdata, axil_rx_queue_manager_wdata, axil_tx_cpl_queue_manager_wdata, axil_tx_queue_manager_wdata, axil_event_queue_manager_wdata, axil_ctrl_wdata, m_axil_csr_wdata}),
.m_axil_wstrb( {axil_sched_wstrb, axil_rx_cpl_queue_manager_wstrb, axil_rx_queue_manager_wstrb, axil_tx_cpl_queue_manager_wstrb, axil_tx_queue_manager_wstrb, axil_event_queue_manager_wstrb, axil_ctrl_wstrb, m_axil_csr_wstrb}),
.m_axil_wvalid( {axil_sched_wvalid, axil_rx_cpl_queue_manager_wvalid, axil_rx_queue_manager_wvalid, axil_tx_cpl_queue_manager_wvalid, axil_tx_queue_manager_wvalid, axil_event_queue_manager_wvalid, axil_ctrl_wvalid, m_axil_csr_wvalid}),
.m_axil_wready( {axil_sched_wready, axil_rx_cpl_queue_manager_wready, axil_rx_queue_manager_wready, axil_tx_cpl_queue_manager_wready, axil_tx_queue_manager_wready, axil_event_queue_manager_wready, axil_ctrl_wready, m_axil_csr_wready}),
.m_axil_bresp( {axil_sched_bresp, axil_rx_cpl_queue_manager_bresp, axil_rx_queue_manager_bresp, axil_tx_cpl_queue_manager_bresp, axil_tx_queue_manager_bresp, axil_event_queue_manager_bresp, axil_ctrl_bresp, m_axil_csr_bresp}),
.m_axil_bvalid( {axil_sched_bvalid, axil_rx_cpl_queue_manager_bvalid, axil_rx_queue_manager_bvalid, axil_tx_cpl_queue_manager_bvalid, axil_tx_queue_manager_bvalid, axil_event_queue_manager_bvalid, axil_ctrl_bvalid, m_axil_csr_bvalid}),
.m_axil_bready( {axil_sched_bready, axil_rx_cpl_queue_manager_bready, axil_rx_queue_manager_bready, axil_tx_cpl_queue_manager_bready, axil_tx_queue_manager_bready, axil_event_queue_manager_bready, axil_ctrl_bready, m_axil_csr_bready}),
.m_axil_araddr( {axil_sched_araddr, axil_rx_cpl_queue_manager_araddr, axil_rx_queue_manager_araddr, axil_tx_cpl_queue_manager_araddr, axil_tx_queue_manager_araddr, axil_event_queue_manager_araddr, axil_ctrl_araddr, m_axil_csr_araddr}),
.m_axil_arprot( {axil_sched_arprot, axil_rx_cpl_queue_manager_arprot, axil_rx_queue_manager_arprot, axil_tx_cpl_queue_manager_arprot, axil_tx_queue_manager_arprot, axil_event_queue_manager_arprot, axil_ctrl_arprot, m_axil_csr_arprot}),
.m_axil_arvalid({axil_sched_arvalid, axil_rx_cpl_queue_manager_arvalid, axil_rx_queue_manager_arvalid, axil_tx_cpl_queue_manager_arvalid, axil_tx_queue_manager_arvalid, axil_event_queue_manager_arvalid, axil_ctrl_arvalid, m_axil_csr_arvalid}),
.m_axil_arready({axil_sched_arready, axil_rx_cpl_queue_manager_arready, axil_rx_queue_manager_arready, axil_tx_cpl_queue_manager_arready, axil_tx_queue_manager_arready, axil_event_queue_manager_arready, axil_ctrl_arready, m_axil_csr_arready}),
.m_axil_rdata( {axil_sched_rdata, axil_rx_cpl_queue_manager_rdata, axil_rx_queue_manager_rdata, axil_tx_cpl_queue_manager_rdata, axil_tx_queue_manager_rdata, axil_event_queue_manager_rdata, axil_ctrl_rdata, m_axil_csr_rdata}),
.m_axil_rresp( {axil_sched_rresp, axil_rx_cpl_queue_manager_rresp, axil_rx_queue_manager_rresp, axil_tx_cpl_queue_manager_rresp, axil_tx_queue_manager_rresp, axil_event_queue_manager_rresp, axil_ctrl_rresp, m_axil_csr_rresp}),
.m_axil_rvalid( {axil_sched_rvalid, axil_rx_cpl_queue_manager_rvalid, axil_rx_queue_manager_rvalid, axil_tx_cpl_queue_manager_rvalid, axil_tx_queue_manager_rvalid, axil_event_queue_manager_rvalid, axil_ctrl_rvalid, m_axil_csr_rvalid}),
.m_axil_rready( {axil_sched_rready, axil_rx_cpl_queue_manager_rready, axil_rx_queue_manager_rready, axil_tx_cpl_queue_manager_rready, axil_tx_queue_manager_rready, axil_event_queue_manager_rready, axil_ctrl_rready, m_axil_csr_rready})
);
// Queue managers
@ -1977,15 +1979,15 @@ rx_event_fifo (
// TX
wire [PORTS*TX_QUEUE_INDEX_WIDTH-1:0] tx_sched_req_queue;
wire [PORTS*REQ_TAG_WIDTH_INT-1:0] tx_sched_req_tag;
wire [PORTS*AXIS_TX_DEST_WIDTH-1:0] tx_sched_req_dest;
wire [PORTS-1:0] tx_sched_req_valid;
wire [PORTS-1:0] tx_sched_req_ready;
wire [SCHEDULERS*TX_QUEUE_INDEX_WIDTH-1:0] tx_sched_req_queue;
wire [SCHEDULERS*REQ_TAG_WIDTH_INT-1:0] tx_sched_req_tag;
wire [SCHEDULERS*AXIS_TX_DEST_WIDTH-1:0] tx_sched_req_dest;
wire [SCHEDULERS-1:0] tx_sched_req_valid;
wire [SCHEDULERS-1:0] tx_sched_req_ready;
wire [PORTS*DMA_CLIENT_LEN_WIDTH-1:0] tx_sched_req_status_len;
wire [PORTS*REQ_TAG_WIDTH_INT-1:0] tx_sched_req_status_tag;
wire [PORTS-1:0] tx_sched_req_status_valid;
wire [SCHEDULERS*DMA_CLIENT_LEN_WIDTH-1:0] tx_sched_req_status_len;
wire [SCHEDULERS*REQ_TAG_WIDTH_INT-1:0] tx_sched_req_status_tag;
wire [SCHEDULERS-1:0] tx_sched_req_status_valid;
wire [TX_QUEUE_INDEX_WIDTH-1:0] tx_req_queue;
wire [REQ_TAG_WIDTH-1:0] tx_req_tag;
@ -2001,7 +2003,7 @@ generate
genvar n;
for (n = 0; n < PORTS; n = n + 1) begin : port
for (n = 0; n < SCHEDULERS; n = n + 1) begin : port
mqnic_tx_scheduler_block #(
.PORTS(PORTS),
@ -2009,12 +2011,12 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
.REG_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH),
.REG_DATA_WIDTH(AXIL_DATA_WIDTH),
.REG_STRB_WIDTH(AXIL_STRB_WIDTH),
.RB_BASE_ADDR(PORT_RB_BASE_ADDR + PORT_RB_STRIDE*n),
.RB_NEXT_PTR(n < PORTS-1 ? PORT_RB_BASE_ADDR + PORT_RB_STRIDE*(n+1) : 0),
.RB_BASE_ADDR(SCHED_RB_BASE_ADDR + SCHED_RB_STRIDE*n),
.RB_NEXT_PTR(n < SCHEDULERS-1 ? SCHED_RB_BASE_ADDR + SCHED_RB_STRIDE*(n+1) : 0),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_PORT_ADDR_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_SCHED_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.AXIL_OFFSET(AXIL_PORT_BASE_ADDR + (2**AXIL_PORT_ADDR_WIDTH)*n),
.AXIL_OFFSET(AXIL_SCHED_BASE_ADDR + (2**AXIL_SCHED_ADDR_WIDTH)*n),
.LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
.REQ_TAG_WIDTH(REQ_TAG_WIDTH_INT),
.OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
@ -2047,25 +2049,25 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
/*
* AXI-Lite slave interface
*/
.s_axil_awaddr(axil_port_awaddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]),
.s_axil_awprot(axil_port_awprot[n*3 +: 3]),
.s_axil_awvalid(axil_port_awvalid[n +: 1]),
.s_axil_awready(axil_port_awready[n +: 1]),
.s_axil_wdata(axil_port_wdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]),
.s_axil_wstrb(axil_port_wstrb[n*AXIL_STRB_WIDTH +: AXIL_STRB_WIDTH]),
.s_axil_wvalid(axil_port_wvalid[n +: 1]),
.s_axil_wready(axil_port_wready[n +: 1]),
.s_axil_bresp(axil_port_bresp[n*2 +: 2]),
.s_axil_bvalid(axil_port_bvalid[n +: 1]),
.s_axil_bready(axil_port_bready[n +: 1]),
.s_axil_araddr(axil_port_araddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]),
.s_axil_arprot(axil_port_arprot[n*3 +: 3]),
.s_axil_arvalid(axil_port_arvalid[n +: 1]),
.s_axil_arready(axil_port_arready[n +: 1]),
.s_axil_rdata(axil_port_rdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]),
.s_axil_rresp(axil_port_rresp[n*2 +: 2]),
.s_axil_rvalid(axil_port_rvalid[n +: 1]),
.s_axil_rready(axil_port_rready[n +: 1]),
.s_axil_awaddr(axil_sched_awaddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]),
.s_axil_awprot(axil_sched_awprot[n*3 +: 3]),
.s_axil_awvalid(axil_sched_awvalid[n +: 1]),
.s_axil_awready(axil_sched_awready[n +: 1]),
.s_axil_wdata(axil_sched_wdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]),
.s_axil_wstrb(axil_sched_wstrb[n*AXIL_STRB_WIDTH +: AXIL_STRB_WIDTH]),
.s_axil_wvalid(axil_sched_wvalid[n +: 1]),
.s_axil_wready(axil_sched_wready[n +: 1]),
.s_axil_bresp(axil_sched_bresp[n*2 +: 2]),
.s_axil_bvalid(axil_sched_bvalid[n +: 1]),
.s_axil_bready(axil_sched_bready[n +: 1]),
.s_axil_araddr(axil_sched_araddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]),
.s_axil_arprot(axil_sched_arprot[n*3 +: 3]),
.s_axil_arvalid(axil_sched_arvalid[n +: 1]),
.s_axil_arready(axil_sched_arready[n +: 1]),
.s_axil_rdata(axil_sched_rdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]),
.s_axil_rresp(axil_sched_rresp[n*2 +: 2]),
.s_axil_rvalid(axil_sched_rvalid[n +: 1]),
.s_axil_rready(axil_sched_rready[n +: 1]),
/*
* Transmit request output (queue index)
@ -2103,10 +2105,10 @@ for (n = 0; n < PORTS; n = n + 1) begin : port
end
if (PORTS > 1) begin
if (SCHEDULERS > 1) begin
tx_req_mux #(
.PORTS(PORTS),
.PORTS(SCHEDULERS),
.QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.S_REQ_TAG_WIDTH(REQ_TAG_WIDTH_INT),
.M_REQ_TAG_WIDTH(REQ_TAG_WIDTH),

4
fpga/common/rtl/mqnic_tx_scheduler_block_rr.v
View File

@ -170,7 +170,7 @@ reg [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = 0;
reg ctrl_reg_rd_ack_reg = 1'b0;
reg sched_enable_reg = 1'b0;
reg [AXIS_TX_DEST_WIDTH-1:0] sched_dest_reg = INDEX << 4;
reg [AXIS_TX_DEST_WIDTH-1:0] sched_dest_reg = (INDEX % PORTS) << 4;
assign ctrl_reg_wr_wait = 1'b0;
assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg;
@ -234,7 +234,7 @@ always @(posedge clk) begin
ctrl_reg_rd_ack_reg <= 1'b0;
sched_enable_reg <= 1'b0;
sched_dest_reg <= INDEX << 4;
sched_dest_reg <= (INDEX % PORTS) << 4;
end
end

4
fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v
View File

@ -208,7 +208,7 @@ reg [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = 0;
reg ctrl_reg_rd_ack_reg = 1'b0;
reg sched_enable_reg = 1'b0;
reg [AXIS_TX_DEST_WIDTH-1:0] sched_dest_reg = INDEX << 4;
reg [AXIS_TX_DEST_WIDTH-1:0] sched_dest_reg = (INDEX % PORTS) << 4;
reg tdma_enable_reg = 1'b0;
wire tdma_locked;
@ -370,7 +370,7 @@ always @(posedge clk) begin
ctrl_reg_rd_ack_reg <= 1'b0;
sched_enable_reg <= 1'b0;
sched_dest_reg <= INDEX << 4;
sched_dest_reg <= (INDEX % PORTS) << 4;
end
end

3
fpga/common/tb/mqnic_core_axi/Makefile
View File

@ -115,6 +115,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# Structural configuration
export PARAM_IF_COUNT ?= 1
export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLOCK_PIPELINE ?= 0
@ -225,6 +226,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
@ -311,6 +313,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)

1
fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
View File

@ -473,6 +473,7 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
# Structural configuration
parameters['IF_COUNT'] = if_count
parameters['PORTS_PER_IF'] = ports_per_if
parameters['SCHED_PER_IF'] = ports_per_if
# PTP configuration
parameters['PTP_CLOCK_PIPELINE'] = 0

3
fpga/common/tb/mqnic_core_pcie_s10/Makefile
View File

@ -125,6 +125,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# Structural configuration
export PARAM_IF_COUNT ?= 1
export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLOCK_PIPELINE ?= 0
@ -240,6 +241,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
@ -333,6 +335,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)

1
fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
View File

@ -597,6 +597,7 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
# Structural configuration
parameters['IF_COUNT'] = if_count
parameters['PORTS_PER_IF'] = ports_per_if
parameters['SCHED_PER_IF'] = ports_per_if
# PTP configuration
parameters['PTP_CLOCK_PIPELINE'] = 0

3
fpga/common/tb/mqnic_core_pcie_us/Makefile
View File

@ -127,6 +127,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# Structural configuration
export PARAM_IF_COUNT ?= 1
export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLOCK_PIPELINE ?= 0
@ -237,6 +238,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
@ -325,6 +327,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)

1
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -674,6 +674,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
# Structural configuration
parameters['IF_COUNT'] = if_count
parameters['PORTS_PER_IF'] = ports_per_if
parameters['SCHED_PER_IF'] = ports_per_if
# PTP configuration
parameters['PTP_CLOCK_PIPELINE'] = 0

3
fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
View File

@ -129,6 +129,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# Structural configuration
export PARAM_IF_COUNT ?= 1
export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLOCK_PIPELINE ?= 0
@ -239,6 +240,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
@ -327,6 +329,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)

1
fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
View File

@ -729,6 +729,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
# Structural configuration
parameters['IF_COUNT'] = if_count
parameters['PORTS_PER_IF'] = ports_per_if
parameters['SCHED_PER_IF'] = ports_per_if
# PTP configuration
parameters['PTP_CLOCK_PIPELINE'] = 0

1
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
View File

@ -90,6 +90,7 @@ dict set params RELEASE_INFO [format "32'h%08x" $release_info]
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"

1
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
View File

@ -90,6 +90,7 @@ dict set params RELEASE_INFO [format "32'h%08x" $release_info]
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
View File

@ -55,6 +55,7 @@ module fpga #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 0,
@ -1677,6 +1678,7 @@ fpga_core #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
View File

@ -55,6 +55,7 @@ module fpga_core #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_TS_WIDTH = 96,
@ -800,6 +801,7 @@ mqnic_core_pcie_us #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),

3
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
View File

@ -129,6 +129,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# Structural configuration
export PARAM_IF_COUNT ?= 2
export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLOCK_PIPELINE ?= 0
@ -234,6 +235,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
@ -317,6 +319,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)

1
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -610,6 +610,7 @@ def test_fpga_core(request):
# Structural configuration
parameters['IF_COUNT'] = 2
parameters['PORTS_PER_IF'] = 1
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
# PTP configuration
parameters['PTP_CLOCK_PIPELINE'] = 0

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl
View File

@ -116,6 +116,7 @@ set eth_xcvr_rx_eq_mode {DFE}
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl
View File

@ -116,6 +116,7 @@ set eth_xcvr_rx_eq_mode {DFE}
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
View File

@ -116,6 +116,7 @@ set eth_xcvr_rx_eq_mode {DFE}
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -55,6 +55,7 @@ module fpga #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 0,
@ -1344,6 +1345,7 @@ fpga_core #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -55,6 +55,7 @@ module fpga_core #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_TS_WIDTH = 96,
@ -1164,6 +1165,7 @@ mqnic_core_pcie_us #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),

3
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
View File

@ -137,6 +137,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# Structural configuration
export PARAM_IF_COUNT ?= 2
export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLOCK_PIPELINE ?= 0
@ -241,6 +242,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -323,6 +325,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -670,6 +670,7 @@ def test_fpga_core(request):
# Structural configuration
parameters['IF_COUNT'] = 2
parameters['PORTS_PER_IF'] = 1
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
# PTP configuration
parameters['PTP_CLOCK_PIPELINE'] = 0

1
fpga/mqnic/AU200/fpga_100g/fpga/config.tcl
View File

@ -90,6 +90,7 @@ dict set params RELEASE_INFO [format "32'h%08x" $release_info]
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"

2
fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
View File

@ -55,6 +55,7 @@ module fpga #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 0,
@ -1811,6 +1812,7 @@ fpga_core #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),

2
fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
View File

@ -55,6 +55,7 @@ module fpga_core #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_TS_WIDTH = 96,
@ -808,6 +809,7 @@ mqnic_core_pcie_us #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),

3
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
View File

@ -129,6 +129,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# Structural configuration
export PARAM_IF_COUNT ?= 2
export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLOCK_PIPELINE ?= 0
@ -234,6 +235,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
@ -317,6 +319,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)

1
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -610,6 +610,7 @@ def test_fpga_core(request):
# Structural configuration
parameters['IF_COUNT'] = 2
parameters['PORTS_PER_IF'] = 1
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
# PTP configuration
parameters['PTP_CLOCK_PIPELINE'] = 0

1
fpga/mqnic/AU200/fpga_25g/fpga/config.tcl
View File

@ -116,6 +116,7 @@ set eth_xcvr_rx_eq_mode {DFE}
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"

1
fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl
View File

@ -116,6 +116,7 @@ set eth_xcvr_rx_eq_mode {DFE}
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"

2
fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
View File

@ -55,6 +55,7 @@ module fpga #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 0,
@ -1477,6 +1478,7 @@ fpga_core #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),

2
fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
View File

@ -55,6 +55,7 @@ module fpga_core #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_TS_WIDTH = 96,
@ -1173,6 +1174,7 @@ mqnic_core_pcie_us #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),

3
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
View File

@ -137,6 +137,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# Structural configuration
export PARAM_IF_COUNT ?= 2
export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLOCK_PIPELINE ?= 0
@ -241,6 +242,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -323,6 +325,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

1
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -670,6 +670,7 @@ def test_fpga_core(request):
# Structural configuration
parameters['IF_COUNT'] = 2
parameters['PORTS_PER_IF'] = 1
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
# PTP configuration
parameters['PTP_CLOCK_PIPELINE'] = 0

1
fpga/mqnic/AU250/fpga_100g/fpga/config.tcl
View File

@ -90,6 +90,7 @@ dict set params RELEASE_INFO [format "32'h%08x" $release_info]
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"

2
fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
View File

@ -55,6 +55,7 @@ module fpga #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 0,
@ -1811,6 +1812,7 @@ fpga_core #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),

2
fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
View File

@ -55,6 +55,7 @@ module fpga_core #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_TS_WIDTH = 96,
@ -808,6 +809,7 @@ mqnic_core_pcie_us #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),

3
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
View File

@ -129,6 +129,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# Structural configuration
export PARAM_IF_COUNT ?= 2
export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLOCK_PIPELINE ?= 0
@ -234,6 +235,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
@ -317,6 +319,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)

1
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -610,6 +610,7 @@ def test_fpga_core(request):
# Structural configuration
parameters['IF_COUNT'] = 2
parameters['PORTS_PER_IF'] = 1
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
# PTP configuration
parameters['PTP_CLOCK_PIPELINE'] = 0

1
fpga/mqnic/AU250/fpga_25g/fpga/config.tcl
View File

@ -116,6 +116,7 @@ set eth_xcvr_rx_eq_mode {DFE}
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"

1
fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl
View File

@ -116,6 +116,7 @@ set eth_xcvr_rx_eq_mode {DFE}
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"

2
fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
View File

@ -55,6 +55,7 @@ module fpga #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 0,
@ -1477,6 +1478,7 @@ fpga_core #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),

2
fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
View File

@ -55,6 +55,7 @@ module fpga_core #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_TS_WIDTH = 96,
@ -1173,6 +1174,7 @@ mqnic_core_pcie_us #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),

3
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile
View File

@ -137,6 +137,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# Structural configuration
export PARAM_IF_COUNT ?= 2
export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLOCK_PIPELINE ?= 0
@ -241,6 +242,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -323,6 +325,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

1
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -670,6 +670,7 @@ def test_fpga_core(request):
# Structural configuration
parameters['IF_COUNT'] = 2
parameters['PORTS_PER_IF'] = 1
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
# PTP configuration
parameters['PTP_CLOCK_PIPELINE'] = 0

1
fpga/mqnic/AU280/fpga_100g/fpga/config.tcl
View File

@ -90,6 +90,7 @@ dict set params RELEASE_INFO [format "32'h%08x" $release_info]
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "1"

2
fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
View File

@ -55,6 +55,7 @@ module fpga #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 1,
@ -1708,6 +1709,7 @@ fpga_core #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),

2
fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
View File

@ -55,6 +55,7 @@ module fpga_core #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_TS_WIDTH = 96,
@ -684,6 +685,7 @@ mqnic_core_pcie_us #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),

3
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
View File

@ -129,6 +129,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# Structural configuration
export PARAM_IF_COUNT ?= 2
export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLOCK_PIPELINE ?= 1
@ -234,6 +235,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
@ -317,6 +319,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)

1
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -599,6 +599,7 @@ def test_fpga_core(request):
# Structural configuration
parameters['IF_COUNT'] = 2
parameters['PORTS_PER_IF'] = 1
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
# PTP configuration
parameters['PTP_CLOCK_PIPELINE'] = 1

1
fpga/mqnic/AU280/fpga_25g/fpga/config.tcl
View File

@ -116,6 +116,7 @@ set eth_xcvr_rx_eq_mode {DFE}
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "1"

1
fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl
View File

@ -116,6 +116,7 @@ set eth_xcvr_rx_eq_mode {DFE}
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "1"

2
fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
View File

@ -55,6 +55,7 @@ module fpga #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 1,
@ -1380,6 +1381,7 @@ fpga_core #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),

2
fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
View File

@ -55,6 +55,7 @@ module fpga_core #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_TS_WIDTH = 96,
@ -1049,6 +1050,7 @@ mqnic_core_pcie_us #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),

3
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
View File

@ -137,6 +137,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# Structural configuration
export PARAM_IF_COUNT ?= 2
export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLOCK_PIPELINE ?= 1
@ -241,6 +242,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -323,6 +325,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

1
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -659,6 +659,7 @@ def test_fpga_core(request):
# Structural configuration
parameters['IF_COUNT'] = 2
parameters['PORTS_PER_IF'] = 1
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
# PTP configuration
parameters['PTP_CLOCK_PIPELINE'] = 1

1
fpga/mqnic/AU50/fpga_100g/fpga/config.tcl
View File

@ -88,6 +88,7 @@ dict set params RELEASE_INFO [format "32'h%08x" $release_info]
dict set params IF_COUNT "1"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "1"

2
fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
View File

@ -55,6 +55,7 @@ module fpga #
// Structural configuration
parameter IF_COUNT = 1,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 1,
@ -1310,6 +1311,7 @@ fpga_core #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),

2
fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
View File

@ -55,6 +55,7 @@ module fpga_core #
// Structural configuration
parameter IF_COUNT = 1,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_TS_WIDTH = 96,
@ -639,6 +640,7 @@ mqnic_core_pcie_us #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),

3
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
View File

@ -129,6 +129,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# Structural configuration
export PARAM_IF_COUNT ?= 1
export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLOCK_PIPELINE ?= 1
@ -234,6 +235,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
@ -317,6 +319,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)

1
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -560,6 +560,7 @@ def test_fpga_core(request):
# Structural configuration
parameters['IF_COUNT'] = 1
parameters['PORTS_PER_IF'] = 1
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
# PTP configuration
parameters['PTP_CLOCK_PIPELINE'] = 1

1
fpga/mqnic/AU50/fpga_25g/fpga/config.tcl
View File

@ -104,6 +104,7 @@ set eth_xcvr_rx_eq_mode {DFE}
dict set params IF_COUNT "1"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "1"

1
fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl
View File

@ -104,6 +104,7 @@ set eth_xcvr_rx_eq_mode {DFE}
dict set params IF_COUNT "1"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "1"

2
fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
View File

@ -55,6 +55,7 @@ module fpga #
// Structural configuration
parameter IF_COUNT = 1,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 1,
@ -1150,6 +1151,7 @@ fpga_core #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),

2
fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
View File

@ -55,6 +55,7 @@ module fpga_core #
// Structural configuration
parameter IF_COUNT = 1,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_TS_WIDTH = 96,
@ -894,6 +895,7 @@ mqnic_core_pcie_us #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),

3
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile
View File

@ -137,6 +137,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# Structural configuration
export PARAM_IF_COUNT ?= 1
export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLOCK_PIPELINE ?= 1
@ -241,6 +242,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -323,6 +325,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

1
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -584,6 +584,7 @@ def test_fpga_core(request):
# Structural configuration
parameters['IF_COUNT'] = 1
parameters['PORTS_PER_IF'] = 1
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
# PTP configuration
parameters['PTP_CLOCK_PIPELINE'] = 1

1
fpga/mqnic/ExaNIC_X10/fpga/fpga/config.tcl
View File

@ -90,6 +90,7 @@ dict set params RELEASE_INFO [format "32'h%08x" $release_info]
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"

2
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v
View File

@ -55,6 +55,7 @@ module fpga #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 0,
@ -1024,6 +1025,7 @@ fpga_core #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),

2
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -55,6 +55,7 @@ module fpga_core #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_TS_WIDTH = 96,
@ -874,6 +875,7 @@ mqnic_core_pcie_us #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),

3
fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/Makefile
View File

@ -137,6 +137,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# Structural configuration
export PARAM_IF_COUNT ?= 2
export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLOCK_PIPELINE ?= 0
@ -241,6 +242,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -323,6 +325,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

1
fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -572,6 +572,7 @@ def test_fpga_core(request):
# Structural configuration
parameters['IF_COUNT'] = 2
parameters['PORTS_PER_IF'] = 1
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
# PTP configuration
parameters['PTP_CLOCK_PIPELINE'] = 0

1
fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/config.tcl
View File

@ -99,6 +99,7 @@ set eth_xcvr_rx_eq_mode {DFE}
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"

1
fpga/mqnic/ExaNIC_X25/fpga_25g/fpga_10g/config.tcl
View File

@ -99,6 +99,7 @@ set eth_xcvr_rx_eq_mode {DFE}
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"

2
fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga.v
View File

@ -55,6 +55,7 @@ module fpga #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 0,
@ -1053,6 +1054,7 @@ fpga_core #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),

2
fpga/mqnic/ExaNIC_X25/fpga_25g/rtl/fpga_core.v
View File

@ -55,6 +55,7 @@ module fpga_core #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_TS_WIDTH = 96,
@ -951,6 +952,7 @@ mqnic_core_pcie_us #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),

3
fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile
View File

@ -137,6 +137,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# Structural configuration
export PARAM_IF_COUNT ?= 2
export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLOCK_PIPELINE ?= 0
@ -241,6 +242,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -323,6 +325,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

1
fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -581,6 +581,7 @@ def test_fpga_core(request):
# Structural configuration
parameters['IF_COUNT'] = 2
parameters['PORTS_PER_IF'] = 1
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
# PTP configuration
parameters['PTP_CLOCK_PIPELINE'] = 0

1
fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl
View File

@ -95,6 +95,7 @@ dict set params RELEASE_INFO [format "32'h%08x" $release_info]
dict set params IF_COUNT "1"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"

2
fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v
View File

@ -55,6 +55,7 @@ module fpga #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 0,
@ -1305,6 +1306,7 @@ fpga_core #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),

2
fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
View File

@ -55,6 +55,7 @@ module fpga_core #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_TS_WIDTH = 96,
@ -752,6 +753,7 @@ mqnic_core_pcie_us #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),

3
fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
View File

@ -136,6 +136,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# Structural configuration
export PARAM_IF_COUNT ?= 2
export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLOCK_PIPELINE ?= 0
@ -240,6 +241,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -322,6 +324,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

1
fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -581,6 +581,7 @@ def test_fpga_core(request):
# Structural configuration
parameters['IF_COUNT'] = 2
parameters['PORTS_PER_IF'] = 1
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
# PTP configuration
parameters['PTP_CLOCK_PIPELINE'] = 0

1
fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/config.tcl
View File

@ -106,6 +106,7 @@ dict set params RELEASE_INFO [format "32'h%08x" $release_info]
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"

1
fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/config.tcl
View File

@ -106,6 +106,7 @@ dict set params RELEASE_INFO [format "32'h%08x" $release_info]
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"

2
fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga.v
View File

@ -55,6 +55,7 @@ module fpga #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 0,
@ -839,6 +840,7 @@ fpga_core #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),

2
fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v
View File

@ -55,6 +55,7 @@ module fpga_core #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_TS_WIDTH = 96,
@ -907,6 +908,7 @@ mqnic_core_pcie_s10 #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),

3
fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile
View File

@ -134,6 +134,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# Structural configuration
export PARAM_IF_COUNT ?= 2
export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLOCK_PIPELINE ?= 0
@ -241,6 +242,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -326,6 +328,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

1
fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -576,6 +576,7 @@ def test_fpga_core(request):
# Structural configuration
parameters['IF_COUNT'] = 2
parameters['PORTS_PER_IF'] = 1
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
# PTP configuration
parameters['PTP_CLOCK_PIPELINE'] = 0

1
fpga/mqnic/VCU108/fpga_10g/fpga/config.tcl
View File

@ -95,6 +95,7 @@ dict set params RELEASE_INFO [format "32'h%08x" $release_info]
dict set params IF_COUNT "1"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"

2
fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v
View File

@ -55,6 +55,7 @@ module fpga #
// Structural configuration
parameter IF_COUNT = 1,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 0,
@ -1116,6 +1117,7 @@ fpga_core #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),

2
fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -55,6 +55,7 @@ module fpga_core #
// Structural configuration
parameter IF_COUNT = 1,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_TS_WIDTH = 96,
@ -937,6 +938,7 @@ mqnic_core_pcie_us #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),

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