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Fix sign error

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This commit is contained in:
Alex Forencich 2018-10-02 00:26:37 -07:00
parent c4da967da9
commit 0928bf80bb
1 changed files with 4 additions and 6 deletions
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10
tb/pcie.py
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@ -2305,8 +2305,8 @@ class MemoryEndpoint(Endpoint):
yield self.send(cpl) yield self.send(cpl)
m += cpl_dw_length; m += cpl_dw_length;
n += cpl_dw_length*4 + (addr&3) n += cpl_dw_length*4 - (addr&3)
addr += cpl_dw_length*4 + (addr&3) addr += cpl_dw_length*4 - (addr&3)
else: else:
# logging # logging
@ -3296,8 +3296,6 @@ class RootComplex(Switch):
# perform operation # perform operation
addr = tlp.address addr = tlp.address
offset = 0 offset = 0
start_offset = None
mask = tlp.first_be
# check for 4k boundary crossing # check for 4k boundary crossing
if tlp.length*4 > 0x1000 - (addr & 0xfff): if tlp.length*4 > 0x1000 - (addr & 0xfff):
@ -3334,8 +3332,8 @@ class RootComplex(Switch):
yield self.send(cpl) yield self.send(cpl)
m += cpl_dw_length; m += cpl_dw_length;
n += cpl_dw_length*4 + (addr&3) n += cpl_dw_length*4 - (addr&3)
addr += cpl_dw_length*4 + (addr&3) addr += cpl_dw_length*4 - (addr&3)
else: else:
# logging # logging