diff --git a/rtl/dma_if_pcie_us_rd.v b/rtl/dma_if_pcie_us_rd.v index 87bc9796a..1b6daf1e1 100644 --- a/rtl/dma_if_pcie_us_rd.v +++ b/rtl/dma_if_pcie_us_rd.v @@ -314,6 +314,7 @@ reg finish_tag; reg [3:0] first_be; reg [3:0] last_be; reg [10:0] dword_count; +reg req_last_tlp; reg [PCIE_ADDR_WIDTH-1:0] req_pcie_addr; reg [PCIE_ADDR_WIDTH-1:0] req_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, req_pcie_addr_next; @@ -586,6 +587,7 @@ always @* begin // crosses 4k boundary req_tlp_count_next = 13'h1000 - req_pcie_addr_reg[11:0]; dword_count = 11'h400 - req_pcie_addr_reg[11:2]; + req_last_tlp = req_pcie_addr_plus_op_count[11:0] == 0; // optimized req_pcie_addr = req_addr_reg + req_tlp_count_next req_pcie_addr[PCIE_ADDR_WIDTH-1:12] = req_pcie_addr_reg[PCIE_ADDR_WIDTH-1:12]+1; req_pcie_addr[11:0] = 12'd0; @@ -593,6 +595,7 @@ always @* begin // does not cross 4k boundary, send one TLP req_tlp_count_next = req_op_count_reg; dword_count = (req_op_count_reg + req_pcie_addr_reg[1:0] + 3) >> 2; + req_last_tlp = 1'b1; // optimized req_pcie_addr = req_addr_reg + req_tlp_count_next req_pcie_addr[PCIE_ADDR_WIDTH-1:12] = req_pcie_addr_reg[PCIE_ADDR_WIDTH-1:12]; req_pcie_addr[11:0] = req_pcie_addr_reg[11:0] + req_op_count_reg; @@ -603,6 +606,7 @@ always @* begin // crosses 4k boundary req_tlp_count_next = 13'h1000 - req_pcie_addr_reg[11:0]; dword_count = 11'h400 - req_pcie_addr_reg[11:2]; + req_last_tlp = 1'b0; // optimized req_pcie_addr = req_addr_reg + req_tlp_count_next req_pcie_addr[PCIE_ADDR_WIDTH-1:12] = req_pcie_addr_reg[PCIE_ADDR_WIDTH-1:12]+1; req_pcie_addr[11:0] = 12'd0; @@ -610,6 +614,7 @@ always @* begin // does not cross 4k boundary, send one TLP req_tlp_count_next = {max_read_request_size_dw_reg, 2'b00} - req_pcie_addr_reg[1:0]; dword_count = max_read_request_size_dw_reg; + req_last_tlp = 1'b0; // optimized req_pcie_addr = req_addr_reg + req_tlp_count_next req_pcie_addr[PCIE_ADDR_WIDTH-1:12] = req_pcie_addr_reg[PCIE_ADDR_WIDTH-1:12]; req_pcie_addr[11:0] = {req_pcie_addr_reg[11:2] + max_read_request_size_dw_reg, 2'b00}; @@ -668,14 +673,14 @@ always @* begin tlp_cmd_addr_next = req_addr_reg; tlp_cmd_pcie_tag_next = new_tag; - tlp_cmd_last_next = req_op_count_next == 0; + tlp_cmd_last_next = req_last_tlp; tlp_cmd_valid_next = 1'b1; op_table_read_start_ptr = tlp_cmd_op_tag_reg; - op_table_read_start_commit = req_op_count_next == 0; + op_table_read_start_commit = req_last_tlp; op_table_read_start_en = 1'b1; - if (req_op_count_next != 0) begin + if (!req_last_tlp) begin req_state_next = REQ_STATE_START; end else begin s_axis_read_desc_ready_next = 1'b0; @@ -711,14 +716,14 @@ always @* begin tlp_cmd_addr_next = req_addr_reg; tlp_cmd_pcie_tag_next = new_tag; - tlp_cmd_last_next = req_op_count_next == 0; + tlp_cmd_last_next = req_last_tlp; tlp_cmd_valid_next = 1'b1; op_table_read_start_ptr = tlp_cmd_op_tag_reg; - op_table_read_start_commit = req_op_count_next == 0; + op_table_read_start_commit = req_last_tlp; op_table_read_start_en = 1'b1; - if (req_op_count_next != 0) begin + if (!req_last_tlp) begin req_state_next = REQ_STATE_START; end else begin s_axis_read_desc_ready_next = 1'b0; diff --git a/rtl/pcie_us_axi_dma_rd.v b/rtl/pcie_us_axi_dma_rd.v index 4bbf8cc11..bd03d5cd4 100644 --- a/rtl/pcie_us_axi_dma_rd.v +++ b/rtl/pcie_us_axi_dma_rd.v @@ -324,6 +324,7 @@ reg finish_tag; reg [3:0] first_be; reg [3:0] last_be; reg [10:0] dword_count; +reg req_last_tlp; reg [PCIE_ADDR_WIDTH-1:0] req_pcie_addr; reg [PCIE_ADDR_WIDTH-1:0] req_pcie_addr_reg = {PCIE_ADDR_WIDTH{1'b0}}, req_pcie_addr_next; @@ -628,6 +629,7 @@ always @* begin // crosses 4k boundary req_tlp_count_next = 13'h1000 - req_pcie_addr_reg[11:0]; dword_count = 11'h400 - req_pcie_addr_reg[11:2]; + req_last_tlp = req_pcie_addr_plus_op_count[11:0] == 0; // optimized req_pcie_addr = req_addr_reg + req_tlp_count_next req_pcie_addr[PCIE_ADDR_WIDTH-1:12] = req_pcie_addr_reg[PCIE_ADDR_WIDTH-1:12]+1; req_pcie_addr[11:0] = 12'd0; @@ -635,6 +637,7 @@ always @* begin // does not cross 4k boundary, send one TLP req_tlp_count_next = req_op_count_reg; dword_count = (req_op_count_reg + req_pcie_addr_reg[1:0] + 3) >> 2; + req_last_tlp = 1'b1; // optimized req_pcie_addr = req_addr_reg + req_tlp_count_next req_pcie_addr[PCIE_ADDR_WIDTH-1:12] = req_pcie_addr_reg[PCIE_ADDR_WIDTH-1:12]; req_pcie_addr[11:0] = req_pcie_addr_reg[11:0] + req_op_count_reg; @@ -645,6 +648,7 @@ always @* begin // crosses 4k boundary req_tlp_count_next = 13'h1000 - req_pcie_addr_reg[11:0]; dword_count = 11'h400 - req_pcie_addr_reg[11:2]; + req_last_tlp = 1'b0; // optimized req_pcie_addr = req_addr_reg + req_tlp_count_next req_pcie_addr[PCIE_ADDR_WIDTH-1:12] = req_pcie_addr_reg[PCIE_ADDR_WIDTH-1:12]+1; req_pcie_addr[11:0] = 12'd0; @@ -652,6 +656,7 @@ always @* begin // does not cross 4k boundary, send one TLP req_tlp_count_next = {max_read_request_size_dw_reg, 2'b00}-req_pcie_addr_reg[1:0]; dword_count = max_read_request_size_dw_reg; + req_last_tlp = 1'b0; // optimized req_pcie_addr = req_addr_reg + req_tlp_count_next req_pcie_addr[PCIE_ADDR_WIDTH-1:12] = req_pcie_addr_reg[PCIE_ADDR_WIDTH-1:12]; req_pcie_addr[11:0] = {req_pcie_addr_reg[11:2] + max_read_request_size_dw_reg, 2'b00}; @@ -710,14 +715,14 @@ always @* begin tlp_cmd_addr_next = req_axi_addr_reg; tlp_cmd_pcie_tag_next = new_tag; - tlp_cmd_last_next = req_op_count_next == 0; + tlp_cmd_last_next = req_last_tlp; tlp_cmd_valid_next = 1'b1; op_table_read_start_ptr = tlp_cmd_op_tag_reg; - op_table_read_start_commit = req_op_count_next == 0; + op_table_read_start_commit = req_last_tlp; op_table_read_start_en = 1'b1; - if (req_op_count_next != 0) begin + if (!req_last_tlp) begin req_state_next = REQ_STATE_START; end else begin s_axis_read_desc_ready_next = 1'b0; @@ -753,14 +758,14 @@ always @* begin tlp_cmd_addr_next = req_axi_addr_reg; tlp_cmd_pcie_tag_next = new_tag; - tlp_cmd_last_next = req_op_count_next == 0; + tlp_cmd_last_next = req_last_tlp; tlp_cmd_valid_next = 1'b1; op_table_read_start_ptr = tlp_cmd_op_tag_reg; - op_table_read_start_commit = req_op_count_next == 0; + op_table_read_start_commit = req_last_tlp; op_table_read_start_en = 1'b1; - if (req_op_count_next != 0) begin + if (!req_last_tlp) begin req_state_next = REQ_STATE_START; end else begin s_axis_read_desc_ready_next = 1'b0;