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Fix signal widths

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This commit is contained in:
Alex Forencich 2019-12-29 16:45:32 -08:00
parent 3690fdeb7d
commit 0955a4101f
10 changed files with 260 additions and 260 deletions
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52
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v
View File

@ -1378,33 +1378,33 @@ wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
dma_if_mux #
(

52
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -1378,33 +1378,33 @@ wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
dma_if_mux #
(

52
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -1283,33 +1283,33 @@ wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
dma_if_mux #
(

52
fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v
View File

@ -1283,33 +1283,33 @@ wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
dma_if_mux #
(

52
fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -1304,33 +1304,33 @@ wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
dma_if_mux #
(

52
fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v
View File

@ -1292,33 +1292,33 @@ wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
dma_if_mux #
(

52
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v
View File

@ -1378,33 +1378,33 @@ wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
dma_if_mux #
(

52
fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -1283,33 +1283,33 @@ wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
dma_if_mux #
(

52
fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -1304,33 +1304,33 @@ wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
dma_if_mux #
(

52
fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v
View File

@ -1292,33 +1292,33 @@ wire pcie_data_dma_write_desc_ready;
wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag;
wire pcie_data_dma_write_desc_status_valid;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel;
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready;
wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid;
wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready;
dma_if_mux #
(