diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v index 895576479..00fed5e14 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v @@ -1378,33 +1378,33 @@ wire pcie_data_dma_write_desc_ready; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire pcie_data_dma_write_desc_status_valid; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; dma_if_mux # ( diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index 7f1100013..3484d11e9 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -1378,33 +1378,33 @@ wire pcie_data_dma_write_desc_ready; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire pcie_data_dma_write_desc_status_valid; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; dma_if_mux # ( diff --git a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v index d735a209e..09cfd6fb1 100644 --- a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -1283,33 +1283,33 @@ wire pcie_data_dma_write_desc_ready; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire pcie_data_dma_write_desc_status_valid; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; dma_if_mux # ( diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v index edd0e0acb..10e7d02b5 100644 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v @@ -1283,33 +1283,33 @@ wire pcie_data_dma_write_desc_ready; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire pcie_data_dma_write_desc_status_valid; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; dma_if_mux # ( diff --git a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v index 5cca33019..4dfb2813f 100644 --- a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v @@ -1304,33 +1304,33 @@ wire pcie_data_dma_write_desc_ready; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire pcie_data_dma_write_desc_status_valid; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; dma_if_mux # ( diff --git a/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v index 91d0049dd..829e48cb9 100644 --- a/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v @@ -1292,33 +1292,33 @@ wire pcie_data_dma_write_desc_ready; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire pcie_data_dma_write_desc_status_valid; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; dma_if_mux # ( diff --git a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v index 6c9ffeef1..9cca87d2f 100644 --- a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v @@ -1378,33 +1378,33 @@ wire pcie_data_dma_write_desc_ready; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire pcie_data_dma_write_desc_status_valid; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; dma_if_mux # ( diff --git a/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v b/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v index da0a7980f..fedd4f8d9 100644 --- a/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -1283,33 +1283,33 @@ wire pcie_data_dma_write_desc_ready; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire pcie_data_dma_write_desc_status_valid; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; dma_if_mux # ( diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v index ed4cec912..e451cdee6 100644 --- a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v @@ -1304,33 +1304,33 @@ wire pcie_data_dma_write_desc_ready; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire pcie_data_dma_write_desc_status_valid; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; dma_if_mux # ( diff --git a/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v index aaec8b925..52d836ba7 100644 --- a/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v @@ -1292,33 +1292,33 @@ wire pcie_data_dma_write_desc_ready; wire [PCIE_DMA_TAG_WIDTH-2:0] pcie_data_dma_write_desc_status_tag; wire pcie_data_dma_write_desc_status_valid; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] ctrl_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ctrl_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] ctrl_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ctrl_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ctrl_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] ctrl_dma_ram_rd_resp_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_wr_cmd_sel; -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; -wire [SEG_COUNT*RAM_SEL_WIDTH-2:0] data_dma_ram_rd_cmd_sel; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; -wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_wr_cmd_sel; +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] data_dma_ram_wr_cmd_be; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_wr_cmd_addr; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_wr_cmd_data; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_wr_cmd_ready; +wire [SEG_COUNT*(RAM_SEL_WIDTH-1)-1:0] data_dma_ram_rd_cmd_sel; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] data_dma_ram_rd_cmd_addr; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_cmd_ready; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] data_dma_ram_rd_resp_data; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_valid; +wire [SEG_COUNT-1:0] data_dma_ram_rd_resp_ready; dma_if_mux # (