mirror of
https://github.com/corundum/corundum.git
synced 2025-01-16 08:12:53 +08:00
Rework 7132 parametrization
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
1b29a88b18
commit
0986d1e901
@ -31,22 +31,27 @@ THE SOFTWARE.
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/*
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* FPGA top-level module
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*/
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module fpga (
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module fpga #
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(
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parameter QUAD_CNT = 17,
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parameter CH_CNT = QUAD_CNT*4
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)
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(
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/*
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* Clock: 156.25MHz
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*/
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input wire [1:0] refclk_user_p,
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input wire [1:0] refclk_user_n,
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input wire [1:0] refclk_user_p,
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input wire [1:0] refclk_user_n,
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/*
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* Ethernet: QSFP28
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*/
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input wire [67:0] eth_gt_ch_rx_p,
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input wire [67:0] eth_gt_ch_rx_n,
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output wire [67:0] eth_gt_ch_tx_p,
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output wire [67:0] eth_gt_ch_tx_n,
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input wire [16:0] eth_gt_pri_refclk_p,
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input wire [16:0] eth_gt_pri_refclk_n
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input wire [CH_CNT-1:0] eth_gt_ch_rx_p,
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input wire [CH_CNT-1:0] eth_gt_ch_rx_n,
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output wire [CH_CNT-1:0] eth_gt_ch_tx_p,
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output wire [CH_CNT-1:0] eth_gt_ch_tx_n,
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input wire [QUAD_CNT-1:0] eth_gt_pri_refclk_p,
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input wire [QUAD_CNT-1:0] eth_gt_pri_refclk_n
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);
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genvar n;
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@ -161,9 +166,6 @@ sync_reset_125mhz_inst (
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);
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// XGMII 10G PHY
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parameter QUAD_CNT = 17;
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parameter CH_CNT = QUAD_CNT*4;
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wire [CH_CNT-1:0] eth_tx_clk;
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wire [CH_CNT-1:0] eth_tx_rst;
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wire [CH_CNT*64-1:0] eth_txd;
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@ -290,160 +290,16 @@ always @(posedge clk) begin
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end
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end
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assign eth_txd[1*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[1*8 +: 8] = 8'hff;
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assign eth_txd[2*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[2*8 +: 8] = 8'hff;
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assign eth_txd[3*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[3*8 +: 8] = 8'hff;
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assign eth_txd[4*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[4*8 +: 8] = 8'hff;
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assign eth_txd[5*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[5*8 +: 8] = 8'hff;
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assign eth_txd[6*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[6*8 +: 8] = 8'hff;
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assign eth_txd[7*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[7*8 +: 8] = 8'hff;
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assign eth_txd[8*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[8*8 +: 8] = 8'hff;
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assign eth_txd[9*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[9*8 +: 8] = 8'hff;
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assign eth_txd[10*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[10*8 +: 8] = 8'hff;
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assign eth_txd[11*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[11*8 +: 8] = 8'hff;
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assign eth_txd[12*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[12*8 +: 8] = 8'hff;
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assign eth_txd[13*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[13*8 +: 8] = 8'hff;
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assign eth_txd[14*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[14*8 +: 8] = 8'hff;
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assign eth_txd[15*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[15*8 +: 8] = 8'hff;
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assign eth_txd[16*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[16*8 +: 8] = 8'hff;
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assign eth_txd[17*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[17*8 +: 8] = 8'hff;
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assign eth_txd[18*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[18*8 +: 8] = 8'hff;
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assign eth_txd[19*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[19*8 +: 8] = 8'hff;
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assign eth_txd[10*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[10*8 +: 8] = 8'hff;
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assign eth_txd[11*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[11*8 +: 8] = 8'hff;
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assign eth_txd[12*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[12*8 +: 8] = 8'hff;
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assign eth_txd[13*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[13*8 +: 8] = 8'hff;
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assign eth_txd[14*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[14*8 +: 8] = 8'hff;
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assign eth_txd[15*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[15*8 +: 8] = 8'hff;
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assign eth_txd[16*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[16*8 +: 8] = 8'hff;
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assign eth_txd[17*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[17*8 +: 8] = 8'hff;
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assign eth_txd[18*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[18*8 +: 8] = 8'hff;
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assign eth_txd[19*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[19*8 +: 8] = 8'hff;
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assign eth_txd[20*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[20*8 +: 8] = 8'hff;
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assign eth_txd[21*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[21*8 +: 8] = 8'hff;
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assign eth_txd[22*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[22*8 +: 8] = 8'hff;
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assign eth_txd[23*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[23*8 +: 8] = 8'hff;
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assign eth_txd[24*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[24*8 +: 8] = 8'hff;
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assign eth_txd[25*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[25*8 +: 8] = 8'hff;
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assign eth_txd[26*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[26*8 +: 8] = 8'hff;
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assign eth_txd[27*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[27*8 +: 8] = 8'hff;
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assign eth_txd[28*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[28*8 +: 8] = 8'hff;
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assign eth_txd[29*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[29*8 +: 8] = 8'hff;
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assign eth_txd[30*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[30*8 +: 8] = 8'hff;
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assign eth_txd[31*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[31*8 +: 8] = 8'hff;
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assign eth_txd[32*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[32*8 +: 8] = 8'hff;
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assign eth_txd[33*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[33*8 +: 8] = 8'hff;
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assign eth_txd[34*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[34*8 +: 8] = 8'hff;
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assign eth_txd[35*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[35*8 +: 8] = 8'hff;
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assign eth_txd[36*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[36*8 +: 8] = 8'hff;
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assign eth_txd[37*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[37*8 +: 8] = 8'hff;
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assign eth_txd[38*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[38*8 +: 8] = 8'hff;
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assign eth_txd[39*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[39*8 +: 8] = 8'hff;
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assign eth_txd[40*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[40*8 +: 8] = 8'hff;
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assign eth_txd[41*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[41*8 +: 8] = 8'hff;
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assign eth_txd[42*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[42*8 +: 8] = 8'hff;
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assign eth_txd[43*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[43*8 +: 8] = 8'hff;
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assign eth_txd[44*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[44*8 +: 8] = 8'hff;
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assign eth_txd[45*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[45*8 +: 8] = 8'hff;
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assign eth_txd[46*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[46*8 +: 8] = 8'hff;
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assign eth_txd[47*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[47*8 +: 8] = 8'hff;
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assign eth_txd[48*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[48*8 +: 8] = 8'hff;
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assign eth_txd[49*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[49*8 +: 8] = 8'hff;
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assign eth_txd[50*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[50*8 +: 8] = 8'hff;
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assign eth_txd[51*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[51*8 +: 8] = 8'hff;
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assign eth_txd[52*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[52*8 +: 8] = 8'hff;
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assign eth_txd[53*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[53*8 +: 8] = 8'hff;
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assign eth_txd[54*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[54*8 +: 8] = 8'hff;
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assign eth_txd[55*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[55*8 +: 8] = 8'hff;
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assign eth_txd[56*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[56*8 +: 8] = 8'hff;
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assign eth_txd[57*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[57*8 +: 8] = 8'hff;
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assign eth_txd[58*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[58*8 +: 8] = 8'hff;
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assign eth_txd[59*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[59*8 +: 8] = 8'hff;
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assign eth_txd[60*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[60*8 +: 8] = 8'hff;
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assign eth_txd[61*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[61*8 +: 8] = 8'hff;
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assign eth_txd[62*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[62*8 +: 8] = 8'hff;
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assign eth_txd[63*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[63*8 +: 8] = 8'hff;
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assign eth_txd[64*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[64*8 +: 8] = 8'hff;
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assign eth_txd[65*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[65*8 +: 8] = 8'hff;
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assign eth_txd[66*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[66*8 +: 8] = 8'hff;
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assign eth_txd[67*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[67*8 +: 8] = 8'hff;
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generate
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genvar n;
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for (n = 1; n < CH_CNT; n = n + 1) begin
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assign eth_txd[n*64 +: 64] = 64'h0707070707070707;
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assign eth_txc[n*8 +: 8] = 8'hff;
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end
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endgenerate
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eth_mac_10g_fifo #(
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.ENABLE_PADDING(1),
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@ -60,12 +60,13 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
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VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
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# module parameters
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#export PARAM_A := value
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export PARAM_QUAD_CNT := 17
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export PARAM_CH_CNT := $(shell expr $(PARAM_QUAD_CNT) \* 4)
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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# COMPILE_ARGS += -P $(TOPLEVEL).A=$(PARAM_A)
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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VERILOG_SOURCES += iverilog_dump.v
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@ -74,7 +75,7 @@ ifeq ($(SIM), icarus)
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
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# COMPILE_ARGS += -GA=$(PARAM_A)
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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@ -202,7 +202,8 @@ def test_fpga_core(request):
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parameters = {}
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# parameters['A'] = val
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parameters['QUAD_CNT'] = 17
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parameters['CH_CNT'] = parameters['QUAD_CNT']*4
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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@ -31,17 +31,19 @@ THE SOFTWARE.
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/*
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* Testbench top-level module
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*/
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module test_fpga_core ();
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module test_fpga_core #
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(
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parameter QUAD_CNT = 17,
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parameter CH_CNT = QUAD_CNT*4
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)
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(
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input wire clk,
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input wire rst
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);
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genvar n;
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wire clk;
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wire rst;
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// XGMII 10G PHY
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parameter QUAD_CNT = 17;
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parameter CH_CNT = QUAD_CNT*4;
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wire [CH_CNT-1:0] eth_tx_clk;
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wire [CH_CNT-1:0] eth_tx_rst;
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wire [CH_CNT*64-1:0] eth_txd;
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@ -77,7 +79,9 @@ end
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endgenerate
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fpga_core
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fpga_core #(
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.CH_CNT(CH_CNT)
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)
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core_inst (
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/*
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* Clock: 156.25 MHz
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