From 09af3eb8828fa08e6a3d7eddb064997a3211246d Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 13 Nov 2023 21:38:20 -0800 Subject: [PATCH] fpga/mqnic/DK_DEV_1SDX_P_A: Mege 25G into 100G for DK-DEV-1SDX-P-A Signed-off-by: Alex Forencich --- .../fpga_100g/{fpga => fpga_100g}/Makefile | 0 .../fpga_100g/{fpga => fpga_100g}/config.tcl | 3 + .../Makefile | 0 .../config.tcl | 3 + .../{fpga_25g => fpga_100g}/fpga_10g/Makefile | 0 .../fpga_10g/config.tcl | 5 +- .../fpga => fpga_100g/fpga_25g}/Makefile | 0 .../fpga => fpga_100g/fpga_25g}/config.tcl | 5 +- .../{fpga_25g => fpga_100g}/ip/10g/mac.tcl | 0 .../ip/25g/mac_rsfec.tcl | 0 .../rtl/eth_mac_quad_wrapper.v | 382 +-- .../DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v | 336 ++- .../DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v | 22 +- .../fpga_100g/tb/fpga_core/test_fpga_core.v | 85 +- fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/README.md | 22 - fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/app | 1 - .../fpga_25g/common/quartus_pro.mk | 188 -- fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga.qsf | 1425 ---------- fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga.sdc | 125 - .../fpga_25g/ip/iopll_etile_ptp.tcl | 304 --- .../DK_DEV_1SDX_P_A/fpga_25g/ip/pcie.tcl | 2294 ----------------- .../DK_DEV_1SDX_P_A/fpga_25g/ip/ref_div.tcl | 61 - .../fpga_25g/ip/reset_release.tcl | 52 - fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/lib | 1 - .../DK_DEV_1SDX_P_A/fpga_25g/rtl/axis_fifo.v | 565 ---- .../mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/common | 1 - .../mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga.v | 1625 ------------ .../DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v | 1288 --------- .../fpga_25g/rtl/sync_signal.v | 62 - .../DK_DEV_1SDX_P_A/fpga_25g/rtl/xcvr_ctrl.v | 268 -- .../fpga_25g/tb/fpga_core/Makefile | 256 -- .../fpga_25g/tb/fpga_core/mqnic.py | 1 - .../fpga_25g/tb/fpga_core/test_fpga_core.py | 756 ------ 33 files changed, 386 insertions(+), 9750 deletions(-) rename fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/{fpga => fpga_100g}/Makefile (100%) rename fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/{fpga => fpga_100g}/config.tcl (99%) rename fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/{fpga_app_dma_bench => fpga_100g_app_dma_bench}/Makefile (100%) rename fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/{fpga_app_dma_bench => fpga_100g_app_dma_bench}/config.tcl (99%) rename fpga/mqnic/DK_DEV_1SDX_P_A/{fpga_25g => fpga_100g}/fpga_10g/Makefile (100%) rename fpga/mqnic/DK_DEV_1SDX_P_A/{fpga_25g => fpga_100g}/fpga_10g/config.tcl (99%) rename fpga/mqnic/DK_DEV_1SDX_P_A/{fpga_25g/fpga => fpga_100g/fpga_25g}/Makefile (100%) rename fpga/mqnic/DK_DEV_1SDX_P_A/{fpga_25g/fpga => fpga_100g/fpga_25g}/config.tcl (99%) rename fpga/mqnic/DK_DEV_1SDX_P_A/{fpga_25g => fpga_100g}/ip/10g/mac.tcl (100%) rename fpga/mqnic/DK_DEV_1SDX_P_A/{fpga_25g => fpga_100g}/ip/25g/mac_rsfec.tcl (100%) rename fpga/mqnic/DK_DEV_1SDX_P_A/{fpga_25g => fpga_100g}/rtl/eth_mac_quad_wrapper.v (56%) delete mode 100644 fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/README.md delete mode 120000 fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/app delete mode 100644 fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/common/quartus_pro.mk delete mode 100644 fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga.qsf delete mode 100644 fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga.sdc delete mode 100644 fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/iopll_etile_ptp.tcl delete mode 100644 fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/pcie.tcl delete mode 100644 fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/ref_div.tcl delete mode 100644 fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/reset_release.tcl delete mode 120000 fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/lib delete mode 100644 fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/axis_fifo.v delete mode 120000 fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/common delete mode 100644 fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga.v delete mode 100644 fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v delete mode 100644 fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/sync_signal.v delete mode 100644 fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/xcvr_ctrl.v delete mode 100644 fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/Makefile delete mode 120000 fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/mqnic.py delete mode 100644 fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/test_fpga_core.py diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g/Makefile similarity index 100% rename from fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga/Makefile rename to fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g/Makefile diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga/config.tcl b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g/config.tcl similarity index 99% rename from fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga/config.tcl rename to fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g/config.tcl index 060dc1b65..434192b9b 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g/config.tcl @@ -53,6 +53,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params MAC_100G "1" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g_app_dma_bench/Makefile similarity index 100% rename from fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_app_dma_bench/Makefile rename to fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g_app_dma_bench/Makefile diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g_app_dma_bench/config.tcl similarity index 99% rename from fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_app_dma_bench/config.tcl rename to fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g_app_dma_bench/config.tcl index bfcbc61f8..6d2c050be 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g_app_dma_bench/config.tcl @@ -53,6 +53,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params MAC_100G "1" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_10g/Makefile similarity index 100% rename from fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga_10g/Makefile rename to fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_10g/Makefile diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_10g/config.tcl similarity index 99% rename from fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga_10g/config.tcl rename to fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_10g/config.tcl index ad3865aea..6e840d8a8 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_10g/config.tcl @@ -53,6 +53,10 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params MAC_100G "0" +dict set params MAC_RSFEC "0" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" @@ -145,7 +149,6 @@ dict set params AXIS_ETH_TX_FIFO_PIPELINE "2" dict set params AXIS_ETH_TX_TS_PIPELINE "0" dict set params AXIS_ETH_RX_PIPELINE "0" dict set params AXIS_ETH_RX_FIFO_PIPELINE "2" -dict set params MAC_RSFEC "0" # Statistics counter subsystem dict set params STAT_ENABLE "1" diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_25g/Makefile similarity index 100% rename from fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga/Makefile rename to fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_25g/Makefile diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga/config.tcl b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_25g/config.tcl similarity index 99% rename from fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga/config.tcl rename to fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_25g/config.tcl index 099ba4cb6..4483c3618 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_25g/config.tcl @@ -53,6 +53,10 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params MAC_100G "0" +dict set params MAC_RSFEC "1" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" @@ -145,7 +149,6 @@ dict set params AXIS_ETH_TX_FIFO_PIPELINE "2" dict set params AXIS_ETH_TX_TS_PIPELINE "0" dict set params AXIS_ETH_RX_PIPELINE "0" dict set params AXIS_ETH_RX_FIFO_PIPELINE "2" -dict set params MAC_RSFEC "1" # Statistics counter subsystem dict set params STAT_ENABLE "1" diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/10g/mac.tcl b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/ip/10g/mac.tcl similarity index 100% rename from fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/10g/mac.tcl rename to fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/ip/10g/mac.tcl diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/25g/mac_rsfec.tcl b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/ip/25g/mac_rsfec.tcl similarity index 100% rename from fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/25g/mac_rsfec.tcl rename to fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/ip/25g/mac_rsfec.tcl diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/eth_mac_quad_wrapper.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/eth_mac_quad_wrapper.v similarity index 56% rename from fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/eth_mac_quad_wrapper.v rename to fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/eth_mac_quad_wrapper.v index bde677cb8..02b9e8614 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/eth_mac_quad_wrapper.v +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/eth_mac_quad_wrapper.v @@ -33,6 +33,7 @@ THE SOFTWARE. */ module eth_mac_quad_wrapper # ( + parameter N_CH = 4, parameter PTP_TS_WIDTH = 96, parameter PTP_TAG_WIDTH = 8, parameter DATA_WIDTH = 64, @@ -42,175 +43,56 @@ module eth_mac_quad_wrapper # parameter MAC_RSFEC = 0 ) ( - input wire ctrl_clk, - input wire ctrl_rst, + input wire ctrl_clk, + input wire ctrl_rst, - output wire [3:0] tx_serial_data_p, - output wire [3:0] tx_serial_data_n, - input wire [3:0] rx_serial_data_p, - input wire [3:0] rx_serial_data_n, - input wire ref_clk, - input wire ptp_sample_clk, + output wire [3:0] tx_serial_data_p, + output wire [3:0] tx_serial_data_n, + input wire [3:0] rx_serial_data_p, + input wire [3:0] rx_serial_data_n, + input wire ref_clk, + input wire ptp_sample_clk, - output wire mac_1_tx_clk, - output wire mac_1_tx_rst, + output wire [N_CH-1:0] mac_tx_clk, + output wire [N_CH-1:0] mac_tx_rst, - output wire mac_1_tx_ptp_clk, - output wire mac_1_tx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_1_tx_ptp_time, + output wire [N_CH-1:0] mac_tx_ptp_clk, + output wire [N_CH-1:0] mac_tx_ptp_rst, + input wire [N_CH*PTP_TS_WIDTH-1:0] mac_tx_ptp_time, - output wire [PTP_TS_WIDTH-1:0] mac_1_tx_ptp_ts, - output wire [PTP_TAG_WIDTH-1:0] mac_1_tx_ptp_ts_tag, - output wire mac_1_tx_ptp_ts_valid, + output wire [N_CH*PTP_TS_WIDTH-1:0] mac_tx_ptp_ts, + output wire [N_CH*PTP_TAG_WIDTH-1:0] mac_tx_ptp_ts_tag, + output wire [N_CH-1:0] mac_tx_ptp_ts_valid, - input wire [DATA_WIDTH-1:0] mac_1_tx_axis_tdata, - input wire [KEEP_WIDTH-1:0] mac_1_tx_axis_tkeep, - input wire mac_1_tx_axis_tvalid, - output wire mac_1_tx_axis_tready, - input wire mac_1_tx_axis_tlast, - input wire [TX_USER_WIDTH-1:0] mac_1_tx_axis_tuser, + input wire [N_CH*DATA_WIDTH-1:0] mac_tx_axis_tdata, + input wire [N_CH*KEEP_WIDTH-1:0] mac_tx_axis_tkeep, + input wire [N_CH-1:0] mac_tx_axis_tvalid, + output wire [N_CH-1:0] mac_tx_axis_tready, + input wire [N_CH-1:0] mac_tx_axis_tlast, + input wire [N_CH*TX_USER_WIDTH-1:0] mac_tx_axis_tuser, - output wire mac_1_tx_status, - input wire mac_1_tx_lfc_req, - input wire [7:0] mac_1_tx_pfc_req, + output wire [N_CH*1-1:0] mac_tx_status, + input wire [N_CH*1-1:0] mac_tx_lfc_req, + input wire [N_CH*8-1:0] mac_tx_pfc_req, - output wire mac_1_rx_clk, - output wire mac_1_rx_rst, + output wire [N_CH-1:0] mac_rx_clk, + output wire [N_CH-1:0] mac_rx_rst, - output wire mac_1_rx_ptp_clk, - output wire mac_1_rx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_1_rx_ptp_time, + output wire [N_CH-1:0] mac_rx_ptp_clk, + output wire [N_CH-1:0] mac_rx_ptp_rst, + input wire [N_CH*PTP_TS_WIDTH-1:0] mac_rx_ptp_time, - output wire [DATA_WIDTH-1:0] mac_1_rx_axis_tdata, - output wire [KEEP_WIDTH-1:0] mac_1_rx_axis_tkeep, - output wire mac_1_rx_axis_tvalid, - output wire mac_1_rx_axis_tlast, - output wire [RX_USER_WIDTH-1:0] mac_1_rx_axis_tuser, + output wire [N_CH*DATA_WIDTH-1:0] mac_rx_axis_tdata, + output wire [N_CH*KEEP_WIDTH-1:0] mac_rx_axis_tkeep, + output wire [N_CH-1:0] mac_rx_axis_tvalid, + output wire [N_CH-1:0] mac_rx_axis_tlast, + output wire [N_CH*RX_USER_WIDTH-1:0] mac_rx_axis_tuser, - output wire mac_1_rx_status, - output wire mac_1_rx_lfc_req, - output wire [7:0] mac_1_rx_pfc_req, - - output wire mac_2_tx_clk, - output wire mac_2_tx_rst, - - output wire mac_2_tx_ptp_clk, - output wire mac_2_tx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_2_tx_ptp_time, - - output wire [PTP_TS_WIDTH-1:0] mac_2_tx_ptp_ts, - output wire [PTP_TAG_WIDTH-1:0] mac_2_tx_ptp_ts_tag, - output wire mac_2_tx_ptp_ts_valid, - - input wire [DATA_WIDTH-1:0] mac_2_tx_axis_tdata, - input wire [KEEP_WIDTH-1:0] mac_2_tx_axis_tkeep, - input wire mac_2_tx_axis_tvalid, - output wire mac_2_tx_axis_tready, - input wire mac_2_tx_axis_tlast, - input wire [TX_USER_WIDTH-1:0] mac_2_tx_axis_tuser, - - output wire mac_2_tx_status, - input wire mac_2_tx_lfc_req, - input wire [7:0] mac_2_tx_pfc_req, - - output wire mac_2_rx_clk, - output wire mac_2_rx_rst, - - output wire mac_2_rx_ptp_clk, - output wire mac_2_rx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_2_rx_ptp_time, - - output wire [DATA_WIDTH-1:0] mac_2_rx_axis_tdata, - output wire [KEEP_WIDTH-1:0] mac_2_rx_axis_tkeep, - output wire mac_2_rx_axis_tvalid, - output wire mac_2_rx_axis_tlast, - output wire [RX_USER_WIDTH-1:0] mac_2_rx_axis_tuser, - - output wire mac_2_rx_status, - output wire mac_2_rx_lfc_req, - output wire [7:0] mac_2_rx_pfc_req, - - output wire mac_3_tx_clk, - output wire mac_3_tx_rst, - - output wire mac_3_tx_ptp_clk, - output wire mac_3_tx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_3_tx_ptp_time, - - output wire [PTP_TS_WIDTH-1:0] mac_3_tx_ptp_ts, - output wire [PTP_TAG_WIDTH-1:0] mac_3_tx_ptp_ts_tag, - output wire mac_3_tx_ptp_ts_valid, - - input wire [DATA_WIDTH-1:0] mac_3_tx_axis_tdata, - input wire [KEEP_WIDTH-1:0] mac_3_tx_axis_tkeep, - input wire mac_3_tx_axis_tvalid, - output wire mac_3_tx_axis_tready, - input wire mac_3_tx_axis_tlast, - input wire [TX_USER_WIDTH-1:0] mac_3_tx_axis_tuser, - - output wire mac_3_tx_status, - input wire mac_3_tx_lfc_req, - input wire [7:0] mac_3_tx_pfc_req, - - output wire mac_3_rx_clk, - output wire mac_3_rx_rst, - - output wire mac_3_rx_ptp_clk, - output wire mac_3_rx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_3_rx_ptp_time, - - output wire [DATA_WIDTH-1:0] mac_3_rx_axis_tdata, - output wire [KEEP_WIDTH-1:0] mac_3_rx_axis_tkeep, - output wire mac_3_rx_axis_tvalid, - output wire mac_3_rx_axis_tlast, - output wire [RX_USER_WIDTH-1:0] mac_3_rx_axis_tuser, - - output wire mac_3_rx_status, - output wire mac_3_rx_lfc_req, - output wire [7:0] mac_3_rx_pfc_req, - - output wire mac_4_tx_clk, - output wire mac_4_tx_rst, - - output wire mac_4_tx_ptp_clk, - output wire mac_4_tx_ptp_rst, - input wire [PTP_TS_WIDTH-1:0] mac_4_tx_ptp_time, - - output wire [PTP_TS_WIDTH-1:0] mac_4_tx_ptp_ts, - output wire [PTP_TAG_WIDTH-1:0] mac_4_tx_ptp_ts_tag, - output wire mac_4_tx_ptp_ts_valid, - - input wire [DATA_WIDTH-1:0] mac_4_tx_axis_tdata, - input wire [KEEP_WIDTH-1:0] mac_4_tx_axis_tkeep, - input wire mac_4_tx_axis_tvalid, - output wire mac_4_tx_axis_tready, - input wire mac_4_tx_axis_tlast, - input wire [TX_USER_WIDTH-1:0] mac_4_tx_axis_tuser, - - output wire mac_4_tx_status, - input wire mac_4_tx_lfc_req, - input wire [7:0] mac_4_tx_pfc_req, - - output wire mac_4_rx_clk, - output wire mac_4_rx_rst, - - output wire mac_4_rx_ptp_clk, - output wire mac_4_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] mac_4_rx_ptp_time, - - output wire [DATA_WIDTH-1:0] mac_4_rx_axis_tdata, - output wire [KEEP_WIDTH-1:0] mac_4_rx_axis_tkeep, - output wire mac_4_rx_axis_tvalid, - output wire mac_4_rx_axis_tlast, - output wire [RX_USER_WIDTH-1:0] mac_4_rx_axis_tuser, - - output wire mac_4_rx_status, - output wire mac_4_rx_lfc_req, - output wire [7:0] mac_4_rx_pfc_req + output wire [N_CH*1-1:0] mac_rx_status, + output wire [N_CH*1-1:0] mac_rx_lfc_req, + output wire [N_CH*8-1:0] mac_rx_pfc_req ); -parameter N_CH = 4; - wire [5:0] mac_pll_clk_d64; wire [5:0] mac_pll_clk_d66; wire [5:0] mac_rec_clk_d64; @@ -218,16 +100,6 @@ wire [5:0] mac_rec_clk_d66; wire [N_CH-1:0] mac_tx_pll_locked; -wire [N_CH-1:0] mac_rx_clk; -wire [N_CH-1:0] mac_rx_rst; -wire [N_CH-1:0] mac_tx_clk; -wire [N_CH-1:0] mac_tx_rst; - -wire [N_CH-1:0] mac_rx_ptp_clk; -wire [N_CH-1:0] mac_rx_ptp_rst; -wire [N_CH-1:0] mac_tx_ptp_clk; -wire [N_CH-1:0] mac_tx_ptp_rst; - wire [N_CH*19-1:0] xcvr_reconfig_address; wire [N_CH-1:0] xcvr_reconfig_read; wire [N_CH-1:0] xcvr_reconfig_write; @@ -489,180 +361,26 @@ end endgenerate -wire [N_CH*DATA_WIDTH-1:0] mac_rx_axis_tdata; -wire [N_CH*KEEP_WIDTH-1:0] mac_rx_axis_tkeep; -wire [N_CH-1:0] mac_rx_axis_tvalid; -wire [N_CH-1:0] mac_rx_axis_tlast; -wire [N_CH*RX_USER_WIDTH-1:0] mac_rx_axis_tuser; - -wire [N_CH*DATA_WIDTH-1:0] mac_tx_axis_tdata; -wire [N_CH*KEEP_WIDTH-1:0] mac_tx_axis_tkeep; -wire [N_CH-1:0] mac_tx_axis_tvalid; -wire [N_CH-1:0] mac_tx_axis_tready; -wire [N_CH-1:0] mac_tx_axis_tlast; -wire [N_CH*TX_USER_WIDTH-1:0] mac_tx_axis_tuser; - assign mac_tx_clk[3:0] = {4{mac_pll_clk_d64[4]}}; assign mac_rx_clk[3:0] = mac_tx_clk[3:0]; assign mac_tx_ptp_clk[3:0] = mac_pll_clk_d66[3:0]; assign mac_rx_ptp_clk[3:0] = mac_rec_clk_d66[3:0]; -assign mac_1_tx_clk = mac_tx_clk[0]; -assign mac_1_tx_rst = mac_tx_rst[0]; +assign mac_ptp_tx_tod = mac_tx_ptp_time; +assign mac_ptp_rx_tod = mac_rx_ptp_time; -assign mac_1_tx_ptp_clk = mac_tx_ptp_clk[0]; -assign mac_1_tx_ptp_rst = mac_tx_ptp_rst[0]; -assign mac_ptp_tx_tod[0*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_1_tx_ptp_time; +assign mac_tx_ptp_ts = mac_ptp_ets; +assign mac_tx_ptp_ts_tag = mac_ptp_ets_fp; +assign mac_tx_ptp_ts_valid = mac_ptp_ets_valid; -assign mac_1_tx_ptp_ts = mac_ptp_ets[0*PTP_TS_WIDTH +: PTP_TS_WIDTH]; -assign mac_1_tx_ptp_ts_tag = mac_ptp_ets_fp[0*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]; -assign mac_1_tx_ptp_ts_valid = mac_ptp_ets_valid[0]; +assign mac_tx_status = mac_tx_lanes_stable; +assign mac_tx_pause = mac_tx_lfc_req; +assign mac_tx_pfc = mac_tx_pfc_req; -assign mac_tx_axis_tdata[0*DATA_WIDTH +: DATA_WIDTH] = mac_1_tx_axis_tdata; -assign mac_tx_axis_tkeep[0*KEEP_WIDTH +: KEEP_WIDTH] = mac_1_tx_axis_tkeep; -assign mac_tx_axis_tvalid[0] = mac_1_tx_axis_tvalid; -assign mac_1_tx_axis_tready = mac_tx_axis_tready[0]; -assign mac_tx_axis_tlast[0] = mac_1_tx_axis_tlast; -assign mac_tx_axis_tuser[0*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_1_tx_axis_tuser; - -assign mac_1_tx_status = mac_tx_lanes_stable[0*1 +: 1]; -assign mac_tx_pause[0*1 +: 1] = mac_1_tx_lfc_req; -assign mac_tx_pfc[0*8 +: 8] = mac_1_tx_pfc_req; - -assign mac_1_rx_clk = mac_rx_clk[0]; -assign mac_1_rx_rst = mac_rx_rst[0]; - -assign mac_1_rx_ptp_clk = mac_rx_ptp_clk[0]; -assign mac_1_rx_ptp_rst = mac_rx_ptp_rst[0]; -assign mac_ptp_rx_tod[0*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_1_rx_ptp_time; - -assign mac_1_rx_axis_tdata = mac_rx_axis_tdata[0*DATA_WIDTH +: DATA_WIDTH]; -assign mac_1_rx_axis_tkeep = mac_rx_axis_tkeep[0*KEEP_WIDTH +: KEEP_WIDTH]; -assign mac_1_rx_axis_tvalid = mac_rx_axis_tvalid[0]; -assign mac_1_rx_axis_tlast = mac_rx_axis_tlast[0]; -assign mac_1_rx_axis_tuser = mac_rx_axis_tuser[0*RX_USER_WIDTH +: RX_USER_WIDTH]; - -assign mac_1_rx_status = mac_rx_pcs_ready[0*1 +: 1]; -assign mac_1_rx_lfc_req = mac_rx_pause[0*1 +: 1]; -assign mac_1_rx_pfc_req = mac_rx_pfc[0*8 +: 8]; - -assign mac_2_tx_clk = mac_tx_clk[1]; -assign mac_2_tx_rst = mac_tx_rst[1]; - -assign mac_2_tx_ptp_clk = mac_tx_ptp_clk[1]; -assign mac_2_tx_ptp_rst = mac_tx_ptp_rst[1]; -assign mac_ptp_tx_tod[1*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_2_tx_ptp_time; - -assign mac_2_tx_ptp_ts = mac_ptp_ets[1*PTP_TS_WIDTH +: PTP_TS_WIDTH]; -assign mac_2_tx_ptp_ts_tag = mac_ptp_ets_fp[1*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]; -assign mac_2_tx_ptp_ts_valid = mac_ptp_ets_valid[1]; - -assign mac_tx_axis_tdata[1*DATA_WIDTH +: DATA_WIDTH] = mac_2_tx_axis_tdata; -assign mac_tx_axis_tkeep[1*KEEP_WIDTH +: KEEP_WIDTH] = mac_2_tx_axis_tkeep; -assign mac_tx_axis_tvalid[1] = mac_2_tx_axis_tvalid; -assign mac_2_tx_axis_tready = mac_tx_axis_tready[1]; -assign mac_tx_axis_tlast[1] = mac_2_tx_axis_tlast; -assign mac_tx_axis_tuser[1*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_2_tx_axis_tuser; - -assign mac_2_tx_status = mac_tx_lanes_stable[1*1 +: 1]; -assign mac_tx_pause[1*1 +: 1] = mac_2_tx_lfc_req; -assign mac_tx_pfc[1*8 +: 8] = mac_2_tx_pfc_req; - -assign mac_2_rx_clk = mac_rx_clk[1]; -assign mac_2_rx_rst = mac_rx_rst[1]; - -assign mac_2_rx_ptp_clk = mac_rx_ptp_clk[1]; -assign mac_2_rx_ptp_rst = mac_rx_ptp_rst[1]; -assign mac_ptp_rx_tod[1*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_2_rx_ptp_time; - -assign mac_2_rx_axis_tdata = mac_rx_axis_tdata[1*DATA_WIDTH +: DATA_WIDTH]; -assign mac_2_rx_axis_tkeep = mac_rx_axis_tkeep[1*KEEP_WIDTH +: KEEP_WIDTH]; -assign mac_2_rx_axis_tvalid = mac_rx_axis_tvalid[1]; -assign mac_2_rx_axis_tlast = mac_rx_axis_tlast[1]; -assign mac_2_rx_axis_tuser = mac_rx_axis_tuser[1*RX_USER_WIDTH +: RX_USER_WIDTH]; - -assign mac_2_rx_status = mac_rx_pcs_ready[1*1 +: 1]; -assign mac_2_rx_lfc_req = mac_rx_pause[1*1 +: 1]; -assign mac_2_rx_pfc_req = mac_rx_pfc[1*8 +: 8]; - -assign mac_3_tx_clk = mac_tx_clk[2]; -assign mac_3_tx_rst = mac_tx_rst[2]; - -assign mac_3_tx_ptp_clk = mac_tx_ptp_clk[2]; -assign mac_3_tx_ptp_rst = mac_tx_ptp_rst[2]; -assign mac_ptp_tx_tod[2*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_3_tx_ptp_time; - -assign mac_3_tx_ptp_ts = mac_ptp_ets[2*PTP_TS_WIDTH +: PTP_TS_WIDTH]; -assign mac_3_tx_ptp_ts_tag = mac_ptp_ets_fp[2*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]; -assign mac_3_tx_ptp_ts_valid = mac_ptp_ets_valid[2]; - -assign mac_tx_axis_tdata[2*DATA_WIDTH +: DATA_WIDTH] = mac_3_tx_axis_tdata; -assign mac_tx_axis_tkeep[2*KEEP_WIDTH +: KEEP_WIDTH] = mac_3_tx_axis_tkeep; -assign mac_tx_axis_tvalid[2] = mac_3_tx_axis_tvalid; -assign mac_3_tx_axis_tready = mac_tx_axis_tready[2]; -assign mac_tx_axis_tlast[2] = mac_3_tx_axis_tlast; -assign mac_tx_axis_tuser[2*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_3_tx_axis_tuser; - -assign mac_3_tx_status = mac_tx_lanes_stable[2*1 +: 1]; -assign mac_tx_pause[2*1 +: 1] = mac_3_tx_lfc_req; -assign mac_tx_pfc[2*8 +: 8] = mac_3_tx_pfc_req; - -assign mac_3_rx_clk = mac_rx_clk[2]; -assign mac_3_rx_rst = mac_rx_rst[2]; - -assign mac_3_rx_ptp_clk = mac_rx_ptp_clk[2]; -assign mac_3_rx_ptp_rst = mac_rx_ptp_rst[2]; -assign mac_ptp_rx_tod[2*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_3_rx_ptp_time; - -assign mac_3_rx_axis_tdata = mac_rx_axis_tdata[2*DATA_WIDTH +: DATA_WIDTH]; -assign mac_3_rx_axis_tkeep = mac_rx_axis_tkeep[2*KEEP_WIDTH +: KEEP_WIDTH]; -assign mac_3_rx_axis_tvalid = mac_rx_axis_tvalid[2]; -assign mac_3_rx_axis_tlast = mac_rx_axis_tlast[2]; -assign mac_3_rx_axis_tuser = mac_rx_axis_tuser[2*RX_USER_WIDTH +: RX_USER_WIDTH]; - -assign mac_3_rx_status = mac_rx_pcs_ready[2*1 +: 1]; -assign mac_3_rx_lfc_req = mac_rx_pause[2*1 +: 1]; -assign mac_3_rx_pfc_req = mac_rx_pfc[2*8 +: 8]; - -assign mac_4_tx_clk = mac_tx_clk[3]; -assign mac_4_tx_rst = mac_tx_rst[3]; - -assign mac_4_tx_ptp_clk = mac_tx_ptp_clk[3]; -assign mac_4_tx_ptp_rst = mac_tx_ptp_rst[3]; -assign mac_ptp_tx_tod[3*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_4_tx_ptp_time; - -assign mac_4_tx_ptp_ts = mac_ptp_ets[3*PTP_TS_WIDTH +: PTP_TS_WIDTH]; -assign mac_4_tx_ptp_ts_tag = mac_ptp_ets_fp[3*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]; -assign mac_4_tx_ptp_ts_valid = mac_ptp_ets_valid[3]; - -assign mac_tx_axis_tdata[3*DATA_WIDTH +: DATA_WIDTH] = mac_4_tx_axis_tdata; -assign mac_tx_axis_tkeep[3*KEEP_WIDTH +: KEEP_WIDTH] = mac_4_tx_axis_tkeep; -assign mac_tx_axis_tvalid[3] = mac_4_tx_axis_tvalid; -assign mac_4_tx_axis_tready = mac_tx_axis_tready[3]; -assign mac_tx_axis_tlast[3] = mac_4_tx_axis_tlast; -assign mac_tx_axis_tuser[3*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_4_tx_axis_tuser; - -assign mac_4_tx_status = mac_tx_lanes_stable[3*1 +: 1]; -assign mac_tx_pause[3*1 +: 1] = mac_4_tx_lfc_req; -assign mac_tx_pfc[3*8 +: 8] = mac_4_tx_pfc_req; - -assign mac_4_rx_clk = mac_rx_clk[3]; -assign mac_4_rx_rst = mac_rx_rst[3]; - -assign mac_4_rx_ptp_clk = mac_rx_ptp_clk[3]; -assign mac_4_rx_ptp_rst = mac_rx_ptp_rst[3]; -assign mac_ptp_rx_tod[3*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_4_rx_ptp_time; - -assign mac_4_rx_axis_tdata = mac_rx_axis_tdata[3*DATA_WIDTH +: DATA_WIDTH]; -assign mac_4_rx_axis_tkeep = mac_rx_axis_tkeep[3*KEEP_WIDTH +: KEEP_WIDTH]; -assign mac_4_rx_axis_tvalid = mac_rx_axis_tvalid[3]; -assign mac_4_rx_axis_tlast = mac_rx_axis_tlast[3]; -assign mac_4_rx_axis_tuser = mac_rx_axis_tuser[3*RX_USER_WIDTH +: RX_USER_WIDTH]; - -assign mac_4_rx_status = mac_rx_pcs_ready[3*1 +: 1]; -assign mac_4_rx_lfc_req = mac_rx_pause[3*1 +: 1]; -assign mac_4_rx_pfc_req = mac_rx_pfc[3*8 +: 8]; +assign mac_rx_status = mac_rx_pcs_ready; +assign mac_rx_lfc_req = mac_rx_pause; +assign mac_rx_pfc_req = mac_rx_pfc; generate diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v index 90aa09b68..c9bfcf588 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v @@ -24,6 +24,10 @@ module fpga # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter MAC_100G = 1, + parameter MAC_RSFEC = 1, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -404,7 +408,7 @@ pcie pcie_hip_inst ( // QSFP28 interfaces localparam QSFP_CNT = 2; -localparam CH_CNT = QSFP_CNT; +localparam CH_CNT = MAC_100G ? QSFP_CNT : QSFP_CNT*4; wire [CH_CNT-1:0] qsfp_mac_tx_clk; wire [CH_CNT-1:0] qsfp_mac_tx_rst; @@ -416,7 +420,10 @@ wire [CH_CNT-1:0] qsfp_mac_tx_axis_tready; wire [CH_CNT-1:0] qsfp_mac_tx_axis_tlast; wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfp_mac_tx_axis_tuser; +wire [CH_CNT-1:0] qsfp_mac_tx_ptp_clk; +wire [CH_CNT-1:0] qsfp_mac_tx_ptp_rst; wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_tx_ptp_time; + wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_tx_ptp_ts; wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfp_mac_tx_ptp_ts_tag; wire [CH_CNT-1:0] qsfp_mac_tx_ptp_ts_valid; @@ -434,117 +441,269 @@ wire [CH_CNT-1:0] qsfp_mac_rx_axis_tvalid; wire [CH_CNT-1:0] qsfp_mac_rx_axis_tlast; wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfp_mac_rx_axis_tuser; +wire [CH_CNT-1:0] qsfp_mac_rx_ptp_clk; +wire [CH_CNT-1:0] qsfp_mac_rx_ptp_rst; wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_rx_ptp_time; wire [CH_CNT-1:0] qsfp_mac_rx_status; wire [CH_CNT-1:0] qsfp_mac_rx_lfc_req; wire [CH_CNT*8-1:0] qsfp_mac_rx_pfc_req; -// QSFP1 -assign qsfp_mac_rx_clk[0*1 +: 1] = qsfp_mac_tx_clk[0*1 +: 1]; -assign qsfp_mac_rx_rst[0*1 +: 1] = qsfp_mac_tx_rst[0*1 +: 1]; +generate -eth_mac_wrapper #( - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_TAG_WIDTH(PTP_TAG_WIDTH), - .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) -) -qsfp1_mac_inst ( - .ctrl_clk(clk_100mhz), - .ctrl_rst(rst_100mhz), +if (MAC_100G) begin - .tx_serial_data_p({qsfp1_tx_p[3], qsfp1_tx_p[1], qsfp1_tx_p[2], qsfp1_tx_p[0]}), - // .tx_serial_data_n({qsfp1_tx_n[3], qsfp1_tx_n[1], qsfp1_tx_n[2], qsfp1_tx_n[0]}), - .rx_serial_data_p({qsfp1_rx_p[3], qsfp1_rx_p[1], qsfp1_rx_p[2], qsfp1_rx_p[0]}), - // .rx_serial_data_n({qsfp1_rx_n[3], qsfp1_rx_n[1], qsfp1_rx_n[2], qsfp1_rx_n[0]}), - .ref_clk(clk_156p25m_qsfp0_p), + // QSFP1 + assign qsfp_mac_tx_ptp_clk[0*1 +: 1] = qsfp_mac_tx_clk[0*1 +: 1]; + assign qsfp_mac_tx_ptp_rst[0*1 +: 1] = qsfp_mac_tx_rst[0*1 +: 1]; + assign qsfp_mac_rx_clk[0*1 +: 1] = qsfp_mac_tx_clk[0*1 +: 1]; + assign qsfp_mac_rx_rst[0*1 +: 1] = qsfp_mac_tx_rst[0*1 +: 1]; + assign qsfp_mac_rx_ptp_clk[0*1 +: 1] = qsfp_mac_tx_clk[0*1 +: 1]; + assign qsfp_mac_rx_ptp_rst[0*1 +: 1] = qsfp_mac_tx_rst[0*1 +: 1]; - .mac_clk(qsfp_mac_tx_clk[0 +: 1]), - .mac_rst(qsfp_mac_tx_rst[0 +: 1]), + eth_mac_wrapper #( + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_TAG_WIDTH(PTP_TAG_WIDTH), + .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) + ) + qsfp1_mac_inst ( + .ctrl_clk(clk_100mhz), + .ctrl_rst(rst_100mhz), - .mac_ptp_time(qsfp_mac_tx_ptp_time[0*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_serial_data_p({qsfp1_tx_p[3], qsfp1_tx_p[1], qsfp1_tx_p[2], qsfp1_tx_p[0]}), + // .tx_serial_data_n({qsfp1_tx_n[3], qsfp1_tx_n[1], qsfp1_tx_n[2], qsfp1_tx_n[0]}), + .rx_serial_data_p({qsfp1_rx_p[3], qsfp1_rx_p[1], qsfp1_rx_p[2], qsfp1_rx_p[0]}), + // .rx_serial_data_n({qsfp1_rx_n[3], qsfp1_rx_n[1], qsfp1_rx_n[2], qsfp1_rx_n[0]}), + .ref_clk(clk_156p25m_qsfp0_p), - .mac_tx_ptp_ts(qsfp_mac_tx_ptp_ts[0*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .mac_tx_ptp_ts_tag(qsfp_mac_tx_ptp_ts_tag[0*TX_TAG_WIDTH +: TX_TAG_WIDTH]), - .mac_tx_ptp_ts_valid(qsfp_mac_tx_ptp_ts_valid[0 +: 1]), + .mac_clk(qsfp_mac_tx_clk[0 +: 1]), + .mac_rst(qsfp_mac_tx_rst[0 +: 1]), - .mac_tx_axis_tdata(qsfp_mac_tx_axis_tdata[0*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), - .mac_tx_axis_tkeep(qsfp_mac_tx_axis_tkeep[0*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), - .mac_tx_axis_tvalid(qsfp_mac_tx_axis_tvalid[0 +: 1]), - .mac_tx_axis_tready(qsfp_mac_tx_axis_tready[0 +: 1]), - .mac_tx_axis_tlast(qsfp_mac_tx_axis_tlast[0 +: 1]), - .mac_tx_axis_tuser(qsfp_mac_tx_axis_tuser[0*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]), + .mac_ptp_time(qsfp_mac_tx_ptp_time[0*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .mac_tx_status(qsfp_mac_tx_status[0 +: 1]), - .mac_tx_lfc_req(qsfp_mac_tx_lfc_req[0 +: 1]), - .mac_tx_pfc_req(qsfp_mac_tx_pfc_req[0*8 +: 8]), + .mac_tx_ptp_ts(qsfp_mac_tx_ptp_ts[0*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .mac_tx_ptp_ts_tag(qsfp_mac_tx_ptp_ts_tag[0*TX_TAG_WIDTH +: TX_TAG_WIDTH]), + .mac_tx_ptp_ts_valid(qsfp_mac_tx_ptp_ts_valid[0 +: 1]), - .mac_rx_axis_tdata(qsfp_mac_rx_axis_tdata[0*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), - .mac_rx_axis_tkeep(qsfp_mac_rx_axis_tkeep[0*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), - .mac_rx_axis_tvalid(qsfp_mac_rx_axis_tvalid[0 +: 1]), - .mac_rx_axis_tlast(qsfp_mac_rx_axis_tlast[0 +: 1]), - .mac_rx_axis_tuser(qsfp_mac_rx_axis_tuser[0*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]), + .mac_tx_axis_tdata(qsfp_mac_tx_axis_tdata[0*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .mac_tx_axis_tkeep(qsfp_mac_tx_axis_tkeep[0*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .mac_tx_axis_tvalid(qsfp_mac_tx_axis_tvalid[0 +: 1]), + .mac_tx_axis_tready(qsfp_mac_tx_axis_tready[0 +: 1]), + .mac_tx_axis_tlast(qsfp_mac_tx_axis_tlast[0 +: 1]), + .mac_tx_axis_tuser(qsfp_mac_tx_axis_tuser[0*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]), - .mac_rx_status(qsfp_mac_rx_status[0 +: 1]), - .mac_rx_lfc_req(qsfp_mac_rx_lfc_req[0 +: 1]), - .mac_rx_pfc_req(qsfp_mac_rx_pfc_req[0*8 +: 8]) -); + .mac_tx_status(qsfp_mac_tx_status[0 +: 1]), + .mac_tx_lfc_req(qsfp_mac_tx_lfc_req[0 +: 1]), + .mac_tx_pfc_req(qsfp_mac_tx_pfc_req[0*8 +: 8]), -// QSFP2 -assign qsfp_mac_rx_clk[1*1 +: 1] = qsfp_mac_tx_clk[1*1 +: 1]; -assign qsfp_mac_rx_rst[1*1 +: 1] = qsfp_mac_tx_rst[1*1 +: 1]; + .mac_rx_axis_tdata(qsfp_mac_rx_axis_tdata[0*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .mac_rx_axis_tkeep(qsfp_mac_rx_axis_tkeep[0*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .mac_rx_axis_tvalid(qsfp_mac_rx_axis_tvalid[0 +: 1]), + .mac_rx_axis_tlast(qsfp_mac_rx_axis_tlast[0 +: 1]), + .mac_rx_axis_tuser(qsfp_mac_rx_axis_tuser[0*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]), -eth_mac_wrapper #( - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_TAG_WIDTH(PTP_TAG_WIDTH), - .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) -) -qsfp2_mac_inst ( - .ctrl_clk(clk_100mhz), - .ctrl_rst(rst_100mhz), + .mac_rx_status(qsfp_mac_rx_status[0 +: 1]), + .mac_rx_lfc_req(qsfp_mac_rx_lfc_req[0 +: 1]), + .mac_rx_pfc_req(qsfp_mac_rx_pfc_req[0*8 +: 8]) + ); - .tx_serial_data_p({qsfp2_tx_p[3], qsfp2_tx_p[1], qsfp2_tx_p[2], qsfp2_tx_p[0]}), - // .tx_serial_data_n({qsfp2_tx_n[3], qsfp2_tx_n[1], qsfp2_tx_n[2], qsfp2_tx_n[0]}), - .rx_serial_data_p({qsfp2_rx_p[3], qsfp2_rx_p[1], qsfp2_rx_p[2], qsfp2_rx_p[0]}), - // .rx_serial_data_n({qsfp2_rx_n[3], qsfp2_rx_n[1], qsfp2_rx_n[2], qsfp2_rx_n[0]}), - .ref_clk(clk_156p25m_qsfp0_p), + // QSFP2 + assign qsfp_mac_tx_ptp_clk[1*1 +: 1] = qsfp_mac_tx_clk[1*1 +: 1]; + assign qsfp_mac_tx_ptp_rst[1*1 +: 1] = qsfp_mac_tx_rst[1*1 +: 1]; + assign qsfp_mac_rx_clk[1*1 +: 1] = qsfp_mac_tx_clk[1*1 +: 1]; + assign qsfp_mac_rx_rst[1*1 +: 1] = qsfp_mac_tx_rst[1*1 +: 1]; + assign qsfp_mac_rx_ptp_clk[1*1 +: 1] = qsfp_mac_tx_clk[1*1 +: 1]; + assign qsfp_mac_rx_ptp_rst[1*1 +: 1] = qsfp_mac_tx_rst[1*1 +: 1]; - .mac_clk(qsfp_mac_tx_clk[1 +: 1]), - .mac_rst(qsfp_mac_tx_rst[1 +: 1]), + eth_mac_wrapper #( + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_TAG_WIDTH(PTP_TAG_WIDTH), + .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) + ) + qsfp2_mac_inst ( + .ctrl_clk(clk_100mhz), + .ctrl_rst(rst_100mhz), - .mac_ptp_time(qsfp_mac_tx_ptp_time[1*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_serial_data_p({qsfp2_tx_p[3], qsfp2_tx_p[1], qsfp2_tx_p[2], qsfp2_tx_p[0]}), + // .tx_serial_data_n({qsfp2_tx_n[3], qsfp2_tx_n[1], qsfp2_tx_n[2], qsfp2_tx_n[0]}), + .rx_serial_data_p({qsfp2_rx_p[3], qsfp2_rx_p[1], qsfp2_rx_p[2], qsfp2_rx_p[0]}), + // .rx_serial_data_n({qsfp2_rx_n[3], qsfp2_rx_n[1], qsfp2_rx_n[2], qsfp2_rx_n[0]}), + .ref_clk(clk_156p25m_qsfp0_p), - .mac_tx_ptp_ts(qsfp_mac_tx_ptp_ts[1*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .mac_tx_ptp_ts_tag(qsfp_mac_tx_ptp_ts_tag[1*TX_TAG_WIDTH +: TX_TAG_WIDTH]), - .mac_tx_ptp_ts_valid(qsfp_mac_tx_ptp_ts_valid[1 +: 1]), + .mac_clk(qsfp_mac_tx_clk[1 +: 1]), + .mac_rst(qsfp_mac_tx_rst[1 +: 1]), - .mac_tx_axis_tdata(qsfp_mac_tx_axis_tdata[1*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), - .mac_tx_axis_tkeep(qsfp_mac_tx_axis_tkeep[1*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), - .mac_tx_axis_tvalid(qsfp_mac_tx_axis_tvalid[1 +: 1]), - .mac_tx_axis_tready(qsfp_mac_tx_axis_tready[1 +: 1]), - .mac_tx_axis_tlast(qsfp_mac_tx_axis_tlast[1 +: 1]), - .mac_tx_axis_tuser(qsfp_mac_tx_axis_tuser[1*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]), + .mac_ptp_time(qsfp_mac_tx_ptp_time[1*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .mac_tx_status(qsfp_mac_tx_status[1 +: 1]), - .mac_tx_lfc_req(qsfp_mac_tx_lfc_req[1 +: 1]), - .mac_tx_pfc_req(qsfp_mac_tx_pfc_req[1*8 +: 8]), + .mac_tx_ptp_ts(qsfp_mac_tx_ptp_ts[1*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .mac_tx_ptp_ts_tag(qsfp_mac_tx_ptp_ts_tag[1*TX_TAG_WIDTH +: TX_TAG_WIDTH]), + .mac_tx_ptp_ts_valid(qsfp_mac_tx_ptp_ts_valid[1 +: 1]), - .mac_rx_axis_tdata(qsfp_mac_rx_axis_tdata[1*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), - .mac_rx_axis_tkeep(qsfp_mac_rx_axis_tkeep[1*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), - .mac_rx_axis_tvalid(qsfp_mac_rx_axis_tvalid[1 +: 1]), - .mac_rx_axis_tlast(qsfp_mac_rx_axis_tlast[1 +: 1]), - .mac_rx_axis_tuser(qsfp_mac_rx_axis_tuser[1*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]), + .mac_tx_axis_tdata(qsfp_mac_tx_axis_tdata[1*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .mac_tx_axis_tkeep(qsfp_mac_tx_axis_tkeep[1*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .mac_tx_axis_tvalid(qsfp_mac_tx_axis_tvalid[1 +: 1]), + .mac_tx_axis_tready(qsfp_mac_tx_axis_tready[1 +: 1]), + .mac_tx_axis_tlast(qsfp_mac_tx_axis_tlast[1 +: 1]), + .mac_tx_axis_tuser(qsfp_mac_tx_axis_tuser[1*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]), - .mac_rx_status(qsfp_mac_rx_status[1 +: 1]), - .mac_rx_lfc_req(qsfp_mac_rx_lfc_req[1 +: 1]), - .mac_rx_pfc_req(qsfp_mac_rx_pfc_req[1*8 +: 8]) -); + .mac_tx_status(qsfp_mac_tx_status[1 +: 1]), + .mac_tx_lfc_req(qsfp_mac_tx_lfc_req[1 +: 1]), + .mac_tx_pfc_req(qsfp_mac_tx_pfc_req[1*8 +: 8]), + + .mac_rx_axis_tdata(qsfp_mac_rx_axis_tdata[1*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .mac_rx_axis_tkeep(qsfp_mac_rx_axis_tkeep[1*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .mac_rx_axis_tvalid(qsfp_mac_rx_axis_tvalid[1 +: 1]), + .mac_rx_axis_tlast(qsfp_mac_rx_axis_tlast[1 +: 1]), + .mac_rx_axis_tuser(qsfp_mac_rx_axis_tuser[1*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]), + + .mac_rx_status(qsfp_mac_rx_status[1 +: 1]), + .mac_rx_lfc_req(qsfp_mac_rx_lfc_req[1 +: 1]), + .mac_rx_pfc_req(qsfp_mac_rx_pfc_req[1*8 +: 8]) + ); + +end else begin + + wire etile_iopll_locked; + wire etile_ptp_sample_clk; + + iopll_etile_ptp iopll_etile_ptp_inst ( + .rst (rst_100mhz), + .refclk (clk_100mhz), + .locked (etile_iopll_locked), + .outclk_0 (etile_ptp_sample_clk) + ); + + // QSFP1 + eth_mac_quad_wrapper #( + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_TAG_WIDTH(PTP_TAG_WIDTH), + .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), + .MAC_RSFEC(MAC_RSFEC) + ) + qsfp1_mac_inst ( + .ctrl_clk(clk_100mhz), + .ctrl_rst(rst_100mhz), + + .tx_serial_data_p({qsfp1_tx_p[3], qsfp1_tx_p[1], qsfp1_tx_p[2], qsfp1_tx_p[0]}), + // .tx_serial_data_n({qsfp1_tx_n[3], qsfp1_tx_n[1], qsfp1_tx_n[2], qsfp1_tx_n[0]}), + .rx_serial_data_p({qsfp1_rx_p[3], qsfp1_rx_p[1], qsfp1_rx_p[2], qsfp1_rx_p[0]}), + // .rx_serial_data_n({qsfp1_rx_n[3], qsfp1_rx_n[1], qsfp1_rx_n[2], qsfp1_rx_n[0]}), + .ref_clk(clk_156p25m_qsfp0_p), + .ptp_sample_clk(etile_ptp_sample_clk), + + .mac_tx_clk(qsfp_mac_tx_clk[0*4 +: 4*1]), + .mac_tx_rst(qsfp_mac_tx_rst[0*4 +: 4*1]), + + .mac_tx_ptp_clk(qsfp_mac_tx_ptp_clk[0*4 +: 4*1]), + .mac_tx_ptp_rst(qsfp_mac_tx_ptp_rst[0*4 +: 4*1]), + .mac_tx_ptp_time(qsfp_mac_tx_ptp_time[0*4*PTP_TS_WIDTH +: 4*PTP_TS_WIDTH]), + + .mac_tx_ptp_ts(qsfp_mac_tx_ptp_ts[0*4*PTP_TS_WIDTH +: 4*PTP_TS_WIDTH]), + .mac_tx_ptp_ts_tag(qsfp_mac_tx_ptp_ts_tag[0*4*TX_TAG_WIDTH +: 4*TX_TAG_WIDTH]), + .mac_tx_ptp_ts_valid(qsfp_mac_tx_ptp_ts_valid[0*4 +: 4*1]), + + .mac_tx_axis_tdata(qsfp_mac_tx_axis_tdata[0*4*AXIS_ETH_DATA_WIDTH +: 4*AXIS_ETH_DATA_WIDTH]), + .mac_tx_axis_tkeep(qsfp_mac_tx_axis_tkeep[0*4*AXIS_ETH_KEEP_WIDTH +: 4*AXIS_ETH_KEEP_WIDTH]), + .mac_tx_axis_tvalid(qsfp_mac_tx_axis_tvalid[0*4 +: 4*1]), + .mac_tx_axis_tready(qsfp_mac_tx_axis_tready[0*4 +: 4*1]), + .mac_tx_axis_tlast(qsfp_mac_tx_axis_tlast[0*4 +: 4*1]), + .mac_tx_axis_tuser(qsfp_mac_tx_axis_tuser[0*4*AXIS_ETH_TX_USER_WIDTH +: 4*AXIS_ETH_TX_USER_WIDTH]), + + .mac_tx_status(qsfp_mac_tx_status[0*4 +: 4*1]), + .mac_tx_lfc_req(qsfp_mac_tx_lfc_req[0*4 +: 4*1]), + .mac_tx_pfc_req(qsfp_mac_tx_pfc_req[0*4*8 +: 4*8]), + + .mac_rx_clk(qsfp_mac_rx_clk[0*4 +: 4*1]), + .mac_rx_rst(qsfp_mac_rx_rst[0*4 +: 4*1]), + + .mac_rx_ptp_clk(qsfp_mac_rx_ptp_clk[0*4 +: 4*1]), + .mac_rx_ptp_rst(qsfp_mac_rx_ptp_rst[0*4 +: 4*1]), + .mac_rx_ptp_time(qsfp_mac_rx_ptp_time[0*4*PTP_TS_WIDTH +: 4*PTP_TS_WIDTH]), + + .mac_rx_axis_tdata(qsfp_mac_rx_axis_tdata[0*4*AXIS_ETH_DATA_WIDTH +: 4*AXIS_ETH_DATA_WIDTH]), + .mac_rx_axis_tkeep(qsfp_mac_rx_axis_tkeep[0*4*AXIS_ETH_KEEP_WIDTH +: 4*AXIS_ETH_KEEP_WIDTH]), + .mac_rx_axis_tvalid(qsfp_mac_rx_axis_tvalid[0*4 +: 4*1]), + .mac_rx_axis_tlast(qsfp_mac_rx_axis_tlast[0*4 +: 4*1]), + .mac_rx_axis_tuser(qsfp_mac_rx_axis_tuser[0*4*AXIS_ETH_RX_USER_WIDTH +: 4*AXIS_ETH_RX_USER_WIDTH]), + + .mac_rx_status(qsfp_mac_rx_status[0*4 +: 4*1]), + .mac_rx_lfc_req(qsfp_mac_rx_lfc_req[0*4 +: 4*1]), + .mac_rx_pfc_req(qsfp_mac_rx_pfc_req[0*4*8 +: 4*8]) + ); + + // QSFP2 + eth_mac_quad_wrapper #( + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_TAG_WIDTH(PTP_TAG_WIDTH), + .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), + .MAC_RSFEC(MAC_RSFEC) + ) + qsfp2_mac_inst ( + .ctrl_clk(clk_100mhz), + .ctrl_rst(rst_100mhz), + + .tx_serial_data_p({qsfp2_tx_p[3], qsfp2_tx_p[1], qsfp2_tx_p[2], qsfp2_tx_p[0]}), + // .tx_serial_data_n({qsfp2_tx_n[3], qsfp2_tx_n[1], qsfp2_tx_n[2], qsfp2_tx_n[0]}), + .rx_serial_data_p({qsfp2_rx_p[3], qsfp2_rx_p[1], qsfp2_rx_p[2], qsfp2_rx_p[0]}), + // .rx_serial_data_n({qsfp2_rx_n[3], qsfp2_rx_n[1], qsfp2_rx_n[2], qsfp2_rx_n[0]}), + .ref_clk(clk_156p25m_qsfp0_p), + .ptp_sample_clk(etile_ptp_sample_clk), + + .mac_tx_clk(qsfp_mac_tx_clk[1*4 +: 4*1]), + .mac_tx_rst(qsfp_mac_tx_rst[1*4 +: 4*1]), + + .mac_tx_ptp_clk(qsfp_mac_tx_ptp_clk[1*4 +: 4*1]), + .mac_tx_ptp_rst(qsfp_mac_tx_ptp_rst[1*4 +: 4*1]), + .mac_tx_ptp_time(qsfp_mac_tx_ptp_time[1*4*PTP_TS_WIDTH +: 4*PTP_TS_WIDTH]), + + .mac_tx_ptp_ts(qsfp_mac_tx_ptp_ts[1*4*PTP_TS_WIDTH +: 4*PTP_TS_WIDTH]), + .mac_tx_ptp_ts_tag(qsfp_mac_tx_ptp_ts_tag[1*4*TX_TAG_WIDTH +: 4*TX_TAG_WIDTH]), + .mac_tx_ptp_ts_valid(qsfp_mac_tx_ptp_ts_valid[1*4 +: 4*1]), + + .mac_tx_axis_tdata(qsfp_mac_tx_axis_tdata[1*4*AXIS_ETH_DATA_WIDTH +: 4*AXIS_ETH_DATA_WIDTH]), + .mac_tx_axis_tkeep(qsfp_mac_tx_axis_tkeep[1*4*AXIS_ETH_KEEP_WIDTH +: 4*AXIS_ETH_KEEP_WIDTH]), + .mac_tx_axis_tvalid(qsfp_mac_tx_axis_tvalid[1*4 +: 4*1]), + .mac_tx_axis_tready(qsfp_mac_tx_axis_tready[1*4 +: 4*1]), + .mac_tx_axis_tlast(qsfp_mac_tx_axis_tlast[1*4 +: 4*1]), + .mac_tx_axis_tuser(qsfp_mac_tx_axis_tuser[1*4*AXIS_ETH_TX_USER_WIDTH +: 4*AXIS_ETH_TX_USER_WIDTH]), + + .mac_tx_status(qsfp_mac_tx_status[1*4 +: 4*1]), + .mac_tx_lfc_req(qsfp_mac_tx_lfc_req[1*4 +: 4*1]), + .mac_tx_pfc_req(qsfp_mac_tx_pfc_req[1*4*8 +: 4*8]), + + .mac_rx_clk(qsfp_mac_rx_clk[1*4 +: 4*1]), + .mac_rx_rst(qsfp_mac_rx_rst[1*4 +: 4*1]), + + .mac_rx_ptp_clk(qsfp_mac_rx_ptp_clk[1*4 +: 4*1]), + .mac_rx_ptp_rst(qsfp_mac_rx_ptp_rst[1*4 +: 4*1]), + .mac_rx_ptp_time(qsfp_mac_rx_ptp_time[1*4*PTP_TS_WIDTH +: 4*PTP_TS_WIDTH]), + + .mac_rx_axis_tdata(qsfp_mac_rx_axis_tdata[1*4*AXIS_ETH_DATA_WIDTH +: 4*AXIS_ETH_DATA_WIDTH]), + .mac_rx_axis_tkeep(qsfp_mac_rx_axis_tkeep[1*4*AXIS_ETH_KEEP_WIDTH +: 4*AXIS_ETH_KEEP_WIDTH]), + .mac_rx_axis_tvalid(qsfp_mac_rx_axis_tvalid[1*4 +: 4*1]), + .mac_rx_axis_tlast(qsfp_mac_rx_axis_tlast[1*4 +: 4*1]), + .mac_rx_axis_tuser(qsfp_mac_rx_axis_tuser[1*4*AXIS_ETH_RX_USER_WIDTH +: 4*AXIS_ETH_RX_USER_WIDTH]), + + .mac_rx_status(qsfp_mac_rx_status[1*4 +: 4*1]), + .mac_rx_lfc_req(qsfp_mac_rx_lfc_req[1*4 +: 4*1]), + .mac_rx_pfc_req(qsfp_mac_rx_pfc_req[1*4*8 +: 4*8]) + ); + +end + +endgenerate wire ptp_clk; wire ptp_rst; @@ -582,6 +741,7 @@ fpga_core #( // Board configuration .QSFP_CNT(QSFP_CNT), .CH_CNT(CH_CNT), + .PORT_GROUP_SIZE(MAC_100G ? 1 : 4), // Structural configuration .IF_COUNT(IF_COUNT), @@ -599,6 +759,8 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), + .PTP_SEPARATE_TX_CLOCK(MAC_100G ? 0 : 1), + .PTP_SEPARATE_RX_CLOCK(MAC_100G ? 0 : 1), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v index 4aa94c7f5..7843b74a5 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v @@ -27,6 +27,7 @@ module fpga_core # // Board configuration parameter QSFP_CNT = 2, parameter CH_CNT = QSFP_CNT, + parameter PORT_GROUP_SIZE = 4, // Structural configuration parameter IF_COUNT = 2, @@ -44,6 +45,8 @@ module fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, + parameter PTP_SEPARATE_TX_CLOCK = 0, + parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -228,7 +231,10 @@ module fpga_core # output wire [CH_CNT-1:0] qsfp_mac_tx_axis_tlast, output wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfp_mac_tx_axis_tuser, + input wire [CH_CNT-1:0] qsfp_mac_tx_ptp_clk, + input wire [CH_CNT-1:0] qsfp_mac_tx_ptp_rst, output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_tx_ptp_time, + input wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_tx_ptp_ts, input wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfp_mac_tx_ptp_ts_tag, input wire [CH_CNT-1:0] qsfp_mac_tx_ptp_ts_valid, @@ -246,6 +252,8 @@ module fpga_core # input wire [CH_CNT-1:0] qsfp_mac_rx_axis_tlast, input wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfp_mac_rx_axis_tuser, + input wire [CH_CNT-1:0] qsfp_mac_rx_ptp_clk, + input wire [CH_CNT-1:0] qsfp_mac_rx_ptp_rst, output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_rx_ptp_time, input wire [CH_CNT-1:0] qsfp_mac_rx_status, @@ -450,7 +458,7 @@ wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack; mqnic_port_map_mac_axis #( .MAC_COUNT(CH_CNT), .PORT_MASK(PORT_MASK), - .PORT_GROUP_SIZE(1), + .PORT_GROUP_SIZE(PORT_GROUP_SIZE), .IF_COUNT(IF_COUNT), .PORTS_PER_IF(PORTS_PER_IF), @@ -469,8 +477,8 @@ mqnic_port_map_mac_axis_inst ( .mac_tx_clk(qsfp_mac_tx_clk), .mac_tx_rst(qsfp_mac_tx_rst), - .mac_tx_ptp_clk(qsfp_mac_tx_clk), - .mac_tx_ptp_rst(qsfp_mac_tx_rst), + .mac_tx_ptp_clk(qsfp_mac_tx_ptp_clk), + .mac_tx_ptp_rst(qsfp_mac_tx_ptp_rst), .mac_tx_ptp_ts_96(qsfp_mac_tx_ptp_time), .mac_tx_ptp_ts_step(), @@ -496,8 +504,8 @@ mqnic_port_map_mac_axis_inst ( .mac_rx_clk(qsfp_mac_rx_clk), .mac_rx_rst(qsfp_mac_rx_rst), - .mac_rx_ptp_clk(qsfp_mac_rx_clk), - .mac_rx_ptp_rst(qsfp_mac_rx_rst), + .mac_rx_ptp_clk(qsfp_mac_rx_ptp_clk), + .mac_rx_ptp_rst(qsfp_mac_rx_ptp_rst), .mac_rx_ptp_ts_96(qsfp_mac_rx_ptp_time), .mac_rx_ptp_ts_step(), @@ -598,8 +606,8 @@ mqnic_core_pcie_ptile #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_TX_CLOCK(0), - .PTP_SEPARATE_RX_CLOCK(0), + .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK), + .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.v index 3e6a6a165..9937a4270 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.v +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.v @@ -46,6 +46,7 @@ module test_fpga_core # // Board configuration parameter QSFP_CNT = 2, parameter CH_CNT = QSFP_CNT, + parameter PORT_GROUP_SIZE = 2, // Structural configuration parameter IF_COUNT = 2, @@ -63,6 +64,8 @@ module test_fpga_core # parameter PTP_TS_WIDTH = 96, parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, + parameter PTP_SEPARATE_TX_CLOCK = 0, + parameter PTP_SEPARATE_RX_CLOCK = 0, parameter PTP_PORT_CDC_PIPELINE = 0, parameter PTP_PEROUT_ENABLE = 1, parameter PTP_PEROUT_COUNT = 1, @@ -232,7 +235,7 @@ module test_fpga_core # input wire [15:0] tl_cfg_ctl, input wire [4:0] tl_cfg_add, - input wire [2:0] tl_cfg_func + input wire [2:0] tl_cfg_func /* * Ethernet: QSFP28 @@ -247,7 +250,10 @@ module test_fpga_core # // output wire [CH_CNT-1:0] qsfp_mac_tx_axis_tlast, // output wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfp_mac_tx_axis_tuser, + // input wire [CH_CNT-1:0] qsfp_mac_tx_ptp_clk, + // input wire [CH_CNT-1:0] qsfp_mac_tx_ptp_rst, // output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_tx_ptp_time, + // input wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_tx_ptp_ts, // input wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfp_mac_tx_ptp_ts_tag, // input wire [CH_CNT-1:0] qsfp_mac_tx_ptp_ts_valid, @@ -265,6 +271,8 @@ module test_fpga_core # // input wire [CH_CNT-1:0] qsfp_mac_rx_axis_tlast, // input wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfp_mac_rx_axis_tuser, + // input wire [CH_CNT-1:0] qsfp_mac_rx_ptp_clk, + // input wire [CH_CNT-1:0] qsfp_mac_rx_ptp_rst, // output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_rx_ptp_time, // input wire [CH_CNT-1:0] qsfp_mac_rx_status, @@ -284,7 +292,10 @@ wire [CH_CNT-1:0] qsfp_mac_tx_axis_tready; wire [CH_CNT-1:0] qsfp_mac_tx_axis_tlast; wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfp_mac_tx_axis_tuser; +wire [CH_CNT-1:0] qsfp_mac_tx_ptp_clk; +wire [CH_CNT-1:0] qsfp_mac_tx_ptp_rst; wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_tx_ptp_time; + wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_tx_ptp_ts; wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfp_mac_tx_ptp_ts_tag; wire [CH_CNT-1:0] qsfp_mac_tx_ptp_ts_valid; @@ -302,6 +313,8 @@ wire [CH_CNT-1:0] qsfp_mac_rx_axis_tvalid; wire [CH_CNT-1:0] qsfp_mac_rx_axis_tlast; wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfp_mac_rx_axis_tuser; +wire [CH_CNT-1:0] qsfp_mac_rx_ptp_clk; +wire [CH_CNT-1:0] qsfp_mac_rx_ptp_rst; wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_rx_ptp_time; wire [CH_CNT-1:0] qsfp_mac_rx_status; @@ -312,39 +325,44 @@ generate for (n = 0; n < QSFP_CNT; n = n + 1) begin : ch - wire ch_mac_tx_clk; - wire ch_mac_tx_rst; + wire ch_mac_tx_clk; + wire ch_mac_tx_rst; - wire [AXIS_ETH_DATA_WIDTH-1:0] ch_mac_tx_axis_tdata; - wire [AXIS_ETH_KEEP_WIDTH-1:0] ch_mac_tx_axis_tkeep; - wire ch_mac_tx_axis_tvalid; - wire ch_mac_tx_axis_tready; - wire ch_mac_tx_axis_tlast; - wire [AXIS_ETH_TX_USER_WIDTH-1:0] ch_mac_tx_axis_tuser; + wire [AXIS_ETH_DATA_WIDTH-1:0] ch_mac_tx_axis_tdata; + wire [AXIS_ETH_KEEP_WIDTH-1:0] ch_mac_tx_axis_tkeep; + wire ch_mac_tx_axis_tvalid; + wire ch_mac_tx_axis_tready; + wire ch_mac_tx_axis_tlast; + wire [AXIS_ETH_TX_USER_WIDTH-1:0] ch_mac_tx_axis_tuser; - wire [PTP_TS_WIDTH-1:0] ch_mac_tx_ptp_time; - wire [PTP_TS_WIDTH-1:0] ch_mac_tx_ptp_ts; - wire [15:0] ch_mac_tx_ptp_ts_tag; - wire ch_mac_tx_ptp_ts_valid; + wire ch_mac_tx_ptp_clk; + wire ch_mac_tx_ptp_rst; + wire [PTP_TS_WIDTH-1:0] ch_mac_tx_ptp_time; - wire ch_mac_tx_status; - wire ch_mac_tx_lfc_req; - wire [7:0] ch_mac_tx_pfc_req; + wire [PTP_TS_WIDTH-1:0] ch_mac_tx_ptp_ts; + wire [15:0] ch_mac_tx_ptp_ts_tag; + wire ch_mac_tx_ptp_ts_valid; - wire ch_mac_rx_clk; - wire ch_mac_rx_rst; + wire ch_mac_tx_status; + wire ch_mac_tx_lfc_req; + wire [7:0] ch_mac_tx_pfc_req; - wire [AXIS_ETH_DATA_WIDTH-1:0] ch_mac_rx_axis_tdata; - wire [AXIS_ETH_KEEP_WIDTH-1:0] ch_mac_rx_axis_tkeep; - wire ch_mac_rx_axis_tvalid; - wire ch_mac_rx_axis_tlast; - wire [AXIS_ETH_RX_USER_WIDTH-1:0] ch_mac_rx_axis_tuser; + wire ch_mac_rx_clk; + wire ch_mac_rx_rst; - wire [PTP_TS_WIDTH-1:0] ch_mac_rx_ptp_time; + wire [AXIS_ETH_DATA_WIDTH-1:0] ch_mac_rx_axis_tdata; + wire [AXIS_ETH_KEEP_WIDTH-1:0] ch_mac_rx_axis_tkeep; + wire ch_mac_rx_axis_tvalid; + wire ch_mac_rx_axis_tlast; + wire [AXIS_ETH_RX_USER_WIDTH-1:0] ch_mac_rx_axis_tuser; - wire ch_mac_rx_status; - wire ch_mac_rx_lfc_req; - wire [7:0] ch_mac_rx_pfc_req; + wire ch_mac_rx_ptp_clk; + wire ch_mac_rx_ptp_rst; + wire [PTP_TS_WIDTH-1:0] ch_mac_rx_ptp_time; + + wire ch_mac_rx_status; + wire ch_mac_rx_lfc_req; + wire [7:0] ch_mac_rx_pfc_req; assign qsfp_mac_tx_clk[n +: 1] = ch_mac_tx_clk; assign qsfp_mac_tx_rst[n +: 1] = ch_mac_tx_rst; @@ -356,7 +374,10 @@ for (n = 0; n < QSFP_CNT; n = n + 1) begin : ch assign ch_mac_tx_axis_tlast = qsfp_mac_tx_axis_tlast[n +: 1]; assign ch_mac_tx_axis_tuser = qsfp_mac_tx_axis_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]; + assign qsfp_mac_tx_ptp_clk[n +: 1] = ch_mac_tx_ptp_clk; + assign qsfp_mac_tx_ptp_rst[n +: 1] = ch_mac_tx_ptp_rst; assign ch_mac_tx_ptp_time = qsfp_mac_tx_ptp_time[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]; + assign qsfp_mac_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = ch_mac_tx_ptp_ts; assign qsfp_mac_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH] = ch_mac_tx_ptp_ts_tag; assign qsfp_mac_tx_ptp_ts_valid[n +: 1] = ch_mac_tx_ptp_ts_valid; @@ -374,6 +395,8 @@ for (n = 0; n < QSFP_CNT; n = n + 1) begin : ch assign qsfp_mac_rx_axis_tlast[n +: 1] = ch_mac_rx_axis_tlast; assign qsfp_mac_rx_axis_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH] = ch_mac_rx_axis_tuser; + assign qsfp_mac_rx_ptp_clk[n +: 1] = ch_mac_rx_ptp_clk; + assign qsfp_mac_rx_ptp_rst[n +: 1] = ch_mac_rx_ptp_rst; assign ch_mac_rx_ptp_time = qsfp_mac_rx_ptp_time[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]; assign qsfp_mac_rx_status[n +: 1] = ch_mac_rx_status; @@ -398,6 +421,7 @@ fpga_core #( // Board configuration .QSFP_CNT(QSFP_CNT), .CH_CNT(CH_CNT), + .PORT_GROUP_SIZE(PORT_GROUP_SIZE), // Structural configuration .IF_COUNT(IF_COUNT), @@ -415,6 +439,8 @@ fpga_core #( .PTP_TS_WIDTH(PTP_TS_WIDTH), .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), + .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK), + .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), @@ -599,7 +625,10 @@ uut ( .qsfp_mac_tx_axis_tlast(qsfp_mac_tx_axis_tlast), .qsfp_mac_tx_axis_tuser(qsfp_mac_tx_axis_tuser), + .qsfp_mac_tx_ptp_clk(qsfp_mac_tx_ptp_clk), + .qsfp_mac_tx_ptp_rst(qsfp_mac_tx_ptp_rst), .qsfp_mac_tx_ptp_time(qsfp_mac_tx_ptp_time), + .qsfp_mac_tx_ptp_ts(qsfp_mac_tx_ptp_ts), .qsfp_mac_tx_ptp_ts_tag(qsfp_mac_tx_ptp_ts_tag), .qsfp_mac_tx_ptp_ts_valid(qsfp_mac_tx_ptp_ts_valid), @@ -617,6 +646,8 @@ uut ( .qsfp_mac_rx_axis_tlast(qsfp_mac_rx_axis_tlast), .qsfp_mac_rx_axis_tuser(qsfp_mac_rx_axis_tuser), + .qsfp_mac_rx_ptp_clk(qsfp_mac_rx_ptp_clk), + .qsfp_mac_rx_ptp_rst(qsfp_mac_rx_ptp_rst), .qsfp_mac_rx_ptp_time(qsfp_mac_rx_ptp_time), .qsfp_mac_rx_status(qsfp_mac_rx_status), diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/README.md b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/README.md deleted file mode 100644 index c209301b9..000000000 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/README.md +++ /dev/null @@ -1,22 +0,0 @@ -# Corundum mqnic for DK-DEV-1SDX-P-A - -## Introduction - -This design targets the Intel DK-DEV-1SDX-P-A FPGA development board. - -* FPGA: 1SD280PT2F55E1VG -* PHY: E-Tile - -## Quick start - -### Build FPGA bitstream - -Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Intel Quartus Pro toolchain components are in PATH. - -### Build driver and userspace tools - -On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools. - -### Testing - -Run `make program` to program the board with Quartus. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state. diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/app b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/app deleted file mode 120000 index 4d46690fb..000000000 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/app +++ /dev/null @@ -1 +0,0 @@ -../../../app/ \ No newline at end of file diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/common/quartus_pro.mk b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/common/quartus_pro.mk deleted file mode 100644 index f7e9cea62..000000000 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/common/quartus_pro.mk +++ /dev/null @@ -1,188 +0,0 @@ -################################################################### -# -# Makefile for Intel Quartus Prime Pro -# -# Alex Forencich -# -################################################################### -# -# Parameters: -# FPGA_TOP - Top module name -# FPGA_FAMILY - FPGA family (e.g. Stratix 10 DX) -# FPGA_DEVICE - FPGA device (e.g. 1SD280PT2F55E1VG) -# SYN_FILES - space-separated list of source files -# IP_FILES - space-separated list of IP files -# IP_TCL_FILES - space-separated list of TCL files for qsys-script -# QSF_FILES - space-separated list of settings files -# SDC_FILES - space-separated list of timing constraint files -# -# Example: -# -# FPGA_TOP = fpga -# FPGA_FAMILY = "Stratix 10 DX" -# FPGA_DEVICE = 1SD280PT2F55E1VG -# SYN_FILES = rtl/fpga.v -# QSF_FILES = fpga.qsf -# SDC_FILES = fpga.sdc -# include ../common/quartus_pro.mk -# -################################################################### - -# phony targets -.PHONY: clean fpga - -# output files to hang on to -.PRECIOUS: %.sof %.ipregen.rpt %.syn.rpt %.fit.rpt %.asm.rpt %.sta.rpt -.SECONDARY: - -# any project specific settings -CONFIG ?= config.mk --include ../$(CONFIG) - -SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) - -IP_FILES_REL = $(patsubst %, ../%, $(IP_FILES)) -IP_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_FILES))) - -IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) -IP_TCL_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_TCL_FILES))) -IP_TCL_FILES_IP_INT = $(patsubst %.tcl, ip/%.ip, $(notdir $(IP_TCL_FILES))) - -CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) - -ifdef QSF_FILES - QSF_FILES_REL = $(foreach p,$(QSF_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -else - QSF_FILES_REL = ../$(FPGA_TOP).qsf -endif - -SDC_FILES_REL = $(foreach p,$(SDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) - -ASSIGNMENT_FILES = $(FPGA_TOP).qpf $(FPGA_TOP).qsf - -################################################################### -# Main Targets -# -# all: build everything -# clean: remove output files and database -################################################################### - -all: fpga - -fpga: $(FPGA_TOP).sof - -quartus: $(FPGA_TOP).qpf - quartus $(FPGA_TOP).qpf - -tmpclean:: - -rm -rf defines.v - -rm -rf *.rpt *.summary *.done *.smsg *.chg smart.log *.htm *.eqn *.pin *.qsf *.qpf *.sld *.txt *.qws *.stp - -rm -rf ip db qdb incremental_db reconfig_mif tmp-clearbox synth_dumps .qsys_edit - -rm -rf create_project.tcl update_config.tcl update_ip_*.tcl - -clean:: tmpclean - -rm -rf *.sof *.pof *.jdi *.jic *.map - -distclean:: clean - -rm -rf rev - -syn: smart.log output_files/$(PROJECT).syn.rpt -fit: smart.log output_files/$(PROJECT).fit.rpt -asm: smart.log output_files/$(PROJECT).asm.rpt -sta: smart.log output_files/$(PROJECT).sta.rpt -smart: smart.log - -################################################################### -# Executable Configuration -################################################################### - -IP_ARGS = --run_default_mode_op -SYN_ARGS = --read_settings_files=on --write_settings_files=off -FIT_ARGS = --read_settings_files=on --write_settings_files=off -ASM_ARGS = --read_settings_files=on --write_settings_files=off -STA_ARGS = - -################################################################### -# Target implementations -################################################################### - -STAMP = echo done > - -define COPY_IP_RULE -$(patsubst %, ip/%, $(notdir $(1))): $(1) - @mkdir -p ip - @cp -pv $(1) ip/ -endef -$(foreach l,$(IP_FILES_REL) $(IP_TCL_FILES_REL),$(eval $(call COPY_IP_RULE,$(l)))) - -define TCL_IP_GEN_RULE -$(patsubst %.tcl,%.ip,$(1)): $(1) - cd ip && rm -f $(patsubst %.tcl,%,$(notdir $(1))).{qpf,qsf} - cd ip && qsys-script --script=$(notdir $(1)) -endef -$(foreach l,$(IP_TCL_FILES_INT),$(eval $(call TCL_IP_GEN_RULE,$(l)))) - -%.ipregen.rpt: $(FPGA_TOP).qpf $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT) - quartus_ipgenerate $(IP_ARGS) $(FPGA_TOP) - -%.syn.rpt: syn.chg %.ipregen.rpt $(SYN_FILES_REL) - quartus_syn $(SYN_ARGS) $(FPGA_TOP) - -%.fit.rpt: fit.chg %.syn.rpt $(SDC_FILES_REL) - quartus_fit $(FIT_ARGS) $(FPGA_TOP) - -%.sta.rpt: sta.chg %.fit.rpt - quartus_sta $(STA_ARGS) $(FPGA_TOP) - -%.asm.rpt: asm.chg %.sta.rpt - quartus_asm $(ASM_ARGS) $(FPGA_TOP) - mkdir -p rev - EXT=sof; COUNT=100; \ - while [ -e rev/$*_rev$$COUNT.$$EXT ]; \ - do let COUNT=COUNT+1; done; \ - cp $*.$$EXT rev/$*_rev$$COUNT.$$EXT; \ - echo "Output: rev/$*_rev$$COUNT.$$EXT"; - -%.sof: smart.log %.asm.rpt - - -smart.log: $(ASSIGNMENT_FILES) - quartus_sh --determine_smart_action $(FPGA_TOP) > smart.log - -################################################################### -# Project initialization -################################################################### - -create_project.tcl: Makefile $(QSF_FILES_REL) | $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT) - rm -f update_config.tcl - echo "project_new $(FPGA_TOP) -overwrite" > $@ - echo "set_global_assignment -name FAMILY \"$(FPGA_FAMILY)\"" >> $@ - echo "set_global_assignment -name DEVICE \"$(FPGA_DEVICE)\"" >> $@ - for x in $(SYN_FILES_REL) $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT); do \ - case $${x##*.} in \ - v|V) echo set_global_assignment -name VERILOG_FILE "$$x" >> $@ ;;\ - vhd|VHD) echo set_global_assignment -name VHDL_FILE "$$x" >> $@ ;;\ - qip|QIP) echo set_global_assignment -name QIP_FILE "$$x" >> $@ ;;\ - ip|IP) echo set_global_assignment -name IP_FILE "$$x" >> $@ ;;\ - *) echo set_global_assignment -name SOURCE_FILE "$$x" >> $@ ;;\ - esac; \ - done - for x in $(SDC_FILES_REL); do echo set_global_assignment -name SDC_FILE "$$x" >> $@; done - for x in $(QSF_FILES_REL); do echo source "$$x" >> $@; done - -update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) - echo "project_open $(FPGA_TOP)" > $@ - for x in $(CONFIG_TCL_FILES_REL); do echo source "$$x" >> $@; done - -$(ASSIGNMENT_FILES): create_project.tcl update_config.tcl - for x in $?; do quartus_sh -t "$$x"; done - touch -c $(ASSIGNMENT_FILES) - -syn.chg: - $(STAMP) syn.chg -fit.chg: - $(STAMP) fit.chg -sta.chg: - $(STAMP) sta.chg -asm.chg: - $(STAMP) asm.chg diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga.qsf b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga.qsf deleted file mode 100644 index a4f1dbf79..000000000 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga.qsf +++ /dev/null @@ -1,1425 +0,0 @@ -# I/O constraints for the Intel Stratix 10 DX FPGA development board -# part: 1SD280PT2F55E1VG - -set_global_assignment -name USE_CONF_DONE SDM_IO16 -set_global_assignment -name USE_CVP_CONFDONE SDM_IO5 - -set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" -set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 -set_global_assignment -name USE_PWRMGT_SDA SDM_IO12 -set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ" -set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE ED8401 -set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 49 -set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 -set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 -set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00 -set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00 -set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00 -set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00 -set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00 -set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT" -set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-13" -set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS -set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE OFF - -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X8" -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON -set_global_assignment -name GENERATE_COMPRESSED_SOF ON -set_global_assignment -name GENERATE_PR_RBF_FILE ON -set_global_assignment -name ENABLE_ED_CRC_CHECK ON -set_global_assignment -name MINIMUM_SEU_INTERVAL 0 -set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_115MHZ_IOSC -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 - -set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON - -set_global_assignment -name verilog_allow_ram_inferred_in_generate_loop on - -# Clock and reset -set_location_assignment PIN_E21 -to clk_133m_ddr4_0_p -set_location_assignment PIN_F21 -to clk_133m_ddr4_0_n -set_location_assignment PIN_J45 -to clk_133m_ddr4_1_p -set_location_assignment PIN_H45 -to clk_133m_ddr4_1_n -set_location_assignment PIN_BH37 -to clk_133m_dimm_0_p -set_location_assignment PIN_BJ36 -to clk_133m_dimm_0_n -set_location_assignment PIN_BF19 -to clk_133m_dimm_1_p -set_location_assignment PIN_BG19 -to clk_133m_dimm_1_n - -set_location_assignment PIN_H33 -to clk2_100m_fpga_2i_p -set_location_assignment PIN_J33 -to clk2_100m_fpga_2i_n -set_location_assignment PIN_K36 -to clk2_100m_fpga_2j_0_p -set_location_assignment PIN_L36 -to clk2_100m_fpga_2j_0_n -set_location_assignment PIN_E36 -to clk2_100m_fpga_2j_1_p -set_location_assignment PIN_F36 -to clk2_100m_fpga_2j_1_n -set_location_assignment PIN_A31 -to clk_100m_fpga_3h_p -set_location_assignment PIN_A30 -to clk_100m_fpga_3h_n -set_location_assignment PIN_C23 -to clk_100m_fpga_3l_0_p -set_location_assignment PIN_B23 -to clk_100m_fpga_3l_0_n -set_location_assignment PIN_J29 -to clk_100m_fpga_3l_1_p -set_location_assignment PIN_J28 -to clk_100m_fpga_3l_1_n - -set_location_assignment PIN_G38 -to clk2_fpga_50m - -set_location_assignment PIN_BJ28 -to clk_125m_lvc1_config - -set_instance_assignment -name IO_STANDARD LVDS -to clk_133m_ddr4_0_p -set_instance_assignment -name IO_STANDARD LVDS -to clk_133m_ddr4_1_p -set_instance_assignment -name IO_STANDARD LVDS -to clk_133m_dimm_0_p -set_instance_assignment -name IO_STANDARD LVDS -to clk_133m_dimm_1_p - -set_instance_assignment -name IO_STANDARD LVDS -to clk2_100m_fpga_2i_p -set_instance_assignment -name IO_STANDARD LVDS -to clk2_100m_fpga_2j_0_p -set_instance_assignment -name IO_STANDARD LVDS -to clk2_100m_fpga_2j_1_p -set_instance_assignment -name IO_STANDARD LVDS -to clk_100m_fpga_3h_p -set_instance_assignment -name IO_STANDARD LVDS -to clk_100m_fpga_3l_0_p -set_instance_assignment -name IO_STANDARD LVDS -to clk_100m_fpga_3l_1_p - -set_instance_assignment -name IO_STANDARD "1.8 V" -to clk2_fpga_50m - -# Switches, buttons, LEDs -set_location_assignment PIN_C41 -to cpu_resetn -set_location_assignment PIN_A39 -to user_pb -set_location_assignment PIN_D39 -to usb_fpga_clk -set_location_assignment PIN_F41 -to tsense_alertn_1v8 - -set_location_assignment PIN_A37 -to user_led_g[0] -set_location_assignment PIN_C38 -to user_led_g[1] -set_location_assignment PIN_A35 -to user_led_g[2] -set_location_assignment PIN_C36 -to user_led_g[3] - -set_instance_assignment -name IO_STANDARD "1.8 V" -to cpu_resetn -set_instance_assignment -name IO_STANDARD "1.8 V" -to user_pb -set_instance_assignment -name IO_STANDARD "1.8 V" -to usb_fpga_clk -set_instance_assignment -name IO_STANDARD "1.8 V" -to tsense_alertn_1v8 - -set_instance_assignment -name IO_STANDARD "1.8 V" -to user_led_g[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to user_led_g[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to user_led_g[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to user_led_g[3] - -# I2C -set_location_assignment PIN_R31 -to bmc_i2c1_disable -set_location_assignment PIN_N36 -to bmc_i2c2_disable -set_location_assignment PIN_P36 -to bmc_i2c3_disable - -set_location_assignment PIN_C32 -to i2c1_scl -set_location_assignment PIN_G32 -to i2c1_sda -set_location_assignment PIN_K32 -to i2c2_scl -set_location_assignment PIN_B33 -to i2c2_sda -set_location_assignment PIN_G33 -to i2c3_scl -set_location_assignment PIN_C33 -to i2c3_sda -set_location_assignment PIN_N35 -to i2c_ddr4_dimm_sda -set_location_assignment PIN_P35 -to i2c_ddr4_dimm_scl - -set_instance_assignment -name IO_STANDARD "1.8 V" -to bmc_i2c1_disable -set_instance_assignment -name IO_STANDARD "1.8 V" -to bmc_i2c2_disable -set_instance_assignment -name IO_STANDARD "1.8 V" -to bmc_i2c3_disable - -set_instance_assignment -name IO_STANDARD "1.8 V" -to i2c1_scl -set_instance_assignment -name IO_STANDARD "1.8 V" -to i2c1_sda -set_instance_assignment -name IO_STANDARD "1.8 V" -to i2c2_scl -set_instance_assignment -name IO_STANDARD "1.8 V" -to i2c2_sda -set_instance_assignment -name IO_STANDARD "1.8 V" -to i2c3_scl -set_instance_assignment -name IO_STANDARD "1.8 V" -to i2c3_sda -set_instance_assignment -name IO_STANDARD "1.8 V" -to i2c_ddr4_dimm_sda -set_instance_assignment -name IO_STANDARD "1.8 V" -to i2c_ddr4_dimm_scl - -# PCIe -set_location_assignment PIN_BJ48 -to pcie_tx_p[0] ;# GXPL10A_TX_CH0P -set_location_assignment PIN_BJ47 -to pcie_tx_n[0] ;# GXPL10A_TX_CH0N -set_location_assignment PIN_BH50 -to pcie_tx_p[1] ;# GXPL10A_TX_CH1P -set_location_assignment PIN_BH49 -to pcie_tx_n[1] ;# GXPL10A_TX_CH1N -set_location_assignment PIN_BG48 -to pcie_tx_p[2] ;# GXPL10A_TX_CH2P -set_location_assignment PIN_BG47 -to pcie_tx_n[2] ;# GXPL10A_TX_CH2N -set_location_assignment PIN_BF50 -to pcie_tx_p[3] ;# GXPL10A_TX_CH3P -set_location_assignment PIN_BF49 -to pcie_tx_n[3] ;# GXPL10A_TX_CH3N -set_location_assignment PIN_BE48 -to pcie_tx_p[4] ;# GXPL10A_TX_CH4P -set_location_assignment PIN_BE47 -to pcie_tx_n[4] ;# GXPL10A_TX_CH4N -set_location_assignment PIN_BD50 -to pcie_tx_p[5] ;# GXPL10A_TX_CH5P -set_location_assignment PIN_BD49 -to pcie_tx_n[5] ;# GXPL10A_TX_CH5N -set_location_assignment PIN_BC48 -to pcie_tx_p[6] ;# GXPL10A_TX_CH6P -set_location_assignment PIN_BC47 -to pcie_tx_n[6] ;# GXPL10A_TX_CH6N -set_location_assignment PIN_BB50 -to pcie_tx_p[7] ;# GXPL10A_TX_CH7P -set_location_assignment PIN_BB49 -to pcie_tx_n[7] ;# GXPL10A_TX_CH7N -set_location_assignment PIN_BA48 -to pcie_tx_p[8] ;# GXPL10A_TX_CH8P -set_location_assignment PIN_BA47 -to pcie_tx_n[8] ;# GXPL10A_TX_CH8N -set_location_assignment PIN_AY50 -to pcie_tx_p[9] ;# GXPL10A_TX_CH9P -set_location_assignment PIN_AY49 -to pcie_tx_n[9] ;# GXPL10A_TX_CH9N -set_location_assignment PIN_AW48 -to pcie_tx_p[10] ;# GXPL10A_TX_CH10P -set_location_assignment PIN_AW47 -to pcie_tx_n[10] ;# GXPL10A_TX_CH10N -set_location_assignment PIN_AV50 -to pcie_tx_p[11] ;# GXPL10A_TX_CH11P -set_location_assignment PIN_AV49 -to pcie_tx_n[11] ;# GXPL10A_TX_CH11N -set_location_assignment PIN_AU48 -to pcie_tx_p[12] ;# GXPL10A_TX_CH12P -set_location_assignment PIN_AU47 -to pcie_tx_n[12] ;# GXPL10A_TX_CH12N -set_location_assignment PIN_AT50 -to pcie_tx_p[13] ;# GXPL10A_TX_CH13P -set_location_assignment PIN_AT49 -to pcie_tx_n[13] ;# GXPL10A_TX_CH13N -set_location_assignment PIN_AR48 -to pcie_tx_p[14] ;# GXPL10A_TX_CH14P -set_location_assignment PIN_AR47 -to pcie_tx_n[14] ;# GXPL10A_TX_CH14N -set_location_assignment PIN_AP50 -to pcie_tx_p[15] ;# GXPL10A_TX_CH15P -set_location_assignment PIN_AP49 -to pcie_tx_n[15] ;# GXPL10A_TX_CH15N -set_location_assignment PIN_BJ52 -to pcie_rx_p[0] ;# GXPL10A_RX_CH0P -set_location_assignment PIN_BJ51 -to pcie_rx_n[0] ;# GXPL10A_RX_CH0N -set_location_assignment PIN_BH54 -to pcie_rx_p[1] ;# GXPL10A_RX_CH1P -set_location_assignment PIN_BH53 -to pcie_rx_n[1] ;# GXPL10A_RX_CH1N -set_location_assignment PIN_BG52 -to pcie_rx_p[2] ;# GXPL10A_RX_CH2P -set_location_assignment PIN_BG51 -to pcie_rx_n[2] ;# GXPL10A_RX_CH2N -set_location_assignment PIN_BF54 -to pcie_rx_p[3] ;# GXPL10A_RX_CH3P -set_location_assignment PIN_BF53 -to pcie_rx_n[3] ;# GXPL10A_RX_CH3N -set_location_assignment PIN_BE52 -to pcie_rx_p[4] ;# GXPL10A_RX_CH4P -set_location_assignment PIN_BE51 -to pcie_rx_n[4] ;# GXPL10A_RX_CH4N -set_location_assignment PIN_BD54 -to pcie_rx_p[5] ;# GXPL10A_RX_CH5P -set_location_assignment PIN_BD53 -to pcie_rx_n[5] ;# GXPL10A_RX_CH5N -set_location_assignment PIN_BC52 -to pcie_rx_p[6] ;# GXPL10A_RX_CH6P -set_location_assignment PIN_BC51 -to pcie_rx_n[6] ;# GXPL10A_RX_CH6N -set_location_assignment PIN_BB54 -to pcie_rx_p[7] ;# GXPL10A_RX_CH7P -set_location_assignment PIN_BB53 -to pcie_rx_n[7] ;# GXPL10A_RX_CH7N -set_location_assignment PIN_BA52 -to pcie_rx_p[8] ;# GXPL10A_RX_CH8P -set_location_assignment PIN_BA51 -to pcie_rx_n[8] ;# GXPL10A_RX_CH8N -set_location_assignment PIN_AY54 -to pcie_rx_p[9] ;# GXPL10A_RX_CH9P -set_location_assignment PIN_AY53 -to pcie_rx_n[9] ;# GXPL10A_RX_CH9N -set_location_assignment PIN_AW52 -to pcie_rx_p[10] ;# GXPL10A_RX_CH10P -set_location_assignment PIN_AW51 -to pcie_rx_n[10] ;# GXPL10A_RX_CH10N -set_location_assignment PIN_AV54 -to pcie_rx_p[11] ;# GXPL10A_RX_CH11P -set_location_assignment PIN_AV53 -to pcie_rx_n[11] ;# GXPL10A_RX_CH11N -set_location_assignment PIN_AU52 -to pcie_rx_p[12] ;# GXPL10A_RX_CH12P -set_location_assignment PIN_AU51 -to pcie_rx_n[12] ;# GXPL10A_RX_CH12N -set_location_assignment PIN_AT54 -to pcie_rx_p[13] ;# GXPL10A_RX_CH13P -set_location_assignment PIN_AT53 -to pcie_rx_n[13] ;# GXPL10A_RX_CH13N -set_location_assignment PIN_AR52 -to pcie_rx_p[14] ;# GXPL10A_RX_CH14P -set_location_assignment PIN_AR51 -to pcie_rx_n[14] ;# GXPL10A_RX_CH14N -set_location_assignment PIN_AP54 -to pcie_rx_p[15] ;# GXPL10A_RX_CH15P -set_location_assignment PIN_AP53 -to pcie_rx_n[15] ;# GXPL10A_RX_CH15N - -set_location_assignment PIN_AT45 -to clk_100m_pcie_0_p ;# REFCLK_GXPL10A_CH0N -set_location_assignment PIN_AT44 -to clk_100m_pcie_0_n ;# REFCLK_GXPL10A_CH0P -set_location_assignment PIN_AP45 -to clk_100m_pcie_1_p ;# REFCLK_GXPL10A_CH2N -set_location_assignment PIN_AP44 -to clk_100m_pcie_1_n ;# REFCLK_GXPL10A_CH2P - -set_location_assignment PIN_BB39 -to pcie_rst_n - -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p[2] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p[3] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p[4] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p[5] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p[6] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p[7] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p[8] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p[9] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p[10] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p[11] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p[12] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p[13] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p[14] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p[15] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_rx_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_rx_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_rx_p[2] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_rx_p[3] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_rx_p[4] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_rx_p[5] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_rx_p[6] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_rx_p[7] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_rx_p[8] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_rx_p[9] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_rx_p[10] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_rx_p[11] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_rx_p[12] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_rx_p[13] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_rx_p[14] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_rx_p[15] - -set_instance_assignment -name IO_STANDARD "HCSL" -to clk_100m_pcie_0_p -set_instance_assignment -name IO_STANDARD "HCSL" -to clk_100m_pcie_1_p - -# UPI0 -set_location_assignment PIN_AN48 -to upi0_tx_p[0] ;# GXPL10B_TX_CH0P -set_location_assignment PIN_AN47 -to upi0_tx_n[0] ;# GXPL10B_TX_CH0N -set_location_assignment PIN_AM50 -to upi0_tx_p[1] ;# GXPL10B_TX_CH1P -set_location_assignment PIN_AM49 -to upi0_tx_n[1] ;# GXPL10B_TX_CH1N -set_location_assignment PIN_AL48 -to upi0_tx_p[2] ;# GXPL10B_TX_CH2P -set_location_assignment PIN_AL47 -to upi0_tx_n[2] ;# GXPL10B_TX_CH2N -set_location_assignment PIN_AK50 -to upi0_tx_p[3] ;# GXPL10B_TX_CH3P -set_location_assignment PIN_AK49 -to upi0_tx_n[3] ;# GXPL10B_TX_CH3N -set_location_assignment PIN_AJ48 -to upi0_tx_p[4] ;# GXPL10B_TX_CH4P -set_location_assignment PIN_AJ47 -to upi0_tx_n[4] ;# GXPL10B_TX_CH4N -set_location_assignment PIN_AH50 -to upi0_tx_p[5] ;# GXPL10B_TX_CH5P -set_location_assignment PIN_AH49 -to upi0_tx_n[5] ;# GXPL10B_TX_CH5N -set_location_assignment PIN_AG48 -to upi0_tx_p[6] ;# GXPL10B_TX_CH6P -set_location_assignment PIN_AG47 -to upi0_tx_n[6] ;# GXPL10B_TX_CH6N -set_location_assignment PIN_AF50 -to upi0_tx_p[7] ;# GXPL10B_TX_CH7P -set_location_assignment PIN_AF49 -to upi0_tx_n[7] ;# GXPL10B_TX_CH7N -set_location_assignment PIN_AE48 -to upi0_tx_p[8] ;# GXPL10B_TX_CH8P -set_location_assignment PIN_AE47 -to upi0_tx_n[8] ;# GXPL10B_TX_CH8N -set_location_assignment PIN_AD50 -to upi0_tx_p[9] ;# GXPL10B_TX_CH9P -set_location_assignment PIN_AD49 -to upi0_tx_n[9] ;# GXPL10B_TX_CH9N -set_location_assignment PIN_AC48 -to upi0_tx_p[10] ;# GXPL10B_TX_CH10P -set_location_assignment PIN_AC47 -to upi0_tx_n[10] ;# GXPL10B_TX_CH10N -set_location_assignment PIN_AB50 -to upi0_tx_p[11] ;# GXPL10B_TX_CH11P -set_location_assignment PIN_AB49 -to upi0_tx_n[11] ;# GXPL10B_TX_CH11N -set_location_assignment PIN_AA48 -to upi0_tx_p[12] ;# GXPL10B_TX_CH12P -set_location_assignment PIN_AA47 -to upi0_tx_n[12] ;# GXPL10B_TX_CH12N -set_location_assignment PIN_Y50 -to upi0_tx_p[13] ;# GXPL10B_TX_CH13P -set_location_assignment PIN_Y49 -to upi0_tx_n[13] ;# GXPL10B_TX_CH13N -set_location_assignment PIN_W48 -to upi0_tx_p[14] ;# GXPL10B_TX_CH14P -set_location_assignment PIN_W47 -to upi0_tx_n[14] ;# GXPL10B_TX_CH14N -set_location_assignment PIN_V50 -to upi0_tx_p[15] ;# GXPL10B_TX_CH15P -set_location_assignment PIN_V49 -to upi0_tx_n[15] ;# GXPL10B_TX_CH15N -set_location_assignment PIN_U48 -to upi0_tx_p[16] ;# GXPL10B_TX_CH16P -set_location_assignment PIN_U47 -to upi0_tx_n[16] ;# GXPL10B_TX_CH16N -set_location_assignment PIN_T50 -to upi0_tx_p[17] ;# GXPL10B_TX_CH17P -set_location_assignment PIN_T49 -to upi0_tx_n[17] ;# GXPL10B_TX_CH17N -set_location_assignment PIN_R48 -to upi0_tx_p[18] ;# GXPL10B_TX_CH18P -set_location_assignment PIN_R47 -to upi0_tx_n[18] ;# GXPL10B_TX_CH18N -set_location_assignment PIN_P50 -to upi0_tx_p[19] ;# GXPL10B_TX_CH19P -set_location_assignment PIN_P49 -to upi0_tx_n[19] ;# GXPL10B_TX_CH19N -set_location_assignment PIN_AN52 -to upi0_rx_p[0] ;# GXPL10B_RX_CH0P -set_location_assignment PIN_AN51 -to upi0_rx_n[0] ;# GXPL10B_RX_CH0N -set_location_assignment PIN_AM54 -to upi0_rx_p[1] ;# GXPL10B_RX_CH1P -set_location_assignment PIN_AM53 -to upi0_rx_n[1] ;# GXPL10B_RX_CH1N -set_location_assignment PIN_AL52 -to upi0_rx_p[2] ;# GXPL10B_RX_CH2P -set_location_assignment PIN_AL51 -to upi0_rx_n[2] ;# GXPL10B_RX_CH2N -set_location_assignment PIN_AK54 -to upi0_rx_p[3] ;# GXPL10B_RX_CH3P -set_location_assignment PIN_AK53 -to upi0_rx_n[3] ;# GXPL10B_RX_CH3N -set_location_assignment PIN_AJ52 -to upi0_rx_p[4] ;# GXPL10B_RX_CH4P -set_location_assignment PIN_AJ51 -to upi0_rx_n[4] ;# GXPL10B_RX_CH4N -set_location_assignment PIN_AH54 -to upi0_rx_p[5] ;# GXPL10B_RX_CH5P -set_location_assignment PIN_AH53 -to upi0_rx_n[5] ;# GXPL10B_RX_CH5N -set_location_assignment PIN_AG52 -to upi0_rx_p[6] ;# GXPL10B_RX_CH6P -set_location_assignment PIN_AG51 -to upi0_rx_n[6] ;# GXPL10B_RX_CH6N -set_location_assignment PIN_AF54 -to upi0_rx_p[7] ;# GXPL10B_RX_CH7P -set_location_assignment PIN_AF53 -to upi0_rx_n[7] ;# GXPL10B_RX_CH7N -set_location_assignment PIN_AE52 -to upi0_rx_p[8] ;# GXPL10B_RX_CH8P -set_location_assignment PIN_AE51 -to upi0_rx_n[8] ;# GXPL10B_RX_CH8N -set_location_assignment PIN_AD54 -to upi0_rx_p[9] ;# GXPL10B_RX_CH9P -set_location_assignment PIN_AD53 -to upi0_rx_n[9] ;# GXPL10B_RX_CH9N -set_location_assignment PIN_AC52 -to upi0_rx_p[10] ;# GXPL10B_RX_CH10P -set_location_assignment PIN_AC51 -to upi0_rx_n[10] ;# GXPL10B_RX_CH10N -set_location_assignment PIN_AB54 -to upi0_rx_p[11] ;# GXPL10B_RX_CH11P -set_location_assignment PIN_AB53 -to upi0_rx_n[11] ;# GXPL10B_RX_CH11N -set_location_assignment PIN_AA52 -to upi0_rx_p[12] ;# GXPL10B_RX_CH12P -set_location_assignment PIN_AA51 -to upi0_rx_n[12] ;# GXPL10B_RX_CH12N -set_location_assignment PIN_Y54 -to upi0_rx_p[13] ;# GXPL10B_RX_CH13P -set_location_assignment PIN_Y53 -to upi0_rx_n[13] ;# GXPL10B_RX_CH13N -set_location_assignment PIN_W52 -to upi0_rx_p[14] ;# GXPL10B_RX_CH14P -set_location_assignment PIN_W51 -to upi0_rx_n[14] ;# GXPL10B_RX_CH14N -set_location_assignment PIN_V54 -to upi0_rx_p[15] ;# GXPL10B_RX_CH15P -set_location_assignment PIN_V53 -to upi0_rx_n[15] ;# GXPL10B_RX_CH15N -set_location_assignment PIN_U52 -to upi0_rx_p[16] ;# GXPL10B_RX_CH16P -set_location_assignment PIN_U51 -to upi0_rx_n[16] ;# GXPL10B_RX_CH16N -set_location_assignment PIN_T54 -to upi0_rx_p[17] ;# GXPL10B_RX_CH17P -set_location_assignment PIN_T53 -to upi0_rx_n[17] ;# GXPL10B_RX_CH17N -set_location_assignment PIN_R52 -to upi0_rx_p[18] ;# GXPL10B_RX_CH18P -set_location_assignment PIN_R51 -to upi0_rx_n[18] ;# GXPL10B_RX_CH18N -set_location_assignment PIN_P54 -to upi0_rx_p[19] ;# GXPL10B_RX_CH19P -set_location_assignment PIN_P53 -to upi0_rx_n[19] ;# GXPL10B_RX_CH19N - -set_location_assignment PIN_AJ45 -to clk_100m_upi0_0_p ;# REFCLK_GXPL10B_CH0P -set_location_assignment PIN_AJ44 -to clk_100m_upi0_0_n ;# REFCLK_GXPL10B_CH0N -set_location_assignment PIN_AG45 -to clk_100m_upi0_1_p ;# REFCLK_GXPL10B_CH2P -set_location_assignment PIN_AG44 -to clk_100m_upi0_1_n ;# REFCLK_GXPL10B_CH2N - -set_location_assignment PIN_AD45 -to upi0_rst_n - -set_location_assignment PIN_F26 -to upi0_lsio_rx[1] -set_location_assignment PIN_H26 -to upi0_lsio_rx[2] -set_location_assignment PIN_H27 -to upi0_lsio_rx[3] -set_location_assignment PIN_G28 -to upi0_lsio_rx[4] -set_location_assignment PIN_H28 -to upi0_lsio_rx[5] -set_location_assignment PIN_K27 -to upi0_lsio_rx[6] -set_location_assignment PIN_L27 -to upi0_lsio_tx[1] -set_location_assignment PIN_L26 -to upi0_lsio_tx[2] -set_location_assignment PIN_M28 -to upi0_lsio_tx[3] -set_location_assignment PIN_N28 -to upi0_lsio_tx[4] -set_location_assignment PIN_J26 -to upi0_lsio_tx[5] -set_location_assignment PIN_K26 -to upi0_lsio_tx[6] - -set_location_assignment PIN_H37 -to upi0_lsio_rx1_pcie_1v8 -set_location_assignment PIN_G37 -to upi0_lsio_rx2_pcie_1v8 -set_location_assignment PIN_J34 -to upi0_lsio_rx5_pcie_1v8 -set_location_assignment PIN_K34 -to upi0_lsio_rx6_pcie_1v8 - -set_location_assignment PIN_D29 -to s10_upi0_nid_1v8[0] -set_location_assignment PIN_E29 -to s10_upi0_nid_1v8[1] - -set_location_assignment PIN_P26 -to s10_upi0_perstn_sel -set_location_assignment PIN_R26 -to s10_upi0_prnstn_1v8 - -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_tx_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_tx_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_tx_p[2] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_tx_p[3] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_tx_p[4] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_tx_p[5] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_tx_p[6] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_tx_p[7] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_tx_p[8] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_tx_p[9] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_tx_p[10] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_tx_p[11] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_tx_p[12] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_tx_p[13] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_tx_p[14] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_tx_p[15] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_rx_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_rx_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_rx_p[2] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_rx_p[3] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_rx_p[4] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_rx_p[5] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_rx_p[6] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_rx_p[7] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_rx_p[8] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_rx_p[9] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_rx_p[10] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_rx_p[11] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_rx_p[12] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_rx_p[13] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_rx_p[14] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi0_rx_p[15] - -set_instance_assignment -name IO_STANDARD "HCSL" -to clk_100m_upi0_0_p -set_instance_assignment -name IO_STANDARD "HCSL" -to clk_100m_upi0_1_p - -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi0_lsio_rx[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi0_lsio_rx[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi0_lsio_rx[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi0_lsio_rx[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi0_lsio_rx[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi0_lsio_rx[6] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi0_lsio_tx[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi0_lsio_tx[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi0_lsio_tx[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi0_lsio_tx[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi0_lsio_tx[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi0_lsio_tx[6] - -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi0_lsio_rx1_pcie_1v8 -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi0_lsio_rx2_pcie_1v8 -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi0_lsio_rx5_pcie_1v8 -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi0_lsio_rx6_pcie_1v8 - -set_instance_assignment -name IO_STANDARD "1.8 V" -to s10_upi0_nid_1v8[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to s10_upi0_nid_1v8[1] - -set_instance_assignment -name IO_STANDARD "1.8 V" -to s10_upi0_perstn_sel -set_instance_assignment -name IO_STANDARD "1.8 V" -to s10_upi0_prnstn_1v8 - -# UPI1 -set_location_assignment PIN_BA7 -to upi1_tx_p[0] ;# GXPR11B_TX_CH0P -set_location_assignment PIN_BA8 -to upi1_tx_n[0] ;# GXPR11B_TX_CH0N -set_location_assignment PIN_AY5 -to upi1_tx_p[1] ;# GXPR11B_TX_CH1P -set_location_assignment PIN_AY6 -to upi1_tx_n[1] ;# GXPR11B_TX_CH1N -set_location_assignment PIN_AW7 -to upi1_tx_p[2] ;# GXPR11B_TX_CH2P -set_location_assignment PIN_AW8 -to upi1_tx_n[2] ;# GXPR11B_TX_CH2N -set_location_assignment PIN_AV5 -to upi1_tx_p[3] ;# GXPR11B_TX_CH3P -set_location_assignment PIN_AV6 -to upi1_tx_n[3] ;# GXPR11B_TX_CH3N -set_location_assignment PIN_AU7 -to upi1_tx_p[4] ;# GXPR11B_TX_CH4P -set_location_assignment PIN_AU8 -to upi1_tx_n[4] ;# GXPR11B_TX_CH4N -set_location_assignment PIN_AT5 -to upi1_tx_p[5] ;# GXPR11B_TX_CH5P -set_location_assignment PIN_AT6 -to upi1_tx_n[5] ;# GXPR11B_TX_CH5N -set_location_assignment PIN_AR7 -to upi1_tx_p[6] ;# GXPR11B_TX_CH6P -set_location_assignment PIN_AR8 -to upi1_tx_n[6] ;# GXPR11B_TX_CH6N -set_location_assignment PIN_AP5 -to upi1_tx_p[7] ;# GXPR11B_TX_CH7P -set_location_assignment PIN_AP6 -to upi1_tx_n[7] ;# GXPR11B_TX_CH7N -set_location_assignment PIN_AN7 -to upi1_tx_p[8] ;# GXPR11B_TX_CH8P -set_location_assignment PIN_AN8 -to upi1_tx_n[8] ;# GXPR11B_TX_CH8N -set_location_assignment PIN_AM5 -to upi1_tx_p[9] ;# GXPR11B_TX_CH9P -set_location_assignment PIN_AM6 -to upi1_tx_n[9] ;# GXPR11B_TX_CH9N -set_location_assignment PIN_AL7 -to upi1_tx_p[10] ;# GXPR11B_TX_CH10P -set_location_assignment PIN_AL8 -to upi1_tx_n[10] ;# GXPR11B_TX_CH10N -set_location_assignment PIN_AK5 -to upi1_tx_p[11] ;# GXPR11B_TX_CH11P -set_location_assignment PIN_AK6 -to upi1_tx_n[11] ;# GXPR11B_TX_CH11N -set_location_assignment PIN_AJ7 -to upi1_tx_p[12] ;# GXPR11B_TX_CH12P -set_location_assignment PIN_AJ8 -to upi1_tx_n[12] ;# GXPR11B_TX_CH12N -set_location_assignment PIN_AH5 -to upi1_tx_p[13] ;# GXPR11B_TX_CH13P -set_location_assignment PIN_AH6 -to upi1_tx_n[13] ;# GXPR11B_TX_CH13N -set_location_assignment PIN_AG7 -to upi1_tx_p[14] ;# GXPR11B_TX_CH14P -set_location_assignment PIN_AG8 -to upi1_tx_n[14] ;# GXPR11B_TX_CH14N -set_location_assignment PIN_AF5 -to upi1_tx_p[15] ;# GXPR11B_TX_CH15P -set_location_assignment PIN_AF6 -to upi1_tx_n[15] ;# GXPR11B_TX_CH15N -set_location_assignment PIN_AE7 -to upi1_tx_p[16] ;# GXPR11B_TX_CH16P -set_location_assignment PIN_AE8 -to upi1_tx_n[16] ;# GXPR11B_TX_CH16N -set_location_assignment PIN_AD5 -to upi1_tx_p[17] ;# GXPR11B_TX_CH17P -set_location_assignment PIN_AD6 -to upi1_tx_n[17] ;# GXPR11B_TX_CH17N -set_location_assignment PIN_AC7 -to upi1_tx_p[18] ;# GXPR11B_TX_CH18P -set_location_assignment PIN_AC8 -to upi1_tx_n[18] ;# GXPR11B_TX_CH18N -set_location_assignment PIN_AB5 -to upi1_tx_p[19] ;# GXPR11B_TX_CH19P -set_location_assignment PIN_AB6 -to upi1_tx_n[19] ;# GXPR11B_TX_CH19N -set_location_assignment PIN_BB1 -to upi1_rx_p[0] ;# GXPR11B_RX_CH0P -set_location_assignment PIN_BB2 -to upi1_rx_n[0] ;# GXPR11B_RX_CH0N -set_location_assignment PIN_BA3 -to upi1_rx_p[1] ;# GXPR11B_RX_CH1P -set_location_assignment PIN_BA4 -to upi1_rx_n[1] ;# GXPR11B_RX_CH1N -set_location_assignment PIN_AY1 -to upi1_rx_p[2] ;# GXPR11B_RX_CH2P -set_location_assignment PIN_AY2 -to upi1_rx_n[2] ;# GXPR11B_RX_CH2N -set_location_assignment PIN_AW3 -to upi1_rx_p[3] ;# GXPR11B_RX_CH3P -set_location_assignment PIN_AW4 -to upi1_rx_n[3] ;# GXPR11B_RX_CH3N -set_location_assignment PIN_AV1 -to upi1_rx_p[4] ;# GXPR11B_RX_CH4P -set_location_assignment PIN_AV2 -to upi1_rx_n[4] ;# GXPR11B_RX_CH4N -set_location_assignment PIN_AU3 -to upi1_rx_p[5] ;# GXPR11B_RX_CH5P -set_location_assignment PIN_AU4 -to upi1_rx_n[5] ;# GXPR11B_RX_CH5N -set_location_assignment PIN_AT1 -to upi1_rx_p[6] ;# GXPR11B_RX_CH6P -set_location_assignment PIN_AT2 -to upi1_rx_n[6] ;# GXPR11B_RX_CH6N -set_location_assignment PIN_AR3 -to upi1_rx_p[7] ;# GXPR11B_RX_CH7P -set_location_assignment PIN_AR4 -to upi1_rx_n[7] ;# GXPR11B_RX_CH7N -set_location_assignment PIN_AP1 -to upi1_rx_p[8] ;# GXPR11B_RX_CH8P -set_location_assignment PIN_AP2 -to upi1_rx_n[8] ;# GXPR11B_RX_CH8N -set_location_assignment PIN_AN3 -to upi1_rx_p[9] ;# GXPR11B_RX_CH9P -set_location_assignment PIN_AN4 -to upi1_rx_n[9] ;# GXPR11B_RX_CH9N -set_location_assignment PIN_AM1 -to upi1_rx_p[10] ;# GXPR11B_RX_CH10P -set_location_assignment PIN_AM2 -to upi1_rx_n[10] ;# GXPR11B_RX_CH10N -set_location_assignment PIN_AL3 -to upi1_rx_p[11] ;# GXPR11B_RX_CH11P -set_location_assignment PIN_AL4 -to upi1_rx_n[11] ;# GXPR11B_RX_CH11N -set_location_assignment PIN_AK1 -to upi1_rx_p[12] ;# GXPR11B_RX_CH12P -set_location_assignment PIN_AK2 -to upi1_rx_n[12] ;# GXPR11B_RX_CH12N -set_location_assignment PIN_AJ3 -to upi1_rx_p[13] ;# GXPR11B_RX_CH13P -set_location_assignment PIN_AJ4 -to upi1_rx_n[13] ;# GXPR11B_RX_CH13N -set_location_assignment PIN_AH1 -to upi1_rx_p[14] ;# GXPR11B_RX_CH14P -set_location_assignment PIN_AH2 -to upi1_rx_n[14] ;# GXPR11B_RX_CH14N -set_location_assignment PIN_AG3 -to upi1_rx_p[15] ;# GXPR11B_RX_CH15P -set_location_assignment PIN_AG4 -to upi1_rx_n[15] ;# GXPR11B_RX_CH15N -set_location_assignment PIN_AF1 -to upi1_rx_p[16] ;# GXPR11B_RX_CH16P -set_location_assignment PIN_AF2 -to upi1_rx_n[16] ;# GXPR11B_RX_CH16N -set_location_assignment PIN_AE3 -to upi1_rx_p[17] ;# GXPR11B_RX_CH17P -set_location_assignment PIN_AE4 -to upi1_rx_n[17] ;# GXPR11B_RX_CH17N -set_location_assignment PIN_AD1 -to upi1_rx_p[18] ;# GXPR11B_RX_CH18P -set_location_assignment PIN_AD2 -to upi1_rx_n[18] ;# GXPR11B_RX_CH18N -set_location_assignment PIN_AC3 -to upi1_rx_p[19] ;# GXPR11B_RX_CH19P -set_location_assignment PIN_AC4 -to upi1_rx_n[19] ;# GXPR11B_RX_CH19N - -set_location_assignment PIN_AH10 -to clk_100m_upi1_0_p ;# REFCLK_GXPR11B_CH0P -set_location_assignment PIN_AH11 -to clk_100m_upi1_0_n ;# REFCLK_GXPR11B_CH0N -set_location_assignment PIN_AF10 -to clk_100m_upi1_1_p ;# REFCLK_GXPR11B_CH2P -set_location_assignment PIN_AF11 -to clk_100m_upi1_1_n ;# REFCLK_GXPR11B_CH2N - -set_location_assignment PIN_AL11 -to upi1_rst_n - -set_location_assignment PIN_D38 -to upi1_lsio_tx[6] -set_location_assignment PIN_E38 -to upi1_lsio_tx[5] -set_location_assignment PIN_D40 -to upi1_lsio_tx[2] -set_location_assignment PIN_C40 -to upi1_lsio_tx[1] -set_location_assignment PIN_G39 -to upi1_lsio_rx[6] -set_location_assignment PIN_F39 -to upi1_lsio_rx[5] -set_location_assignment PIN_K37 -to upi1_lsio_rx[4] -set_location_assignment PIN_L37 -to upi1_lsio_rx[3] -set_location_assignment PIN_K39 -to upi1_lsio_rx[2] -set_location_assignment PIN_J39 -to upi1_lsio_rx[1] -set_location_assignment PIN_E42 -to upi1_lsio_tx[4] -set_location_assignment PIN_F42 -to upi1_lsio_tx[3] - -set_location_assignment PIN_H35 -to upi1_lsio_rx1_pcie_1v8 -set_location_assignment PIN_J35 -to upi1_lsio_rx2_pcie_1v8 -set_location_assignment PIN_L35 -to upi1_lsio_rx5_pcie_1v8 -set_location_assignment PIN_M35 -to upi1_lsio_rx6_pcie_1v8 - -set_location_assignment PIN_F29 -to s10_upi1_nid_1v8[0] -set_location_assignment PIN_G29 -to s10_upi1_nid_1v8[1] - -set_location_assignment PIN_N26 -to s10_upi1_perstn_sel -set_location_assignment PIN_R27 -to s10_upi1_prnstn_1v8 - -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_tx_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_tx_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_tx_p[2] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_tx_p[3] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_tx_p[4] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_tx_p[5] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_tx_p[6] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_tx_p[7] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_tx_p[8] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_tx_p[9] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_tx_p[10] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_tx_p[11] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_tx_p[12] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_tx_p[13] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_tx_p[14] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_tx_p[15] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_rx_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_rx_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_rx_p[2] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_rx_p[3] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_rx_p[4] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_rx_p[5] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_rx_p[6] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_rx_p[7] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_rx_p[8] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_rx_p[9] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_rx_p[10] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_rx_p[11] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_rx_p[12] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_rx_p[13] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_rx_p[14] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi1_rx_p[15] - -set_instance_assignment -name IO_STANDARD "HCSL" -to clk_100m_upi1_0_p -set_instance_assignment -name IO_STANDARD "HCSL" -to clk_100m_upi1_1_p - -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi1_lsio_rx[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi1_lsio_rx[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi1_lsio_rx[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi1_lsio_rx[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi1_lsio_rx[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi1_lsio_rx[6] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi1_lsio_tx[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi1_lsio_tx[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi1_lsio_tx[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi1_lsio_tx[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi1_lsio_tx[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi1_lsio_tx[6] - -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi1_lsio_rx1_pcie_1v8 -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi1_lsio_rx2_pcie_1v8 -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi1_lsio_rx5_pcie_1v8 -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi1_lsio_rx6_pcie_1v8 - -set_instance_assignment -name IO_STANDARD "1.8 V" -to s10_upi1_nid_1v8[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to s10_upi1_nid_1v8[1] - -set_instance_assignment -name IO_STANDARD "1.8 V" -to s10_upi1_perstn_sel -set_instance_assignment -name IO_STANDARD "1.8 V" -to s10_upi1_prnstn_1v8 - -# UPI2 -set_location_assignment PIN_AA7 -to upi2_tx_p[0] ;# GXPR11C_TX_CH0P -set_location_assignment PIN_AA8 -to upi2_tx_n[0] ;# GXPR11C_TX_CH0N -set_location_assignment PIN_Y5 -to upi2_tx_p[1] ;# GXPR11C_TX_CH1P -set_location_assignment PIN_Y6 -to upi2_tx_n[1] ;# GXPR11C_TX_CH1N -set_location_assignment PIN_W7 -to upi2_tx_p[2] ;# GXPR11C_TX_CH2P -set_location_assignment PIN_W8 -to upi2_tx_n[2] ;# GXPR11C_TX_CH2N -set_location_assignment PIN_V5 -to upi2_tx_p[3] ;# GXPR11C_TX_CH3P -set_location_assignment PIN_V6 -to upi2_tx_n[3] ;# GXPR11C_TX_CH3N -set_location_assignment PIN_U7 -to upi2_tx_p[4] ;# GXPR11C_TX_CH4P -set_location_assignment PIN_U8 -to upi2_tx_n[4] ;# GXPR11C_TX_CH4N -set_location_assignment PIN_T5 -to upi2_tx_p[5] ;# GXPR11C_TX_CH5P -set_location_assignment PIN_T6 -to upi2_tx_n[5] ;# GXPR11C_TX_CH5N -set_location_assignment PIN_R7 -to upi2_tx_p[6] ;# GXPR11C_TX_CH6P -set_location_assignment PIN_R8 -to upi2_tx_n[6] ;# GXPR11C_TX_CH6N -set_location_assignment PIN_P5 -to upi2_tx_p[7] ;# GXPR11C_TX_CH7P -set_location_assignment PIN_P6 -to upi2_tx_n[7] ;# GXPR11C_TX_CH7N -set_location_assignment PIN_N7 -to upi2_tx_p[8] ;# GXPR11C_TX_CH8P -set_location_assignment PIN_N8 -to upi2_tx_n[8] ;# GXPR11C_TX_CH8N -set_location_assignment PIN_M5 -to upi2_tx_p[9] ;# GXPR11C_TX_CH9P -set_location_assignment PIN_M6 -to upi2_tx_n[9] ;# GXPR11C_TX_CH9N -set_location_assignment PIN_L7 -to upi2_tx_p[10] ;# GXPR11C_TX_CH10P -set_location_assignment PIN_L8 -to upi2_tx_n[10] ;# GXPR11C_TX_CH10N -set_location_assignment PIN_K5 -to upi2_tx_p[11] ;# GXPR11C_TX_CH11P -set_location_assignment PIN_K6 -to upi2_tx_n[11] ;# GXPR11C_TX_CH11N -set_location_assignment PIN_J7 -to upi2_tx_p[12] ;# GXPR11C_TX_CH12P -set_location_assignment PIN_J8 -to upi2_tx_n[12] ;# GXPR11C_TX_CH12N -set_location_assignment PIN_H5 -to upi2_tx_p[13] ;# GXPR11C_TX_CH13P -set_location_assignment PIN_H6 -to upi2_tx_n[13] ;# GXPR11C_TX_CH13N -set_location_assignment PIN_G7 -to upi2_tx_p[14] ;# GXPR11C_TX_CH14P -set_location_assignment PIN_G8 -to upi2_tx_n[14] ;# GXPR11C_TX_CH14N -set_location_assignment PIN_F5 -to upi2_tx_p[15] ;# GXPR11C_TX_CH15P -set_location_assignment PIN_F6 -to upi2_tx_n[15] ;# GXPR11C_TX_CH15N -set_location_assignment PIN_E7 -to upi2_tx_p[16] ;# GXPR11C_TX_CH16P -set_location_assignment PIN_E8 -to upi2_tx_n[16] ;# GXPR11C_TX_CH16N -set_location_assignment PIN_D5 -to upi2_tx_p[17] ;# GXPR11C_TX_CH17P -set_location_assignment PIN_D6 -to upi2_tx_n[17] ;# GXPR11C_TX_CH17N -set_location_assignment PIN_C7 -to upi2_tx_p[18] ;# GXPR11C_TX_CH18P -set_location_assignment PIN_C8 -to upi2_tx_n[18] ;# GXPR11C_TX_CH18N -set_location_assignment PIN_B5 -to upi2_tx_p[19] ;# GXPR11C_TX_CH19P -set_location_assignment PIN_B6 -to upi2_tx_n[19] ;# GXPR11C_TX_CH19N -set_location_assignment PIN_AB1 -to upi2_rx_p[0] ;# GXPR11C_RX_CH0P -set_location_assignment PIN_AB2 -to upi2_rx_n[0] ;# GXPR11C_RX_CH0N -set_location_assignment PIN_AA3 -to upi2_rx_p[1] ;# GXPR11C_RX_CH1P -set_location_assignment PIN_AA4 -to upi2_rx_n[1] ;# GXPR11C_RX_CH1N -set_location_assignment PIN_Y1 -to upi2_rx_p[2] ;# GXPR11C_RX_CH2P -set_location_assignment PIN_Y2 -to upi2_rx_n[2] ;# GXPR11C_RX_CH2N -set_location_assignment PIN_W3 -to upi2_rx_p[3] ;# GXPR11C_RX_CH3P -set_location_assignment PIN_W4 -to upi2_rx_n[3] ;# GXPR11C_RX_CH3N -set_location_assignment PIN_V1 -to upi2_rx_p[4] ;# GXPR11C_RX_CH4P -set_location_assignment PIN_V2 -to upi2_rx_n[4] ;# GXPR11C_RX_CH4N -set_location_assignment PIN_U3 -to upi2_rx_p[5] ;# GXPR11C_RX_CH5P -set_location_assignment PIN_U4 -to upi2_rx_n[5] ;# GXPR11C_RX_CH5N -set_location_assignment PIN_T1 -to upi2_rx_p[6] ;# GXPR11C_RX_CH6P -set_location_assignment PIN_T2 -to upi2_rx_n[6] ;# GXPR11C_RX_CH6N -set_location_assignment PIN_R3 -to upi2_rx_p[7] ;# GXPR11C_RX_CH7P -set_location_assignment PIN_R4 -to upi2_rx_n[7] ;# GXPR11C_RX_CH7N -set_location_assignment PIN_P1 -to upi2_rx_p[8] ;# GXPR11C_RX_CH8P -set_location_assignment PIN_P2 -to upi2_rx_n[8] ;# GXPR11C_RX_CH8N -set_location_assignment PIN_N3 -to upi2_rx_p[9] ;# GXPR11C_RX_CH9P -set_location_assignment PIN_N4 -to upi2_rx_n[9] ;# GXPR11C_RX_CH9N -set_location_assignment PIN_M1 -to upi2_rx_p[10] ;# GXPR11C_RX_CH10P -set_location_assignment PIN_M2 -to upi2_rx_n[10] ;# GXPR11C_RX_CH10N -set_location_assignment PIN_L3 -to upi2_rx_p[11] ;# GXPR11C_RX_CH11P -set_location_assignment PIN_L4 -to upi2_rx_n[11] ;# GXPR11C_RX_CH11N -set_location_assignment PIN_K1 -to upi2_rx_p[12] ;# GXPR11C_RX_CH12P -set_location_assignment PIN_K2 -to upi2_rx_n[12] ;# GXPR11C_RX_CH12N -set_location_assignment PIN_J3 -to upi2_rx_p[13] ;# GXPR11C_RX_CH13P -set_location_assignment PIN_J4 -to upi2_rx_n[13] ;# GXPR11C_RX_CH13N -set_location_assignment PIN_H1 -to upi2_rx_p[14] ;# GXPR11C_RX_CH14P -set_location_assignment PIN_H2 -to upi2_rx_n[14] ;# GXPR11C_RX_CH14N -set_location_assignment PIN_G3 -to upi2_rx_p[15] ;# GXPR11C_RX_CH15P -set_location_assignment PIN_G4 -to upi2_rx_n[15] ;# GXPR11C_RX_CH15N -set_location_assignment PIN_F1 -to upi2_rx_p[16] ;# GXPR11C_RX_CH16P -set_location_assignment PIN_F2 -to upi2_rx_n[16] ;# GXPR11C_RX_CH16N -set_location_assignment PIN_E3 -to upi2_rx_p[17] ;# GXPR11C_RX_CH17P -set_location_assignment PIN_E4 -to upi2_rx_n[17] ;# GXPR11C_RX_CH17N -set_location_assignment PIN_D1 -to upi2_rx_p[18] ;# GXPR11C_RX_CH18P -set_location_assignment PIN_D2 -to upi2_rx_n[18] ;# GXPR11C_RX_CH18N -set_location_assignment PIN_C3 -to upi2_rx_p[19] ;# GXPR11C_RX_CH19P -set_location_assignment PIN_C4 -to upi2_rx_n[19] ;# GXPR11C_RX_CH19N - -set_location_assignment PIN_V10 -to clk_100m_upi2_0_p ;# REFCLK_GXPR11C_CH0P -set_location_assignment PIN_V11 -to clk_100m_upi2_0_n ;# REFCLK_GXPR11C_CH0N -set_location_assignment PIN_T10 -to clk_100m_upi2_1_p ;# REFCLK_GXPR11C_CH2P -set_location_assignment PIN_T11 -to clk_100m_upi2_1_n ;# REFCLK_GXPR11C_CH2N - -set_location_assignment PIN_AA11 -to upi2_rst_n - -set_location_assignment PIN_P38 -to upi2_lsio_tx[1] -set_location_assignment PIN_R38 -to upi2_lsio_tx[2] -set_location_assignment PIN_L39 -to upi2_lsio_tx[3] -set_location_assignment PIN_M39 -to upi2_lsio_tx[4] -set_location_assignment PIN_N38 -to upi2_lsio_tx[5] -set_location_assignment PIN_M38 -to upi2_lsio_tx[6] -set_location_assignment PIN_R37 -to upi2_lsio_rx[1] -set_location_assignment PIN_R36 -to upi2_lsio_rx[2] -set_location_assignment PIN_M37 -to upi2_lsio_rx[3] -set_location_assignment PIN_N37 -to upi2_lsio_rx[4] -set_location_assignment PIN_R39 -to upi2_lsio_rx[5] -set_location_assignment PIN_P39 -to upi2_lsio_rx[6] - -set_location_assignment PIN_J36 -to upi2_lsio_rx1_pcie_1v8 -set_location_assignment PIN_H36 -to upi2_lsio_rx2_pcie_1v8 -set_location_assignment PIN_P33 -to upi2_lsio_rx5_pcie_1v8 -set_location_assignment PIN_R33 -to upi2_lsio_rx6_pcie_1v8 - -set_location_assignment PIN_E28 -to s10_upi2_nid_1v8[0] -set_location_assignment PIN_D28 -to s10_upi2_nid_1v8[1] - -set_location_assignment PIN_P28 -to s10_upi2_perstn_sel -set_location_assignment PIN_N27 -to s10_upi2_prnstn_1v8 - -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_tx_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_tx_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_tx_p[2] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_tx_p[3] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_tx_p[4] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_tx_p[5] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_tx_p[6] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_tx_p[7] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_tx_p[8] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_tx_p[9] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_tx_p[10] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_tx_p[11] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_tx_p[12] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_tx_p[13] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_tx_p[14] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_tx_p[15] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_rx_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_rx_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_rx_p[2] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_rx_p[3] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_rx_p[4] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_rx_p[5] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_rx_p[6] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_rx_p[7] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_rx_p[8] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_rx_p[9] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_rx_p[10] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_rx_p[11] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_rx_p[12] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_rx_p[13] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_rx_p[14] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to upi2_rx_p[15] - -set_instance_assignment -name IO_STANDARD "HCSL" -to clk_100m_upi2_0_p -set_instance_assignment -name IO_STANDARD "HCSL" -to clk_100m_upi2_1_p - -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi2_lsio_rx[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi2_lsio_rx[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi2_lsio_rx[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi2_lsio_rx[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi2_lsio_rx[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi2_lsio_rx[6] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi2_lsio_tx[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi2_lsio_tx[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi2_lsio_tx[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi2_lsio_tx[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi2_lsio_tx[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi2_lsio_tx[6] - -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi2_lsio_rx1_pcie_1v8 -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi2_lsio_rx2_pcie_1v8 -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi2_lsio_rx5_pcie_1v8 -set_instance_assignment -name IO_STANDARD "1.8 V" -to upi2_lsio_rx6_pcie_1v8 - -set_instance_assignment -name IO_STANDARD "1.8 V" -to s10_upi2_nid_1v8[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to s10_upi2_nid_1v8[1] - -set_instance_assignment -name IO_STANDARD "1.8 V" -to s10_upi2_perstn_sel -set_instance_assignment -name IO_STANDARD "1.8 V" -to s10_upi2_prnstn_1v8 - -# QSFP -set_location_assignment PIN_BP4 -to qsfp1_tx_p[0] ;# GXER9A_TX_CH0P -set_location_assignment PIN_BP5 -to qsfp1_tx_n[0] ;# GXER9A_TX_CH0N -set_location_assignment PIN_BL1 -to qsfp1_tx_p[1] ;# GXER9A_TX_CH2P -set_location_assignment PIN_BL2 -to qsfp1_tx_n[1] ;# GXER9A_TX_CH2N -set_location_assignment PIN_BM4 -to qsfp1_tx_p[2] ;# GXER9A_TX_CH1P -set_location_assignment PIN_BM5 -to qsfp1_tx_n[2] ;# GXER9A_TX_CH1N -set_location_assignment PIN_BK4 -to qsfp1_tx_p[3] ;# GXER9A_TX_CH3P -set_location_assignment PIN_BK5 -to qsfp1_tx_n[3] ;# GXER9A_TX_CH3N - -set_location_assignment PIN_BN7 -to qsfp1_rx_p[0] ;# GXER9A_RX_CH0P -set_location_assignment PIN_BN8 -to qsfp1_rx_n[0] ;# GXER9A_RX_CH0N -set_location_assignment PIN_BJ7 -to qsfp1_rx_p[1] ;# GXER9A_RX_CH2P -set_location_assignment PIN_BJ8 -to qsfp1_rx_n[1] ;# GXER9A_RX_CH2N -set_location_assignment PIN_BL7 -to qsfp1_rx_p[2] ;# GXER9A_RX_CH1P -set_location_assignment PIN_BL8 -to qsfp1_rx_n[2] ;# GXER9A_RX_CH1N -set_location_assignment PIN_BG7 -to qsfp1_rx_p[3] ;# GXER9A_RX_CH3P -set_location_assignment PIN_BG8 -to qsfp1_rx_n[3] ;# GXER9A_RX_CH3N - -set_location_assignment PIN_BJ1 -to qsfp2_tx_p[0] ;# GXER9A_TX_CH12P -set_location_assignment PIN_BJ2 -to qsfp2_tx_n[0] ;# GXER9A_TX_CH12N -set_location_assignment PIN_BG1 -to qsfp2_tx_p[1] ;# GXER9A_TX_CH14P -set_location_assignment PIN_BG2 -to qsfp2_tx_n[1] ;# GXER9A_TX_CH14N -set_location_assignment PIN_BH4 -to qsfp2_tx_p[2] ;# GXER9A_TX_CH13P -set_location_assignment PIN_BH5 -to qsfp2_tx_n[2] ;# GXER9A_TX_CH13N -set_location_assignment PIN_BE1 -to qsfp2_tx_p[3] ;# GXER9A_TX_CH15P -set_location_assignment PIN_BE2 -to qsfp2_tx_n[3] ;# GXER9A_TX_CH15N - -set_location_assignment PIN_BF4 -to qsfp2_rx_p[0] ;# GXER9A_RX_CH12P -set_location_assignment PIN_BF5 -to qsfp2_rx_n[0] ;# GXER9A_RX_CH12N -set_location_assignment PIN_BD4 -to qsfp2_rx_p[1] ;# GXER9A_RX_CH14P -set_location_assignment PIN_BD5 -to qsfp2_rx_n[1] ;# GXER9A_RX_CH14N -set_location_assignment PIN_BE7 -to qsfp2_rx_p[2] ;# GXER9A_RX_CH13P -set_location_assignment PIN_BE8 -to qsfp2_rx_n[2] ;# GXER9A_RX_CH13N -set_location_assignment PIN_BC7 -to qsfp2_rx_p[3] ;# GXER9A_RX_CH15P -set_location_assignment PIN_BC8 -to qsfp2_rx_n[3] ;# GXER9A_RX_CH15N - -set_location_assignment PIN_AT11 -to clk_156p25m_qsfp0_p ;# REFCLK_GXER9A_CH0P -set_location_assignment PIN_AU11 -to clk_156p25m_qsfp0_n ;# REFCLK_GXER9A_CH0N -set_location_assignment PIN_AW11 -to clk_156p25m_qsfp1_p ;# REFCLK_GXER9A_CH1P -set_location_assignment PIN_AY11 -to clk_156p25m_qsfp1_n ;# REFCLK_GXER9A_CH1N -set_location_assignment PIN_AT10 -to clk_312p5m_qsfp0_p ;# REFCLK_GXER9A_CH2P -set_location_assignment PIN_AU10 -to clk_312p5m_qsfp0_n ;# REFCLK_GXER9A_CH2N -set_location_assignment PIN_AV10 -to clk_312p5m_qsfp1_p ;# REFCLK_GXER9A_CH3P -set_location_assignment PIN_AW10 -to clk_312p5m_qsfp1_n ;# REFCLK_GXER9A_CH3N -set_location_assignment PIN_BC11 -to clk_312p5m_qsfp2_p ;# REFCLK_GXER9A_CH8P -set_location_assignment PIN_BC10 -to clk_312p5m_qsfp2_n ;# REFCLK_GXER9A_CH8N - -set_location_assignment PIN_D33 -to zqsfp_1v8_port_en -set_location_assignment PIN_H32 -to zqsfp_1v8_port_int_n - -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp1_tx_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp1_tx_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp1_tx_p[2] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp1_tx_p[3] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp1_rx_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp1_rx_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp1_rx_p[2] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp1_rx_p[3] - -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp2_tx_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp2_tx_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp2_tx_p[2] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp2_tx_p[3] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp2_rx_p[0] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp2_rx_p[1] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp2_rx_p[2] -set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp2_rx_p[3] - -set_instance_assignment -name IO_STANDARD "1.8 V" -to zqsfp_1v8_port_en -set_instance_assignment -name IO_STANDARD "1.8 V" -to zqsfp_1v8_port_int_n - -set_instance_assignment -name IO_STANDARD "Differential LVPECL" -to clk_156p25m_qsfp0_p -set_instance_assignment -name IO_STANDARD "Differential LVPECL" -to clk_156p25m_qsfp1_p -set_instance_assignment -name IO_STANDARD "Differential LVPECL" -to clk_312p5m_qsfp0_p -set_instance_assignment -name IO_STANDARD "Differential LVPECL" -to clk_312p5m_qsfp1_p -set_instance_assignment -name IO_STANDARD "Differential LVPECL" -to clk_312p5m_qsfp2_p - -set_instance_assignment -name HSSI_PARAMETER "refclk_divider_use_as_bti_clock=true" -to clk_156p25m_qsfp0_p -set_instance_assignment -name HSSI_PARAMETER "refclk_divider_input_freq=156250000" -to clk_156p25m_qsfp0_p - -# DDR4 CH0 -set_location_assignment PIN_H18 -to ddr4_ch0_rzq - -set_location_assignment PIN_L34 -to ddr4_ch0_ten_1v8 -set_location_assignment PIN_E14 -to ddr4_ch0_alert_n -set_location_assignment PIN_E17 -to ddr4_ch0_reset_n -set_location_assignment PIN_D14 -to ddr4_ch0_par - -set_location_assignment PIN_A17 -to ddr4_ch0_a[0] -set_location_assignment PIN_A16 -to ddr4_ch0_a[1] -set_location_assignment PIN_D15 -to ddr4_ch0_a[2] -set_location_assignment PIN_C15 -to ddr4_ch0_a[3] -set_location_assignment PIN_C16 -to ddr4_ch0_a[4] -set_location_assignment PIN_D16 -to ddr4_ch0_a[5] -set_location_assignment PIN_B14 -to ddr4_ch0_a[6] -set_location_assignment PIN_A14 -to ddr4_ch0_a[7] -set_location_assignment PIN_B17 -to ddr4_ch0_a[8] -set_location_assignment PIN_C17 -to ddr4_ch0_a[9] -set_location_assignment PIN_B15 -to ddr4_ch0_a[10] -set_location_assignment PIN_A15 -to ddr4_ch0_a[11] -set_location_assignment PIN_G18 -to ddr4_ch0_a[12] -set_location_assignment PIN_G20 -to ddr4_ch0_a[13] -set_location_assignment PIN_F20 -to ddr4_ch0_a[14] -set_location_assignment PIN_E19 -to ddr4_ch0_a[15] -set_location_assignment PIN_F19 -to ddr4_ch0_a[16] -set_location_assignment PIN_H20 -to ddr4_ch0_bg[0] -set_location_assignment PIN_E18 -to ddr4_ch0_bg[1] -set_location_assignment PIN_F14 -to ddr4_ch0_act_n -set_location_assignment PIN_F16 -to ddr4_ch0_odt -set_location_assignment PIN_F17 -to ddr4_ch0_ck_p -set_location_assignment PIN_G17 -to ddr4_ch0_ck_n -set_location_assignment PIN_G14 -to ddr4_ch0_cs_n -set_location_assignment PIN_G15 -to ddr4_ch0_cke -set_location_assignment PIN_G22 -to ddr4_ch0_ba[0] -set_location_assignment PIN_G19 -to ddr4_ch0_ba[1] - -set_location_assignment PIN_J10 -to ddr4_ch0_dm[0] -set_location_assignment PIN_H10 -to ddr4_ch0_dm[1] -set_location_assignment PIN_A9 -to ddr4_ch0_dm[2] -set_location_assignment PIN_E23 -to ddr4_ch0_dm[3] -set_location_assignment PIN_D19 -to ddr4_ch0_dm[4] -set_location_assignment PIN_T24 -to ddr4_ch0_dm[5] -set_location_assignment PIN_K16 -to ddr4_ch0_dm[6] -set_location_assignment PIN_M25 -to ddr4_ch0_dm[7] -set_location_assignment PIN_K22 -to ddr4_ch0_dm[8] - -set_location_assignment PIN_K13 -to ddr4_ch0_dqs_p[0] -set_location_assignment PIN_J13 -to ddr4_ch0_dqs_n[0] -set_location_assignment PIN_F12 -to ddr4_ch0_dqs_p[1] -set_location_assignment PIN_G12 -to ddr4_ch0_dqs_n[1] -set_location_assignment PIN_D10 -to ddr4_ch0_dqs_p[2] -set_location_assignment PIN_C10 -to ddr4_ch0_dqs_n[2] -set_location_assignment PIN_D21 -to ddr4_ch0_dqs_p[3] -set_location_assignment PIN_C21 -to ddr4_ch0_dqs_n[3] -set_location_assignment PIN_D20 -to ddr4_ch0_dqs_p[4] -set_location_assignment PIN_C20 -to ddr4_ch0_dqs_n[4] -set_location_assignment PIN_R24 -to ddr4_ch0_dqs_p[5] -set_location_assignment PIN_P24 -to ddr4_ch0_dqs_n[5] -set_location_assignment PIN_H16 -to ddr4_ch0_dqs_p[6] -set_location_assignment PIN_J16 -to ddr4_ch0_dqs_n[6] -set_location_assignment PIN_J24 -to ddr4_ch0_dqs_p[7] -set_location_assignment PIN_K24 -to ddr4_ch0_dqs_n[7] -set_location_assignment PIN_M22 -to ddr4_ch0_dqs_p[8] -set_location_assignment PIN_N22 -to ddr4_ch0_dqs_n[8] - -set_location_assignment PIN_H11 -to ddr4_ch0_dq[0] -set_location_assignment PIN_H12 -to ddr4_ch0_dq[1] -set_location_assignment PIN_K11 -to ddr4_ch0_dq[2] -set_location_assignment PIN_K12 -to ddr4_ch0_dq[3] -set_location_assignment PIN_J14 -to ddr4_ch0_dq[4] -set_location_assignment PIN_H13 -to ddr4_ch0_dq[5] -set_location_assignment PIN_K14 -to ddr4_ch0_dq[6] -set_location_assignment PIN_G13 -to ddr4_ch0_dq[7] -set_location_assignment PIN_D11 -to ddr4_ch0_dq[8] -set_location_assignment PIN_E13 -to ddr4_ch0_dq[9] -set_location_assignment PIN_D13 -to ddr4_ch0_dq[10] -set_location_assignment PIN_F10 -to ddr4_ch0_dq[11] -set_location_assignment PIN_C11 -to ddr4_ch0_dq[12] -set_location_assignment PIN_F11 -to ddr4_ch0_dq[13] -set_location_assignment PIN_E11 -to ddr4_ch0_dq[14] -set_location_assignment PIN_E12 -to ddr4_ch0_dq[15] -set_location_assignment PIN_A11 -to ddr4_ch0_dq[16] -set_location_assignment PIN_B10 -to ddr4_ch0_dq[17] -set_location_assignment PIN_B12 -to ddr4_ch0_dq[18] -set_location_assignment PIN_A12 -to ddr4_ch0_dq[19] -set_location_assignment PIN_C12 -to ddr4_ch0_dq[20] -set_location_assignment PIN_A10 -to ddr4_ch0_dq[21] -set_location_assignment PIN_B13 -to ddr4_ch0_dq[22] -set_location_assignment PIN_C13 -to ddr4_ch0_dq[23] -set_location_assignment PIN_D24 -to ddr4_ch0_dq[24] -set_location_assignment PIN_G25 -to ddr4_ch0_dq[25] -set_location_assignment PIN_E24 -to ddr4_ch0_dq[26] -set_location_assignment PIN_B22 -to ddr4_ch0_dq[27] -set_location_assignment PIN_D25 -to ddr4_ch0_dq[28] -set_location_assignment PIN_F25 -to ddr4_ch0_dq[29] -set_location_assignment PIN_D23 -to ddr4_ch0_dq[30] -set_location_assignment PIN_C22 -to ddr4_ch0_dq[31] -set_location_assignment PIN_B19 -to ddr4_ch0_dq[32] -set_location_assignment PIN_A20 -to ddr4_ch0_dq[33] -set_location_assignment PIN_A21 -to ddr4_ch0_dq[34] -set_location_assignment PIN_B20 -to ddr4_ch0_dq[35] -set_location_assignment PIN_A22 -to ddr4_ch0_dq[36] -set_location_assignment PIN_B18 -to ddr4_ch0_dq[37] -set_location_assignment PIN_C18 -to ddr4_ch0_dq[38] -set_location_assignment PIN_A19 -to ddr4_ch0_dq[39] -set_location_assignment PIN_P25 -to ddr4_ch0_dq[40] -set_location_assignment PIN_M24 -to ddr4_ch0_dq[41] -set_location_assignment PIN_N25 -to ddr4_ch0_dq[42] -set_location_assignment PIN_L24 -to ddr4_ch0_dq[43] -set_location_assignment PIN_R23 -to ddr4_ch0_dq[44] -set_location_assignment PIN_P23 -to ddr4_ch0_dq[45] -set_location_assignment PIN_N23 -to ddr4_ch0_dq[46] -set_location_assignment PIN_M23 -to ddr4_ch0_dq[47] -set_location_assignment PIN_J18 -to ddr4_ch0_dq[48] -set_location_assignment PIN_H15 -to ddr4_ch0_dq[49] -set_location_assignment PIN_K19 -to ddr4_ch0_dq[50] -set_location_assignment PIN_K18 -to ddr4_ch0_dq[51] -set_location_assignment PIN_J19 -to ddr4_ch0_dq[52] -set_location_assignment PIN_J15 -to ddr4_ch0_dq[53] -set_location_assignment PIN_J20 -to ddr4_ch0_dq[54] -set_location_assignment PIN_H17 -to ddr4_ch0_dq[55] -set_location_assignment PIN_J25 -to ddr4_ch0_dq[56] -set_location_assignment PIN_F24 -to ddr4_ch0_dq[57] -set_location_assignment PIN_G24 -to ddr4_ch0_dq[58] -set_location_assignment PIN_H23 -to ddr4_ch0_dq[59] -set_location_assignment PIN_G23 -to ddr4_ch0_dq[60] -set_location_assignment PIN_H25 -to ddr4_ch0_dq[61] -set_location_assignment PIN_K23 -to ddr4_ch0_dq[62] -set_location_assignment PIN_J23 -to ddr4_ch0_dq[63] -set_location_assignment PIN_K21 -to ddr4_ch0_dq[64] -set_location_assignment PIN_N21 -to ddr4_ch0_dq[65] -set_location_assignment PIN_H22 -to ddr4_ch0_dq[66] -set_location_assignment PIN_H21 -to ddr4_ch0_dq[67] -set_location_assignment PIN_R22 -to ddr4_ch0_dq[68] -set_location_assignment PIN_P21 -to ddr4_ch0_dq[69] -set_location_assignment PIN_J21 -to ddr4_ch0_dq[70] -set_location_assignment PIN_R21 -to ddr4_ch0_dq[71] - -# DDR4 CH1 -set_location_assignment PIN_G48 -to ddr4_ch1_rzq - -set_location_assignment PIN_M34 -to ddr4_ch1_ten_1v8 -set_location_assignment PIN_A51 -to ddr4_ch1_alert_n -set_location_assignment PIN_E51 -to ddr4_ch1_reset_n -set_location_assignment PIN_A50 -to ddr4_ch1_par - -set_location_assignment PIN_A49 -to ddr4_ch1_a[0] -set_location_assignment PIN_B49 -to ddr4_ch1_a[1] -set_location_assignment PIN_G50 -to ddr4_ch1_a[2] -set_location_assignment PIN_F50 -to ddr4_ch1_a[3] -set_location_assignment PIN_E49 -to ddr4_ch1_a[4] -set_location_assignment PIN_F49 -to ddr4_ch1_a[5] -set_location_assignment PIN_D50 -to ddr4_ch1_a[6] -set_location_assignment PIN_D49 -to ddr4_ch1_a[7] -set_location_assignment PIN_E48 -to ddr4_ch1_a[8] -set_location_assignment PIN_D48 -to ddr4_ch1_a[9] -set_location_assignment PIN_B48 -to ddr4_ch1_a[10] -set_location_assignment PIN_C48 -to ddr4_ch1_a[11] -set_location_assignment PIN_G49 -to ddr4_ch1_a[12] -set_location_assignment PIN_J46 -to ddr4_ch1_a[13] -set_location_assignment PIN_H46 -to ddr4_ch1_a[14] -set_location_assignment PIN_J48 -to ddr4_ch1_a[15] -set_location_assignment PIN_H48 -to ddr4_ch1_a[16] -set_location_assignment PIN_G47 -to ddr4_ch1_bg[0] -set_location_assignment PIN_F51 -to ddr4_ch1_bg[1] -set_location_assignment PIN_B53 -to ddr4_ch1_act_n -set_location_assignment PIN_D51 -to ddr4_ch1_odt -set_location_assignment PIN_B50 -to ddr4_ch1_ck_p -set_location_assignment PIN_C50 -to ddr4_ch1_ck_n -set_location_assignment PIN_C53 -to ddr4_ch1_cs_n -set_location_assignment PIN_C52 -to ddr4_ch1_cke -set_location_assignment PIN_K43 -to ddr4_ch1_ba[0] -set_location_assignment PIN_H47 -to ddr4_ch1_ba[1] - -set_location_assignment PIN_J54 -to ddr4_ch1_dm[0] -set_location_assignment PIN_F52 -to ddr4_ch1_dm[1] -set_location_assignment PIN_G45 -to ddr4_ch1_dm[2] -set_location_assignment PIN_H50 -to ddr4_ch1_dm[3] -set_location_assignment PIN_C46 -to ddr4_ch1_dm[4] -set_location_assignment PIN_T44 -to ddr4_ch1_dm[5] -set_location_assignment PIN_P43 -to ddr4_ch1_dm[6] -set_location_assignment PIN_T41 -to ddr4_ch1_dm[7] -set_location_assignment PIN_H41 -to ddr4_ch1_dm[8] - -set_location_assignment PIN_J51 -to ddr4_ch1_dqs_p[0] -set_location_assignment PIN_K51 -to ddr4_ch1_dqs_n[0] -set_location_assignment PIN_G53 -to ddr4_ch1_dqs_p[1] -set_location_assignment PIN_H53 -to ddr4_ch1_dqs_n[1] -set_location_assignment PIN_F44 -to ddr4_ch1_dqs_p[2] -set_location_assignment PIN_G44 -to ddr4_ch1_dqs_n[2] -set_location_assignment PIN_L49 -to ddr4_ch1_dqs_p[3] -set_location_assignment PIN_K49 -to ddr4_ch1_dqs_n[3] -set_location_assignment PIN_C45 -to ddr4_ch1_dqs_p[4] -set_location_assignment PIN_D45 -to ddr4_ch1_dqs_n[4] -set_location_assignment PIN_N45 -to ddr4_ch1_dqs_p[5] -set_location_assignment PIN_M45 -to ddr4_ch1_dqs_n[5] -set_location_assignment PIN_M42 -to ddr4_ch1_dqs_p[6] -set_location_assignment PIN_N42 -to ddr4_ch1_dqs_n[6] -set_location_assignment PIN_P41 -to ddr4_ch1_dqs_p[7] -set_location_assignment PIN_N41 -to ddr4_ch1_dqs_n[7] -set_location_assignment PIN_K41 -to ddr4_ch1_dqs_p[8] -set_location_assignment PIN_L41 -to ddr4_ch1_dqs_n[8] - -set_location_assignment PIN_K53 -to ddr4_ch1_dq[0] -set_location_assignment PIN_L52 -to ddr4_ch1_dq[1] -set_location_assignment PIN_K52 -to ddr4_ch1_dq[2] -set_location_assignment PIN_M53 -to ddr4_ch1_dq[3] -set_location_assignment PIN_K54 -to ddr4_ch1_dq[4] -set_location_assignment PIN_M52 -to ddr4_ch1_dq[5] -set_location_assignment PIN_L54 -to ddr4_ch1_dq[6] -set_location_assignment PIN_M54 -to ddr4_ch1_dq[7] -set_location_assignment PIN_E53 -to ddr4_ch1_dq[8] -set_location_assignment PIN_D53 -to ddr4_ch1_dq[9] -set_location_assignment PIN_F54 -to ddr4_ch1_dq[10] -set_location_assignment PIN_E54 -to ddr4_ch1_dq[11] -set_location_assignment PIN_G54 -to ddr4_ch1_dq[12] -set_location_assignment PIN_D54 -to ddr4_ch1_dq[13] -set_location_assignment PIN_G52 -to ddr4_ch1_dq[14] -set_location_assignment PIN_H52 -to ddr4_ch1_dq[15] -set_location_assignment PIN_E46 -to ddr4_ch1_dq[16] -set_location_assignment PIN_D43 -to ddr4_ch1_dq[17] -set_location_assignment PIN_F47 -to ddr4_ch1_dq[18] -set_location_assignment PIN_D44 -to ddr4_ch1_dq[19] -set_location_assignment PIN_E47 -to ddr4_ch1_dq[20] -set_location_assignment PIN_E43 -to ddr4_ch1_dq[21] -set_location_assignment PIN_F46 -to ddr4_ch1_dq[22] -set_location_assignment PIN_E44 -to ddr4_ch1_dq[23] -set_location_assignment PIN_L50 -to ddr4_ch1_dq[24] -set_location_assignment PIN_K47 -to ddr4_ch1_dq[25] -set_location_assignment PIN_M50 -to ddr4_ch1_dq[26] -set_location_assignment PIN_M49 -to ddr4_ch1_dq[27] -set_location_assignment PIN_J50 -to ddr4_ch1_dq[28] -set_location_assignment PIN_K48 -to ddr4_ch1_dq[29] -set_location_assignment PIN_L51 -to ddr4_ch1_dq[30] -set_location_assignment PIN_J49 -to ddr4_ch1_dq[31] -set_location_assignment PIN_B45 -to ddr4_ch1_dq[32] -set_location_assignment PIN_C47 -to ddr4_ch1_dq[33] -set_location_assignment PIN_A45 -to ddr4_ch1_dq[34] -set_location_assignment PIN_A44 -to ddr4_ch1_dq[35] -set_location_assignment PIN_A46 -to ddr4_ch1_dq[36] -set_location_assignment PIN_B44 -to ddr4_ch1_dq[37] -set_location_assignment PIN_B47 -to ddr4_ch1_dq[38] -set_location_assignment PIN_A47 -to ddr4_ch1_dq[39] -set_location_assignment PIN_M47 -to ddr4_ch1_dq[40] -set_location_assignment PIN_P44 -to ddr4_ch1_dq[41] -set_location_assignment PIN_L46 -to ddr4_ch1_dq[42] -set_location_assignment PIN_N46 -to ddr4_ch1_dq[43] -set_location_assignment PIN_L47 -to ddr4_ch1_dq[44] -set_location_assignment PIN_P45 -to ddr4_ch1_dq[45] -set_location_assignment PIN_M48 -to ddr4_ch1_dq[46] -set_location_assignment PIN_N47 -to ddr4_ch1_dq[47] -set_location_assignment PIN_N43 -to ddr4_ch1_dq[48] -set_location_assignment PIN_R42 -to ddr4_ch1_dq[49] -set_location_assignment PIN_M43 -to ddr4_ch1_dq[50] -set_location_assignment PIN_T42 -to ddr4_ch1_dq[51] -set_location_assignment PIN_M44 -to ddr4_ch1_dq[52] -set_location_assignment PIN_K46 -to ddr4_ch1_dq[53] -set_location_assignment PIN_L45 -to ddr4_ch1_dq[54] -set_location_assignment PIN_L44 -to ddr4_ch1_dq[55] -set_location_assignment PIN_T40 -to ddr4_ch1_dq[56] -set_location_assignment PIN_T39 -to ddr4_ch1_dq[57] -set_location_assignment PIN_V40 -to ddr4_ch1_dq[58] -set_location_assignment PIN_P40 -to ddr4_ch1_dq[59] -set_location_assignment PIN_L40 -to ddr4_ch1_dq[60] -set_location_assignment PIN_U40 -to ddr4_ch1_dq[61] -set_location_assignment PIN_M40 -to ddr4_ch1_dq[62] -set_location_assignment PIN_N40 -to ddr4_ch1_dq[63] -set_location_assignment PIN_J43 -to ddr4_ch1_dq[64] -set_location_assignment PIN_L42 -to ddr4_ch1_dq[65] -set_location_assignment PIN_G42 -to ddr4_ch1_dq[66] -set_location_assignment PIN_K42 -to ddr4_ch1_dq[67] -set_location_assignment PIN_J44 -to ddr4_ch1_dq[68] -set_location_assignment PIN_G43 -to ddr4_ch1_dq[69] -set_location_assignment PIN_H43 -to ddr4_ch1_dq[70] -set_location_assignment PIN_H42 -to ddr4_ch1_dq[71] - -# DDR4 DIMM CH0 -set_location_assignment PIN_BH21 -to ddr4_dimm_ch0_rzq - -set_location_assignment PIN_N33 -to ddr4_dimm_ch0_event_n -set_location_assignment PIN_M33 -to ddr4_dimm_ch0_save_n -set_location_assignment PIN_BC20 -to ddr4_dimm_ch0_alert_n -set_location_assignment PIN_BP19 -to ddr4_dimm_ch0_reset_n -set_location_assignment PIN_BL21 -to ddr4_dimm_ch0_par - -set_location_assignment PIN_BJ19 -to ddr4_dimm_ch0_a[0] -set_location_assignment PIN_BK19 -to ddr4_dimm_ch0_a[1] -set_location_assignment PIN_BL22 -to ddr4_dimm_ch0_a[2] -set_location_assignment PIN_BK22 -to ddr4_dimm_ch0_a[3] -set_location_assignment PIN_BH20 -to ddr4_dimm_ch0_a[4] -set_location_assignment PIN_BJ20 -to ddr4_dimm_ch0_a[5] -set_location_assignment PIN_BL20 -to ddr4_dimm_ch0_a[6] -set_location_assignment PIN_BL19 -to ddr4_dimm_ch0_a[7] -set_location_assignment PIN_BJ18 -to ddr4_dimm_ch0_a[8] -set_location_assignment PIN_BK18 -to ddr4_dimm_ch0_a[9] -set_location_assignment PIN_BK21 -to ddr4_dimm_ch0_a[10] -set_location_assignment PIN_BJ21 -to ddr4_dimm_ch0_a[11] -set_location_assignment PIN_BH22 -to ddr4_dimm_ch0_a[12] -set_location_assignment PIN_BG20 -to ddr4_dimm_ch0_a[13] -set_location_assignment PIN_BF20 -to ddr4_dimm_ch0_a[14] -set_location_assignment PIN_BG22 -to ddr4_dimm_ch0_a[15] -set_location_assignment PIN_BF22 -to ddr4_dimm_ch0_a[16] -set_location_assignment PIN_BH18 -to ddr4_dimm_ch0_a[17] -set_location_assignment PIN_BE21 -to ddr4_dimm_ch0_bg[0] -set_location_assignment PIN_BP20 -to ddr4_dimm_ch0_bg[1] -set_location_assignment PIN_BN21 -to ddr4_dimm_ch0_act_n -set_location_assignment PIN_BN20 -to ddr4_dimm_ch0_odt[0] -set_location_assignment PIN_BM20 -to ddr4_dimm_ch0_odt[1] -set_location_assignment PIN_BM18 -to ddr4_dimm_ch0_ck_p[0] -set_location_assignment PIN_BM19 -to ddr4_dimm_ch0_ck_n[0] -set_location_assignment PIN_BB22 -to ddr4_dimm_ch0_ck_p[1] -set_location_assignment PIN_BA22 -to ddr4_dimm_ch0_ck_n[1] -set_location_assignment PIN_BP21 -to ddr4_dimm_ch0_cs_n[0] -set_location_assignment PIN_BM22 -to ddr4_dimm_ch0_cs_n[1] -set_location_assignment PIN_BD19 -to ddr4_dimm_ch0_cs_n[2] -set_location_assignment PIN_BD20 -to ddr4_dimm_ch0_cs_n[3] -set_location_assignment PIN_BD21 -to ddr4_dimm_ch0_c2 -set_location_assignment PIN_BP18 -to ddr4_dimm_ch0_cke[0] -set_location_assignment PIN_BN18 -to ddr4_dimm_ch0_cke[1] -set_location_assignment PIN_BG18 -to ddr4_dimm_ch0_ba[0] -set_location_assignment PIN_BF21 -to ddr4_dimm_ch0_ba[1] - -set_location_assignment PIN_BF26 -to ddr4_dimm_ch0_dqs_p[0] -set_location_assignment PIN_BE26 -to ddr4_dimm_ch0_dqs_n[0] -set_location_assignment PIN_BN25 -to ddr4_dimm_ch0_dqs_p[1] -set_location_assignment PIN_BP25 -to ddr4_dimm_ch0_dqs_n[1] -set_location_assignment PIN_BK24 -to ddr4_dimm_ch0_dqs_p[2] -set_location_assignment PIN_BL24 -to ddr4_dimm_ch0_dqs_n[2] -set_location_assignment PIN_BM15 -to ddr4_dimm_ch0_dqs_p[3] -set_location_assignment PIN_BN15 -to ddr4_dimm_ch0_dqs_n[3] -set_location_assignment PIN_BH15 -to ddr4_dimm_ch0_dqs_p[4] -set_location_assignment PIN_BG15 -to ddr4_dimm_ch0_dqs_n[4] -set_location_assignment PIN_BF12 -to ddr4_dimm_ch0_dqs_p[5] -set_location_assignment PIN_BE12 -to ddr4_dimm_ch0_dqs_n[5] -set_location_assignment PIN_BE16 -to ddr4_dimm_ch0_dqs_p[6] -set_location_assignment PIN_BD16 -to ddr4_dimm_ch0_dqs_n[6] -set_location_assignment PIN_BB24 -to ddr4_dimm_ch0_dqs_p[7] -set_location_assignment PIN_BA24 -to ddr4_dimm_ch0_dqs_n[7] -set_location_assignment PIN_BK14 -to ddr4_dimm_ch0_dqs_p[8] -set_location_assignment PIN_BL14 -to ddr4_dimm_ch0_dqs_n[8] -set_location_assignment PIN_BE27 -to ddr4_dimm_ch0_dqs_p[9] -set_location_assignment PIN_BF27 -to ddr4_dimm_ch0_dqs_n[9] -set_location_assignment PIN_BN26 -to ddr4_dimm_ch0_dqs_p[10] -set_location_assignment PIN_BP26 -to ddr4_dimm_ch0_dqs_n[10] -set_location_assignment PIN_BJ26 -to ddr4_dimm_ch0_dqs_p[11] -set_location_assignment PIN_BH26 -to ddr4_dimm_ch0_dqs_n[11] -set_location_assignment PIN_BM14 -to ddr4_dimm_ch0_dqs_p[12] -set_location_assignment PIN_BM13 -to ddr4_dimm_ch0_dqs_n[12] -set_location_assignment PIN_BH13 -to ddr4_dimm_ch0_dqs_p[13] -set_location_assignment PIN_BH12 -to ddr4_dimm_ch0_dqs_n[13] -set_location_assignment PIN_BF10 -to ddr4_dimm_ch0_dqs_p[14] -set_location_assignment PIN_BG10 -to ddr4_dimm_ch0_dqs_n[14] -set_location_assignment PIN_BC17 -to ddr4_dimm_ch0_dqs_p[15] -set_location_assignment PIN_BC18 -to ddr4_dimm_ch0_dqs_n[15] -set_location_assignment PIN_BC25 -to ddr4_dimm_ch0_dqs_p[16] -set_location_assignment PIN_BB25 -to ddr4_dimm_ch0_dqs_n[16] -set_location_assignment PIN_BK12 -to ddr4_dimm_ch0_dqs_p[17] -set_location_assignment PIN_BK13 -to ddr4_dimm_ch0_dqs_n[17] - -set_location_assignment PIN_BF24 -to ddr4_dimm_ch0_dq[0] -set_location_assignment PIN_BE24 -to ddr4_dimm_ch0_dq[1] -set_location_assignment PIN_BH27 -to ddr4_dimm_ch0_dq[2] -set_location_assignment PIN_BG27 -to ddr4_dimm_ch0_dq[3] -set_location_assignment PIN_BF25 -to ddr4_dimm_ch0_dq[4] -set_location_assignment PIN_BH25 -to ddr4_dimm_ch0_dq[5] -set_location_assignment PIN_BG25 -to ddr4_dimm_ch0_dq[6] -set_location_assignment PIN_BG24 -to ddr4_dimm_ch0_dq[7] -set_location_assignment PIN_BL25 -to ddr4_dimm_ch0_dq[8] -set_location_assignment PIN_BM25 -to ddr4_dimm_ch0_dq[9] -set_location_assignment PIN_BM23 -to ddr4_dimm_ch0_dq[10] -set_location_assignment PIN_BM24 -to ddr4_dimm_ch0_dq[11] -set_location_assignment PIN_BP24 -to ddr4_dimm_ch0_dq[12] -set_location_assignment PIN_BP23 -to ddr4_dimm_ch0_dq[13] -set_location_assignment PIN_BN22 -to ddr4_dimm_ch0_dq[14] -set_location_assignment PIN_BN23 -to ddr4_dimm_ch0_dq[15] -set_location_assignment PIN_BH23 -to ddr4_dimm_ch0_dq[16] -set_location_assignment PIN_BJ24 -to ddr4_dimm_ch0_dq[17] -set_location_assignment PIN_BG23 -to ddr4_dimm_ch0_dq[18] -set_location_assignment PIN_BJ25 -to ddr4_dimm_ch0_dq[19] -set_location_assignment PIN_BL26 -to ddr4_dimm_ch0_dq[20] -set_location_assignment PIN_BK26 -to ddr4_dimm_ch0_dq[21] -set_location_assignment PIN_BJ23 -to ddr4_dimm_ch0_dq[22] -set_location_assignment PIN_BK23 -to ddr4_dimm_ch0_dq[23] -set_location_assignment PIN_BP15 -to ddr4_dimm_ch0_dq[24] -set_location_assignment PIN_BP16 -to ddr4_dimm_ch0_dq[25] -set_location_assignment PIN_BP13 -to ddr4_dimm_ch0_dq[26] -set_location_assignment PIN_BP14 -to ddr4_dimm_ch0_dq[27] -set_location_assignment PIN_BN17 -to ddr4_dimm_ch0_dq[28] -set_location_assignment PIN_BN16 -to ddr4_dimm_ch0_dq[29] -set_location_assignment PIN_BN13 -to ddr4_dimm_ch0_dq[30] -set_location_assignment PIN_BN12 -to ddr4_dimm_ch0_dq[31] -set_location_assignment PIN_BJ14 -to ddr4_dimm_ch0_dq[32] -set_location_assignment PIN_BJ15 -to ddr4_dimm_ch0_dq[33] -set_location_assignment PIN_BJ16 -to ddr4_dimm_ch0_dq[34] -set_location_assignment PIN_BJ13 -to ddr4_dimm_ch0_dq[35] -set_location_assignment PIN_BG14 -to ddr4_dimm_ch0_dq[36] -set_location_assignment PIN_BH16 -to ddr4_dimm_ch0_dq[37] -set_location_assignment PIN_BF14 -to ddr4_dimm_ch0_dq[38] -set_location_assignment PIN_BH17 -to ddr4_dimm_ch0_dq[39] -set_location_assignment PIN_BG12 -to ddr4_dimm_ch0_dq[40] -set_location_assignment PIN_BF11 -to ddr4_dimm_ch0_dq[41] -set_location_assignment PIN_BG13 -to ddr4_dimm_ch0_dq[42] -set_location_assignment PIN_BE11 -to ddr4_dimm_ch0_dq[43] -set_location_assignment PIN_BE13 -to ddr4_dimm_ch0_dq[44] -set_location_assignment PIN_BD14 -to ddr4_dimm_ch0_dq[45] -set_location_assignment PIN_BD13 -to ddr4_dimm_ch0_dq[46] -set_location_assignment PIN_BE14 -to ddr4_dimm_ch0_dq[47] -set_location_assignment PIN_BC16 -to ddr4_dimm_ch0_dq[48] -set_location_assignment PIN_BD15 -to ddr4_dimm_ch0_dq[49] -set_location_assignment PIN_BF17 -to ddr4_dimm_ch0_dq[50] -set_location_assignment PIN_BG17 -to ddr4_dimm_ch0_dq[51] -set_location_assignment PIN_BF16 -to ddr4_dimm_ch0_dq[52] -set_location_assignment PIN_BF15 -to ddr4_dimm_ch0_dq[53] -set_location_assignment PIN_BE17 -to ddr4_dimm_ch0_dq[54] -set_location_assignment PIN_BD18 -to ddr4_dimm_ch0_dq[55] -set_location_assignment PIN_BD25 -to ddr4_dimm_ch0_dq[56] -set_location_assignment PIN_BD26 -to ddr4_dimm_ch0_dq[57] -set_location_assignment PIN_AY24 -to ddr4_dimm_ch0_dq[58] -set_location_assignment PIN_AW24 -to ddr4_dimm_ch0_dq[59] -set_location_assignment PIN_BE23 -to ddr4_dimm_ch0_dq[60] -set_location_assignment PIN_BD23 -to ddr4_dimm_ch0_dq[61] -set_location_assignment PIN_BB23 -to ddr4_dimm_ch0_dq[62] -set_location_assignment PIN_BC23 -to ddr4_dimm_ch0_dq[63] -set_location_assignment PIN_BM12 -to ddr4_dimm_ch0_dq[64] -set_location_assignment PIN_BM17 -to ddr4_dimm_ch0_dq[65] -set_location_assignment PIN_BL17 -to ddr4_dimm_ch0_dq[66] -set_location_assignment PIN_BL12 -to ddr4_dimm_ch0_dq[67] -set_location_assignment PIN_BL15 -to ddr4_dimm_ch0_dq[68] -set_location_assignment PIN_BK17 -to ddr4_dimm_ch0_dq[69] -set_location_assignment PIN_BL16 -to ddr4_dimm_ch0_dq[70] -set_location_assignment PIN_BK16 -to ddr4_dimm_ch0_dq[71] - -# DDR4 DIMM CH1 -set_location_assignment PIN_BF35 -to ddr4_dimm_ch1_rzq - -set_location_assignment PIN_P34 -to ddr4_dimm_ch1_event_n -set_location_assignment PIN_R34 -to ddr4_dimm_ch1_save_n -set_location_assignment PIN_BA32 -to ddr4_dimm_ch1_alert_n -set_location_assignment PIN_BP38 -to ddr4_dimm_ch1_reset_n -set_location_assignment PIN_BM35 -to ddr4_dimm_ch1_par - -set_location_assignment PIN_BK38 -to ddr4_dimm_ch1_a[0] -set_location_assignment PIN_BJ38 -to ddr4_dimm_ch1_a[1] -set_location_assignment PIN_BL35 -to ddr4_dimm_ch1_a[2] -set_location_assignment PIN_BK34 -to ddr4_dimm_ch1_a[3] -set_location_assignment PIN_BK36 -to ddr4_dimm_ch1_a[4] -set_location_assignment PIN_BL36 -to ddr4_dimm_ch1_a[5] -set_location_assignment PIN_BJ33 -to ddr4_dimm_ch1_a[6] -set_location_assignment PIN_BK33 -to ddr4_dimm_ch1_a[7] -set_location_assignment PIN_BK37 -to ddr4_dimm_ch1_a[8] -set_location_assignment PIN_BL37 -to ddr4_dimm_ch1_a[9] -set_location_assignment PIN_BL34 -to ddr4_dimm_ch1_a[10] -set_location_assignment PIN_BM34 -to ddr4_dimm_ch1_a[11] -set_location_assignment PIN_BG35 -to ddr4_dimm_ch1_a[12] -set_location_assignment PIN_BF34 -to ddr4_dimm_ch1_a[13] -set_location_assignment PIN_BG34 -to ddr4_dimm_ch1_a[14] -set_location_assignment PIN_BJ34 -to ddr4_dimm_ch1_a[15] -set_location_assignment PIN_BJ35 -to ddr4_dimm_ch1_a[16] -set_location_assignment PIN_BH35 -to ddr4_dimm_ch1_a[17] -set_location_assignment PIN_BG33 -to ddr4_dimm_ch1_bg[0] -set_location_assignment PIN_BP39 -to ddr4_dimm_ch1_bg[1] -set_location_assignment PIN_BM38 -to ddr4_dimm_ch1_act_n -set_location_assignment PIN_BP36 -to ddr4_dimm_ch1_odt[0] -set_location_assignment PIN_BN36 -to ddr4_dimm_ch1_odt[1] -set_location_assignment PIN_BN37 -to ddr4_dimm_ch1_ck_p[0] -set_location_assignment PIN_BM37 -to ddr4_dimm_ch1_ck_n[0] -set_location_assignment PIN_BB32 -to ddr4_dimm_ch1_ck_p[1] -set_location_assignment PIN_BC32 -to ddr4_dimm_ch1_ck_n[1] -set_location_assignment PIN_BN38 -to ddr4_dimm_ch1_cs_n[0] -set_location_assignment PIN_BN35 -to ddr4_dimm_ch1_cs_n[1] -set_location_assignment PIN_BD34 -to ddr4_dimm_ch1_cs_n[2] -set_location_assignment PIN_BE34 -to ddr4_dimm_ch1_cs_n[3] -set_location_assignment PIN_BB34 -to ddr4_dimm_ch1_c2 -set_location_assignment PIN_BP35 -to ddr4_dimm_ch1_cke[0] -set_location_assignment PIN_BP34 -to ddr4_dimm_ch1_cke[1] -set_location_assignment PIN_BH36 -to ddr4_dimm_ch1_ba[0] -set_location_assignment PIN_BH33 -to ddr4_dimm_ch1_ba[1] - -set_location_assignment PIN_BH40 -to ddr4_dimm_ch1_dqs_p[0] -set_location_assignment PIN_BJ40 -to ddr4_dimm_ch1_dqs_n[0] -set_location_assignment PIN_BG44 -to ddr4_dimm_ch1_dqs_p[1] -set_location_assignment PIN_BF44 -to ddr4_dimm_ch1_dqs_n[1] -set_location_assignment PIN_BM50 -to ddr4_dimm_ch1_dqs_p[2] -set_location_assignment PIN_BL50 -to ddr4_dimm_ch1_dqs_n[2] -set_location_assignment PIN_BH45 -to ddr4_dimm_ch1_dqs_p[3] -set_location_assignment PIN_BJ45 -to ddr4_dimm_ch1_dqs_n[3] -set_location_assignment PIN_BP41 -to ddr4_dimm_ch1_dqs_p[4] -set_location_assignment PIN_BN41 -to ddr4_dimm_ch1_dqs_n[4] -set_location_assignment PIN_BM47 -to ddr4_dimm_ch1_dqs_p[5] -set_location_assignment PIN_BN47 -to ddr4_dimm_ch1_dqs_n[5] -set_location_assignment PIN_BG38 -to ddr4_dimm_ch1_dqs_p[6] -set_location_assignment PIN_BH38 -to ddr4_dimm_ch1_dqs_n[6] -set_location_assignment PIN_BD36 -to ddr4_dimm_ch1_dqs_p[7] -set_location_assignment PIN_BE36 -to ddr4_dimm_ch1_dqs_n[7] -set_location_assignment PIN_BG32 -to ddr4_dimm_ch1_dqs_p[8] -set_location_assignment PIN_BF32 -to ddr4_dimm_ch1_dqs_n[8] -set_location_assignment PIN_BL39 -to ddr4_dimm_ch1_dqs_p[9] -set_location_assignment PIN_BM39 -to ddr4_dimm_ch1_dqs_n[9] -set_location_assignment PIN_BE42 -to ddr4_dimm_ch1_dqs_p[10] -set_location_assignment PIN_BE43 -to ddr4_dimm_ch1_dqs_n[10] -set_location_assignment PIN_BL51 -to ddr4_dimm_ch1_dqs_p[11] -set_location_assignment PIN_BL52 -to ddr4_dimm_ch1_dqs_n[11] -set_location_assignment PIN_BM49 -to ddr4_dimm_ch1_dqs_p[12] -set_location_assignment PIN_BL49 -to ddr4_dimm_ch1_dqs_n[12] -set_location_assignment PIN_BM40 -to ddr4_dimm_ch1_dqs_p[13] -set_location_assignment PIN_BL40 -to ddr4_dimm_ch1_dqs_n[13] -set_location_assignment PIN_BN50 -to ddr4_dimm_ch1_dqs_p[14] -set_location_assignment PIN_BP50 -to ddr4_dimm_ch1_dqs_n[14] -set_location_assignment PIN_BF37 -to ddr4_dimm_ch1_dqs_p[15] -set_location_assignment PIN_BE37 -to ddr4_dimm_ch1_dqs_n[15] -set_location_assignment PIN_BA35 -to ddr4_dimm_ch1_dqs_p[16] -set_location_assignment PIN_BB35 -to ddr4_dimm_ch1_dqs_n[16] -set_location_assignment PIN_BD30 -to ddr4_dimm_ch1_dqs_p[17] -set_location_assignment PIN_BD31 -to ddr4_dimm_ch1_dqs_n[17] - -set_location_assignment PIN_BJ39 -to ddr4_dimm_ch1_dq[0] -set_location_assignment PIN_BK39 -to ddr4_dimm_ch1_dq[1] -set_location_assignment PIN_BL42 -to ddr4_dimm_ch1_dq[2] -set_location_assignment PIN_BK42 -to ddr4_dimm_ch1_dq[3] -set_location_assignment PIN_BH41 -to ddr4_dimm_ch1_dq[4] -set_location_assignment PIN_BJ41 -to ddr4_dimm_ch1_dq[5] -set_location_assignment PIN_BL41 -to ddr4_dimm_ch1_dq[6] -set_location_assignment PIN_BK41 -to ddr4_dimm_ch1_dq[7] -set_location_assignment PIN_BK44 -to ddr4_dimm_ch1_dq[8] -set_location_assignment PIN_BJ44 -to ddr4_dimm_ch1_dq[9] -set_location_assignment PIN_BP45 -to ddr4_dimm_ch1_dq[10] -set_location_assignment PIN_BN45 -to ddr4_dimm_ch1_dq[11] -set_location_assignment PIN_BM44 -to ddr4_dimm_ch1_dq[12] -set_location_assignment PIN_BL44 -to ddr4_dimm_ch1_dq[13] -set_location_assignment PIN_BN46 -to ddr4_dimm_ch1_dq[14] -set_location_assignment PIN_BP46 -to ddr4_dimm_ch1_dq[15] -set_location_assignment PIN_BL46 -to ddr4_dimm_ch1_dq[16] -set_location_assignment PIN_BL47 -to ddr4_dimm_ch1_dq[17] -set_location_assignment PIN_BN52 -to ddr4_dimm_ch1_dq[18] -set_location_assignment PIN_BM52 -to ddr4_dimm_ch1_dq[19] -set_location_assignment PIN_BL54 -to ddr4_dimm_ch1_dq[20] -set_location_assignment PIN_BN53 -to ddr4_dimm_ch1_dq[21] -set_location_assignment PIN_BK54 -to ddr4_dimm_ch1_dq[22] -set_location_assignment PIN_BM53 -to ddr4_dimm_ch1_dq[23] -set_location_assignment PIN_BG45 -to ddr4_dimm_ch1_dq[24] -set_location_assignment PIN_BM45 -to ddr4_dimm_ch1_dq[25] -set_location_assignment PIN_BF45 -to ddr4_dimm_ch1_dq[26] -set_location_assignment PIN_BL45 -to ddr4_dimm_ch1_dq[27] -set_location_assignment PIN_BP51 -to ddr4_dimm_ch1_dq[28] -set_location_assignment PIN_BN51 -to ddr4_dimm_ch1_dq[29] -set_location_assignment PIN_BM48 -to ddr4_dimm_ch1_dq[30] -set_location_assignment PIN_BN48 -to ddr4_dimm_ch1_dq[31] -set_location_assignment PIN_BP40 -to ddr4_dimm_ch1_dq[32] -set_location_assignment PIN_BN40 -to ddr4_dimm_ch1_dq[33] -set_location_assignment PIN_BN43 -to ddr4_dimm_ch1_dq[34] -set_location_assignment PIN_BM43 -to ddr4_dimm_ch1_dq[35] -set_location_assignment PIN_BM42 -to ddr4_dimm_ch1_dq[36] -set_location_assignment PIN_BN42 -to ddr4_dimm_ch1_dq[37] -set_location_assignment PIN_BP44 -to ddr4_dimm_ch1_dq[38] -set_location_assignment PIN_BP43 -to ddr4_dimm_ch1_dq[39] -set_location_assignment PIN_BP48 -to ddr4_dimm_ch1_dq[40] -set_location_assignment PIN_BP49 -to ddr4_dimm_ch1_dq[41] -set_location_assignment PIN_BF41 -to ddr4_dimm_ch1_dq[42] -set_location_assignment PIN_BF42 -to ddr4_dimm_ch1_dq[43] -set_location_assignment PIN_BK43 -to ddr4_dimm_ch1_dq[44] -set_location_assignment PIN_BJ43 -to ddr4_dimm_ch1_dq[45] -set_location_assignment PIN_BH43 -to ddr4_dimm_ch1_dq[46] -set_location_assignment PIN_BG43 -to ddr4_dimm_ch1_dq[47] -set_location_assignment PIN_BF40 -to ddr4_dimm_ch1_dq[48] -set_location_assignment PIN_BF39 -to ddr4_dimm_ch1_dq[49] -set_location_assignment PIN_BG37 -to ddr4_dimm_ch1_dq[50] -set_location_assignment PIN_BF36 -to ddr4_dimm_ch1_dq[51] -set_location_assignment PIN_BG42 -to ddr4_dimm_ch1_dq[52] -set_location_assignment PIN_BH42 -to ddr4_dimm_ch1_dq[53] -set_location_assignment PIN_BG40 -to ddr4_dimm_ch1_dq[54] -set_location_assignment PIN_BG39 -to ddr4_dimm_ch1_dq[55] -set_location_assignment PIN_AY36 -to ddr4_dimm_ch1_dq[56] -set_location_assignment PIN_BC36 -to ddr4_dimm_ch1_dq[57] -set_location_assignment PIN_BA36 -to ddr4_dimm_ch1_dq[58] -set_location_assignment PIN_BC35 -to ddr4_dimm_ch1_dq[59] -set_location_assignment PIN_AW35 -to ddr4_dimm_ch1_dq[60] -set_location_assignment PIN_AW36 -to ddr4_dimm_ch1_dq[61] -set_location_assignment PIN_AW34 -to ddr4_dimm_ch1_dq[62] -set_location_assignment PIN_AY34 -to ddr4_dimm_ch1_dq[63] -set_location_assignment PIN_BA29 -to ddr4_dimm_ch1_dq[64] -set_location_assignment PIN_BE31 -to ddr4_dimm_ch1_dq[65] -set_location_assignment PIN_AY29 -to ddr4_dimm_ch1_dq[66] -set_location_assignment PIN_BF31 -to ddr4_dimm_ch1_dq[67] -set_location_assignment PIN_BA30 -to ddr4_dimm_ch1_dq[68] -set_location_assignment PIN_BC30 -to ddr4_dimm_ch1_dq[69] -set_location_assignment PIN_BB30 -to ddr4_dimm_ch1_dq[70] -set_location_assignment PIN_BC31 -to ddr4_dimm_ch1_dq[71] diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga.sdc b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga.sdc deleted file mode 100644 index e94985ca6..000000000 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/fpga.sdc +++ /dev/null @@ -1,125 +0,0 @@ -# Timing constraints for the Intel Stratix 10 DX FPGA development board - -set_time_format -unit ns -decimal_places 3 - -# Clock constraints -create_clock -period 7.519 -name "clk_133m_ddr4_1" [ get_ports "clk_133m_ddr4_1_p" ] -create_clock -period 7.519 -name "clk_133m_ddr4_0" [ get_ports "clk_133m_ddr4_0_p" ] -create_clock -period 7.519 -name "clk_133m_dimm_1" [ get_ports "clk_133m_dimm_1_p" ] -create_clock -period 7.519 -name "clk_133m_dimm_0" [ get_ports "clk_133m_dimm_0_p" ] - -create_clock -period 10.000 -name "clk2_100m_fpga_2i" [ get_ports "clk2_100m_fpga_2i_p" ] -create_clock -period 10.000 -name "clk2_100m_fpga_2j_0" [ get_ports "clk2_100m_fpga_2j_0_p" ] -create_clock -period 10.000 -name "clk2_100m_fpga_2j_1" [ get_ports "clk2_100m_fpga_2j_1_p" ] -create_clock -period 10.000 -name "clk_100m_fpga_3h" [ get_ports "clk_100m_fpga_3h_p" ] -create_clock -period 10.000 -name "clk_100m_fpga_3l_0" [ get_ports "clk_100m_fpga_3l_0_p" ] -create_clock -period 10.000 -name "clk_100m_fpga_3l_1" [ get_ports "clk_100m_fpga_3l_1_p" ] - -create_clock -period 20.000 -name "clk2_fpga_50m" [ get_ports "clk2_fpga_50m" ] - -create_clock -period 10.000 -name "clk_100m_pcie_0" [ get_ports "clk_100m_pcie_0_p" ] -create_clock -period 10.000 -name "clk_100m_pcie_1" [ get_ports "clk_100m_pcie_1_p" ] - -create_clock -period 10.000 -name "clk_100m_upi0_0" [ get_ports "clk_100m_upi0_0_p" ] -create_clock -period 10.000 -name "clk_100m_upi0_1" [ get_ports "clk_100m_upi0_1_p" ] - -create_clock -period 10.000 -name "clk_100m_upi1_0" [ get_ports "clk_100m_upi1_0_p" ] -create_clock -period 10.000 -name "clk_100m_upi1_1" [ get_ports "clk_100m_upi1_1_p" ] - -create_clock -period 10.000 -name "clk_100m_upi2_0" [ get_ports "clk_100m_upi2_0_p" ] -create_clock -period 10.000 -name "clk_100m_upi2_1" [ get_ports "clk_100m_upi2_1_p" ] - -create_clock -period 3.2 -name "clk_312p5m_qsfp0" [ get_ports "clk_312p5m_qsfp0_p" ] -create_clock -period 6.4 -name "clk_156p25m_qsfp0" [ get_ports "clk_156p25m_qsfp0_p" ] -create_clock -period 3.2 -name "clk_312p5m_qsfp1" [ get_ports "clk_312p5m_qsfp1_p" ] -create_clock -period 6.4 -name "clk_156p25m_qsfp1" [ get_ports "clk_156p25m_qsfp1_p" ] -create_clock -period 3.2 -name "clk_312p5m_qsfp2" [ get_ports "clk_312p5m_qsfp2_p" ] - -derive_clock_uncertainty - -set_clock_groups -asynchronous -group [ get_clocks "clk_133m_ddr4_1" ] -set_clock_groups -asynchronous -group [ get_clocks "clk_133m_ddr4_0" ] -set_clock_groups -asynchronous -group [ get_clocks "clk_133m_dimm_1" ] -set_clock_groups -asynchronous -group [ get_clocks "clk_133m_dimm_0" ] - -set_clock_groups -asynchronous -group [ get_clocks "clk2_100m_fpga_2i" ] -set_clock_groups -asynchronous -group [ get_clocks "clk2_100m_fpga_2j_0" ] -set_clock_groups -asynchronous -group [ get_clocks "clk2_100m_fpga_2j_1" ] -set_clock_groups -asynchronous -group [ get_clocks "clk_100m_fpga_3h" ] -set_clock_groups -asynchronous -group [ get_clocks "clk_100m_fpga_3l_0" ] -set_clock_groups -asynchronous -group [ get_clocks "clk_100m_fpga_3l_1" ] - -set_clock_groups -asynchronous -group [ get_clocks "clk2_fpga_50m" ] - -set_clock_groups -asynchronous -group [ get_clocks "clk_100m_pcie_0" ] -set_clock_groups -asynchronous -group [ get_clocks "clk_100m_pcie_1" ] - -set_clock_groups -asynchronous -group [ get_clocks "clk_100m_upi0_0" ] -set_clock_groups -asynchronous -group [ get_clocks "clk_100m_upi0_1" ] - -set_clock_groups -asynchronous -group [ get_clocks "clk_100m_upi1_0" ] -set_clock_groups -asynchronous -group [ get_clocks "clk_100m_upi1_1" ] - -set_clock_groups -asynchronous -group [ get_clocks "clk_100m_upi2_0" ] -set_clock_groups -asynchronous -group [ get_clocks "clk_100m_upi2_1" ] - -set_clock_groups -asynchronous -group [ get_clocks "clk_312p5m_qsfp0" ] -set_clock_groups -asynchronous -group [ get_clocks "clk_156p25m_qsfp0" ] -set_clock_groups -asynchronous -group [ get_clocks "clk_312p5m_qsfp1" ] -set_clock_groups -asynchronous -group [ get_clocks "clk_156p25m_qsfp1" ] -set_clock_groups -asynchronous -group [ get_clocks "clk_312p5m_qsfp2" ] - -# JTAG constraints -create_clock -name "altera_reserved_tck" -period 40.800 "altera_reserved_tck" - -set_clock_groups -asynchronous -group [get_clocks "altera_reserved_tck"] - -# IO constraints -set_false_path -from "cpu_resetn" -set_false_path -to "user_led_g[*]" - -set_false_path -from "pcie_rst_n" - - -source ../lib/eth/lib/axis/syn/quartus_pro/sync_reset.sdc - -# clocking infrastructure -constrain_sync_reset_inst "sync_reset_100mhz_inst" -constrain_sync_reset_inst "ptp_rst_reset_sync_inst" - -# PCIe clock -set_clock_groups -asynchronous -group [ get_clocks "pcie_hip_inst|intel_pcie_ptile_ast_0|inst|inst|maib_and_tile|rx_pcs_x2_clk|ch15" ] - -# PTP ref clock -set_clock_groups -asynchronous -group [ get_clocks "ref_div_inst|stratix10_clkctrl_0|clkdiv_inst|clock_div2" ] - -# E-Tile MACs -set_clock_groups -asynchronous -group [ get_clocks "iopll_etile_ptp_inst|iopll_0_refclk" ] -set_clock_groups -asynchronous -group [ get_clocks "iopll_etile_ptp_inst|iopll_0_outclk0" ] - -proc constrain_etile_mac_quad { inst } { - puts "Inserting timing constraints for MAC quad $inst" - - for {set i 0} {$i < 4} {incr i} { - set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|rx_clkout2|ch${i}" ] - set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|rx_clkout|ch${i}" ] - set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|tx_clkout2|ch${i}" ] - set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|tx_clkout|ch${i}" ] - set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|rx_clkout2|ch${i}" ] - set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|rx_clkout|ch${i}" ] - set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|tx_clkout2|ch${i}" ] - set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|tx_clkout|ch${i}" ] - } - - set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp0|alt_ehipc3_nphy_elane_ptp|tx_clkout|ch0" ] - set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp1|alt_ehipc3_nphy_elane_ptp_plloff|tx_transfer_clk|ch0" ] - - for {set i 0} {$i < 4} {incr i} { - constrain_sync_reset_inst "$inst|mac_ch[$i].mac_tx_reset_sync_inst" - constrain_sync_reset_inst "$inst|mac_ch[$i].mac_tx_ptp_reset_sync_inst" - constrain_sync_reset_inst "$inst|mac_ch[$i].mac_rx_ptp_reset_sync_inst" - } -} - -constrain_etile_mac_quad "qsfp1_mac_inst" -constrain_etile_mac_quad "qsfp2_mac_inst" diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/iopll_etile_ptp.tcl b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/iopll_etile_ptp.tcl deleted file mode 100644 index 1914d6f39..000000000 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/iopll_etile_ptp.tcl +++ /dev/null @@ -1,304 +0,0 @@ -package require -exact qsys 21.3 - -# create the system "iopll_etile_ptp" -proc do_create_iopll_etile_ptp {} { - # create the system - create_system iopll_etile_ptp - set_project_property DEVICE {1SD280PT2F55E1VG} - set_project_property DEVICE_FAMILY {Stratix 10} - set_project_property HIDE_FROM_IP_CATALOG {true} - set_use_testbench_naming_pattern 0 {} - - # add HDL parameters - - # add the components - add_instance iopll_0 altera_iopll - set_instance_parameter_value iopll_0 {gui_active_clk} {0} - set_instance_parameter_value iopll_0 {gui_c_cnt_in_src0} {c_m_cnt_in_src_ph_mux_clk} - set_instance_parameter_value iopll_0 {gui_c_cnt_in_src1} {c_m_cnt_in_src_ph_mux_clk} - set_instance_parameter_value iopll_0 {gui_c_cnt_in_src2} {c_m_cnt_in_src_ph_mux_clk} - set_instance_parameter_value iopll_0 {gui_c_cnt_in_src3} {c_m_cnt_in_src_ph_mux_clk} - set_instance_parameter_value iopll_0 {gui_c_cnt_in_src4} {c_m_cnt_in_src_ph_mux_clk} - set_instance_parameter_value iopll_0 {gui_c_cnt_in_src5} {c_m_cnt_in_src_ph_mux_clk} - set_instance_parameter_value iopll_0 {gui_c_cnt_in_src6} {c_m_cnt_in_src_ph_mux_clk} - set_instance_parameter_value iopll_0 {gui_c_cnt_in_src7} {c_m_cnt_in_src_ph_mux_clk} - set_instance_parameter_value iopll_0 {gui_c_cnt_in_src8} {c_m_cnt_in_src_ph_mux_clk} - set_instance_parameter_value iopll_0 {gui_cal_code_hex_file} {iossm.hex} - set_instance_parameter_value iopll_0 {gui_cal_converge} {0} - set_instance_parameter_value iopll_0 {gui_cal_error} {cal_clean} - set_instance_parameter_value iopll_0 {gui_cascade_counter0} {0} - set_instance_parameter_value iopll_0 {gui_cascade_counter1} {0} - set_instance_parameter_value iopll_0 {gui_cascade_counter10} {0} - set_instance_parameter_value iopll_0 {gui_cascade_counter11} {0} - set_instance_parameter_value iopll_0 {gui_cascade_counter12} {0} - set_instance_parameter_value iopll_0 {gui_cascade_counter13} {0} - set_instance_parameter_value iopll_0 {gui_cascade_counter14} {0} - set_instance_parameter_value iopll_0 {gui_cascade_counter15} {0} - set_instance_parameter_value iopll_0 {gui_cascade_counter16} {0} - set_instance_parameter_value iopll_0 {gui_cascade_counter17} {0} - set_instance_parameter_value iopll_0 {gui_cascade_counter2} {0} - set_instance_parameter_value iopll_0 {gui_cascade_counter3} {0} - set_instance_parameter_value iopll_0 {gui_cascade_counter4} {0} - set_instance_parameter_value iopll_0 {gui_cascade_counter5} {0} - set_instance_parameter_value iopll_0 {gui_cascade_counter6} {0} - set_instance_parameter_value iopll_0 {gui_cascade_counter7} {0} - set_instance_parameter_value iopll_0 {gui_cascade_counter8} {0} - set_instance_parameter_value iopll_0 {gui_cascade_counter9} {0} - set_instance_parameter_value iopll_0 {gui_cascade_outclk_index} {0} - set_instance_parameter_value iopll_0 {gui_clk_bad} {0} - set_instance_parameter_value iopll_0 {gui_clock_name_global} {0} - set_instance_parameter_value iopll_0 {gui_clock_name_string0} {outclk0} - set_instance_parameter_value iopll_0 {gui_clock_name_string1} {outclk1} - set_instance_parameter_value iopll_0 {gui_clock_name_string10} {outclk10} - set_instance_parameter_value iopll_0 {gui_clock_name_string11} {outclk11} - set_instance_parameter_value iopll_0 {gui_clock_name_string12} {outclk12} - set_instance_parameter_value iopll_0 {gui_clock_name_string13} {outclk13} - set_instance_parameter_value iopll_0 {gui_clock_name_string14} {outclk14} - set_instance_parameter_value iopll_0 {gui_clock_name_string15} {outclk15} - set_instance_parameter_value iopll_0 {gui_clock_name_string16} {outclk16} - set_instance_parameter_value iopll_0 {gui_clock_name_string17} {outclk17} - set_instance_parameter_value iopll_0 {gui_clock_name_string2} {outclk2} - set_instance_parameter_value iopll_0 {gui_clock_name_string3} {outclk3} - set_instance_parameter_value iopll_0 {gui_clock_name_string4} {outclk4} - set_instance_parameter_value iopll_0 {gui_clock_name_string5} {outclk5} - set_instance_parameter_value iopll_0 {gui_clock_name_string6} {outclk6} - set_instance_parameter_value iopll_0 {gui_clock_name_string7} {outclk7} - set_instance_parameter_value iopll_0 {gui_clock_name_string8} {outclk8} - set_instance_parameter_value iopll_0 {gui_clock_name_string9} {outclk9} - set_instance_parameter_value iopll_0 {gui_clock_to_compensate} {0} - set_instance_parameter_value iopll_0 {gui_debug_mode} {0} - set_instance_parameter_value iopll_0 {gui_divide_factor_c0} {6} - set_instance_parameter_value iopll_0 {gui_divide_factor_c1} {6} - set_instance_parameter_value iopll_0 {gui_divide_factor_c10} {6} - set_instance_parameter_value iopll_0 {gui_divide_factor_c11} {6} - set_instance_parameter_value iopll_0 {gui_divide_factor_c12} {6} - set_instance_parameter_value iopll_0 {gui_divide_factor_c13} {6} - set_instance_parameter_value iopll_0 {gui_divide_factor_c14} {6} - set_instance_parameter_value iopll_0 {gui_divide_factor_c15} {6} - set_instance_parameter_value iopll_0 {gui_divide_factor_c16} {6} - set_instance_parameter_value iopll_0 {gui_divide_factor_c17} {6} - set_instance_parameter_value iopll_0 {gui_divide_factor_c2} {6} - set_instance_parameter_value iopll_0 {gui_divide_factor_c3} {6} - set_instance_parameter_value iopll_0 {gui_divide_factor_c4} {6} - set_instance_parameter_value iopll_0 {gui_divide_factor_c5} {6} - set_instance_parameter_value iopll_0 {gui_divide_factor_c6} {6} - set_instance_parameter_value iopll_0 {gui_divide_factor_c7} {6} - set_instance_parameter_value iopll_0 {gui_divide_factor_c8} {6} - set_instance_parameter_value iopll_0 {gui_divide_factor_c9} {6} - set_instance_parameter_value iopll_0 {gui_divide_factor_n} {1} - set_instance_parameter_value iopll_0 {gui_dps_cntr} {C0} - set_instance_parameter_value iopll_0 {gui_dps_dir} {Positive} - set_instance_parameter_value iopll_0 {gui_dps_num} {1} - set_instance_parameter_value iopll_0 {gui_dsm_out_sel} {1st_order} - set_instance_parameter_value iopll_0 {gui_duty_cycle0} {50.0} - set_instance_parameter_value iopll_0 {gui_duty_cycle1} {50.0} - set_instance_parameter_value iopll_0 {gui_duty_cycle10} {50.0} - set_instance_parameter_value iopll_0 {gui_duty_cycle11} {50.0} - set_instance_parameter_value iopll_0 {gui_duty_cycle12} {50.0} - set_instance_parameter_value iopll_0 {gui_duty_cycle13} {50.0} - set_instance_parameter_value iopll_0 {gui_duty_cycle14} {50.0} - set_instance_parameter_value iopll_0 {gui_duty_cycle15} {50.0} - set_instance_parameter_value iopll_0 {gui_duty_cycle16} {50.0} - set_instance_parameter_value iopll_0 {gui_duty_cycle17} {50.0} - set_instance_parameter_value iopll_0 {gui_duty_cycle2} {50.0} - set_instance_parameter_value iopll_0 {gui_duty_cycle3} {50.0} - set_instance_parameter_value iopll_0 {gui_duty_cycle4} {50.0} - set_instance_parameter_value iopll_0 {gui_duty_cycle5} {50.0} - set_instance_parameter_value iopll_0 {gui_duty_cycle6} {50.0} - set_instance_parameter_value iopll_0 {gui_duty_cycle7} {50.0} - set_instance_parameter_value iopll_0 {gui_duty_cycle8} {50.0} - set_instance_parameter_value iopll_0 {gui_duty_cycle9} {50.0} - set_instance_parameter_value iopll_0 {gui_en_adv_params} {0} - set_instance_parameter_value iopll_0 {gui_en_dps_ports} {0} - set_instance_parameter_value iopll_0 {gui_en_extclkout_ports} {0} - set_instance_parameter_value iopll_0 {gui_en_iossm_reconf} {0} - set_instance_parameter_value iopll_0 {gui_en_lvds_ports} {Disabled} - set_instance_parameter_value iopll_0 {gui_en_periphery_ports} {0} - set_instance_parameter_value iopll_0 {gui_en_phout_ports} {0} - set_instance_parameter_value iopll_0 {gui_en_reconf} {0} - set_instance_parameter_value iopll_0 {gui_enable_cascade_in} {0} - set_instance_parameter_value iopll_0 {gui_enable_cascade_out} {0} - set_instance_parameter_value iopll_0 {gui_enable_mif_dps} {0} - set_instance_parameter_value iopll_0 {gui_enable_output_counter_cascading} {0} - set_instance_parameter_value iopll_0 {gui_enable_permit_cal} {0} - set_instance_parameter_value iopll_0 {gui_enable_upstream_out_clk} {0} - set_instance_parameter_value iopll_0 {gui_existing_mif_file_path} {~/pll.mif} - set_instance_parameter_value iopll_0 {gui_extclkout_0_source} {C0} - set_instance_parameter_value iopll_0 {gui_extclkout_1_source} {C0} - set_instance_parameter_value iopll_0 {gui_feedback_clock} {Global Clock} - set_instance_parameter_value iopll_0 {gui_fix_vco_frequency} {0} - set_instance_parameter_value iopll_0 {gui_fixed_vco_frequency} {600.0} - set_instance_parameter_value iopll_0 {gui_fixed_vco_frequency_ps} {1667.0} - set_instance_parameter_value iopll_0 {gui_frac_multiply_factor} {1.0} - set_instance_parameter_value iopll_0 {gui_fractional_cout} {32} - set_instance_parameter_value iopll_0 {gui_include_iossm} {0} - set_instance_parameter_value iopll_0 {gui_location_type} {I/O Bank} - set_instance_parameter_value iopll_0 {gui_lock_setting} {Low Lock Time} - set_instance_parameter_value iopll_0 {gui_mif_config_name} {unnamed} - set_instance_parameter_value iopll_0 {gui_mif_gen_options} {Generate New MIF File} - set_instance_parameter_value iopll_0 {gui_multiply_factor} {6} - set_instance_parameter_value iopll_0 {gui_new_mif_file_path} {~/pll.mif} - set_instance_parameter_value iopll_0 {gui_number_of_clocks} {1} - set_instance_parameter_value iopll_0 {gui_operation_mode} {direct} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency0} {114.285714} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency1} {100.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency10} {100.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency11} {100.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency12} {100.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency13} {100.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency14} {100.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency15} {100.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency16} {100.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency17} {100.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency2} {100.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency3} {100.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency4} {100.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency5} {100.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency6} {100.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency7} {100.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency8} {100.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency9} {100.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps0} {8750.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps1} {10000.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps10} {10000.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps11} {10000.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps12} {10000.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps13} {10000.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps14} {10000.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps15} {10000.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps16} {10000.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps17} {10000.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps2} {10000.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps3} {10000.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps4} {10000.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps5} {10000.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps6} {10000.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps7} {10000.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps8} {10000.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps9} {10000.0} - set_instance_parameter_value iopll_0 {gui_parameter_table_hex_file} {seq_params_sim.hex} - set_instance_parameter_value iopll_0 {gui_phase_shift0} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift1} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift10} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift11} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift12} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift13} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift14} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift15} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift16} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift17} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift2} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift3} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift4} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift5} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift6} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift7} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift8} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift9} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift_deg0} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift_deg1} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift_deg10} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift_deg11} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift_deg12} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift_deg13} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift_deg14} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift_deg15} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift_deg16} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift_deg17} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift_deg2} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift_deg3} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift_deg4} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift_deg5} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift_deg6} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift_deg7} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift_deg8} {0.0} - set_instance_parameter_value iopll_0 {gui_phase_shift_deg9} {0.0} - set_instance_parameter_value iopll_0 {gui_phout_division} {1} - set_instance_parameter_value iopll_0 {gui_pll_auto_reset} {0} - set_instance_parameter_value iopll_0 {gui_pll_bandwidth_preset} {Low} - set_instance_parameter_value iopll_0 {gui_pll_cal_done} {0} - set_instance_parameter_value iopll_0 {gui_pll_cascading_mode} {adjpllin} - set_instance_parameter_value iopll_0 {gui_pll_freqcal_en} {1} - set_instance_parameter_value iopll_0 {gui_pll_freqcal_req_flag} {1} - set_instance_parameter_value iopll_0 {gui_pll_m_cnt_in_src} {c_m_cnt_in_src_ph_mux_clk} - set_instance_parameter_value iopll_0 {gui_pll_mode} {Integer-N PLL} - set_instance_parameter_value iopll_0 {gui_pll_tclk_mux_en} {0} - set_instance_parameter_value iopll_0 {gui_pll_tclk_sel} {pll_tclk_m_src} - set_instance_parameter_value iopll_0 {gui_pll_type} {S10_Simple} - set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_0} {pll_freq_clk0_band18} - set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_1} {pll_freq_clk1_band18} - set_instance_parameter_value iopll_0 {gui_prot_mode} {UNUSED} - set_instance_parameter_value iopll_0 {gui_ps_units0} {ps} - set_instance_parameter_value iopll_0 {gui_ps_units1} {ps} - set_instance_parameter_value iopll_0 {gui_ps_units10} {ps} - set_instance_parameter_value iopll_0 {gui_ps_units11} {ps} - set_instance_parameter_value iopll_0 {gui_ps_units12} {ps} - set_instance_parameter_value iopll_0 {gui_ps_units13} {ps} - set_instance_parameter_value iopll_0 {gui_ps_units14} {ps} - set_instance_parameter_value iopll_0 {gui_ps_units15} {ps} - set_instance_parameter_value iopll_0 {gui_ps_units16} {ps} - set_instance_parameter_value iopll_0 {gui_ps_units17} {ps} - set_instance_parameter_value iopll_0 {gui_ps_units2} {ps} - set_instance_parameter_value iopll_0 {gui_ps_units3} {ps} - set_instance_parameter_value iopll_0 {gui_ps_units4} {ps} - set_instance_parameter_value iopll_0 {gui_ps_units5} {ps} - set_instance_parameter_value iopll_0 {gui_ps_units6} {ps} - set_instance_parameter_value iopll_0 {gui_ps_units7} {ps} - set_instance_parameter_value iopll_0 {gui_ps_units8} {ps} - set_instance_parameter_value iopll_0 {gui_ps_units9} {ps} - set_instance_parameter_value iopll_0 {gui_refclk1_frequency} {100.0} - set_instance_parameter_value iopll_0 {gui_refclk_might_change} {0} - set_instance_parameter_value iopll_0 {gui_refclk_switch} {0} - set_instance_parameter_value iopll_0 {gui_reference_clock_frequency} {100.0} - set_instance_parameter_value iopll_0 {gui_reference_clock_frequency_ps} {10000.0} - set_instance_parameter_value iopll_0 {gui_simulation_type} {0} - set_instance_parameter_value iopll_0 {gui_skip_sdc_generation} {0} - set_instance_parameter_value iopll_0 {gui_switchover_delay} {0} - set_instance_parameter_value iopll_0 {gui_switchover_mode} {Automatic Switchover} - set_instance_parameter_value iopll_0 {gui_use_NDFB_modes} {0} - set_instance_parameter_value iopll_0 {gui_use_coreclk} {0} - set_instance_parameter_value iopll_0 {gui_use_locked} {1} - set_instance_parameter_value iopll_0 {gui_use_logical} {0} - set_instance_parameter_value iopll_0 {gui_usr_device_speed_grade} {1} - set_instance_parameter_value iopll_0 {gui_vco_frequency} {600.0} - set_instance_parameter_value iopll_0 {hp_qsys_scripting_mode} {0} - set_instance_parameter_value iopll_0 {system_info_device_iobank_rev} {} - set_instance_property iopll_0 AUTO_EXPORT true - - # add wirelevel expressions - - # preserve ports for debug - - # add the exports - set_interface_property reset EXPORT_OF iopll_0.reset - set_interface_property refclk EXPORT_OF iopll_0.refclk - set_interface_property locked EXPORT_OF iopll_0.locked - set_interface_property outclk0 EXPORT_OF iopll_0.outclk0 - - # set values for exposed HDL parameters - - # set the the module properties - set_module_property BONUS_DATA { - - - - - -} - set_module_property FILE {iopll_etile_ptp.ip} - set_module_property GENERATION_ID {0x00000000} - set_module_property NAME {iopll_etile_ptp} - - # save the system - sync_sysinfo_parameters - save_system iopll_etile_ptp -} - -proc do_set_exported_interface_sysinfo_parameters {} { -} - -# create all the systems, from bottom up -do_create_iopll_etile_ptp - -# set system info parameters on exported interface, from bottom up -do_set_exported_interface_sysinfo_parameters diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/pcie.tcl b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/pcie.tcl deleted file mode 100644 index 42a775d1d..000000000 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/pcie.tcl +++ /dev/null @@ -1,2294 +0,0 @@ -package require -exact qsys 21.3 - -# create the system "pcie" -proc do_create_pcie {} { - # create the system - create_system pcie - set_project_property DEVICE {1SD280PT2F55E1VG} - set_project_property DEVICE_FAMILY {Stratix 10} - set_project_property HIDE_FROM_IP_CATALOG {true} - set_use_testbench_naming_pattern 0 {} - - # add HDL parameters - - # add the components - add_instance intel_pcie_ptile_ast_0 intel_pcie_ptile_ast - set_instance_parameter_value intel_pcie_ptile_ast_0 {aib_csr_top_dfd_ctrl_src_sel_hwtcl} {cfg_avmm_src} - set_instance_parameter_value intel_pcie_ptile_ast_0 {aib_csr_top_ecc_enable_mode_hwtcl} {Disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {aibnd_rx_sup_mode_hwtcl} {engineering_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {aibnd_tx_sup_mode_hwtcl} {engineering_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {aibwraux_top_wrp_dft_aux_en_hwtcl} {disable_dft} - set_instance_parameter_value intel_pcie_ptile_ast_0 {aibwraux_top_wrp_dft_dll_osc_dftsel_hwtcl} {disable_dll_osc_dftsel} - set_instance_parameter_value intel_pcie_ptile_ast_0 {aibwraux_top_wrp_dft_osc_dftcounter_hwtcl} {disable_osc_dftcounter} - set_instance_parameter_value intel_pcie_ptile_ast_0 {aibwraux_top_wrp_redundancy_en_hwtcl} {Disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {apps_type_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {avmm_enabled_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_adptwrap_dummy_func_mode_hwtcl} {c3adpt_disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_adptwrap_dummy_sup_mode_hwtcl} {advanced_user_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_aibio_dummy_sup_mode_hwtcl} {engineering_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set0_fsr_pld_10g_rx_crc32_err_rst_val_hwtcl} {set0_reset_to_one_crc32} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set0_fsr_pld_8g_sigdet_out_rst_val_hwtcl} {set0_reset_to_one_sigdet} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set0_fsr_pld_ltd_b_rst_val_hwtcl} {set0_reset_to_one_ltdb} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set0_fsr_pld_ltr_rst_val_hwtcl} {set0_reset_to_one_ltr} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set0_fsr_pld_rx_fifo_align_clr_rst_val_hwtcl} {set0_reset_to_one_alignclr} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set0_rxfifowr_post_ct_sel_hwtcl} {set0_rxfifowr_post_ct} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set0_rxfifowr_pre_ct_sel_hwtcl} {set0_rxfifowr_pre_ct} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set1_fsr_pld_8g_sigdet_out_rst_val_hwtcl} {set1_reset_to_one_sigdet} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set1_rxfiford_post_ct_sel_hwtcl} {set1_rxfiford_post_ct} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set1_rxfifowr_post_ct_sel_hwtcl} {set1_rxfifowr_post_ct} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set1_txfiford_pre_ct_sel_hwtcl} {set1_txfiford_pre_ct} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_rxchnl_dummy_set1_txfifowr_from_aib_sel_hwtcl} {set1_txfifowr_from_aib} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_in_bit0_rst_val_hwtcl} {set0_reset_to_one_hfsrin0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_in_bit1_rst_val_hwtcl} {set0_reset_to_one_hfsrin1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_in_bit2_rst_val_hwtcl} {set0_reset_to_one_hfsrin2} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_in_bit3_rst_val_hwtcl} {set0_reset_to_one_hfsrin3} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_out_bit0_rst_val_hwtcl} {set0_reset_to_one_hfsrout0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_out_bit1_rst_val_hwtcl} {set0_reset_to_one_hfsrout1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_out_bit2_rst_val_hwtcl} {set0_reset_to_one_hfsrout2} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_out_bit3_rst_val_hwtcl} {set0_reset_to_one_hfsrout3} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set0_fsr_mask_tx_pll_rst_val_hwtcl} {set0_reset_to_one_maskpll} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_in_bit0_rst_val_hwtcl} {set1_reset_to_one_hfsrin0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_in_bit1_rst_val_hwtcl} {set1_reset_to_one_hfsrin1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_in_bit2_rst_val_hwtcl} {set1_reset_to_one_hfsrin2} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_in_bit3_rst_val_hwtcl} {set1_reset_to_one_hfsrin3} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_out_bit0_rst_val_hwtcl} {set1_reset_to_one_hfsrout0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_out_bit1_rst_val_hwtcl} {set1_reset_to_one_hfsrout1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_out_bit2_rst_val_hwtcl} {set1_reset_to_one_hfsrout2} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_out_bit3_rst_val_hwtcl} {set1_reset_to_one_hfsrout3} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bcmrbc_txchnl_dummy_set1_fsr_mask_tx_pll_rst_val_hwtcl} {set1_reset_to_one_maskpll} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bfm_drive_interface_clk_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bfm_drive_interface_pin_perst_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bfm_drive_interface_pipe_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {bfm_drive_interface_test_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {chosen_devkit_hwtcl} {NONE} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_avmm_enabled_virtio_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_cap_ext_tag_supp_user_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_cap_slot_clk_config_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_ceb_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_cvp_user_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_10bit_tag_support_intf_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_app_xfer_pending_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_apps_pm_xmt_turnoff_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_apps_ready_entr_l23_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_cii_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_cpl_timeout_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_ecc_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_error_intf_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_hotplug_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_legacy_int_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_legacy_interrupt_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_multi_func_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_pld_warm_rst_rdy_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_power_mgnt_intf_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_prs_event_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_rx_buffer_limit_ports_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_sriov_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_test_intf_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_test_out_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_enable_virtio_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msix_tablesize_pf0} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msix_tablesize_pf1} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msix_tablesize_pf2} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msix_tablesize_pf3} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msix_tablesize_pf4} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msix_tablesize_pf5} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msix_tablesize_pf6} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msix_tablesize_pf7} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_bir_pf0} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_bir_pf1} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_bir_pf2} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_bir_pf3} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_bir_pf4} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_bir_pf5} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_bir_pf6} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_bir_pf7} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_offset_pf0} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_offset_pf1} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_offset_pf2} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_offset_pf3} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_offset_pf4} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_offset_pf5} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_offset_pf6} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixpba_offset_pf7} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_bir_pf0} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_bir_pf1} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_bir_pf2} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_bir_pf3} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_bir_pf4} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_bir_pf5} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_bir_pf6} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_bir_pf7} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_offset_pf0} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_offset_pf1} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_offset_pf2} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_offset_pf3} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_offset_pf4} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_offset_pf5} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_offset_pf6} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_msixtable_offset_pf7} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_subsysid_pf0} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_subsysid_pf1} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_subsysid_pf2} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_subsysid_pf3} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_subsysid_pf4} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_subsysid_pf5} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_subsysid_pf6} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_exvf_subsysid_pf7} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_flr_cap_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_hip_reconfig_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar0_address_width_user_hwtcl} {24} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar0_type_user_hwtcl} {64-bit prefetchable memory} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_class_code_hwtcl} {131072} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_dsp_16g_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_dsp_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_gen3_eq_pset_req_vec_atg4_hwtcl} {624} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_gen3_eq_pset_req_vec_hwtcl} {4} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_pba_offset_hwtcl} {12288.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_table_offset_hwtcl} {8192.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_table_size_hwtcl} {31} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_type0_device_id_hwtcl} {4097} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pci_type0_vendor_id_hwtcl} {4660} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pcie_cap_phy_slot_num_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pcie_cap_port_num_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pcie_cap_slot_power_limit_scale_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pcie_cap_slot_power_limit_value_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pcie_slot_imp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_pme_support_hwtcl} {15} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_rp_rom_bar_enabled_hwtcl} {disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_subsys_dev_id_hwtcl} {40973} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_subsys_vendor_id_hwtcl} {4466} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_usp_16g_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_usp_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf0vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_class_code_hwtcl} {16711680} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf1vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_class_code_hwtcl} {16711680} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf2vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_class_code_hwtcl} {16711680} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf3vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_class_code_hwtcl} {16711680} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf4vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_class_code_hwtcl} {16711680} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf5vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_class_code_hwtcl} {16711680} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf6vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_class_code_hwtcl} {16711680} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf7vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf_ceb_pointer_addr_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_pf_no_soft_rst_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_sn_ser_num_reg_1_dw_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_sn_ser_num_reg_2_dw_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_total_pf_count_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_use_ast_parity_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_user_mode_to_pld_in_use_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_user_pcie_cap_ep_l0s_accpt_latency_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_user_pcie_cap_ep_l1_accpt_latency_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_user_vsec_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_vf_ceb_pointer_addr_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtio_start_byte_address_hwtcl} {72} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_drop_vendor0_msg_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_drop_vendor1_msg_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_ecrc_strip_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_ep_native_hwtcl} {Native} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_hrdrstctrl_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_maxpayload_size_hwtcl} {512} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_num_of_lanes_hwtcl} {num_1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_io_decode_hwtcl} {io16} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_ltr_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_msix_enable_user_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_prefetch_decode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_ras_des_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf0_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf1_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf2_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf3_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf4_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf5_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf6_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_pf7_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_sn_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_txeq_mode_hwtcl} {eq_fom_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_virtual_uc_calibration_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core16_vsec_next_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_cap_ext_tag_supp_user_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_cap_slot_clk_config_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_cvp_user_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_app_xfer_pending_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_apps_pm_xmt_turnoff_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_apps_ready_entr_l23_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_cpl_timeout_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_ecc_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_error_intf_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_hotplug_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_legacy_int_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_legacy_interrupt_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_pld_warm_rst_rdy_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_power_mgnt_intf_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_rx_buffer_limit_ports_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_test_intf_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_enable_test_out_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_flr_cap_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_hip_reconfig_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_dsp_16g_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_dsp_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_gen3_eq_pset_req_vec_atg4_hwtcl} {624} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_gen3_eq_pset_req_vec_hwtcl} {4} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pci_type0_vendor_id_hwtcl} {4466} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pcie_cap_phy_slot_num_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pcie_cap_port_num_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pcie_cap_slot_power_limit_scale_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pcie_cap_slot_power_limit_value_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_pcie_slot_imp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_revision_id_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_rom_bar_enabled_hwtcl} {disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_rp_rom_bar_enabled_hwtcl} {disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_tph_req_cap_st_table_loc_1_hwtcl} {pf0_not_in_msix_table} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_usp_16g_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_usp_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf0vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf1_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf1vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf2_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf2vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf3_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf3vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf4_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf4vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf5_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf5vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf6_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf6vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf7_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_pf7vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_sn_ser_num_reg_1_dw_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_sn_ser_num_reg_2_dw_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_use_ast_parity_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_user_mode_to_pld_in_use_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_user_pcie_cap_ep_l0s_accpt_latency_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_user_pcie_cap_ep_l1_accpt_latency_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_user_vsec_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_drop_vendor0_msg_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_drop_vendor1_msg_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_ecrc_strip_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_ep_native_hwtcl} {Native} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_hrdrstctrl_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_maxpayload_size_hwtcl} {512} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_num_of_lanes_hwtcl} {num_1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_pf0_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_pf0_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_pf0_io_decode_hwtcl} {io16} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_pf0_msix_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_pf0_prefetch_decode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_pf0_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_pf0_ras_des_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_pf0_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_sn_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_txeq_mode_hwtcl} {eq_fom_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_virtual_uc_calibration_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_0_vsec_next_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_cap_ext_tag_supp_user_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_cap_slot_clk_config_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_cvp_user_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_app_xfer_pending_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_apps_pm_xmt_turnoff_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_apps_ready_entr_l23_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_cpl_timeout_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_ecc_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_error_intf_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_hotplug_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_legacy_int_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_legacy_interrupt_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_pld_warm_rst_rdy_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_power_mgnt_intf_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_rx_buffer_limit_ports_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_test_intf_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_enable_test_out_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_flr_cap_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_hip_reconfig_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_dsp_16g_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_dsp_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_gen3_eq_pset_req_vec_atg4_hwtcl} {624} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_gen3_eq_pset_req_vec_hwtcl} {4} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pci_type0_vendor_id_hwtcl} {4466} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pcie_cap_phy_slot_num_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pcie_cap_port_num_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pcie_cap_slot_power_limit_scale_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pcie_cap_slot_power_limit_value_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_pcie_slot_imp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_revision_id_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_rom_bar_enabled_hwtcl} {disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_rp_rom_bar_enabled_hwtcl} {disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_tph_req_cap_st_table_loc_1_hwtcl} {pf0_not_in_msix_table} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_usp_16g_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_usp_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf0vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf1_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf1vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf2_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf2vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf3_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf3vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf4_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf4vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf5_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf5vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf6_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf6vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf7_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_pf7vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_sn_ser_num_reg_1_dw_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_sn_ser_num_reg_2_dw_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_use_ast_parity_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_user_mode_to_pld_in_use_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_user_pcie_cap_ep_l0s_accpt_latency_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_user_pcie_cap_ep_l1_accpt_latency_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_user_vsec_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_drop_vendor0_msg_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_drop_vendor1_msg_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_ecrc_strip_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_ep_native_hwtcl} {Native} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_hrdrstctrl_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_maxpayload_size_hwtcl} {512} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_num_of_lanes_hwtcl} {num_1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_pf0_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_pf0_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_pf0_io_decode_hwtcl} {io16} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_pf0_msix_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_pf0_prefetch_decode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_pf0_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_pf0_ras_des_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_pf0_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_sn_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_txeq_mode_hwtcl} {eq_fom_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_virtual_uc_calibration_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core4_1_vsec_next_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_avmm_enabled_virtio_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_cap_ext_tag_supp_user_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_cap_slot_clk_config_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_ceb_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_cvp_user_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_app_xfer_pending_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_apps_pm_xmt_turnoff_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_apps_ready_entr_l23_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_cii_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_cpl_timeout_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_ecc_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_error_intf_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_hotplug_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_legacy_int_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_legacy_interrupt_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_multi_func_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_pld_warm_rst_rdy_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_power_mgnt_intf_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_prs_event_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_rx_buffer_limit_ports_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_sriov_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_test_intf_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_test_out_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_enable_virtio_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msix_tablesize_pf0} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msix_tablesize_pf1} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msix_tablesize_pf2} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msix_tablesize_pf3} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msix_tablesize_pf4} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msix_tablesize_pf5} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msix_tablesize_pf6} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msix_tablesize_pf7} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_bir_pf0} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_bir_pf1} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_bir_pf2} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_bir_pf3} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_bir_pf4} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_bir_pf5} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_bir_pf6} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_bir_pf7} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_offset_pf0} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_offset_pf1} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_offset_pf2} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_offset_pf3} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_offset_pf4} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_offset_pf5} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_offset_pf6} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixpba_offset_pf7} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_bir_pf0} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_bir_pf1} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_bir_pf2} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_bir_pf3} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_bir_pf4} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_bir_pf5} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_bir_pf6} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_bir_pf7} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_offset_pf0} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_offset_pf1} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_offset_pf2} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_offset_pf3} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_offset_pf4} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_offset_pf5} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_offset_pf6} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_msixtable_offset_pf7} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_subsysid_pf0} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_subsysid_pf1} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_subsysid_pf2} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_subsysid_pf3} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_subsysid_pf4} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_subsysid_pf5} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_subsysid_pf6} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_exvf_subsysid_pf7} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_flr_cap_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_hip_reconfig_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar0_address_width_user_hwtcl} {16} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar0_type_user_hwtcl} {64-bit prefetchable memory} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_dsp_16g_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_dsp_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_gen3_eq_pset_req_vec_atg4_hwtcl} {624} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_gen3_eq_pset_req_vec_hwtcl} {4} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pci_type0_vendor_id_hwtcl} {4466} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pcie_cap_phy_slot_num_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pcie_cap_port_num_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pcie_cap_slot_power_limit_scale_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pcie_cap_slot_power_limit_value_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_pcie_slot_imp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_revision_id_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_rp_rom_bar_enabled_hwtcl} {disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_usp_16g_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_usp_tx_preset_hwtcl} {8} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf0vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf1vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf2vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf3vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf4vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf5vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf6vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_acs_cap_acs_egress_ctrl_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_acs_cap_acs_p2p_egress_control_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_acs_cap_peer_to_peer_traffic_supp_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar0_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar0_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar1_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar1_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar2_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar2_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar3_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar3_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar4_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar4_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar5_address_width_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_bar5_type_user_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_class_code_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_expansion_base_address_register_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_int_pin_hwtcl} {NO INT} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pasid_cap_execute_permission_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pasid_cap_max_pasid_width} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pasid_cap_privileged_mode_supported} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_msi_ext_data_cap_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_msi_multiple_msg_cap_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_msix_bir_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_msix_pba_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_msix_pba_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_msix_table_offset_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_msix_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_msix_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_type0_device_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_pci_type0_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_revision_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar0_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar0_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar1_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar1_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar2_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar2_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar3_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar3_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar4_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar4_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar5_address_width_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_bar5_type_hwtcl} {Disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_sriov_vf_device_id} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_subsys_dev_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_subsys_vendor_id_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_tph_req_cap_st_table_size_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_vf_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_vf_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_vf_count_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_vf_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_vf_tph_st_dev_spec_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_vf_tph_st_int_mode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_capability_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_cmn_config_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_cmn_config_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_cmn_config_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_device_specific_cap_present_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_devspecific_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_devspecific_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_devspecific_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_isrstatus_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_isrstatus_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_isrstatus_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_notification_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_notification_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_notification_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_notify_off_multiplier_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_pciconfig_access_bar_indicator_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_pciconfig_access_bar_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf7vf_virtio_pciconfig_access_structure_length_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf_ceb_pointer_addr_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_pf_no_soft_rst_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_refclk_init_active_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_sn_ser_num_reg_1_dw_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_sn_ser_num_reg_2_dw_hwtcl} {0.0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_total_pf_count_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_use_ast_parity_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_user_mode_to_pld_in_use_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_user_pcie_cap_ep_l0s_accpt_latency_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_user_pcie_cap_ep_l1_accpt_latency_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_user_vsec_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_vf_ceb_pointer_addr_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtio_start_byte_address_hwtcl} {72} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_drop_vendor0_msg_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_drop_vendor1_msg_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_ecrc_strip_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_ep_native_hwtcl} {Native} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_hrdrstctrl_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_maxpayload_size_hwtcl} {512} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_num_of_lanes_hwtcl} {num_1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_io_decode_hwtcl} {io16} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_ltr_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_prefetch_decode_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_ras_des_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf0_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf1_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf2_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf3_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf4_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf5_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf6_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_acs_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_ats_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_exvf_msix_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_msi_64b_addressing_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_msi_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_msix_enable_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_pasid_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_prs_ext_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_tph_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_pf7_user_vsec_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_sn_cap_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_txeq_mode_hwtcl} {eq_fom_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_virtual_uc_calibration_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {core8_vsec_next_offset_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {design_environment} {NATIVE} - set_instance_parameter_value intel_pcie_ptile_ast_0 {enable_example_design_sim_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {enable_example_design_synth_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {enable_example_design_tb_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {enable_switch_port_termination_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {example_design_mode_hwtcl} {PIO/SRIOV} - set_instance_parameter_value intel_pcie_ptile_ast_0 {g3_pld_clkfreq_user_hwtcl} {250MHz} - set_instance_parameter_value intel_pcie_ptile_ast_0 {g4_pld_clkfreq_user_hwtcl} {400MHz} - set_instance_parameter_value intel_pcie_ptile_ast_0 {hrc_cpll_ena_warm_reset_hwtcl} {disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {hrc_pin_perst_is_full_rst_hwtcl} {true} - set_instance_parameter_value intel_pcie_ptile_ast_0 {if_pldadapt_hip_mode_hwtcl} {user_chnl} - set_instance_parameter_value intel_pcie_ptile_ast_0 {is_cvp_enable_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {mcdma_enabled_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {mlab_ram_block_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pcs_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pld_clrpcs_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pldadapt_rx_aib_clk2_sel_hwtcl} {aib_clk2_pld_pcs_rx_clk_out} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pldadapt_rx_pld_clk1_sel_hwtcl} {pld_clk1_dcm} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pldadapt_tx_pld_clk1_sel_hwtcl} {pld_clk1_dcm} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pma_top_0_bs_mode_hwtcl} {bs_ac_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pma_top_0_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pma_top_1_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pma_top_2_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pma_top_3_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {pma_top_4_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {ptile_debug_toolkit_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {ptile_enable_pciess_register_access_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {ptile_link_insp_avmm_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {ref_clk_mode_hwtcl} {ref_clk_separate} - set_instance_parameter_value intel_pcie_ptile_ast_0 {rx_dft_hssitestip_dll_dcc_en_hwtcl} {disable_dft} - set_instance_parameter_value intel_pcie_ptile_ast_0 {select_design_example_rtl_lang_hwtcl} {Verilog} - set_instance_parameter_value intel_pcie_ptile_ast_0 {serial_sim_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {sim_mode_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {standard_interface_selection_hwtcl} {1} - set_instance_parameter_value intel_pcie_ptile_ast_0 {subtopology_pcie_x8_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {sup_mode_hwtcl} {user_mode} - set_instance_parameter_value intel_pcie_ptile_ast_0 {targeted_devkit_hwtcl} {NONE} - set_instance_parameter_value intel_pcie_ptile_ast_0 {top_4_es_mode_hwtcl} {common_ref_clk} - set_instance_parameter_value intel_pcie_ptile_ast_0 {top_topology_hwtcl} {Gen3x16, Interface - 512 bit} - set_instance_parameter_value intel_pcie_ptile_ast_0 {tx_dfd_dll_dcc_en_hwtcl} {disable_dfd} - set_instance_parameter_value intel_pcie_ptile_ast_0 {tx_dft_hssitestip_dll_dcc_en_hwtcl} {disable_dft} - set_instance_parameter_value intel_pcie_ptile_ast_0 {upi_core_lpbk_mode_hwtcl} {lpbk_comp_slave} - set_instance_parameter_value intel_pcie_ptile_ast_0 {upi_core_u_upiphy_agent_slow_mode_hwtcl} {disable} - set_instance_parameter_value intel_pcie_ptile_ast_0 {virtual_rp_ep_mode_hwtcl} {Native Endpoint} - set_instance_parameter_value intel_pcie_ptile_ast_0 {virtual_sris_enable_en_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {virtual_tlp_bypass_en_user_hwtcl} {0} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch0_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch10_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch11_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch12_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch13_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch14_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch15_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch16_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch17_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch18_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch19_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch1_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch20_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch21_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch22_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch23_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch2_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch3_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch4_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch5_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch6_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch7_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch8_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibadapt_wrap_ch9_powerdown_mode_hwtcl} {false} - set_instance_parameter_value intel_pcie_ptile_ast_0 {wraibcmn_top_u_bcmrbc_adptwrap_dummy_powermode_ac_hwtcl} {disabled} - set_instance_parameter_value intel_pcie_ptile_ast_0 {xcvr_reconfig_user_hwtcl} {0} - set_instance_property intel_pcie_ptile_ast_0 AUTO_EXPORT true - - # add wirelevel expressions - - # preserve ports for debug - - # add the exports - set_interface_property p0_rx_st EXPORT_OF intel_pcie_ptile_ast_0.p0_rx_st - set_interface_property p0_rx_st_misc EXPORT_OF intel_pcie_ptile_ast_0.p0_rx_st_misc - set_interface_property p0_tx_st EXPORT_OF intel_pcie_ptile_ast_0.p0_tx_st - set_interface_property p0_tx_st_misc EXPORT_OF intel_pcie_ptile_ast_0.p0_tx_st_misc - set_interface_property p0_tx_cred EXPORT_OF intel_pcie_ptile_ast_0.p0_tx_cred - set_interface_property p0_config_tl EXPORT_OF intel_pcie_ptile_ast_0.p0_config_tl - set_interface_property p0_reset_status_n EXPORT_OF intel_pcie_ptile_ast_0.p0_reset_status_n - set_interface_property p0_pin_perst EXPORT_OF intel_pcie_ptile_ast_0.p0_pin_perst - set_interface_property p0_hip_status EXPORT_OF intel_pcie_ptile_ast_0.p0_hip_status - set_interface_property hip_serial EXPORT_OF intel_pcie_ptile_ast_0.hip_serial - set_interface_property coreclkout_hip EXPORT_OF intel_pcie_ptile_ast_0.coreclkout_hip - set_interface_property refclk0 EXPORT_OF intel_pcie_ptile_ast_0.refclk0 - set_interface_property refclk1 EXPORT_OF intel_pcie_ptile_ast_0.refclk1 - set_interface_property pin_perst EXPORT_OF intel_pcie_ptile_ast_0.pin_perst - set_interface_property ninit_done EXPORT_OF intel_pcie_ptile_ast_0.ninit_done - - # set values for exposed HDL parameters - - # set the the module properties - set_module_property BONUS_DATA { - - - - - -} - set_module_property FILE {pcie.ip} - set_module_property GENERATION_ID {0x00000000} - set_module_property NAME {pcie} - - # save the system - sync_sysinfo_parameters - save_system pcie -} - -proc do_set_exported_interface_sysinfo_parameters {} { -} - -# create all the systems, from bottom up -do_create_pcie - -# set system info parameters on exported interface, from bottom up -do_set_exported_interface_sysinfo_parameters diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/ref_div.tcl b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/ref_div.tcl deleted file mode 100644 index 656fcfbb1..000000000 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/ref_div.tcl +++ /dev/null @@ -1,61 +0,0 @@ -package require -exact qsys 21.3 - -# create the system "ref_div" -proc do_create_ref_div {} { - # create the system - create_system ref_div - set_project_property DEVICE {1SD280PT2F55E1VG} - set_project_property DEVICE_FAMILY {Stratix 10} - set_project_property HIDE_FROM_IP_CATALOG {true} - set_use_testbench_naming_pattern 0 {} - - # add HDL parameters - - # add the components - add_instance stratix10_clkctrl_0 stratix10_clkctrl - set_instance_parameter_value stratix10_clkctrl_0 {CLOCK_DIVIDER} {1} - set_instance_parameter_value stratix10_clkctrl_0 {CLOCK_DIVIDER_OUTPUTS} {3} - set_instance_parameter_value stratix10_clkctrl_0 {ENABLE} {0} - set_instance_parameter_value stratix10_clkctrl_0 {ENABLE_REGISTER_TYPE} {1} - set_instance_parameter_value stratix10_clkctrl_0 {ENABLE_TYPE} {2} - set_instance_parameter_value stratix10_clkctrl_0 {GLITCH_FREE_SWITCHOVER} {0} - set_instance_parameter_value stratix10_clkctrl_0 {NUM_CLOCKS} {1} - set_instance_property stratix10_clkctrl_0 AUTO_EXPORT true - - # add wirelevel expressions - - # preserve ports for debug - - # add the exports - set_interface_property inclk EXPORT_OF stratix10_clkctrl_0.inclk - set_interface_property clock_div1x EXPORT_OF stratix10_clkctrl_0.clock_div1x - set_interface_property clock_div2x EXPORT_OF stratix10_clkctrl_0.clock_div2x - set_interface_property clock_div4x EXPORT_OF stratix10_clkctrl_0.clock_div4x - - # set values for exposed HDL parameters - - # set the the module properties - set_module_property BONUS_DATA { - - - - - -} - set_module_property FILE {ref_div.ip} - set_module_property GENERATION_ID {0x00000000} - set_module_property NAME {ref_div} - - # save the system - sync_sysinfo_parameters - save_system ref_div -} - -proc do_set_exported_interface_sysinfo_parameters {} { -} - -# create all the systems, from bottom up -do_create_ref_div - -# set system info parameters on exported interface, from bottom up -do_set_exported_interface_sysinfo_parameters diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/reset_release.tcl b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/reset_release.tcl deleted file mode 100644 index f5ea14f4d..000000000 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/ip/reset_release.tcl +++ /dev/null @@ -1,52 +0,0 @@ -package require -exact qsys 21.3 - -# create the system "reset_release" -proc do_create_reset_release {} { - # create the system - create_system reset_release - set_project_property DEVICE {1SD280PT2F55E1VG} - set_project_property DEVICE_FAMILY {Stratix 10} - set_project_property HIDE_FROM_IP_CATALOG {true} - set_use_testbench_naming_pattern 0 {} - - # add HDL parameters - - # add the components - add_instance s10_user_rst_clkgate_0 altera_s10_user_rst_clkgate - set_instance_parameter_value s10_user_rst_clkgate_0 {outputType} {Conduit Interface} - set_instance_property s10_user_rst_clkgate_0 AUTO_EXPORT true - - # add wirelevel expressions - - # preserve ports for debug - - # add the exports - set_interface_property ninit_done EXPORT_OF s10_user_rst_clkgate_0.ninit_done - - # set values for exposed HDL parameters - - # set the the module properties - set_module_property BONUS_DATA { - - - - - -} - set_module_property FILE {reset_release.ip} - set_module_property GENERATION_ID {0x00000000} - set_module_property NAME {reset_release} - - # save the system - sync_sysinfo_parameters - save_system reset_release -} - -proc do_set_exported_interface_sysinfo_parameters {} { -} - -# create all the systems, from bottom up -do_create_reset_release - -# set system info parameters on exported interface, from bottom up -do_set_exported_interface_sysinfo_parameters diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/lib b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/lib deleted file mode 120000 index 9512b3d5e..000000000 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/lib +++ /dev/null @@ -1 +0,0 @@ -../../../lib/ \ No newline at end of file diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/axis_fifo.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/axis_fifo.v deleted file mode 100644 index 45b7232f1..000000000 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/axis_fifo.v +++ /dev/null @@ -1,565 +0,0 @@ -/* - -Copyright (c) 2013-2023 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * AXI4-Stream FIFO - */ -module axis_fifo # -( - // FIFO depth in words - // KEEP_WIDTH words per cycle if KEEP_ENABLE set - // Rounded up to nearest power of 2 cycles - parameter DEPTH = 4096, - // Width of AXI stream interfaces in bits - parameter DATA_WIDTH = 8, - // Propagate tkeep signal - // If disabled, tkeep assumed to be 1'b1 - parameter KEEP_ENABLE = (DATA_WIDTH>8), - // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), - // Propagate tlast signal - parameter LAST_ENABLE = 1, - // Propagate tid signal - parameter ID_ENABLE = 0, - // tid signal width - parameter ID_WIDTH = 8, - // Propagate tdest signal - parameter DEST_ENABLE = 0, - // tdest signal width - parameter DEST_WIDTH = 8, - // Propagate tuser signal - parameter USER_ENABLE = 1, - // tuser signal width - parameter USER_WIDTH = 1, - // number of RAM pipeline registers - parameter RAM_PIPELINE = 1, - // use output FIFO - // When set, the RAM read enable and pipeline clock enables are removed - parameter OUTPUT_FIFO_ENABLE = 0, - // Frame FIFO mode - operate on frames instead of cycles - // When set, m_axis_tvalid will not be deasserted within a frame - // Requires LAST_ENABLE set - parameter FRAME_FIFO = 0, - // tuser value for bad frame marker - parameter USER_BAD_FRAME_VALUE = 1'b1, - // tuser mask for bad frame marker - parameter USER_BAD_FRAME_MASK = 1'b1, - // Drop frames larger than FIFO - // Requires FRAME_FIFO set - parameter DROP_OVERSIZE_FRAME = FRAME_FIFO, - // Drop frames marked bad - // Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set - parameter DROP_BAD_FRAME = 0, - // Drop incoming frames when full - // When set, s_axis_tready is always asserted - // Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set - parameter DROP_WHEN_FULL = 0, - // Mark incoming frames as bad frames when full - // When set, s_axis_tready is always asserted - // Requires FRAME_FIFO to be clear - parameter MARK_WHEN_FULL = 0, - // Enable pause request input - parameter PAUSE_ENABLE = 0, - // Pause between frames - parameter FRAME_PAUSE = FRAME_FIFO -) -( - input wire clk, - input wire rst, - - /* - * AXI input - */ - input wire [DATA_WIDTH-1:0] s_axis_tdata, - input wire [KEEP_WIDTH-1:0] s_axis_tkeep, - input wire s_axis_tvalid, - output wire s_axis_tready, - input wire s_axis_tlast, - input wire [ID_WIDTH-1:0] s_axis_tid, - input wire [DEST_WIDTH-1:0] s_axis_tdest, - input wire [USER_WIDTH-1:0] s_axis_tuser, - - /* - * AXI output - */ - output wire [DATA_WIDTH-1:0] m_axis_tdata, - output wire [KEEP_WIDTH-1:0] m_axis_tkeep, - output wire m_axis_tvalid, - input wire m_axis_tready, - output wire m_axis_tlast, - output wire [ID_WIDTH-1:0] m_axis_tid, - output wire [DEST_WIDTH-1:0] m_axis_tdest, - output wire [USER_WIDTH-1:0] m_axis_tuser, - - /* - * Pause - */ - input wire pause_req, - output wire pause_ack, - - /* - * Status - */ - output wire [$clog2(DEPTH):0] status_depth, - output wire [$clog2(DEPTH):0] status_depth_commit, - output wire status_overflow, - output wire status_bad_frame, - output wire status_good_frame -); - -parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH) : $clog2(DEPTH); - -parameter OUTPUT_FIFO_ADDR_WIDTH = RAM_PIPELINE < 2 ? 3 : $clog2(RAM_PIPELINE*2+7); - -// check configuration -initial begin - if (FRAME_FIFO && !LAST_ENABLE) begin - $error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)"); - $finish; - end - - if (DROP_OVERSIZE_FRAME && !FRAME_FIFO) begin - $error("Error: DROP_OVERSIZE_FRAME set requires FRAME_FIFO set (instance %m)"); - $finish; - end - - if (DROP_BAD_FRAME && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin - $error("Error: DROP_BAD_FRAME set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)"); - $finish; - end - - if (DROP_WHEN_FULL && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin - $error("Error: DROP_WHEN_FULL set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)"); - $finish; - end - - if ((DROP_BAD_FRAME || MARK_WHEN_FULL) && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin - $error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)"); - $finish; - end - - if (MARK_WHEN_FULL && FRAME_FIFO) begin - $error("Error: MARK_WHEN_FULL is not compatible with FRAME_FIFO (instance %m)"); - $finish; - end - - if (MARK_WHEN_FULL && !LAST_ENABLE) begin - $error("Error: MARK_WHEN_FULL set requires LAST_ENABLE set (instance %m)"); - $finish; - end -end - -localparam KEEP_OFFSET = DATA_WIDTH; -localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0); -localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0); -localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0); -localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0); -localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0); - -reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}; -reg [ADDR_WIDTH:0] wr_ptr_commit_reg = {ADDR_WIDTH+1{1'b0}}; -reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}; - -// (* ramstyle = "no_rw_check" *) -// Workaround for Quartus MLAB RAM read enable bug -// https://www.intel.com/content/www/us/en/support/programmable/articles/000093130.html -(* ramstyle = "no_rw_check, m20k" *) -reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0]; -reg mem_read_data_valid_reg = 1'b0; - -(* shreg_extract = "no" *) -reg [WIDTH-1:0] m_axis_pipe_reg[RAM_PIPELINE+1-1:0]; -reg [RAM_PIPELINE+1-1:0] m_axis_tvalid_pipe_reg = 0; - -// full when first MSB different but rest same -wire full = wr_ptr_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}}); -// empty when pointers match exactly -wire empty = wr_ptr_commit_reg == rd_ptr_reg; -// overflow within packet -wire full_wr = wr_ptr_reg == (wr_ptr_commit_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}}); - -reg s_frame_reg = 1'b0; - -reg drop_frame_reg = 1'b0; -reg mark_frame_reg = 1'b0; -reg send_frame_reg = 1'b0; -reg [ADDR_WIDTH:0] depth_reg = 0; -reg [ADDR_WIDTH:0] depth_commit_reg = 0; -reg overflow_reg = 1'b0; -reg bad_frame_reg = 1'b0; -reg good_frame_reg = 1'b0; - -assign s_axis_tready = FRAME_FIFO ? (!full || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : (!full || MARK_WHEN_FULL); - -wire [WIDTH-1:0] s_axis; - -generate - assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata; - if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET +: KEEP_WIDTH] = s_axis_tkeep; - if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast | mark_frame_reg; - if (ID_ENABLE) assign s_axis[ID_OFFSET +: ID_WIDTH] = s_axis_tid; - if (DEST_ENABLE) assign s_axis[DEST_OFFSET +: DEST_WIDTH] = s_axis_tdest; - if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = mark_frame_reg ? USER_BAD_FRAME_VALUE : s_axis_tuser; -endgenerate - -wire [WIDTH-1:0] m_axis = m_axis_pipe_reg[RAM_PIPELINE+1-1]; - -wire m_axis_tready_pipe; -wire m_axis_tvalid_pipe = m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1]; - -wire [DATA_WIDTH-1:0] m_axis_tdata_pipe = m_axis[DATA_WIDTH-1:0]; -wire [KEEP_WIDTH-1:0] m_axis_tkeep_pipe = KEEP_ENABLE ? m_axis[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}}; -wire m_axis_tlast_pipe = LAST_ENABLE ? m_axis[LAST_OFFSET] : 1'b1; -wire [ID_WIDTH-1:0] m_axis_tid_pipe = ID_ENABLE ? m_axis[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}}; -wire [DEST_WIDTH-1:0] m_axis_tdest_pipe = DEST_ENABLE ? m_axis[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}}; -wire [USER_WIDTH-1:0] m_axis_tuser_pipe = USER_ENABLE ? m_axis[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}}; - -wire m_axis_tready_out; -wire m_axis_tvalid_out; - -wire [DATA_WIDTH-1:0] m_axis_tdata_out; -wire [KEEP_WIDTH-1:0] m_axis_tkeep_out; -wire m_axis_tlast_out; -wire [ID_WIDTH-1:0] m_axis_tid_out; -wire [DEST_WIDTH-1:0] m_axis_tdest_out; -wire [USER_WIDTH-1:0] m_axis_tuser_out; - -wire pipe_ready; - -assign status_depth = (KEEP_ENABLE && KEEP_WIDTH > 1) ? {depth_reg, {$clog2(KEEP_WIDTH){1'b0}}} : depth_reg; -assign status_depth_commit = (KEEP_ENABLE && KEEP_WIDTH > 1) ? {depth_commit_reg, {$clog2(KEEP_WIDTH){1'b0}}} : depth_commit_reg; -assign status_overflow = overflow_reg; -assign status_bad_frame = bad_frame_reg; -assign status_good_frame = good_frame_reg; - -// Write logic -always @(posedge clk) begin - overflow_reg <= 1'b0; - bad_frame_reg <= 1'b0; - good_frame_reg <= 1'b0; - - if (s_axis_tready && s_axis_tvalid && LAST_ENABLE) begin - // track input frame status - s_frame_reg <= !s_axis_tlast; - end - - if (FRAME_FIFO) begin - // frame FIFO mode - if (s_axis_tready && s_axis_tvalid) begin - // transfer in - if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin - // full, packet overflow, or currently dropping frame - // drop frame - drop_frame_reg <= 1'b1; - if (s_axis_tlast) begin - // end of frame, reset write pointer - wr_ptr_reg <= wr_ptr_commit_reg; - drop_frame_reg <= 1'b0; - overflow_reg <= 1'b1; - end - end else begin - // store it - mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis; - wr_ptr_reg <= wr_ptr_reg + 1; - if (s_axis_tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin - // end of frame or send frame - send_frame_reg <= !s_axis_tlast; - if (s_axis_tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin - // bad packet, reset write pointer - wr_ptr_reg <= wr_ptr_commit_reg; - bad_frame_reg <= 1'b1; - end else begin - // good packet or packet overflow, update write pointer - wr_ptr_commit_reg <= wr_ptr_reg + 1; - good_frame_reg <= s_axis_tlast; - end - end - end - end else if (s_axis_tvalid && full_wr && !DROP_OVERSIZE_FRAME) begin - // data valid with packet overflow - // update write pointer - send_frame_reg <= 1'b1; - wr_ptr_commit_reg <= wr_ptr_reg; - end - end else begin - // normal FIFO mode - if (s_axis_tready && s_axis_tvalid) begin - if (drop_frame_reg && MARK_WHEN_FULL) begin - // currently dropping frame - if (s_axis_tlast) begin - // end of frame - if (!full && mark_frame_reg) begin - // terminate marked frame - mark_frame_reg <= 1'b0; - mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis; - wr_ptr_reg <= wr_ptr_reg + 1; - wr_ptr_commit_reg <= wr_ptr_reg + 1; - end - // end of frame, clear drop flag - drop_frame_reg <= 1'b0; - overflow_reg <= 1'b1; - end - end else if ((full || mark_frame_reg) && MARK_WHEN_FULL) begin - // full or marking frame - // drop frame; mark if this isn't the first cycle - drop_frame_reg <= 1'b1; - mark_frame_reg <= mark_frame_reg || s_frame_reg; - if (s_axis_tlast) begin - drop_frame_reg <= 1'b0; - overflow_reg <= 1'b1; - end - end else begin - // transfer in - mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis; - wr_ptr_reg <= wr_ptr_reg + 1; - wr_ptr_commit_reg <= wr_ptr_reg + 1; - end - end else if ((!full && !drop_frame_reg && mark_frame_reg) && MARK_WHEN_FULL) begin - // terminate marked frame - mark_frame_reg <= 1'b0; - mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis; - wr_ptr_reg <= wr_ptr_reg + 1; - wr_ptr_commit_reg <= wr_ptr_reg + 1; - end - end - - if (rst) begin - wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}}; - wr_ptr_commit_reg <= {ADDR_WIDTH+1{1'b0}}; - - s_frame_reg <= 1'b0; - - drop_frame_reg <= 1'b0; - mark_frame_reg <= 1'b0; - send_frame_reg <= 1'b0; - overflow_reg <= 1'b0; - bad_frame_reg <= 1'b0; - good_frame_reg <= 1'b0; - end -end - -// Status -always @(posedge clk) begin - depth_reg <= wr_ptr_reg - rd_ptr_reg; - depth_commit_reg <= wr_ptr_commit_reg - rd_ptr_reg; -end - -// Read logic -integer j; - -always @(posedge clk) begin - if (m_axis_tready_pipe) begin - // output ready; invalidate stage - m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b0; - end - - for (j = RAM_PIPELINE+1-1; j > 0; j = j - 1) begin - if (m_axis_tready_pipe || ((~m_axis_tvalid_pipe_reg) >> j)) begin - // output ready or bubble in pipeline; transfer down pipeline - m_axis_tvalid_pipe_reg[j] <= m_axis_tvalid_pipe_reg[j-1]; - m_axis_pipe_reg[j] <= m_axis_pipe_reg[j-1]; - m_axis_tvalid_pipe_reg[j-1] <= 1'b0; - end - end - - if (m_axis_tready_pipe || ~m_axis_tvalid_pipe_reg) begin - // output ready or bubble in pipeline; read new data from FIFO - m_axis_tvalid_pipe_reg[0] <= 1'b0; - m_axis_pipe_reg[0] <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]]; - if (!empty && pipe_ready) begin - // not empty, increment pointer - m_axis_tvalid_pipe_reg[0] <= 1'b1; - rd_ptr_reg <= rd_ptr_reg + 1; - end - end - - if (rst) begin - rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}}; - m_axis_tvalid_pipe_reg <= 0; - end -end - -generate - -if (!OUTPUT_FIFO_ENABLE) begin - - assign pipe_ready = 1'b1; - - assign m_axis_tready_pipe = m_axis_tready_out; - assign m_axis_tvalid_out = m_axis_tvalid_pipe; - - assign m_axis_tdata_out = m_axis_tdata_pipe; - assign m_axis_tkeep_out = m_axis_tkeep_pipe; - assign m_axis_tlast_out = m_axis_tlast_pipe; - assign m_axis_tid_out = m_axis_tid_pipe; - assign m_axis_tdest_out = m_axis_tdest_pipe; - assign m_axis_tuser_out = m_axis_tuser_pipe; - -end else begin : output_fifo - - // output datapath logic - reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; - reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; - reg m_axis_tvalid_reg = 1'b0; - reg m_axis_tlast_reg = 1'b0; - reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}}; - reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; - reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}}; - - reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_wr_ptr_reg = 0; - reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_rd_ptr_reg = 0; - reg out_fifo_half_full_reg = 1'b0; - - wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}}); - wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg; - - (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) - reg [DATA_WIDTH-1:0] out_fifo_tdata[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; - (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) - reg [KEEP_WIDTH-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; - (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) - reg out_fifo_tlast[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; - (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) - reg [ID_WIDTH-1:0] out_fifo_tid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; - (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) - reg [DEST_WIDTH-1:0] out_fifo_tdest[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; - (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) - reg [USER_WIDTH-1:0] out_fifo_tuser[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; - - assign pipe_ready = !out_fifo_half_full_reg; - - assign m_axis_tready_pipe = 1'b1; - - assign m_axis_tdata_out = m_axis_tdata_reg; - assign m_axis_tkeep_out = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}}; - assign m_axis_tvalid_out = m_axis_tvalid_reg; - assign m_axis_tlast_out = LAST_ENABLE ? m_axis_tlast_reg : 1'b1; - assign m_axis_tid_out = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; - assign m_axis_tdest_out = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; - assign m_axis_tuser_out = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; - - always @(posedge clk) begin - m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready_out; - - out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1); - - if (!out_fifo_full && m_axis_tvalid_pipe) begin - out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdata_pipe; - out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tkeep_pipe; - out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tlast_pipe; - out_fifo_tid[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tid_pipe; - out_fifo_tdest[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdest_pipe; - out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tuser_pipe; - out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1; - end - - if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready_out)) begin - m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; - m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; - m_axis_tvalid_reg <= 1'b1; - m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; - m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; - m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; - m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]]; - out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1; - end - - if (rst) begin - out_fifo_wr_ptr_reg <= 0; - out_fifo_rd_ptr_reg <= 0; - m_axis_tvalid_reg <= 1'b0; - end - end - -end - -if (PAUSE_ENABLE) begin : pause - - // Pause logic - reg pause_reg = 1'b0; - reg pause_frame_reg = 1'b0; - - assign m_axis_tready_out = m_axis_tready && !pause_reg; - assign m_axis_tvalid = m_axis_tvalid_out && !pause_reg; - - assign m_axis_tdata = m_axis_tdata_out; - assign m_axis_tkeep = m_axis_tkeep_out; - assign m_axis_tlast = m_axis_tlast_out; - assign m_axis_tid = m_axis_tid_out; - assign m_axis_tdest = m_axis_tdest_out; - assign m_axis_tuser = m_axis_tuser_out; - - assign pause_ack = pause_reg; - - always @(posedge clk) begin - if (FRAME_PAUSE) begin - if (m_axis_tvalid && m_axis_tready) begin - if (m_axis_tlast) begin - pause_frame_reg <= 1'b0; - pause_reg <= pause_req; - end else begin - pause_frame_reg <= 1'b1; - end - end else begin - if (!pause_frame_reg) begin - pause_reg <= pause_req; - end - end - end else begin - pause_reg <= pause_req; - end - - if (rst) begin - pause_frame_reg <= 1'b0; - pause_reg <= 1'b0; - end - end - -end else begin - - assign m_axis_tready_out = m_axis_tready; - assign m_axis_tvalid = m_axis_tvalid_out; - - assign m_axis_tdata = m_axis_tdata_out; - assign m_axis_tkeep = m_axis_tkeep_out; - assign m_axis_tlast = m_axis_tlast_out; - assign m_axis_tid = m_axis_tid_out; - assign m_axis_tdest = m_axis_tdest_out; - assign m_axis_tuser = m_axis_tuser_out; - - assign pause_ack = 1'b0; - -end - -endgenerate - -endmodule - -`resetall diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/common b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/common deleted file mode 120000 index 449c9409c..000000000 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/common +++ /dev/null @@ -1 +0,0 @@ -../../../../common/rtl/ \ No newline at end of file diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga.v deleted file mode 100644 index b1537dfd2..000000000 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga.v +++ /dev/null @@ -1,1625 +0,0 @@ -// SPDX-License-Identifier: BSD-2-Clause-Views -/* - * Copyright (c) 2021-2023 The Regents of the University of California - */ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA top-level module - */ -module fpga # -( - // FW and board IDs - parameter FPGA_ID = 32'hC32450DD, - parameter FW_ID = 32'h00000000, - parameter FW_VER = 32'h00_00_01_00, - parameter BOARD_ID = 32'h1172_A00D, - parameter BOARD_VER = 32'h01_00_00_00, - parameter BUILD_DATE = 32'd1563227611, - parameter GIT_HASH = 32'hdce357bf, - parameter RELEASE_INFO = 32'h00000000, - - // Structural configuration - parameter IF_COUNT = 2, - parameter PORTS_PER_IF = 1, - parameter SCHED_PER_IF = PORTS_PER_IF, - parameter PORT_MASK = 0, - - // Clock configuration - parameter CLK_PERIOD_NS_NUM = 4, - parameter CLK_PERIOD_NS_DENOM = 1, - - // PTP configuration - parameter PTP_CLOCK_PIPELINE = 0, - parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_PORT_CDC_PIPELINE = 0, - parameter PTP_PEROUT_ENABLE = 1, - parameter PTP_PEROUT_COUNT = 1, - - // Queue manager configuration - parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_QUEUE_OP_TABLE_SIZE = 32, - parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter CQ_OP_TABLE_SIZE = 32, - parameter EQN_WIDTH = 5, - parameter TX_QUEUE_INDEX_WIDTH = 10, - parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, - parameter EQ_PIPELINE = 3, - parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), - parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), - - // TX and RX engine configuration - parameter TX_DESC_TABLE_SIZE = 32, - parameter RX_DESC_TABLE_SIZE = 32, - parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, - - // Scheduler configuration - parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, - parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, - parameter TDMA_INDEX_WIDTH = 6, - - // Interface configuration - parameter PTP_TS_ENABLE = 1, - parameter TX_CPL_FIFO_DEPTH = 32, - parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_HASH_ENABLE = 1, - parameter RX_CHECKSUM_ENABLE = 1, - parameter PFC_ENABLE = 1, - parameter LFC_ENABLE = PFC_ENABLE, - parameter TX_FIFO_DEPTH = 32768, - parameter RX_FIFO_DEPTH = 32768, - parameter MAX_TX_SIZE = 9214, - parameter MAX_RX_SIZE = 9214, - parameter TX_RAM_SIZE = 32768, - parameter RX_RAM_SIZE = 32768, - - // Application block configuration - parameter APP_ID = 32'h00000000, - parameter APP_ENABLE = 0, - parameter APP_CTRL_ENABLE = 1, - parameter APP_DMA_ENABLE = 1, - parameter APP_AXIS_DIRECT_ENABLE = 1, - parameter APP_AXIS_SYNC_ENABLE = 1, - parameter APP_AXIS_IF_ENABLE = 1, - parameter APP_STAT_ENABLE = 1, - - // DMA interface configuration - parameter DMA_IMM_ENABLE = 0, - parameter DMA_IMM_WIDTH = 32, - parameter DMA_LEN_WIDTH = 16, - parameter DMA_TAG_WIDTH = 16, - parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), - parameter RAM_PIPELINE = 2, - - // PCIe interface configuration - parameter SEG_COUNT = 2, - parameter SEG_DATA_WIDTH = 256, - parameter PF_COUNT = 1, - parameter VF_COUNT = 0, - - // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EQN_WIDTH, - - // AXI lite interface configuration (control) - parameter AXIL_CTRL_DATA_WIDTH = 32, - parameter AXIL_CTRL_ADDR_WIDTH = 24, - - // AXI lite interface configuration (application control) - parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, - parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, - - // Ethernet interface configuration - parameter AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE = 1, - parameter AXIS_ETH_TX_PIPELINE = 0, - parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, - parameter AXIS_ETH_TX_TS_PIPELINE = 0, - parameter AXIS_ETH_RX_PIPELINE = 0, - parameter AXIS_ETH_RX_FIFO_PIPELINE = 2, - parameter MAC_RSFEC = 1, - - // Statistics counter subsystem - parameter STAT_ENABLE = 1, - parameter STAT_DMA_ENABLE = 1, - parameter STAT_PCIE_ENABLE = 1, - parameter STAT_INC_WIDTH = 24, - parameter STAT_ID_WIDTH = 12 -) -( - /* - * Clock: 100 MHz - * Reset: Push button, active low - */ - // input wire clk2_fpga_50m, - input wire clk2_100m_fpga_2i_p, - // input wire cpu_resetn, - - /* - * GPIO - */ - input wire user_pb, - output wire [3:0] user_led_g, - - /* - * I2C - */ - inout wire i2c2_scl, - inout wire i2c2_sda, - output wire bmc_i2c2_disable, - - /* - * PCIe: gen 4 x16 - */ - output wire [15:0] pcie_tx_p, - output wire [15:0] pcie_tx_n, - input wire [15:0] pcie_rx_p, - input wire [15:0] pcie_rx_n, - input wire clk_100m_pcie_0_p, - input wire clk_100m_pcie_1_p, - input wire pcie_rst_n, - - /* - * Ethernet: QSFP28 - */ - output wire [3:0] qsfp1_tx_p, - output wire [3:0] qsfp1_tx_n, - input wire [3:0] qsfp1_rx_p, - input wire [3:0] qsfp1_rx_n, - output wire [3:0] qsfp2_tx_p, - output wire [3:0] qsfp2_tx_n, - input wire [3:0] qsfp2_rx_p, - input wire [3:0] qsfp2_rx_n, - input wire clk_156p25m_qsfp0_p - // input wire clk_156p25m_qsfp1_p, - // input wire clk_312p5m_qsfp0_p, - // input wire clk_312p5m_qsfp1_p, - // input wire clk_312p5m_qsfp2_p -); - -// PTP configuration -parameter PTP_CLK_PERIOD_NS_NUM = 4096; -parameter PTP_CLK_PERIOD_NS_DENOM = 825; -parameter PTP_TS_WIDTH = 96; -parameter PTP_TAG_WIDTH = 8; - -// Interface configuration -parameter TX_TAG_WIDTH = PTP_TAG_WIDTH; - -// PCIe interface configuration -parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32); -parameter SEG_HDR_WIDTH = 128; -parameter SEG_PRFX_WIDTH = 32; -parameter TX_SEQ_NUM_WIDTH = 6; -parameter PCIE_TAG_COUNT = 256; - -// Ethernet interface configuration -parameter AXIS_ETH_DATA_WIDTH = 64; -parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; -parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE ? 2 : 1); -parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1; -parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; - -// Clock and reset -wire ninit_done; - -wire pcie_clk; -wire pcie_rst; - -reset_release reset_release_inst ( - .ninit_done (ninit_done) -); - -wire clk_100mhz = clk2_100m_fpga_2i_p; -wire rst_100mhz; - -sync_reset #( - .N(20) -) -sync_reset_100mhz_inst ( - .clk(clk_100mhz), - .rst(pcie_rst), - .out(rst_100mhz) -); - -// GPIO -wire i2c2_scl_i; -wire i2c2_scl_o; -wire i2c2_scl_t; -wire i2c2_sda_i; -wire i2c2_sda_o; -wire i2c2_sda_t; - -reg i2c2_scl_o_reg; -reg i2c2_scl_t_reg; -reg i2c2_sda_o_reg; -reg i2c2_sda_t_reg; - -always @(posedge pcie_clk) begin - i2c2_scl_o_reg <= i2c2_scl_o; - i2c2_scl_t_reg <= i2c2_scl_t; - i2c2_sda_o_reg <= i2c2_sda_o; - i2c2_sda_t_reg <= i2c2_sda_t; -end - -sync_signal #( - .WIDTH(2), - .N(2) -) -sync_signal_inst ( - .clk(pcie_clk), - .in({i2c2_scl, i2c2_sda}), - .out({i2c2_scl_i, i2c2_sda_i}) -); - -assign i2c2_scl = i2c2_scl_t_reg ? 1'bz : i2c2_scl_o_reg; -assign i2c2_sda = i2c2_sda_t_reg ? 1'bz : i2c2_sda_o_reg; - -// PCIe -wire coreclkout_hip; -wire reset_status_n; - -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data; -wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty; -wire [SEG_COUNT-1:0] rx_st_sop; -wire [SEG_COUNT-1:0] rx_st_eop; -wire [SEG_COUNT-1:0] rx_st_valid; -wire rx_st_ready; -wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] rx_st_hdr; -wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] rx_st_tlp_prfx; -wire [SEG_COUNT-1:0] rx_st_vf_active = 0; -wire [SEG_COUNT*3-1:0] rx_st_func_num = 0; -wire [SEG_COUNT*11-1:0] rx_st_vf_num = 0; -wire [SEG_COUNT*3-1:0] rx_st_bar_range; -wire [SEG_COUNT-1:0] rx_st_tlp_abort; - -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data; -wire [SEG_COUNT-1:0] tx_st_sop; -wire [SEG_COUNT-1:0] tx_st_eop; -wire [SEG_COUNT-1:0] tx_st_valid; -wire tx_st_ready; -wire [SEG_COUNT-1:0] tx_st_err; -wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] tx_st_hdr; -wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] tx_st_tlp_prfx; - -wire [11:0] rx_buffer_limit; -wire [1:0] rx_buffer_limit_tdm_idx; - -wire [15:0] tx_cdts_limit; -wire [2:0] tx_cdts_limit_tdm_idx; - -wire [15:0] tl_cfg_ctl; -wire [4:0] tl_cfg_add; -wire [2:0] tl_cfg_func; - -assign pcie_clk = coreclkout_hip; -assign pcie_rst = !reset_status_n; - -pcie pcie_hip_inst ( - .p0_rx_st_ready_i(rx_st_ready), - .p0_rx_st_sop_o(rx_st_sop), - .p0_rx_st_eop_o(rx_st_eop), - .p0_rx_st_data_o(rx_st_data), - .p0_rx_st_valid_o(rx_st_valid), - .p0_rx_st_empty_o(rx_st_empty), - .p0_rx_st_hdr_o(rx_st_hdr), - .p0_rx_st_tlp_prfx_o(rx_st_tlp_prfx), - .p0_rx_st_bar_range_o(rx_st_bar_range), - .p0_rx_st_tlp_abort_o(rx_st_tlp_abort), - .p0_rx_par_err_o(), - .p0_tx_st_sop_i(tx_st_sop), - .p0_tx_st_eop_i(tx_st_eop), - .p0_tx_st_data_i(tx_st_data), - .p0_tx_st_valid_i(tx_st_valid), - .p0_tx_st_err_i(tx_st_err), - .p0_tx_st_ready_o(tx_st_ready), - .p0_tx_st_hdr_i(tx_st_hdr), - .p0_tx_st_tlp_prfx_i(tx_st_tlp_prfx), - .p0_tx_par_err_o(), - .p0_tx_cdts_limit_o(tx_cdts_limit), - .p0_tx_cdts_limit_tdm_idx_o(tx_cdts_limit_tdm_idx), - .p0_tl_cfg_func_o(tl_cfg_func), - .p0_tl_cfg_add_o(tl_cfg_add), - .p0_tl_cfg_ctl_o(tl_cfg_ctl), - .p0_dl_timer_update_o(), - .p0_reset_status_n(reset_status_n), - .p0_pin_perst_n(), - .p0_link_up_o(), - .p0_dl_up_o(), - .p0_surprise_down_err_o(), - .p0_ltssm_state_o(), - .rx_n_in0(pcie_rx_n[0]), - .rx_n_in1(pcie_rx_n[1]), - .rx_n_in2(pcie_rx_n[2]), - .rx_n_in3(pcie_rx_n[3]), - .rx_n_in4(pcie_rx_n[4]), - .rx_n_in5(pcie_rx_n[5]), - .rx_n_in6(pcie_rx_n[6]), - .rx_n_in7(pcie_rx_n[7]), - .rx_n_in8(pcie_rx_n[8]), - .rx_n_in9(pcie_rx_n[9]), - .rx_n_in10(pcie_rx_n[10]), - .rx_n_in11(pcie_rx_n[11]), - .rx_n_in12(pcie_rx_n[12]), - .rx_n_in13(pcie_rx_n[13]), - .rx_n_in14(pcie_rx_n[14]), - .rx_n_in15(pcie_rx_n[15]), - .rx_p_in0(pcie_rx_p[0]), - .rx_p_in1(pcie_rx_p[1]), - .rx_p_in2(pcie_rx_p[2]), - .rx_p_in3(pcie_rx_p[3]), - .rx_p_in4(pcie_rx_p[4]), - .rx_p_in5(pcie_rx_p[5]), - .rx_p_in6(pcie_rx_p[6]), - .rx_p_in7(pcie_rx_p[7]), - .rx_p_in8(pcie_rx_p[8]), - .rx_p_in9(pcie_rx_p[9]), - .rx_p_in10(pcie_rx_p[10]), - .rx_p_in11(pcie_rx_p[11]), - .rx_p_in12(pcie_rx_p[12]), - .rx_p_in13(pcie_rx_p[13]), - .rx_p_in14(pcie_rx_p[14]), - .rx_p_in15(pcie_rx_p[15]), - .tx_n_out0(pcie_tx_n[0]), - .tx_n_out1(pcie_tx_n[1]), - .tx_n_out2(pcie_tx_n[2]), - .tx_n_out3(pcie_tx_n[3]), - .tx_n_out4(pcie_tx_n[4]), - .tx_n_out5(pcie_tx_n[5]), - .tx_n_out6(pcie_tx_n[6]), - .tx_n_out7(pcie_tx_n[7]), - .tx_n_out8(pcie_tx_n[8]), - .tx_n_out9(pcie_tx_n[9]), - .tx_n_out10(pcie_tx_n[10]), - .tx_n_out11(pcie_tx_n[11]), - .tx_n_out12(pcie_tx_n[12]), - .tx_n_out13(pcie_tx_n[13]), - .tx_n_out14(pcie_tx_n[14]), - .tx_n_out15(pcie_tx_n[15]), - .tx_p_out0(pcie_tx_p[0]), - .tx_p_out1(pcie_tx_p[1]), - .tx_p_out2(pcie_tx_p[2]), - .tx_p_out3(pcie_tx_p[3]), - .tx_p_out4(pcie_tx_p[4]), - .tx_p_out5(pcie_tx_p[5]), - .tx_p_out6(pcie_tx_p[6]), - .tx_p_out7(pcie_tx_p[7]), - .tx_p_out8(pcie_tx_p[8]), - .tx_p_out9(pcie_tx_p[9]), - .tx_p_out10(pcie_tx_p[10]), - .tx_p_out11(pcie_tx_p[11]), - .tx_p_out12(pcie_tx_p[12]), - .tx_p_out13(pcie_tx_p[13]), - .tx_p_out14(pcie_tx_p[14]), - .tx_p_out15(pcie_tx_p[15]), - .coreclkout_hip(coreclkout_hip), - .refclk0(clk_100m_pcie_0_p), - .refclk1(clk_100m_pcie_1_p), - .pin_perst_n(pcie_rst_n), - .ninit_done(ninit_done) -); - -// QSFP28 interfaces - -wire etile_iopll_locked; -wire etile_ptp_sample_clk; - -iopll_etile_ptp iopll_etile_ptp_inst ( - .rst (rst_100mhz), - .refclk (clk_100mhz), - .locked (etile_iopll_locked), - .outclk_0 (etile_ptp_sample_clk) -); - -// QSFP1 -wire qsfp1_mac_1_tx_clk_int; -wire qsfp1_mac_1_tx_rst_int; - -wire qsfp1_mac_1_tx_ptp_clk_int; -wire qsfp1_mac_1_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfp1_mac_1_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfp1_mac_1_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfp1_mac_1_tx_ptp_ts_tag_int; -wire qsfp1_mac_1_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_1_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_1_tx_axis_tkeep_int; -wire qsfp1_mac_1_tx_axis_tvalid_int; -wire qsfp1_mac_1_tx_axis_tready_int; -wire qsfp1_mac_1_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp1_mac_1_tx_axis_tuser_int; - -wire qsfp1_mac_1_tx_status_int; -wire qsfp1_mac_1_tx_lfc_req_int; -wire [7:0] qsfp1_mac_1_tx_pfc_req_int; - -wire qsfp1_mac_1_rx_clk_int; -wire qsfp1_mac_1_rx_rst_int; - -wire qsfp1_mac_1_rx_ptp_clk_int; -wire qsfp1_mac_1_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfp1_mac_1_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_1_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_1_rx_axis_tkeep_int; -wire qsfp1_mac_1_rx_axis_tvalid_int; -wire qsfp1_mac_1_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp1_mac_1_rx_axis_tuser_int; - -wire qsfp1_mac_1_rx_status_int; -wire qsfp1_mac_1_rx_lfc_req_int; -wire [7:0] qsfp1_mac_1_rx_pfc_req_int; - -wire qsfp1_mac_2_tx_clk_int; -wire qsfp1_mac_2_tx_rst_int; - -wire qsfp1_mac_2_tx_ptp_clk_int; -wire qsfp1_mac_2_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfp1_mac_2_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfp1_mac_2_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfp1_mac_2_tx_ptp_ts_tag_int; -wire qsfp1_mac_2_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_2_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_2_tx_axis_tkeep_int; -wire qsfp1_mac_2_tx_axis_tvalid_int; -wire qsfp1_mac_2_tx_axis_tready_int; -wire qsfp1_mac_2_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp1_mac_2_tx_axis_tuser_int; - -wire qsfp1_mac_2_tx_status_int; -wire qsfp1_mac_2_tx_lfc_req_int; -wire [7:0] qsfp1_mac_2_tx_pfc_req_int; - -wire qsfp1_mac_2_rx_clk_int; -wire qsfp1_mac_2_rx_rst_int; - -wire qsfp1_mac_2_rx_ptp_clk_int; -wire qsfp1_mac_2_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfp1_mac_2_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_2_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_2_rx_axis_tkeep_int; -wire qsfp1_mac_2_rx_axis_tvalid_int; -wire qsfp1_mac_2_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp1_mac_2_rx_axis_tuser_int; - -wire qsfp1_mac_2_rx_status_int; -wire qsfp1_mac_2_rx_lfc_req_int; -wire [7:0] qsfp1_mac_2_rx_pfc_req_int; - -wire qsfp1_mac_3_tx_clk_int; -wire qsfp1_mac_3_tx_rst_int; - -wire qsfp1_mac_3_tx_ptp_clk_int; -wire qsfp1_mac_3_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfp1_mac_3_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfp1_mac_3_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfp1_mac_3_tx_ptp_ts_tag_int; -wire qsfp1_mac_3_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_3_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_3_tx_axis_tkeep_int; -wire qsfp1_mac_3_tx_axis_tvalid_int; -wire qsfp1_mac_3_tx_axis_tready_int; -wire qsfp1_mac_3_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp1_mac_3_tx_axis_tuser_int; - -wire qsfp1_mac_3_tx_status_int; -wire qsfp1_mac_3_tx_lfc_req_int; -wire [7:0] qsfp1_mac_3_tx_pfc_req_int; - -wire qsfp1_mac_3_rx_clk_int; -wire qsfp1_mac_3_rx_rst_int; - -wire qsfp1_mac_3_rx_ptp_clk_int; -wire qsfp1_mac_3_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfp1_mac_3_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_3_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_3_rx_axis_tkeep_int; -wire qsfp1_mac_3_rx_axis_tvalid_int; -wire qsfp1_mac_3_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp1_mac_3_rx_axis_tuser_int; - -wire qsfp1_mac_3_rx_status_int; -wire qsfp1_mac_3_rx_lfc_req_int; -wire [7:0] qsfp1_mac_3_rx_pfc_req_int; - -wire qsfp1_mac_4_tx_clk_int; -wire qsfp1_mac_4_tx_rst_int; - -wire qsfp1_mac_4_tx_ptp_clk_int; -wire qsfp1_mac_4_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfp1_mac_4_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfp1_mac_4_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfp1_mac_4_tx_ptp_ts_tag_int; -wire qsfp1_mac_4_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_4_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_4_tx_axis_tkeep_int; -wire qsfp1_mac_4_tx_axis_tvalid_int; -wire qsfp1_mac_4_tx_axis_tready_int; -wire qsfp1_mac_4_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp1_mac_4_tx_axis_tuser_int; - -wire qsfp1_mac_4_tx_status_int; -wire qsfp1_mac_4_tx_lfc_req_int; -wire [7:0] qsfp1_mac_4_tx_pfc_req_int; - -wire qsfp1_mac_4_rx_clk_int; -wire qsfp1_mac_4_rx_rst_int; - -wire qsfp1_mac_4_rx_ptp_clk_int; -wire qsfp1_mac_4_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfp1_mac_4_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_4_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_4_rx_axis_tkeep_int; -wire qsfp1_mac_4_rx_axis_tvalid_int; -wire qsfp1_mac_4_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp1_mac_4_rx_axis_tuser_int; - -wire qsfp1_mac_4_rx_status_int; -wire qsfp1_mac_4_rx_lfc_req_int; -wire [7:0] qsfp1_mac_4_rx_pfc_req_int; - -eth_mac_quad_wrapper #( - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_TAG_WIDTH(PTP_TAG_WIDTH), - .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .MAC_RSFEC(MAC_RSFEC) -) -qsfp1_mac_inst ( - .ctrl_clk(clk_100mhz), - .ctrl_rst(rst_100mhz), - - .tx_serial_data_p({qsfp1_tx_p[3], qsfp1_tx_p[1], qsfp1_tx_p[2], qsfp1_tx_p[0]}), - .tx_serial_data_n({qsfp1_tx_n[3], qsfp1_tx_n[1], qsfp1_tx_n[2], qsfp1_tx_n[0]}), - .rx_serial_data_p({qsfp1_rx_p[3], qsfp1_rx_p[1], qsfp1_rx_p[2], qsfp1_rx_p[0]}), - .rx_serial_data_n({qsfp1_rx_n[3], qsfp1_rx_n[1], qsfp1_rx_n[2], qsfp1_rx_n[0]}), - .ref_clk(clk_156p25m_qsfp0_p), - .ptp_sample_clk(etile_ptp_sample_clk), - - .mac_1_tx_clk(qsfp1_mac_1_tx_clk_int), - .mac_1_tx_rst(qsfp1_mac_1_tx_rst_int), - - .mac_1_tx_ptp_clk(qsfp1_mac_1_tx_ptp_clk_int), - .mac_1_tx_ptp_rst(qsfp1_mac_1_tx_ptp_rst_int), - .mac_1_tx_ptp_time(qsfp1_mac_1_tx_ptp_time_int), - - .mac_1_tx_ptp_ts(qsfp1_mac_1_tx_ptp_ts_int), - .mac_1_tx_ptp_ts_tag(qsfp1_mac_1_tx_ptp_ts_tag_int), - .mac_1_tx_ptp_ts_valid(qsfp1_mac_1_tx_ptp_ts_valid_int), - - .mac_1_tx_axis_tdata(qsfp1_mac_1_tx_axis_tdata_int), - .mac_1_tx_axis_tkeep(qsfp1_mac_1_tx_axis_tkeep_int), - .mac_1_tx_axis_tvalid(qsfp1_mac_1_tx_axis_tvalid_int), - .mac_1_tx_axis_tready(qsfp1_mac_1_tx_axis_tready_int), - .mac_1_tx_axis_tlast(qsfp1_mac_1_tx_axis_tlast_int), - .mac_1_tx_axis_tuser(qsfp1_mac_1_tx_axis_tuser_int), - - .mac_1_tx_status(qsfp1_mac_1_tx_status_int), - .mac_1_tx_lfc_req(qsfp1_mac_1_tx_lfc_req_int), - .mac_1_tx_pfc_req(qsfp1_mac_1_tx_pfc_req_int), - - .mac_1_rx_clk(qsfp1_mac_1_rx_clk_int), - .mac_1_rx_rst(qsfp1_mac_1_rx_rst_int), - - .mac_1_rx_ptp_clk(qsfp1_mac_1_rx_ptp_clk_int), - .mac_1_rx_ptp_rst(qsfp1_mac_1_rx_ptp_rst_int), - .mac_1_rx_ptp_time(qsfp1_mac_1_rx_ptp_time_int), - - .mac_1_rx_axis_tdata(qsfp1_mac_1_rx_axis_tdata_int), - .mac_1_rx_axis_tkeep(qsfp1_mac_1_rx_axis_tkeep_int), - .mac_1_rx_axis_tvalid(qsfp1_mac_1_rx_axis_tvalid_int), - .mac_1_rx_axis_tlast(qsfp1_mac_1_rx_axis_tlast_int), - .mac_1_rx_axis_tuser(qsfp1_mac_1_rx_axis_tuser_int), - - .mac_1_rx_status(qsfp1_mac_1_rx_status_int), - .mac_1_rx_lfc_req(qsfp1_mac_1_rx_lfc_req_int), - .mac_1_rx_pfc_req(qsfp1_mac_1_rx_pfc_req_int), - - .mac_2_tx_clk(qsfp1_mac_3_tx_clk_int), - .mac_2_tx_rst(qsfp1_mac_3_tx_rst_int), - - .mac_2_tx_ptp_clk(qsfp1_mac_3_tx_ptp_clk_int), - .mac_2_tx_ptp_rst(qsfp1_mac_3_tx_ptp_rst_int), - .mac_2_tx_ptp_time(qsfp1_mac_3_tx_ptp_time_int), - - .mac_2_tx_ptp_ts(qsfp1_mac_3_tx_ptp_ts_int), - .mac_2_tx_ptp_ts_tag(qsfp1_mac_3_tx_ptp_ts_tag_int), - .mac_2_tx_ptp_ts_valid(qsfp1_mac_3_tx_ptp_ts_valid_int), - - .mac_2_tx_axis_tdata(qsfp1_mac_3_tx_axis_tdata_int), - .mac_2_tx_axis_tkeep(qsfp1_mac_3_tx_axis_tkeep_int), - .mac_2_tx_axis_tvalid(qsfp1_mac_3_tx_axis_tvalid_int), - .mac_2_tx_axis_tready(qsfp1_mac_3_tx_axis_tready_int), - .mac_2_tx_axis_tlast(qsfp1_mac_3_tx_axis_tlast_int), - .mac_2_tx_axis_tuser(qsfp1_mac_3_tx_axis_tuser_int), - - .mac_2_tx_status(qsfp1_mac_3_tx_status_int), - .mac_2_tx_lfc_req(qsfp1_mac_3_tx_lfc_req_int), - .mac_2_tx_pfc_req(qsfp1_mac_3_tx_pfc_req_int), - - .mac_2_rx_clk(qsfp1_mac_3_rx_clk_int), - .mac_2_rx_rst(qsfp1_mac_3_rx_rst_int), - - .mac_2_rx_ptp_clk(qsfp1_mac_3_rx_ptp_clk_int), - .mac_2_rx_ptp_rst(qsfp1_mac_3_rx_ptp_rst_int), - .mac_2_rx_ptp_time(qsfp1_mac_3_rx_ptp_time_int), - - .mac_2_rx_axis_tdata(qsfp1_mac_3_rx_axis_tdata_int), - .mac_2_rx_axis_tkeep(qsfp1_mac_3_rx_axis_tkeep_int), - .mac_2_rx_axis_tvalid(qsfp1_mac_3_rx_axis_tvalid_int), - .mac_2_rx_axis_tlast(qsfp1_mac_3_rx_axis_tlast_int), - .mac_2_rx_axis_tuser(qsfp1_mac_3_rx_axis_tuser_int), - - .mac_2_rx_status(qsfp1_mac_3_rx_status_int), - .mac_2_rx_lfc_req(qsfp1_mac_3_rx_lfc_req_int), - .mac_2_rx_pfc_req(qsfp1_mac_3_rx_pfc_req_int), - - .mac_3_tx_clk(qsfp1_mac_2_tx_clk_int), - .mac_3_tx_rst(qsfp1_mac_2_tx_rst_int), - - .mac_3_tx_ptp_clk(qsfp1_mac_2_tx_ptp_clk_int), - .mac_3_tx_ptp_rst(qsfp1_mac_2_tx_ptp_rst_int), - .mac_3_tx_ptp_time(qsfp1_mac_2_tx_ptp_time_int), - - .mac_3_tx_ptp_ts(qsfp1_mac_2_tx_ptp_ts_int), - .mac_3_tx_ptp_ts_tag(qsfp1_mac_2_tx_ptp_ts_tag_int), - .mac_3_tx_ptp_ts_valid(qsfp1_mac_2_tx_ptp_ts_valid_int), - - .mac_3_tx_axis_tdata(qsfp1_mac_2_tx_axis_tdata_int), - .mac_3_tx_axis_tkeep(qsfp1_mac_2_tx_axis_tkeep_int), - .mac_3_tx_axis_tvalid(qsfp1_mac_2_tx_axis_tvalid_int), - .mac_3_tx_axis_tready(qsfp1_mac_2_tx_axis_tready_int), - .mac_3_tx_axis_tlast(qsfp1_mac_2_tx_axis_tlast_int), - .mac_3_tx_axis_tuser(qsfp1_mac_2_tx_axis_tuser_int), - - .mac_3_tx_status(qsfp1_mac_2_tx_status_int), - .mac_3_tx_lfc_req(qsfp1_mac_2_tx_lfc_req_int), - .mac_3_tx_pfc_req(qsfp1_mac_2_tx_pfc_req_int), - - .mac_3_rx_clk(qsfp1_mac_2_rx_clk_int), - .mac_3_rx_rst(qsfp1_mac_2_rx_rst_int), - - .mac_3_rx_ptp_clk(qsfp1_mac_2_rx_ptp_clk_int), - .mac_3_rx_ptp_rst(qsfp1_mac_2_rx_ptp_rst_int), - .mac_3_rx_ptp_time(qsfp1_mac_2_rx_ptp_time_int), - - .mac_3_rx_axis_tdata(qsfp1_mac_2_rx_axis_tdata_int), - .mac_3_rx_axis_tkeep(qsfp1_mac_2_rx_axis_tkeep_int), - .mac_3_rx_axis_tvalid(qsfp1_mac_2_rx_axis_tvalid_int), - .mac_3_rx_axis_tlast(qsfp1_mac_2_rx_axis_tlast_int), - .mac_3_rx_axis_tuser(qsfp1_mac_2_rx_axis_tuser_int), - - .mac_3_rx_status(qsfp1_mac_2_rx_status_int), - .mac_3_rx_lfc_req(qsfp1_mac_2_rx_lfc_req_int), - .mac_3_rx_pfc_req(qsfp1_mac_2_rx_pfc_req_int), - - .mac_4_tx_clk(qsfp1_mac_4_tx_clk_int), - .mac_4_tx_rst(qsfp1_mac_4_tx_rst_int), - - .mac_4_tx_ptp_clk(qsfp1_mac_4_tx_ptp_clk_int), - .mac_4_tx_ptp_rst(qsfp1_mac_4_tx_ptp_rst_int), - .mac_4_tx_ptp_time(qsfp1_mac_4_tx_ptp_time_int), - - .mac_4_tx_ptp_ts(qsfp1_mac_4_tx_ptp_ts_int), - .mac_4_tx_ptp_ts_tag(qsfp1_mac_4_tx_ptp_ts_tag_int), - .mac_4_tx_ptp_ts_valid(qsfp1_mac_4_tx_ptp_ts_valid_int), - - .mac_4_tx_axis_tdata(qsfp1_mac_4_tx_axis_tdata_int), - .mac_4_tx_axis_tkeep(qsfp1_mac_4_tx_axis_tkeep_int), - .mac_4_tx_axis_tvalid(qsfp1_mac_4_tx_axis_tvalid_int), - .mac_4_tx_axis_tready(qsfp1_mac_4_tx_axis_tready_int), - .mac_4_tx_axis_tlast(qsfp1_mac_4_tx_axis_tlast_int), - .mac_4_tx_axis_tuser(qsfp1_mac_4_tx_axis_tuser_int), - - .mac_4_tx_status(qsfp1_mac_4_tx_status_int), - .mac_4_tx_lfc_req(qsfp1_mac_4_tx_lfc_req_int), - .mac_4_tx_pfc_req(qsfp1_mac_4_tx_pfc_req_int), - - .mac_4_rx_clk(qsfp1_mac_4_rx_clk_int), - .mac_4_rx_rst(qsfp1_mac_4_rx_rst_int), - - .mac_4_rx_ptp_clk(qsfp1_mac_4_rx_ptp_clk_int), - .mac_4_rx_ptp_rst(qsfp1_mac_4_rx_ptp_rst_int), - .mac_4_rx_ptp_time(qsfp1_mac_4_rx_ptp_time_int), - - .mac_4_rx_axis_tdata(qsfp1_mac_4_rx_axis_tdata_int), - .mac_4_rx_axis_tkeep(qsfp1_mac_4_rx_axis_tkeep_int), - .mac_4_rx_axis_tvalid(qsfp1_mac_4_rx_axis_tvalid_int), - .mac_4_rx_axis_tlast(qsfp1_mac_4_rx_axis_tlast_int), - .mac_4_rx_axis_tuser(qsfp1_mac_4_rx_axis_tuser_int), - - .mac_4_rx_status(qsfp1_mac_4_rx_status_int), - .mac_4_rx_lfc_req(qsfp1_mac_4_rx_lfc_req_int), - .mac_4_rx_pfc_req(qsfp1_mac_4_rx_pfc_req_int) -); - -// QSFP2 -wire qsfp2_mac_1_tx_clk_int; -wire qsfp2_mac_1_tx_rst_int; - -wire qsfp2_mac_1_tx_ptp_clk_int; -wire qsfp2_mac_1_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfp2_mac_1_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfp2_mac_1_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfp2_mac_1_tx_ptp_ts_tag_int; -wire qsfp2_mac_1_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_1_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_1_tx_axis_tkeep_int; -wire qsfp2_mac_1_tx_axis_tvalid_int; -wire qsfp2_mac_1_tx_axis_tready_int; -wire qsfp2_mac_1_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp2_mac_1_tx_axis_tuser_int; - -wire qsfp2_mac_1_tx_status_int; -wire qsfp2_mac_1_tx_lfc_req_int; -wire [7:0] qsfp2_mac_1_tx_pfc_req_int; - -wire qsfp2_mac_1_rx_clk_int; -wire qsfp2_mac_1_rx_rst_int; - -wire qsfp2_mac_1_rx_ptp_clk_int; -wire qsfp2_mac_1_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfp2_mac_1_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_1_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_1_rx_axis_tkeep_int; -wire qsfp2_mac_1_rx_axis_tvalid_int; -wire qsfp2_mac_1_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp2_mac_1_rx_axis_tuser_int; - -wire qsfp2_mac_1_rx_status_int; -wire qsfp2_mac_1_rx_lfc_req_int; -wire [7:0] qsfp2_mac_1_rx_pfc_req_int; - -wire qsfp2_mac_2_tx_clk_int; -wire qsfp2_mac_2_tx_rst_int; - -wire qsfp2_mac_2_tx_ptp_clk_int; -wire qsfp2_mac_2_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfp2_mac_2_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfp2_mac_2_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfp2_mac_2_tx_ptp_ts_tag_int; -wire qsfp2_mac_2_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_2_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_2_tx_axis_tkeep_int; -wire qsfp2_mac_2_tx_axis_tvalid_int; -wire qsfp2_mac_2_tx_axis_tready_int; -wire qsfp2_mac_2_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp2_mac_2_tx_axis_tuser_int; - -wire qsfp2_mac_2_tx_status_int; -wire qsfp2_mac_2_tx_lfc_req_int; -wire [7:0] qsfp2_mac_2_tx_pfc_req_int; - -wire qsfp2_mac_2_rx_clk_int; -wire qsfp2_mac_2_rx_rst_int; - -wire qsfp2_mac_2_rx_ptp_clk_int; -wire qsfp2_mac_2_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfp2_mac_2_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_2_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_2_rx_axis_tkeep_int; -wire qsfp2_mac_2_rx_axis_tvalid_int; -wire qsfp2_mac_2_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp2_mac_2_rx_axis_tuser_int; - -wire qsfp2_mac_2_rx_status_int; -wire qsfp2_mac_2_rx_lfc_req_int; -wire [7:0] qsfp2_mac_2_rx_pfc_req_int; - -wire qsfp2_mac_3_tx_clk_int; -wire qsfp2_mac_3_tx_rst_int; - -wire qsfp2_mac_3_tx_ptp_clk_int; -wire qsfp2_mac_3_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfp2_mac_3_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfp2_mac_3_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfp2_mac_3_tx_ptp_ts_tag_int; -wire qsfp2_mac_3_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_3_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_3_tx_axis_tkeep_int; -wire qsfp2_mac_3_tx_axis_tvalid_int; -wire qsfp2_mac_3_tx_axis_tready_int; -wire qsfp2_mac_3_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp2_mac_3_tx_axis_tuser_int; - -wire qsfp2_mac_3_tx_status_int; -wire qsfp2_mac_3_tx_lfc_req_int; -wire [7:0] qsfp2_mac_3_tx_pfc_req_int; - -wire qsfp2_mac_3_rx_clk_int; -wire qsfp2_mac_3_rx_rst_int; - -wire qsfp2_mac_3_rx_ptp_clk_int; -wire qsfp2_mac_3_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfp2_mac_3_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_3_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_3_rx_axis_tkeep_int; -wire qsfp2_mac_3_rx_axis_tvalid_int; -wire qsfp2_mac_3_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp2_mac_3_rx_axis_tuser_int; - -wire qsfp2_mac_3_rx_status_int; -wire qsfp2_mac_3_rx_lfc_req_int; -wire [7:0] qsfp2_mac_3_rx_pfc_req_int; - -wire qsfp2_mac_4_tx_clk_int; -wire qsfp2_mac_4_tx_rst_int; - -wire qsfp2_mac_4_tx_ptp_clk_int; -wire qsfp2_mac_4_tx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfp2_mac_4_tx_ptp_time_int; - -wire [PTP_TS_WIDTH-1:0] qsfp2_mac_4_tx_ptp_ts_int; -wire [PTP_TAG_WIDTH-1:0] qsfp2_mac_4_tx_ptp_ts_tag_int; -wire qsfp2_mac_4_tx_ptp_ts_valid_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_4_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_4_tx_axis_tkeep_int; -wire qsfp2_mac_4_tx_axis_tvalid_int; -wire qsfp2_mac_4_tx_axis_tready_int; -wire qsfp2_mac_4_tx_axis_tlast_int; -wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp2_mac_4_tx_axis_tuser_int; - -wire qsfp2_mac_4_tx_status_int; -wire qsfp2_mac_4_tx_lfc_req_int; -wire [7:0] qsfp2_mac_4_tx_pfc_req_int; - -wire qsfp2_mac_4_rx_clk_int; -wire qsfp2_mac_4_rx_rst_int; - -wire qsfp2_mac_4_rx_ptp_clk_int; -wire qsfp2_mac_4_rx_ptp_rst_int; -wire [PTP_TS_WIDTH-1:0] qsfp2_mac_4_rx_ptp_time_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_4_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_4_rx_axis_tkeep_int; -wire qsfp2_mac_4_rx_axis_tvalid_int; -wire qsfp2_mac_4_rx_axis_tlast_int; -wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp2_mac_4_rx_axis_tuser_int; - -wire qsfp2_mac_4_rx_status_int; -wire qsfp2_mac_4_rx_lfc_req_int; -wire [7:0] qsfp2_mac_4_rx_pfc_req_int; - -eth_mac_quad_wrapper #( - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_TAG_WIDTH(PTP_TAG_WIDTH), - .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .MAC_RSFEC(MAC_RSFEC) -) -qsfp2_mac_inst ( - .ctrl_clk(clk_100mhz), - .ctrl_rst(rst_100mhz), - - .tx_serial_data_p({qsfp2_tx_p[3], qsfp2_tx_p[1], qsfp2_tx_p[2], qsfp2_tx_p[0]}), - .tx_serial_data_n({qsfp2_tx_n[3], qsfp2_tx_n[1], qsfp2_tx_n[2], qsfp2_tx_n[0]}), - .rx_serial_data_p({qsfp2_rx_p[3], qsfp2_rx_p[1], qsfp2_rx_p[2], qsfp2_rx_p[0]}), - .rx_serial_data_n({qsfp2_rx_n[3], qsfp2_rx_n[1], qsfp2_rx_n[2], qsfp2_rx_n[0]}), - .ref_clk(clk_156p25m_qsfp0_p), - .ptp_sample_clk(etile_ptp_sample_clk), - - .mac_1_tx_clk(qsfp2_mac_1_tx_clk_int), - .mac_1_tx_rst(qsfp2_mac_1_tx_rst_int), - - .mac_1_tx_ptp_clk(qsfp2_mac_1_tx_ptp_clk_int), - .mac_1_tx_ptp_rst(qsfp2_mac_1_tx_ptp_rst_int), - .mac_1_tx_ptp_time(qsfp2_mac_1_tx_ptp_time_int), - - .mac_1_tx_ptp_ts(qsfp2_mac_1_tx_ptp_ts_int), - .mac_1_tx_ptp_ts_tag(qsfp2_mac_1_tx_ptp_ts_tag_int), - .mac_1_tx_ptp_ts_valid(qsfp2_mac_1_tx_ptp_ts_valid_int), - - .mac_1_tx_axis_tdata(qsfp2_mac_1_tx_axis_tdata_int), - .mac_1_tx_axis_tkeep(qsfp2_mac_1_tx_axis_tkeep_int), - .mac_1_tx_axis_tvalid(qsfp2_mac_1_tx_axis_tvalid_int), - .mac_1_tx_axis_tready(qsfp2_mac_1_tx_axis_tready_int), - .mac_1_tx_axis_tlast(qsfp2_mac_1_tx_axis_tlast_int), - .mac_1_tx_axis_tuser(qsfp2_mac_1_tx_axis_tuser_int), - - .mac_1_tx_status(qsfp2_mac_1_tx_status_int), - .mac_1_tx_lfc_req(qsfp2_mac_1_tx_lfc_req_int), - .mac_1_tx_pfc_req(qsfp2_mac_1_tx_pfc_req_int), - - .mac_1_rx_clk(qsfp2_mac_1_rx_clk_int), - .mac_1_rx_rst(qsfp2_mac_1_rx_rst_int), - - .mac_1_rx_ptp_clk(qsfp2_mac_1_rx_ptp_clk_int), - .mac_1_rx_ptp_rst(qsfp2_mac_1_rx_ptp_rst_int), - .mac_1_rx_ptp_time(qsfp2_mac_1_rx_ptp_time_int), - - .mac_1_rx_axis_tdata(qsfp2_mac_1_rx_axis_tdata_int), - .mac_1_rx_axis_tkeep(qsfp2_mac_1_rx_axis_tkeep_int), - .mac_1_rx_axis_tvalid(qsfp2_mac_1_rx_axis_tvalid_int), - .mac_1_rx_axis_tlast(qsfp2_mac_1_rx_axis_tlast_int), - .mac_1_rx_axis_tuser(qsfp2_mac_1_rx_axis_tuser_int), - - .mac_1_rx_status(qsfp2_mac_1_rx_status_int), - .mac_1_rx_lfc_req(qsfp2_mac_1_rx_lfc_req_int), - .mac_1_rx_pfc_req(qsfp2_mac_1_rx_pfc_req_int), - - .mac_2_tx_clk(qsfp2_mac_3_tx_clk_int), - .mac_2_tx_rst(qsfp2_mac_3_tx_rst_int), - - .mac_2_tx_ptp_clk(qsfp2_mac_3_tx_ptp_clk_int), - .mac_2_tx_ptp_rst(qsfp2_mac_3_tx_ptp_rst_int), - .mac_2_tx_ptp_time(qsfp2_mac_3_tx_ptp_time_int), - - .mac_2_tx_ptp_ts(qsfp2_mac_3_tx_ptp_ts_int), - .mac_2_tx_ptp_ts_tag(qsfp2_mac_3_tx_ptp_ts_tag_int), - .mac_2_tx_ptp_ts_valid(qsfp2_mac_3_tx_ptp_ts_valid_int), - - .mac_2_tx_axis_tdata(qsfp2_mac_3_tx_axis_tdata_int), - .mac_2_tx_axis_tkeep(qsfp2_mac_3_tx_axis_tkeep_int), - .mac_2_tx_axis_tvalid(qsfp2_mac_3_tx_axis_tvalid_int), - .mac_2_tx_axis_tready(qsfp2_mac_3_tx_axis_tready_int), - .mac_2_tx_axis_tlast(qsfp2_mac_3_tx_axis_tlast_int), - .mac_2_tx_axis_tuser(qsfp2_mac_3_tx_axis_tuser_int), - - .mac_2_tx_status(qsfp2_mac_3_tx_status_int), - .mac_2_tx_lfc_req(qsfp2_mac_3_tx_lfc_req_int), - .mac_2_tx_pfc_req(qsfp2_mac_3_tx_pfc_req_int), - - .mac_2_rx_clk(qsfp2_mac_3_rx_clk_int), - .mac_2_rx_rst(qsfp2_mac_3_rx_rst_int), - - .mac_2_rx_ptp_clk(qsfp2_mac_3_rx_ptp_clk_int), - .mac_2_rx_ptp_rst(qsfp2_mac_3_rx_ptp_rst_int), - .mac_2_rx_ptp_time(qsfp2_mac_3_rx_ptp_time_int), - - .mac_2_rx_axis_tdata(qsfp2_mac_3_rx_axis_tdata_int), - .mac_2_rx_axis_tkeep(qsfp2_mac_3_rx_axis_tkeep_int), - .mac_2_rx_axis_tvalid(qsfp2_mac_3_rx_axis_tvalid_int), - .mac_2_rx_axis_tlast(qsfp2_mac_3_rx_axis_tlast_int), - .mac_2_rx_axis_tuser(qsfp2_mac_3_rx_axis_tuser_int), - - .mac_2_rx_status(qsfp2_mac_3_rx_status_int), - .mac_2_rx_lfc_req(qsfp2_mac_3_rx_lfc_req_int), - .mac_2_rx_pfc_req(qsfp2_mac_3_rx_pfc_req_int), - - .mac_3_tx_clk(qsfp2_mac_2_tx_clk_int), - .mac_3_tx_rst(qsfp2_mac_2_tx_rst_int), - - .mac_3_tx_ptp_clk(qsfp2_mac_2_tx_ptp_clk_int), - .mac_3_tx_ptp_rst(qsfp2_mac_2_tx_ptp_rst_int), - .mac_3_tx_ptp_time(qsfp2_mac_2_tx_ptp_time_int), - - .mac_3_tx_ptp_ts(qsfp2_mac_2_tx_ptp_ts_int), - .mac_3_tx_ptp_ts_tag(qsfp2_mac_2_tx_ptp_ts_tag_int), - .mac_3_tx_ptp_ts_valid(qsfp2_mac_2_tx_ptp_ts_valid_int), - - .mac_3_tx_axis_tdata(qsfp2_mac_2_tx_axis_tdata_int), - .mac_3_tx_axis_tkeep(qsfp2_mac_2_tx_axis_tkeep_int), - .mac_3_tx_axis_tvalid(qsfp2_mac_2_tx_axis_tvalid_int), - .mac_3_tx_axis_tready(qsfp2_mac_2_tx_axis_tready_int), - .mac_3_tx_axis_tlast(qsfp2_mac_2_tx_axis_tlast_int), - .mac_3_tx_axis_tuser(qsfp2_mac_2_tx_axis_tuser_int), - - .mac_3_tx_status(qsfp2_mac_2_tx_status_int), - .mac_3_tx_lfc_req(qsfp2_mac_2_tx_lfc_req_int), - .mac_3_tx_pfc_req(qsfp2_mac_2_tx_pfc_req_int), - - .mac_3_rx_clk(qsfp2_mac_2_rx_clk_int), - .mac_3_rx_rst(qsfp2_mac_2_rx_rst_int), - - .mac_3_rx_ptp_clk(qsfp2_mac_2_rx_ptp_clk_int), - .mac_3_rx_ptp_rst(qsfp2_mac_2_rx_ptp_rst_int), - .mac_3_rx_ptp_time(qsfp2_mac_2_rx_ptp_time_int), - - .mac_3_rx_axis_tdata(qsfp2_mac_2_rx_axis_tdata_int), - .mac_3_rx_axis_tkeep(qsfp2_mac_2_rx_axis_tkeep_int), - .mac_3_rx_axis_tvalid(qsfp2_mac_2_rx_axis_tvalid_int), - .mac_3_rx_axis_tlast(qsfp2_mac_2_rx_axis_tlast_int), - .mac_3_rx_axis_tuser(qsfp2_mac_2_rx_axis_tuser_int), - - .mac_3_rx_status(qsfp2_mac_2_rx_status_int), - .mac_3_rx_lfc_req(qsfp2_mac_2_rx_lfc_req_int), - .mac_3_rx_pfc_req(qsfp2_mac_2_rx_pfc_req_int), - - .mac_4_tx_clk(qsfp2_mac_4_tx_clk_int), - .mac_4_tx_rst(qsfp2_mac_4_tx_rst_int), - - .mac_4_tx_ptp_clk(qsfp2_mac_4_tx_ptp_clk_int), - .mac_4_tx_ptp_rst(qsfp2_mac_4_tx_ptp_rst_int), - .mac_4_tx_ptp_time(qsfp2_mac_4_tx_ptp_time_int), - - .mac_4_tx_ptp_ts(qsfp2_mac_4_tx_ptp_ts_int), - .mac_4_tx_ptp_ts_tag(qsfp2_mac_4_tx_ptp_ts_tag_int), - .mac_4_tx_ptp_ts_valid(qsfp2_mac_4_tx_ptp_ts_valid_int), - - .mac_4_tx_axis_tdata(qsfp2_mac_4_tx_axis_tdata_int), - .mac_4_tx_axis_tkeep(qsfp2_mac_4_tx_axis_tkeep_int), - .mac_4_tx_axis_tvalid(qsfp2_mac_4_tx_axis_tvalid_int), - .mac_4_tx_axis_tready(qsfp2_mac_4_tx_axis_tready_int), - .mac_4_tx_axis_tlast(qsfp2_mac_4_tx_axis_tlast_int), - .mac_4_tx_axis_tuser(qsfp2_mac_4_tx_axis_tuser_int), - - .mac_4_tx_status(qsfp2_mac_4_tx_status_int), - .mac_4_tx_lfc_req(qsfp2_mac_4_tx_lfc_req_int), - .mac_4_tx_pfc_req(qsfp2_mac_4_tx_pfc_req_int), - - .mac_4_rx_clk(qsfp2_mac_4_rx_clk_int), - .mac_4_rx_rst(qsfp2_mac_4_rx_rst_int), - - .mac_4_rx_ptp_clk(qsfp2_mac_4_rx_ptp_clk_int), - .mac_4_rx_ptp_rst(qsfp2_mac_4_rx_ptp_rst_int), - .mac_4_rx_ptp_time(qsfp2_mac_4_rx_ptp_time_int), - - .mac_4_rx_axis_tdata(qsfp2_mac_4_rx_axis_tdata_int), - .mac_4_rx_axis_tkeep(qsfp2_mac_4_rx_axis_tkeep_int), - .mac_4_rx_axis_tvalid(qsfp2_mac_4_rx_axis_tvalid_int), - .mac_4_rx_axis_tlast(qsfp2_mac_4_rx_axis_tlast_int), - .mac_4_rx_axis_tuser(qsfp2_mac_4_rx_axis_tuser_int), - - .mac_4_rx_status(qsfp2_mac_4_rx_status_int), - .mac_4_rx_lfc_req(qsfp2_mac_4_rx_lfc_req_int), - .mac_4_rx_pfc_req(qsfp2_mac_4_rx_pfc_req_int) -); - -wire ptp_clk; -wire ptp_rst; -wire ptp_sample_clk; - -assign ptp_sample_clk = clk_100mhz; - -ref_div ref_div_inst ( - .inclk(qsfp1_mac_1_tx_clk_int), - .clock_div1x(), - .clock_div2x(ptp_clk), - .clock_div4x() -); - -sync_reset #( - .N(4) -) -ptp_rst_reset_sync_inst ( - .clk(ptp_clk), - .rst(qsfp1_mac_1_tx_rst_int), - .out(ptp_rst) -); - -fpga_core #( - // FW and board IDs - .FPGA_ID(FPGA_ID), - .FW_ID(FW_ID), - .FW_VER(FW_VER), - .BOARD_ID(BOARD_ID), - .BOARD_VER(BOARD_VER), - .BUILD_DATE(BUILD_DATE), - .GIT_HASH(GIT_HASH), - .RELEASE_INFO(RELEASE_INFO), - - // Structural configuration - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - .SCHED_PER_IF(SCHED_PER_IF), - .PORT_MASK(PORT_MASK), - - // Clock configuration - .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), - .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), - - // PTP configuration - .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), - .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), - .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_TX_CLOCK(1), - .PTP_SEPARATE_RX_CLOCK(1), - .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), - - // Queue manager configuration - .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), - .EQN_WIDTH(EQN_WIDTH), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .CQN_WIDTH(CQN_WIDTH), - .EQ_PIPELINE(EQ_PIPELINE), - .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), - .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .CQ_PIPELINE(CQ_PIPELINE), - - // TX and RX engine configuration - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), - - // Scheduler configuration - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - - // Interface configuration - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), - .TX_TAG_WIDTH(TX_TAG_WIDTH), - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .PFC_ENABLE(PFC_ENABLE), - .LFC_ENABLE(LFC_ENABLE), - .TX_FIFO_DEPTH(TX_FIFO_DEPTH), - .RX_FIFO_DEPTH(RX_FIFO_DEPTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - - // Application block configuration - .APP_ID(APP_ID), - .APP_ENABLE(APP_ENABLE), - .APP_CTRL_ENABLE(APP_CTRL_ENABLE), - .APP_DMA_ENABLE(APP_DMA_ENABLE), - .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), - .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), - .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), - .APP_STAT_ENABLE(APP_STAT_ENABLE), - - // DMA interface configuration - .DMA_IMM_ENABLE(DMA_IMM_ENABLE), - .DMA_IMM_WIDTH(DMA_IMM_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - - // PCIe interface configuration - .SEG_COUNT(SEG_COUNT), - .SEG_DATA_WIDTH(SEG_DATA_WIDTH), - .SEG_EMPTY_WIDTH(SEG_EMPTY_WIDTH), - .TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH), - .PF_COUNT(PF_COUNT), - .VF_COUNT(VF_COUNT), - .PCIE_TAG_COUNT(PCIE_TAG_COUNT), - - // Interrupt configuration - .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), - - // AXI lite interface configuration (control) - .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - - // AXI lite interface configuration (application control) - .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), - .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), - - // Ethernet interface configuration - .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), - .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), - .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), - .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), - .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), - .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), - - // Statistics counter subsystem - .STAT_ENABLE(STAT_ENABLE), - .STAT_DMA_ENABLE(STAT_DMA_ENABLE), - .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), - .STAT_INC_WIDTH(STAT_INC_WIDTH), - .STAT_ID_WIDTH(STAT_ID_WIDTH) -) -core_inst ( - /* - * Clock: 250 MHz - * Synchronous reset - */ - .clk_250mhz(pcie_clk), - .rst_250mhz(pcie_rst), - - /* - * PTP clock - */ - .ptp_clk(ptp_clk), - .ptp_rst(ptp_rst), - .ptp_sample_clk(ptp_sample_clk), - - /* - * GPIO - */ - .user_pb(user_pb), - .user_led_g(user_led_g), - - /* - * I2C - */ - .i2c2_scl_i(i2c2_scl_i), - .i2c2_scl_o(i2c2_scl_o), - .i2c2_scl_t(i2c2_scl_t), - .i2c2_sda_i(i2c2_sda_i), - .i2c2_sda_o(i2c2_sda_o), - .i2c2_sda_t(i2c2_sda_t), - .bmc_i2c2_disable(bmc_i2c2_disable), - - /* - * P-Tile interface - */ - .rx_st_data(rx_st_data), - .rx_st_empty(rx_st_empty), - .rx_st_sop(rx_st_sop), - .rx_st_eop(rx_st_eop), - .rx_st_valid(rx_st_valid), - .rx_st_ready(rx_st_ready), - .rx_st_hdr(rx_st_hdr), - .rx_st_tlp_prfx(rx_st_tlp_prfx), - .rx_st_vf_active(rx_st_vf_active), - .rx_st_func_num(rx_st_func_num), - .rx_st_vf_num(rx_st_vf_num), - .rx_st_bar_range(rx_st_bar_range), - .rx_st_tlp_abort(rx_st_tlp_abort), - - .tx_st_data(tx_st_data), - .tx_st_sop(tx_st_sop), - .tx_st_eop(tx_st_eop), - .tx_st_valid(tx_st_valid), - .tx_st_ready(tx_st_ready), - .tx_st_err(tx_st_err), - .tx_st_hdr(tx_st_hdr), - .tx_st_tlp_prfx(tx_st_tlp_prfx), - - .rx_buffer_limit(rx_buffer_limit), - .rx_buffer_limit_tdm_idx(rx_buffer_limit_tdm_idx), - - .tx_cdts_limit(tx_cdts_limit), - .tx_cdts_limit_tdm_idx(tx_cdts_limit_tdm_idx), - - .tl_cfg_ctl(tl_cfg_ctl), - .tl_cfg_add(tl_cfg_add), - .tl_cfg_func(tl_cfg_func), - - /* - * Ethernet: QSFP28 - */ - .qsfp1_mac_1_tx_clk(qsfp1_mac_1_tx_clk_int), - .qsfp1_mac_1_tx_rst(qsfp1_mac_1_tx_rst_int), - - .qsfp1_mac_1_tx_ptp_clk(qsfp1_mac_1_tx_ptp_clk_int), - .qsfp1_mac_1_tx_ptp_rst(qsfp1_mac_1_tx_ptp_rst_int), - .qsfp1_mac_1_tx_ptp_time(qsfp1_mac_1_tx_ptp_time_int), - - .qsfp1_mac_1_tx_ptp_ts(qsfp1_mac_1_tx_ptp_ts_int), - .qsfp1_mac_1_tx_ptp_ts_tag(qsfp1_mac_1_tx_ptp_ts_tag_int), - .qsfp1_mac_1_tx_ptp_ts_valid(qsfp1_mac_1_tx_ptp_ts_valid_int), - - .qsfp1_mac_1_tx_axis_tdata(qsfp1_mac_1_tx_axis_tdata_int), - .qsfp1_mac_1_tx_axis_tkeep(qsfp1_mac_1_tx_axis_tkeep_int), - .qsfp1_mac_1_tx_axis_tvalid(qsfp1_mac_1_tx_axis_tvalid_int), - .qsfp1_mac_1_tx_axis_tready(qsfp1_mac_1_tx_axis_tready_int), - .qsfp1_mac_1_tx_axis_tlast(qsfp1_mac_1_tx_axis_tlast_int), - .qsfp1_mac_1_tx_axis_tuser(qsfp1_mac_1_tx_axis_tuser_int), - - .qsfp1_mac_1_tx_status(qsfp1_mac_1_tx_status_int), - .qsfp1_mac_1_tx_lfc_req(qsfp1_mac_1_tx_lfc_req_int), - .qsfp1_mac_1_tx_pfc_req(qsfp1_mac_1_tx_pfc_req_int), - - .qsfp1_mac_1_rx_clk(qsfp1_mac_1_rx_clk_int), - .qsfp1_mac_1_rx_rst(qsfp1_mac_1_rx_rst_int), - - .qsfp1_mac_1_rx_ptp_clk(qsfp1_mac_1_rx_ptp_clk_int), - .qsfp1_mac_1_rx_ptp_rst(qsfp1_mac_1_rx_ptp_rst_int), - .qsfp1_mac_1_rx_ptp_time(qsfp1_mac_1_rx_ptp_time_int), - - .qsfp1_mac_1_rx_axis_tdata(qsfp1_mac_1_rx_axis_tdata_int), - .qsfp1_mac_1_rx_axis_tkeep(qsfp1_mac_1_rx_axis_tkeep_int), - .qsfp1_mac_1_rx_axis_tvalid(qsfp1_mac_1_rx_axis_tvalid_int), - .qsfp1_mac_1_rx_axis_tlast(qsfp1_mac_1_rx_axis_tlast_int), - .qsfp1_mac_1_rx_axis_tuser(qsfp1_mac_1_rx_axis_tuser_int), - - .qsfp1_mac_1_rx_status(qsfp1_mac_1_rx_status_int), - .qsfp1_mac_1_rx_lfc_req(qsfp1_mac_1_rx_lfc_req_int), - .qsfp1_mac_1_rx_pfc_req(qsfp1_mac_1_rx_pfc_req_int), - - .qsfp1_mac_2_tx_clk(qsfp1_mac_2_tx_clk_int), - .qsfp1_mac_2_tx_rst(qsfp1_mac_2_tx_rst_int), - - .qsfp1_mac_2_tx_ptp_clk(qsfp1_mac_2_tx_ptp_clk_int), - .qsfp1_mac_2_tx_ptp_rst(qsfp1_mac_2_tx_ptp_rst_int), - .qsfp1_mac_2_tx_ptp_time(qsfp1_mac_2_tx_ptp_time_int), - - .qsfp1_mac_2_tx_ptp_ts(qsfp1_mac_2_tx_ptp_ts_int), - .qsfp1_mac_2_tx_ptp_ts_tag(qsfp1_mac_2_tx_ptp_ts_tag_int), - .qsfp1_mac_2_tx_ptp_ts_valid(qsfp1_mac_2_tx_ptp_ts_valid_int), - - .qsfp1_mac_2_tx_axis_tdata(qsfp1_mac_2_tx_axis_tdata_int), - .qsfp1_mac_2_tx_axis_tkeep(qsfp1_mac_2_tx_axis_tkeep_int), - .qsfp1_mac_2_tx_axis_tvalid(qsfp1_mac_2_tx_axis_tvalid_int), - .qsfp1_mac_2_tx_axis_tready(qsfp1_mac_2_tx_axis_tready_int), - .qsfp1_mac_2_tx_axis_tlast(qsfp1_mac_2_tx_axis_tlast_int), - .qsfp1_mac_2_tx_axis_tuser(qsfp1_mac_2_tx_axis_tuser_int), - - .qsfp1_mac_2_tx_status(qsfp1_mac_2_tx_status_int), - .qsfp1_mac_2_tx_lfc_req(qsfp1_mac_2_tx_lfc_req_int), - .qsfp1_mac_2_tx_pfc_req(qsfp1_mac_2_tx_pfc_req_int), - - .qsfp1_mac_2_rx_clk(qsfp1_mac_2_rx_clk_int), - .qsfp1_mac_2_rx_rst(qsfp1_mac_2_rx_rst_int), - - .qsfp1_mac_2_rx_ptp_clk(qsfp1_mac_2_rx_ptp_clk_int), - .qsfp1_mac_2_rx_ptp_rst(qsfp1_mac_2_rx_ptp_rst_int), - .qsfp1_mac_2_rx_ptp_time(qsfp1_mac_2_rx_ptp_time_int), - - .qsfp1_mac_2_rx_axis_tdata(qsfp1_mac_2_rx_axis_tdata_int), - .qsfp1_mac_2_rx_axis_tkeep(qsfp1_mac_2_rx_axis_tkeep_int), - .qsfp1_mac_2_rx_axis_tvalid(qsfp1_mac_2_rx_axis_tvalid_int), - .qsfp1_mac_2_rx_axis_tlast(qsfp1_mac_2_rx_axis_tlast_int), - .qsfp1_mac_2_rx_axis_tuser(qsfp1_mac_2_rx_axis_tuser_int), - - .qsfp1_mac_2_rx_status(qsfp1_mac_2_rx_status_int), - .qsfp1_mac_2_rx_lfc_req(qsfp1_mac_2_rx_lfc_req_int), - .qsfp1_mac_2_rx_pfc_req(qsfp1_mac_2_rx_pfc_req_int), - - .qsfp1_mac_3_tx_clk(qsfp1_mac_3_tx_clk_int), - .qsfp1_mac_3_tx_rst(qsfp1_mac_3_tx_rst_int), - - .qsfp1_mac_3_tx_ptp_clk(qsfp1_mac_3_tx_ptp_clk_int), - .qsfp1_mac_3_tx_ptp_rst(qsfp1_mac_3_tx_ptp_rst_int), - .qsfp1_mac_3_tx_ptp_time(qsfp1_mac_3_tx_ptp_time_int), - - .qsfp1_mac_3_tx_ptp_ts(qsfp1_mac_3_tx_ptp_ts_int), - .qsfp1_mac_3_tx_ptp_ts_tag(qsfp1_mac_3_tx_ptp_ts_tag_int), - .qsfp1_mac_3_tx_ptp_ts_valid(qsfp1_mac_3_tx_ptp_ts_valid_int), - - .qsfp1_mac_3_tx_axis_tdata(qsfp1_mac_3_tx_axis_tdata_int), - .qsfp1_mac_3_tx_axis_tkeep(qsfp1_mac_3_tx_axis_tkeep_int), - .qsfp1_mac_3_tx_axis_tvalid(qsfp1_mac_3_tx_axis_tvalid_int), - .qsfp1_mac_3_tx_axis_tready(qsfp1_mac_3_tx_axis_tready_int), - .qsfp1_mac_3_tx_axis_tlast(qsfp1_mac_3_tx_axis_tlast_int), - .qsfp1_mac_3_tx_axis_tuser(qsfp1_mac_3_tx_axis_tuser_int), - - .qsfp1_mac_3_tx_status(qsfp1_mac_3_tx_status_int), - .qsfp1_mac_3_tx_lfc_req(qsfp1_mac_3_tx_lfc_req_int), - .qsfp1_mac_3_tx_pfc_req(qsfp1_mac_3_tx_pfc_req_int), - - .qsfp1_mac_3_rx_clk(qsfp1_mac_3_rx_clk_int), - .qsfp1_mac_3_rx_rst(qsfp1_mac_3_rx_rst_int), - - .qsfp1_mac_3_rx_ptp_clk(qsfp1_mac_3_rx_ptp_clk_int), - .qsfp1_mac_3_rx_ptp_rst(qsfp1_mac_3_rx_ptp_rst_int), - .qsfp1_mac_3_rx_ptp_time(qsfp1_mac_3_rx_ptp_time_int), - - .qsfp1_mac_3_rx_axis_tdata(qsfp1_mac_3_rx_axis_tdata_int), - .qsfp1_mac_3_rx_axis_tkeep(qsfp1_mac_3_rx_axis_tkeep_int), - .qsfp1_mac_3_rx_axis_tvalid(qsfp1_mac_3_rx_axis_tvalid_int), - .qsfp1_mac_3_rx_axis_tlast(qsfp1_mac_3_rx_axis_tlast_int), - .qsfp1_mac_3_rx_axis_tuser(qsfp1_mac_3_rx_axis_tuser_int), - - .qsfp1_mac_3_rx_status(qsfp1_mac_3_rx_status_int), - .qsfp1_mac_3_rx_lfc_req(qsfp1_mac_3_rx_lfc_req_int), - .qsfp1_mac_3_rx_pfc_req(qsfp1_mac_3_rx_pfc_req_int), - - .qsfp1_mac_4_tx_clk(qsfp1_mac_4_tx_clk_int), - .qsfp1_mac_4_tx_rst(qsfp1_mac_4_tx_rst_int), - - .qsfp1_mac_4_tx_ptp_clk(qsfp1_mac_4_tx_ptp_clk_int), - .qsfp1_mac_4_tx_ptp_rst(qsfp1_mac_4_tx_ptp_rst_int), - .qsfp1_mac_4_tx_ptp_time(qsfp1_mac_4_tx_ptp_time_int), - - .qsfp1_mac_4_tx_ptp_ts(qsfp1_mac_4_tx_ptp_ts_int), - .qsfp1_mac_4_tx_ptp_ts_tag(qsfp1_mac_4_tx_ptp_ts_tag_int), - .qsfp1_mac_4_tx_ptp_ts_valid(qsfp1_mac_4_tx_ptp_ts_valid_int), - - .qsfp1_mac_4_tx_axis_tdata(qsfp1_mac_4_tx_axis_tdata_int), - .qsfp1_mac_4_tx_axis_tkeep(qsfp1_mac_4_tx_axis_tkeep_int), - .qsfp1_mac_4_tx_axis_tvalid(qsfp1_mac_4_tx_axis_tvalid_int), - .qsfp1_mac_4_tx_axis_tready(qsfp1_mac_4_tx_axis_tready_int), - .qsfp1_mac_4_tx_axis_tlast(qsfp1_mac_4_tx_axis_tlast_int), - .qsfp1_mac_4_tx_axis_tuser(qsfp1_mac_4_tx_axis_tuser_int), - - .qsfp1_mac_4_tx_status(qsfp1_mac_4_tx_status_int), - .qsfp1_mac_4_tx_lfc_req(qsfp1_mac_4_tx_lfc_req_int), - .qsfp1_mac_4_tx_pfc_req(qsfp1_mac_4_tx_pfc_req_int), - - .qsfp1_mac_4_rx_clk(qsfp1_mac_4_rx_clk_int), - .qsfp1_mac_4_rx_rst(qsfp1_mac_4_rx_rst_int), - - .qsfp1_mac_4_rx_ptp_clk(qsfp1_mac_4_rx_ptp_clk_int), - .qsfp1_mac_4_rx_ptp_rst(qsfp1_mac_4_rx_ptp_rst_int), - .qsfp1_mac_4_rx_ptp_time(qsfp1_mac_4_rx_ptp_time_int), - - .qsfp1_mac_4_rx_axis_tdata(qsfp1_mac_4_rx_axis_tdata_int), - .qsfp1_mac_4_rx_axis_tkeep(qsfp1_mac_4_rx_axis_tkeep_int), - .qsfp1_mac_4_rx_axis_tvalid(qsfp1_mac_4_rx_axis_tvalid_int), - .qsfp1_mac_4_rx_axis_tlast(qsfp1_mac_4_rx_axis_tlast_int), - .qsfp1_mac_4_rx_axis_tuser(qsfp1_mac_4_rx_axis_tuser_int), - - .qsfp1_mac_4_rx_status(qsfp1_mac_4_rx_status_int), - .qsfp1_mac_4_rx_lfc_req(qsfp1_mac_4_rx_lfc_req_int), - .qsfp1_mac_4_rx_pfc_req(qsfp1_mac_4_rx_pfc_req_int), - - .qsfp2_mac_1_tx_clk(qsfp2_mac_1_tx_clk_int), - .qsfp2_mac_1_tx_rst(qsfp2_mac_1_tx_rst_int), - - .qsfp2_mac_1_tx_ptp_clk(qsfp2_mac_1_tx_ptp_clk_int), - .qsfp2_mac_1_tx_ptp_rst(qsfp2_mac_1_tx_ptp_rst_int), - .qsfp2_mac_1_tx_ptp_time(qsfp2_mac_1_tx_ptp_time_int), - - .qsfp2_mac_1_tx_ptp_ts(qsfp2_mac_1_tx_ptp_ts_int), - .qsfp2_mac_1_tx_ptp_ts_tag(qsfp2_mac_1_tx_ptp_ts_tag_int), - .qsfp2_mac_1_tx_ptp_ts_valid(qsfp2_mac_1_tx_ptp_ts_valid_int), - - .qsfp2_mac_1_tx_axis_tdata(qsfp2_mac_1_tx_axis_tdata_int), - .qsfp2_mac_1_tx_axis_tkeep(qsfp2_mac_1_tx_axis_tkeep_int), - .qsfp2_mac_1_tx_axis_tvalid(qsfp2_mac_1_tx_axis_tvalid_int), - .qsfp2_mac_1_tx_axis_tready(qsfp2_mac_1_tx_axis_tready_int), - .qsfp2_mac_1_tx_axis_tlast(qsfp2_mac_1_tx_axis_tlast_int), - .qsfp2_mac_1_tx_axis_tuser(qsfp2_mac_1_tx_axis_tuser_int), - - .qsfp2_mac_1_tx_status(qsfp2_mac_1_tx_status_int), - .qsfp2_mac_1_tx_lfc_req(qsfp2_mac_1_tx_lfc_req_int), - .qsfp2_mac_1_tx_pfc_req(qsfp2_mac_1_tx_pfc_req_int), - - .qsfp2_mac_1_rx_clk(qsfp2_mac_1_rx_clk_int), - .qsfp2_mac_1_rx_rst(qsfp2_mac_1_rx_rst_int), - - .qsfp2_mac_1_rx_ptp_clk(qsfp2_mac_1_rx_ptp_clk_int), - .qsfp2_mac_1_rx_ptp_rst(qsfp2_mac_1_rx_ptp_rst_int), - .qsfp2_mac_1_rx_ptp_time(qsfp2_mac_1_rx_ptp_time_int), - - .qsfp2_mac_1_rx_axis_tdata(qsfp2_mac_1_rx_axis_tdata_int), - .qsfp2_mac_1_rx_axis_tkeep(qsfp2_mac_1_rx_axis_tkeep_int), - .qsfp2_mac_1_rx_axis_tvalid(qsfp2_mac_1_rx_axis_tvalid_int), - .qsfp2_mac_1_rx_axis_tlast(qsfp2_mac_1_rx_axis_tlast_int), - .qsfp2_mac_1_rx_axis_tuser(qsfp2_mac_1_rx_axis_tuser_int), - - .qsfp2_mac_1_rx_status(qsfp2_mac_1_rx_status_int), - .qsfp2_mac_1_rx_lfc_req(qsfp2_mac_1_rx_lfc_req_int), - .qsfp2_mac_1_rx_pfc_req(qsfp2_mac_1_rx_pfc_req_int), - - .qsfp2_mac_2_tx_clk(qsfp2_mac_2_tx_clk_int), - .qsfp2_mac_2_tx_rst(qsfp2_mac_2_tx_rst_int), - - .qsfp2_mac_2_tx_ptp_clk(qsfp2_mac_2_tx_ptp_clk_int), - .qsfp2_mac_2_tx_ptp_rst(qsfp2_mac_2_tx_ptp_rst_int), - .qsfp2_mac_2_tx_ptp_time(qsfp2_mac_2_tx_ptp_time_int), - - .qsfp2_mac_2_tx_ptp_ts(qsfp2_mac_2_tx_ptp_ts_int), - .qsfp2_mac_2_tx_ptp_ts_tag(qsfp2_mac_2_tx_ptp_ts_tag_int), - .qsfp2_mac_2_tx_ptp_ts_valid(qsfp2_mac_2_tx_ptp_ts_valid_int), - - .qsfp2_mac_2_tx_axis_tdata(qsfp2_mac_2_tx_axis_tdata_int), - .qsfp2_mac_2_tx_axis_tkeep(qsfp2_mac_2_tx_axis_tkeep_int), - .qsfp2_mac_2_tx_axis_tvalid(qsfp2_mac_2_tx_axis_tvalid_int), - .qsfp2_mac_2_tx_axis_tready(qsfp2_mac_2_tx_axis_tready_int), - .qsfp2_mac_2_tx_axis_tlast(qsfp2_mac_2_tx_axis_tlast_int), - .qsfp2_mac_2_tx_axis_tuser(qsfp2_mac_2_tx_axis_tuser_int), - - .qsfp2_mac_2_tx_status(qsfp2_mac_2_tx_status_int), - .qsfp2_mac_2_tx_lfc_req(qsfp2_mac_2_tx_lfc_req_int), - .qsfp2_mac_2_tx_pfc_req(qsfp2_mac_2_tx_pfc_req_int), - - .qsfp2_mac_2_rx_clk(qsfp2_mac_2_rx_clk_int), - .qsfp2_mac_2_rx_rst(qsfp2_mac_2_rx_rst_int), - - .qsfp2_mac_2_rx_ptp_clk(qsfp2_mac_2_rx_ptp_clk_int), - .qsfp2_mac_2_rx_ptp_rst(qsfp2_mac_2_rx_ptp_rst_int), - .qsfp2_mac_2_rx_ptp_time(qsfp2_mac_2_rx_ptp_time_int), - - .qsfp2_mac_2_rx_axis_tdata(qsfp2_mac_2_rx_axis_tdata_int), - .qsfp2_mac_2_rx_axis_tkeep(qsfp2_mac_2_rx_axis_tkeep_int), - .qsfp2_mac_2_rx_axis_tvalid(qsfp2_mac_2_rx_axis_tvalid_int), - .qsfp2_mac_2_rx_axis_tlast(qsfp2_mac_2_rx_axis_tlast_int), - .qsfp2_mac_2_rx_axis_tuser(qsfp2_mac_2_rx_axis_tuser_int), - - .qsfp2_mac_2_rx_status(qsfp2_mac_2_rx_status_int), - .qsfp2_mac_2_rx_lfc_req(qsfp2_mac_2_rx_lfc_req_int), - .qsfp2_mac_2_rx_pfc_req(qsfp2_mac_2_rx_pfc_req_int), - - .qsfp2_mac_3_tx_clk(qsfp2_mac_3_tx_clk_int), - .qsfp2_mac_3_tx_rst(qsfp2_mac_3_tx_rst_int), - - .qsfp2_mac_3_tx_ptp_clk(qsfp2_mac_3_tx_ptp_clk_int), - .qsfp2_mac_3_tx_ptp_rst(qsfp2_mac_3_tx_ptp_rst_int), - .qsfp2_mac_3_tx_ptp_time(qsfp2_mac_3_tx_ptp_time_int), - - .qsfp2_mac_3_tx_ptp_ts(qsfp2_mac_3_tx_ptp_ts_int), - .qsfp2_mac_3_tx_ptp_ts_tag(qsfp2_mac_3_tx_ptp_ts_tag_int), - .qsfp2_mac_3_tx_ptp_ts_valid(qsfp2_mac_3_tx_ptp_ts_valid_int), - - .qsfp2_mac_3_tx_axis_tdata(qsfp2_mac_3_tx_axis_tdata_int), - .qsfp2_mac_3_tx_axis_tkeep(qsfp2_mac_3_tx_axis_tkeep_int), - .qsfp2_mac_3_tx_axis_tvalid(qsfp2_mac_3_tx_axis_tvalid_int), - .qsfp2_mac_3_tx_axis_tready(qsfp2_mac_3_tx_axis_tready_int), - .qsfp2_mac_3_tx_axis_tlast(qsfp2_mac_3_tx_axis_tlast_int), - .qsfp2_mac_3_tx_axis_tuser(qsfp2_mac_3_tx_axis_tuser_int), - - .qsfp2_mac_3_tx_status(qsfp2_mac_3_tx_status_int), - .qsfp2_mac_3_tx_lfc_req(qsfp2_mac_3_tx_lfc_req_int), - .qsfp2_mac_3_tx_pfc_req(qsfp2_mac_3_tx_pfc_req_int), - - .qsfp2_mac_3_rx_clk(qsfp2_mac_3_rx_clk_int), - .qsfp2_mac_3_rx_rst(qsfp2_mac_3_rx_rst_int), - - .qsfp2_mac_3_rx_ptp_clk(qsfp2_mac_3_rx_ptp_clk_int), - .qsfp2_mac_3_rx_ptp_rst(qsfp2_mac_3_rx_ptp_rst_int), - .qsfp2_mac_3_rx_ptp_time(qsfp2_mac_3_rx_ptp_time_int), - - .qsfp2_mac_3_rx_axis_tdata(qsfp2_mac_3_rx_axis_tdata_int), - .qsfp2_mac_3_rx_axis_tkeep(qsfp2_mac_3_rx_axis_tkeep_int), - .qsfp2_mac_3_rx_axis_tvalid(qsfp2_mac_3_rx_axis_tvalid_int), - .qsfp2_mac_3_rx_axis_tlast(qsfp2_mac_3_rx_axis_tlast_int), - .qsfp2_mac_3_rx_axis_tuser(qsfp2_mac_3_rx_axis_tuser_int), - - .qsfp2_mac_3_rx_status(qsfp2_mac_3_rx_status_int), - .qsfp2_mac_3_rx_lfc_req(qsfp2_mac_3_rx_lfc_req_int), - .qsfp2_mac_3_rx_pfc_req(qsfp2_mac_3_rx_pfc_req_int), - - .qsfp2_mac_4_tx_clk(qsfp2_mac_4_tx_clk_int), - .qsfp2_mac_4_tx_rst(qsfp2_mac_4_tx_rst_int), - - .qsfp2_mac_4_tx_ptp_clk(qsfp2_mac_4_tx_ptp_clk_int), - .qsfp2_mac_4_tx_ptp_rst(qsfp2_mac_4_tx_ptp_rst_int), - .qsfp2_mac_4_tx_ptp_time(qsfp2_mac_4_tx_ptp_time_int), - - .qsfp2_mac_4_tx_ptp_ts(qsfp2_mac_4_tx_ptp_ts_int), - .qsfp2_mac_4_tx_ptp_ts_tag(qsfp2_mac_4_tx_ptp_ts_tag_int), - .qsfp2_mac_4_tx_ptp_ts_valid(qsfp2_mac_4_tx_ptp_ts_valid_int), - - .qsfp2_mac_4_tx_axis_tdata(qsfp2_mac_4_tx_axis_tdata_int), - .qsfp2_mac_4_tx_axis_tkeep(qsfp2_mac_4_tx_axis_tkeep_int), - .qsfp2_mac_4_tx_axis_tvalid(qsfp2_mac_4_tx_axis_tvalid_int), - .qsfp2_mac_4_tx_axis_tready(qsfp2_mac_4_tx_axis_tready_int), - .qsfp2_mac_4_tx_axis_tlast(qsfp2_mac_4_tx_axis_tlast_int), - .qsfp2_mac_4_tx_axis_tuser(qsfp2_mac_4_tx_axis_tuser_int), - - .qsfp2_mac_4_tx_status(qsfp2_mac_4_tx_status_int), - .qsfp2_mac_4_tx_lfc_req(qsfp2_mac_4_tx_lfc_req_int), - .qsfp2_mac_4_tx_pfc_req(qsfp2_mac_4_tx_pfc_req_int), - - .qsfp2_mac_4_rx_clk(qsfp2_mac_4_rx_clk_int), - .qsfp2_mac_4_rx_rst(qsfp2_mac_4_rx_rst_int), - - .qsfp2_mac_4_rx_ptp_clk(qsfp2_mac_4_rx_ptp_clk_int), - .qsfp2_mac_4_rx_ptp_rst(qsfp2_mac_4_rx_ptp_rst_int), - .qsfp2_mac_4_rx_ptp_time(qsfp2_mac_4_rx_ptp_time_int), - - .qsfp2_mac_4_rx_axis_tdata(qsfp2_mac_4_rx_axis_tdata_int), - .qsfp2_mac_4_rx_axis_tkeep(qsfp2_mac_4_rx_axis_tkeep_int), - .qsfp2_mac_4_rx_axis_tvalid(qsfp2_mac_4_rx_axis_tvalid_int), - .qsfp2_mac_4_rx_axis_tlast(qsfp2_mac_4_rx_axis_tlast_int), - .qsfp2_mac_4_rx_axis_tuser(qsfp2_mac_4_rx_axis_tuser_int), - - .qsfp2_mac_4_rx_status(qsfp2_mac_4_rx_status_int), - .qsfp2_mac_4_rx_lfc_req(qsfp2_mac_4_rx_lfc_req_int), - .qsfp2_mac_4_rx_pfc_req(qsfp2_mac_4_rx_pfc_req_int) -); - -endmodule - -`resetall diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v deleted file mode 100644 index 57dca4033..000000000 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/fpga_core.v +++ /dev/null @@ -1,1288 +0,0 @@ -// SPDX-License-Identifier: BSD-2-Clause-Views -/* - * Copyright (c) 2021-2023 The Regents of the University of California - */ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA core logic - */ -module fpga_core # -( - // FW and board IDs - parameter FPGA_ID = 32'hC32450DD, - parameter FW_ID = 32'h00000000, - parameter FW_VER = 32'h00_00_01_00, - parameter BOARD_ID = 32'h1172_A00D, - parameter BOARD_VER = 32'h01_00_00_00, - parameter BUILD_DATE = 32'd1563227611, - parameter GIT_HASH = 32'hdce357bf, - parameter RELEASE_INFO = 32'h00000000, - - // Structural configuration - parameter IF_COUNT = 2, - parameter PORTS_PER_IF = 1, - parameter SCHED_PER_IF = PORTS_PER_IF, - parameter PORT_MASK = 0, - - // Clock configuration - parameter CLK_PERIOD_NS_NUM = 4, - parameter CLK_PERIOD_NS_DENOM = 1, - - // PTP configuration - parameter PTP_CLK_PERIOD_NS_NUM = 4096, - parameter PTP_CLK_PERIOD_NS_DENOM = 825, - parameter PTP_TS_WIDTH = 96, - parameter PTP_CLOCK_PIPELINE = 0, - parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_SEPARATE_TX_CLOCK = 1, - parameter PTP_SEPARATE_RX_CLOCK = 1, - parameter PTP_PORT_CDC_PIPELINE = 0, - parameter PTP_PEROUT_ENABLE = 1, - parameter PTP_PEROUT_COUNT = 1, - - // Queue manager configuration - parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_QUEUE_OP_TABLE_SIZE = 32, - parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter CQ_OP_TABLE_SIZE = 32, - parameter EQN_WIDTH = 5, - parameter TX_QUEUE_INDEX_WIDTH = 13, - parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, - parameter EQ_PIPELINE = 3, - parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), - parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), - - // TX and RX engine configuration - parameter TX_DESC_TABLE_SIZE = 32, - parameter RX_DESC_TABLE_SIZE = 32, - parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, - - // Scheduler configuration - parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, - parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, - parameter TDMA_INDEX_WIDTH = 6, - - // Interface configuration - parameter PTP_TS_ENABLE = 1, - parameter TX_CPL_FIFO_DEPTH = 32, - parameter TX_TAG_WIDTH = 16, - parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_HASH_ENABLE = 1, - parameter RX_CHECKSUM_ENABLE = 1, - parameter PFC_ENABLE = 1, - parameter LFC_ENABLE = PFC_ENABLE, - parameter TX_FIFO_DEPTH = 32768, - parameter RX_FIFO_DEPTH = 32768, - parameter MAX_TX_SIZE = 9214, - parameter MAX_RX_SIZE = 9214, - parameter TX_RAM_SIZE = 32768, - parameter RX_RAM_SIZE = 32768, - - // Application block configuration - parameter APP_ID = 32'h00000000, - parameter APP_ENABLE = 0, - parameter APP_CTRL_ENABLE = 1, - parameter APP_DMA_ENABLE = 1, - parameter APP_AXIS_DIRECT_ENABLE = 1, - parameter APP_AXIS_SYNC_ENABLE = 1, - parameter APP_AXIS_IF_ENABLE = 1, - parameter APP_STAT_ENABLE = 1, - - // DMA interface configuration - parameter DMA_IMM_ENABLE = 0, - parameter DMA_IMM_WIDTH = 32, - parameter DMA_LEN_WIDTH = 16, - parameter DMA_TAG_WIDTH = 16, - parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), - parameter RAM_PIPELINE = 2, - - // PCIe interface configuration - parameter SEG_COUNT = 2, - parameter SEG_DATA_WIDTH = 256, - parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32), - parameter SEG_HDR_WIDTH = 128, - parameter SEG_PRFX_WIDTH = 32, - parameter TX_SEQ_NUM_WIDTH = 6, - parameter PF_COUNT = 1, - parameter VF_COUNT = 0, - parameter PCIE_TAG_COUNT = 256, - - // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EQN_WIDTH, - - // AXI lite interface configuration (control) - parameter AXIL_CTRL_DATA_WIDTH = 32, - parameter AXIL_CTRL_ADDR_WIDTH = 24, - - // AXI lite interface configuration (application control) - parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, - parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, - - // Ethernet interface configuration - parameter AXIS_ETH_DATA_WIDTH = 64, - parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, - parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*2, - parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1, - parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, - parameter AXIS_ETH_TX_PIPELINE = 0, - parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, - parameter AXIS_ETH_TX_TS_PIPELINE = 0, - parameter AXIS_ETH_RX_PIPELINE = 0, - parameter AXIS_ETH_RX_FIFO_PIPELINE = 2, - - // Statistics counter subsystem - parameter STAT_ENABLE = 1, - parameter STAT_DMA_ENABLE = 1, - parameter STAT_PCIE_ENABLE = 1, - parameter STAT_INC_WIDTH = 24, - parameter STAT_ID_WIDTH = 12 -) -( - /* - * Clock: 250 MHz - * Synchronous reset - */ - input wire clk_250mhz, - input wire rst_250mhz, - - /* - * PTP clock - */ - input wire ptp_clk, - input wire ptp_rst, - input wire ptp_sample_clk, - - /* - * GPIO - */ - input wire user_pb, - output wire [3:0] user_led_g, - - /* - * I2C - */ - input wire i2c2_scl_i, - output wire i2c2_scl_o, - output wire i2c2_scl_t, - input wire i2c2_sda_i, - output wire i2c2_sda_o, - output wire i2c2_sda_t, - output wire bmc_i2c2_disable, - - /* - * P-Tile interface - */ - input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data, - input wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty, - input wire [SEG_COUNT-1:0] rx_st_sop, - input wire [SEG_COUNT-1:0] rx_st_eop, - input wire [SEG_COUNT-1:0] rx_st_valid, - output wire rx_st_ready, - input wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] rx_st_hdr, - input wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] rx_st_tlp_prfx, - input wire [SEG_COUNT-1:0] rx_st_vf_active, - input wire [SEG_COUNT*3-1:0] rx_st_func_num, - input wire [SEG_COUNT*11-1:0] rx_st_vf_num, - input wire [SEG_COUNT*3-1:0] rx_st_bar_range, - input wire [SEG_COUNT-1:0] rx_st_tlp_abort, - - output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data, - output wire [SEG_COUNT-1:0] tx_st_sop, - output wire [SEG_COUNT-1:0] tx_st_eop, - output wire [SEG_COUNT-1:0] tx_st_valid, - input wire tx_st_ready, - output wire [SEG_COUNT-1:0] tx_st_err, - output wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] tx_st_hdr, - output wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] tx_st_tlp_prfx, - - output wire [11:0] rx_buffer_limit, - output wire [1:0] rx_buffer_limit_tdm_idx, - - input wire [15:0] tx_cdts_limit, - input wire [2:0] tx_cdts_limit_tdm_idx, - - input wire [15:0] tl_cfg_ctl, - input wire [4:0] tl_cfg_add, - input wire [2:0] tl_cfg_func, - - /* - * Ethernet: QSFP28 - */ - input wire qsfp1_mac_1_tx_clk, - input wire qsfp1_mac_1_tx_rst, - - input wire qsfp1_mac_1_tx_ptp_clk, - input wire qsfp1_mac_1_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfp1_mac_1_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfp1_mac_1_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfp1_mac_1_tx_ptp_ts_tag, - input wire qsfp1_mac_1_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_1_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_1_tx_axis_tkeep, - output wire qsfp1_mac_1_tx_axis_tvalid, - input wire qsfp1_mac_1_tx_axis_tready, - output wire qsfp1_mac_1_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp1_mac_1_tx_axis_tuser, - - input wire qsfp1_mac_1_tx_status, - output wire qsfp1_mac_1_tx_lfc_req, - output wire [7:0] qsfp1_mac_1_tx_pfc_req, - - input wire qsfp1_mac_1_rx_clk, - input wire qsfp1_mac_1_rx_rst, - - input wire qsfp1_mac_1_rx_ptp_clk, - input wire qsfp1_mac_1_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfp1_mac_1_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_1_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_1_rx_axis_tkeep, - input wire qsfp1_mac_1_rx_axis_tvalid, - input wire qsfp1_mac_1_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp1_mac_1_rx_axis_tuser, - - input wire qsfp1_mac_1_rx_status, - input wire qsfp1_mac_1_rx_lfc_req, - input wire [7:0] qsfp1_mac_1_rx_pfc_req, - - input wire qsfp1_mac_2_tx_clk, - input wire qsfp1_mac_2_tx_rst, - - input wire qsfp1_mac_2_tx_ptp_clk, - input wire qsfp1_mac_2_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfp1_mac_2_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfp1_mac_2_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfp1_mac_2_tx_ptp_ts_tag, - input wire qsfp1_mac_2_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_2_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_2_tx_axis_tkeep, - output wire qsfp1_mac_2_tx_axis_tvalid, - input wire qsfp1_mac_2_tx_axis_tready, - output wire qsfp1_mac_2_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp1_mac_2_tx_axis_tuser, - - input wire qsfp1_mac_2_tx_status, - output wire qsfp1_mac_2_tx_lfc_req, - output wire [7:0] qsfp1_mac_2_tx_pfc_req, - - input wire qsfp1_mac_2_rx_clk, - input wire qsfp1_mac_2_rx_rst, - - input wire qsfp1_mac_2_rx_ptp_clk, - input wire qsfp1_mac_2_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfp1_mac_2_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_2_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_2_rx_axis_tkeep, - input wire qsfp1_mac_2_rx_axis_tvalid, - input wire qsfp1_mac_2_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp1_mac_2_rx_axis_tuser, - - input wire qsfp1_mac_2_rx_status, - input wire qsfp1_mac_2_rx_lfc_req, - input wire [7:0] qsfp1_mac_2_rx_pfc_req, - - input wire qsfp1_mac_3_tx_clk, - input wire qsfp1_mac_3_tx_rst, - - input wire qsfp1_mac_3_tx_ptp_clk, - input wire qsfp1_mac_3_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfp1_mac_3_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfp1_mac_3_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfp1_mac_3_tx_ptp_ts_tag, - input wire qsfp1_mac_3_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_3_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_3_tx_axis_tkeep, - output wire qsfp1_mac_3_tx_axis_tvalid, - input wire qsfp1_mac_3_tx_axis_tready, - output wire qsfp1_mac_3_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp1_mac_3_tx_axis_tuser, - - input wire qsfp1_mac_3_tx_status, - output wire qsfp1_mac_3_tx_lfc_req, - output wire [7:0] qsfp1_mac_3_tx_pfc_req, - - input wire qsfp1_mac_3_rx_clk, - input wire qsfp1_mac_3_rx_rst, - - input wire qsfp1_mac_3_rx_ptp_clk, - input wire qsfp1_mac_3_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfp1_mac_3_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_3_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_3_rx_axis_tkeep, - input wire qsfp1_mac_3_rx_axis_tvalid, - input wire qsfp1_mac_3_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp1_mac_3_rx_axis_tuser, - - input wire qsfp1_mac_3_rx_status, - input wire qsfp1_mac_3_rx_lfc_req, - input wire [7:0] qsfp1_mac_3_rx_pfc_req, - - input wire qsfp1_mac_4_tx_clk, - input wire qsfp1_mac_4_tx_rst, - - input wire qsfp1_mac_4_tx_ptp_clk, - input wire qsfp1_mac_4_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfp1_mac_4_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfp1_mac_4_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfp1_mac_4_tx_ptp_ts_tag, - input wire qsfp1_mac_4_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_4_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_4_tx_axis_tkeep, - output wire qsfp1_mac_4_tx_axis_tvalid, - input wire qsfp1_mac_4_tx_axis_tready, - output wire qsfp1_mac_4_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp1_mac_4_tx_axis_tuser, - - input wire qsfp1_mac_4_tx_status, - output wire qsfp1_mac_4_tx_lfc_req, - output wire [7:0] qsfp1_mac_4_tx_pfc_req, - - input wire qsfp1_mac_4_rx_clk, - input wire qsfp1_mac_4_rx_rst, - - input wire qsfp1_mac_4_rx_ptp_clk, - input wire qsfp1_mac_4_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfp1_mac_4_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_4_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_4_rx_axis_tkeep, - input wire qsfp1_mac_4_rx_axis_tvalid, - input wire qsfp1_mac_4_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp1_mac_4_rx_axis_tuser, - - input wire qsfp1_mac_4_rx_status, - input wire qsfp1_mac_4_rx_lfc_req, - input wire [7:0] qsfp1_mac_4_rx_pfc_req, - - input wire qsfp2_mac_1_tx_clk, - input wire qsfp2_mac_1_tx_rst, - - input wire qsfp2_mac_1_tx_ptp_clk, - input wire qsfp2_mac_1_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfp2_mac_1_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfp2_mac_1_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfp2_mac_1_tx_ptp_ts_tag, - input wire qsfp2_mac_1_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_1_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_1_tx_axis_tkeep, - output wire qsfp2_mac_1_tx_axis_tvalid, - input wire qsfp2_mac_1_tx_axis_tready, - output wire qsfp2_mac_1_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp2_mac_1_tx_axis_tuser, - - input wire qsfp2_mac_1_tx_status, - output wire qsfp2_mac_1_tx_lfc_req, - output wire [7:0] qsfp2_mac_1_tx_pfc_req, - - input wire qsfp2_mac_1_rx_clk, - input wire qsfp2_mac_1_rx_rst, - - input wire qsfp2_mac_1_rx_ptp_clk, - input wire qsfp2_mac_1_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfp2_mac_1_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_1_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_1_rx_axis_tkeep, - input wire qsfp2_mac_1_rx_axis_tvalid, - input wire qsfp2_mac_1_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp2_mac_1_rx_axis_tuser, - - input wire qsfp2_mac_1_rx_status, - input wire qsfp2_mac_1_rx_lfc_req, - input wire [7:0] qsfp2_mac_1_rx_pfc_req, - - input wire qsfp2_mac_2_tx_clk, - input wire qsfp2_mac_2_tx_rst, - - input wire qsfp2_mac_2_tx_ptp_clk, - input wire qsfp2_mac_2_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfp2_mac_2_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfp2_mac_2_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfp2_mac_2_tx_ptp_ts_tag, - input wire qsfp2_mac_2_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_2_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_2_tx_axis_tkeep, - output wire qsfp2_mac_2_tx_axis_tvalid, - input wire qsfp2_mac_2_tx_axis_tready, - output wire qsfp2_mac_2_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp2_mac_2_tx_axis_tuser, - - input wire qsfp2_mac_2_tx_status, - output wire qsfp2_mac_2_tx_lfc_req, - output wire [7:0] qsfp2_mac_2_tx_pfc_req, - - input wire qsfp2_mac_2_rx_clk, - input wire qsfp2_mac_2_rx_rst, - - input wire qsfp2_mac_2_rx_ptp_clk, - input wire qsfp2_mac_2_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfp2_mac_2_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_2_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_2_rx_axis_tkeep, - input wire qsfp2_mac_2_rx_axis_tvalid, - input wire qsfp2_mac_2_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp2_mac_2_rx_axis_tuser, - - input wire qsfp2_mac_2_rx_status, - input wire qsfp2_mac_2_rx_lfc_req, - input wire [7:0] qsfp2_mac_2_rx_pfc_req, - - input wire qsfp2_mac_3_tx_clk, - input wire qsfp2_mac_3_tx_rst, - - input wire qsfp2_mac_3_tx_ptp_clk, - input wire qsfp2_mac_3_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfp2_mac_3_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfp2_mac_3_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfp2_mac_3_tx_ptp_ts_tag, - input wire qsfp2_mac_3_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_3_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_3_tx_axis_tkeep, - output wire qsfp2_mac_3_tx_axis_tvalid, - input wire qsfp2_mac_3_tx_axis_tready, - output wire qsfp2_mac_3_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp2_mac_3_tx_axis_tuser, - - input wire qsfp2_mac_3_tx_status, - output wire qsfp2_mac_3_tx_lfc_req, - output wire [7:0] qsfp2_mac_3_tx_pfc_req, - - input wire qsfp2_mac_3_rx_clk, - input wire qsfp2_mac_3_rx_rst, - - input wire qsfp2_mac_3_rx_ptp_clk, - input wire qsfp2_mac_3_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfp2_mac_3_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_3_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_3_rx_axis_tkeep, - input wire qsfp2_mac_3_rx_axis_tvalid, - input wire qsfp2_mac_3_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp2_mac_3_rx_axis_tuser, - - input wire qsfp2_mac_3_rx_status, - input wire qsfp2_mac_3_rx_lfc_req, - input wire [7:0] qsfp2_mac_3_rx_pfc_req, - - input wire qsfp2_mac_4_tx_clk, - input wire qsfp2_mac_4_tx_rst, - - input wire qsfp2_mac_4_tx_ptp_clk, - input wire qsfp2_mac_4_tx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfp2_mac_4_tx_ptp_time, - - input wire [PTP_TS_WIDTH-1:0] qsfp2_mac_4_tx_ptp_ts, - input wire [TX_TAG_WIDTH-1:0] qsfp2_mac_4_tx_ptp_ts_tag, - input wire qsfp2_mac_4_tx_ptp_ts_valid, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_4_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_4_tx_axis_tkeep, - output wire qsfp2_mac_4_tx_axis_tvalid, - input wire qsfp2_mac_4_tx_axis_tready, - output wire qsfp2_mac_4_tx_axis_tlast, - output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp2_mac_4_tx_axis_tuser, - - input wire qsfp2_mac_4_tx_status, - output wire qsfp2_mac_4_tx_lfc_req, - output wire [7:0] qsfp2_mac_4_tx_pfc_req, - - input wire qsfp2_mac_4_rx_clk, - input wire qsfp2_mac_4_rx_rst, - - input wire qsfp2_mac_4_rx_ptp_clk, - input wire qsfp2_mac_4_rx_ptp_rst, - output wire [PTP_TS_WIDTH-1:0] qsfp2_mac_4_rx_ptp_time, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_4_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_4_rx_axis_tkeep, - input wire qsfp2_mac_4_rx_axis_tvalid, - input wire qsfp2_mac_4_rx_axis_tlast, - input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp2_mac_4_rx_axis_tuser, - - input wire qsfp2_mac_4_rx_status, - input wire qsfp2_mac_4_rx_lfc_req, - input wire [7:0] qsfp2_mac_4_rx_pfc_req -); - -parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; - -parameter F_COUNT = PF_COUNT+VF_COUNT; - -parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8); -parameter AXIL_IF_CTRL_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT); -parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8); - -localparam RB_BASE_ADDR = 16'h1000; -localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; - -initial begin - if (PORT_COUNT > 8) begin - $error("Error: Max port count exceeded (instance %m)"); - $finish; - end -end - -// AXI lite connections -wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_awaddr; -wire [2:0] axil_csr_awprot; -wire axil_csr_awvalid; -wire axil_csr_awready; -wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_wdata; -wire [AXIL_CTRL_STRB_WIDTH-1:0] axil_csr_wstrb; -wire axil_csr_wvalid; -wire axil_csr_wready; -wire [1:0] axil_csr_bresp; -wire axil_csr_bvalid; -wire axil_csr_bready; -wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_araddr; -wire [2:0] axil_csr_arprot; -wire axil_csr_arvalid; -wire axil_csr_arready; -wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_rdata; -wire [1:0] axil_csr_rresp; -wire axil_csr_rvalid; -wire axil_csr_rready; - -// PTP -wire ptp_td_sd; -wire ptp_pps; -wire ptp_pps_str; -wire ptp_sync_locked; -wire [63:0] ptp_sync_ts_rel; -wire ptp_sync_ts_rel_step; -wire [95:0] ptp_sync_ts_tod; -wire ptp_sync_ts_tod_step; -wire ptp_sync_pps; -wire ptp_sync_pps_str; - -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse; - -// control registers -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_wr_addr; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_wr_data; -wire [AXIL_CTRL_STRB_WIDTH-1:0] ctrl_reg_wr_strb; -wire ctrl_reg_wr_en; -wire ctrl_reg_wr_wait; -wire ctrl_reg_wr_ack; -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_rd_addr; -wire ctrl_reg_rd_en; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data; -wire ctrl_reg_rd_wait; -wire ctrl_reg_rd_ack; - -reg ctrl_reg_wr_ack_reg = 1'b0; -reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; -reg ctrl_reg_rd_ack_reg = 1'b0; - -reg i2c2_scl_o_reg = 1'b1; -reg i2c2_sda_o_reg = 1'b1; - -assign ctrl_reg_wr_wait = 1'b0; -assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg; -assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg; -assign ctrl_reg_rd_wait = 1'b0; -assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg; - -assign i2c2_scl_o = i2c2_scl_o_reg; -assign i2c2_scl_t = i2c2_scl_o_reg; -assign i2c2_sda_o = i2c2_sda_o_reg; -assign i2c2_sda_t = i2c2_sda_o_reg; -assign bmc_i2c2_disable = 1'b1; - -always @(posedge clk_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; - ctrl_reg_rd_ack_reg <= 1'b0; - - if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin - // write operation - ctrl_reg_wr_ack_reg <= 1'b0; - case ({ctrl_reg_wr_addr >> 2, 2'b00}) - // I2C 0 - RBB+8'h0C: begin - // I2C ctrl: control - if (ctrl_reg_wr_strb[0]) begin - i2c2_scl_o_reg <= ctrl_reg_wr_data[1]; - end - if (ctrl_reg_wr_strb[1]) begin - i2c2_sda_o_reg <= ctrl_reg_wr_data[9]; - end - end - default: ctrl_reg_wr_ack_reg <= 1'b0; - endcase - end - - if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin - // read operation - ctrl_reg_rd_ack_reg <= 1'b1; - case ({ctrl_reg_rd_addr >> 2, 2'b00}) - // I2C 0 - RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type - RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version - RBB+8'h08: ctrl_reg_rd_data_reg <= 0; // I2C ctrl: Next header - RBB+8'h0C: begin - // I2C ctrl: control - ctrl_reg_rd_data_reg[0] <= i2c2_scl_i; - ctrl_reg_rd_data_reg[1] <= i2c2_scl_o_reg; - ctrl_reg_rd_data_reg[8] <= i2c2_sda_i; - ctrl_reg_rd_data_reg[9] <= i2c2_sda_o_reg; - end - default: ctrl_reg_rd_ack_reg <= 1'b0; - endcase - end - - if (rst_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_ack_reg <= 1'b0; - - i2c2_scl_o_reg <= 1'b1; - i2c2_sda_o_reg <= 1'b1; - end -end - -assign user_led_g[0] = 1'b0; -assign user_led_g[1] = 1'b0; -assign user_led_g[2] = 1'b0; -assign user_led_g[3] = ptp_pps_str; - -wire [PORT_COUNT-1:0] eth_tx_clk; -wire [PORT_COUNT-1:0] eth_tx_rst; - -wire [PORT_COUNT-1:0] eth_tx_ptp_clk; -wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_tod; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_tod_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_tx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_tx_tready; -wire [PORT_COUNT-1:0] axis_eth_tx_tlast; -wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts; -wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; - -wire [PORT_COUNT-1:0] eth_tx_enable; -wire [PORT_COUNT-1:0] eth_tx_status; -wire [PORT_COUNT-1:0] eth_tx_lfc_en; -wire [PORT_COUNT-1:0] eth_tx_lfc_req; -wire [PORT_COUNT*8-1:0] eth_tx_pfc_en; -wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; - -wire [PORT_COUNT-1:0] eth_rx_clk; -wire [PORT_COUNT-1:0] eth_rx_rst; - -wire [PORT_COUNT-1:0] eth_rx_ptp_clk; -wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_tod; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_tod_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_rx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_rx_tready; -wire [PORT_COUNT-1:0] axis_eth_rx_tlast; -wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; - -wire [PORT_COUNT-1:0] eth_rx_enable; -wire [PORT_COUNT-1:0] eth_rx_status; -wire [PORT_COUNT-1:0] eth_rx_lfc_en; -wire [PORT_COUNT-1:0] eth_rx_lfc_req; -wire [PORT_COUNT-1:0] eth_rx_lfc_ack; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_en; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_req; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack; - -mqnic_port_map_mac_axis #( - .MAC_COUNT(8), - .PORT_MASK(PORT_MASK), - .PORT_GROUP_SIZE(4), - - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - - .PORT_COUNT(PORT_COUNT), - - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_TAG_WIDTH(TX_TAG_WIDTH), - .AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) -) -mqnic_port_map_mac_axis_inst ( - // towards MAC - .mac_tx_clk({qsfp2_mac_4_tx_clk, qsfp2_mac_3_tx_clk, qsfp2_mac_2_tx_clk, qsfp2_mac_1_tx_clk, qsfp1_mac_4_tx_clk, qsfp1_mac_3_tx_clk, qsfp1_mac_2_tx_clk, qsfp1_mac_1_tx_clk}), - .mac_tx_rst({qsfp2_mac_4_tx_rst, qsfp2_mac_3_tx_rst, qsfp2_mac_2_tx_rst, qsfp2_mac_1_tx_rst, qsfp1_mac_4_tx_rst, qsfp1_mac_3_tx_rst, qsfp1_mac_2_tx_rst, qsfp1_mac_1_tx_rst}), - - .mac_tx_ptp_clk({qsfp2_mac_4_tx_ptp_clk, qsfp2_mac_3_tx_ptp_clk, qsfp2_mac_2_tx_ptp_clk, qsfp2_mac_1_tx_ptp_clk, qsfp1_mac_4_tx_ptp_clk, qsfp1_mac_3_tx_ptp_clk, qsfp1_mac_2_tx_ptp_clk, qsfp1_mac_1_tx_ptp_clk}), - .mac_tx_ptp_rst({qsfp2_mac_4_tx_ptp_rst, qsfp2_mac_3_tx_ptp_rst, qsfp2_mac_2_tx_ptp_rst, qsfp2_mac_1_tx_ptp_rst, qsfp1_mac_4_tx_ptp_rst, qsfp1_mac_3_tx_ptp_rst, qsfp1_mac_2_tx_ptp_rst, qsfp1_mac_1_tx_ptp_rst}), - .mac_tx_ptp_ts_96({qsfp2_mac_4_tx_ptp_time, qsfp2_mac_3_tx_ptp_time, qsfp2_mac_2_tx_ptp_time, qsfp2_mac_1_tx_ptp_time, qsfp1_mac_4_tx_ptp_time, qsfp1_mac_3_tx_ptp_time, qsfp1_mac_2_tx_ptp_time, qsfp1_mac_1_tx_ptp_time}), - .mac_tx_ptp_ts_step(), - - .m_axis_mac_tx_tdata({qsfp2_mac_4_tx_axis_tdata, qsfp2_mac_3_tx_axis_tdata, qsfp2_mac_2_tx_axis_tdata, qsfp2_mac_1_tx_axis_tdata, qsfp1_mac_4_tx_axis_tdata, qsfp1_mac_3_tx_axis_tdata, qsfp1_mac_2_tx_axis_tdata, qsfp1_mac_1_tx_axis_tdata}), - .m_axis_mac_tx_tkeep({qsfp2_mac_4_tx_axis_tkeep, qsfp2_mac_3_tx_axis_tkeep, qsfp2_mac_2_tx_axis_tkeep, qsfp2_mac_1_tx_axis_tkeep, qsfp1_mac_4_tx_axis_tkeep, qsfp1_mac_3_tx_axis_tkeep, qsfp1_mac_2_tx_axis_tkeep, qsfp1_mac_1_tx_axis_tkeep}), - .m_axis_mac_tx_tvalid({qsfp2_mac_4_tx_axis_tvalid, qsfp2_mac_3_tx_axis_tvalid, qsfp2_mac_2_tx_axis_tvalid, qsfp2_mac_1_tx_axis_tvalid, qsfp1_mac_4_tx_axis_tvalid, qsfp1_mac_3_tx_axis_tvalid, qsfp1_mac_2_tx_axis_tvalid, qsfp1_mac_1_tx_axis_tvalid}), - .m_axis_mac_tx_tready({qsfp2_mac_4_tx_axis_tready, qsfp2_mac_3_tx_axis_tready, qsfp2_mac_2_tx_axis_tready, qsfp2_mac_1_tx_axis_tready, qsfp1_mac_4_tx_axis_tready, qsfp1_mac_3_tx_axis_tready, qsfp1_mac_2_tx_axis_tready, qsfp1_mac_1_tx_axis_tready}), - .m_axis_mac_tx_tlast({qsfp2_mac_4_tx_axis_tlast, qsfp2_mac_3_tx_axis_tlast, qsfp2_mac_2_tx_axis_tlast, qsfp2_mac_1_tx_axis_tlast, qsfp1_mac_4_tx_axis_tlast, qsfp1_mac_3_tx_axis_tlast, qsfp1_mac_2_tx_axis_tlast, qsfp1_mac_1_tx_axis_tlast}), - .m_axis_mac_tx_tuser({qsfp2_mac_4_tx_axis_tuser, qsfp2_mac_3_tx_axis_tuser, qsfp2_mac_2_tx_axis_tuser, qsfp2_mac_1_tx_axis_tuser, qsfp1_mac_4_tx_axis_tuser, qsfp1_mac_3_tx_axis_tuser, qsfp1_mac_2_tx_axis_tuser, qsfp1_mac_1_tx_axis_tuser}), - - .s_axis_mac_tx_ptp_ts({qsfp2_mac_4_tx_ptp_ts, qsfp2_mac_3_tx_ptp_ts, qsfp2_mac_2_tx_ptp_ts, qsfp2_mac_1_tx_ptp_ts, qsfp1_mac_4_tx_ptp_ts, qsfp1_mac_3_tx_ptp_ts, qsfp1_mac_2_tx_ptp_ts, qsfp1_mac_1_tx_ptp_ts}), - .s_axis_mac_tx_ptp_ts_tag({qsfp2_mac_4_tx_ptp_ts_tag, qsfp2_mac_3_tx_ptp_ts_tag, qsfp2_mac_2_tx_ptp_ts_tag, qsfp2_mac_1_tx_ptp_ts_tag, qsfp1_mac_4_tx_ptp_ts_tag, qsfp1_mac_3_tx_ptp_ts_tag, qsfp1_mac_2_tx_ptp_ts_tag, qsfp1_mac_1_tx_ptp_ts_tag}), - .s_axis_mac_tx_ptp_ts_valid({qsfp2_mac_4_tx_ptp_ts_valid, qsfp2_mac_3_tx_ptp_ts_valid, qsfp2_mac_2_tx_ptp_ts_valid, qsfp2_mac_1_tx_ptp_ts_valid, qsfp1_mac_4_tx_ptp_ts_valid, qsfp1_mac_3_tx_ptp_ts_valid, qsfp1_mac_2_tx_ptp_ts_valid, qsfp1_mac_1_tx_ptp_ts_valid}), - .s_axis_mac_tx_ptp_ts_ready(), - - .mac_tx_enable(), - .mac_tx_status({qsfp2_mac_4_tx_status, qsfp2_mac_3_tx_status, qsfp2_mac_2_tx_status, qsfp2_mac_1_tx_status, qsfp1_mac_4_tx_status, qsfp1_mac_3_tx_status, qsfp1_mac_2_tx_status, qsfp1_mac_1_tx_status}), - .mac_tx_lfc_en(), - .mac_tx_lfc_req({qsfp2_mac_4_tx_lfc_req, qsfp2_mac_3_tx_lfc_req, qsfp2_mac_2_tx_lfc_req, qsfp2_mac_1_tx_lfc_req, qsfp1_mac_4_tx_lfc_req, qsfp1_mac_3_tx_lfc_req, qsfp1_mac_2_tx_lfc_req, qsfp1_mac_1_tx_lfc_req}), - .mac_tx_pfc_en(), - .mac_tx_pfc_req({qsfp2_mac_4_tx_pfc_req, qsfp2_mac_3_tx_pfc_req, qsfp2_mac_2_tx_pfc_req, qsfp2_mac_1_tx_pfc_req, qsfp1_mac_4_tx_pfc_req, qsfp1_mac_3_tx_pfc_req, qsfp1_mac_2_tx_pfc_req, qsfp1_mac_1_tx_pfc_req}), - - .mac_rx_clk({qsfp2_mac_4_rx_clk, qsfp2_mac_3_rx_clk, qsfp2_mac_2_rx_clk, qsfp2_mac_1_rx_clk, qsfp1_mac_4_rx_clk, qsfp1_mac_3_rx_clk, qsfp1_mac_2_rx_clk, qsfp1_mac_1_rx_clk}), - .mac_rx_rst({qsfp2_mac_4_rx_rst, qsfp2_mac_3_rx_rst, qsfp2_mac_2_rx_rst, qsfp2_mac_1_rx_rst, qsfp1_mac_4_rx_rst, qsfp1_mac_3_rx_rst, qsfp1_mac_2_rx_rst, qsfp1_mac_1_rx_rst}), - - .mac_rx_ptp_clk({qsfp2_mac_4_rx_ptp_clk, qsfp2_mac_3_rx_ptp_clk, qsfp2_mac_2_rx_ptp_clk, qsfp2_mac_1_rx_ptp_clk, qsfp1_mac_4_rx_ptp_clk, qsfp1_mac_3_rx_ptp_clk, qsfp1_mac_2_rx_ptp_clk, qsfp1_mac_1_rx_ptp_clk}), - .mac_rx_ptp_rst({qsfp2_mac_4_rx_ptp_rst, qsfp2_mac_3_rx_ptp_rst, qsfp2_mac_2_rx_ptp_rst, qsfp2_mac_1_rx_ptp_rst, qsfp1_mac_4_rx_ptp_rst, qsfp1_mac_3_rx_ptp_rst, qsfp1_mac_2_rx_ptp_rst, qsfp1_mac_1_rx_ptp_rst}), - .mac_rx_ptp_ts_96({qsfp2_mac_4_rx_ptp_time, qsfp2_mac_3_rx_ptp_time, qsfp2_mac_2_rx_ptp_time, qsfp2_mac_1_rx_ptp_time, qsfp1_mac_4_rx_ptp_time, qsfp1_mac_3_rx_ptp_time, qsfp1_mac_2_rx_ptp_time, qsfp1_mac_1_rx_ptp_time}), - .mac_rx_ptp_ts_step(), - - .s_axis_mac_rx_tdata({qsfp2_mac_4_rx_axis_tdata, qsfp2_mac_3_rx_axis_tdata, qsfp2_mac_2_rx_axis_tdata, qsfp2_mac_1_rx_axis_tdata, qsfp1_mac_4_rx_axis_tdata, qsfp1_mac_3_rx_axis_tdata, qsfp1_mac_2_rx_axis_tdata, qsfp1_mac_1_rx_axis_tdata}), - .s_axis_mac_rx_tkeep({qsfp2_mac_4_rx_axis_tkeep, qsfp2_mac_3_rx_axis_tkeep, qsfp2_mac_2_rx_axis_tkeep, qsfp2_mac_1_rx_axis_tkeep, qsfp1_mac_4_rx_axis_tkeep, qsfp1_mac_3_rx_axis_tkeep, qsfp1_mac_2_rx_axis_tkeep, qsfp1_mac_1_rx_axis_tkeep}), - .s_axis_mac_rx_tvalid({qsfp2_mac_4_rx_axis_tvalid, qsfp2_mac_3_rx_axis_tvalid, qsfp2_mac_2_rx_axis_tvalid, qsfp2_mac_1_rx_axis_tvalid, qsfp1_mac_4_rx_axis_tvalid, qsfp1_mac_3_rx_axis_tvalid, qsfp1_mac_2_rx_axis_tvalid, qsfp1_mac_1_rx_axis_tvalid}), - .s_axis_mac_rx_tready(), - .s_axis_mac_rx_tlast({qsfp2_mac_4_rx_axis_tlast, qsfp2_mac_3_rx_axis_tlast, qsfp2_mac_2_rx_axis_tlast, qsfp2_mac_1_rx_axis_tlast, qsfp1_mac_4_rx_axis_tlast, qsfp1_mac_3_rx_axis_tlast, qsfp1_mac_2_rx_axis_tlast, qsfp1_mac_1_rx_axis_tlast}), - .s_axis_mac_rx_tuser({qsfp2_mac_4_rx_axis_tuser, qsfp2_mac_3_rx_axis_tuser, qsfp2_mac_2_rx_axis_tuser, qsfp2_mac_1_rx_axis_tuser, qsfp1_mac_4_rx_axis_tuser, qsfp1_mac_3_rx_axis_tuser, qsfp1_mac_2_rx_axis_tuser, qsfp1_mac_1_rx_axis_tuser}), - - .mac_rx_enable(), - .mac_rx_status({qsfp2_mac_4_rx_status, qsfp2_mac_3_rx_status, qsfp2_mac_2_rx_status, qsfp2_mac_1_rx_status, qsfp1_mac_4_rx_status, qsfp1_mac_3_rx_status, qsfp1_mac_2_rx_status, qsfp1_mac_1_rx_status}), - .mac_rx_lfc_en(), - .mac_rx_lfc_req({qsfp2_mac_4_rx_lfc_req, qsfp2_mac_3_rx_lfc_req, qsfp2_mac_2_rx_lfc_req, qsfp2_mac_1_rx_lfc_req, qsfp1_mac_4_rx_lfc_req, qsfp1_mac_3_rx_lfc_req, qsfp1_mac_2_rx_lfc_req, qsfp1_mac_1_rx_lfc_req}), - .mac_rx_lfc_ack(), - .mac_rx_pfc_en(), - .mac_rx_pfc_req({qsfp2_mac_4_rx_pfc_req, qsfp2_mac_3_rx_pfc_req, qsfp2_mac_2_rx_pfc_req, qsfp2_mac_1_rx_pfc_req, qsfp1_mac_4_rx_pfc_req, qsfp1_mac_3_rx_pfc_req, qsfp1_mac_2_rx_pfc_req, qsfp1_mac_1_rx_pfc_req}), - .mac_rx_pfc_ack(), - - // towards datapath - .tx_clk(eth_tx_clk), - .tx_rst(eth_tx_rst), - - .tx_ptp_clk(eth_tx_ptp_clk), - .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_tod), - .tx_ptp_ts_step(eth_tx_ptp_ts_tod_step), - - .s_axis_tx_tdata(axis_eth_tx_tdata), - .s_axis_tx_tkeep(axis_eth_tx_tkeep), - .s_axis_tx_tvalid(axis_eth_tx_tvalid), - .s_axis_tx_tready(axis_eth_tx_tready), - .s_axis_tx_tlast(axis_eth_tx_tlast), - .s_axis_tx_tuser(axis_eth_tx_tuser), - - .m_axis_tx_ptp_ts(axis_eth_tx_ptp_ts), - .m_axis_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag), - .m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid), - .m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready), - - .tx_enable(eth_tx_enable), - .tx_status(eth_tx_status), - .tx_lfc_en(eth_tx_lfc_en), - .tx_lfc_req(eth_tx_lfc_req), - .tx_pfc_en(eth_tx_pfc_en), - .tx_pfc_req(eth_tx_pfc_req), - - .rx_clk(eth_rx_clk), - .rx_rst(eth_rx_rst), - - .rx_ptp_clk(eth_rx_ptp_clk), - .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_tod), - .rx_ptp_ts_step(eth_rx_ptp_ts_tod_step), - - .m_axis_rx_tdata(axis_eth_rx_tdata), - .m_axis_rx_tkeep(axis_eth_rx_tkeep), - .m_axis_rx_tvalid(axis_eth_rx_tvalid), - .m_axis_rx_tready(axis_eth_rx_tready), - .m_axis_rx_tlast(axis_eth_rx_tlast), - .m_axis_rx_tuser(axis_eth_rx_tuser), - - .rx_enable(eth_rx_enable), - .rx_status(eth_rx_status), - .rx_lfc_en(eth_rx_lfc_en), - .rx_lfc_req(eth_rx_lfc_req), - .rx_lfc_ack(eth_rx_lfc_ack), - .rx_pfc_en(eth_rx_pfc_en), - .rx_pfc_req(eth_rx_pfc_req), - .rx_pfc_ack(eth_rx_pfc_ack) -); - -mqnic_core_pcie_ptile #( - // FW and board IDs - .FPGA_ID(FPGA_ID), - .FW_ID(FW_ID), - .FW_VER(FW_VER), - .BOARD_ID(BOARD_ID), - .BOARD_VER(BOARD_VER), - .BUILD_DATE(BUILD_DATE), - .GIT_HASH(GIT_HASH), - .RELEASE_INFO(RELEASE_INFO), - - // Structural configuration - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - .SCHED_PER_IF(SCHED_PER_IF), - - .PORT_COUNT(PORT_COUNT), - - // Clock configuration - .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), - .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), - - // PTP configuration - .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), - .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), - .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), - .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), - - // Queue manager configuration - .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), - .EQN_WIDTH(EQN_WIDTH), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .CQN_WIDTH(CQN_WIDTH), - .EQ_PIPELINE(EQ_PIPELINE), - .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), - .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .CQ_PIPELINE(CQ_PIPELINE), - - // TX and RX engine configuration - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), - - // Scheduler configuration - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - - // Interface configuration - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_CPL_ENABLE(PTP_TS_ENABLE), - .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), - .TX_TAG_WIDTH(TX_TAG_WIDTH), - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .PFC_ENABLE(PFC_ENABLE), - .LFC_ENABLE(LFC_ENABLE), - .MAC_CTRL_ENABLE(0), - .TX_FIFO_DEPTH(TX_FIFO_DEPTH), - .RX_FIFO_DEPTH(RX_FIFO_DEPTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - - // RAM configuration - .DDR_ENABLE(0), - .HBM_ENABLE(0), - - // Application block configuration - .APP_ID(APP_ID), - .APP_ENABLE(APP_ENABLE), - .APP_CTRL_ENABLE(APP_CTRL_ENABLE), - .APP_DMA_ENABLE(APP_DMA_ENABLE), - .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), - .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), - .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), - .APP_STAT_ENABLE(APP_STAT_ENABLE), - .APP_GPIO_IN_WIDTH(32), - .APP_GPIO_OUT_WIDTH(32), - - // DMA interface configuration - .DMA_IMM_ENABLE(DMA_IMM_ENABLE), - .DMA_IMM_WIDTH(DMA_IMM_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - - // PCIe interface configuration - .SEG_COUNT(SEG_COUNT), - .SEG_DATA_WIDTH(SEG_DATA_WIDTH), - .SEG_EMPTY_WIDTH(SEG_EMPTY_WIDTH), - .TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH), - .PF_COUNT(PF_COUNT), - .VF_COUNT(VF_COUNT), - .F_COUNT(F_COUNT), - .PCIE_TAG_COUNT(PCIE_TAG_COUNT), - - // Interrupt configuration - .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), - - // AXI lite interface configuration (control) - .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), - .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(0), - .RB_NEXT_PTR(RB_BASE_ADDR), - - // AXI lite interface configuration (application control) - .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), - .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), - - // Ethernet interface configuration - .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), - .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .AXIS_ETH_RX_USE_READY(0), - .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), - .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), - .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), - .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), - .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), - - // Statistics counter subsystem - .STAT_ENABLE(STAT_ENABLE), - .STAT_DMA_ENABLE(STAT_DMA_ENABLE), - .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), - .STAT_INC_WIDTH(STAT_INC_WIDTH), - .STAT_ID_WIDTH(STAT_ID_WIDTH) -) -core_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * P-Tile RX AVST interface - */ - .rx_st_data(rx_st_data), - .rx_st_empty(rx_st_empty), - .rx_st_sop(rx_st_sop), - .rx_st_eop(rx_st_eop), - .rx_st_valid(rx_st_valid), - .rx_st_ready(rx_st_ready), - .rx_st_hdr(rx_st_hdr), - .rx_st_tlp_prfx(rx_st_tlp_prfx), - .rx_st_vf_active(rx_st_vf_active), - .rx_st_func_num(rx_st_func_num), - .rx_st_vf_num(rx_st_vf_num), - .rx_st_bar_range(rx_st_bar_range), - .rx_st_tlp_abort(rx_st_tlp_abort), - - /* - * P-Tile TX AVST interface - */ - .tx_st_data(tx_st_data), - .tx_st_sop(tx_st_sop), - .tx_st_eop(tx_st_eop), - .tx_st_valid(tx_st_valid), - .tx_st_ready(tx_st_ready), - .tx_st_err(tx_st_err), - .tx_st_hdr(tx_st_hdr), - .tx_st_tlp_prfx(tx_st_tlp_prfx), - - /* - * P-Tile RX flow control - */ - .rx_buffer_limit(rx_buffer_limit), - .rx_buffer_limit_tdm_idx(rx_buffer_limit_tdm_idx), - - /* - * P-Tile TX flow control - */ - .tx_cdts_limit(tx_cdts_limit), - .tx_cdts_limit_tdm_idx(tx_cdts_limit_tdm_idx), - - /* - * P-Tile configuration interface - */ - .tl_cfg_ctl(tl_cfg_ctl), - .tl_cfg_add(tl_cfg_add), - .tl_cfg_func(tl_cfg_func), - - /* - * AXI-Lite master interface (passthrough for NIC control and status) - */ - .m_axil_csr_awaddr(axil_csr_awaddr), - .m_axil_csr_awprot(axil_csr_awprot), - .m_axil_csr_awvalid(axil_csr_awvalid), - .m_axil_csr_awready(axil_csr_awready), - .m_axil_csr_wdata(axil_csr_wdata), - .m_axil_csr_wstrb(axil_csr_wstrb), - .m_axil_csr_wvalid(axil_csr_wvalid), - .m_axil_csr_wready(axil_csr_wready), - .m_axil_csr_bresp(axil_csr_bresp), - .m_axil_csr_bvalid(axil_csr_bvalid), - .m_axil_csr_bready(axil_csr_bready), - .m_axil_csr_araddr(axil_csr_araddr), - .m_axil_csr_arprot(axil_csr_arprot), - .m_axil_csr_arvalid(axil_csr_arvalid), - .m_axil_csr_arready(axil_csr_arready), - .m_axil_csr_rdata(axil_csr_rdata), - .m_axil_csr_rresp(axil_csr_rresp), - .m_axil_csr_rvalid(axil_csr_rvalid), - .m_axil_csr_rready(axil_csr_rready), - - /* - * Control register interface - */ - .ctrl_reg_wr_addr(ctrl_reg_wr_addr), - .ctrl_reg_wr_data(ctrl_reg_wr_data), - .ctrl_reg_wr_strb(ctrl_reg_wr_strb), - .ctrl_reg_wr_en(ctrl_reg_wr_en), - .ctrl_reg_wr_wait(ctrl_reg_wr_wait), - .ctrl_reg_wr_ack(ctrl_reg_wr_ack), - .ctrl_reg_rd_addr(ctrl_reg_rd_addr), - .ctrl_reg_rd_en(ctrl_reg_rd_en), - .ctrl_reg_rd_data(ctrl_reg_rd_data), - .ctrl_reg_rd_wait(ctrl_reg_rd_wait), - .ctrl_reg_rd_ack(ctrl_reg_rd_ack), - - /* - * PTP clock - */ - .ptp_clk(ptp_clk), - .ptp_rst(ptp_rst), - .ptp_sample_clk(ptp_sample_clk), - .ptp_td_sd(ptp_td_sd), - .ptp_pps(ptp_pps), - .ptp_pps_str(ptp_pps_str), - .ptp_sync_locked(ptp_sync_locked), - .ptp_sync_ts_rel(ptp_sync_ts_rel), - .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), - .ptp_sync_ts_tod(ptp_sync_ts_tod), - .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), - .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_pps_str(ptp_sync_pps_str), - .ptp_perout_locked(ptp_perout_locked), - .ptp_perout_error(ptp_perout_error), - .ptp_perout_pulse(ptp_perout_pulse), - - /* - * Ethernet - */ - .eth_tx_clk(eth_tx_clk), - .eth_tx_rst(eth_tx_rst), - - .eth_tx_ptp_clk(eth_tx_ptp_clk), - .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_tod(eth_tx_ptp_ts_tod), - .eth_tx_ptp_ts_tod_step(eth_tx_ptp_ts_tod_step), - - .m_axis_eth_tx_tdata(axis_eth_tx_tdata), - .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), - .m_axis_eth_tx_tvalid(axis_eth_tx_tvalid), - .m_axis_eth_tx_tready(axis_eth_tx_tready), - .m_axis_eth_tx_tlast(axis_eth_tx_tlast), - .m_axis_eth_tx_tuser(axis_eth_tx_tuser), - - .s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts), - .s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag), - .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), - .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), - - .eth_tx_enable(eth_tx_enable), - .eth_tx_status(eth_tx_status), - .eth_tx_lfc_en(eth_tx_lfc_en), - .eth_tx_lfc_req(eth_tx_lfc_req), - .eth_tx_pfc_en(eth_tx_pfc_en), - .eth_tx_pfc_req(eth_tx_pfc_req), - .eth_tx_fc_quanta_clk_en(0), - - .eth_rx_clk(eth_rx_clk), - .eth_rx_rst(eth_rx_rst), - - .eth_rx_ptp_clk(eth_rx_ptp_clk), - .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_tod(eth_rx_ptp_ts_tod), - .eth_rx_ptp_ts_tod_step(eth_rx_ptp_ts_tod_step), - - .s_axis_eth_rx_tdata(axis_eth_rx_tdata), - .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), - .s_axis_eth_rx_tvalid(axis_eth_rx_tvalid), - .s_axis_eth_rx_tready(axis_eth_rx_tready), - .s_axis_eth_rx_tlast(axis_eth_rx_tlast), - .s_axis_eth_rx_tuser(axis_eth_rx_tuser), - - .eth_rx_enable(eth_rx_enable), - .eth_rx_status(eth_rx_status), - .eth_rx_lfc_en(eth_rx_lfc_en), - .eth_rx_lfc_req(eth_rx_lfc_req), - .eth_rx_lfc_ack(eth_rx_lfc_ack), - .eth_rx_pfc_en(eth_rx_pfc_en), - .eth_rx_pfc_req(eth_rx_pfc_req), - .eth_rx_pfc_ack(eth_rx_pfc_ack), - .eth_rx_fc_quanta_clk_en(0), - - /* - * DDR - */ - .ddr_clk(0), - .ddr_rst(0), - - .m_axi_ddr_awid(), - .m_axi_ddr_awaddr(), - .m_axi_ddr_awlen(), - .m_axi_ddr_awsize(), - .m_axi_ddr_awburst(), - .m_axi_ddr_awlock(), - .m_axi_ddr_awcache(), - .m_axi_ddr_awprot(), - .m_axi_ddr_awqos(), - .m_axi_ddr_awuser(), - .m_axi_ddr_awvalid(), - .m_axi_ddr_awready(0), - .m_axi_ddr_wdata(), - .m_axi_ddr_wstrb(), - .m_axi_ddr_wlast(), - .m_axi_ddr_wuser(), - .m_axi_ddr_wvalid(), - .m_axi_ddr_wready(0), - .m_axi_ddr_bid(0), - .m_axi_ddr_bresp(0), - .m_axi_ddr_buser(0), - .m_axi_ddr_bvalid(0), - .m_axi_ddr_bready(), - .m_axi_ddr_arid(), - .m_axi_ddr_araddr(), - .m_axi_ddr_arlen(), - .m_axi_ddr_arsize(), - .m_axi_ddr_arburst(), - .m_axi_ddr_arlock(), - .m_axi_ddr_arcache(), - .m_axi_ddr_arprot(), - .m_axi_ddr_arqos(), - .m_axi_ddr_aruser(), - .m_axi_ddr_arvalid(), - .m_axi_ddr_arready(0), - .m_axi_ddr_rid(0), - .m_axi_ddr_rdata(0), - .m_axi_ddr_rresp(0), - .m_axi_ddr_rlast(0), - .m_axi_ddr_ruser(0), - .m_axi_ddr_rvalid(0), - .m_axi_ddr_rready(), - - .ddr_status(0), - - /* - * HBM - */ - .hbm_clk(0), - .hbm_rst(0), - - .m_axi_hbm_awid(), - .m_axi_hbm_awaddr(), - .m_axi_hbm_awlen(), - .m_axi_hbm_awsize(), - .m_axi_hbm_awburst(), - .m_axi_hbm_awlock(), - .m_axi_hbm_awcache(), - .m_axi_hbm_awprot(), - .m_axi_hbm_awqos(), - .m_axi_hbm_awuser(), - .m_axi_hbm_awvalid(), - .m_axi_hbm_awready(0), - .m_axi_hbm_wdata(), - .m_axi_hbm_wstrb(), - .m_axi_hbm_wlast(), - .m_axi_hbm_wuser(), - .m_axi_hbm_wvalid(), - .m_axi_hbm_wready(0), - .m_axi_hbm_bid(0), - .m_axi_hbm_bresp(0), - .m_axi_hbm_buser(0), - .m_axi_hbm_bvalid(0), - .m_axi_hbm_bready(), - .m_axi_hbm_arid(), - .m_axi_hbm_araddr(), - .m_axi_hbm_arlen(), - .m_axi_hbm_arsize(), - .m_axi_hbm_arburst(), - .m_axi_hbm_arlock(), - .m_axi_hbm_arcache(), - .m_axi_hbm_arprot(), - .m_axi_hbm_arqos(), - .m_axi_hbm_aruser(), - .m_axi_hbm_arvalid(), - .m_axi_hbm_arready(0), - .m_axi_hbm_rid(0), - .m_axi_hbm_rdata(0), - .m_axi_hbm_rresp(0), - .m_axi_hbm_rlast(0), - .m_axi_hbm_ruser(0), - .m_axi_hbm_rvalid(0), - .m_axi_hbm_rready(), - - .hbm_status(0), - - /* - * Statistics input - */ - .s_axis_stat_tdata(0), - .s_axis_stat_tid(0), - .s_axis_stat_tvalid(1'b0), - .s_axis_stat_tready(), - - /* - * GPIO - */ - .app_gpio_in(0), - .app_gpio_out(), - - /* - * JTAG - */ - .app_jtag_tdi(1'b0), - .app_jtag_tdo(), - .app_jtag_tms(1'b0), - .app_jtag_tck(1'b0) -); - -endmodule - -`resetall diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/sync_signal.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/sync_signal.v deleted file mode 100644 index 74b855fa1..000000000 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/sync_signal.v +++ /dev/null @@ -1,62 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog-2001 - -`resetall -`timescale 1 ns / 1 ps -`default_nettype none - -/* - * Synchronizes an asyncronous signal to a given clock by using a pipeline of - * two registers. - */ -module sync_signal #( - parameter WIDTH=1, // width of the input and output signals - parameter N=2 // depth of synchronizer -)( - input wire clk, - input wire [WIDTH-1:0] in, - output wire [WIDTH-1:0] out -); - -reg [WIDTH-1:0] sync_reg[N-1:0]; - -/* - * The synchronized output is the last register in the pipeline. - */ -assign out = sync_reg[N-1]; - -integer k; - -always @(posedge clk) begin - sync_reg[0] <= in; - for (k = 1; k < N; k = k + 1) begin - sync_reg[k] <= sync_reg[k-1]; - end -end - -endmodule - -`resetall diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/xcvr_ctrl.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/xcvr_ctrl.v deleted file mode 100644 index b1e52b02d..000000000 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/rtl/xcvr_ctrl.v +++ /dev/null @@ -1,268 +0,0 @@ -/* - -Copyright (c) 2021 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * Transceiver control - */ -module xcvr_ctrl ( - input wire reconfig_clk, - input wire reconfig_rst, - - input wire pll_locked_in, - - output wire [18:0] xcvr_reconfig_address, - output wire xcvr_reconfig_read, - output wire xcvr_reconfig_write, - input wire [7:0] xcvr_reconfig_readdata, - output wire [7:0] xcvr_reconfig_writedata, - input wire xcvr_reconfig_waitrequest -); - -localparam [3:0] - STATE_IDLE = 4'd0, - STATE_LOAD_PMA_1 = 4'd1, - STATE_LOAD_PMA_2 = 4'd2, - STATE_INIT_ADAPT_1 = 4'd3, - STATE_INIT_ADAPT_2 = 4'd4, - STATE_INIT_ADAPT_3 = 4'd5, - STATE_INIT_ADAPT_4 = 4'd6, - STATE_CONT_ADAPT_1 = 4'd7, - STATE_CONT_ADAPT_2 = 4'd8, - STATE_CONT_ADAPT_3 = 4'd9, - STATE_CONT_ADAPT_4 = 4'd10, - STATE_DONE = 4'd11; - -reg [3:0] state_reg = STATE_IDLE, state_next; - -reg [18:0] xcvr_reconfig_address_reg = 19'd0, xcvr_reconfig_address_next; -reg xcvr_reconfig_read_reg = 1'b0, xcvr_reconfig_read_next; -reg xcvr_reconfig_write_reg = 1'b0, xcvr_reconfig_write_next; -reg [7:0] xcvr_reconfig_writedata_reg = 8'd0, xcvr_reconfig_writedata_next; - -reg [7:0] read_data_reg = 8'd0, read_data_next; -reg read_data_valid_reg = 1'b0, read_data_valid_next; - -reg [15:0] delay_count_reg = 0, delay_count_next; - -reg pll_locked_sync_1_reg = 0; -reg pll_locked_sync_2_reg = 0; -reg pll_locked_sync_3_reg = 0; - -assign xcvr_reconfig_address = xcvr_reconfig_address_reg; -assign xcvr_reconfig_read = xcvr_reconfig_read_reg; -assign xcvr_reconfig_write = xcvr_reconfig_write_reg; -assign xcvr_reconfig_writedata = xcvr_reconfig_writedata_reg; - -always @(posedge reconfig_clk) begin - pll_locked_sync_1_reg <= pll_locked_in; - pll_locked_sync_2_reg <= pll_locked_sync_1_reg; - pll_locked_sync_3_reg <= pll_locked_sync_2_reg; -end - -always @* begin - state_next = STATE_IDLE; - - xcvr_reconfig_address_next = xcvr_reconfig_address_reg; - xcvr_reconfig_read_next = 1'b0; - xcvr_reconfig_write_next = 1'b0; - xcvr_reconfig_writedata_next = xcvr_reconfig_writedata_reg; - - read_data_next = read_data_reg; - read_data_valid_next = read_data_valid_reg; - - delay_count_next = delay_count_reg; - - if (xcvr_reconfig_read_reg || xcvr_reconfig_write_reg) begin - // operation in progress - if (xcvr_reconfig_waitrequest) begin - // wait state, hold command - xcvr_reconfig_read_next = xcvr_reconfig_read_reg; - xcvr_reconfig_write_next = xcvr_reconfig_write_reg; - end else begin - // release command - xcvr_reconfig_read_next = 1'b0; - xcvr_reconfig_write_next = 1'b0; - - if (xcvr_reconfig_read_reg) begin - // latch read data - read_data_next = xcvr_reconfig_readdata; - read_data_valid_next = 1'b1; - end - end - state_next = state_reg; - end else if (delay_count_reg != 0) begin - // stall for delay - delay_count_next = delay_count_reg - 1; - state_next = state_reg; - end else begin - read_data_valid_next = 1'b0; - - case (state_reg) - STATE_IDLE: begin - // wait for PLL to lock - if (pll_locked_sync_3_reg) begin - delay_count_next = 16'hffff; - state_next = STATE_LOAD_PMA_1; - end else begin - state_next = STATE_IDLE; - end - end - STATE_LOAD_PMA_1: begin - // load PMA config - xcvr_reconfig_address_next = 19'h40143; - xcvr_reconfig_writedata_next = 8'h80; - xcvr_reconfig_write_next = 1'b1; - state_next = STATE_LOAD_PMA_2; - end - STATE_LOAD_PMA_2: begin - // check status - if (read_data_valid_reg && read_data_reg[0]) begin - // start initial adaptation - xcvr_reconfig_address_next = 19'h200; - xcvr_reconfig_writedata_next = 8'hD2; - xcvr_reconfig_write_next = 1'b1; - state_next = STATE_INIT_ADAPT_1; - end else begin - // read status - xcvr_reconfig_address_next = 19'h40144; - xcvr_reconfig_read_next = 1'b1; - state_next = STATE_LOAD_PMA_2; - end - end - STATE_INIT_ADAPT_1: begin - // start initial adaptation - xcvr_reconfig_address_next = 19'h201; - xcvr_reconfig_writedata_next = 8'h02; - xcvr_reconfig_write_next = 1'b1; - state_next = STATE_INIT_ADAPT_2; - end - STATE_INIT_ADAPT_2: begin - // start initial adaptation - xcvr_reconfig_address_next = 19'h202; - xcvr_reconfig_writedata_next = 8'h01; - xcvr_reconfig_write_next = 1'b1; - state_next = STATE_INIT_ADAPT_3; - end - STATE_INIT_ADAPT_3: begin - // start initial adaptation - xcvr_reconfig_address_next = 19'h203; - xcvr_reconfig_writedata_next = 8'h96; - xcvr_reconfig_write_next = 1'b1; - state_next = STATE_INIT_ADAPT_4; - end - STATE_INIT_ADAPT_4: begin - // check status - if (read_data_valid_reg && read_data_reg == 8'h80) begin - // start continuous adaptation - xcvr_reconfig_address_next = 19'h200; - xcvr_reconfig_writedata_next = 8'hF6; - xcvr_reconfig_write_next = 1'b1; - state_next = STATE_CONT_ADAPT_1; - end else begin - // read status - xcvr_reconfig_address_next = 19'h207; - xcvr_reconfig_read_next = 1'b1; - state_next = STATE_INIT_ADAPT_4; - end - end - STATE_CONT_ADAPT_1: begin - // start continuous adaptation - xcvr_reconfig_address_next = 19'h201; - xcvr_reconfig_writedata_next = 8'h01; - xcvr_reconfig_write_next = 1'b1; - state_next = STATE_CONT_ADAPT_2; - end - STATE_CONT_ADAPT_2: begin - // start continuous adaptation - xcvr_reconfig_address_next = 19'h202; - xcvr_reconfig_writedata_next = 8'h03; - xcvr_reconfig_write_next = 1'b1; - state_next = STATE_CONT_ADAPT_3; - end - STATE_CONT_ADAPT_3: begin - // start continuous adaptation - xcvr_reconfig_address_next = 19'h203; - xcvr_reconfig_writedata_next = 8'h96; - xcvr_reconfig_write_next = 1'b1; - state_next = STATE_CONT_ADAPT_4; - end - STATE_CONT_ADAPT_4: begin - // check status - if (read_data_valid_reg && read_data_reg == 8'h80) begin - // done - state_next = STATE_DONE; - end else begin - // read status - xcvr_reconfig_address_next = 19'h207; - xcvr_reconfig_read_next = 1'b1; - state_next = STATE_CONT_ADAPT_4; - end - end - STATE_DONE: begin - // done with operation - state_next = STATE_DONE; - end - endcase - end - - if (!pll_locked_sync_3_reg) begin - // go back to idle if PLL is unlocked - state_next = STATE_IDLE; - end -end - -always @(posedge reconfig_clk) begin - state_reg <= state_next; - - xcvr_reconfig_address_reg <= xcvr_reconfig_address_next; - xcvr_reconfig_read_reg <= xcvr_reconfig_read_next; - xcvr_reconfig_write_reg <= xcvr_reconfig_write_next; - xcvr_reconfig_writedata_reg <= xcvr_reconfig_writedata_next; - - read_data_reg <= read_data_next; - read_data_valid_reg <= read_data_valid_next; - - delay_count_reg <= delay_count_next; - - if (reconfig_rst) begin - state_reg <= STATE_IDLE; - - xcvr_reconfig_read_reg <= 1'b0; - xcvr_reconfig_write_reg <= 1'b0; - - read_data_valid_reg <= 1'b0; - - delay_count_reg <= 0; - end -end - -endmodule - -`resetall diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/Makefile deleted file mode 100644 index 593962e07..000000000 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/Makefile +++ /dev/null @@ -1,256 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2020-2023 The Regents of the University of California - -TOPLEVEL_LANG = verilog - -SIM ?= icarus -WAVES ?= 0 - -COCOTB_HDL_TIMEUNIT = 1ns -COCOTB_HDL_TIMEPRECISION = 1ps - -DUT = fpga_core -TOPLEVEL = $(DUT) -MODULE = test_$(DUT) -VERILOG_SOURCES += ../../rtl/$(DUT).v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_ptile.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v -VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v -VERILOG_SOURCES += ../../rtl/common/cpl_write.v -VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v -VERILOG_SOURCES += ../../rtl/common/desc_fetch.v -VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/queue_manager.v -VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v -VERILOG_SOURCES += ../../rtl/common/tx_fifo.v -VERILOG_SOURCES += ../../rtl/common/rx_fifo.v -VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v -VERILOG_SOURCES += ../../rtl/common/tx_engine.v -VERILOG_SOURCES += ../../rtl/common/rx_engine.v -VERILOG_SOURCES += ../../rtl/common/tx_checksum.v -VERILOG_SOURCES += ../../rtl/common/rx_hash.v -VERILOG_SOURCES += ../../rtl/common/rx_checksum.v -VERILOG_SOURCES += ../../rtl/common/stats_counter.v -VERILOG_SOURCES += ../../rtl/common/stats_collect.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v -VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v -VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v -VERILOG_SOURCES += ../../rtl/common/tdma_ber.v -VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v -VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v -VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fc_count.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v -VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_if.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_if_rx.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_if_tx.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_cfg.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_fc_counter.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v - -# module parameters - -# Structural configuration -export PARAM_IF_COUNT := 2 -export PARAM_PORTS_PER_IF := 1 -export PARAM_SCHED_PER_IF := $(PARAM_PORTS_PER_IF) -export PARAM_PORT_MASK := 0 - -# Clock configuration -export PARAM_CLK_PERIOD_NS_NUM := 4 -export PARAM_CLK_PERIOD_NS_DENOM := 1 - -# PTP configuration -export PARAM_PTP_CLK_PERIOD_NS_NUM := 4096 -export PARAM_PTP_CLK_PERIOD_NS_DENOM := 825 -export PARAM_PTP_CLOCK_PIPELINE := 0 -export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_SEPARATE_TX_CLOCK := 0 -export PARAM_PTP_SEPARATE_RX_CLOCK := 0 -export PARAM_PTP_PORT_CDC_PIPELINE := 0 -export PARAM_PTP_PEROUT_ENABLE := 1 -export PARAM_PTP_PEROUT_COUNT := 1 - -# Queue manager configuration -export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_CQ_OP_TABLE_SIZE := 32 -export PARAM_EQN_WIDTH := 6 -export PARAM_TX_QUEUE_INDEX_WIDTH := 13 -export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") -export PARAM_EQ_PIPELINE := 3 -export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") - -# TX and RX engine configuration -export PARAM_TX_DESC_TABLE_SIZE := 32 -export PARAM_RX_DESC_TABLE_SIZE := 32 -export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") - -# Scheduler configuration -export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) -export PARAM_TX_SCHEDULER_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_TDMA_INDEX_WIDTH := 6 - -# Interface configuration -export PARAM_PTP_TS_ENABLE := 1 -export PARAM_TX_CPL_FIFO_DEPTH := 32 -export PARAM_TX_CHECKSUM_ENABLE := 1 -export PARAM_RX_HASH_ENABLE := 1 -export PARAM_RX_CHECKSUM_ENABLE := 1 -export PARAM_LFC_ENABLE := 1 -export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) -export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 -export PARAM_MAX_TX_SIZE := 9214 -export PARAM_MAX_RX_SIZE := 9214 -export PARAM_TX_RAM_SIZE := 32768 -export PARAM_RX_RAM_SIZE := 32768 - -# Application block configuration -export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) -export PARAM_APP_ENABLE := 0 -export PARAM_APP_CTRL_ENABLE := 1 -export PARAM_APP_DMA_ENABLE := 1 -export PARAM_APP_AXIS_DIRECT_ENABLE := 1 -export PARAM_APP_AXIS_SYNC_ENABLE := 1 -export PARAM_APP_AXIS_IF_ENABLE := 1 -export PARAM_APP_STAT_ENABLE := 1 - -# DMA interface configuration -export PARAM_DMA_IMM_ENABLE := 0 -export PARAM_DMA_IMM_WIDTH := 32 -export PARAM_DMA_LEN_WIDTH := 16 -export PARAM_DMA_TAG_WIDTH := 16 -export PARAM_RAM_ADDR_WIDTH := $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())") -export PARAM_RAM_PIPELINE := 2 - -# PCIe interface configuration -export PARAM_SEG_COUNT := 2 -export PARAM_SEG_DATA_WIDTH := 256 -export PARAM_PF_COUNT := 1 -export PARAM_VF_COUNT := 0 - -# Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) - -# AXI lite interface configuration (control) -export PARAM_AXIL_CTRL_DATA_WIDTH := 32 -export PARAM_AXIL_CTRL_ADDR_WIDTH := 24 - -# AXI lite interface configuration (application control) -export PARAM_AXIL_APP_CTRL_DATA_WIDTH := $(PARAM_AXIL_CTRL_DATA_WIDTH) -export PARAM_AXIL_APP_CTRL_ADDR_WIDTH := 24 - -# Ethernet interface configuration -export PARAM_AXIS_ETH_TX_PIPELINE := 0 -export PARAM_AXIS_ETH_TX_FIFO_PIPELINE := 2 -export PARAM_AXIS_ETH_TX_TS_PIPELINE := 0 -export PARAM_AXIS_ETH_RX_PIPELINE := 0 -export PARAM_AXIS_ETH_RX_FIFO_PIPELINE := 2 - -# Statistics counter subsystem -export PARAM_STAT_ENABLE := 1 -export PARAM_STAT_DMA_ENABLE := 1 -export PARAM_STAT_PCIE_ENABLE := 1 -export PARAM_STAT_INC_WIDTH := 24 -export PARAM_STAT_ID_WIDTH := 12 - -ifeq ($(SIM), icarus) - PLUSARGS += -fst - - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif -else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - COMPILE_ARGS += --trace-fst - endif -endif - -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/mqnic.py b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/mqnic.py deleted file mode 120000 index dfa8522e7..000000000 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/mqnic.py +++ /dev/null @@ -1 +0,0 @@ -../../../../../common/tb/mqnic.py \ No newline at end of file diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/test_fpga_core.py deleted file mode 100644 index 5da409d42..000000000 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_25g/tb/fpga_core/test_fpga_core.py +++ /dev/null @@ -1,756 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2020-2023 The Regents of the University of California - -import logging -import os -import sys - -import scapy.utils -from scapy.layers.l2 import Ether -from scapy.layers.inet import IP, UDP - -import cocotb_test.simulator - -import cocotb -from cocotb.log import SimLog -from cocotb.clock import Clock -from cocotb.triggers import RisingEdge, FallingEdge, Timer - -from cocotbext.axi import AxiStreamBus -from cocotbext.eth import EthMac -from cocotbext.pcie.core import RootComplex -from cocotbext.pcie.intel.ptile import PTilePcieDevice, PTileRxBus, PTileTxBus - -try: - import mqnic -except ImportError: - # attempt import from current directory - sys.path.insert(0, os.path.join(os.path.dirname(__file__))) - try: - import mqnic - finally: - del sys.path[0] - - -class TB(object): - def __init__(self, dut, msix_count=32): - self.dut = dut - - self.log = SimLog("cocotb.tb") - self.log.setLevel(logging.DEBUG) - - # PCIe - self.rc = RootComplex() - - self.rc.max_payload_size = 0x1 # 256 bytes - self.rc.max_read_request_size = 0x2 # 512 bytes - - self.dev = PTilePcieDevice( - # configuration options - pcie_generation=3, - pcie_link_width=16, - pld_clk_frequency=250e6, - pf_count=1, - max_payload_size=512, - enable_extended_tag=True, - - pf0_msi_enable=False, - pf0_msi_count=1, - pf1_msi_enable=False, - pf1_msi_count=1, - pf2_msi_enable=False, - pf2_msi_count=1, - pf3_msi_enable=False, - pf3_msi_count=1, - pf0_msix_enable=True, - pf0_msix_table_size=msix_count-1, - pf0_msix_table_bir=0, - pf0_msix_table_offset=0x00010000, - pf0_msix_pba_bir=0, - pf0_msix_pba_offset=0x00018000, - pf1_msix_enable=False, - pf1_msix_table_size=0, - pf1_msix_table_bir=0, - pf1_msix_table_offset=0x00000000, - pf1_msix_pba_bir=0, - pf1_msix_pba_offset=0x00000000, - pf2_msix_enable=False, - pf2_msix_table_size=0, - pf2_msix_table_bir=0, - pf2_msix_table_offset=0x00000000, - pf2_msix_pba_bir=0, - pf2_msix_pba_offset=0x00000000, - pf3_msix_enable=False, - pf3_msix_table_size=0, - pf3_msix_table_bir=0, - pf3_msix_table_offset=0x00000000, - pf3_msix_pba_bir=0, - pf3_msix_pba_offset=0x00000000, - - # signals - # Clock and reset - reset_status=dut.rst_250mhz, - # reset_status_n=dut.reset_status_n, - coreclkout_hip=dut.clk_250mhz, - # refclk0=dut.refclk0, - # refclk1=dut.refclk1, - # pin_perst_n=dut.pin_perst_n, - - # RX interface - rx_bus=PTileRxBus.from_prefix(dut, "rx_st"), - # rx_par_err=dut.rx_par_err, - - # TX interface - tx_bus=PTileTxBus.from_prefix(dut, "tx_st"), - # tx_par_err=dut.tx_par_err, - - # RX flow control - rx_buffer_limit=dut.rx_buffer_limit, - rx_buffer_limit_tdm_idx=dut.rx_buffer_limit_tdm_idx, - - # TX flow control - tx_cdts_limit=dut.tx_cdts_limit, - tx_cdts_limit_tdm_idx=dut.tx_cdts_limit_tdm_idx, - - # Power management and hard IP status interface - # link_up=dut.link_up, - # dl_up=dut.dl_up, - # surprise_down_err=dut.surprise_down_err, - # ltssm_state=dut.ltssm_state, - # pm_state=dut.pm_state, - # pm_dstate=dut.pm_dstate, - # apps_pm_xmt_pme=dut.apps_pm_xmt_pme, - # app_req_retry_en=dut.app_req_retry_en, - - # Interrupt interface - # app_int=dut.app_int, - # msi_pnd_func=dut.msi_pnd_func, - # msi_pnd_byte=dut.msi_pnd_byte, - # msi_pnd_addr=dut.msi_pnd_addr, - - # Error interface - # serr_out=dut.serr_out, - # hip_enter_err_mode=dut.hip_enter_err_mode, - # app_err_valid=dut.app_err_valid, - # app_err_hdr=dut.app_err_hdr, - # app_err_info=dut.app_err_info, - # app_err_func_num=dut.app_err_func_num, - - # Completion timeout interface - # cpl_timeout=dut.cpl_timeout, - # cpl_timeout_avmm_clk=dut.cpl_timeout_avmm_clk, - # cpl_timeout_avmm_address=dut.cpl_timeout_avmm_address, - # cpl_timeout_avmm_read=dut.cpl_timeout_avmm_read, - # cpl_timeout_avmm_readdata=dut.cpl_timeout_avmm_readdata, - # cpl_timeout_avmm_readdatavalid=dut.cpl_timeout_avmm_readdatavalid, - # cpl_timeout_avmm_write=dut.cpl_timeout_avmm_write, - # cpl_timeout_avmm_writedata=dut.cpl_timeout_avmm_writedata, - # cpl_timeout_avmm_waitrequest=dut.cpl_timeout_avmm_waitrequest, - - # Configuration output - tl_cfg_func=dut.tl_cfg_func, - tl_cfg_add=dut.tl_cfg_add, - tl_cfg_ctl=dut.tl_cfg_ctl, - # dl_timer_update=dut.dl_timer_update, - - # Configuration intercept interface - # cii_req=dut.cii_req, - # cii_hdr_poisoned=dut.cii_hdr_poisoned, - # cii_hdr_first_be=dut.cii_hdr_first_be, - # cii_func_num=dut.cii_func_num, - # cii_wr_vf_active=dut.cii_wr_vf_active, - # cii_vf_num=dut.cii_vf_num, - # cii_wr=dut.cii_wr, - # cii_addr=dut.cii_addr, - # cii_dout=dut.cii_dout, - # cii_override_en=dut.cii_override_en, - # cii_override_din=dut.cii_override_din, - # cii_halt=dut.cii_halt, - - # Hard IP reconfiguration interface - # hip_reconfig_clk=dut.hip_reconfig_clk, - # hip_reconfig_address=dut.hip_reconfig_address, - # hip_reconfig_read=dut.hip_reconfig_read, - # hip_reconfig_readdata=dut.hip_reconfig_readdata, - # hip_reconfig_readdatavalid=dut.hip_reconfig_readdatavalid, - # hip_reconfig_write=dut.hip_reconfig_write, - # hip_reconfig_writedata=dut.hip_reconfig_writedata, - # hip_reconfig_waitrequest=dut.hip_reconfig_waitrequest, - - # Page request service - # prs_event_valid=dut.prs_event_valid, - # prs_event_func=dut.prs_event_func, - # prs_event=dut.prs_event, - - # SR-IOV (VF error) - # vf_err_ur_posted_s0=dut.vf_err_ur_posted_s0, - # vf_err_ur_posted_s1=dut.vf_err_ur_posted_s1, - # vf_err_ur_posted_s2=dut.vf_err_ur_posted_s2, - # vf_err_ur_posted_s3=dut.vf_err_ur_posted_s3, - # vf_err_func_num_s0=dut.vf_err_func_num_s0, - # vf_err_func_num_s1=dut.vf_err_func_num_s1, - # vf_err_func_num_s2=dut.vf_err_func_num_s2, - # vf_err_func_num_s3=dut.vf_err_func_num_s3, - # vf_err_ca_postedreq_s0=dut.vf_err_ca_postedreq_s0, - # vf_err_ca_postedreq_s1=dut.vf_err_ca_postedreq_s1, - # vf_err_ca_postedreq_s2=dut.vf_err_ca_postedreq_s2, - # vf_err_ca_postedreq_s3=dut.vf_err_ca_postedreq_s3, - # vf_err_vf_num_s0=dut.vf_err_vf_num_s0, - # vf_err_vf_num_s1=dut.vf_err_vf_num_s1, - # vf_err_vf_num_s2=dut.vf_err_vf_num_s2, - # vf_err_vf_num_s3=dut.vf_err_vf_num_s3, - # vf_err_poisonedwrreq_s0=dut.vf_err_poisonedwrreq_s0, - # vf_err_poisonedwrreq_s1=dut.vf_err_poisonedwrreq_s1, - # vf_err_poisonedwrreq_s2=dut.vf_err_poisonedwrreq_s2, - # vf_err_poisonedwrreq_s3=dut.vf_err_poisonedwrreq_s3, - # vf_err_poisonedcompl_s0=dut.vf_err_poisonedcompl_s0, - # vf_err_poisonedcompl_s1=dut.vf_err_poisonedcompl_s1, - # vf_err_poisonedcompl_s2=dut.vf_err_poisonedcompl_s2, - # vf_err_poisonedcompl_s3=dut.vf_err_poisonedcompl_s3, - # user_vfnonfatalmsg_func_num=dut.user_vfnonfatalmsg_func_num, - # user_vfnonfatalmsg_vfnum=dut.user_vfnonfatalmsg_vfnum, - # user_sent_vfnonfatalmsg=dut.user_sent_vfnonfatalmsg, - # vf_err_overflow=dut.vf_err_overflow, - - # FLR - # flr_rcvd_pf=dut.flr_rcvd_pf, - # flr_rcvd_vf=dut.flr_rcvd_vf, - # flr_rcvd_pf_num=dut.flr_rcvd_pf_num, - # flr_rcvd_vf_num=dut.flr_rcvd_vf_num, - # flr_completed_pf=dut.flr_completed_pf, - # flr_completed_vf=dut.flr_completed_vf, - # flr_completed_pf_num=dut.flr_completed_pf_num, - # flr_completed_vf_num=dut.flr_completed_vf_num, - - # VirtIO - # virtio_pcicfg_vfaccess=dut.virtio_pcicfg_vfaccess, - # virtio_pcicfg_vfnum=dut.virtio_pcicfg_vfnum, - # virtio_pcicfg_pfnum=dut.virtio_pcicfg_pfnum, - # virtio_pcicfg_bar=dut.virtio_pcicfg_bar, - # virtio_pcicfg_length=dut.virtio_pcicfg_length, - # virtio_pcicfg_baroffset=dut.virtio_pcicfg_baroffset, - # virtio_pcicfg_cfgdata=dut.virtio_pcicfg_cfgdata, - # virtio_pcicfg_cfgwr=dut.virtio_pcicfg_cfgwr, - # virtio_pcicfg_cfgrd=dut.virtio_pcicfg_cfgrd, - # virtio_pcicfg_appvfnum=dut.virtio_pcicfg_appvfnum, - # virtio_pcicfg_apppfnum=dut.virtio_pcicfg_apppfnum, - # virtio_pcicfg_rdack=dut.virtio_pcicfg_rdack, - # virtio_pcicfg_rdbe=dut.virtio_pcicfg_rdbe, - # virtio_pcicfg_data=dut.virtio_pcicfg_data, - ) - - # self.dev.log.setLevel(logging.DEBUG) - - self.rc.make_port().connect(self.dev) - - self.driver = mqnic.Driver() - - self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) - if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): - self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) - - cocotb.start_soon(Clock(dut.ptp_clk, 4.964, units="ns").start()) - dut.ptp_rst.setimmediatevalue(0) - cocotb.start_soon(Clock(dut.ptp_sample_clk, 10, units="ns").start()) - - # Ethernet - self.qsfp_mac = [] - - for x in range(1, 3): - macs = [] - for y in range(1, 5): - cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_mac_{y}_rx_clk"), 2.482, units="ns").start()) - cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_mac_{y}_tx_clk"), 2.482, units="ns").start()) - - mac = EthMac( - tx_clk=getattr(dut, f"qsfp{x}_mac_{y}_tx_clk"), - tx_rst=getattr(dut, f"qsfp{x}_mac_{y}_tx_rst"), - tx_bus=AxiStreamBus.from_prefix(dut, f"qsfp{x}_mac_{y}_tx_axis"), - tx_ptp_time=getattr(dut, f"qsfp{x}_mac_{y}_tx_ptp_time"), - tx_ptp_ts=getattr(dut, f"qsfp{x}_mac_{y}_tx_ptp_ts"), - tx_ptp_ts_tag=getattr(dut, f"qsfp{x}_mac_{y}_tx_ptp_ts_tag"), - tx_ptp_ts_valid=getattr(dut, f"qsfp{x}_mac_{y}_tx_ptp_ts_valid"), - rx_clk=getattr(dut, f"qsfp{x}_mac_{y}_rx_clk"), - rx_rst=getattr(dut, f"qsfp{x}_mac_{y}_rx_rst"), - rx_bus=AxiStreamBus.from_prefix(dut, f"qsfp{x}_mac_{y}_rx_axis"), - rx_ptp_time=getattr(dut, f"qsfp{x}_mac_{y}_rx_ptp_time"), - ifg=12, speed=25e9 - ) - - macs.append(mac) - - getattr(dut, f"qsfp{x}_mac_{y}_rx_status").setimmediatevalue(1) - getattr(dut, f"qsfp{x}_mac_{y}_rx_lfc_req").setimmediatevalue(0) - getattr(dut, f"qsfp{x}_mac_{y}_rx_pfc_req").setimmediatevalue(0) - - self.qsfp_mac.append(macs) - - dut.user_pb.setimmediatevalue(0) - - dut.i2c2_scl_i.setimmediatevalue(1) - dut.i2c2_sda_i.setimmediatevalue(1) - - self.loopback_enable = False - cocotb.start_soon(self._run_loopback()) - - async def init(self): - - self.dut.ptp_rst.setimmediatevalue(0) - for x in range(1, 3): - for y in range(1, 5): - getattr(self.dut, f"qsfp{x}_mac_{y}_rx_rst").setimmediatevalue(0) - getattr(self.dut, f"qsfp{x}_mac_{y}_tx_rst").setimmediatevalue(0) - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.ptp_rst.setimmediatevalue(1) - for x in range(1, 3): - for y in range(1, 5): - getattr(self.dut, f"qsfp{x}_mac_{y}_rx_rst").setimmediatevalue(1) - getattr(self.dut, f"qsfp{x}_mac_{y}_tx_rst").setimmediatevalue(1) - - await FallingEdge(self.dut.rst_250mhz) - await Timer(100, 'ns') - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.ptp_rst.setimmediatevalue(0) - for x in range(1, 3): - for y in range(1, 5): - getattr(self.dut, f"qsfp{x}_mac_{y}_rx_rst").setimmediatevalue(0) - getattr(self.dut, f"qsfp{x}_mac_{y}_tx_rst").setimmediatevalue(0) - - await self.rc.enumerate() - - async def _run_loopback(self): - while True: - await RisingEdge(self.dut.clk_250mhz) - - if self.loopback_enable: - for macs in self.qsfp_mac: - for mac in macs: - if not mac.tx.empty(): - await mac.rx.send(await mac.tx.recv()) - - -@cocotb.test() -async def run_test_nic(dut): - - tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index)) - - await tb.init() - - tb.log.info("Init driver") - await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id)) - await tb.driver.interfaces[0].open() - # await tb.driver.interfaces[1].open() - - # enable queues - tb.log.info("Enable queues") - await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) - for k in range(len(tb.driver.interfaces[0].txq)): - await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003) - - # wait for all writes to complete - await tb.driver.hw_regs.read_dword(0) - tb.log.info("Init complete") - - tb.log.info("Send and receive single packet") - - data = bytearray([x % 256 for x in range(1024)]) - - await tb.driver.interfaces[0].start_xmit(data, 0) - - pkt = await tb.qsfp_mac[0][0].tx.recv() - tb.log.info("Packet: %s", pkt) - - await tb.qsfp_mac[0][0].rx.send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - # await tb.driver.interfaces[1].start_xmit(data, 0) - - # pkt = await tb.qsfp_mac[1][0].tx.recv() - # tb.log.info("Packet: %s", pkt) - - # await tb.qsfp_mac[1][0].rx.send(pkt) - - # pkt = await tb.driver.interfaces[1].recv() - - # tb.log.info("Packet: %s", pkt) - # assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.log.info("RX and TX checksum tests") - - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') - ip = IP(src='192.168.1.100', dst='192.168.1.101') - udp = UDP(sport=1, dport=2) - test_pkt = eth / ip / udp / payload - - test_pkt2 = test_pkt.copy() - test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) - - await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - - pkt = await tb.qsfp_mac[0][0].tx.recv() - tb.log.info("Packet: %s", pkt) - - await tb.qsfp_mac[0][0].rx.send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - assert Ether(pkt.data).build() == test_pkt.build() - - tb.log.info("Queue mapping offset test") - - data = bytearray([x % 256 for x in range(1024)]) - - tb.loopback_enable = True - - for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) - - await tb.driver.interfaces[0].start_xmit(data, 0) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - assert pkt.queue == k - - tb.loopback_enable = False - - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) - - tb.log.info("Queue mapping RSS mask test") - - await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) - - for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) - - tb.loopback_enable = True - - queues = set() - - for k in range(64): - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') - ip = IP(src='192.168.1.100', dst='192.168.1.101') - udp = UDP(sport=1, dport=k+0) - test_pkt = eth / ip / udp / payload - - test_pkt2 = test_pkt.copy() - test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) - - await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - - for k in range(64): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - queues.add(pkt.queue) - - assert len(queues) == 4 - - tb.loopback_enable = False - - await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0) - - tb.log.info("Multiple small packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - tb.log.info("Multiple large packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - await RisingEdge(dut.clk_250mhz) - await RisingEdge(dut.clk_250mhz) - - -# cocotb-test - -tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) -app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app')) -axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl')) -axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) -eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) -pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl')) - - -def test_fpga_core(request): - dut = "fpga_core" - module = os.path.splitext(os.path.basename(__file__))[0] - toplevel = dut - - verilog_sources = [ - os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie_ptile.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), - os.path.join(rtl_dir, "common", "mqnic_core.v"), - os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), - os.path.join(rtl_dir, "common", "mqnic_port_tx.v"), - os.path.join(rtl_dir, "common", "mqnic_port_rx.v"), - os.path.join(rtl_dir, "common", "mqnic_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), - os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), - os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"), - os.path.join(rtl_dir, "common", "cpl_write.v"), - os.path.join(rtl_dir, "common", "cpl_op_mux.v"), - os.path.join(rtl_dir, "common", "desc_fetch.v"), - os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "queue_manager.v"), - os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), - os.path.join(rtl_dir, "common", "tx_fifo.v"), - os.path.join(rtl_dir, "common", "rx_fifo.v"), - os.path.join(rtl_dir, "common", "tx_req_mux.v"), - os.path.join(rtl_dir, "common", "tx_engine.v"), - os.path.join(rtl_dir, "common", "rx_engine.v"), - os.path.join(rtl_dir, "common", "tx_checksum.v"), - os.path.join(rtl_dir, "common", "rx_hash.v"), - os.path.join(rtl_dir, "common", "rx_checksum.v"), - os.path.join(rtl_dir, "common", "stats_counter.v"), - os.path.join(rtl_dir, "common", "stats_collect.v"), - os.path.join(rtl_dir, "common", "stats_pcie_if.v"), - os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"), - os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"), - os.path.join(rtl_dir, "common", "stats_dma_latency.v"), - os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), - os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(rtl_dir, "common", "tdma_scheduler.v"), - os.path.join(rtl_dir, "common", "tdma_ber.v"), - os.path.join(rtl_dir, "common", "tdma_ber_ch.v"), - os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_td_phc.v"), - os.path.join(eth_rtl_dir, "ptp_td_leaf.v"), - os.path.join(eth_rtl_dir, "ptp_perout.v"), - os.path.join(axi_rtl_dir, "axil_interconnect.v"), - os.path.join(axi_rtl_dir, "axil_crossbar.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"), - os.path.join(axi_rtl_dir, "axil_reg_if.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"), - os.path.join(axi_rtl_dir, "axil_register_rd.v"), - os.path.join(axi_rtl_dir, "axil_register_wr.v"), - os.path.join(axi_rtl_dir, "arbiter.v"), - os.path.join(axi_rtl_dir, "priority_encoder.v"), - os.path.join(axis_rtl_dir, "axis_adapter.v"), - os.path.join(axis_rtl_dir, "axis_arb_mux.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_demux.v"), - os.path.join(axis_rtl_dir, "axis_fifo.v"), - os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), - os.path.join(axis_rtl_dir, "axis_register.v"), - os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fc_count.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_mux.v"), - os.path.join(pcie_rtl_dir, "pcie_msix.v"), - os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_psdpram.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"), - os.path.join(pcie_rtl_dir, "pcie_ptile_if.v"), - os.path.join(pcie_rtl_dir, "pcie_ptile_if_rx.v"), - os.path.join(pcie_rtl_dir, "pcie_ptile_if_tx.v"), - os.path.join(pcie_rtl_dir, "pcie_ptile_cfg.v"), - os.path.join(pcie_rtl_dir, "pcie_ptile_fc_counter.v"), - os.path.join(pcie_rtl_dir, "pulse_merge.v"), - ] - - parameters = {} - - # Structural configuration - parameters['IF_COUNT'] = 2 - parameters['PORTS_PER_IF'] = 1 - parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] - parameters['PORT_MASK'] = 0 - - # Clock configuration - parameters['CLK_PERIOD_NS_NUM'] = 4 - parameters['CLK_PERIOD_NS_DENOM'] = 1 - - # PTP configuration - parameters['PTP_CLK_PERIOD_NS_NUM'] = 4096 - parameters['PTP_CLK_PERIOD_NS_DENOM'] = 825 - parameters['PTP_CLOCK_PIPELINE'] = 0 - parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_SEPARATE_TX_CLOCK'] = 0 - parameters['PTP_SEPARATE_RX_CLOCK'] = 0 - parameters['PTP_PORT_CDC_PIPELINE'] = 0 - parameters['PTP_PEROUT_ENABLE'] = 1 - parameters['PTP_PEROUT_COUNT'] = 1 - - # Queue manager configuration - parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['CQ_OP_TABLE_SIZE'] = 32 - parameters['EQN_WIDTH'] = 6 - parameters['TX_QUEUE_INDEX_WIDTH'] = 13 - parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 - parameters['EQ_PIPELINE'] = 3 - parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) - - # TX and RX engine configuration - parameters['TX_DESC_TABLE_SIZE'] = 32 - parameters['RX_DESC_TABLE_SIZE'] = 32 - parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) - - # Scheduler configuration - parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] - parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['TDMA_INDEX_WIDTH'] = 6 - - # Interface configuration - parameters['PTP_TS_ENABLE'] = 1 - parameters['TX_CPL_FIFO_DEPTH'] = 32 - parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_HASH_ENABLE'] = 1 - parameters['RX_CHECKSUM_ENABLE'] = 1 - parameters['LFC_ENABLE'] = 1 - parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] - parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 - parameters['MAX_TX_SIZE'] = 9214 - parameters['MAX_RX_SIZE'] = 9214 - parameters['TX_RAM_SIZE'] = 32768 - parameters['RX_RAM_SIZE'] = 32768 - - # Application block configuration - parameters['APP_ID'] = 0x00000000 - parameters['APP_ENABLE'] = 0 - parameters['APP_CTRL_ENABLE'] = 1 - parameters['APP_DMA_ENABLE'] = 1 - parameters['APP_AXIS_DIRECT_ENABLE'] = 1 - parameters['APP_AXIS_SYNC_ENABLE'] = 1 - parameters['APP_AXIS_IF_ENABLE'] = 1 - parameters['APP_STAT_ENABLE'] = 1 - - # DMA interface configuration - parameters['DMA_IMM_ENABLE'] = 0 - parameters['DMA_IMM_WIDTH'] = 32 - parameters['DMA_LEN_WIDTH'] = 16 - parameters['DMA_TAG_WIDTH'] = 16 - parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length() - parameters['RAM_PIPELINE'] = 2 - - # PCIe interface configuration - parameters['SEG_COUNT'] = 2 - parameters['SEG_DATA_WIDTH'] = 256 - parameters['PF_COUNT'] = 1 - parameters['VF_COUNT'] = 0 - - # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] - - # AXI lite interface configuration (control) - parameters['AXIL_CTRL_DATA_WIDTH'] = 32 - parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 - - # AXI lite interface configuration (application control) - parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH'] - parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24 - - # Ethernet interface configuration - parameters['AXIS_ETH_TX_PIPELINE'] = 0 - parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 2 - parameters['AXIS_ETH_TX_TS_PIPELINE'] = 0 - parameters['AXIS_ETH_RX_PIPELINE'] = 0 - parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 2 - - # Statistics counter subsystem - parameters['STAT_ENABLE'] = 1 - parameters['STAT_DMA_ENABLE'] = 1 - parameters['STAT_PCIE_ENABLE'] = 1 - parameters['STAT_INC_WIDTH'] = 24 - parameters['STAT_ID_WIDTH'] = 12 - - extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} - - sim_build = os.path.join(tests_dir, "sim_build", - request.node.name.replace('[', '-').replace(']', '')) - - cocotb_test.simulator.run( - python_search=[tests_dir], - verilog_sources=verilog_sources, - toplevel=toplevel, - module=module, - parameters=parameters, - sim_build=sim_build, - extra_env=extra_env, - )