From 0b16849b571eafd07be94659c73fef2f3ab62efb Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 4 Nov 2021 20:43:13 -0700 Subject: [PATCH] Add attributes to RAMs for proper synthesis in Quartus --- rtl/axi_dma_rd.v | 12 ++++++------ rtl/axi_dma_wr.v | 6 +++--- rtl/axi_fifo_rd.v | 1 + rtl/axi_fifo_wr.v | 1 + rtl/axil_crossbar_rd.v | 3 +++ rtl/axil_crossbar_wr.v | 3 +++ 6 files changed, 17 insertions(+), 9 deletions(-) diff --git a/rtl/axi_dma_rd.v b/rtl/axi_dma_rd.v index 710006d05..9e01f9b87 100644 --- a/rtl/axi_dma_rd.v +++ b/rtl/axi_dma_rd.v @@ -631,17 +631,17 @@ reg out_fifo_half_full_reg = 1'b0; wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}}); wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg; -(* ram_style = "distributed" *) +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [AXIS_DATA_WIDTH-1:0] out_fifo_tdata[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; -(* ram_style = "distributed" *) +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [AXIS_KEEP_WIDTH-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; -(* ram_style = "distributed" *) +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg out_fifo_tlast[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; -(* ram_style = "distributed" *) +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [AXIS_ID_WIDTH-1:0] out_fifo_tid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; -(* ram_style = "distributed" *) +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [AXIS_DEST_WIDTH-1:0] out_fifo_tdest[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; -(* ram_style = "distributed" *) +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [AXIS_USER_WIDTH-1:0] out_fifo_tuser[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; assign m_axis_read_data_tready_int = !out_fifo_half_full_reg; diff --git a/rtl/axi_dma_wr.v b/rtl/axi_dma_wr.v index 119199a22..672910c68 100644 --- a/rtl/axi_dma_wr.v +++ b/rtl/axi_dma_wr.v @@ -896,11 +896,11 @@ reg out_fifo_half_full_reg = 1'b0; wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}}); wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg; -(* ram_style = "distributed" *) +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [AXI_DATA_WIDTH-1:0] out_fifo_wdata[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; -(* ram_style = "distributed" *) +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [AXI_STRB_WIDTH-1:0] out_fifo_wstrb[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; -(* ram_style = "distributed" *) +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg out_fifo_wlast[2**OUTPUT_FIFO_ADDR_WIDTH-1:0]; assign m_axi_wready_int = !out_fifo_half_full_reg; diff --git a/rtl/axi_fifo_rd.v b/rtl/axi_fifo_rd.v index fe3bad3b2..8037faa52 100644 --- a/rtl/axi_fifo_rd.v +++ b/rtl/axi_fifo_rd.v @@ -120,6 +120,7 @@ reg [FIFO_ADDR_WIDTH:0] wr_addr_reg = {FIFO_ADDR_WIDTH+1{1'b0}}; reg [FIFO_ADDR_WIDTH:0] rd_ptr_reg = {FIFO_ADDR_WIDTH+1{1'b0}}, rd_ptr_next; reg [FIFO_ADDR_WIDTH:0] rd_addr_reg = {FIFO_ADDR_WIDTH+1{1'b0}}; +(* ramstyle = "no_rw_check" *) reg [RWIDTH-1:0] mem[(2**FIFO_ADDR_WIDTH)-1:0]; reg [RWIDTH-1:0] mem_read_data_reg; reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next; diff --git a/rtl/axi_fifo_wr.v b/rtl/axi_fifo_wr.v index 8a4ff8418..668d45e4c 100644 --- a/rtl/axi_fifo_wr.v +++ b/rtl/axi_fifo_wr.v @@ -131,6 +131,7 @@ reg [FIFO_ADDR_WIDTH:0] wr_addr_reg = {FIFO_ADDR_WIDTH+1{1'b0}}; reg [FIFO_ADDR_WIDTH:0] rd_ptr_reg = {FIFO_ADDR_WIDTH+1{1'b0}}, rd_ptr_next; reg [FIFO_ADDR_WIDTH:0] rd_addr_reg = {FIFO_ADDR_WIDTH+1{1'b0}}; +(* ramstyle = "no_rw_check" *) reg [WWIDTH-1:0] mem[(2**FIFO_ADDR_WIDTH)-1:0]; reg [WWIDTH-1:0] mem_read_data_reg; reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next; diff --git a/rtl/axil_crossbar_rd.v b/rtl/axil_crossbar_rd.v index b7d93cf24..3586839c4 100644 --- a/rtl/axil_crossbar_rd.v +++ b/rtl/axil_crossbar_rd.v @@ -150,7 +150,9 @@ generate reg [FIFO_ADDR_WIDTH+1-1:0] fifo_wr_ptr_reg = 0; reg [FIFO_ADDR_WIDTH+1-1:0] fifo_rd_ptr_reg = 0; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [CL_M_COUNT-1:0] fifo_select[(2**FIFO_ADDR_WIDTH)-1:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg fifo_decerr[(2**FIFO_ADDR_WIDTH)-1:0]; wire [CL_M_COUNT-1:0] fifo_wr_select; wire fifo_wr_decerr; @@ -307,6 +309,7 @@ generate reg [FIFO_ADDR_WIDTH+1-1:0] fifo_wr_ptr_reg = 0; reg [FIFO_ADDR_WIDTH+1-1:0] fifo_rd_ptr_reg = 0; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [CL_S_COUNT-1:0] fifo_select[(2**FIFO_ADDR_WIDTH)-1:0]; wire [CL_S_COUNT-1:0] fifo_wr_select; wire fifo_wr_en; diff --git a/rtl/axil_crossbar_wr.v b/rtl/axil_crossbar_wr.v index d7f8a8dc6..db08a7b7e 100644 --- a/rtl/axil_crossbar_wr.v +++ b/rtl/axil_crossbar_wr.v @@ -169,7 +169,9 @@ generate reg [FIFO_ADDR_WIDTH+1-1:0] fifo_wr_ptr_reg = 0; reg [FIFO_ADDR_WIDTH+1-1:0] fifo_rd_ptr_reg = 0; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [CL_M_COUNT-1:0] fifo_select[(2**FIFO_ADDR_WIDTH)-1:0]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg fifo_decerr[(2**FIFO_ADDR_WIDTH)-1:0]; wire [CL_M_COUNT-1:0] fifo_wr_select; wire fifo_wr_decerr; @@ -371,6 +373,7 @@ generate reg [FIFO_ADDR_WIDTH+1-1:0] fifo_wr_ptr_reg = 0; reg [FIFO_ADDR_WIDTH+1-1:0] fifo_rd_ptr_reg = 0; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [CL_S_COUNT-1:0] fifo_select[(2**FIFO_ADDR_WIDTH)-1:0]; wire [CL_S_COUNT-1:0] fifo_wr_select; wire fifo_wr_en;