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Code Issues Projects Releases Wiki Activity

Use new PCIe DMA modules

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This commit is contained in:
Alex Forencich 2021-08-04 01:20:57 -07:00
parent 038772b175
commit 0b65a1271a
126 changed files with 8673 additions and 4928 deletions
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13
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile
View File

@ -38,10 +38,15 @@ SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

7
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/placement.xdc
View File

@ -1,8 +1,7 @@
# Placement constraints
create_pblock pblock_pcie
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list pcie4_uscale_plus_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_msi_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_cfg_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_axil_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_us_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_if_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_axi_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_inst]]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y4}

503
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
View File

@ -742,49 +742,106 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(4),
.PCIE_CAP_OFFSET(12'h070)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
pcie_us_axil_master #(
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -796,7 +853,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -805,6 +862,163 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -832,7 +1046,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -841,140 +1054,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
// ila_0 ila_desc (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0({pcie_dma_read_desc_pcie_addr, pcie_dma_read_desc_ram_sel, pcie_dma_read_desc_ram_addr, pcie_dma_read_desc_tag, pcie_dma_read_desc_status_tag, pcie_dma_write_desc_pcie_addr, pcie_dma_write_desc_ram_sel, pcie_dma_write_desc_ram_addr, pcie_dma_write_desc_tag, pcie_dma_write_desc_status_tag}),
// .probe1(0),
// .probe2(0),
// .probe3(0),
// .probe4({pcie_dma_read_desc_valid, pcie_dma_read_desc_ready, pcie_dma_read_desc_len, pcie_dma_read_desc_status_valid, pcie_dma_write_desc_valid, pcie_dma_write_desc_ready, pcie_dma_write_desc_len, pcie_dma_write_desc_status_valid, status_error_cor_int, status_error_uncor_int}),
// .probe5(0)
// );
// ila_0 ila_rq (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0(m_axis_rq_tdata),
// .probe1(m_axis_rq_tkeep),
// .probe2(m_axis_rq_tvalid),
// .probe3(m_axis_rq_tready),
// .probe4(m_axis_rq_tuser),
// .probe5(m_axis_rq_tlast)
// );
// ila_0 ila_rc (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0(axis_rc_tdata_r),
// .probe1(axis_rc_tkeep_r),
// .probe2(axis_rc_tvalid_r),
// .probe3(axis_rc_tready_r),
// .probe4({axis_rc_tuser_r, dma_if_pcie_us_inst.dma_if_pcie_us_rd_inst.req_state_reg, dma_if_pcie_us_inst.dma_if_pcie_us_rd_inst.tlp_state_reg, dma_if_pcie_us_inst.dma_if_pcie_us_rd_inst.ram_mask_reg}),
// .probe5(axis_rc_tlast_r)
// );
// ila_0 ila_mem (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0({dma_ram_wr_cmd_valid, dma_ram_wr_cmd_ready, dma_ram_wr_cmd_sel, if_dma_ram_wr_cmd_valid, if_dma_ram_wr_cmd_ready, if_dma_ram_wr_cmd_sel, iface[0].interface_inst.desc_dma_ram_wr_cmd_valid, iface[0].interface_inst.desc_dma_ram_wr_cmd_ready, iface[0].interface_inst.port_dma_ram_wr_cmd_valid, iface[0].interface_inst.port_dma_ram_wr_cmd_ready}),
// .probe1(0),
// .probe2(0),
// .probe3(0),
// .probe4(0),
// .probe5(0)
// );
// ila_0 ila_w (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0(axi_pcie_dma_wdata),
// .probe1(0),
// .probe2(axi_pcie_dma_wvalid),
// .probe3(axi_pcie_dma_wready),
// .probe4({axi_pcie_dma_wstrb, axi_pcie_dma_awaddr, axi_pcie_dma_awid, axi_pcie_dma_awlen, axi_pcie_dma_awvalid, axi_pcie_dma_awready, dbg}),
// .probe5(axi_pcie_dma_wlast)
// );
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -986,39 +1082,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(16),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -1088,7 +1198,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1125,34 +1234,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
View File

@ -70,10 +70,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -547,10 +547,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile
View File

@ -55,10 +55,15 @@ SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

7
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/placement.xdc
View File

@ -1,8 +1,7 @@
# Placement constraints
create_pblock pblock_pcie
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list pcie4_uscale_plus_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_msi_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_cfg_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_axil_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_us_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_if_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_axi_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_inst]]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y4}

503
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v
View File

@ -805,49 +805,106 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(4),
.PCIE_CAP_OFFSET(12'h070)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
pcie_us_axil_master #(
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -859,7 +916,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -868,6 +925,163 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -895,7 +1109,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -904,140 +1117,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
// ila_0 ila_desc (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0({pcie_dma_read_desc_pcie_addr, pcie_dma_read_desc_ram_sel, pcie_dma_read_desc_ram_addr, pcie_dma_read_desc_tag, pcie_dma_read_desc_status_tag, pcie_dma_write_desc_pcie_addr, pcie_dma_write_desc_ram_sel, pcie_dma_write_desc_ram_addr, pcie_dma_write_desc_tag, pcie_dma_write_desc_status_tag}),
// .probe1(0),
// .probe2(0),
// .probe3(0),
// .probe4({pcie_dma_read_desc_valid, pcie_dma_read_desc_ready, pcie_dma_read_desc_len, pcie_dma_read_desc_status_valid, pcie_dma_write_desc_valid, pcie_dma_write_desc_ready, pcie_dma_write_desc_len, pcie_dma_write_desc_status_valid, status_error_cor_int, status_error_uncor_int}),
// .probe5(0)
// );
// ila_0 ila_rq (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0(m_axis_rq_tdata),
// .probe1(m_axis_rq_tkeep),
// .probe2(m_axis_rq_tvalid),
// .probe3(m_axis_rq_tready),
// .probe4(m_axis_rq_tuser),
// .probe5(m_axis_rq_tlast)
// );
// ila_0 ila_rc (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0(axis_rc_tdata_r),
// .probe1(axis_rc_tkeep_r),
// .probe2(axis_rc_tvalid_r),
// .probe3(axis_rc_tready_r),
// .probe4({axis_rc_tuser_r, dma_if_pcie_us_inst.dma_if_pcie_us_rd_inst.req_state_reg, dma_if_pcie_us_inst.dma_if_pcie_us_rd_inst.tlp_state_reg, dma_if_pcie_us_inst.dma_if_pcie_us_rd_inst.ram_mask_reg}),
// .probe5(axis_rc_tlast_r)
// );
// ila_0 ila_mem (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0({dma_ram_wr_cmd_valid, dma_ram_wr_cmd_ready, dma_ram_wr_cmd_sel, if_dma_ram_wr_cmd_valid, if_dma_ram_wr_cmd_ready, if_dma_ram_wr_cmd_sel, iface[0].interface_inst.desc_dma_ram_wr_cmd_valid, iface[0].interface_inst.desc_dma_ram_wr_cmd_ready, iface[0].interface_inst.port_dma_ram_wr_cmd_valid, iface[0].interface_inst.port_dma_ram_wr_cmd_ready}),
// .probe1(0),
// .probe2(0),
// .probe3(0),
// .probe4(0),
// .probe5(0)
// );
// ila_0 ila_w (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0(axi_pcie_dma_wdata),
// .probe1(0),
// .probe2(axi_pcie_dma_wvalid),
// .probe3(axi_pcie_dma_wready),
// .probe4({axi_pcie_dma_wstrb, axi_pcie_dma_awaddr, axi_pcie_dma_awid, axi_pcie_dma_awlen, axi_pcie_dma_awvalid, axi_pcie_dma_awready, dbg}),
// .probe5(axi_pcie_dma_wlast)
// );
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -1049,39 +1145,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(16),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -1151,7 +1261,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1188,34 +1297,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/Makefile
View File

@ -75,10 +75,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -596,10 +596,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
View File

@ -55,10 +55,15 @@ SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

7
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/placement.xdc
View File

@ -1,8 +1,7 @@
# Placement constraints
create_pblock pblock_pcie
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list pcie4_uscale_plus_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_msi_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_cfg_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_axil_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_us_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_if_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_axi_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_inst]]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y4}

504
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -805,49 +805,107 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(4),
.PCIE_CAP_OFFSET(12'h070)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
pcie_us_axil_master #(
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -859,7 +917,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -868,6 +926,163 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -895,7 +1110,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -904,140 +1118,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
// ila_0 ila_desc (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0({pcie_dma_read_desc_pcie_addr, pcie_dma_read_desc_ram_sel, pcie_dma_read_desc_ram_addr, pcie_dma_read_desc_tag, pcie_dma_read_desc_status_tag, pcie_dma_write_desc_pcie_addr, pcie_dma_write_desc_ram_sel, pcie_dma_write_desc_ram_addr, pcie_dma_write_desc_tag, pcie_dma_write_desc_status_tag}),
// .probe1(0),
// .probe2(0),
// .probe3(0),
// .probe4({pcie_dma_read_desc_valid, pcie_dma_read_desc_ready, pcie_dma_read_desc_len, pcie_dma_read_desc_status_valid, pcie_dma_write_desc_valid, pcie_dma_write_desc_ready, pcie_dma_write_desc_len, pcie_dma_write_desc_status_valid, status_error_cor_int, status_error_uncor_int}),
// .probe5(0)
// );
// ila_0 ila_rq (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0(m_axis_rq_tdata),
// .probe1(m_axis_rq_tkeep),
// .probe2(m_axis_rq_tvalid),
// .probe3(m_axis_rq_tready),
// .probe4(m_axis_rq_tuser),
// .probe5(m_axis_rq_tlast)
// );
// ila_0 ila_rc (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0(axis_rc_tdata_r),
// .probe1(axis_rc_tkeep_r),
// .probe2(axis_rc_tvalid_r),
// .probe3(axis_rc_tready_r),
// .probe4({axis_rc_tuser_r, dma_if_pcie_us_inst.dma_if_pcie_us_rd_inst.req_state_reg, dma_if_pcie_us_inst.dma_if_pcie_us_rd_inst.tlp_state_reg, dma_if_pcie_us_inst.dma_if_pcie_us_rd_inst.ram_mask_reg}),
// .probe5(axis_rc_tlast_r)
// );
// ila_0 ila_mem (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0({dma_ram_wr_cmd_valid, dma_ram_wr_cmd_ready, dma_ram_wr_cmd_sel, if_dma_ram_wr_cmd_valid, if_dma_ram_wr_cmd_ready, if_dma_ram_wr_cmd_sel, iface[0].interface_inst.desc_dma_ram_wr_cmd_valid, iface[0].interface_inst.desc_dma_ram_wr_cmd_ready, iface[0].interface_inst.port_dma_ram_wr_cmd_valid, iface[0].interface_inst.port_dma_ram_wr_cmd_ready}),
// .probe1(0),
// .probe2(0),
// .probe3(0),
// .probe4(0),
// .probe5(0)
// );
// ila_0 ila_w (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0(axi_pcie_dma_wdata),
// .probe1(0),
// .probe2(axi_pcie_dma_wvalid),
// .probe3(axi_pcie_dma_wready),
// .probe4({axi_pcie_dma_wstrb, axi_pcie_dma_awaddr, axi_pcie_dma_awid, axi_pcie_dma_awlen, axi_pcie_dma_awvalid, axi_pcie_dma_awready, dbg}),
// .probe5(axi_pcie_dma_wlast)
// );
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -1049,39 +1146,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(16),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -1151,7 +1262,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1188,34 +1298,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
View File

@ -75,10 +75,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -596,10 +596,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/AU200/fpga_100g/fpga/Makefile
View File

@ -41,10 +41,15 @@ SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/axis_pipeline_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

7
fpga/mqnic/AU200/fpga_100g/placement.xdc
View File

@ -17,10 +17,9 @@ resize_pblock [get_pblocks pblock_slr1] -add {SLR1}
create_pblock pblock_pcie
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list pcie4_uscale_plus_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_msi_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_cfg_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_axil_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_us_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_if_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_axi_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_inst]]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}
create_pblock pblock_eth

479
fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
View File

@ -756,49 +756,106 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(4),
.PCIE_CAP_OFFSET(12'h070)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
pcie_us_axil_master #(
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -810,7 +867,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -819,6 +876,163 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -846,7 +1060,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -855,116 +1068,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep_r;
wire axis_rq_tlast_r;
wire axis_rq_tready_r;
wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser_r;
wire axis_rq_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH)
)
rq_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(axis_rq_tdata_r),
.s_axis_tkeep(axis_rq_tkeep_r),
.s_axis_tvalid(axis_rq_tvalid_r),
.s_axis_tready(axis_rq_tready_r),
.s_axis_tlast(axis_rq_tlast_r),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(axis_rq_tuser_r),
/*
* AXI output
*/
.m_axis_tdata(m_axis_rq_tdata),
.m_axis_tkeep(m_axis_rq_tkeep),
.m_axis_tvalid(m_axis_rq_tvalid),
.m_axis_tready(m_axis_rq_tready),
.m_axis_tlast(m_axis_rq_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(m_axis_rq_tuser)
);
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -976,39 +1096,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(16),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(axis_rq_tdata_r),
.m_axis_rq_tkeep(axis_rq_tkeep_r),
.m_axis_rq_tvalid(axis_rq_tvalid_r),
.m_axis_rq_tready(axis_rq_tready_r),
.m_axis_rq_tlast(axis_rq_tlast_r),
.m_axis_rq_tuser(axis_rq_tuser_r),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -1078,7 +1212,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1115,34 +1248,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
View File

@ -71,10 +71,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -548,10 +548,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/AU200/fpga_10g/fpga/Makefile
View File

@ -56,10 +56,15 @@ SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

7
fpga/mqnic/AU200/fpga_10g/placement.xdc
View File

@ -17,8 +17,7 @@ resize_pblock [get_pblocks pblock_slr1] -add {SLR1}
create_pblock pblock_pcie
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list pcie4_uscale_plus_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_msi_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_cfg_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_axil_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_us_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_if_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_axi_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_inst]]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}

433
fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v
View File

@ -816,49 +816,106 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(4),
.PCIE_CAP_OFFSET(12'h070)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
pcie_us_axil_master #(
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -870,7 +927,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -879,6 +936,163 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -906,7 +1120,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -915,70 +1128,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -990,39 +1156,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(16),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -1092,7 +1272,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1129,34 +1308,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/AU200/fpga_10g/tb/fpga_core/Makefile
View File

@ -75,10 +75,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/AU200/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -596,10 +596,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/AU250/fpga_100g/fpga/Makefile
View File

@ -41,10 +41,15 @@ SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_pipeline_register.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

7
fpga/mqnic/AU250/fpga_100g/placement.xdc
View File

@ -21,10 +21,9 @@ resize_pblock [get_pblocks pblock_slr1] -add {SLR1}
create_pblock pblock_pcie
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list pcie4_uscale_plus_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_msi_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_cfg_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_axil_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_us_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_if_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_axi_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_inst]]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y4:CLOCKREGION_X7Y7}
create_pblock pblock_eth

479
fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
View File

@ -756,49 +756,106 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(4),
.PCIE_CAP_OFFSET(12'h070)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
pcie_us_axil_master #(
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -810,7 +867,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -819,6 +876,163 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -846,7 +1060,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -855,116 +1068,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep_r;
wire axis_rq_tlast_r;
wire axis_rq_tready_r;
wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser_r;
wire axis_rq_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH)
)
rq_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(axis_rq_tdata_r),
.s_axis_tkeep(axis_rq_tkeep_r),
.s_axis_tvalid(axis_rq_tvalid_r),
.s_axis_tready(axis_rq_tready_r),
.s_axis_tlast(axis_rq_tlast_r),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(axis_rq_tuser_r),
/*
* AXI output
*/
.m_axis_tdata(m_axis_rq_tdata),
.m_axis_tkeep(m_axis_rq_tkeep),
.m_axis_tvalid(m_axis_rq_tvalid),
.m_axis_tready(m_axis_rq_tready),
.m_axis_tlast(m_axis_rq_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(m_axis_rq_tuser)
);
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -976,39 +1096,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(16),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(axis_rq_tdata_r),
.m_axis_rq_tkeep(axis_rq_tkeep_r),
.m_axis_rq_tvalid(axis_rq_tvalid_r),
.m_axis_rq_tready(axis_rq_tready_r),
.m_axis_rq_tlast(axis_rq_tlast_r),
.m_axis_rq_tuser(axis_rq_tuser_r),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -1078,7 +1212,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1115,34 +1248,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
View File

@ -71,10 +71,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -548,10 +548,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/AU250/fpga_10g/fpga/Makefile
View File

@ -56,10 +56,15 @@ SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

7
fpga/mqnic/AU250/fpga_10g/placement.xdc
View File

@ -21,8 +21,7 @@ resize_pblock [get_pblocks pblock_slr1] -add {SLR1}
create_pblock pblock_pcie
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list pcie4_uscale_plus_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_msi_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_cfg_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_axil_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_us_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_if_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_axi_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_inst]]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y4:CLOCKREGION_X7Y7}

433
fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v
View File

@ -816,49 +816,106 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(4),
.PCIE_CAP_OFFSET(12'h070)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
pcie_us_axil_master #(
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -870,7 +927,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -879,6 +936,163 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -906,7 +1120,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -915,70 +1128,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -990,39 +1156,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(16),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -1092,7 +1272,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1129,34 +1308,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/AU250/fpga_10g/tb/fpga_core/Makefile
View File

@ -75,10 +75,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/AU250/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -596,10 +596,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/AU280/fpga_100g/fpga/Makefile
View File

@ -40,10 +40,15 @@ SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_pipeline_register.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

7
fpga/mqnic/AU280/fpga_100g/placement.xdc
View File

@ -17,10 +17,9 @@ resize_pblock [get_pblocks pblock_slr0] -add {SLR0}
create_pblock pblock_pcie
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list pcie4c_uscale_plus_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_msi_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_cfg_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_axil_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_us_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_if_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_axi_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_inst]]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y0:CLOCKREGION_X7Y3}
create_pblock pblock_eth

479
fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
View File

@ -667,49 +667,106 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(4),
.PCIE_CAP_OFFSET(12'h070)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
pcie_us_axil_master #(
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -721,7 +778,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -730,6 +787,163 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -757,7 +971,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -766,116 +979,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep_r;
wire axis_rq_tlast_r;
wire axis_rq_tready_r;
wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser_r;
wire axis_rq_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH)
)
rq_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(axis_rq_tdata_r),
.s_axis_tkeep(axis_rq_tkeep_r),
.s_axis_tvalid(axis_rq_tvalid_r),
.s_axis_tready(axis_rq_tready_r),
.s_axis_tlast(axis_rq_tlast_r),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(axis_rq_tuser_r),
/*
* AXI output
*/
.m_axis_tdata(m_axis_rq_tdata),
.m_axis_tkeep(m_axis_rq_tkeep),
.m_axis_tvalid(m_axis_rq_tvalid),
.m_axis_tready(m_axis_rq_tready),
.m_axis_tlast(m_axis_rq_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(m_axis_rq_tuser)
);
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -887,39 +1007,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(16),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(axis_rq_tdata_r),
.m_axis_rq_tkeep(axis_rq_tkeep_r),
.m_axis_rq_tvalid(axis_rq_tvalid_r),
.m_axis_rq_tready(axis_rq_tready_r),
.m_axis_rq_tlast(axis_rq_tlast_r),
.m_axis_rq_tuser(axis_rq_tuser_r),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -989,7 +1123,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1026,34 +1159,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
View File

@ -71,10 +71,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -537,10 +537,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/AU280/fpga_10g/fpga/Makefile
View File

@ -55,10 +55,15 @@ SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

7
fpga/mqnic/AU280/fpga_10g/placement.xdc
View File

@ -17,8 +17,7 @@ resize_pblock [get_pblocks pblock_slr0] -add {SLR0}
create_pblock pblock_pcie
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list pcie4c_uscale_plus_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_msi_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_cfg_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_axil_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_us_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_if_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_axi_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_inst]]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X6Y0:CLOCKREGION_X7Y3}

433
fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v
View File

@ -727,49 +727,106 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(4),
.PCIE_CAP_OFFSET(12'h070)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
pcie_us_axil_master #(
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -781,7 +838,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -790,6 +847,163 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -817,7 +1031,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -826,70 +1039,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -901,39 +1067,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(16),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -1003,7 +1183,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1040,34 +1219,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/AU280/fpga_10g/tb/fpga_core/Makefile
View File

@ -75,10 +75,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/AU280/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -585,10 +585,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/AU50/fpga_100g/fpga/Makefile
View File

@ -40,10 +40,15 @@ SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_pipeline_register.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

479
fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
View File

@ -649,49 +649,106 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(4),
.PCIE_CAP_OFFSET(12'h070)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
pcie_us_axil_master #(
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -703,7 +760,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -712,6 +769,163 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -739,7 +953,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -748,116 +961,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep_r;
wire axis_rq_tlast_r;
wire axis_rq_tready_r;
wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser_r;
wire axis_rq_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH)
)
rq_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(axis_rq_tdata_r),
.s_axis_tkeep(axis_rq_tkeep_r),
.s_axis_tvalid(axis_rq_tvalid_r),
.s_axis_tready(axis_rq_tready_r),
.s_axis_tlast(axis_rq_tlast_r),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(axis_rq_tuser_r),
/*
* AXI output
*/
.m_axis_tdata(m_axis_rq_tdata),
.m_axis_tkeep(m_axis_rq_tkeep),
.m_axis_tvalid(m_axis_rq_tvalid),
.m_axis_tready(m_axis_rq_tready),
.m_axis_tlast(m_axis_rq_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(m_axis_rq_tuser)
);
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -869,39 +989,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(16),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(axis_rq_tdata_r),
.m_axis_rq_tkeep(axis_rq_tkeep_r),
.m_axis_rq_tvalid(axis_rq_tvalid_r),
.m_axis_rq_tready(axis_rq_tready_r),
.m_axis_rq_tlast(axis_rq_tlast_r),
.m_axis_rq_tuser(axis_rq_tuser_r),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -971,7 +1105,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1008,34 +1141,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
View File

@ -71,10 +71,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -499,10 +499,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/AU50/fpga_10g/fpga/Makefile
View File

@ -55,10 +55,15 @@ SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

433
fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v
View File

@ -689,49 +689,106 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(4),
.PCIE_CAP_OFFSET(12'h070)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
pcie_us_axil_master #(
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -743,7 +800,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -752,6 +809,163 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -779,7 +993,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -788,70 +1001,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -863,39 +1029,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(16),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -965,7 +1145,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1002,34 +1181,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/AU50/fpga_10g/tb/fpga_core/Makefile
View File

@ -75,10 +75,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -515,10 +515,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile
View File

@ -53,10 +53,15 @@ SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

435
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -798,51 +798,106 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(64),
.PCIE_CAP_OFFSET(12'h0C0)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr[9:0]),
.cfg_mgmt_function_number(cfg_mgmt_addr[17:10]),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
assign cfg_mgmt_addr[18] = 1'b0;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
pcie_us_axil_master #(
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -854,7 +909,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -863,6 +918,165 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid),
.s_axis_rq_seq_num_1(4'd0),
.s_axis_rq_seq_num_valid_1(1'b0),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr[9:0]),
.cfg_mgmt_function_number(cfg_mgmt_addr[17:10]),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
assign cfg_mgmt_addr[18] = 1'b0;
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -890,7 +1104,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -899,70 +1112,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -974,39 +1140,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(8),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid),
.s_axis_rq_seq_num_1(4'd0),
.s_axis_rq_seq_num_valid_1(1'b0),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -1076,7 +1256,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1113,34 +1292,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/Makefile
View File

@ -75,10 +75,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -503,10 +503,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile
View File

@ -55,10 +55,15 @@ SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

433
fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v
View File

@ -800,49 +800,106 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(4),
.PCIE_CAP_OFFSET(12'h070)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
pcie_us_axil_master #(
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -854,7 +911,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -863,6 +920,163 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -890,7 +1104,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -899,70 +1112,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -974,39 +1140,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(16),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -1076,7 +1256,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1113,34 +1292,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile
View File

@ -75,10 +75,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -509,10 +509,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile
View File

@ -55,10 +55,15 @@ SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

435
fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
View File

@ -686,51 +686,106 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(64),
.PCIE_CAP_OFFSET(12'h0C0)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr[9:0]),
.cfg_mgmt_function_number(cfg_mgmt_addr[17:10]),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
assign cfg_mgmt_addr[18] = 1'b0;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
pcie_us_axil_master #(
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -742,7 +797,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -751,6 +806,165 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid),
.s_axis_rq_seq_num_1(4'd0),
.s_axis_rq_seq_num_valid_1(1'b0),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr[9:0]),
.cfg_mgmt_function_number(cfg_mgmt_addr[17:10]),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
assign cfg_mgmt_addr[18] = 1'b0;
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -778,7 +992,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -787,70 +1000,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -862,39 +1028,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(8),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid),
.s_axis_rq_seq_num_1(4'd0),
.s_axis_rq_seq_num_valid_1(1'b0),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -964,7 +1144,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1001,34 +1180,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
View File

@ -75,10 +75,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -518,10 +518,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/VCU108/fpga_10g/fpga/Makefile
View File

@ -55,10 +55,15 @@ SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

435
fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -782,51 +782,106 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(64),
.PCIE_CAP_OFFSET(12'h0C0)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr[9:0]),
.cfg_mgmt_function_number(cfg_mgmt_addr[17:10]),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
assign cfg_mgmt_addr[18] = 1'b0;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
pcie_us_axil_master #(
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -838,7 +893,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -847,6 +902,165 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid),
.s_axis_rq_seq_num_1(4'd0),
.s_axis_rq_seq_num_valid_1(1'b0),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr[9:0]),
.cfg_mgmt_function_number(cfg_mgmt_addr[17:10]),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
assign cfg_mgmt_addr[18] = 1'b0;
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -874,7 +1088,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -883,70 +1096,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -958,39 +1124,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(8),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid),
.s_axis_rq_seq_num_1(4'd0),
.s_axis_rq_seq_num_valid_1(1'b0),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -1060,7 +1240,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1097,34 +1276,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile
View File

@ -75,10 +75,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -522,10 +522,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/VCU118/fpga_100g/fpga/Makefile
View File

@ -39,10 +39,15 @@ SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/axis_pipeline_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

7
fpga/mqnic/VCU118/fpga_100g/placement.xdc
View File

@ -17,10 +17,9 @@ resize_pblock [get_pblocks pblock_slr1] -add {SLR1}
create_pblock pblock_pcie
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list pcie4_uscale_plus_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_msi_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_cfg_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_axil_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_us_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_if_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_axi_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_inst]]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}
create_pblock pblock_eth

433
fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
View File

@ -791,49 +791,106 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(4),
.PCIE_CAP_OFFSET(12'h070)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
pcie_us_axil_master #(
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -845,7 +902,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -854,6 +911,163 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -881,7 +1095,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -890,70 +1103,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -965,39 +1131,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(16),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -1067,7 +1247,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1104,34 +1283,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile
View File

@ -71,10 +71,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -552,10 +552,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/VCU118/fpga_10g/fpga/Makefile
View File

@ -55,10 +55,15 @@ SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

7
fpga/mqnic/VCU118/fpga_10g/placement.xdc
View File

@ -17,8 +17,7 @@ resize_pblock [get_pblocks pblock_slr1] -add {SLR1}
create_pblock pblock_pcie
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list pcie4_uscale_plus_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_msi_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_cfg_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_axil_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_us_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_if_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_axi_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_inst]]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}

433
fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v
View File

@ -851,49 +851,106 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(4),
.PCIE_CAP_OFFSET(12'h070)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
pcie_us_axil_master #(
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -905,7 +962,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -914,6 +971,163 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -941,7 +1155,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -950,70 +1163,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -1025,39 +1191,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(16),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -1127,7 +1307,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1164,34 +1343,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/VCU118/fpga_10g/tb/fpga_core/Makefile
View File

@ -75,10 +75,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -600,10 +600,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile
View File

@ -38,10 +38,15 @@ SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/axis_pipeline_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

7
fpga/mqnic/VCU1525/fpga_100g/placement.xdc
View File

@ -17,10 +17,9 @@ resize_pblock [get_pblocks pblock_slr1] -add {SLR1}
create_pblock pblock_pcie
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list pcie4_uscale_plus_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_msi_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_cfg_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_axil_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_us_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_if_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_axi_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_inst]]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}
create_pblock pblock_eth

479
fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
View File

@ -684,49 +684,106 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(4),
.PCIE_CAP_OFFSET(12'h070)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
pcie_us_axil_master #(
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -738,7 +795,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -747,6 +804,163 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -774,7 +988,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -783,116 +996,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep_r;
wire axis_rq_tlast_r;
wire axis_rq_tready_r;
wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser_r;
wire axis_rq_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH)
)
rq_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(axis_rq_tdata_r),
.s_axis_tkeep(axis_rq_tkeep_r),
.s_axis_tvalid(axis_rq_tvalid_r),
.s_axis_tready(axis_rq_tready_r),
.s_axis_tlast(axis_rq_tlast_r),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(axis_rq_tuser_r),
/*
* AXI output
*/
.m_axis_tdata(m_axis_rq_tdata),
.m_axis_tkeep(m_axis_rq_tkeep),
.m_axis_tvalid(m_axis_rq_tvalid),
.m_axis_tready(m_axis_rq_tready),
.m_axis_tlast(m_axis_rq_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(m_axis_rq_tuser)
);
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -904,39 +1024,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(16),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(axis_rq_tdata_r),
.m_axis_rq_tkeep(axis_rq_tkeep_r),
.m_axis_rq_tvalid(axis_rq_tvalid_r),
.m_axis_rq_tready(axis_rq_tready_r),
.m_axis_rq_tlast(axis_rq_tlast_r),
.m_axis_rq_tuser(axis_rq_tuser_r),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -1006,7 +1140,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1043,34 +1176,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile
View File

@ -71,10 +71,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -546,10 +546,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/VCU1525/fpga_10g/fpga/Makefile
View File

@ -53,10 +53,15 @@ SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

7
fpga/mqnic/VCU1525/fpga_10g/placement.xdc
View File

@ -17,8 +17,7 @@ resize_pblock [get_pblocks pblock_slr1] -add {SLR1}
create_pblock pblock_pcie
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list pcie4_uscale_plus_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_msi_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_cfg_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_axil_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_us_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_if_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_axi_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_inst]]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}

433
fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v
View File

@ -744,49 +744,106 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(4),
.PCIE_CAP_OFFSET(12'h070)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
pcie_us_axil_master #(
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -798,7 +855,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -807,6 +864,163 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -834,7 +1048,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -843,70 +1056,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -918,39 +1084,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(16),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -1020,7 +1200,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1057,34 +1236,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/VCU1525/fpga_10g/tb/fpga_core/Makefile
View File

@ -75,10 +75,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/VCU1525/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -594,10 +594,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile
View File

@ -55,10 +55,15 @@ SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

433
fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
View File

@ -576,49 +576,106 @@ always @(posedge clk_250mhz) begin
end
end
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(4),
.PCIE_CAP_OFFSET(12'h070)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
pcie_us_axil_master #(
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -630,7 +687,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -639,6 +696,163 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -666,7 +880,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -675,70 +888,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -750,39 +916,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(16),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -852,7 +1032,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -889,34 +1068,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile
View File

@ -75,10 +75,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py
View File

@ -503,10 +503,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile
View File

@ -39,10 +39,15 @@ SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

7
fpga/mqnic/fb2CG/fpga_100g/placement.xdc
View File

@ -1,10 +1,9 @@
# Placement constraints
create_pblock pblock_pcie
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list pcie4_uscale_plus_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_msi_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_cfg_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_axil_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_us_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_if_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_axi_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_inst]]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X2Y0:CLOCKREGION_X3Y3}
# create_pblock pblock_eth

503
fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
View File

@ -839,49 +839,106 @@ bmc_spi_inst (
.bmc_int(bmc_int)
);
pcie_us_cfg #(
.PF_COUNT(1),
.VF_COUNT(0),
.VF_OFFSET(4),
.PCIE_CAP_OFFSET(12'h070)
)
pcie_us_cfg_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
/*
* Interface to Ultrascale PCIe IP core
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
);
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
pcie_us_axil_master #(
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.ENABLE_PARITY(0)
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSI_ENABLE(1),
.MSI_COUNT(32)
)
pcie_us_axil_master_inst (
pcie_if_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
@ -893,7 +950,7 @@ pcie_us_axil_master_inst (
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI input (CC)
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
@ -902,6 +959,163 @@ pcie_us_axil_master_inst (
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
pcie_axil_master #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(1)
)
pcie_axil_master_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
@ -929,7 +1143,6 @@ pcie_us_axil_master_inst (
* Configuration
*/
.completer_id({8'd0, 5'd0, 3'd0}),
.completer_id_enable(1'b0),
/*
* Status
@ -938,140 +1151,23 @@ pcie_us_axil_master_inst (
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r;
wire axis_rc_tlast_r;
wire axis_rc_tready_r;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
wire axis_rc_tvalid_r;
axis_register #(
.DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.KEEP_ENABLE(1),
.KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
)
rc_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input
*/
.s_axis_tdata(s_axis_rc_tdata),
.s_axis_tkeep(s_axis_rc_tkeep),
.s_axis_tvalid(s_axis_rc_tvalid),
.s_axis_tready(s_axis_rc_tready),
.s_axis_tlast(s_axis_rc_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_rc_tuser),
/*
* AXI output
*/
.m_axis_tdata(axis_rc_tdata_r),
.m_axis_tkeep(axis_rc_tkeep_r),
.m_axis_tvalid(axis_rc_tvalid_r),
.m_axis_tready(axis_rc_tready_r),
.m_axis_tlast(axis_rc_tlast_r),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rc_tuser_r)
);
// ila_0 ila_desc (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0({pcie_dma_read_desc_pcie_addr, pcie_dma_read_desc_ram_sel, pcie_dma_read_desc_ram_addr, pcie_dma_read_desc_tag, pcie_dma_read_desc_status_tag, pcie_dma_write_desc_pcie_addr, pcie_dma_write_desc_ram_sel, pcie_dma_write_desc_ram_addr, pcie_dma_write_desc_tag, pcie_dma_write_desc_status_tag}),
// .probe1(0),
// .probe2(0),
// .probe3(0),
// .probe4({pcie_dma_read_desc_valid, pcie_dma_read_desc_ready, pcie_dma_read_desc_len, pcie_dma_read_desc_status_valid, pcie_dma_write_desc_valid, pcie_dma_write_desc_ready, pcie_dma_write_desc_len, pcie_dma_write_desc_status_valid, status_error_cor_int, status_error_uncor_int}),
// .probe5(0)
// );
// ila_0 ila_rq (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0(m_axis_rq_tdata),
// .probe1(m_axis_rq_tkeep),
// .probe2(m_axis_rq_tvalid),
// .probe3(m_axis_rq_tready),
// .probe4(m_axis_rq_tuser),
// .probe5(m_axis_rq_tlast)
// );
// ila_0 ila_rc (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0(axis_rc_tdata_r),
// .probe1(axis_rc_tkeep_r),
// .probe2(axis_rc_tvalid_r),
// .probe3(axis_rc_tready_r),
// .probe4({axis_rc_tuser_r, dma_if_pcie_us_inst.dma_if_pcie_us_rd_inst.req_state_reg, dma_if_pcie_us_inst.dma_if_pcie_us_rd_inst.tlp_state_reg, dma_if_pcie_us_inst.dma_if_pcie_us_rd_inst.ram_mask_reg}),
// .probe5(axis_rc_tlast_r)
// );
// ila_0 ila_mem (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0({dma_ram_wr_cmd_valid, dma_ram_wr_cmd_ready, dma_ram_wr_cmd_sel, if_dma_ram_wr_cmd_valid, if_dma_ram_wr_cmd_ready, if_dma_ram_wr_cmd_sel, iface[0].interface_inst.desc_dma_ram_wr_cmd_valid, iface[0].interface_inst.desc_dma_ram_wr_cmd_ready, iface[0].interface_inst.port_dma_ram_wr_cmd_valid, iface[0].interface_inst.port_dma_ram_wr_cmd_ready}),
// .probe1(0),
// .probe2(0),
// .probe3(0),
// .probe4(0),
// .probe5(0)
// );
// ila_0 ila_w (
// .clk(clk_250mhz),
// .trig_out(),
// .trig_out_ack(1'b0),
// .trig_in(1'b0),
// .trig_in_ack(),
// .probe0(axi_pcie_dma_wdata),
// .probe1(0),
// .probe2(axi_pcie_dma_wvalid),
// .probe3(axi_pcie_dma_wready),
// .probe4({axi_pcie_dma_wstrb, axi_pcie_dma_awaddr, axi_pcie_dma_awid, axi_pcie_dma_awlen, axi_pcie_dma_awvalid, axi_pcie_dma_awready, dbg}),
// .probe5(axi_pcie_dma_wlast)
// );
assign cfg_fc_sel = 3'b100;
wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph;
wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph;
wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd;
dma_if_pcie_us #
(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
dma_if_pcie #(
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.RAM_SEG_COUNT(SEG_COUNT),
.RAM_SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
@ -1083,39 +1179,53 @@ dma_if_pcie_us #
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(16),
.WRITE_TX_LIMIT(3),
.WRITE_TX_FC_ENABLE(1)
.WRITE_TX_FC_ENABLE(1),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0)
)
dma_if_pcie_us_inst (
dma_if_pcie_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* AXI input (RC)
* TLP input (completion)
*/
.s_axis_rc_tdata(axis_rc_tdata_r),
.s_axis_rc_tkeep(axis_rc_tkeep_r),
.s_axis_rc_tvalid(axis_rc_tvalid_r),
.s_axis_rc_tready(axis_rc_tready_r),
.s_axis_rc_tlast(axis_rc_tlast_r),
.s_axis_rc_tuser(axis_rc_tuser_r),
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* AXI output (RQ)
* TLP output (read request)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
.s_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
@ -1185,7 +1295,6 @@ dma_if_pcie_us_inst (
.write_enable(pcie_dma_enable),
.ext_tag_enable(ext_tag_enable),
.requester_id({8'd0, 5'd0, 3'd0}),
.requester_id_enable(1'b0),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
@ -1222,34 +1331,6 @@ status_error_uncor_pm_inst (
.pulse_out(status_error_uncor)
);
pcie_us_msi #(
.MSI_COUNT(32)
)
pcie_us_msi_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.msi_irq(msi_irq),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
);
wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr;
wire [IF_COUNT*3-1:0] axil_if_awprot;
wire [IF_COUNT-1:0] axil_if_awvalid;

13
fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile
View File

@ -71,10 +71,15 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_us_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v

13
fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -550,10 +550,15 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_us_wr.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),

13
fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile
View File

@ -56,10 +56,15 @@ SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v

7
fpga/mqnic/fb2CG/fpga_10g/placement.xdc
View File

@ -1,8 +1,7 @@
# Placement constraints
create_pblock pblock_pcie
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list pcie4_uscale_plus_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_msi_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_cfg_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_us_axil_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_us_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_if_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/pcie_axi_master_inst]]
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet [list core_inst/dma_if_pcie_inst]]
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X2Y0:CLOCKREGION_X3Y3}

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