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Minor refactor of zero-length handling logic

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This commit is contained in:
Alex Forencich 2022-03-31 00:05:55 -07:00
parent 7cae50fa10
commit 0b9c7671fb
3 changed files with 24 additions and 24 deletions
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10
rtl/dma_if_axi_rd.v
View File

@ -580,18 +580,18 @@ always @* begin
addr_next = addr_next + cycle_byte_count_next;
op_count_next = op_count_next - cycle_byte_count_next;
if (zero_len_next) begin
status_fifo_mask_next = 1'b0;
end else begin
m_axi_rdata_int_next = m_axi_rdata;
m_axi_rvalid_int_next = 1'b1;
status_fifo_mask_next = 1'b1;
end
status_fifo_finish_next = 1'b0;
status_fifo_we_next = 1'b1;
if (zero_len_next) begin
m_axi_rvalid_int_next = 1'b0;
status_fifo_mask_next = 1'b0;
end
if (!USE_AXI_ID) begin
op_table_read_complete_en = 1'b1;
end

10
rtl/dma_if_pcie_rd.v
View File

@ -1061,19 +1061,19 @@ always @* begin
end else begin
// no error
if (zero_len_next) begin
status_fifo_mask_next = 1'b0;
end else begin
tlp_data_int_next = rx_cpl_tlp_data;
tlp_data_valid_int_next = 1'b1;
status_fifo_mask_next = 1'b1;
end
status_fifo_finish_next = 1'b0;
status_fifo_error_next = DMA_ERROR_NONE;
status_fifo_we_next = 1'b1;
if (zero_len_next) begin
tlp_data_valid_int_next = 1'b0;
status_fifo_mask_next = 1'b0;
end
stat_rd_req_finish_tag_next = pcie_tag_next;
stat_rd_req_finish_status_next = DMA_ERROR_NONE;

10
rtl/dma_if_pcie_us_rd.v
View File

@ -1064,19 +1064,19 @@ always @* begin
end else begin
// no error
if (zero_len_next) begin
status_fifo_mask_next = 1'b0;
end else begin
rc_tdata_int_next = s_axis_rc_tdata;
rc_tvalid_int_next = 1'b1;
status_fifo_mask_next = 1'b1;
end
status_fifo_finish_next = 1'b0;
status_fifo_error_next = DMA_ERROR_NONE;
status_fifo_we_next = 1'b1;
if (zero_len_next) begin
rc_tvalid_int_next = 1'b0;
status_fifo_mask_next = 1'b0;
end
if (last_cycle) begin
if (final_cpl_next) begin
// last completion in current read request (PCIe tag)