FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity

Enable termination on LVDS clock input

Browse Source
This commit is contained in:
Alex Forencich 2021-02-05 22:12:59 -08:00
parent 1d7dc703b5
commit 0c1acadbfa
4 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga.xdc
View File

@ -13,8 +13,8 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
# 300 MHz system clock
set_property -dict {LOC AP26 IOSTANDARD LVDS} [get_ports clk_300mhz_p]
set_property -dict {LOC AP27 IOSTANDARD LVDS} [get_ports clk_300mhz_n]
set_property -dict {LOC AP26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_p]
set_property -dict {LOC AP27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_n]
create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
# LEDs

4
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga.xdc
View File

@ -13,8 +13,8 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
# 300 MHz system clock
set_property -dict {LOC AP26 IOSTANDARD LVDS} [get_ports clk_300mhz_p]
set_property -dict {LOC AP27 IOSTANDARD LVDS} [get_ports clk_300mhz_n]
set_property -dict {LOC AP26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_p]
set_property -dict {LOC AP27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_n]
create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
# LEDs

4
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga.xdc
View File

@ -13,8 +13,8 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
# 300 MHz system clock
set_property -dict {LOC AP26 IOSTANDARD LVDS} [get_ports clk_300mhz_p]
set_property -dict {LOC AP27 IOSTANDARD LVDS} [get_ports clk_300mhz_n]
set_property -dict {LOC AP26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_p]
set_property -dict {LOC AP27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_n]
create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
# LEDs

4
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/fpga.xdc
View File

@ -13,8 +13,8 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
# 300 MHz system clock
set_property -dict {LOC AP26 IOSTANDARD LVDS} [get_ports clk_300mhz_p]
set_property -dict {LOC AP27 IOSTANDARD LVDS} [get_ports clk_300mhz_n]
set_property -dict {LOC AP26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_p]
set_property -dict {LOC AP27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_n]
create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
# LEDs