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Enable termination on LVDS clock input

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This commit is contained in:
Alex Forencich 2021-02-05 22:12:59 -08:00
parent 1d7dc703b5
commit 0c1acadbfa
4 changed files with 8 additions and 8 deletions
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4
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga.xdc
View File

@ -13,8 +13,8 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
# 300 MHz system clock # 300 MHz system clock
set_property -dict {LOC AP26 IOSTANDARD LVDS} [get_ports clk_300mhz_p] set_property -dict {LOC AP26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_p]
set_property -dict {LOC AP27 IOSTANDARD LVDS} [get_ports clk_300mhz_n] set_property -dict {LOC AP27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_n]
create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p] create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
# LEDs # LEDs

4
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga.xdc
View File

@ -13,8 +13,8 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
# 300 MHz system clock # 300 MHz system clock
set_property -dict {LOC AP26 IOSTANDARD LVDS} [get_ports clk_300mhz_p] set_property -dict {LOC AP26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_p]
set_property -dict {LOC AP27 IOSTANDARD LVDS} [get_ports clk_300mhz_n] set_property -dict {LOC AP27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_n]
create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p] create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
# LEDs # LEDs

4
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga.xdc
View File

@ -13,8 +13,8 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
# 300 MHz system clock # 300 MHz system clock
set_property -dict {LOC AP26 IOSTANDARD LVDS} [get_ports clk_300mhz_p] set_property -dict {LOC AP26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_p]
set_property -dict {LOC AP27 IOSTANDARD LVDS} [get_ports clk_300mhz_n] set_property -dict {LOC AP27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_n]
create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p] create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
# LEDs # LEDs

4
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/fpga.xdc
View File

@ -13,8 +13,8 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
# 300 MHz system clock # 300 MHz system clock
set_property -dict {LOC AP26 IOSTANDARD LVDS} [get_ports clk_300mhz_p] set_property -dict {LOC AP26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_p]
set_property -dict {LOC AP27 IOSTANDARD LVDS} [get_ports clk_300mhz_n] set_property -dict {LOC AP27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_n]
create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p] create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
# LEDs # LEDs