From 0c350857146b40fc14cf56402c63e3779e2ec6b3 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 14 Nov 2023 21:51:15 -0800 Subject: [PATCH] fpga/common/rtl: Update scheduler block parameters and PTP connections Signed-off-by: Alex Forencich --- fpga/common/rtl/mqnic_core.v | 35 +++++-- fpga/common/rtl/mqnic_interface.v | 86 +++++++++++++--- fpga/common/rtl/mqnic_tx_scheduler_block_rr.v | 95 ++++++++++-------- .../rtl/mqnic_tx_scheduler_block_rr_tdma.v | 99 +++++++++++-------- 4 files changed, 216 insertions(+), 99 deletions(-) diff --git a/fpga/common/rtl/mqnic_core.v b/fpga/common/rtl/mqnic_core.v index 51072f016..bc7ac9a99 100644 --- a/fpga/common/rtl/mqnic_core.v +++ b/fpga/common/rtl/mqnic_core.v @@ -3036,8 +3036,17 @@ generate .PORTS(PORTS_PER_IF), .SCHEDULERS(SCHED_PER_IF), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration + .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), + .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), + .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), + .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), // Queue manager configuration .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), @@ -3490,8 +3499,22 @@ generate /* * PTP clock */ - .ptp_ts_tod(ptp_sync_ts_tod), - .ptp_ts_tod_step(ptp_sync_ts_tod_step), + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), + .ptp_pps(ptp_pps), + .ptp_pps_str(ptp_pps_str), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), + .ptp_sync_pps(ptp_sync_pps), + .ptp_sync_pps_str(ptp_sync_pps_str), + .ptp_perout_locked(ptp_perout_locked), + .ptp_perout_error(ptp_perout_error), + .ptp_perout_pulse(ptp_perout_pulse), /* * Interrupt request output @@ -3530,10 +3553,10 @@ generate assign all_clocks[(n*PORTS_PER_IF+m)*2+0] = port_tx_clk; assign all_clocks[(n*PORTS_PER_IF+m)*2+1] = port_rx_clk; - wire [PTP_TS_WIDTH-1:0] port_rx_ptp_ts_tod; + wire [95:0] port_rx_ptp_ts_tod; wire port_rx_ptp_ts_tod_step; - wire [PTP_TS_WIDTH-1:0] port_tx_ptp_ts_tod; + wire [95:0] port_tx_ptp_ts_tod; wire port_tx_ptp_ts_tod_step; if (PTP_TS_ENABLE) begin: ptp @@ -3633,10 +3656,10 @@ generate end - assign tx_ptp_ts_tod[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = port_tx_ptp_ts_tod; + assign tx_ptp_ts_tod[(n*PORTS_PER_IF+m)*96 +: 96] = port_tx_ptp_ts_tod; assign tx_ptp_ts_tod_step[n*PORTS_PER_IF+m] = port_tx_ptp_ts_tod_step; - assign rx_ptp_ts_tod[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = port_rx_ptp_ts_tod; + assign rx_ptp_ts_tod[(n*PORTS_PER_IF+m)*96 +: 96] = port_rx_ptp_ts_tod; assign rx_ptp_ts_tod_step[n*PORTS_PER_IF+m] = port_rx_ptp_ts_tod_step; end diff --git a/fpga/common/rtl/mqnic_interface.v b/fpga/common/rtl/mqnic_interface.v index e64bafd4b..77d118b61 100644 --- a/fpga/common/rtl/mqnic_interface.v +++ b/fpga/common/rtl/mqnic_interface.v @@ -18,8 +18,17 @@ module mqnic_interface # parameter PORTS = 1, parameter SCHEDULERS = 1, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration + parameter PTP_CLK_PERIOD_NS_NUM = 4, + parameter PTP_CLK_PERIOD_NS_DENOM = 1, parameter PTP_TS_WIDTH = 96, + parameter PTP_CLOCK_CDC_PIPELINE = 0, + parameter PTP_PEROUT_ENABLE = 0, + parameter PTP_PEROUT_COUNT = 1, // Queue manager configuration (interface) parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, @@ -472,8 +481,22 @@ module mqnic_interface # /* * PTP clock */ - input wire [95:0] ptp_ts_tod, - input wire ptp_ts_tod_step, + input wire ptp_clk, + input wire ptp_rst, + input wire ptp_sample_clk, + input wire ptp_td_sd, + input wire ptp_pps, + input wire ptp_pps_str, + input wire ptp_sync_locked, + input wire [63:0] ptp_sync_ts_rel, + input wire ptp_sync_ts_rel_step, + input wire [96:0] ptp_sync_ts_tod, + input wire ptp_sync_ts_tod_step, + input wire ptp_sync_pps, + input wire ptp_sync_pps_str, + input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked, + input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error, + input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse, /* * Interrupt request output @@ -2222,26 +2245,49 @@ genvar n; for (n = 0; n < SCHEDULERS; n = n + 1) begin : sched mqnic_tx_scheduler_block #( + // Structural configuration .PORTS(PORTS), .INDEX(n), + + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + + // PTP configuration + .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), + .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), + .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), + .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), + .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), + + // Queue manager configuration + .QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), + + // Scheduler configuration + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), + .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), + .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), + + // Interface configuration + .DMA_LEN_WIDTH(DMA_CLIENT_LEN_WIDTH), + .TX_REQ_TAG_WIDTH(REQ_TAG_WIDTH_INT), + .MAX_TX_SIZE(MAX_TX_SIZE), + + // Register interface configuration .REG_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), .REG_DATA_WIDTH(AXIL_DATA_WIDTH), .REG_STRB_WIDTH(AXIL_STRB_WIDTH), .RB_BASE_ADDR(SCHED_RB_BASE_ADDR + SCHED_RB_STRIDE*n), .RB_NEXT_PTR(n < SCHEDULERS-1 ? SCHED_RB_BASE_ADDR + SCHED_RB_STRIDE*(n+1) : 0), + + // AXI lite interface configuration .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), .AXIL_ADDR_WIDTH(AXIL_SCHED_ADDR_WIDTH), .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH), .AXIL_OFFSET(AXIL_SCHED_BASE_ADDR + (2**AXIL_SCHED_ADDR_WIDTH)*n), - .LEN_WIDTH(DMA_CLIENT_LEN_WIDTH), - .REQ_TAG_WIDTH(REQ_TAG_WIDTH_INT), - .OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .AXIS_TX_DEST_WIDTH(AXIS_IF_TX_DEST_WIDTH), - .MAX_TX_SIZE(MAX_TX_SIZE) + + // Streaming interface configuration + .AXIS_TX_DEST_WIDTH(AXIS_IF_TX_DEST_WIDTH) ) scheduler_block ( .clk(clk), @@ -2310,8 +2356,22 @@ for (n = 0; n < SCHEDULERS; n = n + 1) begin : sched /* * PTP clock */ - .ptp_ts_96(ptp_ts_tod), - .ptp_ts_step(ptp_ts_tod_step), + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sd(ptp_td_sd), + .ptp_pps(ptp_pps), + .ptp_pps_str(ptp_pps_str), + .ptp_sync_locked(ptp_sync_locked), + .ptp_sync_ts_rel(ptp_sync_ts_rel), + .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step), + .ptp_sync_ts_tod(ptp_sync_ts_tod), + .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step), + .ptp_sync_pps(ptp_sync_pps), + .ptp_sync_pps_str(ptp_sync_pps_str), + .ptp_perout_locked(ptp_perout_locked), + .ptp_perout_error(ptp_perout_error), + .ptp_perout_pulse(ptp_perout_pulse), /* * Configuration diff --git a/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v b/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v index 37f33a8af..73822c708 100644 --- a/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v +++ b/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v @@ -14,46 +14,49 @@ */ module mqnic_tx_scheduler_block # ( - // Number of ports + // Structural configuration parameter PORTS = 1, - // Scheduler index parameter INDEX = 0, - // Width of control register interface address in bits + + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + + // PTP configuration + parameter PTP_CLK_PERIOD_NS_NUM = 4, + parameter PTP_CLK_PERIOD_NS_DENOM = 1, + parameter PTP_CLOCK_CDC_PIPELINE = 0, + parameter PTP_PEROUT_ENABLE = 0, + parameter PTP_PEROUT_COUNT = 1, + + // Queue manager configuration + parameter QUEUE_INDEX_WIDTH = 13, + + // Scheduler configuration + parameter TX_SCHEDULER_OP_TABLE_SIZE = 8, + parameter TX_SCHEDULER_PIPELINE = 3, + parameter TDMA_INDEX_WIDTH = 6, + + // Interface configuration + parameter DMA_LEN_WIDTH = 16, + parameter TX_REQ_TAG_WIDTH = 8, + parameter MAX_TX_SIZE = 9214, + + // Register interface configuration parameter REG_ADDR_WIDTH = 16, - // Width of control register interface data in bits parameter REG_DATA_WIDTH = 32, - // Width of control register interface strb parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8), - // Register block base address parameter RB_BASE_ADDR = 0, - // Register block next pointer parameter RB_NEXT_PTR = 0, - // Width of AXI lite data bus in bits + + // AXI lite interface configuration parameter AXIL_DATA_WIDTH = 32, - // Width of AXI lite address bus in bits parameter AXIL_ADDR_WIDTH = 16, - // Width of AXI lite wstrb (width of data bus in words) parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8), - // Offset to AXI lite interface parameter AXIL_OFFSET = 0, - // Length field width - parameter LEN_WIDTH = 16, - // Transmit request tag field width - parameter REQ_TAG_WIDTH = 8, - // Number of outstanding operations - parameter OP_TABLE_SIZE = 16, - // Queue index width - parameter QUEUE_INDEX_WIDTH = 6, - // Pipeline setting - parameter PIPELINE = 3, - // Scheduler TDMA index width - parameter TDMA_INDEX_WIDTH = 8, - // PTP timestamp width - parameter PTP_TS_WIDTH = 96, - // AXI stream tdest signal width - parameter AXIS_TX_DEST_WIDTH = $clog2(PORTS)+4, - // Max transmit packet size - parameter MAX_TX_SIZE = 2048 + + // Streaming interface configuration + parameter AXIS_TX_DEST_WIDTH = $clog2(PORTS)+4 ) ( input wire clk, @@ -101,7 +104,7 @@ module mqnic_tx_scheduler_block # * Transmit request output (queue index) */ output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_tx_req_queue, - output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_req_tag, + output wire [TX_REQ_TAG_WIDTH-1:0] m_axis_tx_req_tag, output wire [AXIS_TX_DEST_WIDTH-1:0] m_axis_tx_req_dest, output wire m_axis_tx_req_valid, input wire m_axis_tx_req_ready, @@ -109,8 +112,8 @@ module mqnic_tx_scheduler_block # /* * Transmit request status input */ - input wire [LEN_WIDTH-1:0] s_axis_tx_req_status_len, - input wire [REQ_TAG_WIDTH-1:0] s_axis_tx_req_status_tag, + input wire [DMA_LEN_WIDTH-1:0] s_axis_tx_req_status_len, + input wire [TX_REQ_TAG_WIDTH-1:0] s_axis_tx_req_status_tag, input wire s_axis_tx_req_status_valid, /* @@ -122,13 +125,27 @@ module mqnic_tx_scheduler_block # /* * PTP clock */ - input wire [PTP_TS_WIDTH-1:0] ptp_ts_96, - input wire ptp_ts_step, + input wire ptp_clk, + input wire ptp_rst, + input wire ptp_sample_clk, + input wire ptp_td_sd, + input wire ptp_pps, + input wire ptp_pps_str, + input wire ptp_sync_locked, + input wire [63:0] ptp_sync_ts_rel, + input wire ptp_sync_ts_rel_step, + input wire [96:0] ptp_sync_ts_tod, + input wire ptp_sync_ts_tod_step, + input wire ptp_sync_pps, + input wire ptp_sync_pps_str, + input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked, + input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error, + input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse, /* * Configuration */ - input wire [LEN_WIDTH-1:0] mtu + input wire [DMA_LEN_WIDTH-1:0] mtu ); parameter SCHED_COUNT = 1; @@ -216,11 +233,11 @@ tx_scheduler_rr #( .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), .AXIL_ADDR_WIDTH(AXIL_SCHED_ADDR_WIDTH), .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH), - .LEN_WIDTH(LEN_WIDTH), - .REQ_TAG_WIDTH(REQ_TAG_WIDTH), - .OP_TABLE_SIZE(OP_TABLE_SIZE), + .LEN_WIDTH(DMA_LEN_WIDTH), + .REQ_TAG_WIDTH(TX_REQ_TAG_WIDTH), + .OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH), - .PIPELINE(PIPELINE), + .PIPELINE(TX_SCHEDULER_PIPELINE), .SCHED_CTRL_ENABLE(0) ) tx_scheduler_inst ( diff --git a/fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v b/fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v index 13fdf4173..b9b60a351 100644 --- a/fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v +++ b/fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v @@ -14,46 +14,49 @@ */ module mqnic_tx_scheduler_block # ( - // Number of ports + // Structural configuration parameter PORTS = 1, - // Scheduler index parameter INDEX = 0, - // Width of control register interface address in bits + + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + + // PTP configuration + parameter PTP_CLK_PERIOD_NS_NUM = 4, + parameter PTP_CLK_PERIOD_NS_DENOM = 1, + parameter PTP_CLOCK_CDC_PIPELINE = 0, + parameter PTP_PEROUT_ENABLE = 0, + parameter PTP_PEROUT_COUNT = 1, + + // Queue manager configuration + parameter QUEUE_INDEX_WIDTH = 13, + + // Scheduler configuration + parameter TX_SCHEDULER_OP_TABLE_SIZE = 8, + parameter TX_SCHEDULER_PIPELINE = 3, + parameter TDMA_INDEX_WIDTH = 6, + + // Interface configuration + parameter DMA_LEN_WIDTH = 16, + parameter TX_REQ_TAG_WIDTH = 8, + parameter MAX_TX_SIZE = 9214, + + // Register interface configuration parameter REG_ADDR_WIDTH = 16, - // Width of control register interface data in bits parameter REG_DATA_WIDTH = 32, - // Width of control register interface strb parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8), - // Register block base address parameter RB_BASE_ADDR = 0, - // Register block next pointer parameter RB_NEXT_PTR = 0, - // Width of AXI lite data bus in bits + + // AXI lite interface configuration parameter AXIL_DATA_WIDTH = 32, - // Width of AXI lite address bus in bits parameter AXIL_ADDR_WIDTH = 16, - // Width of AXI lite wstrb (width of data bus in words) parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8), - // Offset to AXI lite interface parameter AXIL_OFFSET = 0, - // Length field width - parameter LEN_WIDTH = 16, - // Transmit request tag field width - parameter REQ_TAG_WIDTH = 8, - // Number of outstanding operations - parameter OP_TABLE_SIZE = 16, - // Queue index width - parameter QUEUE_INDEX_WIDTH = 6, - // Pipeline setting - parameter PIPELINE = 3, - // Scheduler TDMA index width - parameter TDMA_INDEX_WIDTH = 8, - // PTP timestamp width - parameter PTP_TS_WIDTH = 96, - // AXI stream tdest signal width - parameter AXIS_TX_DEST_WIDTH = $clog2(PORTS)+4, - // Max transmit packet size - parameter MAX_TX_SIZE = 2048 + + // Streaming interface configuration + parameter AXIS_TX_DEST_WIDTH = $clog2(PORTS)+4 ) ( input wire clk, @@ -101,7 +104,7 @@ module mqnic_tx_scheduler_block # * Transmit request output (queue index) */ output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_tx_req_queue, - output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_req_tag, + output wire [TX_REQ_TAG_WIDTH-1:0] m_axis_tx_req_tag, output wire [AXIS_TX_DEST_WIDTH-1:0] m_axis_tx_req_dest, output wire m_axis_tx_req_valid, input wire m_axis_tx_req_ready, @@ -109,8 +112,8 @@ module mqnic_tx_scheduler_block # /* * Transmit request status input */ - input wire [LEN_WIDTH-1:0] s_axis_tx_req_status_len, - input wire [REQ_TAG_WIDTH-1:0] s_axis_tx_req_status_tag, + input wire [DMA_LEN_WIDTH-1:0] s_axis_tx_req_status_len, + input wire [TX_REQ_TAG_WIDTH-1:0] s_axis_tx_req_status_tag, input wire s_axis_tx_req_status_valid, /* @@ -122,13 +125,27 @@ module mqnic_tx_scheduler_block # /* * PTP clock */ - input wire [PTP_TS_WIDTH-1:0] ptp_ts_96, - input wire ptp_ts_step, + input wire ptp_clk, + input wire ptp_rst, + input wire ptp_sample_clk, + input wire ptp_td_sd, + input wire ptp_pps, + input wire ptp_pps_str, + input wire ptp_sync_locked, + input wire [63:0] ptp_sync_ts_rel, + input wire ptp_sync_ts_rel_step, + input wire [96:0] ptp_sync_ts_tod, + input wire ptp_sync_ts_tod_step, + input wire ptp_sync_pps, + input wire ptp_sync_pps_str, + input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked, + input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error, + input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse, /* * Configuration */ - input wire [LEN_WIDTH-1:0] mtu + input wire [DMA_LEN_WIDTH-1:0] mtu ); parameter SCHED_COUNT = 2; @@ -409,11 +426,11 @@ tx_scheduler_rr #( .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), .AXIL_ADDR_WIDTH(AXIL_SCHED_ADDR_WIDTH), .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH), - .LEN_WIDTH(LEN_WIDTH), - .REQ_TAG_WIDTH(REQ_TAG_WIDTH), - .OP_TABLE_SIZE(OP_TABLE_SIZE), + .LEN_WIDTH(DMA_LEN_WIDTH), + .REQ_TAG_WIDTH(TX_REQ_TAG_WIDTH), + .OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH), - .PIPELINE(PIPELINE), + .PIPELINE(TX_SCHEDULER_PIPELINE), .SCHED_CTRL_ENABLE(1) ) tx_scheduler_inst ( @@ -493,8 +510,8 @@ tdma_scheduler #( tdma_scheduler_inst ( .clk(clk), .rst(rst), - .input_ts_96(ptp_ts_96), - .input_ts_step(ptp_ts_step), + .input_ts_96(ptp_sync_ts_tod), + .input_ts_step(ptp_sync_ts_tod_step), .enable(tdma_enable_reg), .input_schedule_start(set_tdma_schedule_start_reg), .input_schedule_start_valid(set_tdma_schedule_start_valid_reg),