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Reverse priority in arbitrated mux

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This commit is contained in:
Alex Forencich 2014-11-16 02:00:27 -08:00
parent d193ca5905
commit 0c3af7d5bb
6 changed files with 78 additions and 66 deletions
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7
rtl/axis_arb_mux.py
View File

@ -103,7 +103,9 @@ module {{name}} #
(
parameter DATA_WIDTH = 8,
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY"
parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
)
(
input wire clk,
@ -166,7 +168,8 @@ mux_inst (
arbiter #(
.PORTS({{n}}),
.TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE")
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
)
arb_inst (
.clk(clk),

7
rtl/axis_arb_mux_4.v
View File

@ -33,7 +33,9 @@ module axis_arb_mux_4 #
(
parameter DATA_WIDTH = 8,
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY"
parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
)
(
input wire clk,
@ -131,7 +133,8 @@ mux_inst (
arbiter #(
.PORTS(4),
.TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE")
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
)
arb_inst (
.clk(clk),

7
rtl/axis_arb_mux_64.py
View File

@ -104,7 +104,9 @@ module {{name}} #
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY"
parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
)
(
input wire clk,
@ -171,7 +173,8 @@ mux_inst (
arbiter #(
.PORTS({{n}}),
.TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE")
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
)
arb_inst (
.clk(clk),

7
rtl/axis_arb_mux_64_4.v
View File

@ -34,7 +34,9 @@ module axis_arb_mux_64_4 #
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY"
parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
)
(
input wire clk,
@ -142,7 +144,8 @@ mux_inst (
arbiter #(
.PORTS(4),
.TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE")
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
)
arb_inst (
.clk(clk),

58
tb/test_axis_arb_mux_4.py
View File

@ -366,13 +366,13 @@ def bench():
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
assert rx_frame == test_frame2
yield delay(100)
@ -412,13 +412,13 @@ def bench():
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
assert rx_frame == test_frame2
yield delay(100)
@ -452,13 +452,13 @@ def bench():
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
assert rx_frame == test_frame2
yield delay(100)
@ -476,39 +476,21 @@ def bench():
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_1_queue.put(test_frame1)
source_1_queue.put(test_frame1)
source_1_queue.put(test_frame1)
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
yield clk.posedge
yield delay(800)
yield clk.posedge
source_2_queue.put(test_frame2)
source_1_queue.put(test_frame1)
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
@ -521,12 +503,30 @@ def bench():
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
raise StopSimulation

58
tb/test_axis_arb_mux_64_4.py
View File

@ -391,13 +391,13 @@ def bench():
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
assert rx_frame == test_frame2
yield delay(100)
@ -437,13 +437,13 @@ def bench():
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
assert rx_frame == test_frame2
yield delay(100)
@ -477,13 +477,13 @@ def bench():
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
assert rx_frame == test_frame2
yield delay(100)
@ -501,39 +501,21 @@ def bench():
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_1_queue.put(test_frame1)
source_1_queue.put(test_frame1)
source_1_queue.put(test_frame1)
source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
source_2_queue.put(test_frame2)
yield clk.posedge
yield delay(150)
yield clk.posedge
source_2_queue.put(test_frame2)
source_1_queue.put(test_frame1)
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
@ -546,12 +528,30 @@ def bench():
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
raise StopSimulation