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Add missing QSFP28 control signal connections on AU200 and AU250

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-05-18 01:30:19 -07:00
parent ed2d34153d
commit 0c7bdb5635
2 changed files with 24 additions and 0 deletions
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12
fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
View File

@ -2162,6 +2162,12 @@ core_inst (
.qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int),
.qsfp0_rx_status(qsfp0_rx_status),
.qsfp0_modprsl(qsfp0_modprsl_int),
.qsfp0_modsell(qsfp0_modsell),
.qsfp0_resetl(qsfp0_resetl),
.qsfp0_intl(qsfp0_intl_int),
.qsfp0_lpmode(qsfp0_lpmode),
.qsfp1_tx_clk(qsfp1_tx_clk_int),
.qsfp1_tx_rst(qsfp1_tx_rst_int),
.qsfp1_tx_axis_tdata(qsfp1_tx_axis_tdata_int),
@ -2186,6 +2192,12 @@ core_inst (
.qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int),
.qsfp1_rx_status(qsfp1_rx_status),
.qsfp1_modprsl(qsfp1_modprsl_int),
.qsfp1_modsell(qsfp1_modsell),
.qsfp1_resetl(qsfp1_resetl),
.qsfp1_intl(qsfp1_intl_int),
.qsfp1_lpmode(qsfp1_lpmode),
/*
* QSPI flash
*/

12
fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
View File

@ -2162,6 +2162,12 @@ core_inst (
.qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int),
.qsfp0_rx_status(qsfp0_rx_status),
.qsfp0_modprsl(qsfp0_modprsl_int),
.qsfp0_modsell(qsfp0_modsell),
.qsfp0_resetl(qsfp0_resetl),
.qsfp0_intl(qsfp0_intl_int),
.qsfp0_lpmode(qsfp0_lpmode),
.qsfp1_tx_clk(qsfp1_tx_clk_int),
.qsfp1_tx_rst(qsfp1_tx_rst_int),
.qsfp1_tx_axis_tdata(qsfp1_tx_axis_tdata_int),
@ -2186,6 +2192,12 @@ core_inst (
.qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int),
.qsfp1_rx_status(qsfp1_rx_status),
.qsfp1_modprsl(qsfp1_modprsl_int),
.qsfp1_modsell(qsfp1_modsell),
.qsfp1_resetl(qsfp1_resetl),
.qsfp1_intl(qsfp1_intl_int),
.qsfp1_lpmode(qsfp1_lpmode),
/*
* QSPI flash
*/