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Update DMA RAM instances
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882b56dbfa
commit
0d1617c05c
@ -282,11 +282,12 @@ dma_psdpram #(
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.PIPELINE(RAM_PIPELINE)
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)
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dma_psdpram_inst (
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.clk(clk),
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.rst(rst),
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/*
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* Write port
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*/
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.clk_wr(clk),
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.rst_wr(rst),
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.wr_cmd_be(dma_ram_wr_cmd_be_int),
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.wr_cmd_addr(dma_ram_wr_cmd_addr_int),
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.wr_cmd_data(dma_ram_wr_cmd_data_int),
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@ -296,8 +297,6 @@ dma_psdpram_inst (
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/*
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* Read port
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*/
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.clk_rd(clk),
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.rst_rd(rst),
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.rd_cmd_addr(dma_ram_rd_cmd_addr),
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.rd_cmd_valid(dma_ram_rd_cmd_valid),
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.rd_cmd_ready(dma_ram_rd_cmd_ready),
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@ -335,11 +335,12 @@ dma_psdpram #(
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.PIPELINE(RAM_PIPELINE)
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)
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dma_psdpram_inst (
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.clk(clk),
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.rst(rst),
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/*
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* Write port
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*/
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.clk_wr(clk),
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.rst_wr(rst),
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.wr_cmd_be(dma_ram_wr_cmd_be),
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.wr_cmd_addr(dma_ram_wr_cmd_addr),
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.wr_cmd_data(dma_ram_wr_cmd_data),
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@ -349,8 +350,6 @@ dma_psdpram_inst (
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/*
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* Read port
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*/
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.clk_rd(clk),
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.rst_rd(rst),
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.rd_cmd_addr(dma_ram_rd_cmd_addr_int),
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.rd_cmd_valid(dma_ram_rd_cmd_valid_int),
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.rd_cmd_ready(dma_ram_rd_cmd_ready_int),
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@ -1857,11 +1857,12 @@ dma_psdpram #(
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.PIPELINE(RAM_PIPELINE)
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)
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dma_psdpram_tx_inst (
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.clk(clk),
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.rst(rst),
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/*
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* Write port
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*/
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.clk_wr(clk),
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.rst_wr(rst),
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.wr_cmd_be(dma_ram_wr_cmd_be),
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.wr_cmd_addr(dma_ram_wr_cmd_addr),
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.wr_cmd_data(dma_ram_wr_cmd_data),
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@ -1871,8 +1872,6 @@ dma_psdpram_tx_inst (
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/*
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* Read port
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*/
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.clk_rd(clk),
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.rst_rd(rst),
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.rd_cmd_addr(dma_ram_rd_cmd_addr_int),
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.rd_cmd_valid(dma_ram_rd_cmd_valid_int),
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.rd_cmd_ready(dma_ram_rd_cmd_ready_int),
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@ -1963,11 +1962,12 @@ dma_psdpram #(
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.PIPELINE(RAM_PIPELINE)
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)
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dma_psdpram_rx_inst (
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.clk(clk),
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.rst(rst),
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/*
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* Write port
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*/
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.clk_wr(clk),
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.rst_wr(rst),
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.wr_cmd_be(dma_ram_wr_cmd_be_int),
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.wr_cmd_addr(dma_ram_wr_cmd_addr_int),
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.wr_cmd_data(dma_ram_wr_cmd_data_int),
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@ -1977,8 +1977,6 @@ dma_psdpram_rx_inst (
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/*
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* Read port
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*/
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.clk_rd(clk),
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.rst_rd(rst),
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.rd_cmd_addr(dma_ram_rd_cmd_addr),
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.rd_cmd_valid(dma_ram_rd_cmd_valid),
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.rd_cmd_ready(dma_ram_rd_cmd_ready),
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