mirror of
https://github.com/corundum/corundum.git
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fpga/mqnic/AU50: Add DMA bench target for Alveo U50
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
a4e115949b
commit
0e6c48f468
191
fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/Makefile
Normal file
191
fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/Makefile
Normal file
@ -0,0 +1,191 @@
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# FPGA settings
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FPGA_PART = xcu50-fsvh2104-2-e
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FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/sync_signal.v
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SYN_FILES += rtl/common/mqnic_core_pcie_us.v
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SYN_FILES += rtl/common/mqnic_core_pcie.v
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SYN_FILES += rtl/common/mqnic_core.v
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SYN_FILES += rtl/common/mqnic_interface.v
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SYN_FILES += rtl/common/mqnic_interface_tx.v
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SYN_FILES += rtl/common/mqnic_interface_rx.v
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SYN_FILES += rtl/common/mqnic_port.v
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SYN_FILES += rtl/common/mqnic_port_tx.v
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SYN_FILES += rtl/common/mqnic_port_rx.v
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SYN_FILES += rtl/common/mqnic_egress.v
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SYN_FILES += rtl/common/mqnic_ingress.v
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SYN_FILES += rtl/common/mqnic_l2_egress.v
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SYN_FILES += rtl/common/mqnic_l2_ingress.v
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SYN_FILES += rtl/common/mqnic_rx_queue_map.v
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SYN_FILES += rtl/common/mqnic_ptp.v
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SYN_FILES += rtl/common/mqnic_ptp_clock.v
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SYN_FILES += rtl/common/mqnic_ptp_perout.v
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SYN_FILES += rtl/common/mqnic_rb_clk_info.v
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SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
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SYN_FILES += rtl/common/cpl_write.v
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SYN_FILES += rtl/common/cpl_op_mux.v
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SYN_FILES += rtl/common/desc_fetch.v
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SYN_FILES += rtl/common/desc_op_mux.v
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SYN_FILES += rtl/common/event_mux.v
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SYN_FILES += rtl/common/queue_manager.v
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SYN_FILES += rtl/common/cpl_queue_manager.v
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SYN_FILES += rtl/common/tx_fifo.v
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SYN_FILES += rtl/common/rx_fifo.v
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SYN_FILES += rtl/common/tx_req_mux.v
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SYN_FILES += rtl/common/tx_engine.v
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SYN_FILES += rtl/common/rx_engine.v
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SYN_FILES += rtl/common/tx_checksum.v
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SYN_FILES += rtl/common/rx_hash.v
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SYN_FILES += rtl/common/rx_checksum.v
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SYN_FILES += rtl/common/rb_drp.v
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SYN_FILES += rtl/common/cmac_gty_wrapper.v
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SYN_FILES += rtl/common/cmac_gty_ch_wrapper.v
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SYN_FILES += rtl/common/stats_counter.v
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SYN_FILES += rtl/common/stats_collect.v
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SYN_FILES += rtl/common/stats_pcie_if.v
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SYN_FILES += rtl/common/stats_pcie_tlp.v
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SYN_FILES += rtl/common/stats_dma_if_pcie.v
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SYN_FILES += rtl/common/stats_dma_latency.v
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SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
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SYN_FILES += rtl/common/tx_scheduler_rr.v
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SYN_FILES += rtl/common/cmac_pad.v
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SYN_FILES += rtl/common/mac_ts_insert.v
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SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
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SYN_FILES += app/dma_bench/rtl/dma_bench.v
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SYN_FILES += lib/eth/rtl/ptp_clock.v
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SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
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SYN_FILES += lib/eth/rtl/ptp_perout.v
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SYN_FILES += lib/axi/rtl/axil_cdc.v
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SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
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SYN_FILES += lib/axi/rtl/axil_cdc_wr.v
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SYN_FILES += lib/axi/rtl/axil_interconnect.v
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SYN_FILES += lib/axi/rtl/axil_crossbar.v
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SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
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SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v
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SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v
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SYN_FILES += lib/axi/rtl/axil_reg_if.v
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SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v
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SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v
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SYN_FILES += lib/axi/rtl/axil_register_rd.v
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SYN_FILES += lib/axi/rtl/axil_register_wr.v
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SYN_FILES += lib/axi/rtl/arbiter.v
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SYN_FILES += lib/axi/rtl/priority_encoder.v
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SYN_FILES += lib/axis/rtl/axis_adapter.v
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SYN_FILES += lib/axis/rtl/axis_arb_mux.v
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SYN_FILES += lib/axis/rtl/axis_async_fifo.v
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SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
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SYN_FILES += lib/axis/rtl/axis_demux.v
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SYN_FILES += lib/axis/rtl/axis_fifo.v
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SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
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SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
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SYN_FILES += lib/axis/rtl/axis_register.v
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SYN_FILES += lib/axis/rtl/sync_reset.v
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SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
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SYN_FILES += lib/pcie/rtl/pcie_msix.v
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SYN_FILES += lib/pcie/rtl/irq_rate_limit.v
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SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
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SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
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SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
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SYN_FILES += lib/pcie/rtl/dma_if_mux.v
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SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
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SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
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SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v
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SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v
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SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v
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SYN_FILES += lib/pcie/rtl/dma_psdpram.v
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SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
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SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
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SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
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SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
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SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES += placement.xdc
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XDC_FILES += boot.xdc
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XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
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XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
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XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
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XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
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XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
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XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
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XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
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XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
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XDC_FILES += ../../../common/syn/vivado/cmac_gty_wrapper.tcl
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XDC_FILES += ../../../common/syn/vivado/cmac_gty_ch_wrapper.tcl
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XDC_FILES += hbm.xdc
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# IP
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IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
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IP_TCL_FILES += ip/cmac_usplus.tcl
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IP_TCL_FILES += ip/cmac_gty.tcl
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IP_TCL_FILES += ip/cms.tcl
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IP_TCL_FILES += ip/hbm_0.tcl
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# Configuration
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CONFIG_TCL_FILES = ./config.tcl
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include ../common/vivado.mk
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program: $(FPGA_TOP).bit
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echo "open_hw" > program.tcl
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echo "connect_hw_server" >> program.tcl
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echo "open_hw_target" >> program.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
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echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
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echo "program_hw_devices [current_hw_device]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -nojournal -nolog -mode batch -source program.tcl
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%.mcs %.prm: %.bit
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echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
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echo "exit" >> generate_mcs.tcl
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vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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COUNT=$$((COUNT-1)); \
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for x in .mcs .prm; \
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do cp $*$$x rev/$*_rev$$COUNT$$x; \
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echo "Output: rev/$*_rev$$COUNT$$x"; done;
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flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
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echo "open_hw" > flash.tcl
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echo "connect_hw_server" >> flash.tcl
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echo "open_hw_target" >> flash.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
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echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
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echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
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echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
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echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
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echo "program_hw_devices [current_hw_device]" >> flash.tcl
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echo "refresh_hw_device [current_hw_device]" >> flash.tcl
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echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
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echo "boot_hw_device [current_hw_device]" >> flash.tcl
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echo "exit" >> flash.tcl
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vivado -nojournal -nolog -mode batch -source flash.tcl
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262
fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl
Normal file
262
fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl
Normal file
@ -0,0 +1,262 @@
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# Copyright 2021, The Regents of the University of California.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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# OF SUCH DAMAGE.
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#
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# The views and conclusions contained in the software and documentation are those
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# of the authors and should not be interpreted as representing official policies,
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# either expressed or implied, of The Regents of the University of California.
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set params [dict create]
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# collect build information
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set build_date [clock seconds]
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set git_hash 00000000
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set git_tag ""
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if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
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puts "Error running git or project not under version control"
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}
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if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
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puts "Error running git, project not under version control, or no tag found"
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}
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puts "Build date: ${build_date}"
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puts "Git hash: ${git_hash}"
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puts "Git tag: ${git_tag}"
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if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
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puts "Failed to extract version from git tag"
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set tag_ver 0.0.1
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}
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puts "Tag version: ${tag_ver}"
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# FW and board IDs
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set fpga_id [expr 0x4B77093]
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set fw_id [expr 0x00000000]
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set fw_ver $tag_ver
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set board_vendor_id [expr 0x10ee]
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set board_device_id [expr 0x9032]
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set board_ver 1.0
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set release_info [expr 0x00000000]
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# PCIe IDs
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set pcie_vendor_id [expr 0x1234]
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set pcie_device_id [expr 0x1001]
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set pcie_class_code [expr 0x020000]
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set pcie_revision_id [expr 0x00]
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set pcie_subsystem_vendor_id $board_vendor_id
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set pcie_subsystem_device_id $board_device_id
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# FW ID block
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dict set params FPGA_ID [format "32'h%08x" $fpga_id]
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dict set params FW_ID [format "32'h%08x" $fw_id]
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dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0]
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dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
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dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0]
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dict set params BUILD_DATE "32'd${build_date}"
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dict set params GIT_HASH "32'h${git_hash}"
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dict set params RELEASE_INFO [format "32'h%08x" $release_info]
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# Structural configuration
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dict set params IF_COUNT "1"
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dict set params PORTS_PER_IF "1"
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dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
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dict set params PORT_MASK "0"
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# Clock configuration
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dict set params CLK_PERIOD_NS_NUM "4"
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dict set params CLK_PERIOD_NS_DENOM "1"
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# PTP configuration
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dict set params PTP_CLOCK_PIPELINE "1"
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dict set params PTP_CLOCK_CDC_PIPELINE "0"
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dict set params PTP_PORT_CDC_PIPELINE "1"
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dict set params PTP_PEROUT_ENABLE "0"
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dict set params PTP_PEROUT_COUNT "1"
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||||
# Queue manager configuration
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dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
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dict set params TX_QUEUE_OP_TABLE_SIZE "32"
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dict set params RX_QUEUE_OP_TABLE_SIZE "32"
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dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
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dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
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dict set params EVENT_QUEUE_INDEX_WIDTH "6"
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dict set params TX_QUEUE_INDEX_WIDTH "13"
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dict set params RX_QUEUE_INDEX_WIDTH "8"
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dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
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dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
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dict set params EVENT_QUEUE_PIPELINE "3"
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dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
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dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
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dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
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dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
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# TX and RX engine configuration
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dict set params TX_DESC_TABLE_SIZE "32"
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dict set params RX_DESC_TABLE_SIZE "32"
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# Scheduler configuration
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dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
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dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
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dict set params TDMA_INDEX_WIDTH "6"
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# Interface configuration
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dict set params PTP_TS_ENABLE "1"
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dict set params TX_CPL_FIFO_DEPTH "32"
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dict set params TX_CHECKSUM_ENABLE "1"
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dict set params RX_RSS_ENABLE "1"
|
||||
dict set params RX_HASH_ENABLE "1"
|
||||
dict set params RX_CHECKSUM_ENABLE "1"
|
||||
dict set params TX_FIFO_DEPTH "32768"
|
||||
dict set params RX_FIFO_DEPTH "131072"
|
||||
dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "131072"
|
||||
dict set params RX_RAM_SIZE "131072"
|
||||
|
||||
# RAM configuration
|
||||
dict set params HBM_CH "32"
|
||||
dict set params HBM_ENABLE "1"
|
||||
dict set params HBM_GROUP_SIZE "32"
|
||||
dict set params AXI_HBM_ADDR_WIDTH "33"
|
||||
dict set params AXI_HBM_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h12348001"
|
||||
dict set params APP_ENABLE "1"
|
||||
dict set params APP_CTRL_ENABLE "1"
|
||||
dict set params APP_DMA_ENABLE "1"
|
||||
dict set params APP_AXIS_DIRECT_ENABLE "1"
|
||||
dict set params APP_AXIS_SYNC_ENABLE "1"
|
||||
dict set params APP_AXIS_IF_ENABLE "1"
|
||||
dict set params APP_STAT_ENABLE "1"
|
||||
|
||||
# DMA interface configuration
|
||||
dict set params DMA_IMM_ENABLE "0"
|
||||
dict set params DMA_IMM_WIDTH "32"
|
||||
dict set params DMA_LEN_WIDTH "16"
|
||||
dict set params DMA_TAG_WIDTH "16"
|
||||
dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
|
||||
dict set params RAM_PIPELINE "2"
|
||||
|
||||
# PCIe interface configuration
|
||||
dict set params PCIE_TAG_COUNT "256"
|
||||
dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
|
||||
dict set params PCIE_DMA_READ_TX_LIMIT "16"
|
||||
dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
|
||||
dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
|
||||
|
||||
# Interrupt configuration
|
||||
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
dict set params AXIL_CTRL_DATA_WIDTH "32"
|
||||
dict set params AXIL_CTRL_ADDR_WIDTH "24"
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
|
||||
dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
|
||||
|
||||
# Ethernet interface configuration
|
||||
dict set params AXIS_ETH_TX_PIPELINE "4"
|
||||
dict set params AXIS_ETH_TX_FIFO_PIPELINE "4"
|
||||
dict set params AXIS_ETH_TX_TS_PIPELINE "4"
|
||||
dict set params AXIS_ETH_RX_PIPELINE "4"
|
||||
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
|
||||
|
||||
# Statistics counter subsystem
|
||||
dict set params STAT_ENABLE "1"
|
||||
dict set params STAT_DMA_ENABLE "1"
|
||||
dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4c_uscale_plus_0]
|
||||
|
||||
# PCIe IDs
|
||||
set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie
|
||||
set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie
|
||||
set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie
|
||||
set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie
|
||||
set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie
|
||||
set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie
|
||||
|
||||
# PCIe IP core configuration
|
||||
set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie
|
||||
|
||||
# Internal interface settings
|
||||
dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
|
||||
dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]
|
||||
dict set params AXIS_PCIE_RC_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 75 : 161]
|
||||
dict set params AXIS_PCIE_RQ_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 62 : 137]
|
||||
dict set params AXIS_PCIE_CQ_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 85 : 183]
|
||||
dict set params AXIS_PCIE_CC_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 33 : 81]
|
||||
dict set params RQ_SEQ_NUM_WIDTH [expr [dict get $params AXIS_PCIE_RQ_USER_WIDTH] == 60 ? 4 : 6]
|
||||
|
||||
# configure BAR settings
|
||||
proc configure_bar {pcie pf bar aperture} {
|
||||
set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes}
|
||||
for { set i 0 } { $i < [llength $size_list] } { incr i } {
|
||||
set scale [lindex $size_list $i]
|
||||
|
||||
if {$aperture > 0 && $aperture < ($i+1)*10} {
|
||||
set size [expr 1 << $aperture - ($i*10)]
|
||||
|
||||
puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)"
|
||||
|
||||
set pcie_config [dict create]
|
||||
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size
|
||||
|
||||
set_property -dict $pcie_config $pcie
|
||||
|
||||
return
|
||||
}
|
||||
}
|
||||
puts "${pcie} PF${pf} BAR${bar}: disabled"
|
||||
set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie
|
||||
}
|
||||
|
||||
# Control BAR (BAR 0)
|
||||
configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH]
|
||||
|
||||
# Application BAR (BAR 2)
|
||||
configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0]
|
||||
|
||||
# apply parameters to top-level
|
||||
set param_list {}
|
||||
dict for {name value} $params {
|
||||
lappend param_list $name=$value
|
||||
}
|
||||
|
||||
# set_property generic $param_list [current_fileset]
|
||||
set_property generic $param_list [get_filesets sources_1]
|
||||
Loading…
x
Reference in New Issue
Block a user