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fpga/common: Remove unnecessary reset from clock info register block

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-02-24 21:32:30 -08:00
parent 1682389fd0
commit 0f86ea9bb1
2 changed files with 0 additions and 7 deletions
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1
fpga/common/rtl/mqnic_core.v
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@ -923,7 +923,6 @@ mqnic_rb_clk_info_inst (
* Clock inputs
*/
.ref_clk(ptp_clk),
.ref_rst(ptp_rst),
.ch_clk(all_clocks)
);

6
fpga/common/rtl/mqnic_rb_clk_info.v
View File

@ -77,7 +77,6 @@ module mqnic_rb_clk_info #
* Clock inputs
*/
input wire ref_clk,
input wire ref_rst,
input wire [CH_CNT-1:0] ch_clk
);
@ -133,11 +132,6 @@ always @(posedge ref_clk) begin
ref_cnt_reg <= (REF_CLK_CYCLES_PER_SEC >> SHIFT) - 1;
ref_strb_reg <= !ref_strb_reg;
end
if (ref_rst) begin
ref_cnt_reg <= 0;
ref_strb_reg <= 0;
end
end
reg ref_strb_sync_1_reg = 0;