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Add BPI flash access and IPROG for VCU108
This commit is contained in:
Alex Forencich
parent
b57905eed6
commit
10357d97d4
4
fpga/mqnic/VCU108/fpga_10g/boot.xdc
Normal file
4
fpga/mqnic/VCU108/fpga_10g/boot.xdc
Normal file
@ -0,0 +1,4 @@
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# Timing constraints for FPGA boot logic
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set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"]
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set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"]
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@ -171,4 +171,47 @@ set_property -dict {LOC AM17 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_re
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# 100 MHz MGT reference clock
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create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p]
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# Flash
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set_property -dict {LOC AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[4]}]
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set_property -dict {LOC AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[5]}]
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set_property -dict {LOC AN20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[6]}]
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set_property -dict {LOC AP20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[7]}]
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set_property -dict {LOC AN19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[8]}]
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set_property -dict {LOC AN18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[9]}]
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set_property -dict {LOC AR18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[10]}]
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set_property -dict {LOC AR17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[11]}]
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set_property -dict {LOC AT20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[12]}]
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set_property -dict {LOC AT19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[13]}]
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set_property -dict {LOC AT17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[14]}]
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set_property -dict {LOC AU17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[15]}]
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set_property -dict {LOC AR20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[0]}]
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set_property -dict {LOC AR19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[1]}]
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set_property -dict {LOC AV20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[2]}]
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set_property -dict {LOC AW20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[3]}]
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set_property -dict {LOC AU19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[4]}]
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set_property -dict {LOC AU18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[5]}]
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set_property -dict {LOC AV19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[6]}]
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set_property -dict {LOC AV18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[7]}]
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set_property -dict {LOC AW18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[8]}]
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set_property -dict {LOC AY18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[9]}]
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set_property -dict {LOC AY19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[10]}]
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set_property -dict {LOC BA19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[11]}]
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set_property -dict {LOC BA17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[12]}]
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set_property -dict {LOC BB17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[13]}]
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set_property -dict {LOC BB19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[14]}]
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set_property -dict {LOC BC19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[15]}]
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set_property -dict {LOC BB18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[16]}]
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set_property -dict {LOC BC18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[17]}]
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set_property -dict {LOC AY20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[18]}]
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set_property -dict {LOC BA20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[19]}]
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set_property -dict {LOC BD18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[20]}]
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set_property -dict {LOC BD17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[21]}]
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set_property -dict {LOC BC20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[22]}]
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set_property -dict {LOC BD20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[23]}]
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set_property -dict {LOC BE20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_region[0]}]
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set_property -dict {LOC BF20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_region[1]}]
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set_property -dict {LOC BF17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_oe_n}]
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set_property -dict {LOC BF16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_we_n}]
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set_property -dict {LOC AW17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_adv_n}]
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set_property -dict {LOC BC23 IOSTANDARD LVCMOS18} [get_ports {flash_wait}]
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@ -72,6 +72,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES += boot.xdc
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XDC_FILES += lib/axis/syn/axis_async_fifo.tcl
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XDC_FILES += lib/axis/syn/sync_reset.tcl
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XDC_FILES += lib/eth/syn/ptp_clock_cdc.tcl
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@ -42,69 +42,80 @@ module fpga (
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/*
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* Clock: 100MHz LVDS
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*/
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input wire clk_125mhz_p,
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input wire clk_125mhz_n,
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input wire clk_125mhz_p,
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input wire clk_125mhz_n,
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/*
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* GPIO
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*/
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input wire btnu,
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input wire btnl,
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input wire btnd,
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input wire btnr,
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input wire btnc,
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input wire [3:0] sw,
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output wire [7:0] led,
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output wire [7:0] pmod0,
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output wire [7:0] pmod1,
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input wire btnu,
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input wire btnl,
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input wire btnd,
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input wire btnr,
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input wire btnc,
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input wire [3:0] sw,
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output wire [7:0] led,
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output wire [7:0] pmod0,
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output wire [7:0] pmod1,
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/*
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* I2C for board management
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*/
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inout wire i2c_scl,
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inout wire i2c_sda,
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inout wire i2c_scl,
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inout wire i2c_sda,
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/*
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* PCI express
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*/
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input wire [7:0] pcie_rx_p,
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input wire [7:0] pcie_rx_n,
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output wire [7:0] pcie_tx_p,
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output wire [7:0] pcie_tx_n,
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input wire pcie_mgt_refclk_p,
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input wire pcie_mgt_refclk_n,
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input wire pcie_reset_n,
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input wire [7:0] pcie_rx_p,
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input wire [7:0] pcie_rx_n,
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output wire [7:0] pcie_tx_p,
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output wire [7:0] pcie_tx_n,
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input wire pcie_mgt_refclk_p,
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input wire pcie_mgt_refclk_n,
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input wire pcie_reset_n,
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/*
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* Ethernet: QSFP28
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*/
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input wire qsfp_rx1_p,
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input wire qsfp_rx1_n,
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input wire qsfp_rx2_p,
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input wire qsfp_rx2_n,
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input wire qsfp_rx3_p,
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input wire qsfp_rx3_n,
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input wire qsfp_rx4_p,
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input wire qsfp_rx4_n,
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output wire qsfp_tx1_p,
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output wire qsfp_tx1_n,
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output wire qsfp_tx2_p,
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output wire qsfp_tx2_n,
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output wire qsfp_tx3_p,
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output wire qsfp_tx3_n,
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output wire qsfp_tx4_p,
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output wire qsfp_tx4_n,
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input wire qsfp_mgt_refclk_0_p,
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input wire qsfp_mgt_refclk_0_n,
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// input wire qsfp_mgt_refclk_1_p,
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// input wire qsfp_mgt_refclk_1_n,
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// output wire qsfp_recclk_p,
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// output wire qsfp_recclk_n,
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output wire qsfp_modsell,
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output wire qsfp_resetl,
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input wire qsfp_modprsl,
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input wire qsfp_intl,
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output wire qsfp_lpmode
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input wire qsfp_rx1_p,
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input wire qsfp_rx1_n,
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input wire qsfp_rx2_p,
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input wire qsfp_rx2_n,
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input wire qsfp_rx3_p,
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input wire qsfp_rx3_n,
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input wire qsfp_rx4_p,
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input wire qsfp_rx4_n,
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output wire qsfp_tx1_p,
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output wire qsfp_tx1_n,
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output wire qsfp_tx2_p,
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output wire qsfp_tx2_n,
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output wire qsfp_tx3_p,
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output wire qsfp_tx3_n,
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output wire qsfp_tx4_p,
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output wire qsfp_tx4_n,
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input wire qsfp_mgt_refclk_0_p,
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input wire qsfp_mgt_refclk_0_n,
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// input wire qsfp_mgt_refclk_1_p,
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// input wire qsfp_mgt_refclk_1_n,
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// output wire qsfp_recclk_p,
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// output wire qsfp_recclk_n,
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output wire qsfp_modsell,
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output wire qsfp_resetl,
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input wire qsfp_modprsl,
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input wire qsfp_intl,
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output wire qsfp_lpmode,
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/*
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* BPI Flash
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*/
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inout wire [15:4] flash_dq,
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output wire [23:0] flash_addr,
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output wire [1:0] flash_region,
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output wire flash_oe_n,
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output wire flash_we_n,
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output wire flash_adv_n,
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input wire flash_wait
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);
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parameter AXIS_PCIE_DATA_WIDTH = 256;
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@ -271,6 +282,172 @@ sync_signal_inst (
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assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
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assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
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// Flash
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wire [3:0] flash_dq_int;
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wire [15:0] flash_dq_i_int;
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wire [15:0] flash_dq_o_int;
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wire flash_dq_oe_int;
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wire [23:0] flash_addr_int;
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wire [1:0] flash_region_int;
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wire flash_region_oe_int;
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wire flash_ce_n_int;
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wire flash_oe_n_int;
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wire flash_we_n_int;
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wire flash_adv_n_int;
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assign flash_dq[15:4] = flash_dq_oe_int ? flash_dq_o_int[15:4] : 12'hzzz;
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assign flash_addr = flash_addr_int;
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assign flash_region = flash_region_oe_int ? flash_region_int : 2'bz;
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assign flash_oe_n = flash_oe_n_int;
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assign flash_we_n = flash_we_n_int;
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assign flash_adv_n = flash_adv_n_int;
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sync_signal #(
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.WIDTH(16),
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.N(2)
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)
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flash_sync_signal_inst (
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.clk(pcie_user_clk),
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.in({flash_dq, flash_dq_int}),
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.out(flash_dq_i_int)
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);
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STARTUPE3
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startupe3_inst (
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.CFGCLK(),
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.CFGMCLK(),
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.DI(flash_dq_int),
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.DO(flash_dq_o_int[3:0]),
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.DTS({4{~flash_dq_oe_int}}),
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.EOS(),
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.FCSBO(flash_ce_n_int),
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.FCSBTS(1'b0),
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.GSR(1'b0),
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.GTS(1'b0),
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.KEYCLEARB(1'b1),
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.PACK(1'b0),
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.PREQ(),
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.USRCCLKO(1'b0),
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.USRCCLKTS(1'b1),
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.USRDONEO(1'b0),
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.USRDONETS(1'b1)
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);
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// FPGA boot
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wire fpga_boot;
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reg fpga_boot_sync_reg_0 = 1'b0;
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reg fpga_boot_sync_reg_1 = 1'b0;
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reg fpga_boot_sync_reg_2 = 1'b0;
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wire icap_avail;
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reg [2:0] icap_state = 0;
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reg icap_csib_reg = 1'b1;
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reg icap_rdwrb_reg = 1'b0;
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reg [31:0] icap_di_reg = 32'hffffffff;
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wire [31:0] icap_di_rev;
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assign icap_di_rev[ 7] = icap_di_reg[ 0];
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assign icap_di_rev[ 6] = icap_di_reg[ 1];
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assign icap_di_rev[ 5] = icap_di_reg[ 2];
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assign icap_di_rev[ 4] = icap_di_reg[ 3];
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assign icap_di_rev[ 3] = icap_di_reg[ 4];
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assign icap_di_rev[ 2] = icap_di_reg[ 5];
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assign icap_di_rev[ 1] = icap_di_reg[ 6];
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assign icap_di_rev[ 0] = icap_di_reg[ 7];
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assign icap_di_rev[15] = icap_di_reg[ 8];
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assign icap_di_rev[14] = icap_di_reg[ 9];
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assign icap_di_rev[13] = icap_di_reg[10];
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assign icap_di_rev[12] = icap_di_reg[11];
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assign icap_di_rev[11] = icap_di_reg[12];
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assign icap_di_rev[10] = icap_di_reg[13];
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assign icap_di_rev[ 9] = icap_di_reg[14];
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assign icap_di_rev[ 8] = icap_di_reg[15];
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assign icap_di_rev[23] = icap_di_reg[16];
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assign icap_di_rev[22] = icap_di_reg[17];
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assign icap_di_rev[21] = icap_di_reg[18];
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assign icap_di_rev[20] = icap_di_reg[19];
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assign icap_di_rev[19] = icap_di_reg[20];
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assign icap_di_rev[18] = icap_di_reg[21];
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assign icap_di_rev[17] = icap_di_reg[22];
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assign icap_di_rev[16] = icap_di_reg[23];
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assign icap_di_rev[31] = icap_di_reg[24];
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assign icap_di_rev[30] = icap_di_reg[25];
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assign icap_di_rev[29] = icap_di_reg[26];
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assign icap_di_rev[28] = icap_di_reg[27];
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assign icap_di_rev[27] = icap_di_reg[28];
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assign icap_di_rev[26] = icap_di_reg[29];
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assign icap_di_rev[25] = icap_di_reg[30];
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assign icap_di_rev[24] = icap_di_reg[31];
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always @(posedge clk_125mhz_int) begin
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case (icap_state)
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0: begin
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icap_state <= 0;
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icap_csib_reg <= 1'b1;
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icap_rdwrb_reg <= 1'b0;
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icap_di_reg <= 32'hffffffff; // dummy word
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if (fpga_boot_sync_reg_2 && icap_avail) begin
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icap_state <= 1;
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icap_csib_reg <= 1'b0;
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icap_rdwrb_reg <= 1'b0;
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icap_di_reg <= 32'hffffffff; // dummy word
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end
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end
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1: begin
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icap_state <= 2;
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icap_csib_reg <= 1'b0;
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icap_rdwrb_reg <= 1'b0;
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icap_di_reg <= 32'hAA995566; // sync word
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end
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2: begin
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icap_state <= 3;
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icap_csib_reg <= 1'b0;
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icap_rdwrb_reg <= 1'b0;
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icap_di_reg <= 32'h20000000; // type 1 noop
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end
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3: begin
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icap_state <= 4;
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icap_csib_reg <= 1'b0;
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icap_rdwrb_reg <= 1'b0;
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icap_di_reg <= 32'h30008001; // write 1 word to CMD
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end
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4: begin
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icap_state <= 5;
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icap_csib_reg <= 1'b0;
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icap_rdwrb_reg <= 1'b0;
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icap_di_reg <= 32'h0000000F; // IPROG
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end
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5: begin
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icap_state <= 0;
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icap_csib_reg <= 1'b0;
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icap_rdwrb_reg <= 1'b0;
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icap_di_reg <= 32'h20000000; // type 1 noop
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end
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endcase
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fpga_boot_sync_reg_0 <= fpga_boot;
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fpga_boot_sync_reg_1 <= fpga_boot_sync_reg_0;
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fpga_boot_sync_reg_2 <= fpga_boot_sync_reg_1;
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end
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ICAPE3
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icape3_inst (
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.AVAIL(icap_avail),
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.CLK(clk_125mhz_int),
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.CSIB(icap_csib_reg),
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.I(icap_di_rev),
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.O(),
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.PRDONE(),
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.PRERROR(),
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.RDWRB(icap_rdwrb_reg)
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);
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// PCIe
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wire pcie_sys_clk;
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wire pcie_sys_clk_gt;
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@ -1091,7 +1268,22 @@ core_inst (
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.qsfp_modsell(qsfp_modsell),
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.qsfp_resetl(qsfp_resetl),
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.qsfp_intl(qsfp_intl_int),
|
||||
.qsfp_lpmode(qsfp_lpmode)
|
||||
.qsfp_lpmode(qsfp_lpmode),
|
||||
|
||||
/*
|
||||
* BPI flash
|
||||
*/
|
||||
.fpga_boot(fpga_boot),
|
||||
.flash_dq_i(flash_dq_i_int),
|
||||
.flash_dq_o(flash_dq_o_int),
|
||||
.flash_dq_oe(flash_dq_oe_int),
|
||||
.flash_addr(flash_addr_int),
|
||||
.flash_region(flash_region_int),
|
||||
.flash_region_oe(flash_region_oe_int),
|
||||
.flash_ce_n(flash_ce_n_int),
|
||||
.flash_oe_n(flash_oe_n_int),
|
||||
.flash_we_n(flash_we_n_int),
|
||||
.flash_adv_n(flash_adv_n_int)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -215,11 +215,12 @@ module fpga_core #
|
||||
/*
|
||||
* BPI Flash
|
||||
*/
|
||||
output wire fpga_boot,
|
||||
input wire [15:0] flash_dq_i,
|
||||
output wire [15:0] flash_dq_o,
|
||||
output wire flash_dq_oe,
|
||||
output wire [22:0] flash_addr,
|
||||
output wire flash_region,
|
||||
output wire [23:0] flash_addr,
|
||||
output wire [1:0] flash_region,
|
||||
output wire flash_region_oe,
|
||||
output wire flash_ce_n,
|
||||
output wire flash_oe_n,
|
||||
@ -464,10 +465,12 @@ reg qsfp_lpmode_reg = 1'b0;
|
||||
reg i2c_scl_o_reg = 1'b1;
|
||||
reg i2c_sda_o_reg = 1'b1;
|
||||
|
||||
reg fpga_boot_reg = 1'b0;
|
||||
|
||||
reg [15:0] flash_dq_o_reg = 16'd0;
|
||||
reg flash_dq_oe_reg = 1'b0;
|
||||
reg [22:0] flash_addr_reg = 23'd0;
|
||||
reg flash_region_reg = 1'b0;
|
||||
reg [23:0] flash_addr_reg = 24'd0;
|
||||
reg [1:0] flash_region_reg = 2'd0;
|
||||
reg flash_region_oe_reg = 1'b0;
|
||||
reg flash_ce_n_reg = 1'b1;
|
||||
reg flash_oe_n_reg = 1'b1;
|
||||
@ -513,6 +516,8 @@ assign i2c_scl_t = i2c_scl_o_reg;
|
||||
assign i2c_sda_o = i2c_sda_o_reg;
|
||||
assign i2c_sda_t = i2c_sda_o_reg;
|
||||
|
||||
assign fpga_boot = fpga_boot_reg;
|
||||
|
||||
assign flash_dq_o = flash_dq_o_reg;
|
||||
assign flash_dq_oe = flash_dq_oe_reg;
|
||||
assign flash_addr = flash_addr_reg;
|
||||
@ -549,6 +554,10 @@ always @(posedge clk_250mhz) begin
|
||||
axil_csr_bvalid_reg <= 1'b1;
|
||||
|
||||
case ({axil_csr_awaddr[15:2], 2'b00})
|
||||
16'h0040: begin
|
||||
// FPGA ID
|
||||
fpga_boot_reg <= axil_csr_wdata == 32'hFEE1DEAD;
|
||||
end
|
||||
// GPIO
|
||||
16'h0110: begin
|
||||
// GPIO I2C 0
|
||||
@ -569,8 +578,8 @@ always @(posedge clk_250mhz) begin
|
||||
// Flash
|
||||
16'h0144: begin
|
||||
// Flash address
|
||||
flash_addr_reg <= axil_csr_wdata[22:0];
|
||||
flash_region_reg <= axil_csr_wdata[23];
|
||||
flash_addr_reg <= axil_csr_wdata[23:0];
|
||||
flash_region_reg <= axil_csr_wdata[25:24];
|
||||
end
|
||||
16'h0148: flash_dq_o_reg <= axil_csr_wdata; // Flash data
|
||||
16'h014C: begin
|
||||
@ -678,8 +687,8 @@ always @(posedge clk_250mhz) begin
|
||||
16'h0140: axil_csr_rdata_reg <= {8'd26, 8'd16, 8'd4, 8'd1}; // Flash ID
|
||||
16'h0144: begin
|
||||
// Flash address
|
||||
axil_csr_rdata_reg[22:0] <= flash_addr_reg;
|
||||
axil_csr_rdata_reg[23] <= flash_region_reg;
|
||||
axil_csr_rdata_reg[23:0] <= flash_addr_reg;
|
||||
axil_csr_rdata_reg[25:24] <= flash_region_reg;
|
||||
end
|
||||
16'h0148: axil_csr_rdata_reg <= flash_dq_i; // Flash data
|
||||
16'h014C: begin
|
||||
@ -689,7 +698,7 @@ always @(posedge clk_250mhz) begin
|
||||
axil_csr_rdata_reg[2] <= flash_we_n_reg; // write enable (inverted)
|
||||
axil_csr_rdata_reg[3] <= flash_adv_n_reg; // address valid (inverted)
|
||||
axil_csr_rdata_reg[8] <= flash_dq_oe_reg; // data output enable
|
||||
axil_csr_rdata_reg[16] <= flash_region_oe_reg; // region output enable (addr bit 23)
|
||||
axil_csr_rdata_reg[16] <= flash_region_oe_reg; // region output enable (addr bit 25)
|
||||
end
|
||||
// PHC
|
||||
16'h0200: axil_csr_rdata_reg <= {8'd0, 8'd0, 8'd0, 8'd1}; // PHC features
|
||||
@ -754,10 +763,12 @@ always @(posedge clk_250mhz) begin
|
||||
i2c_scl_o_reg <= 1'b1;
|
||||
i2c_sda_o_reg <= 1'b1;
|
||||
|
||||
fpga_boot_reg <= 1'b0;
|
||||
|
||||
flash_dq_o_reg <= 16'd0;
|
||||
flash_dq_oe_reg <= 1'b0;
|
||||
flash_addr_reg <= 23'd0;
|
||||
flash_region_reg <= 1'b0;
|
||||
flash_addr_reg <= 24'd0;
|
||||
flash_region_reg <= 2'b0;
|
||||
flash_region_oe_reg <= 1'b0;
|
||||
flash_ce_n_reg <= 1'b1;
|
||||
flash_oe_n_reg <= 1'b1;
|
||||
|
||||
@ -261,10 +261,11 @@ def bench():
|
||||
qsfp_modsell = Signal(bool(0))
|
||||
qsfp_resetl = Signal(bool(1))
|
||||
qsfp_lpmode = Signal(bool(0))
|
||||
fpga_boot = Signal(bool(0))
|
||||
flash_dq_o = Signal(intbv(0)[16:])
|
||||
flash_dq_oe = Signal(bool(0))
|
||||
flash_addr = Signal(intbv(0)[23:])
|
||||
flash_region = Signal(bool(0))
|
||||
flash_addr = Signal(intbv(0)[24:])
|
||||
flash_region = Signal(intbv(0)[2:])
|
||||
flash_region_oe = Signal(bool(0))
|
||||
flash_ce_n = Signal(bool(1))
|
||||
flash_oe_n = Signal(bool(1))
|
||||
@ -624,6 +625,7 @@ def bench():
|
||||
qsfp_modprsl=qsfp_modprsl,
|
||||
qsfp_intl=qsfp_intl,
|
||||
qsfp_lpmode=qsfp_lpmode,
|
||||
fpga_boot=fpga_boot,
|
||||
flash_dq_i=flash_dq_i,
|
||||
flash_dq_o=flash_dq_o,
|
||||
flash_dq_oe=flash_dq_oe,
|
||||
|
||||
@ -122,8 +122,8 @@ reg qsfp_rx_clk_4 = 0;
|
||||
reg qsfp_rx_rst_4 = 0;
|
||||
reg [63:0] qsfp_rxd_4 = 0;
|
||||
reg [7:0] qsfp_rxc_4 = 0;
|
||||
reg qsfp_modprsl = 1'b1;
|
||||
reg qsfp_intl = 1'b1;
|
||||
reg qsfp_modprsl = 1;
|
||||
reg qsfp_intl = 1;
|
||||
reg [15:0] flash_dq_i = 0;
|
||||
|
||||
// Outputs
|
||||
@ -173,10 +173,11 @@ wire [7:0] qsfp_txc_4;
|
||||
wire qsfp_modsell;
|
||||
wire qsfp_resetl;
|
||||
wire qsfp_lpmode;
|
||||
wire fpga_boot;
|
||||
wire [15:0] flash_dq_o;
|
||||
wire flash_dq_oe;
|
||||
wire [22:0] flash_addr;
|
||||
wire flash_region;
|
||||
wire [23:0] flash_addr;
|
||||
wire [1:0] flash_region;
|
||||
wire flash_region_oe;
|
||||
wire flash_ce_n;
|
||||
wire flash_oe_n;
|
||||
@ -305,6 +306,7 @@ initial begin
|
||||
qsfp_modsell,
|
||||
qsfp_resetl,
|
||||
qsfp_lpmode,
|
||||
fpga_boot,
|
||||
flash_dq_o,
|
||||
flash_dq_oe,
|
||||
flash_addr,
|
||||
@ -447,6 +449,7 @@ UUT (
|
||||
.qsfp_resetl(qsfp_resetl),
|
||||
.qsfp_intl(qsfp_intl),
|
||||
.qsfp_lpmode(qsfp_lpmode),
|
||||
.fpga_boot(fpga_boot),
|
||||
.flash_dq_i(flash_dq_i),
|
||||
.flash_dq_o(flash_dq_o),
|
||||
.flash_dq_oe(flash_dq_oe),
|
||||
|
||||
4
fpga/mqnic_tdma/VCU108/fpga_10g/boot.xdc
Normal file
4
fpga/mqnic_tdma/VCU108/fpga_10g/boot.xdc
Normal file
@ -0,0 +1,4 @@
|
||||
# Timing constraints for FPGA boot logic
|
||||
|
||||
set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"]
|
||||
set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"]
|
||||
@ -171,4 +171,47 @@ set_property -dict {LOC AM17 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_re
|
||||
# 100 MHz MGT reference clock
|
||||
create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p]
|
||||
|
||||
# Flash
|
||||
set_property -dict {LOC AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[4]}]
|
||||
set_property -dict {LOC AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[5]}]
|
||||
set_property -dict {LOC AN20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[6]}]
|
||||
set_property -dict {LOC AP20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[7]}]
|
||||
set_property -dict {LOC AN19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[8]}]
|
||||
set_property -dict {LOC AN18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[9]}]
|
||||
set_property -dict {LOC AR18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[10]}]
|
||||
set_property -dict {LOC AR17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[11]}]
|
||||
set_property -dict {LOC AT20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[12]}]
|
||||
set_property -dict {LOC AT19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[13]}]
|
||||
set_property -dict {LOC AT17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[14]}]
|
||||
set_property -dict {LOC AU17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[15]}]
|
||||
set_property -dict {LOC AR20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[0]}]
|
||||
set_property -dict {LOC AR19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[1]}]
|
||||
set_property -dict {LOC AV20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[2]}]
|
||||
set_property -dict {LOC AW20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[3]}]
|
||||
set_property -dict {LOC AU19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[4]}]
|
||||
set_property -dict {LOC AU18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[5]}]
|
||||
set_property -dict {LOC AV19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[6]}]
|
||||
set_property -dict {LOC AV18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[7]}]
|
||||
set_property -dict {LOC AW18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[8]}]
|
||||
set_property -dict {LOC AY18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[9]}]
|
||||
set_property -dict {LOC AY19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[10]}]
|
||||
set_property -dict {LOC BA19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[11]}]
|
||||
set_property -dict {LOC BA17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[12]}]
|
||||
set_property -dict {LOC BB17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[13]}]
|
||||
set_property -dict {LOC BB19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[14]}]
|
||||
set_property -dict {LOC BC19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[15]}]
|
||||
set_property -dict {LOC BB18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[16]}]
|
||||
set_property -dict {LOC BC18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[17]}]
|
||||
set_property -dict {LOC AY20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[18]}]
|
||||
set_property -dict {LOC BA20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[19]}]
|
||||
set_property -dict {LOC BD18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[20]}]
|
||||
set_property -dict {LOC BD17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[21]}]
|
||||
set_property -dict {LOC BC20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[22]}]
|
||||
set_property -dict {LOC BD20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[23]}]
|
||||
set_property -dict {LOC BE20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_region[0]}]
|
||||
set_property -dict {LOC BF20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_region[1]}]
|
||||
set_property -dict {LOC BF17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_oe_n}]
|
||||
set_property -dict {LOC BF16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_we_n}]
|
||||
set_property -dict {LOC AW17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_adv_n}]
|
||||
set_property -dict {LOC BC23 IOSTANDARD LVCMOS18} [get_ports {flash_wait}]
|
||||
|
||||
|
||||
@ -73,6 +73,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES += boot.xdc
|
||||
XDC_FILES += lib/axis/syn/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/axis/syn/sync_reset.tcl
|
||||
XDC_FILES += lib/eth/syn/ptp_clock_cdc.tcl
|
||||
|
||||
@ -42,69 +42,80 @@ module fpga (
|
||||
/*
|
||||
* Clock: 100MHz LVDS
|
||||
*/
|
||||
input wire clk_125mhz_p,
|
||||
input wire clk_125mhz_n,
|
||||
input wire clk_125mhz_p,
|
||||
input wire clk_125mhz_n,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
input wire btnu,
|
||||
input wire btnl,
|
||||
input wire btnd,
|
||||
input wire btnr,
|
||||
input wire btnc,
|
||||
input wire [3:0] sw,
|
||||
output wire [7:0] led,
|
||||
output wire [7:0] pmod0,
|
||||
output wire [7:0] pmod1,
|
||||
input wire btnu,
|
||||
input wire btnl,
|
||||
input wire btnd,
|
||||
input wire btnr,
|
||||
input wire btnc,
|
||||
input wire [3:0] sw,
|
||||
output wire [7:0] led,
|
||||
output wire [7:0] pmod0,
|
||||
output wire [7:0] pmod1,
|
||||
|
||||
/*
|
||||
* I2C for board management
|
||||
*/
|
||||
inout wire i2c_scl,
|
||||
inout wire i2c_sda,
|
||||
inout wire i2c_scl,
|
||||
inout wire i2c_sda,
|
||||
|
||||
/*
|
||||
* PCI express
|
||||
*/
|
||||
input wire [7:0] pcie_rx_p,
|
||||
input wire [7:0] pcie_rx_n,
|
||||
output wire [7:0] pcie_tx_p,
|
||||
output wire [7:0] pcie_tx_n,
|
||||
input wire pcie_mgt_refclk_p,
|
||||
input wire pcie_mgt_refclk_n,
|
||||
input wire pcie_reset_n,
|
||||
input wire [7:0] pcie_rx_p,
|
||||
input wire [7:0] pcie_rx_n,
|
||||
output wire [7:0] pcie_tx_p,
|
||||
output wire [7:0] pcie_tx_n,
|
||||
input wire pcie_mgt_refclk_p,
|
||||
input wire pcie_mgt_refclk_n,
|
||||
input wire pcie_reset_n,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
input wire qsfp_rx1_p,
|
||||
input wire qsfp_rx1_n,
|
||||
input wire qsfp_rx2_p,
|
||||
input wire qsfp_rx2_n,
|
||||
input wire qsfp_rx3_p,
|
||||
input wire qsfp_rx3_n,
|
||||
input wire qsfp_rx4_p,
|
||||
input wire qsfp_rx4_n,
|
||||
output wire qsfp_tx1_p,
|
||||
output wire qsfp_tx1_n,
|
||||
output wire qsfp_tx2_p,
|
||||
output wire qsfp_tx2_n,
|
||||
output wire qsfp_tx3_p,
|
||||
output wire qsfp_tx3_n,
|
||||
output wire qsfp_tx4_p,
|
||||
output wire qsfp_tx4_n,
|
||||
input wire qsfp_mgt_refclk_0_p,
|
||||
input wire qsfp_mgt_refclk_0_n,
|
||||
// input wire qsfp_mgt_refclk_1_p,
|
||||
// input wire qsfp_mgt_refclk_1_n,
|
||||
// output wire qsfp_recclk_p,
|
||||
// output wire qsfp_recclk_n,
|
||||
output wire qsfp_modsell,
|
||||
output wire qsfp_resetl,
|
||||
input wire qsfp_modprsl,
|
||||
input wire qsfp_intl,
|
||||
output wire qsfp_lpmode
|
||||
input wire qsfp_rx1_p,
|
||||
input wire qsfp_rx1_n,
|
||||
input wire qsfp_rx2_p,
|
||||
input wire qsfp_rx2_n,
|
||||
input wire qsfp_rx3_p,
|
||||
input wire qsfp_rx3_n,
|
||||
input wire qsfp_rx4_p,
|
||||
input wire qsfp_rx4_n,
|
||||
output wire qsfp_tx1_p,
|
||||
output wire qsfp_tx1_n,
|
||||
output wire qsfp_tx2_p,
|
||||
output wire qsfp_tx2_n,
|
||||
output wire qsfp_tx3_p,
|
||||
output wire qsfp_tx3_n,
|
||||
output wire qsfp_tx4_p,
|
||||
output wire qsfp_tx4_n,
|
||||
input wire qsfp_mgt_refclk_0_p,
|
||||
input wire qsfp_mgt_refclk_0_n,
|
||||
// input wire qsfp_mgt_refclk_1_p,
|
||||
// input wire qsfp_mgt_refclk_1_n,
|
||||
// output wire qsfp_recclk_p,
|
||||
// output wire qsfp_recclk_n,
|
||||
output wire qsfp_modsell,
|
||||
output wire qsfp_resetl,
|
||||
input wire qsfp_modprsl,
|
||||
input wire qsfp_intl,
|
||||
output wire qsfp_lpmode,
|
||||
|
||||
/*
|
||||
* BPI Flash
|
||||
*/
|
||||
inout wire [15:4] flash_dq,
|
||||
output wire [23:0] flash_addr,
|
||||
output wire [1:0] flash_region,
|
||||
output wire flash_oe_n,
|
||||
output wire flash_we_n,
|
||||
output wire flash_adv_n,
|
||||
input wire flash_wait
|
||||
);
|
||||
|
||||
parameter AXIS_PCIE_DATA_WIDTH = 256;
|
||||
@ -271,6 +282,172 @@ sync_signal_inst (
|
||||
assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
|
||||
assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
|
||||
|
||||
// Flash
|
||||
wire [3:0] flash_dq_int;
|
||||
wire [15:0] flash_dq_i_int;
|
||||
wire [15:0] flash_dq_o_int;
|
||||
wire flash_dq_oe_int;
|
||||
wire [23:0] flash_addr_int;
|
||||
wire [1:0] flash_region_int;
|
||||
wire flash_region_oe_int;
|
||||
wire flash_ce_n_int;
|
||||
wire flash_oe_n_int;
|
||||
wire flash_we_n_int;
|
||||
wire flash_adv_n_int;
|
||||
|
||||
assign flash_dq[15:4] = flash_dq_oe_int ? flash_dq_o_int[15:4] : 12'hzzz;
|
||||
assign flash_addr = flash_addr_int;
|
||||
assign flash_region = flash_region_oe_int ? flash_region_int : 2'bz;
|
||||
assign flash_oe_n = flash_oe_n_int;
|
||||
assign flash_we_n = flash_we_n_int;
|
||||
assign flash_adv_n = flash_adv_n_int;
|
||||
|
||||
sync_signal #(
|
||||
.WIDTH(16),
|
||||
.N(2)
|
||||
)
|
||||
flash_sync_signal_inst (
|
||||
.clk(pcie_user_clk),
|
||||
.in({flash_dq, flash_dq_int}),
|
||||
.out(flash_dq_i_int)
|
||||
);
|
||||
|
||||
STARTUPE3
|
||||
startupe3_inst (
|
||||
.CFGCLK(),
|
||||
.CFGMCLK(),
|
||||
.DI(flash_dq_int),
|
||||
.DO(flash_dq_o_int[3:0]),
|
||||
.DTS({4{~flash_dq_oe_int}}),
|
||||
.EOS(),
|
||||
.FCSBO(flash_ce_n_int),
|
||||
.FCSBTS(1'b0),
|
||||
.GSR(1'b0),
|
||||
.GTS(1'b0),
|
||||
.KEYCLEARB(1'b1),
|
||||
.PACK(1'b0),
|
||||
.PREQ(),
|
||||
.USRCCLKO(1'b0),
|
||||
.USRCCLKTS(1'b1),
|
||||
.USRDONEO(1'b0),
|
||||
.USRDONETS(1'b1)
|
||||
);
|
||||
|
||||
// FPGA boot
|
||||
wire fpga_boot;
|
||||
|
||||
reg fpga_boot_sync_reg_0 = 1'b0;
|
||||
reg fpga_boot_sync_reg_1 = 1'b0;
|
||||
reg fpga_boot_sync_reg_2 = 1'b0;
|
||||
|
||||
wire icap_avail;
|
||||
reg [2:0] icap_state = 0;
|
||||
reg icap_csib_reg = 1'b1;
|
||||
reg icap_rdwrb_reg = 1'b0;
|
||||
reg [31:0] icap_di_reg = 32'hffffffff;
|
||||
|
||||
wire [31:0] icap_di_rev;
|
||||
|
||||
assign icap_di_rev[ 7] = icap_di_reg[ 0];
|
||||
assign icap_di_rev[ 6] = icap_di_reg[ 1];
|
||||
assign icap_di_rev[ 5] = icap_di_reg[ 2];
|
||||
assign icap_di_rev[ 4] = icap_di_reg[ 3];
|
||||
assign icap_di_rev[ 3] = icap_di_reg[ 4];
|
||||
assign icap_di_rev[ 2] = icap_di_reg[ 5];
|
||||
assign icap_di_rev[ 1] = icap_di_reg[ 6];
|
||||
assign icap_di_rev[ 0] = icap_di_reg[ 7];
|
||||
|
||||
assign icap_di_rev[15] = icap_di_reg[ 8];
|
||||
assign icap_di_rev[14] = icap_di_reg[ 9];
|
||||
assign icap_di_rev[13] = icap_di_reg[10];
|
||||
assign icap_di_rev[12] = icap_di_reg[11];
|
||||
assign icap_di_rev[11] = icap_di_reg[12];
|
||||
assign icap_di_rev[10] = icap_di_reg[13];
|
||||
assign icap_di_rev[ 9] = icap_di_reg[14];
|
||||
assign icap_di_rev[ 8] = icap_di_reg[15];
|
||||
|
||||
assign icap_di_rev[23] = icap_di_reg[16];
|
||||
assign icap_di_rev[22] = icap_di_reg[17];
|
||||
assign icap_di_rev[21] = icap_di_reg[18];
|
||||
assign icap_di_rev[20] = icap_di_reg[19];
|
||||
assign icap_di_rev[19] = icap_di_reg[20];
|
||||
assign icap_di_rev[18] = icap_di_reg[21];
|
||||
assign icap_di_rev[17] = icap_di_reg[22];
|
||||
assign icap_di_rev[16] = icap_di_reg[23];
|
||||
|
||||
assign icap_di_rev[31] = icap_di_reg[24];
|
||||
assign icap_di_rev[30] = icap_di_reg[25];
|
||||
assign icap_di_rev[29] = icap_di_reg[26];
|
||||
assign icap_di_rev[28] = icap_di_reg[27];
|
||||
assign icap_di_rev[27] = icap_di_reg[28];
|
||||
assign icap_di_rev[26] = icap_di_reg[29];
|
||||
assign icap_di_rev[25] = icap_di_reg[30];
|
||||
assign icap_di_rev[24] = icap_di_reg[31];
|
||||
|
||||
always @(posedge clk_125mhz_int) begin
|
||||
case (icap_state)
|
||||
0: begin
|
||||
icap_state <= 0;
|
||||
icap_csib_reg <= 1'b1;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'hffffffff; // dummy word
|
||||
|
||||
if (fpga_boot_sync_reg_2 && icap_avail) begin
|
||||
icap_state <= 1;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'hffffffff; // dummy word
|
||||
end
|
||||
end
|
||||
1: begin
|
||||
icap_state <= 2;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'hAA995566; // sync word
|
||||
end
|
||||
2: begin
|
||||
icap_state <= 3;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h20000000; // type 1 noop
|
||||
end
|
||||
3: begin
|
||||
icap_state <= 4;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h30008001; // write 1 word to CMD
|
||||
end
|
||||
4: begin
|
||||
icap_state <= 5;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h0000000F; // IPROG
|
||||
end
|
||||
5: begin
|
||||
icap_state <= 0;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h20000000; // type 1 noop
|
||||
end
|
||||
endcase
|
||||
|
||||
fpga_boot_sync_reg_0 <= fpga_boot;
|
||||
fpga_boot_sync_reg_1 <= fpga_boot_sync_reg_0;
|
||||
fpga_boot_sync_reg_2 <= fpga_boot_sync_reg_1;
|
||||
end
|
||||
|
||||
ICAPE3
|
||||
icape3_inst (
|
||||
.AVAIL(icap_avail),
|
||||
.CLK(clk_125mhz_int),
|
||||
.CSIB(icap_csib_reg),
|
||||
.I(icap_di_rev),
|
||||
.O(),
|
||||
.PRDONE(),
|
||||
.PRERROR(),
|
||||
.RDWRB(icap_rdwrb_reg)
|
||||
);
|
||||
|
||||
// PCIe
|
||||
wire pcie_sys_clk;
|
||||
wire pcie_sys_clk_gt;
|
||||
@ -1091,7 +1268,22 @@ core_inst (
|
||||
.qsfp_modsell(qsfp_modsell),
|
||||
.qsfp_resetl(qsfp_resetl),
|
||||
.qsfp_intl(qsfp_intl_int),
|
||||
.qsfp_lpmode(qsfp_lpmode)
|
||||
.qsfp_lpmode(qsfp_lpmode),
|
||||
|
||||
/*
|
||||
* BPI flash
|
||||
*/
|
||||
.fpga_boot(fpga_boot),
|
||||
.flash_dq_i(flash_dq_i_int),
|
||||
.flash_dq_o(flash_dq_o_int),
|
||||
.flash_dq_oe(flash_dq_oe_int),
|
||||
.flash_addr(flash_addr_int),
|
||||
.flash_region(flash_region_int),
|
||||
.flash_region_oe(flash_region_oe_int),
|
||||
.flash_ce_n(flash_ce_n_int),
|
||||
.flash_oe_n(flash_oe_n_int),
|
||||
.flash_we_n(flash_we_n_int),
|
||||
.flash_adv_n(flash_adv_n_int)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -215,11 +215,12 @@ module fpga_core #
|
||||
/*
|
||||
* BPI Flash
|
||||
*/
|
||||
output wire fpga_boot,
|
||||
input wire [15:0] flash_dq_i,
|
||||
output wire [15:0] flash_dq_o,
|
||||
output wire flash_dq_oe,
|
||||
output wire [22:0] flash_addr,
|
||||
output wire flash_region,
|
||||
output wire [23:0] flash_addr,
|
||||
output wire [1:0] flash_region,
|
||||
output wire flash_region_oe,
|
||||
output wire flash_ce_n,
|
||||
output wire flash_oe_n,
|
||||
@ -464,10 +465,12 @@ reg qsfp_lpmode_reg = 1'b0;
|
||||
reg i2c_scl_o_reg = 1'b1;
|
||||
reg i2c_sda_o_reg = 1'b1;
|
||||
|
||||
reg fpga_boot_reg = 1'b0;
|
||||
|
||||
reg [15:0] flash_dq_o_reg = 16'd0;
|
||||
reg flash_dq_oe_reg = 1'b0;
|
||||
reg [22:0] flash_addr_reg = 23'd0;
|
||||
reg flash_region_reg = 1'b0;
|
||||
reg [23:0] flash_addr_reg = 24'd0;
|
||||
reg [1:0] flash_region_reg = 2'd0;
|
||||
reg flash_region_oe_reg = 1'b0;
|
||||
reg flash_ce_n_reg = 1'b1;
|
||||
reg flash_oe_n_reg = 1'b1;
|
||||
@ -513,6 +516,8 @@ assign i2c_scl_t = i2c_scl_o_reg;
|
||||
assign i2c_sda_o = i2c_sda_o_reg;
|
||||
assign i2c_sda_t = i2c_sda_o_reg;
|
||||
|
||||
assign fpga_boot = fpga_boot_reg;
|
||||
|
||||
assign flash_dq_o = flash_dq_o_reg;
|
||||
assign flash_dq_oe = flash_dq_oe_reg;
|
||||
assign flash_addr = flash_addr_reg;
|
||||
@ -549,6 +554,10 @@ always @(posedge clk_250mhz) begin
|
||||
axil_csr_bvalid_reg <= 1'b1;
|
||||
|
||||
case ({axil_csr_awaddr[15:2], 2'b00})
|
||||
16'h0040: begin
|
||||
// FPGA ID
|
||||
fpga_boot_reg <= axil_csr_wdata == 32'hFEE1DEAD;
|
||||
end
|
||||
// GPIO
|
||||
16'h0110: begin
|
||||
// GPIO I2C 0
|
||||
@ -569,8 +578,8 @@ always @(posedge clk_250mhz) begin
|
||||
// Flash
|
||||
16'h0144: begin
|
||||
// Flash address
|
||||
flash_addr_reg <= axil_csr_wdata[22:0];
|
||||
flash_region_reg <= axil_csr_wdata[23];
|
||||
flash_addr_reg <= axil_csr_wdata[23:0];
|
||||
flash_region_reg <= axil_csr_wdata[25:24];
|
||||
end
|
||||
16'h0148: flash_dq_o_reg <= axil_csr_wdata; // Flash data
|
||||
16'h014C: begin
|
||||
@ -678,8 +687,8 @@ always @(posedge clk_250mhz) begin
|
||||
16'h0140: axil_csr_rdata_reg <= {8'd26, 8'd16, 8'd4, 8'd1}; // Flash ID
|
||||
16'h0144: begin
|
||||
// Flash address
|
||||
axil_csr_rdata_reg[22:0] <= flash_addr_reg;
|
||||
axil_csr_rdata_reg[23] <= flash_region_reg;
|
||||
axil_csr_rdata_reg[23:0] <= flash_addr_reg;
|
||||
axil_csr_rdata_reg[25:24] <= flash_region_reg;
|
||||
end
|
||||
16'h0148: axil_csr_rdata_reg <= flash_dq_i; // Flash data
|
||||
16'h014C: begin
|
||||
@ -689,7 +698,7 @@ always @(posedge clk_250mhz) begin
|
||||
axil_csr_rdata_reg[2] <= flash_we_n_reg; // write enable (inverted)
|
||||
axil_csr_rdata_reg[3] <= flash_adv_n_reg; // address valid (inverted)
|
||||
axil_csr_rdata_reg[8] <= flash_dq_oe_reg; // data output enable
|
||||
axil_csr_rdata_reg[16] <= flash_region_oe_reg; // region output enable (addr bit 23)
|
||||
axil_csr_rdata_reg[16] <= flash_region_oe_reg; // region output enable (addr bit 25)
|
||||
end
|
||||
// PHC
|
||||
16'h0200: axil_csr_rdata_reg <= {8'd0, 8'd0, 8'd0, 8'd1}; // PHC features
|
||||
@ -754,10 +763,12 @@ always @(posedge clk_250mhz) begin
|
||||
i2c_scl_o_reg <= 1'b1;
|
||||
i2c_sda_o_reg <= 1'b1;
|
||||
|
||||
fpga_boot_reg <= 1'b0;
|
||||
|
||||
flash_dq_o_reg <= 16'd0;
|
||||
flash_dq_oe_reg <= 1'b0;
|
||||
flash_addr_reg <= 23'd0;
|
||||
flash_region_reg <= 1'b0;
|
||||
flash_addr_reg <= 24'd0;
|
||||
flash_region_reg <= 2'b0;
|
||||
flash_region_oe_reg <= 1'b0;
|
||||
flash_ce_n_reg <= 1'b1;
|
||||
flash_oe_n_reg <= 1'b1;
|
||||
|
||||
@ -262,10 +262,11 @@ def bench():
|
||||
qsfp_modsell = Signal(bool(0))
|
||||
qsfp_resetl = Signal(bool(1))
|
||||
qsfp_lpmode = Signal(bool(0))
|
||||
fpga_boot = Signal(bool(0))
|
||||
flash_dq_o = Signal(intbv(0)[16:])
|
||||
flash_dq_oe = Signal(bool(0))
|
||||
flash_addr = Signal(intbv(0)[23:])
|
||||
flash_region = Signal(bool(0))
|
||||
flash_addr = Signal(intbv(0)[24:])
|
||||
flash_region = Signal(intbv(0)[2:])
|
||||
flash_region_oe = Signal(bool(0))
|
||||
flash_ce_n = Signal(bool(1))
|
||||
flash_oe_n = Signal(bool(1))
|
||||
@ -625,6 +626,7 @@ def bench():
|
||||
qsfp_modprsl=qsfp_modprsl,
|
||||
qsfp_intl=qsfp_intl,
|
||||
qsfp_lpmode=qsfp_lpmode,
|
||||
fpga_boot=fpga_boot,
|
||||
flash_dq_i=flash_dq_i,
|
||||
flash_dq_o=flash_dq_o,
|
||||
flash_dq_oe=flash_dq_oe,
|
||||
|
||||
@ -122,8 +122,8 @@ reg qsfp_rx_clk_4 = 0;
|
||||
reg qsfp_rx_rst_4 = 0;
|
||||
reg [63:0] qsfp_rxd_4 = 0;
|
||||
reg [7:0] qsfp_rxc_4 = 0;
|
||||
reg qsfp_modprsl = 1'b1;
|
||||
reg qsfp_intl = 1'b1;
|
||||
reg qsfp_modprsl = 1;
|
||||
reg qsfp_intl = 1;
|
||||
reg [15:0] flash_dq_i = 0;
|
||||
|
||||
// Outputs
|
||||
@ -173,10 +173,11 @@ wire [7:0] qsfp_txc_4;
|
||||
wire qsfp_modsell;
|
||||
wire qsfp_resetl;
|
||||
wire qsfp_lpmode;
|
||||
wire fpga_boot;
|
||||
wire [15:0] flash_dq_o;
|
||||
wire flash_dq_oe;
|
||||
wire [22:0] flash_addr;
|
||||
wire flash_region;
|
||||
wire [23:0] flash_addr;
|
||||
wire [1:0] flash_region;
|
||||
wire flash_region_oe;
|
||||
wire flash_ce_n;
|
||||
wire flash_oe_n;
|
||||
@ -305,6 +306,7 @@ initial begin
|
||||
qsfp_modsell,
|
||||
qsfp_resetl,
|
||||
qsfp_lpmode,
|
||||
fpga_boot,
|
||||
flash_dq_o,
|
||||
flash_dq_oe,
|
||||
flash_addr,
|
||||
@ -447,6 +449,7 @@ UUT (
|
||||
.qsfp_resetl(qsfp_resetl),
|
||||
.qsfp_intl(qsfp_intl),
|
||||
.qsfp_lpmode(qsfp_lpmode),
|
||||
.fpga_boot(fpga_boot),
|
||||
.flash_dq_i(flash_dq_i),
|
||||
.flash_dq_o(flash_dq_o),
|
||||
.flash_dq_oe(flash_dq_oe),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user