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merged changes in pcie

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This commit is contained in:
Alex Forencich 2019-08-03 23:33:15 -07:00
commit 13835c18a1
10 changed files with 63 additions and 34 deletions
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2
fpga/lib/pcie/rtl/pcie_axi_dma_desc_mux.v
View File

@ -91,7 +91,7 @@ parameter CL_PORTS = $clog2(PORTS);
// check configuration
initial begin
if (M_TAG_WIDTH < S_TAG_WIDTH+$clog2(PORTS)) begin
$error("Error: M_TAG_WIDTH must be at least $clog2(PORTS) larger than S_TAG_WIDTH");
$error("Error: M_TAG_WIDTH must be at least $clog2(PORTS) larger than S_TAG_WIDTH (instance %m)");
$finish;
end
end

8
fpga/lib/pcie/rtl/pcie_tag_manager.v
View File

@ -66,21 +66,21 @@ module pcie_tag_manager #
// parameter assertions
initial begin
if (PCIE_TAG_WIDTH < $clog2(PCIE_TAG_COUNT)) begin
$error("Error: PCIe tag width insufficient for requested tag count");
$error("Error: PCIe tag width insufficient for requested tag count (instance %m)");
$finish;
end
if (PCIE_TAG_COUNT < 1 || PCIE_TAG_COUNT > 256) begin
$error("Error: PCIe tag count must be between 1 and 256");
$error("Error: PCIe tag count must be between 1 and 256 (instance %m)");
$finish;
end
if (PCIE_TAG_COUNT > 32 && !PCIE_EXT_TAG_ENABLE) begin
$warning("Warning: PCIe tag count set larger than 32, but extended tag support is disabled");
$warning("Warning: PCIe tag count set larger than 32, but extended tag support is disabled (instance %m)");
end
if (PCIE_TAG_COUNT <= 32 && PCIE_EXT_TAG_ENABLE) begin
$warning("Warning: PCIe tag count set to 32 or less, but extended tag support is enabled");
$warning("Warning: PCIe tag count set to 32 or less, but extended tag support is enabled (instance %m)");
end
end

10
fpga/lib/pcie/rtl/pcie_us_axi_dma_rd.v
View File

@ -161,27 +161,27 @@ parameter STATUS_FIFO_ADDR_WIDTH = 5;
// bus width assertions
initial begin
if (AXIS_PCIE_DATA_WIDTH != 64 && AXIS_PCIE_DATA_WIDTH != 128 && AXIS_PCIE_DATA_WIDTH != 256) begin
$error("Error: PCIe interface width must be 64, 128, or 256");
$error("Error: PCIe interface width must be 64, 128, or 256 (instance %m)");
$finish;
end
if (AXIS_PCIE_KEEP_WIDTH * 32 != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: PCIe interface requires dword (32-bit) granularity");
$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
$finish;
end
if (AXI_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: AXI interface width must match PCIe interface width");
$error("Error: AXI interface width must match PCIe interface width (instance %m)");
$finish;
end
if (AXI_STRB_WIDTH * 8 != AXI_DATA_WIDTH) begin
$error("Error: AXI interface requires byte (8-bit) granularity");
$error("Error: AXI interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
if (AXI_MAX_BURST_LEN < 1 || AXI_MAX_BURST_LEN > 256) begin
$error("Error: AXI_MAX_BURST_LEN must be between 1 and 256");
$error("Error: AXI_MAX_BURST_LEN must be between 1 and 256 (instance %m)");
$finish;
end
end

12
fpga/lib/pcie/rtl/pcie_us_axi_dma_wr.v
View File

@ -123,30 +123,32 @@ parameter OFFSET_WIDTH = $clog2(AXI_DATA_WIDTH/8);
parameter WORD_LEN_WIDTH = LEN_WIDTH - $clog2(AXIS_PCIE_KEEP_WIDTH);
parameter CYCLE_COUNT_WIDTH = 13-AXI_BURST_SIZE;
parameter TLP_CMD_FIFO_ADDR_WIDTH = 3;
// bus width assertions
initial begin
if (AXIS_PCIE_DATA_WIDTH != 64 && AXIS_PCIE_DATA_WIDTH != 128 && AXIS_PCIE_DATA_WIDTH != 256) begin
$error("Error: PCIe interface width must be 64, 128, or 256");
$error("Error: PCIe interface width must be 64, 128, or 256 (instance %m)");
$finish;
end
if (AXIS_PCIE_KEEP_WIDTH * 32 != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: PCIe interface requires dword (32-bit) granularity");
$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
$finish;
end
if (AXI_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: AXI interface width must match PCIe interface width");
$error("Error: AXI interface width must match PCIe interface width (instance %m)");
$finish;
end
if (AXI_STRB_WIDTH * 8 != AXI_DATA_WIDTH) begin
$error("Error: AXI interface requires byte (8-bit) granularity");
$error("Error: AXI interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
if (AXI_MAX_BURST_LEN < 1 || AXI_MAX_BURST_LEN > 256) begin
$error("Error: AXI_MAX_BURST_LEN must be between 1 and 256");
$error("Error: AXI_MAX_BURST_LEN must be between 1 and 256 (instance %m)");
$finish;
end
end

10
fpga/lib/pcie/rtl/pcie_us_axi_master_rd.v
View File

@ -119,27 +119,27 @@ parameter OFFSET_WIDTH = $clog2(AXI_DATA_WIDTH/32);
// bus width assertions
initial begin
if (AXIS_PCIE_DATA_WIDTH != 64 && AXIS_PCIE_DATA_WIDTH != 128 && AXIS_PCIE_DATA_WIDTH != 256) begin
$error("Error: PCIe interface width must be 64, 128, or 256");
$error("Error: PCIe interface width must be 64, 128, or 256 (instance %m)");
$finish;
end
if (AXIS_PCIE_KEEP_WIDTH * 32 != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: PCIe interface requires dword (32-bit) granularity");
$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
$finish;
end
if (AXI_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: AXI interface width must match PCIe interface width");
$error("Error: AXI interface width must match PCIe interface width (instance %m)");
$finish;
end
if (AXI_STRB_WIDTH * 8 != AXI_DATA_WIDTH) begin
$error("Error: AXI interface requires byte (8-bit) granularity");
$error("Error: AXI interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
if (AXI_MAX_BURST_LEN < 1 || AXI_MAX_BURST_LEN > 256) begin
$error("Error: AXI_MAX_BURST_LEN must be between 1 and 256");
$error("Error: AXI_MAX_BURST_LEN must be between 1 and 256 (instance %m)");
$finish;
end
end

10
fpga/lib/pcie/rtl/pcie_us_axi_master_wr.v
View File

@ -102,27 +102,27 @@ parameter OFFSET_WIDTH = $clog2(AXIS_PCIE_DATA_WIDTH/32);
// bus width assertions
initial begin
if (AXIS_PCIE_DATA_WIDTH != 64 && AXIS_PCIE_DATA_WIDTH != 128 && AXIS_PCIE_DATA_WIDTH != 256) begin
$error("Error: PCIe interface width must be 64, 128, or 256");
$error("Error: PCIe interface width must be 64, 128, or 256 (instance %m)");
$finish;
end
if (AXIS_PCIE_KEEP_WIDTH * 32 != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: PCIe interface requires dword (32-bit) granularity");
$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
$finish;
end
if (AXI_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: AXI interface width must match PCIe interface width");
$error("Error: AXI interface width must match PCIe interface width (instance %m)");
$finish;
end
if (AXI_STRB_WIDTH * 8 != AXI_DATA_WIDTH) begin
$error("Error: AXI interface requires byte (8-bit) granularity");
$error("Error: AXI interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
if (AXI_MAX_BURST_LEN < 1 || AXI_MAX_BURST_LEN > 256) begin
$error("Error: AXI_MAX_BURST_LEN must be between 1 and 256");
$error("Error: AXI_MAX_BURST_LEN must be between 1 and 256 (instance %m)");
$finish;
end
end

8
fpga/lib/pcie/rtl/pcie_us_axil_master.v
View File

@ -107,22 +107,22 @@ module pcie_us_axil_master #
// bus width assertions
initial begin
if (AXIS_PCIE_DATA_WIDTH != 64 && AXIS_PCIE_DATA_WIDTH != 128 && AXIS_PCIE_DATA_WIDTH != 256) begin
$error("Error: PCIe interface width must be 64, 128, or 256");
$error("Error: PCIe interface width must be 64, 128, or 256 (instance %m)");
$finish;
end
if (AXIS_PCIE_KEEP_WIDTH * 32 != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: PCIe interface requires dword (32-bit) granularity");
$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
$finish;
end
if (AXI_DATA_WIDTH != 32) begin
$error("Error: AXI interface width must be 32");
$error("Error: AXI interface width must be 32 (instance %m)");
$finish;
end
if (AXI_STRB_WIDTH * 8 != AXI_DATA_WIDTH) begin
$error("Error: AXI interface requires byte (8-bit) granularity");
$error("Error: AXI interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
end

4
fpga/lib/pcie/rtl/pcie_us_axis_cq_demux.v
View File

@ -84,12 +84,12 @@ parameter CL_M_COUNT = $clog2(M_COUNT);
// bus width assertions
initial begin
if (AXIS_PCIE_DATA_WIDTH != 64 && AXIS_PCIE_DATA_WIDTH != 128 && AXIS_PCIE_DATA_WIDTH != 256) begin
$error("Error: PCIe interface width must be 64, 128, or 256");
$error("Error: PCIe interface width must be 64, 128, or 256 (instance %m)");
$finish;
end
if (AXIS_PCIE_KEEP_WIDTH * 32 != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: PCIe interface requires dword (32-bit) granularity");
$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
$finish;
end
end

4
fpga/lib/pcie/rtl/pcie_us_axis_rc_demux.v
View File

@ -80,12 +80,12 @@ parameter CL_M_COUNT = $clog2(M_COUNT);
// bus width assertions
initial begin
if (AXIS_PCIE_DATA_WIDTH != 64 && AXIS_PCIE_DATA_WIDTH != 128 && AXIS_PCIE_DATA_WIDTH != 256) begin
$error("Error: PCIe interface width must be 64, 128, or 256");
$error("Error: PCIe interface width must be 64, 128, or 256 (instance %m)");
$finish;
end
if (AXIS_PCIE_KEEP_WIDTH * 32 != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: PCIe interface requires dword (32-bit) granularity");
$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
$finish;
end
end

29
fpga/lib/pcie/scripts/pcie_force_gen2.sh → fpga/lib/pcie/scripts/pcie_set_speed.sh
View File

@ -1,6 +1,7 @@
#!/bin/bash
dev=$1
speed=$2
if [ -z "$dev" ]; then
echo "Error: no device specified"
@ -23,6 +24,24 @@ if [[ $port != pci* ]]; then
echo "Device $dev is connected to upstream port $port"
fi
lc=$(setpci -s $dev CAP_EXP+0c.L)
ls=$(setpci -s $dev CAP_EXP+12.W)
max_speed=$(("0x$lc" & 0xF))
echo "Link capabilities:" $lc
echo "Max link speed:" $max_speed
echo "Link status:" $ls
echo "Current link speed:" $(("0x$ls" & 0xF))
if [ -z "$speed" ]; then
speed=$max_speed
fi
if (($speed > $max_speed)); then
speed=$max_speed
fi
echo "Configuring $dev..."
lc2=$(setpci -s $dev CAP_EXP+30.L)
@ -30,8 +49,9 @@ lc2=$(setpci -s $dev CAP_EXP+30.L)
echo "Original link control 2:" $lc2
echo "Original link target speed:" $(("0x$lc2" & 0xF))
lc2n=$(printf "%08x" $((("0x$lc2" & 0xFFFFFFF0) | 0x2)))
lc2n=$(printf "%08x" $((("0x$lc2" & 0xFFFFFFF0) | $speed)))
echo "New target link speed:" $speed
echo "New link control 2:" $lc2n
setpci -s $dev CAP_EXP+30.L=$lc2n
@ -47,3 +67,10 @@ lcn=$(printf "%08x" $(("0x$lc" | 0x20)))
echo "New link control:" $lcn
setpci -s $dev CAP_EXP+10.L=$lcn
sleep 0.1
ls=$(setpci -s $dev CAP_EXP+12.W)
echo "Link status:" $ls
echo "Current link speed:" $(("0x$ls" & 0xF))