From 1486da601f32e405c33b2a33f067ddf2b67128d8 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 4 Sep 2022 12:03:35 -0700 Subject: [PATCH] fpga: Add clock period parameters Signed-off-by: Alex Forencich --- docs/source/modules/mqnic_app_block.rst | 8 ++++++++ docs/source/modules/mqnic_core.rst | 8 ++++++++ fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v | 4 ++++ fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile | 8 ++++++++ .../tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py | 4 ++++ fpga/app/template/rtl/mqnic_app_block.v | 4 ++++ fpga/app/template/tb/mqnic_core_pcie_us/Makefile | 8 ++++++++ .../tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py | 4 ++++ fpga/common/rtl/mqnic_core.v | 8 ++++++++ fpga/common/rtl/mqnic_core_axi.v | 8 ++++++++ fpga/common/rtl/mqnic_core_pcie.v | 8 ++++++++ fpga/common/rtl/mqnic_core_pcie_ptile.v | 8 ++++++++ fpga/common/rtl/mqnic_core_pcie_s10.v | 8 ++++++++ fpga/common/rtl/mqnic_core_pcie_us.v | 8 ++++++++ fpga/common/tb/mqnic_core_axi/Makefile | 8 ++++++++ fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py | 4 ++++ fpga/common/tb/mqnic_core_pcie_ptile/Makefile | 8 ++++++++ .../mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py | 4 ++++ fpga/common/tb/mqnic_core_pcie_s10/Makefile | 8 ++++++++ .../tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py | 4 ++++ fpga/common/tb/mqnic_core_pcie_us/Makefile | 8 ++++++++ .../tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py | 4 ++++ fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile | 8 ++++++++ .../tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py | 4 ++++ fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl | 4 ++++ fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile | 8 ++++++++ .../250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl | 4 ++++ fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl | 4 ++++ fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile | 8 ++++++++ .../mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl | 4 ++++ fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl | 4 ++++ fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile | 8 ++++++++ .../ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl | 4 ++++ fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl | 4 ++++ fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl | 4 ++++ fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile | 8 ++++++++ .../ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/AU200/fpga_100g/fpga/config.tcl | 4 ++++ fpga/mqnic/AU200/fpga_100g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile | 8 ++++++++ fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/AU200/fpga_25g/fpga/config.tcl | 4 ++++ fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl | 4 ++++ fpga/mqnic/AU200/fpga_25g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile | 8 ++++++++ fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/AU250/fpga_100g/fpga/config.tcl | 4 ++++ fpga/mqnic/AU250/fpga_100g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile | 8 ++++++++ fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/AU250/fpga_25g/fpga/config.tcl | 4 ++++ fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl | 4 ++++ fpga/mqnic/AU250/fpga_25g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile | 8 ++++++++ fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/AU280/fpga_100g/fpga/config.tcl | 4 ++++ fpga/mqnic/AU280/fpga_100g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile | 8 ++++++++ fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/AU280/fpga_25g/fpga/config.tcl | 4 ++++ fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl | 4 ++++ fpga/mqnic/AU280/fpga_25g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile | 8 ++++++++ fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/AU50/fpga_100g/fpga/config.tcl | 4 ++++ fpga/mqnic/AU50/fpga_100g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile | 8 ++++++++ fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/AU50/fpga_25g/fpga/config.tcl | 4 ++++ fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl | 4 ++++ fpga/mqnic/AU50/fpga_25g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile | 8 ++++++++ fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/config.tcl | 4 ++++ fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24B/config.tcl | 4 ++++ fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile | 8 ++++++++ .../DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/config.tcl | 4 ++++ fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24B/config.tcl | 4 ++++ fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/config.tcl | 4 ++++ fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24B/config.tcl | 4 ++++ fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile | 8 ++++++++ .../DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py | 4 ++++ .../DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl | 4 ++++ .../DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl | 4 ++++ fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v | 8 ++++++++ fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v | 8 ++++++++ .../DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile | 8 ++++++++ .../fpga/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl | 4 ++++ fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v | 8 ++++++++ fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile | 8 ++++++++ .../NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl | 4 ++++ fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v | 8 ++++++++ fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile | 8 ++++++++ .../mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl | 4 ++++ fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl | 4 ++++ fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile | 8 ++++++++ .../Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl | 4 ++++ fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl | 4 ++++ fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile | 8 ++++++++ .../Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/S10DX_DK/fpga_25g/fpga/config.tcl | 4 ++++ fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/config.tcl | 4 ++++ fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile | 8 ++++++++ .../S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/config.tcl | 4 ++++ fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/config.tcl | 4 ++++ fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/config.tcl | 4 ++++ fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/config.tcl | 4 ++++ fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile | 8 ++++++++ .../S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl | 4 ++++ fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl | 4 ++++ fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile | 8 ++++++++ fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl | 4 ++++ fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile | 8 ++++++++ .../mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl | 4 ++++ fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl | 4 ++++ fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile | 8 ++++++++ fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl | 4 ++++ fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile | 8 ++++++++ .../VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl | 4 ++++ fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl | 4 ++++ fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile | 8 ++++++++ .../mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl | 4 ++++ fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile | 8 ++++++++ .../mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl | 4 ++++ fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl | 4 ++++ fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile | 8 ++++++++ fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/ZCU102/fpga/fpga/config.tcl | 4 ++++ fpga/mqnic/ZCU102/fpga/rtl/fpga.v | 8 ++++++++ fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile | 8 ++++++++ fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl | 4 ++++ fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v | 8 ++++++++ fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile | 8 ++++++++ .../mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl | 4 ++++ fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v | 8 ++++++++ fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile | 8 ++++++++ .../ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl | 4 ++++ fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl | 4 ++++ fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl | 4 ++++ fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl | 4 ++++ fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile | 8 ++++++++ fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py | 4 ++++ fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl | 4 ++++ fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl | 4 ++++ fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl | 4 ++++ fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v | 8 ++++++++ fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v | 8 ++++++++ fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile | 8 ++++++++ fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py | 4 ++++ 217 files changed, 1324 insertions(+) diff --git a/docs/source/modules/mqnic_app_block.rst b/docs/source/modules/mqnic_app_block.rst index 4a12de2e3..3f752d7fd 100644 --- a/docs/source/modules/mqnic_app_block.rst +++ b/docs/source/modules/mqnic_app_block.rst @@ -74,6 +74,14 @@ Parameters Total port count, must be set to ``IF_COUNT*PORTS_PER_IF``. +.. object:: CLK_PERIOD_NS_NUM + + Numerator of core clock period in ns, default ``4``. + +.. object:: CLK_PERIOD_NS_DENOM + + Denominator of core clock period in ns, default ``1``. + .. object:: PTP_CLK_PERIOD_NS_NUM Numerator of PTP clock period in ns, default ``4``. diff --git a/docs/source/modules/mqnic_core.rst b/docs/source/modules/mqnic_core.rst index 16963297b..316ccac47 100644 --- a/docs/source/modules/mqnic_core.rst +++ b/docs/source/modules/mqnic_core.rst @@ -69,6 +69,14 @@ Parameters Total port count, must be set to ``IF_COUNT*PORTS_PER_IF``. +.. object:: CLK_PERIOD_NS_NUM + + Numerator of core clock period in ns, default ``4``. + +.. object:: CLK_PERIOD_NS_DENOM + + Denominator of core clock period in ns, default ``1``. + .. object:: PTP_CLK_PERIOD_NS_NUM Numerator of PTP clock period in ns, default ``4``. diff --git a/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v b/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v index 4c78ba615..dfb8a98a9 100644 --- a/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v +++ b/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v @@ -49,6 +49,10 @@ module mqnic_app_block # parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 4, parameter PTP_CLK_PERIOD_NS_DENOM = 1, diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile index 5c6e48f2f..41f47cfaa 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile @@ -138,6 +138,10 @@ export PARAM_IF_COUNT ?= 1 export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5 @@ -255,6 +259,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -351,6 +357,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index b1c4d4968..f22c9e76f 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -958,6 +958,10 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['PORTS_PER_IF'] = ports_per_if parameters['SCHED_PER_IF'] = ports_per_if + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 32 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 diff --git a/fpga/app/template/rtl/mqnic_app_block.v b/fpga/app/template/rtl/mqnic_app_block.v index ecefd2d98..6c91d79f1 100644 --- a/fpga/app/template/rtl/mqnic_app_block.v +++ b/fpga/app/template/rtl/mqnic_app_block.v @@ -49,6 +49,10 @@ module mqnic_app_block # parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 4, parameter PTP_CLK_PERIOD_NS_DENOM = 1, diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile index 989afa81c..dcab5f92a 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile @@ -137,6 +137,10 @@ export PARAM_IF_COUNT ?= 1 export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5 @@ -254,6 +258,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -350,6 +356,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 9ad6d2523..f4272300f 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -798,6 +798,10 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['PORTS_PER_IF'] = ports_per_if parameters['SCHED_PER_IF'] = ports_per_if + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 32 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 diff --git a/fpga/common/rtl/mqnic_core.v b/fpga/common/rtl/mqnic_core.v index a91753b05..edbc26df9 100644 --- a/fpga/common/rtl/mqnic_core.v +++ b/fpga/common/rtl/mqnic_core.v @@ -59,6 +59,10 @@ module mqnic_core # parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 4, parameter PTP_CLK_PERIOD_NS_DENOM = 1, @@ -2888,6 +2892,10 @@ if (APP_ENABLE) begin : app .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/common/rtl/mqnic_core_axi.v b/fpga/common/rtl/mqnic_core_axi.v index fcd994d5e..5219052ef 100644 --- a/fpga/common/rtl/mqnic_core_axi.v +++ b/fpga/common/rtl/mqnic_core_axi.v @@ -59,6 +59,10 @@ module mqnic_core_axi # parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 4, parameter PTP_CLK_PERIOD_NS_DENOM = 1, @@ -819,6 +823,10 @@ mqnic_core #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/common/rtl/mqnic_core_pcie.v b/fpga/common/rtl/mqnic_core_pcie.v index 0db81f21c..358e9ba43 100644 --- a/fpga/common/rtl/mqnic_core_pcie.v +++ b/fpga/common/rtl/mqnic_core_pcie.v @@ -59,6 +59,10 @@ module mqnic_core_pcie # parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 4, parameter PTP_CLK_PERIOD_NS_DENOM = 1, @@ -1451,6 +1455,10 @@ mqnic_core #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/common/rtl/mqnic_core_pcie_ptile.v b/fpga/common/rtl/mqnic_core_pcie_ptile.v index fbe8ef90b..6ffb463e1 100644 --- a/fpga/common/rtl/mqnic_core_pcie_ptile.v +++ b/fpga/common/rtl/mqnic_core_pcie_ptile.v @@ -59,6 +59,10 @@ module mqnic_core_pcie_ptile # parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 4, parameter PTP_CLK_PERIOD_NS_DENOM = 1, @@ -616,6 +620,10 @@ mqnic_core_pcie #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/common/rtl/mqnic_core_pcie_s10.v b/fpga/common/rtl/mqnic_core_pcie_s10.v index 5f56174df..3561ae6a2 100644 --- a/fpga/common/rtl/mqnic_core_pcie_s10.v +++ b/fpga/common/rtl/mqnic_core_pcie_s10.v @@ -59,6 +59,10 @@ module mqnic_core_pcie_s10 # parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 4, parameter PTP_CLK_PERIOD_NS_DENOM = 1, @@ -625,6 +629,10 @@ mqnic_core_pcie #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/common/rtl/mqnic_core_pcie_us.v b/fpga/common/rtl/mqnic_core_pcie_us.v index 772bddc9a..0bd7d5719 100644 --- a/fpga/common/rtl/mqnic_core_pcie_us.v +++ b/fpga/common/rtl/mqnic_core_pcie_us.v @@ -59,6 +59,10 @@ module mqnic_core_pcie_us # parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 4, parameter PTP_CLK_PERIOD_NS_DENOM = 1, @@ -746,6 +750,10 @@ mqnic_core_pcie #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/common/tb/mqnic_core_axi/Makefile b/fpga/common/tb/mqnic_core_axi/Makefile index d6d953f5b..2ab6c0cbb 100644 --- a/fpga/common/tb/mqnic_core_axi/Makefile +++ b/fpga/common/tb/mqnic_core_axi/Makefile @@ -121,6 +121,10 @@ export PARAM_IF_COUNT ?= 1 export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5 @@ -238,6 +242,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -334,6 +340,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py index 7c19855aa..f83e0c110 100644 --- a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py +++ b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py @@ -554,6 +554,10 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width, parameters['PORTS_PER_IF'] = ports_per_if parameters['SCHED_PER_IF'] = ports_per_if + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 32 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile index df5738956..d67e9cc79 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile @@ -136,6 +136,10 @@ export PARAM_IF_COUNT ?= 1 export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5 @@ -259,6 +263,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -361,6 +367,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py index 9730a5b7f..e65dde19f 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py +++ b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py @@ -769,6 +769,10 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width, parameters['PORTS_PER_IF'] = ports_per_if parameters['SCHED_PER_IF'] = ports_per_if + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 32 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 diff --git a/fpga/common/tb/mqnic_core_pcie_s10/Makefile b/fpga/common/tb/mqnic_core_pcie_s10/Makefile index 71b7fa64c..5e0dddf25 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_s10/Makefile @@ -135,6 +135,10 @@ export PARAM_IF_COUNT ?= 1 export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5 @@ -257,6 +261,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -358,6 +364,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py index c783f3079..0a3cac2de 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py +++ b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py @@ -716,6 +716,10 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width, parameters['PORTS_PER_IF'] = ports_per_if parameters['SCHED_PER_IF'] = ports_per_if + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 32 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 diff --git a/fpga/common/tb/mqnic_core_pcie_us/Makefile b/fpga/common/tb/mqnic_core_pcie_us/Makefile index 1e7b82efc..49ad787ec 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us/Makefile @@ -135,6 +135,10 @@ export PARAM_IF_COUNT ?= 1 export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5 @@ -252,6 +256,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -348,6 +354,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 916db6866..38de1e240 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -790,6 +790,10 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['PORTS_PER_IF'] = ports_per_if parameters['SCHED_PER_IF'] = ports_per_if + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 32 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile index 18b0fa471..32e3f7b0f 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile @@ -137,6 +137,10 @@ export PARAM_IF_COUNT ?= 1 export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5 @@ -254,6 +258,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -350,6 +356,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py index 900ba8f86..edbca35bf 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py @@ -845,6 +845,10 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt parameters['PORTS_PER_IF'] = ports_per_if parameters['SCHED_PER_IF'] = ports_per_if + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 32 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl b/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl index e898b4ce4..b83ad613f 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl @@ -86,6 +86,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v index 8257f8d19..95031c4d8 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v @@ -58,6 +58,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1566,6 +1570,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v index 598b69f12..baaaf4347 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v @@ -58,6 +58,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 512, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -763,6 +767,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile index 7467bb5d4..5fb791757 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile @@ -139,6 +139,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 512 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -250,6 +254,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -340,6 +346,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py index c923171d4..74b2bd213 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -718,6 +718,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 512 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl b/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl index cba6e6375..abfa02265 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl index 4bb1c6edf..f93942eaa 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v index 26eeec7e1..9d69dffc2 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v @@ -61,6 +61,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1166,6 +1170,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v index 745d84da9..9b455daf4 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v @@ -61,6 +61,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 512, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -1030,6 +1034,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile index f71695b10..68072b9ac 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile @@ -147,6 +147,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 512 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -257,6 +261,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -346,6 +352,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py index 4b9c1258f..cc6b76e83 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -785,6 +785,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 512 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl index ecac3a57a..c5b86e09b 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl @@ -86,6 +86,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl index e9cfc071c..b55ec5b84 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl @@ -86,6 +86,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v index dbcc1614e..767ab5600 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v @@ -58,6 +58,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1769,6 +1773,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v index 8ad19084a..bf14c05b8 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v @@ -58,6 +58,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 1024, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -832,6 +836,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile index e7f4d381d..e5852da44 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile @@ -139,6 +139,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -250,6 +254,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -340,6 +346,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py index 56e331035..e736d7771 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -718,6 +718,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl index 8568233b4..efc928bce 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl index cd73f6b3c..f30df7a36 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl index b30dbb2cf..26d305dbe 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v index b4a67e564..fa6fb1734 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v @@ -61,6 +61,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1370,6 +1374,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index 2b557a4d2..731ed070e 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -61,6 +61,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 1024, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -1098,6 +1102,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile index fa781ff23..30ca622f1 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile @@ -147,6 +147,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -257,6 +261,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -346,6 +352,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py index 506a013cb..a59cda0f9 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -785,6 +785,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl index 77d06d90f..cd99ce297 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl @@ -86,6 +86,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v index c9fed5bb7..bb00e2e2b 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v @@ -58,6 +58,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1902,6 +1906,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v index 182b0ad56..961708d04 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v @@ -58,6 +58,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 1024, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -840,6 +844,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile index 84164f9c6..2a60d9d0d 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile @@ -139,6 +139,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -250,6 +254,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -340,6 +346,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py index e2d62745d..8f81405f5 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -718,6 +718,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl index 4280ff209..95d71a0c7 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl index a50986019..67ff1e397 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v index a8e8f8e61..2d1e439ca 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v @@ -61,6 +61,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1503,6 +1507,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v index 02b1c92e4..88fcc1762 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v @@ -61,6 +61,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 1024, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -1107,6 +1111,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile index 5780ed6f8..2d0efaf0c 100644 --- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile @@ -147,6 +147,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -257,6 +261,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -346,6 +352,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py index 9e8664926..4bf49efbb 100644 --- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -785,6 +785,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl index 643f1b399..90dea6058 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl @@ -86,6 +86,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v index ad7cd4bf0..cdc01eaa4 100644 --- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v @@ -58,6 +58,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1902,6 +1906,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v index ce7e9b3b4..322e86cd6 100644 --- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v @@ -58,6 +58,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 1024, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -840,6 +844,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile index 84164f9c6..2a60d9d0d 100644 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile @@ -139,6 +139,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -250,6 +254,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -340,6 +346,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py index e2d62745d..8f81405f5 100644 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -718,6 +718,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl index 4942fc56c..c3633f8b9 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl index 15d93732a..cdb1450bf 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v index 65d3db060..87b724c48 100644 --- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v @@ -61,6 +61,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1503,6 +1507,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v index 284b285e3..ce863e687 100644 --- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v @@ -61,6 +61,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 1024, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -1107,6 +1111,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile index 5780ed6f8..2d0efaf0c 100644 --- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile @@ -147,6 +147,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -257,6 +261,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -346,6 +352,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py index 9e8664926..4bf49efbb 100644 --- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -785,6 +785,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl index 2e5b1e375..913ee7e3b 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl @@ -86,6 +86,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "1" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v index 112e6668f..ee080b5cb 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v @@ -58,6 +58,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 1, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1799,6 +1803,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v index 06ad363e9..20b0f3cc0 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v @@ -58,6 +58,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 1024, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -729,6 +733,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile index 67fa0e4e8..1a1a48795 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile @@ -139,6 +139,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -250,6 +254,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -340,6 +346,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py index 772c05f16..1d1068c89 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -707,6 +707,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl index f34a926f0..ab9b890da 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "1" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl index cb15dc695..6c4dbeeb5 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "1" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v index e173e5326..2f6479890 100644 --- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v @@ -61,6 +61,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 1, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1406,6 +1410,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v index bdc7e6206..8150d0708 100644 --- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v @@ -61,6 +61,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 1024, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -996,6 +1000,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile index e96228946..51ffb00a9 100644 --- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile @@ -147,6 +147,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -257,6 +261,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -346,6 +352,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py index 78663f605..c525d19fa 100644 --- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -774,6 +774,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl index 8cd880867..5ad3e79b4 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl @@ -86,6 +86,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "1" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v index f7a43cacd..6e293f7e3 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v @@ -58,6 +58,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 1, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1364,6 +1368,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v index a3ef4285e..017578a4f 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v @@ -58,6 +58,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 1024, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -706,6 +710,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile index 0f1050e45..046ed756b 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile @@ -139,6 +139,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -250,6 +254,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -340,6 +346,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py index 04c0bb4e8..93a785510 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -667,6 +667,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl index a2789a524..5bffa3f7f 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "1" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl index 54a71dc5b..6f5194c8b 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "1" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v index 417235dd3..ed06a1419 100644 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v @@ -61,6 +61,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 1, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1168,6 +1172,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v index 216fc94b1..940db81db 100644 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v @@ -61,6 +61,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 1024, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -892,6 +896,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile index 564f5bd15..bbc385195 100644 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile @@ -147,6 +147,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -257,6 +261,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -346,6 +352,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py index 79ba1c395..c719202e1 100644 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -694,6 +694,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/config.tcl index 695c5c205..46d9084b8 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24AR0/config.tcl @@ -85,6 +85,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24B/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24B/config.tcl index 1cc9da5ff..4c131ad72 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24B/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_24B/config.tcl @@ -85,6 +85,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v index bdf116c46..61a57cb73 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v @@ -58,6 +58,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -734,6 +738,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v index ef2d41e37..b126f455e 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v @@ -58,6 +58,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 2048, parameter PTP_CLK_PERIOD_NS_DENOM = 825, @@ -749,6 +753,10 @@ mqnic_core_pcie_ptile #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile index 4ff2e068c..332749ae3 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile @@ -147,6 +147,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 2048 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 825 @@ -260,6 +264,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -352,6 +358,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py index cc495c8e4..271c27c76 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -743,6 +743,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 2048 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 825 diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/config.tcl index f345989b6..9f8baf1d8 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24AR0/config.tcl @@ -85,6 +85,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24B/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24B/config.tcl index baa2dff5b..f61c8c393 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24B/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_10g_24B/config.tcl @@ -85,6 +85,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/config.tcl index f4575a289..71f04c6b7 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24AR0/config.tcl @@ -85,6 +85,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24B/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24B/config.tcl index 3c524ab45..b05afdc13 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24B/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga_24B/config.tcl @@ -85,6 +85,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v index 3165b896b..651a79ae3 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga.v @@ -58,6 +58,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1630,6 +1634,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v index 9609b9bd0..01242d0c7 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v @@ -58,6 +58,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 2048, parameter PTP_CLK_PERIOD_NS_DENOM = 825, @@ -1183,6 +1187,10 @@ mqnic_core_pcie_ptile #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile index 25065fb71..78424a40a 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/Makefile @@ -147,6 +147,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 2048 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 825 @@ -262,6 +266,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -356,6 +362,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py index 54f3d2035..b69624dce 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -1063,6 +1063,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 2048 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 825 diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl index 3924755d4..e192b94b0 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl @@ -89,6 +89,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl index 83397fc0d..bae242832 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl @@ -89,6 +89,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v index 8e9060f6c..234121d0c 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v @@ -61,6 +61,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1356,6 +1360,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v index 4266d2137..ba09e3678 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v @@ -61,6 +61,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 32, parameter PTP_CLK_PERIOD_NS_DENOM = 5, @@ -1126,6 +1130,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile index 7fd08307e..e5c462886 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile @@ -147,6 +147,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5 @@ -257,6 +261,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -346,6 +352,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py index 33ac339fb..96194eae9 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py @@ -749,6 +749,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 32 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl index fb6b96501..752230505 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl +++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl @@ -86,6 +86,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v index 825ebfae7..40bfd0a08 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v +++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v @@ -58,6 +58,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1311,6 +1315,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v index 19038f3e6..00179feeb 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v @@ -58,6 +58,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 32, parameter PTP_CLK_PERIOD_NS_DENOM = 5, @@ -728,6 +732,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile index 9dc0c01aa..700a984c8 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile @@ -146,6 +146,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5 @@ -256,6 +260,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -345,6 +351,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py index dd518019a..642ba979f 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py @@ -671,6 +671,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 32 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 diff --git a/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl b/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl index f6a90825f..0fbc7258a 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl @@ -86,6 +86,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v index dcb43513e..8d32af58c 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v @@ -58,6 +58,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1026,6 +1030,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v index 1bc3f6956..f54c45f25 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v @@ -58,6 +58,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 1024, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -882,6 +886,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile index f1da89dcd..f63c03e03 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile @@ -147,6 +147,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -257,6 +261,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -346,6 +352,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py index 8b4f6163b..a20d1d169 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py @@ -660,6 +660,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl index 1a6f27024..c209677b3 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl index f23df276f..735b75d6c 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v index f4e3de535..6304f17af 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v @@ -61,6 +61,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1298,6 +1302,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v index 9cdbedabd..1994d4d74 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v @@ -61,6 +61,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 1024, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -1162,6 +1166,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile index a485873f7..80316b466 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile @@ -147,6 +147,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -257,6 +261,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -346,6 +352,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py index 3eb06f5cd..85fa84eef 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -789,6 +789,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl index 10499efea..facb426f9 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl index 49e25d33e..f846fe75d 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v index d7c02acc3..3d6f2777d 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v @@ -61,6 +61,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1067,6 +1071,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v index 9e108e524..bc933faa5 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v @@ -61,6 +61,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 1024, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -980,6 +984,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile index a485873f7..80316b466 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile @@ -147,6 +147,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -257,6 +261,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -346,6 +352,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py index f50d9b026..a1241e8ca 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -689,6 +689,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/fpga/config.tcl b/fpga/mqnic/S10DX_DK/fpga_25g/fpga/config.tcl index ae7a3085f..1a186eb04 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/S10DX_DK/fpga_25g/fpga/config.tcl @@ -85,6 +85,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/config.tcl index 7df2811ed..7286d6934 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/S10DX_DK/fpga_25g/fpga_10g/config.tcl @@ -85,6 +85,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga.v b/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga.v index 6a62bb1e6..713f65bbd 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga.v @@ -58,6 +58,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1015,6 +1019,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v index a14b7bced..5326291b4 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v @@ -58,6 +58,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 4096, parameter PTP_CLK_PERIOD_NS_DENOM = 825, @@ -909,6 +913,10 @@ mqnic_core_pcie_ptile #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile index a804bd486..cb50bfecc 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/Makefile @@ -144,6 +144,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 4096 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 825 @@ -259,6 +263,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -353,6 +359,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py index 303917209..acc71c78a 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/S10DX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -853,6 +853,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 4096 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 825 diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/config.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/config.tcl index 53b9523cc..07fc75b01 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/config.tcl +++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/config.tcl @@ -89,6 +89,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/config.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/config.tcl index 40c31841f..d102a6d1e 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/config.tcl +++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/config.tcl @@ -89,6 +89,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/config.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/config.tcl index 870edbd96..c936fb260 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/config.tcl +++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/config.tcl @@ -89,6 +89,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/config.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/config.tcl index 8746019aa..baae5e744 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/config.tcl +++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/config.tcl @@ -89,6 +89,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga.v b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga.v index e0781aa3b..e455eae19 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga.v @@ -61,6 +61,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -961,6 +965,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v index bc75d3d60..dc12dc3e4 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v @@ -61,6 +61,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 32, parameter PTP_CLK_PERIOD_NS_DENOM = 5, @@ -837,6 +841,10 @@ mqnic_core_pcie_s10 #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile index ba2ab69d8..3e55b3910 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile @@ -146,6 +146,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -259,6 +263,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -351,6 +357,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py index cdf263f16..347956445 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -694,6 +694,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl index 3358cb86e..6cc943b73 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl index de4d671ec..1aa474d58 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v index e02111c64..da25c608c 100644 --- a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v @@ -61,6 +61,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1132,6 +1136,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v index 73d035067..d4f19ef5a 100644 --- a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v @@ -61,6 +61,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 32, parameter PTP_CLK_PERIOD_NS_DENOM = 5, @@ -932,6 +936,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile index 5ffc98154..1d3ce9e28 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile @@ -147,6 +147,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5 @@ -257,6 +261,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -346,6 +352,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py index 1cee73992..a89bf28bc 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -681,6 +681,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 32 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl index f97126958..00cec4d1c 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl @@ -86,6 +86,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v index 3506f0984..ab3440d77 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v @@ -58,6 +58,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1756,6 +1760,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v index 1ff0dce2e..dffdba871 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v @@ -58,6 +58,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 32, parameter PTP_CLK_PERIOD_NS_DENOM = 5, @@ -808,6 +812,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile index f2675120f..2e9101c82 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile @@ -139,6 +139,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5 @@ -250,6 +254,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -340,6 +346,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py index 01d2ebaf6..fffd29fdd 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -722,6 +722,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 32 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl index 1232671c8..284b765bc 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl index e43dfc373..08a8177ea 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v index cb0d3fc78..248869390 100644 --- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v @@ -61,6 +61,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1356,6 +1360,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v index c3d6a87ac..53e497d4d 100644 --- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v @@ -61,6 +61,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 32, parameter PTP_CLK_PERIOD_NS_DENOM = 5, @@ -1075,6 +1079,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile index e59d06565..fbe3d3237 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile @@ -147,6 +147,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5 @@ -257,6 +261,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -346,6 +352,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py index 5ee3fa1cf..488e1419b 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -789,6 +789,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 32 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl index 472943e8e..686875baf 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl @@ -86,6 +86,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v index e69380204..9b36792eb 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v @@ -58,6 +58,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1747,6 +1751,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v index 11f0dac16..2c7407447 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v @@ -58,6 +58,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 1024, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -763,6 +767,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile index 84164f9c6..2a60d9d0d 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile @@ -139,6 +139,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -250,6 +254,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -340,6 +346,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py index deb686c28..5e89dc1fb 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -716,6 +716,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl index 15a9c2ec4..064601017 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl index 78bc81886..9822704b5 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v index 7e2cb0350..34c4ac6e1 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v @@ -61,6 +61,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1348,6 +1352,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v index dc5cdd5ff..9cbb67657 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v @@ -61,6 +61,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 1024, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -1030,6 +1034,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile index 5780ed6f8..2d0efaf0c 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile @@ -147,6 +147,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -257,6 +261,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -346,6 +352,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py index caaf8e501..c907a7fc9 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -783,6 +783,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl index cc162ef7d..92cdad8f3 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl @@ -86,6 +86,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v index f32527a10..90c23534d 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v @@ -58,6 +58,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -2682,6 +2686,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v index 336700002..547b78e4c 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v @@ -58,6 +58,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 512, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -1019,6 +1023,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile index a7405d409..92cbcaa50 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile @@ -139,6 +139,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 512 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -250,6 +254,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -340,6 +346,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py index be7f9c53f..5c7899f4f 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -786,6 +786,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 512 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl index 682a4ebaf..dd1520fae 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl index 48e3e64f0..fec4223cb 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v index c9485758a..7398545df 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v @@ -61,6 +61,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1883,6 +1887,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v index b3cdf229e..e61c65a57 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v @@ -61,6 +61,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 512, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -1449,6 +1453,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile index bcb46e150..403fb4214 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile @@ -147,6 +147,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 512 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -257,6 +261,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -346,6 +352,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py index 61bd892e8..e38ff47aa 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -933,6 +933,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 512 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/ZCU102/fpga/fpga/config.tcl b/fpga/mqnic/ZCU102/fpga/fpga/config.tcl index 543cfeea1..9998d9ee9 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga/config.tcl +++ b/fpga/mqnic/ZCU102/fpga/fpga/config.tcl @@ -81,6 +81,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "10" +dict set params CLK_PERIOD_NS_DENOM "3" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v index 146fcc660..bd5052257 100644 --- a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v +++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v @@ -61,6 +61,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 10, + parameter CLK_PERIOD_NS_DENOM = 3, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -788,6 +792,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v index 72e39ee53..5910c3b85 100644 --- a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v @@ -61,6 +61,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 10, + parameter CLK_PERIOD_NS_DENOM = 3, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 32, parameter PTP_CLK_PERIOD_NS_DENOM = 5, @@ -795,6 +799,10 @@ mqnic_core_axi #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile index 942393614..f3dece5af 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile @@ -131,6 +131,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 10 +export PARAM_CLK_PERIOD_NS_DENOM = 3 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5 @@ -234,6 +238,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -318,6 +324,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py index 31aa7dea0..9e6b0d1fa 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py @@ -474,6 +474,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 10 + parameters['CLK_PERIOD_NS_DENOM'] = 3 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 32 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl index f60a0100a..752e8fe3f 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl @@ -89,6 +89,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v index 2d1be4fcf..d64c73890 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v @@ -61,6 +61,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -843,6 +847,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v index 27c2b81b7..2d6822928 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v @@ -61,6 +61,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 32, parameter PTP_CLK_PERIOD_NS_DENOM = 5, @@ -790,6 +794,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile index 40ed31c01..e75da58f6 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile @@ -147,6 +147,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5 @@ -257,6 +261,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -346,6 +352,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py index 064b0fa3f..7f7701dc4 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py @@ -683,6 +683,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 32 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl index b63033c89..248dc68c4 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl @@ -81,6 +81,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "10" +dict set params CLK_PERIOD_NS_DENOM "3" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v index 73f4f18b7..612743d44 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v @@ -61,6 +61,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 10, + parameter CLK_PERIOD_NS_DENOM = 3, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -709,6 +713,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v index 36010173e..d51c04a0f 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v @@ -61,6 +61,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 10, + parameter CLK_PERIOD_NS_DENOM = 3, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 32, parameter PTP_CLK_PERIOD_NS_DENOM = 5, @@ -749,6 +753,10 @@ mqnic_core_axi #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile index 942393614..f3dece5af 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile @@ -131,6 +131,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 10 +export PARAM_CLK_PERIOD_NS_DENOM = 3 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 32 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5 @@ -234,6 +238,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -318,6 +324,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py index 924d5e129..dd53b5706 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py @@ -444,6 +444,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 10 + parameters['CLK_PERIOD_NS_DENOM'] = 3 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 32 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl index caf22d8d4..5d7e274b1 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl @@ -86,6 +86,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl index 3c8ffaeea..1cb23f7b1 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl @@ -93,6 +93,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl index d47174f78..c53b86f80 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl @@ -86,6 +86,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl index 8d762cf63..5b4d55278 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl @@ -86,6 +86,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v index 1786f687d..7d23de2e3 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v @@ -58,6 +58,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1785,6 +1789,10 @@ fpga_core #( .SCHED_PER_IF(SCHED_PER_IF), .PORT_MASK(PORT_MASK), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v index 4c3bc4f04..c067653c2 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v @@ -58,6 +58,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 1024, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -865,6 +869,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile index deb724df1..870042e38 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile @@ -140,6 +140,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -251,6 +255,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -341,6 +347,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py index 0caf7b40c..7e5afeeb5 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -723,6 +723,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl index 6d6c7fe0d..dd3d5e842 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl index 517119223..98342c885 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl index ef72a18f7..124dee6f2 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl @@ -98,6 +98,10 @@ dict set params PORTS_PER_IF "1" dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] dict set params PORT_MASK "0" +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + # PTP configuration dict set params PTP_CLOCK_PIPELINE "0" dict set params PTP_CLOCK_CDC_PIPELINE "0" diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v index e6a417f46..01a26d981 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v @@ -61,6 +61,10 @@ module fpga # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLOCK_PIPELINE = 0, parameter PTP_CLOCK_CDC_PIPELINE = 0, @@ -1390,6 +1394,10 @@ fpga_core #( // Board configuration .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // Structural configuration .IF_COUNT(IF_COUNT), .PORTS_PER_IF(PORTS_PER_IF), diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v index 194f5b739..a15a3c14d 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v @@ -61,6 +61,10 @@ module fpga_core # parameter SCHED_PER_IF = PORTS_PER_IF, parameter PORT_MASK = 0, + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + // PTP configuration parameter PTP_CLK_PERIOD_NS_NUM = 1024, parameter PTP_CLK_PERIOD_NS_DENOM = 165, @@ -1131,6 +1135,10 @@ mqnic_core_pcie_us #( .PORT_COUNT(PORT_COUNT), + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + // PTP configuration .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile index 4b37f3d46..825e5c1f5 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile @@ -148,6 +148,10 @@ export PARAM_PORTS_PER_IF ?= 1 export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) export PARAM_PORT_MASK ?= 0 +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM = 4 +export PARAM_CLK_PERIOD_NS_DENOM = 1 + # PTP configuration export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024 export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165 @@ -258,6 +262,8 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).CLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) @@ -347,6 +353,8 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GCLK_PERIOD_NS_NUM=$(PARAM_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GCLK_PERIOD_NS_DENOM=$(PARAM_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py index 2ac671086..817b0f573 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -788,6 +788,10 @@ def test_fpga_core(request): parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] parameters['PORT_MASK'] = 0 + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + # PTP configuration parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165