From 152c96dc0027b4e1c2b8af061f4207c3a6e64f66 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 15 Nov 2023 11:25:45 -0800 Subject: [PATCH] fpga/mqnic/Alveo: Rework AU50 clocking Signed-off-by: Alex Forencich --- fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v | 65 +++++++++++----------- fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v | 65 +++++++++++----------- 2 files changed, 62 insertions(+), 68 deletions(-) diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v index f9744ce99..ccda81510 100644 --- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v +++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v @@ -219,7 +219,8 @@ parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; wire pcie_user_clk; wire pcie_user_reset; -wire clk_161mhz_ref_int; +wire clk_100mhz_1_ibufg; +wire clk_100mhz_1_int; wire clk_50mhz_mmcm_out; wire clk_125mhz_mmcm_out; @@ -236,19 +237,35 @@ wire mmcm_rst = pcie_user_reset; wire mmcm_locked; wire mmcm_clkfb; +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_100mhz_1_ibufg_inst ( + .O (clk_100mhz_1_ibufg), + .I (clk_100mhz_1_p), + .IB (clk_100mhz_1_n) +); + +BUFG +clk_100mhz_1_bufg_inst ( + .I(clk_100mhz_1_ibufg), + .O(clk_100mhz_1_int) +); + // MMCM instance -// 161.13 MHz in, 50 MHz + 125 MHz out +// 100 MHz in, 125 MHz + 50 MHz out // PFD range: 10 MHz to 500 MHz // VCO range: 800 MHz to 1600 MHz -// M = 128, D = 15 sets Fvco = 1375 MHz (in range) -// Divide by 27.5 to get output frequency of 50 MHz -// Divide by 11 to get output frequency of 125 MHz +// M = 10, D = 1 sets Fvco = 1000 MHz +// Divide by 8 to get output frequency of 125 MHz +// Divide by 20 to get output frequency of 50 MHz MMCME4_BASE #( .BANDWIDTH("OPTIMIZED"), - .CLKOUT0_DIVIDE_F(27.5), + .CLKOUT0_DIVIDE_F(8), .CLKOUT0_DUTY_CYCLE(0.5), .CLKOUT0_PHASE(0), - .CLKOUT1_DIVIDE(11), + .CLKOUT1_DIVIDE(20), .CLKOUT1_DUTY_CYCLE(0.5), .CLKOUT1_PHASE(0), .CLKOUT2_DIVIDE(1), @@ -266,22 +283,22 @@ MMCME4_BASE #( .CLKOUT6_DIVIDE(1), .CLKOUT6_DUTY_CYCLE(0.5), .CLKOUT6_PHASE(0), - .CLKFBOUT_MULT_F(128), + .CLKFBOUT_MULT_F(10), .CLKFBOUT_PHASE(0), - .DIVCLK_DIVIDE(15), + .DIVCLK_DIVIDE(1), .REF_JITTER1(0.010), - .CLKIN1_PERIOD(6.206), + .CLKIN1_PERIOD(10.000), .STARTUP_WAIT("FALSE"), .CLKOUT4_CASCADE("FALSE") ) clk_mmcm_inst ( - .CLKIN1(clk_161mhz_ref_int), + .CLKIN1(clk_100mhz_1_int), .CLKFBIN(mmcm_clkfb), .RST(mmcm_rst), .PWRDWN(1'b0), - .CLKOUT0(clk_50mhz_mmcm_out), + .CLKOUT0(clk_125mhz_mmcm_out), .CLKOUT0B(), - .CLKOUT1(clk_125mhz_mmcm_out), + .CLKOUT1(clk_50mhz_mmcm_out), .CLKOUT1B(), .CLKOUT2(), .CLKOUT2B(), @@ -986,8 +1003,6 @@ wire qsfp_mgt_refclk_0; wire qsfp_mgt_refclk_0_int; wire qsfp_mgt_refclk_0_bufg; -assign clk_161mhz_ref_int = qsfp_mgt_refclk_0_bufg; - IBUFDS_GTE4 ibufds_gte4_qsfp_mgt_refclk_0_inst ( .I (qsfp_mgt_refclk_0_p), .IB (qsfp_mgt_refclk_0_n), @@ -1154,29 +1169,11 @@ wire [HBM_CH-1:0] m_axi_hbm_rready; wire [HBM_CH-1:0] hbm_status; -wire clk_100mhz_1_ibufg; - -IBUFGDS #( - .DIFF_TERM("FALSE"), - .IBUF_LOW_PWR("FALSE") -) -clk_100mhz_1_ibufg_inst ( - .O (clk_100mhz_1_ibufg), - .I (clk_100mhz_1_p), - .IB (clk_100mhz_1_n) -); - generate if (HBM_ENABLE) begin - wire hbm_ref_clk; - - BUFG - hbm_ref_clk_bufg_inst ( - .I(clk_100mhz_1_ibufg), - .O(hbm_ref_clk) - ); + wire hbm_ref_clk = clk_100mhz_1_int; wire hbm_cattrip_1; wire hbm_cattrip_2; diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v index 9f832b5c7..908723907 100644 --- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v +++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v @@ -228,7 +228,8 @@ parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; wire pcie_user_clk; wire pcie_user_reset; -wire clk_161mhz_ref_int; +wire clk_100mhz_1_ibufg; +wire clk_100mhz_1_int; wire clk_50mhz_mmcm_out; wire clk_125mhz_mmcm_out; @@ -245,19 +246,35 @@ wire mmcm_rst = pcie_user_reset; wire mmcm_locked; wire mmcm_clkfb; +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_100mhz_1_ibufg_inst ( + .O (clk_100mhz_1_ibufg), + .I (clk_100mhz_1_p), + .IB (clk_100mhz_1_n) +); + +BUFG +clk_100mhz_1_bufg_inst ( + .I(clk_100mhz_1_ibufg), + .O(clk_100mhz_1_int) +); + // MMCM instance -// 161.13 MHz in, 50 MHz + 125 MHz out +// 100 MHz in, 125 MHz + 50 MHz out // PFD range: 10 MHz to 500 MHz // VCO range: 800 MHz to 1600 MHz -// M = 128, D = 15 sets Fvco = 1375 MHz (in range) -// Divide by 27.5 to get output frequency of 50 MHz -// Divide by 11 to get output frequency of 125 MHz +// M = 10, D = 1 sets Fvco = 1000 MHz +// Divide by 8 to get output frequency of 125 MHz +// Divide by 20 to get output frequency of 50 MHz MMCME4_BASE #( .BANDWIDTH("OPTIMIZED"), - .CLKOUT0_DIVIDE_F(27.5), + .CLKOUT0_DIVIDE_F(8), .CLKOUT0_DUTY_CYCLE(0.5), .CLKOUT0_PHASE(0), - .CLKOUT1_DIVIDE(11), + .CLKOUT1_DIVIDE(20), .CLKOUT1_DUTY_CYCLE(0.5), .CLKOUT1_PHASE(0), .CLKOUT2_DIVIDE(1), @@ -275,22 +292,22 @@ MMCME4_BASE #( .CLKOUT6_DIVIDE(1), .CLKOUT6_DUTY_CYCLE(0.5), .CLKOUT6_PHASE(0), - .CLKFBOUT_MULT_F(128), + .CLKFBOUT_MULT_F(10), .CLKFBOUT_PHASE(0), - .DIVCLK_DIVIDE(15), + .DIVCLK_DIVIDE(1), .REF_JITTER1(0.010), - .CLKIN1_PERIOD(6.206), + .CLKIN1_PERIOD(10.000), .STARTUP_WAIT("FALSE"), .CLKOUT4_CASCADE("FALSE") ) clk_mmcm_inst ( - .CLKIN1(clk_161mhz_ref_int), + .CLKIN1(clk_100mhz_1_int), .CLKFBIN(mmcm_clkfb), .RST(mmcm_rst), .PWRDWN(1'b0), - .CLKOUT0(clk_50mhz_mmcm_out), + .CLKOUT0(clk_125mhz_mmcm_out), .CLKOUT0B(), - .CLKOUT1(clk_125mhz_mmcm_out), + .CLKOUT1(clk_50mhz_mmcm_out), .CLKOUT1B(), .CLKOUT2(), .CLKOUT2B(), @@ -967,8 +984,6 @@ wire qsfp_mgt_refclk_0; wire qsfp_mgt_refclk_0_int; wire qsfp_mgt_refclk_0_bufg; -assign clk_161mhz_ref_int = qsfp_mgt_refclk_0_bufg; - IBUFDS_GTE4 ibufds_gte4_qsfp_mgt_refclk_0_inst ( .I (qsfp_mgt_refclk_0_p), .IB (qsfp_mgt_refclk_0_n), @@ -1162,29 +1177,11 @@ wire [HBM_CH-1:0] m_axi_hbm_rready; wire [HBM_CH-1:0] hbm_status; -wire clk_100mhz_1_ibufg; - -IBUFGDS #( - .DIFF_TERM("FALSE"), - .IBUF_LOW_PWR("FALSE") -) -clk_100mhz_1_ibufg_inst ( - .O (clk_100mhz_1_ibufg), - .I (clk_100mhz_1_p), - .IB (clk_100mhz_1_n) -); - generate if (HBM_ENABLE) begin - wire hbm_ref_clk; - - BUFG - hbm_ref_clk_bufg_inst ( - .I(clk_100mhz_1_ibufg), - .O(hbm_ref_clk) - ); + wire hbm_ref_clk = clk_100mhz_1_int; wire hbm_cattrip_1; wire hbm_cattrip_2;