From 16111eb7a8d221fd6621bd931c0a35f83b238053 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 3 Mar 2022 20:15:06 -0800 Subject: [PATCH] Update AU50 to use new wrapper --- fpga/mqnic/AU50/fpga_10g/fpga/Makefile | 7 +- fpga/mqnic/AU50/fpga_10g/ip/eth_xcvr_gt.tcl | 89 +++- .../fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v | 396 ------------------ .../AU50/fpga_10g/rtl/eth_xcvr_phy_wrapper.v | 299 ------------- fpga/mqnic/AU50/fpga_10g/rtl/fpga.v | 32 +- fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v | 71 +++- .../mqnic/AU50/fpga_10g/tb/fpga_core/Makefile | 1 + .../fpga_10g/tb/fpga_core/test_fpga_core.py | 6 + 8 files changed, 179 insertions(+), 722 deletions(-) delete mode 100644 fpga/mqnic/AU50/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v delete mode 100644 fpga/mqnic/AU50/fpga_10g/rtl/eth_xcvr_phy_wrapper.v diff --git a/fpga/mqnic/AU50/fpga_10g/fpga/Makefile b/fpga/mqnic/AU50/fpga_10g/fpga/Makefile index eacfde226..b07278361 100644 --- a/fpga/mqnic/AU50/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/AU50/fpga_10g/fpga/Makefile @@ -7,8 +7,6 @@ FPGA_ARCH = virtexuplus # Files for synthesis SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v -SYN_FILES += rtl/eth_xcvr_phy_wrapper.v -SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v @@ -38,6 +36,9 @@ SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v SYN_FILES += rtl/common/rx_hash.v SYN_FILES += rtl/common/rx_checksum.v +SYN_FILES += rtl/common/rb_drp.v +SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_wrapper.v +SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_quad_wrapper.v SYN_FILES += rtl/common/stats_counter.v SYN_FILES += rtl/common/stats_collect.v SYN_FILES += rtl/common/stats_pcie_if.v @@ -124,6 +125,8 @@ XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl +XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP diff --git a/fpga/mqnic/AU50/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/mqnic/AU50/fpga_10g/ip/eth_xcvr_gt.tcl index cecca12f7..f7f544cfe 100644 --- a/fpga/mqnic/AU50/fpga_10g/ip/eth_xcvr_gt.tcl +++ b/fpga/mqnic/AU50/fpga_10g/ip/eth_xcvr_gt.tcl @@ -1,22 +1,31 @@ -# Copyright (c) 2021 Alex Forencich +# Copyright 2022, The Regents of the University of California. +# All rights reserved. # -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), to deal -# in the Software without restriction, including without limitation the rights -# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -# copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: # -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. # -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -# THE SOFTWARE. +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +# OF SUCH DAMAGE. +# +# The views and conclusions contained in the software and documentation are those +# of the authors and should not be interpreted as representing official policies, +# either expressed or implied, of The Regents of the University of California. set base_name {eth_xcvr_gt} @@ -24,12 +33,47 @@ set preset {GTY-10GBASE-R} set freerun_freq {125} set line_rate {10.3125} +set sec_line_rate {0} set refclk_freq {161.1328125} set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] set user_data_width {64} set int_data_width $user_data_width +set rx_eq_mode {DFE} set extra_ports [list] -set extra_pll_ports [list {qpll0lock_out}] +set extra_pll_ports [list] +# DRP connections +lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out +lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out +# PLL reset and power down +lappend extra_pll_ports qpll0reset_in qpll1reset_in +lappend extra_pll_ports qpll0pd_in qpll1pd_in +# PLL clocking +lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out +lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# channel reset +lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out +lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out +# channel power down +lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in +# channel clock selection +lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in +# channel polarity +lappend extra_ports txpolarity_in rxpolarity_in +# channel TX driver +lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in +# channel CDR +lappend extra_ports rxcdrlock_out rxcdrhold_in +# channel EQ +lappend extra_ports rxlpmen_in +# channel digital monitor +lappend extra_ports dmonitorout_out +# channel PRBS +lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out +# channel eye scan +lappend extra_ports eyescandataerror_out +# channel loopback +lappend extra_ports loopback_in set config [dict create] @@ -43,9 +87,18 @@ dict set config RX_REFCLK_FREQUENCY $refclk_freq dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn dict set config RX_USER_DATA_WIDTH $user_data_width dict set config RX_INT_DATA_WIDTH $int_data_width +dict set config RX_EQ_MODE $rx_eq_mode +if {$sec_line_rate != 0} { + dict set config SECONDARY_QPLL_ENABLE true + dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn + dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq +} else { + dict set config SECONDARY_QPLL_ENABLE false +} dict set config ENABLE_OPTIONAL_PORTS $extra_ports dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {CORE} +dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} dict set config LOCATE_TX_USER_CLOCKING {CORE} dict set config LOCATE_RX_USER_CLOCKING {CORE} dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} diff --git a/fpga/mqnic/AU50/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v b/fpga/mqnic/AU50/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v deleted file mode 100644 index 4bd7eba28..000000000 --- a/fpga/mqnic/AU50/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v +++ /dev/null @@ -1,396 +0,0 @@ -/* - -Copyright 2022, The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS -IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR -CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. - -The views and conclusions contained in the software and documentation are those -of the authors and should not be interpreted as representing official policies, -either expressed or implied, of The Regents of the University of California. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * Transceiver and PHY quad wrapper - */ -module eth_xcvr_phy_quad_wrapper # -( - parameter COUNT = 4, - parameter DATA_WIDTH = 64, - parameter CTRL_WIDTH = (DATA_WIDTH/8), - parameter HDR_WIDTH = 2, - parameter PRBS31_ENABLE = 0, - parameter TX_SERDES_PIPELINE = 0, - parameter RX_SERDES_PIPELINE = 0, - parameter BITSLIP_HIGH_CYCLES = 1, - parameter BITSLIP_LOW_CYCLES = 8, - parameter COUNT_125US = 125000/6.4 -) -( - input wire xcvr_ctrl_clk, - input wire xcvr_ctrl_rst, - - /* - * Common - */ - output wire xcvr_gtpowergood_out, - input wire xcvr_ref_clk, - - /* - * Serial data - */ - output wire [COUNT-1:0] xcvr_txp, - output wire [COUNT-1:0] xcvr_txn, - input wire [COUNT-1:0] xcvr_rxp, - input wire [COUNT-1:0] xcvr_rxn, - - /* - * PHY connections - */ - output wire phy_1_tx_clk, - output wire phy_1_tx_rst, - input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, - input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, - output wire phy_1_rx_clk, - output wire phy_1_rx_rst, - output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, - output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, - output wire phy_1_tx_bad_block, - output wire [6:0] phy_1_rx_error_count, - output wire phy_1_rx_bad_block, - output wire phy_1_rx_sequence_error, - output wire phy_1_rx_block_lock, - output wire phy_1_rx_high_ber, - input wire phy_1_tx_prbs31_enable, - input wire phy_1_rx_prbs31_enable, - - output wire phy_2_tx_clk, - output wire phy_2_tx_rst, - input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, - input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, - output wire phy_2_rx_clk, - output wire phy_2_rx_rst, - output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, - output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, - output wire phy_2_tx_bad_block, - output wire [6:0] phy_2_rx_error_count, - output wire phy_2_rx_bad_block, - output wire phy_2_rx_sequence_error, - output wire phy_2_rx_block_lock, - output wire phy_2_rx_high_ber, - input wire phy_2_tx_prbs31_enable, - input wire phy_2_rx_prbs31_enable, - - output wire phy_3_tx_clk, - output wire phy_3_tx_rst, - input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, - input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, - output wire phy_3_rx_clk, - output wire phy_3_rx_rst, - output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, - output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, - output wire phy_3_tx_bad_block, - output wire [6:0] phy_3_rx_error_count, - output wire phy_3_rx_bad_block, - output wire phy_3_rx_sequence_error, - output wire phy_3_rx_block_lock, - output wire phy_3_rx_high_ber, - input wire phy_3_tx_prbs31_enable, - input wire phy_3_rx_prbs31_enable, - - output wire phy_4_tx_clk, - output wire phy_4_tx_rst, - input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, - input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, - output wire phy_4_rx_clk, - output wire phy_4_rx_rst, - output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, - output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, - output wire phy_4_tx_bad_block, - output wire [6:0] phy_4_rx_error_count, - output wire phy_4_rx_bad_block, - output wire phy_4_rx_sequence_error, - output wire phy_4_rx_block_lock, - output wire phy_4_rx_high_ber, - input wire phy_4_tx_prbs31_enable, - input wire phy_4_rx_prbs31_enable -); - -generate - -wire xcvr_qpll0lock; -wire xcvr_qpll0outclk; -wire xcvr_qpll0outrefclk; - -if (COUNT > 0) begin : phy1 - - eth_xcvr_phy_wrapper #( - .HAS_COMMON(1), - .DATA_WIDTH(DATA_WIDTH), - .CTRL_WIDTH(CTRL_WIDTH), - .HDR_WIDTH(HDR_WIDTH), - .PRBS31_ENABLE(PRBS31_ENABLE), - .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), - .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), - .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), - .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), - .COUNT_125US(COUNT_125US) - ) - eth_xcvr_phy_1 ( - .xcvr_ctrl_clk(xcvr_ctrl_clk), - .xcvr_ctrl_rst(xcvr_ctrl_rst), - - // Common - .xcvr_gtpowergood_out(xcvr_gtpowergood_out), - - // PLL out - .xcvr_gtrefclk00_in(xcvr_ref_clk), - .xcvr_qpll0lock_out(xcvr_qpll0lock), - .xcvr_qpll0outclk_out(xcvr_qpll0outclk), - .xcvr_qpll0outrefclk_out(xcvr_qpll0outrefclk), - - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), - - // Serial data - .xcvr_txp(xcvr_txp[0]), - .xcvr_txn(xcvr_txn[0]), - .xcvr_rxp(xcvr_rxp[0]), - .xcvr_rxn(xcvr_rxn[0]), - - // PHY connections - .phy_tx_clk(phy_1_tx_clk), - .phy_tx_rst(phy_1_tx_rst), - .phy_xgmii_txd(phy_1_xgmii_txd), - .phy_xgmii_txc(phy_1_xgmii_txc), - .phy_rx_clk(phy_1_rx_clk), - .phy_rx_rst(phy_1_rx_rst), - .phy_xgmii_rxd(phy_1_xgmii_rxd), - .phy_xgmii_rxc(phy_1_xgmii_rxc), - .phy_tx_bad_block(phy_1_tx_bad_block), - .phy_rx_error_count(phy_1_rx_error_count), - .phy_rx_bad_block(phy_1_rx_bad_block), - .phy_rx_sequence_error(phy_1_rx_sequence_error), - .phy_rx_block_lock(phy_1_rx_block_lock), - .phy_rx_high_ber(phy_1_rx_high_ber), - .phy_tx_prbs31_enable(phy_1_tx_prbs31_enable), - .phy_rx_prbs31_enable(phy_1_rx_prbs31_enable) - ); - -end - -if (COUNT > 1) begin : phy2 - - eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .DATA_WIDTH(DATA_WIDTH), - .CTRL_WIDTH(CTRL_WIDTH), - .HDR_WIDTH(HDR_WIDTH), - .PRBS31_ENABLE(PRBS31_ENABLE), - .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), - .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), - .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), - .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), - .COUNT_125US(COUNT_125US) - ) - eth_xcvr_phy_2 ( - .xcvr_ctrl_clk(xcvr_ctrl_clk), - .xcvr_ctrl_rst(xcvr_ctrl_rst), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(xcvr_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(xcvr_qpll0outclk), - .xcvr_qpll0refclk_in(xcvr_qpll0outrefclk), - - // Serial data - .xcvr_txp(xcvr_txp[1]), - .xcvr_txn(xcvr_txn[1]), - .xcvr_rxp(xcvr_rxp[1]), - .xcvr_rxn(xcvr_rxn[1]), - - // PHY connections - .phy_tx_clk(phy_2_tx_clk), - .phy_tx_rst(phy_2_tx_rst), - .phy_xgmii_txd(phy_2_xgmii_txd), - .phy_xgmii_txc(phy_2_xgmii_txc), - .phy_rx_clk(phy_2_rx_clk), - .phy_rx_rst(phy_2_rx_rst), - .phy_xgmii_rxd(phy_2_xgmii_rxd), - .phy_xgmii_rxc(phy_2_xgmii_rxc), - .phy_tx_bad_block(phy_2_tx_bad_block), - .phy_rx_error_count(phy_2_rx_error_count), - .phy_rx_bad_block(phy_2_rx_bad_block), - .phy_rx_sequence_error(phy_2_rx_sequence_error), - .phy_rx_block_lock(phy_2_rx_block_lock), - .phy_rx_high_ber(phy_2_rx_high_ber), - .phy_tx_prbs31_enable(phy_2_tx_prbs31_enable), - .phy_rx_prbs31_enable(phy_2_rx_prbs31_enable) - ); - -end - -if (COUNT > 2) begin : phy3 - - eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .DATA_WIDTH(DATA_WIDTH), - .CTRL_WIDTH(CTRL_WIDTH), - .HDR_WIDTH(HDR_WIDTH), - .PRBS31_ENABLE(PRBS31_ENABLE), - .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), - .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), - .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), - .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), - .COUNT_125US(COUNT_125US) - ) - eth_xcvr_phy_3 ( - .xcvr_ctrl_clk(xcvr_ctrl_clk), - .xcvr_ctrl_rst(xcvr_ctrl_rst), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(xcvr_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(xcvr_qpll0outclk), - .xcvr_qpll0refclk_in(xcvr_qpll0outrefclk), - - // Serial data - .xcvr_txp(xcvr_txp[2]), - .xcvr_txn(xcvr_txn[2]), - .xcvr_rxp(xcvr_rxp[2]), - .xcvr_rxn(xcvr_rxn[2]), - - // PHY connections - .phy_tx_clk(phy_3_tx_clk), - .phy_tx_rst(phy_3_tx_rst), - .phy_xgmii_txd(phy_3_xgmii_txd), - .phy_xgmii_txc(phy_3_xgmii_txc), - .phy_rx_clk(phy_3_rx_clk), - .phy_rx_rst(phy_3_rx_rst), - .phy_xgmii_rxd(phy_3_xgmii_rxd), - .phy_xgmii_rxc(phy_3_xgmii_rxc), - .phy_tx_bad_block(phy_3_tx_bad_block), - .phy_rx_error_count(phy_3_rx_error_count), - .phy_rx_bad_block(phy_3_rx_bad_block), - .phy_rx_sequence_error(phy_3_rx_sequence_error), - .phy_rx_block_lock(phy_3_rx_block_lock), - .phy_rx_high_ber(phy_3_rx_high_ber), - .phy_tx_prbs31_enable(phy_3_tx_prbs31_enable), - .phy_rx_prbs31_enable(phy_3_rx_prbs31_enable) - ); - -end - -if (COUNT > 3) begin : phy4 - - eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .DATA_WIDTH(DATA_WIDTH), - .CTRL_WIDTH(CTRL_WIDTH), - .HDR_WIDTH(HDR_WIDTH), - .PRBS31_ENABLE(PRBS31_ENABLE), - .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), - .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), - .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), - .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), - .COUNT_125US(COUNT_125US) - ) - eth_xcvr_phy_4 ( - .xcvr_ctrl_clk(xcvr_ctrl_clk), - .xcvr_ctrl_rst(xcvr_ctrl_rst), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(xcvr_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(xcvr_qpll0outclk), - .xcvr_qpll0refclk_in(xcvr_qpll0outrefclk), - - // Serial data - .xcvr_txp(xcvr_txp[3]), - .xcvr_txn(xcvr_txn[3]), - .xcvr_rxp(xcvr_rxp[3]), - .xcvr_rxn(xcvr_rxn[3]), - - // PHY connections - .phy_tx_clk(phy_4_tx_clk), - .phy_tx_rst(phy_4_tx_rst), - .phy_xgmii_txd(phy_4_xgmii_txd), - .phy_xgmii_txc(phy_4_xgmii_txc), - .phy_rx_clk(phy_4_rx_clk), - .phy_rx_rst(phy_4_rx_rst), - .phy_xgmii_rxd(phy_4_xgmii_rxd), - .phy_xgmii_rxc(phy_4_xgmii_rxc), - .phy_tx_bad_block(phy_4_tx_bad_block), - .phy_rx_error_count(phy_4_rx_error_count), - .phy_rx_bad_block(phy_4_rx_bad_block), - .phy_rx_sequence_error(phy_4_rx_sequence_error), - .phy_rx_block_lock(phy_4_rx_block_lock), - .phy_rx_high_ber(phy_4_rx_high_ber), - .phy_tx_prbs31_enable(phy_4_tx_prbs31_enable), - .phy_rx_prbs31_enable(phy_4_rx_prbs31_enable) - ); - -end - -endgenerate - -endmodule - -`resetall diff --git a/fpga/mqnic/AU50/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/fpga/mqnic/AU50/fpga_10g/rtl/eth_xcvr_phy_wrapper.v deleted file mode 100644 index acac5e3f9..000000000 --- a/fpga/mqnic/AU50/fpga_10g/rtl/eth_xcvr_phy_wrapper.v +++ /dev/null @@ -1,299 +0,0 @@ -/* - -Copyright (c) 2021 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * Transceiver and PHY wrapper - */ -module eth_xcvr_phy_wrapper # -( - parameter HAS_COMMON = 1, - parameter DATA_WIDTH = 64, - parameter CTRL_WIDTH = (DATA_WIDTH/8), - parameter HDR_WIDTH = 2, - parameter PRBS31_ENABLE = 0, - parameter TX_SERDES_PIPELINE = 0, - parameter RX_SERDES_PIPELINE = 0, - parameter BITSLIP_HIGH_CYCLES = 1, - parameter BITSLIP_LOW_CYCLES = 8, - parameter COUNT_125US = 125000/6.4 -) -( - input wire xcvr_ctrl_clk, - input wire xcvr_ctrl_rst, - - /* - * Common - */ - output wire xcvr_gtpowergood_out, - - /* - * PLL out - */ - input wire xcvr_gtrefclk00_in, - output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, - - /* - * PLL in - */ - input wire xcvr_qpll0lock_in, - output wire xcvr_qpll0reset_out, - input wire xcvr_qpll0clk_in, - input wire xcvr_qpll0refclk_in, - - /* - * Serial data - */ - output wire xcvr_txp, - output wire xcvr_txn, - input wire xcvr_rxp, - input wire xcvr_rxn, - - /* - * PHY connections - */ - output wire phy_tx_clk, - output wire phy_tx_rst, - input wire [DATA_WIDTH-1:0] phy_xgmii_txd, - input wire [CTRL_WIDTH-1:0] phy_xgmii_txc, - output wire phy_rx_clk, - output wire phy_rx_rst, - output wire [DATA_WIDTH-1:0] phy_xgmii_rxd, - output wire [CTRL_WIDTH-1:0] phy_xgmii_rxc, - output wire phy_tx_bad_block, - output wire [6:0] phy_rx_error_count, - output wire phy_rx_bad_block, - output wire phy_rx_sequence_error, - output wire phy_rx_block_lock, - output wire phy_rx_high_ber, - input wire phy_tx_prbs31_enable, - input wire phy_rx_prbs31_enable -); - -wire phy_rx_reset_req; - -wire gt_reset_tx_datapath = 1'b0; -wire gt_reset_rx_datapath = phy_rx_reset_req; - -wire gt_reset_tx_done; -wire gt_reset_rx_done; - -wire [5:0] gt_txheader; -wire [63:0] gt_txdata; -wire gt_rxgearboxslip; -wire [5:0] gt_rxheader; -wire [1:0] gt_rxheadervalid; -wire [63:0] gt_rxdata; -wire [1:0] gt_rxdatavalid; - -generate - -if (HAS_COMMON) begin : xcvr - - eth_xcvr_gt_full - eth_xcvr_gt_full_inst ( - // Common - .gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk), - .gtwiz_reset_all_in(xcvr_ctrl_rst), - .gtpowergood_out(xcvr_gtpowergood_out), - - // PLL - .gtrefclk00_in(xcvr_gtrefclk00_in), - .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), - - // Serial data - .gtytxp_out(xcvr_txp), - .gtytxn_out(xcvr_txn), - .gtyrxp_in(xcvr_rxp), - .gtyrxn_in(xcvr_rxn), - - // Transmit - .gtwiz_userclk_tx_reset_in(1'b0), - .gtwiz_userclk_tx_srcclk_out(), - .gtwiz_userclk_tx_usrclk_out(), - .gtwiz_userclk_tx_usrclk2_out(phy_tx_clk), - .gtwiz_userclk_tx_active_out(), - .gtwiz_reset_tx_pll_and_datapath_in(1'b0), - .gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath), - .gtwiz_reset_tx_done_out(gt_reset_tx_done), - .txpmaresetdone_out(), - .txprgdivresetdone_out(), - - .gtwiz_userdata_tx_in(gt_txdata), - .txheader_in(gt_txheader), - .txsequence_in(7'b0), - - // Receive - .gtwiz_userclk_rx_reset_in(1'b0), - .gtwiz_userclk_rx_srcclk_out(), - .gtwiz_userclk_rx_usrclk_out(), - .gtwiz_userclk_rx_usrclk2_out(phy_rx_clk), - .gtwiz_userclk_rx_active_out(), - .gtwiz_reset_rx_pll_and_datapath_in(1'b0), - .gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath), - .gtwiz_reset_rx_cdr_stable_out(), - .gtwiz_reset_rx_done_out(gt_reset_rx_done), - .rxpmaresetdone_out(), - .rxprgdivresetdone_out(), - - .rxgearboxslip_in(gt_rxgearboxslip), - .gtwiz_userdata_rx_out(gt_rxdata), - .rxdatavalid_out(gt_rxdatavalid), - .rxheader_out(gt_rxheader), - .rxheadervalid_out(gt_rxheadervalid), - .rxstartofseq_out() - ); - -end else begin : xcvr - - eth_xcvr_gt_channel - eth_xcvr_gt_channel_inst ( - // Common - .gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk), - .gtwiz_reset_all_in(xcvr_ctrl_rst), - .gtpowergood_out(xcvr_gtpowergood_out), - - // PLL - .gtwiz_reset_qpll0lock_in(xcvr_qpll0lock_in), - .gtwiz_reset_qpll0reset_out(xcvr_qpll0reset_out), - .qpll0clk_in(xcvr_qpll0clk_in), - .qpll0refclk_in(xcvr_qpll0refclk_in), - .qpll1clk_in(1'b0), - .qpll1refclk_in(1'b0), - - // Serial data - .gtytxp_out(xcvr_txp), - .gtytxn_out(xcvr_txn), - .gtyrxp_in(xcvr_rxp), - .gtyrxn_in(xcvr_rxn), - - // Transmit - .gtwiz_userclk_tx_reset_in(1'b0), - .gtwiz_userclk_tx_srcclk_out(), - .gtwiz_userclk_tx_usrclk_out(), - .gtwiz_userclk_tx_usrclk2_out(phy_tx_clk), - .gtwiz_userclk_tx_active_out(), - .gtwiz_reset_tx_pll_and_datapath_in(1'b0), - .gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath), - .gtwiz_reset_tx_done_out(gt_reset_tx_done), - .txpmaresetdone_out(), - .txprgdivresetdone_out(), - - .gtwiz_userdata_tx_in(gt_txdata), - .txheader_in(gt_txheader), - .txsequence_in(7'b0), - - // Receive - .gtwiz_userclk_rx_reset_in(1'b0), - .gtwiz_userclk_rx_srcclk_out(), - .gtwiz_userclk_rx_usrclk_out(), - .gtwiz_userclk_rx_usrclk2_out(phy_rx_clk), - .gtwiz_userclk_rx_active_out(), - .gtwiz_reset_rx_pll_and_datapath_in(1'b0), - .gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath), - .gtwiz_reset_rx_cdr_stable_out(), - .gtwiz_reset_rx_done_out(gt_reset_rx_done), - .rxpmaresetdone_out(), - .rxprgdivresetdone_out(), - - .rxgearboxslip_in(gt_rxgearboxslip), - .gtwiz_userdata_rx_out(gt_rxdata), - .rxdatavalid_out(gt_rxdatavalid), - .rxheader_out(gt_rxheader), - .rxheadervalid_out(gt_rxheadervalid), - .rxstartofseq_out() - ); - -end - -endgenerate - -sync_reset #( - .N(4) -) -tx_reset_sync_inst ( - .clk(phy_tx_clk), - .rst(!gt_reset_tx_done), - .out(phy_tx_rst) -); - -sync_reset #( - .N(4) -) -rx_reset_sync_inst ( - .clk(phy_rx_clk), - .rst(!gt_reset_rx_done), - .out(phy_rx_rst) -); - -eth_phy_10g #( - .DATA_WIDTH(DATA_WIDTH), - .CTRL_WIDTH(CTRL_WIDTH), - .HDR_WIDTH(HDR_WIDTH), - .BIT_REVERSE(1), - .SCRAMBLER_DISABLE(0), - .PRBS31_ENABLE(PRBS31_ENABLE), - .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), - .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), - .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), - .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), - .COUNT_125US(COUNT_125US) -) -phy_inst ( - .tx_clk(phy_tx_clk), - .tx_rst(phy_tx_rst), - .rx_clk(phy_rx_clk), - .rx_rst(phy_rx_rst), - .xgmii_txd(phy_xgmii_txd), - .xgmii_txc(phy_xgmii_txc), - .xgmii_rxd(phy_xgmii_rxd), - .xgmii_rxc(phy_xgmii_rxc), - .serdes_tx_data(gt_txdata), - .serdes_tx_hdr(gt_txheader), - .serdes_rx_data(gt_rxdata), - .serdes_rx_hdr(gt_rxheader), - .serdes_rx_bitslip(gt_rxgearboxslip), - .serdes_rx_reset_req(phy_rx_reset_req), - .tx_bad_block(phy_tx_bad_block), - .rx_error_count(phy_rx_error_count), - .rx_bad_block(phy_rx_bad_block), - .rx_sequence_error(phy_rx_sequence_error), - .rx_block_lock(phy_rx_block_lock), - .rx_high_ber(phy_rx_high_ber), - .tx_prbs31_enable(phy_tx_prbs31_enable), - .rx_prbs31_enable(phy_rx_prbs31_enable) -); - -endmodule - -`resetall diff --git a/fpga/mqnic/AU50/fpga_10g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_10g/rtl/fpga.v index 58af775f7..2afe4debc 100644 --- a/fpga/mqnic/AU50/fpga_10g/rtl/fpga.v +++ b/fpga/mqnic/AU50/fpga_10g/rtl/fpga.v @@ -970,6 +970,15 @@ wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_4_int; wire qsfp_rx_prbs31_enable_4_int; wire [6:0] qsfp_rx_error_count_4_int; +wire qsfp_drp_clk = clk_125mhz_int; +wire qsfp_drp_rst = rst_125mhz_int; +wire [23:0] qsfp_drp_addr; +wire [15:0] qsfp_drp_di; +wire qsfp_drp_en; +wire qsfp_drp_we; +wire [15:0] qsfp_drp_do; +wire qsfp_drp_rdy; + wire qsfp_rx_block_lock_1; wire qsfp_rx_block_lock_2; wire qsfp_rx_block_lock_3; @@ -1012,7 +1021,7 @@ qsfp_sync_reset_inst ( .out(qsfp_rst) ); -eth_xcvr_phy_quad_wrapper #( +eth_xcvr_phy_10g_gty_quad_wrapper #( .PRBS31_ENABLE(1) ) qsfp_phy_quad_inst ( @@ -1025,6 +1034,18 @@ qsfp_phy_quad_inst ( .xcvr_gtpowergood_out(qsfp_gtpowergood), .xcvr_ref_clk(qsfp_mgt_refclk_0), + /* + * DRP + */ + .drp_clk(qsfp_drp_clk), + .drp_rst(qsfp_drp_rst), + .drp_addr(qsfp_drp_addr), + .drp_di(qsfp_drp_di), + .drp_en(qsfp_drp_en), + .drp_we(qsfp_drp_we), + .drp_do(qsfp_drp_do), + .drp_rdy(qsfp_drp_rdy), + /* * Serial data */ @@ -1377,6 +1398,15 @@ core_inst ( .qsfp_rx_prbs31_enable_4(qsfp_rx_prbs31_enable_4_int), .qsfp_rx_error_count_4(qsfp_rx_error_count_4_int), + .qsfp_drp_clk(qsfp_drp_clk), + .qsfp_drp_rst(qsfp_drp_rst), + .qsfp_drp_addr(qsfp_drp_addr), + .qsfp_drp_di(qsfp_drp_di), + .qsfp_drp_en(qsfp_drp_en), + .qsfp_drp_we(qsfp_drp_we), + .qsfp_drp_do(qsfp_drp_do), + .qsfp_drp_rdy(qsfp_drp_rdy), + /* * QSPI flash */ diff --git a/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v index 2132c7e81..3f167b337 100644 --- a/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v @@ -320,6 +320,15 @@ module fpga_core # output wire qsfp_rx_prbs31_enable_4, input wire [6:0] qsfp_rx_error_count_4, + input wire qsfp_drp_clk, + input wire qsfp_drp_rst, + output wire [23:0] qsfp_drp_addr, + output wire [15:0] qsfp_drp_di, + output wire qsfp_drp_en, + output wire qsfp_drp_we, + input wire [15:0] qsfp_drp_do, + input wire qsfp_drp_rdy, + /* * QSPI flash */ @@ -367,6 +376,8 @@ parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3 localparam RB_BASE_ADDR = 16'h1000; localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; +localparam RB_DRP_QSFP_BASE = RB_BASE_ADDR + 16'h40; + initial begin if (PORT_COUNT > 4) begin $error("Error: Max port count exceeded (instance %m)"); @@ -417,6 +428,12 @@ wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data; wire ctrl_reg_rd_wait; wire ctrl_reg_rd_ack; +wire qsfp_drp_reg_wr_wait; +wire qsfp_drp_reg_wr_ack; +wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp_drp_reg_rd_data; +wire qsfp_drp_reg_rd_wait; +wire qsfp_drp_reg_rd_ack; + reg ctrl_reg_wr_ack_reg = 1'b0; reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; reg ctrl_reg_rd_ack_reg = 1'b0; @@ -435,11 +452,11 @@ reg [3:0] m_axil_cms_wstrb_reg = 4'b0000; reg m_axil_cms_wvalid_reg = 1'b0; reg m_axil_cms_arvalid_reg = 1'b0; -assign ctrl_reg_wr_wait = 1'b0; -assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg; -assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg; -assign ctrl_reg_rd_wait = 1'b0; -assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg; +assign ctrl_reg_wr_wait = qsfp_drp_reg_wr_wait; +assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp_drp_reg_wr_ack; +assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp_drp_reg_rd_data; +assign ctrl_reg_rd_wait = qsfp_drp_reg_rd_wait; +assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp_drp_reg_rd_ack; assign fpga_boot = fpga_boot_reg; @@ -544,7 +561,7 @@ always @(posedge clk_250mhz) begin // Alveo BMC RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C140; // BMC ctrl: Type RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000100; // BMC ctrl: Version - RBB+8'h28: ctrl_reg_rd_data_reg <= 0; // BMC ctrl: Next header + RBB+8'h28: ctrl_reg_rd_data_reg <= RB_DRP_QSFP_BASE; // BMC ctrl: Next header RBB+8'h2C: ctrl_reg_rd_data_reg <= m_axil_cms_addr_reg; // BMC ctrl: Addr RBB+8'h30: ctrl_reg_rd_data_reg <= m_axil_cms_rdata; // BMC ctrl: Data default: ctrl_reg_rd_ack_reg <= 1'b0; @@ -568,6 +585,48 @@ always @(posedge clk_250mhz) begin end end +rb_drp #( + .DRP_ADDR_WIDTH(24), + .DRP_DATA_WIDTH(16), + .DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}), + .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), + .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .RB_BASE_ADDR(RB_DRP_QSFP_BASE), + .RB_NEXT_PTR(0) +) +qsfp_rb_drp_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * Register interface + */ + .reg_wr_addr(ctrl_reg_wr_addr), + .reg_wr_data(ctrl_reg_wr_data), + .reg_wr_strb(ctrl_reg_wr_strb), + .reg_wr_en(ctrl_reg_wr_en), + .reg_wr_wait(qsfp_drp_reg_wr_wait), + .reg_wr_ack(qsfp_drp_reg_wr_ack), + .reg_rd_addr(ctrl_reg_rd_addr), + .reg_rd_en(ctrl_reg_rd_en), + .reg_rd_data(qsfp_drp_reg_rd_data), + .reg_rd_wait(qsfp_drp_reg_rd_wait), + .reg_rd_ack(qsfp_drp_reg_rd_ack), + + /* + * DRP + */ + .drp_clk(qsfp_drp_clk), + .drp_rst(qsfp_drp_rst), + .drp_addr(qsfp_drp_addr), + .drp_di(qsfp_drp_di), + .drp_en(qsfp_drp_en), + .drp_we(qsfp_drp_we), + .drp_do(qsfp_drp_do), + .drp_rdy(qsfp_drp_rdy) +); + reg [26:0] pps_led_counter_reg = 0; reg pps_led_reg = 0; diff --git a/fpga/mqnic/AU50/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_10g/tb/fpga_core/Makefile index 060889f54..a6e335efa 100644 --- a/fpga/mqnic/AU50/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_10g/tb/fpga_core/Makefile @@ -67,6 +67,7 @@ VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v VERILOG_SOURCES += ../../rtl/common/rx_hash.v VERILOG_SOURCES += ../../rtl/common/rx_checksum.v +VERILOG_SOURCES += ../../rtl/common/rb_drp.v VERILOG_SOURCES += ../../rtl/common/stats_counter.v VERILOG_SOURCES += ../../rtl/common/stats_collect.v VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v diff --git a/fpga/mqnic/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py index 72ec0ed1b..ae2cf946d 100644 --- a/fpga/mqnic/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -289,6 +289,11 @@ class TB(object): cocotb.start_soon(Clock(dut.qsfp_tx_clk_4, 6.4, units="ns").start()) self.qsfp_4_sink = XgmiiSink(dut.qsfp_txd_4, dut.qsfp_txc_4, dut.qsfp_tx_clk_4, dut.qsfp_tx_rst_4) + cocotb.start_soon(Clock(dut.qsfp_drp_clk, 8, units="ns").start()) + dut.qsfp_drp_rst.setimmediatevalue(0) + dut.qsfp_drp_do.setimmediatevalue(0) + dut.qsfp_drp_rdy.setimmediatevalue(0) + dut.qsfp_rx_error_count_1.setimmediatevalue(0) dut.qsfp_rx_error_count_2.setimmediatevalue(0) dut.qsfp_rx_error_count_3.setimmediatevalue(0) @@ -508,6 +513,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "tx_checksum.v"), os.path.join(rtl_dir, "common", "rx_hash.v"), os.path.join(rtl_dir, "common", "rx_checksum.v"), + os.path.join(rtl_dir, "common", "rb_drp.v"), os.path.join(rtl_dir, "common", "stats_counter.v"), os.path.join(rtl_dir, "common", "stats_collect.v"), os.path.join(rtl_dir, "common", "stats_pcie_if.v"),