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Add more FPGA JTAG IDs

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This commit is contained in:
Alex Forencich 2021-12-03 00:22:29 -08:00
parent bbb9f42516
commit 161a25b4d5
2 changed files with 91 additions and 10 deletions
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50
utils/fpga_id.c
View File

@ -42,6 +42,13 @@ struct fpga_id {
const struct fpga_id fpga_id_list[] =
{
// Xilinx
// Spartan 7
{FPGA_ID_XC7S6, FPGA_ID_MASK_NOVER, "XC7S6"},
{FPGA_ID_XC7S15, FPGA_ID_MASK_NOVER, "XC7S15"},
{FPGA_ID_XC7S25, FPGA_ID_MASK_NOVER, "XC7S25"},
{FPGA_ID_XC7S50, FPGA_ID_MASK_NOVER, "XC7S50"},
{FPGA_ID_XC7S75, FPGA_ID_MASK_NOVER, "XC7S75"},
{FPGA_ID_XC7S100, FPGA_ID_MASK_NOVER, "XC7S100"},
// Artix 7
{FPGA_ID_XC7A15T, FPGA_ID_MASK_NOVER, "XC7A15T"},
{FPGA_ID_XC7A35T, FPGA_ID_MASK_NOVER, "XC7A35T"},
@ -69,7 +76,18 @@ const struct fpga_id fpga_id_list[] =
{FPGA_ID_XC7VX1140T, FPGA_ID_MASK_NOVER, "XC7VX1140T"},
{FPGA_ID_XC7VH580T, FPGA_ID_MASK_NOVER, "XC7VH580T"},
{FPGA_ID_XC7VH870T, FPGA_ID_MASK_NOVER, "XC7VH870T"},
// Kintex Ultrascale
// Zynq 7000
{FPGA_ID_XC7Z007, FPGA_ID_MASK_NOVER, "XC7Z007"},
{FPGA_ID_XC7Z010, FPGA_ID_MASK_NOVER, "XC7Z010"},
{FPGA_ID_XC7Z012, FPGA_ID_MASK_NOVER, "XC7Z012"},
{FPGA_ID_XC7Z014, FPGA_ID_MASK_NOVER, "XC7Z014"},
{FPGA_ID_XC7Z015, FPGA_ID_MASK_NOVER, "XC7Z015"},
{FPGA_ID_XC7Z020, FPGA_ID_MASK_NOVER, "XC7Z020"},
{FPGA_ID_XC7Z030, FPGA_ID_MASK_NOVER, "XC7Z030"},
{FPGA_ID_XC7Z035, FPGA_ID_MASK_NOVER, "XC7Z035"},
{FPGA_ID_XC7Z045, FPGA_ID_MASK_NOVER, "XC7Z045"},
{FPGA_ID_XC7Z100, FPGA_ID_MASK_NOVER, "XC7Z100"},
// Kintex UltraScale
{FPGA_ID_XCKU025, FPGA_ID_MASK_NOVER, "XCKU025"},
{FPGA_ID_XCKU035, FPGA_ID_MASK_NOVER, "XCKU035"},
{FPGA_ID_XCKU040, FPGA_ID_MASK_NOVER, "XCKU040"},
@ -77,7 +95,7 @@ const struct fpga_id fpga_id_list[] =
{FPGA_ID_XCKU085, FPGA_ID_MASK_NOVER, "XCKU085"},
{FPGA_ID_XCKU095, FPGA_ID_MASK_NOVER, "XCKU095"},
{FPGA_ID_XCKU115, FPGA_ID_MASK_NOVER, "XCKU115"},
// Virtex Ultrascale
// Virtex UltraScale
{FPGA_ID_XCVU065, FPGA_ID_MASK_NOVER, "XCVU065"},
{FPGA_ID_XCVU080, FPGA_ID_MASK_NOVER, "XCVU080"},
{FPGA_ID_XCVU095, FPGA_ID_MASK_NOVER, "XCVU095"},
@ -85,21 +103,37 @@ const struct fpga_id fpga_id_list[] =
{FPGA_ID_XCVU160, FPGA_ID_MASK_NOVER, "XCVU160"},
{FPGA_ID_XCVU190, FPGA_ID_MASK_NOVER, "XCVU190"},
{FPGA_ID_XCVU440, FPGA_ID_MASK_NOVER, "XCVU440"},
// Kintex Ultrascale+
// Artix UltraScale+
{FPGA_ID_XCAU10P, FPGA_ID_MASK_NOVER, "XCAU10P"},
{FPGA_ID_XCAU15P, FPGA_ID_MASK_NOVER, "XCAU15P"},
{FPGA_ID_XCAU20P, FPGA_ID_MASK_NOVER, "XCAU20P"},
{FPGA_ID_XCAU25P, FPGA_ID_MASK_NOVER, "XCAU25P"},
// Kintex UltraScale+
{FPGA_ID_XCKU3P, FPGA_ID_MASK_NOVER, "XCKU3P"},
{FPGA_ID_XCKU5P, FPGA_ID_MASK_NOVER, "XCKU5P"},
{FPGA_ID_XCKU9P, FPGA_ID_MASK_NOVER, "XCKU9P"},
{FPGA_ID_XCKU11P, FPGA_ID_MASK_NOVER, "XCKU11P"},
{FPGA_ID_XCKU13P, FPGA_ID_MASK_NOVER, "XCKU13P"},
{FPGA_ID_XCKU15P, FPGA_ID_MASK_NOVER, "XCKU15P"},
// Virtex Ultrascale+
// Virtex UltraScale+
{FPGA_ID_XCVU3P, FPGA_ID_MASK_NOVER, "XCVU3P"},
{FPGA_ID_XCVU5P, FPGA_ID_MASK_NOVER, "XCVU5P"},
{FPGA_ID_XCVU7P, FPGA_ID_MASK_NOVER, "XCVU7P"},
{FPGA_ID_XCVU9P, FPGA_ID_MASK_NOVER, "XCVU9P"},
{FPGA_ID_XCVU11P, FPGA_ID_MASK_NOVER, "XCVU11P"},
{FPGA_ID_XCVU13P, FPGA_ID_MASK_NOVER, "XCVU13P"},
// Zynq Ultrascale+
{FPGA_ID_XCVU19P, FPGA_ID_MASK_NOVER, "XCVU19P"},
{FPGA_ID_XCVU23P, FPGA_ID_MASK_NOVER, "XCVU23P"},
{FPGA_ID_XCVU27P, FPGA_ID_MASK_NOVER, "XCVU27P"},
{FPGA_ID_XCVU29P, FPGA_ID_MASK_NOVER, "XCVU29P"},
{FPGA_ID_XCVU31P, FPGA_ID_MASK_NOVER, "XCVU31P"},
{FPGA_ID_XCVU33P, FPGA_ID_MASK_NOVER, "XCVU33P"},
{FPGA_ID_XCVU35P, FPGA_ID_MASK_NOVER, "XCVU35P"},
{FPGA_ID_XCVU37P, FPGA_ID_MASK_NOVER, "XCVU37P"},
{FPGA_ID_XCVU45P, FPGA_ID_MASK_NOVER, "XCVU45P"},
{FPGA_ID_XCVU47P, FPGA_ID_MASK_NOVER, "XCVU47P"},
{FPGA_ID_XCVU57P, FPGA_ID_MASK_NOVER, "XCVU57P"},
// Zynq UltraScale+
{FPGA_ID_XCZU2, FPGA_ID_MASK_NOVER, "XCZU2"},
{FPGA_ID_XCZU3, FPGA_ID_MASK_NOVER, "XCZU3"},
{FPGA_ID_XCZU4, FPGA_ID_MASK_NOVER, "XCZU4"},
@ -116,6 +150,12 @@ const struct fpga_id fpga_id_list[] =
{FPGA_ID_XCZU27, FPGA_ID_MASK_NOVER, "XCZU27"},
{FPGA_ID_XCZU28, FPGA_ID_MASK_NOVER, "XCZU28"},
{FPGA_ID_XCZU29, FPGA_ID_MASK_NOVER, "XCZU29"},
{FPGA_ID_XCZU39, FPGA_ID_MASK_NOVER, "XCZU39"},
{FPGA_ID_XCZU43, FPGA_ID_MASK_NOVER, "XCZU43"},
{FPGA_ID_XCZU46, FPGA_ID_MASK_NOVER, "XCZU46"},
{FPGA_ID_XCZU47, FPGA_ID_MASK_NOVER, "XCZU47"},
{FPGA_ID_XCZU48, FPGA_ID_MASK_NOVER, "XCZU48"},
{FPGA_ID_XCZU49, FPGA_ID_MASK_NOVER, "XCZU49"},
// Alveo
{FPGA_ID_XCU50, FPGA_ID_MASK_NOVER, "XCU50"},
{FPGA_ID_XCU200, FPGA_ID_MASK_NOVER, "XCU200"},

51
utils/fpga_id.h
View File

@ -41,6 +41,13 @@ either expressed or implied, of The Regents of the University of California.
#define FPGA_ID_MASK_NOVER 0x0FFFFFFF
// Xilinx
// Spartan 7
#define FPGA_ID_XC7S6 0x3622093
#define FPGA_ID_XC7S15 0x3620093
#define FPGA_ID_XC7S25 0x37C4093
#define FPGA_ID_XC7S50 0x362F093
#define FPGA_ID_XC7S75 0x37C8093
#define FPGA_ID_XC7S100 0x37C7093
// Artix 7
#define FPGA_ID_XC7A15T 0x362D093
#define FPGA_ID_XC7A35T 0x362D093
@ -68,7 +75,18 @@ either expressed or implied, of The Regents of the University of California.
#define FPGA_ID_XC7VX1140T 0x36D5093
#define FPGA_ID_XC7VH580T 0x36D9093
#define FPGA_ID_XC7VH870T 0x36DB093
// Kintex Ultrascale
// Zynq 7000
#define FPGA_ID_XC7Z007 0x3723093
#define FPGA_ID_XC7Z010 0x3722093
#define FPGA_ID_XC7Z012 0x373C093
#define FPGA_ID_XC7Z014 0x3728093
#define FPGA_ID_XC7Z015 0x373B093
#define FPGA_ID_XC7Z020 0x3727093
#define FPGA_ID_XC7Z030 0x372C093
#define FPGA_ID_XC7Z035 0x3732093
#define FPGA_ID_XC7Z045 0x3731093
#define FPGA_ID_XC7Z100 0x3736093
// Kintex UltraScale
#define FPGA_ID_XCKU025 0x3824093
#define FPGA_ID_XCKU035 0x3823093
#define FPGA_ID_XCKU040 0x3822093
@ -76,7 +94,7 @@ either expressed or implied, of The Regents of the University of California.
#define FPGA_ID_XCKU085 0x380F093
#define FPGA_ID_XCKU095 0x3844093
#define FPGA_ID_XCKU115 0x390D093
// Virtex Ultrascale
// Virtex UltraScale
#define FPGA_ID_XCVU065 0x3939093
#define FPGA_ID_XCVU080 0x3843093
#define FPGA_ID_XCVU095 0x3842093
@ -84,21 +102,38 @@ either expressed or implied, of The Regents of the University of California.
#define FPGA_ID_XCVU160 0x3933093
#define FPGA_ID_XCVU190 0x3931093
#define FPGA_ID_XCVU440 0x396D093
// Kintex Ultrascale+
// Artix UltraScale+
#define FPGA_ID_XCAU10P 0x4AC5093
#define FPGA_ID_XCAU15P 0x4AC4093
#define FPGA_ID_XCAU20P 0x4A65093
#define FPGA_ID_XCAU25P 0x4A64093
// Kintex UltraScale+
#define FPGA_ID_XCKU3P 0x4A63093
#define FPGA_ID_XCKU5P 0x4A62093
#define FPGA_ID_XCKU9P 0x484A093
#define FPGA_ID_XCKU11P 0x4A4E093
#define FPGA_ID_XCKU13P 0x4A52093
#define FPGA_ID_XCKU15P 0x4A56093
// Virtex Ultrascale+
#define FPGA_ID_XCKU19P 0x4ACF093
// Virtex UltraScale+
#define FPGA_ID_XCVU3P 0x4B39093
#define FPGA_ID_XCVU5P 0x4B2B093
#define FPGA_ID_XCVU7P 0x4B29093
#define FPGA_ID_XCVU9P 0x4B31093
#define FPGA_ID_XCVU11P 0x4B49093
#define FPGA_ID_XCVU13P 0x4B51093
// Zynq Ultrascale+
#define FPGA_ID_XCVU19P 0x4BA1093
#define FPGA_ID_XCVU23P 0x4ACE093
#define FPGA_ID_XCVU27P 0x4B43093
#define FPGA_ID_XCVU29P 0x4B41093
#define FPGA_ID_XCVU31P 0x4B6B093
#define FPGA_ID_XCVU33P 0x4B69093
#define FPGA_ID_XCVU35P 0x4B71093
#define FPGA_ID_XCVU37P 0x4B79093
#define FPGA_ID_XCVU45P 0x4B73093
#define FPGA_ID_XCVU47P 0x4B7B093
#define FPGA_ID_XCVU57P 0x4B61093
// Zynq UltraScale+
#define FPGA_ID_XCZU2 0x4711093
#define FPGA_ID_XCZU3 0x4710093
#define FPGA_ID_XCZU4 0x4721093
@ -115,6 +150,12 @@ either expressed or implied, of The Regents of the University of California.
#define FPGA_ID_XCZU27 0x47E4093
#define FPGA_ID_XCZU28 0x47E0093
#define FPGA_ID_XCZU29 0x47E2093
#define FPGA_ID_XCZU39 0x47E6093
#define FPGA_ID_XCZU43 0x47FD093
#define FPGA_ID_XCZU46 0x47F8093
#define FPGA_ID_XCZU47 0x47FF093
#define FPGA_ID_XCZU48 0x47FB093
#define FPGA_ID_XCZU49 0x47FE093
// Alveo
#define FPGA_ID_XCU50 0x4B77093
#define FPGA_ID_XCU200 0x4B37093