FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity

fpga/mqnic/ZCU106/fpga_zynqmp: Remove SI570 workaround

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-08-15 23:54:02 -07:00
parent c5efd8ff0a
commit 171c2a9a69
1 changed files with 1 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi
View File

@ -59,28 +59,7 @@
};
};
/* WORKAROUND:
* Letting the Linux driver for USER MGT SI570 (U56) chip program the output
* frequency causes the peer of mqnic's PHY to loose its link.
* Reason: The USER MGT SI570 (U56) chip is used as the source for the 156.25 MHz
* MGT ref clock. And the factory default is 156.25 HHz. However the frequency
* hard-coded into the PetaLinux device tree snippet for the ZCU106 board
* (file: zcu106-reva.dtsi) is 148.5 MHz.
*
* However even when overwriting the "clock-frequency" property to 156.25 MHz and
* letting the Linux driver reprogram/reconfigure the USER MGT SI570 (U56) chip
* with this desired frequency the mqnic's PHY RX direction still breaks (block
* lock lost); the peer however still keeps saying "link up".
*
* Thus, for now, we make Linux NOT load the driver for the USER MGT SI570 (U56)
* chip.
* In the future the mqnic PHY may get a control interface, in order for the
* software to reprogram the USER MGT SI570 (U56) chip and then be able to
* trigger a PHY reset.
*/
/* USER MGT SI570 (U56) */
&si570_2 {
status = "disabled";
/* clock-frequency = <156250000>; */
clock-frequency = <156250000>;
};