FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity

Indexing updates

Browse Source
This commit is contained in:
Alex Forencich 2021-12-02 16:59:16 -08:00
parent 3a12483711
commit 17d7353523
2 changed files with 9 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
rtl/dma_if_desc_mux.v
View File

@ -177,10 +177,9 @@ assign acknowledge = grant & s_axis_desc_valid & s_axis_desc_ready;
always @* begin
// pass through selected packet data
m_axis_desc_dma_addr_int = current_s_desc_dma_addr;
if (S_RAM_SEL_WIDTH > 0) begin
m_axis_desc_ram_sel_int = {grant_encoded, current_s_desc_ram_sel};
end else begin
m_axis_desc_ram_sel_int = grant_encoded;
m_axis_desc_ram_sel_int = current_s_desc_ram_sel;
if (PORTS > 1) begin
m_axis_desc_ram_sel_int[M_RAM_SEL_WIDTH-1:M_RAM_SEL_WIDTH-CL_PORTS] = grant_encoded;
end
m_axis_desc_ram_addr_int = current_s_desc_ram_addr;
m_axis_desc_len_int = current_s_desc_len;
@ -293,7 +292,7 @@ assign m_axis_desc_status_valid = m_axis_desc_status_valid_reg;
always @(posedge clk) begin
m_axis_desc_status_tag_reg <= s_axis_desc_status_tag;
m_axis_desc_status_error_reg <= s_axis_desc_status_error;
m_axis_desc_status_valid_reg <= s_axis_desc_status_valid << (PORTS > 1 ? s_axis_desc_status_tag[S_TAG_WIDTH+CL_PORTS-1:S_TAG_WIDTH] : 0);
m_axis_desc_status_valid_reg <= s_axis_desc_status_valid << (PORTS > 1 ? s_axis_desc_status_tag[M_TAG_WIDTH-1:M_TAG_WIDTH-CL_PORTS] : 0);
if (rst) begin
m_axis_desc_status_valid_reg <= {PORTS{1'b0}};

7
rtl/pcie_axi_dma_desc_mux.v
View File

@ -152,7 +152,10 @@ always @* begin
m_axis_desc_pcie_addr_int = current_s_desc_pcie_addr;
m_axis_desc_axi_addr_int = current_s_desc_axi_addr;
m_axis_desc_len_int = current_s_desc_len;
m_axis_desc_tag_int = {grant_encoded, current_s_desc_tag};
m_axis_desc_tag_int = current_s_desc_tag;
if (PORTS > 1) begin
m_axis_desc_tag_int[M_TAG_WIDTH-1:M_TAG_WIDTH-CL_PORTS] = grant_encoded;
end
m_axis_desc_valid_int = current_s_desc_valid && m_axis_desc_ready_int_reg && grant_valid;
end
@ -255,7 +258,7 @@ assign m_axis_desc_status_valid = m_axis_desc_status_valid_reg;
always @* begin
m_axis_desc_status_tag_next = s_axis_desc_status_tag;
m_axis_desc_status_error_next = s_axis_desc_status_error;
m_axis_desc_status_valid_next = s_axis_desc_status_valid << (PORTS > 1 ? s_axis_desc_status_tag[S_TAG_WIDTH+CL_PORTS-1:S_TAG_WIDTH] : 0);
m_axis_desc_status_valid_next = s_axis_desc_status_valid << (PORTS > 1 ? s_axis_desc_status_tag[M_TAG_WIDTH-1:M_TAG_WIDTH-CL_PORTS] : 0);
end
always @(posedge clk) begin