From 184b7242e96bb6bd2b87a2a76115d3be6b80cd2d Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 14 Nov 2023 18:11:59 -0800 Subject: [PATCH] fpga/mqnic/DE10_Agilex: Fix MAC timing constraints for DE10-Agilex Signed-off-by: Alex Forencich --- fpga/mqnic/DE10_Agilex/fpga_100g/fpga.sdc | 17 ---------- .../DE10_Agilex/fpga_100g/fpga_100g/Makefile | 3 +- .../fpga_100g/fpga_100g_24AR0/Makefile | 3 +- .../fpga_100g_app_dma_bench/Makefile | 3 +- .../fpga_100g_app_dma_bench_24AR0/Makefile | 3 +- .../DE10_Agilex/fpga_100g/fpga_10g/Makefile | 3 +- .../fpga_100g/fpga_10g_24AR0/Makefile | 3 +- .../DE10_Agilex/fpga_100g/fpga_25g/Makefile | 3 +- .../fpga_100g/fpga_25g_24AR0/Makefile | 3 +- fpga/mqnic/DE10_Agilex/fpga_100g/mac_100g.sdc | 16 +++++++++ fpga/mqnic/DE10_Agilex/fpga_100g/mac_25g.sdc | 33 +++++++++++++++++++ 11 files changed, 65 insertions(+), 25 deletions(-) create mode 100644 fpga/mqnic/DE10_Agilex/fpga_100g/mac_100g.sdc create mode 100644 fpga/mqnic/DE10_Agilex/fpga_100g/mac_25g.sdc diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga.sdc b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga.sdc index abd73a732..6194cad1b 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga.sdc +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga.sdc @@ -66,20 +66,3 @@ constrain_sync_reset_inst "ptp_rst_reset_sync_inst" # PCIe clock set_clock_groups -asynchronous -group [ get_clocks "pcie_hip_inst|intel_pcie_ptile_ast_0|inst|inst|maib_and_tile|xcvr_hip_native|rx_ch15" ] - -# E-Tile MACs -proc constrain_etile_mac_dual { inst } { - puts "Inserting timing constraints for MAC dual $inst" - - foreach mac {mac_02_inst mac_13_inst} { - set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp0|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ] - set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp1|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ] - } - - for {set i 0} {$i < 2} {incr i} { - constrain_sync_reset_inst "$inst|mac_ch[$i].mac_reset_sync_inst" - } -} - -constrain_etile_mac_dual "qsfpdda_mac_inst" -constrain_etile_mac_dual "qsfpddb_mac_inst" diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g/Makefile index b8a5b8c8d..792103d92 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g/Makefile @@ -126,7 +126,8 @@ IP_TCL_FILES += ip/mac_13.tcl QSF_FILES = fpga.qsf # SDC files -SDC_FILES = fpga.sdc +SDC_FILES += fpga.sdc +SDC_FILES += mac_100g.sdc # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_24AR0/Makefile index ec83d94ee..5c28d542a 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_24AR0/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_24AR0/Makefile @@ -126,7 +126,8 @@ IP_TCL_FILES += ip/mac_13.tcl QSF_FILES = fpga.qsf # SDC files -SDC_FILES = fpga.sdc +SDC_FILES += fpga.sdc +SDC_FILES += mac_100g.sdc # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench/Makefile index f06e301c9..0e08bd1d0 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench/Makefile @@ -128,7 +128,8 @@ IP_TCL_FILES += ip/mac_13.tcl QSF_FILES = fpga.qsf # SDC files -SDC_FILES = fpga.sdc +SDC_FILES += fpga.sdc +SDC_FILES += mac_100g.sdc # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench_24AR0/Makefile index c7ec69f5b..3aeb1cda1 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench_24AR0/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_100g_app_dma_bench_24AR0/Makefile @@ -128,7 +128,8 @@ IP_TCL_FILES += ip/mac_13.tcl QSF_FILES = fpga.qsf # SDC files -SDC_FILES = fpga.sdc +SDC_FILES += fpga.sdc +SDC_FILES += mac_100g.sdc # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g/Makefile index af30819a5..8aa6739d3 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g/Makefile @@ -127,7 +127,8 @@ IP_TCL_FILES += ip/iopll_etile_ptp.tcl QSF_FILES = fpga.qsf # SDC files -SDC_FILES = fpga.sdc +SDC_FILES += fpga.sdc +SDC_FILES += mac_25g.sdc # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g_24AR0/Makefile index edc8a89ab..a8a69d712 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g_24AR0/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_10g_24AR0/Makefile @@ -127,7 +127,8 @@ IP_TCL_FILES += ip/iopll_etile_ptp.tcl QSF_FILES = fpga.qsf # SDC files -SDC_FILES = fpga.sdc +SDC_FILES += fpga.sdc +SDC_FILES += mac_25g.sdc # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/Makefile index 6ca79e59a..e16daa5fe 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/Makefile @@ -127,7 +127,8 @@ IP_TCL_FILES += ip/iopll_etile_ptp.tcl QSF_FILES = fpga.qsf # SDC files -SDC_FILES = fpga.sdc +SDC_FILES += fpga.sdc +SDC_FILES += mac_25g.sdc # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/Makefile b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/Makefile index 6152b1179..5ac6486a7 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/Makefile +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/Makefile @@ -127,7 +127,8 @@ IP_TCL_FILES += ip/iopll_etile_ptp.tcl QSF_FILES = fpga.qsf # SDC files -SDC_FILES = fpga.sdc +SDC_FILES += fpga.sdc +SDC_FILES += mac_25g.sdc # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/mac_100g.sdc b/fpga/mqnic/DE10_Agilex/fpga_100g/mac_100g.sdc new file mode 100644 index 000000000..9821d9a5c --- /dev/null +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/mac_100g.sdc @@ -0,0 +1,16 @@ +# E-Tile MACs +proc constrain_etile_mac_dual { inst } { + puts "Inserting timing constraints for MAC dual $inst" + + foreach mac {mac_02_inst mac_13_inst} { + set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp0|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ] + set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp1|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ] + } + + for {set i 0} {$i < 2} {incr i} { + constrain_sync_reset_inst "$inst|mac_ch[$i].mac_reset_sync_inst" + } +} + +constrain_etile_mac_dual "qsfpdda_mac_inst" +constrain_etile_mac_dual "qsfpddb_mac_inst" diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/mac_25g.sdc b/fpga/mqnic/DE10_Agilex/fpga_100g/mac_25g.sdc new file mode 100644 index 000000000..e9889551e --- /dev/null +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/mac_25g.sdc @@ -0,0 +1,33 @@ +# E-Tile MACs +set_clock_groups -asynchronous -group [ get_clocks "iopll_etile_ptp_inst|iopll_0_refclk" ] +set_clock_groups -asynchronous -group [ get_clocks "iopll_etile_ptp_inst|iopll_0_outclk0" ] + +proc constrain_etile_mac_dual_quad { inst } { + puts "Inserting timing constraints for MAC quad $inst" + + foreach mac {mac_02_inst mac_13_inst} { + for {set i 0} {$i < 4} {incr i} { + set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout2|ch${i}" ] + set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout|ch${i}" ] + set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout2|ch${i}" ] + set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout|ch${i}" ] + set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout2|ch${i}" ] + set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout|ch${i}" ] + set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout2|ch${i}" ] + set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout|ch${i}" ] + } + + set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp0|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ] + set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp1|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ] + set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp1|alt_ehipc3_fm_nphy_elane_ptp_plloff|tx_transfer_clk|ch0" ] + } + + for {set i 0} {$i < 8} {incr i} { + constrain_sync_reset_inst "$inst|mac_ch[$i].mac_tx_reset_sync_inst" + constrain_sync_reset_inst "$inst|mac_ch[$i].mac_tx_ptp_reset_sync_inst" + constrain_sync_reset_inst "$inst|mac_ch[$i].mac_rx_ptp_reset_sync_inst" + } +} + +constrain_etile_mac_dual_quad "qsfpdda_mac_inst" +constrain_etile_mac_dual_quad "qsfpddb_mac_inst"