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merged changes in axis

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This commit is contained in:
Alex Forencich 2017-12-01 00:02:34 -08:00
commit 18787c2eed
126 changed files with 7447 additions and 8655 deletions
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4
lib/axis/.travis.yml
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@ -1,6 +1,6 @@
language: python language: python
python: python:
- "3.4" - "3.6"
before_install: before_install:
- export d=`pwd` - export d=`pwd`
- export PYTHON_EXE=`which python` - export PYTHON_EXE=`which python`
@ -8,7 +8,7 @@ before_install:
- sudo apt-get install -y iverilog - sudo apt-get install -y iverilog
- git clone https://github.com/jandecaluwe/myhdl.git - git clone https://github.com/jandecaluwe/myhdl.git
- cd $d/myhdl && sudo $PYTHON_EXE setup.py install - cd $d/myhdl && sudo $PYTHON_EXE setup.py install
- cd $d/myhdl/cosimulation/icarus && make && sudo install -m 0755 -D ./myhdl.vpi /usr/lib/ivl/myhdl.vpi - cd $d/myhdl/cosimulation/icarus && make && sudo install -m 0755 -D ./myhdl.vpi /usr/lib/x86_64-linux-gnu/ivl/myhdl.vpi
- cd $d - cd $d
script: script:
- cd tb && py.test - cd tb && py.test

132
lib/axis/README.md
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@ -34,33 +34,16 @@ Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with axis_arb_mux.py. Can be generated with arbitrary port counts with axis_arb_mux.py.
### axis_arb_mux_64_N module
Frame-aware AXI stream arbitrated muliplexer with tkeep signal and
parametrizable data width. Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with axis_arb_mux_64.py.
### axis_async_fifo module ### axis_async_fifo module
Basic word-based asynchronous FIFO with parametrizable data width and depth. Basic word-based asynchronous FIFO with parametrizable data width and depth.
Supports power of two depths only. Supports power of two depths only.
### axis_async_fifo_64 module
Basic word-based asynchronous FIFO with tkeep signal and parametrizable data
width and depth. Supports power of two depths only.
### axis_async_frame_fifo module ### axis_async_frame_fifo module
Basic frame-based asynchronous FIFO with parametrizable data width and depth. Basic frame-based asynchronous FIFO with parametrizable data width and depth.
Supports power of two depths only. Supports power of two depths only.
### axis_async_fifo_64 module
Basic frame-based asynchronous FIFO with tkeep signal and parametrizable data
width and depth. Supports power of two depths only.
### axis_crosspoint module ### axis_crosspoint module
Basic crosspoint switch. tready signal not supported. Parametrizable data Basic crosspoint switch. tready signal not supported. Parametrizable data
@ -68,46 +51,22 @@ width.
Can be generated with arbitrary port counts with axis_crosspoint.py. Can be generated with arbitrary port counts with axis_crosspoint.py.
### axis_crosspoint_64 module
Basic crosspoint switch with tkeep. tready signal not supported.
Parametrizable data width.
Can be generated with arbitrary port counts with axis_crosspoint_64.py.
### axis_demux_N module ### axis_demux_N module
Frame-aware AXI stream demuliplexer with parametrizable data width. Frame-aware AXI stream demuliplexer with parametrizable data width.
Can be generated with arbitrary port counts with axis_demux.py. Can be generated with arbitrary port counts with axis_demux.py.
### axis_demux_64_N module
Frame-aware AXI stream demuliplexer with tkeep signal and parametrizable data
width.
Can be generated with arbitrary port counts with axis_demux_64.py.
### axis_fifo module ### axis_fifo module
Basic word-based synchronous FIFO with parametrizable data width and depth. Basic word-based synchronous FIFO with parametrizable data width and depth.
Supports power of two depths only. Supports power of two depths only.
### axis_fifo_64 module
Basic word-based synchronous FIFO with tkeep signal and parametrizable data
width and depth. Supports power of two depths only.
### axis_frame_fifo module ### axis_frame_fifo module
Basic frame-based synchronous FIFO with parametrizable data width and depth. Basic frame-based synchronous FIFO with parametrizable data width and depth.
Supports power of two depths only. Supports power of two depths only.
### axis_frame_fifo_64 module
Basic frame-based synchronous FIFO with tkeep signal and parametrizable data
width and depth. Supports power of two depths only.
### axis_frame_join_N module ### axis_frame_join_N module
Frame joiner with optional tag. 8 bit data path only. Frame joiner with optional tag. 8 bit data path only.
@ -129,14 +88,6 @@ current lengths as well as whether the packet was truncated or padded. FIFOs
are used so that the status information can be read before the packet itself. are used so that the status information can be read before the packet itself.
Length limits are configurable at run time. Length limits are configurable at run time.
### axis_frame_length_adjust_fifo_64 module
Frame length adjuster module with FIFO. Truncates or pads frames as necessary
to meet the specified minimum and maximum length. Reports the original and
current lengths as well as whether the packet was truncated or padded. FIFOs
are used so that the status information can be read before the packet itself.
Length limits are configurable at run time. Packet FIFO has a tkeep signal.
### axis_ll_bridge module ### axis_ll_bridge module
AXI stream to LocalLink bridge. AXI stream to LocalLink bridge.
@ -147,13 +98,6 @@ Frame-aware AXI stream muliplexer with parametrizable data width.
Can be generated with arbitrary port counts with axis_mux.py. Can be generated with arbitrary port counts with axis_mux.py.
### axis_mux_64_N module
Frame-aware AXI stream muliplexer with tkeep signal and parametrizable data
width.
Can be generated with arbitrary port counts with axis_mux_64.py.
### axis_rate_limit module ### axis_rate_limit module
Fractional rate limiter, supports word and frame modes. Inserts wait states Fractional rate limiter, supports word and frame modes. Inserts wait states
@ -161,43 +105,20 @@ to limit data rate to specified ratio. Frame mode inserts wait states at end
of frames, word mode ignores frames and inserts wait states at any point. of frames, word mode ignores frames and inserts wait states at any point.
Parametrizable data width. Rate and mode are configurable at run time. Parametrizable data width. Rate and mode are configurable at run time.
### axis_rate_limit_64 module
Fractional rate limiter with tkeep signal, supports word and frame modes.
Inserts wait states to limit data rate to specified ratio. Frame mode inserts
wait states at end of frames, word mode ignores frames and inserts wait states
at any point. Parametrizable data width. Rate and mode are configurable at
run time.
### axis_register module ### axis_register module
Datapath register. Use to improve timing for long routes. Datapath register. Use to improve timing for long routes.
### axis_register_64 module
Datapath register with tkeep signal. Use to improve timing for long routes.
### axis_srl_fifo module ### axis_srl_fifo module
SRL-based FIFO. Good for small FIFOs. SRLs on Xilinx FPGAs have a very fast SRL-based FIFO. Good for small FIFOs. SRLs on Xilinx FPGAs have a very fast
input setup time, so this module can be used to aid in timing closure. input setup time, so this module can be used to aid in timing closure.
### axis_srl_fifo_64 module
SRL-based FIFO with tkeep signal. Good for small FIFOs. SRLs on Xilinx FPGAs
have a very fast input setup time, so this module can be used to aid in timing
closure.
### axis_srl_register module ### axis_srl_register module
SRL-based register. SRLs on Xilinx FPGAs have a very fast input setup time, SRL-based register. SRLs on Xilinx FPGAs have a very fast input setup time,
so this module can be used to aid in timing closure. so this module can be used to aid in timing closure.
### axis_srl_register_64 module
SRL-based register with tkeep signal. SRLs on Xilinx FPGAs have a very fast
input setup time, so this module can be used to aid in timing closure.
### axis_stat_counter module ### axis_stat_counter module
Statistics counter module. Counts bytes and frames passing through monitored Statistics counter module. Counts bytes and frames passing through monitored
@ -211,24 +132,12 @@ Frame-aware AXI stream switch with parametrizable data width.
Can be generated with arbitrary port counts with axis_switch.py. Can be generated with arbitrary port counts with axis_switch.py.
### axis_switch_64_NxN module
Frame-aware AXI stream switch with tkeep signal and parametrizable data width.
Can be generated with arbitrary port counts with axis_mux_64.py.
### axis_tap module ### axis_tap module
AXI stream tap module. Used to make a copy of an AXI stream bus without AXI stream tap module. Used to make a copy of an AXI stream bus without
affecting the bus. Back-pressure on the output results in truncated frames affecting the bus. Back-pressure on the output results in truncated frames
with tuser set. with tuser set.
### axis_tap_64 module
AXI stream tap module with tkeep signal. Used to make a copy of an AXI stream
bus without affecting the bus. Back-pressure on the output results in
truncated frames with tuser set.
### ll_axis_bridge module ### ll_axis_bridge module
LocalLink to AXI stream bridge. LocalLink to AXI stream bridge.
@ -240,11 +149,28 @@ Parametrizable priority encoder.
### Common signals ### Common signals
tdata : Data (width generally DATA_WIDTH) tdata : Data (width generally DATA_WIDTH)
tkeep : Data word valid (width generally KEEP_WIDTH, present on _64 modules) tkeep : Data word valid (width generally KEEP_WIDTH)
tvalid : Data valid tvalid : Data valid
tready : Sink ready tready : Sink ready
tlast : End-of-frame tlast : End-of-frame
tuser : Bad frame (valid with tlast & tvalid) tid : Identifier tag (width generally ID_WIDTH)
tdest : Destination tag (width generally DEST_WIDTH)
tuser : User sideband signals (width generally USER_WIDTH)
### Common parameters
DATA_WIDTH : width of tdata signal
KEEP_ENABLE : enable tkeep signal (default DATA_WIDTH>8)
KEEP_WIDTH : width of tkeep signal (default DATA_WIDTH/8)
LAST_ENABLE : enable tlast signal
ID_ENABLE : enable tid signal
ID_WIDTH : width of tid signal
DEST_ENABLE : enable tdest signal
DEST_WIDTH : width of tdest signal
USER_ENABLE : enable tuser signal
USER_WIDTH : width of tuser signal
USER_BAD_FRAME_VALUE : value of tuser indicating bad frame
USER_BAD_FRAME_MASK : bitmask for tuser bad frame indication
### Source Files ### Source Files
@ -252,49 +178,29 @@ Parametrizable priority encoder.
axis_adapter.v : Parametrizable bus width adapter axis_adapter.v : Parametrizable bus width adapter
axis_arb_mux.py : Arbitrated multiplexer generator axis_arb_mux.py : Arbitrated multiplexer generator
axis_arb_mux_4.v : 4 port arbitrated multiplexer axis_arb_mux_4.v : 4 port arbitrated multiplexer
axis_arb_mux_64.py : Arbitrated multiplexer generator (64 bit)
axis_arb_mux_64_4.v : 4 port arbitrated multiplexer (64 bit)
axis_async_fifo.v : Asynchronous FIFO axis_async_fifo.v : Asynchronous FIFO
axis_async_fifo_64.v : Asynchronous FIFO (64 bit)
axis_async_frame_fifo.v : Asynchronous frame FIFO axis_async_frame_fifo.v : Asynchronous frame FIFO
axis_async_frame_fifo_64.v : Asynchronous frame FIFO (64 bit)
axis_crosspoint.py : Crosspoint switch generator axis_crosspoint.py : Crosspoint switch generator
axis_crosspoint_4x4.v : 4x4 crosspoint switch axis_crosspoint_4x4.v : 4x4 crosspoint switch
axis_crosspoint_64.py : Crosspoint switch generator (64 bit)
axis_crosspoint_64_4x4.v : 4x4 crosspoint switch (64 bit)
axis_demux.py : Demultiplexer generator axis_demux.py : Demultiplexer generator
axis_demux_4.v : 4 port demultiplexer axis_demux_4.v : 4 port demultiplexer
axis_demux_64.py : Demultiplexer generator (64 bit)
axis_demux_64_4.v : 4 port demultiplexer (64 bit)
axis_fifo.v : Synchronous FIFO axis_fifo.v : Synchronous FIFO
axis_fifo_64.v : Synchronous FIFO (64 bit)
axis_frame_fifo.v : Synchronous frame FIFO axis_frame_fifo.v : Synchronous frame FIFO
axis_frame_fifo_64.v : Synchronous frame FIFO (64 bit)
axis_frame_join.py : Frame joiner generator axis_frame_join.py : Frame joiner generator
axis_frame_join_4.v : 4 port frame joiner axis_frame_join_4.v : 4 port frame joiner
axis_frame_length_adjust.v : Frame length adjuster axis_frame_length_adjust.v : Frame length adjuster
axis_frame_length_adjust_fifo.v : Frame length adjuster with FIFO axis_frame_length_adjust_fifo.v : Frame length adjuster with FIFO
axis_frame_length_adjust_fifo_64.v : Frame length adjuster with FIFO (64 bit)
axis_ll_bridge.v : AXI stream to LocalLink bridge axis_ll_bridge.v : AXI stream to LocalLink bridge
axis_mux.py : Multiplexer generator axis_mux.py : Multiplexer generator
axis_mux_4.v : 4 port multiplexer axis_mux_4.v : 4 port multiplexer
axis_mux_64.py : Multiplexer generator (64 bit)
axis_mux_64_4.v : 4 port multiplexer (64 bit)
axis_rate_limit.v : Fractional rate limiter axis_rate_limit.v : Fractional rate limiter
axis_rate_limit_64.v : Fractional rate limiter (64 bit)
axis_register.v : AXI Stream register axis_register.v : AXI Stream register
axis_register_64.v : AXI Stream register (64 bit)
axis_srl_fifo.v : SRL-based FIFO axis_srl_fifo.v : SRL-based FIFO
axis_srl_fifo_64.v : SRL-based FIFO (64 bit)
axis_srl_register.v : SRL-based register axis_srl_register.v : SRL-based register
axis_srl_register_64.v : SRL-based register (64 bit)
axis_switch.py : AXI stream switch generator axis_switch.py : AXI stream switch generator
axis_switch_4x4.v : 4x4 port AXI stream switch axis_switch_4x4.v : 4x4 port AXI stream switch
axis_switch_64.py : AXI stream switch generator (64 bit)
axis_switch_64_4x4.v : 4x4 port AXI stream switch (64 bit)
axis_stat_counter.v : Statistics counter axis_stat_counter.v : Statistics counter
axis_tap.v : AXI stream tap axis_tap.v : AXI stream tap
axis_tap_64.v : AXI stream tap (64 bit)
ll_axis_bridge.v : LocalLink to AXI stream bridge ll_axis_bridge.v : LocalLink to AXI stream bridge
priority_encoder.v : Parametrizable priority encoder priority_encoder.v : Parametrizable priority encoder

2
lib/axis/rtl/arbiter.v
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@ -42,7 +42,7 @@ module arbiter #
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
input wire [PORTS-1:0] request, input wire [PORTS-1:0] request,
input wire [PORTS-1:0] acknowledge, input wire [PORTS-1:0] acknowledge,

184
lib/axis/rtl/axis_adapter.v
View File

@ -32,9 +32,17 @@ THE SOFTWARE.
module axis_adapter # module axis_adapter #
( (
parameter INPUT_DATA_WIDTH = 8, parameter INPUT_DATA_WIDTH = 8,
parameter INPUT_KEEP_ENABLE = (INPUT_DATA_WIDTH>8),
parameter INPUT_KEEP_WIDTH = (INPUT_DATA_WIDTH/8), parameter INPUT_KEEP_WIDTH = (INPUT_DATA_WIDTH/8),
parameter OUTPUT_DATA_WIDTH = 8, parameter OUTPUT_DATA_WIDTH = 8,
parameter OUTPUT_KEEP_WIDTH = (OUTPUT_DATA_WIDTH/8) parameter OUTPUT_KEEP_ENABLE = (OUTPUT_DATA_WIDTH>8),
parameter OUTPUT_KEEP_WIDTH = (OUTPUT_DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
) )
( (
input wire clk, input wire clk,
@ -48,7 +56,9 @@ module axis_adapter #
input wire input_axis_tvalid, input wire input_axis_tvalid,
output wire input_axis_tready, output wire input_axis_tready,
input wire input_axis_tlast, input wire input_axis_tlast,
input wire input_axis_tuser, input wire [ID_WIDTH-1:0] input_axis_tid,
input wire [DEST_WIDTH-1:0] input_axis_tdest,
input wire [USER_WIDTH-1:0] input_axis_tuser,
/* /*
* AXI output * AXI output
@ -58,31 +68,37 @@ module axis_adapter #
output wire output_axis_tvalid, output wire output_axis_tvalid,
input wire output_axis_tready, input wire output_axis_tready,
output wire output_axis_tlast, output wire output_axis_tlast,
output wire output_axis_tuser output wire [ID_WIDTH-1:0] output_axis_tid,
output wire [DEST_WIDTH-1:0] output_axis_tdest,
output wire [USER_WIDTH-1:0] output_axis_tuser
); );
// force keep width to 1 when disabled
localparam INPUT_KEEP_WIDTH_INT = INPUT_KEEP_ENABLE ? INPUT_KEEP_WIDTH : 1;
localparam OUTPUT_KEEP_WIDTH_INT = OUTPUT_KEEP_ENABLE ? OUTPUT_KEEP_WIDTH : 1;
// bus word sizes (must be identical) // bus word sizes (must be identical)
localparam INPUT_DATA_WORD_SIZE = INPUT_DATA_WIDTH / INPUT_KEEP_WIDTH; localparam INPUT_DATA_WORD_SIZE = INPUT_DATA_WIDTH / INPUT_KEEP_WIDTH_INT;
localparam OUTPUT_DATA_WORD_SIZE = OUTPUT_DATA_WIDTH / OUTPUT_KEEP_WIDTH; localparam OUTPUT_DATA_WORD_SIZE = OUTPUT_DATA_WIDTH / OUTPUT_KEEP_WIDTH_INT;
// output bus is wider // output bus is wider
localparam EXPAND_BUS = OUTPUT_KEEP_WIDTH > INPUT_KEEP_WIDTH; localparam EXPAND_BUS = OUTPUT_KEEP_WIDTH_INT > INPUT_KEEP_WIDTH_INT;
// total data and keep widths // total data and keep widths
localparam DATA_WIDTH = EXPAND_BUS ? OUTPUT_DATA_WIDTH : INPUT_DATA_WIDTH; localparam DATA_WIDTH = EXPAND_BUS ? OUTPUT_DATA_WIDTH : INPUT_DATA_WIDTH;
localparam KEEP_WIDTH = EXPAND_BUS ? OUTPUT_KEEP_WIDTH : INPUT_KEEP_WIDTH; localparam KEEP_WIDTH = EXPAND_BUS ? OUTPUT_KEEP_WIDTH_INT : INPUT_KEEP_WIDTH_INT;
// required number of cycles to match widths // required number of cycles to match widths
localparam CYCLE_COUNT = EXPAND_BUS ? (OUTPUT_KEEP_WIDTH / INPUT_KEEP_WIDTH) : (INPUT_KEEP_WIDTH / OUTPUT_KEEP_WIDTH); localparam CYCLE_COUNT = EXPAND_BUS ? (OUTPUT_KEEP_WIDTH_INT / INPUT_KEEP_WIDTH_INT) : (INPUT_KEEP_WIDTH_INT / OUTPUT_KEEP_WIDTH_INT);
// data width and keep width per cycle // data width and keep width per cycle
localparam CYCLE_DATA_WIDTH = DATA_WIDTH / CYCLE_COUNT; localparam CYCLE_DATA_WIDTH = DATA_WIDTH / CYCLE_COUNT;
localparam CYCLE_KEEP_WIDTH = KEEP_WIDTH / CYCLE_COUNT; localparam CYCLE_KEEP_WIDTH = KEEP_WIDTH / CYCLE_COUNT;
// bus width assertions // bus width assertions
initial begin initial begin
if (INPUT_DATA_WORD_SIZE * INPUT_KEEP_WIDTH != INPUT_DATA_WIDTH) begin if (INPUT_DATA_WORD_SIZE * INPUT_KEEP_WIDTH_INT != INPUT_DATA_WIDTH) begin
$error("Error: input data width not evenly divisble"); $error("Error: input data width not evenly divisble");
$finish; $finish;
end end
if (OUTPUT_DATA_WORD_SIZE * OUTPUT_KEEP_WIDTH != OUTPUT_DATA_WIDTH) begin if (OUTPUT_DATA_WORD_SIZE * OUTPUT_KEEP_WIDTH_INT != OUTPUT_DATA_WIDTH) begin
$error("Error: output data width not evenly divisble"); $error("Error: output data width not evenly divisble");
$finish; $finish;
end end
@ -108,16 +124,20 @@ reg last_cycle;
reg [DATA_WIDTH-1:0] temp_tdata_reg = {DATA_WIDTH{1'b0}}, temp_tdata_next; reg [DATA_WIDTH-1:0] temp_tdata_reg = {DATA_WIDTH{1'b0}}, temp_tdata_next;
reg [KEEP_WIDTH-1:0] temp_tkeep_reg = {KEEP_WIDTH{1'b0}}, temp_tkeep_next; reg [KEEP_WIDTH-1:0] temp_tkeep_reg = {KEEP_WIDTH{1'b0}}, temp_tkeep_next;
reg temp_tlast_reg = 1'b0, temp_tlast_next; reg temp_tlast_reg = 1'b0, temp_tlast_next;
reg temp_tuser_reg = 1'b0, temp_tuser_next; reg [ID_WIDTH-1:0] temp_tid_reg = {ID_WIDTH{1'b0}}, temp_tid_next;
reg [DEST_WIDTH-1:0] temp_tdest_reg = {DEST_WIDTH{1'b0}}, temp_tdest_next;
reg [USER_WIDTH-1:0] temp_tuser_reg = {USER_WIDTH{1'b0}}, temp_tuser_next;
// internal datapath // internal datapath
reg [OUTPUT_DATA_WIDTH-1:0] output_axis_tdata_int; reg [OUTPUT_DATA_WIDTH-1:0] output_axis_tdata_int;
reg [OUTPUT_KEEP_WIDTH-1:0] output_axis_tkeep_int; reg [OUTPUT_KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tvalid_int; reg output_axis_tvalid_int;
reg output_axis_tready_int_reg = 1'b0; reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tlast_int; reg output_axis_tlast_int;
reg output_axis_tuser_int; reg [ID_WIDTH-1:0] output_axis_tid_int;
wire output_axis_tready_int_early; reg [DEST_WIDTH-1:0] output_axis_tdest_int;
reg [USER_WIDTH-1:0] output_axis_tuser_int;
wire output_axis_tready_int_early;
reg input_axis_tready_reg = 1'b0, input_axis_tready_next; reg input_axis_tready_reg = 1'b0, input_axis_tready_next;
@ -131,13 +151,17 @@ always @* begin
temp_tdata_next = temp_tdata_reg; temp_tdata_next = temp_tdata_reg;
temp_tkeep_next = temp_tkeep_reg; temp_tkeep_next = temp_tkeep_reg;
temp_tlast_next = temp_tlast_reg; temp_tlast_next = temp_tlast_reg;
temp_tid_next = temp_tid_reg;
temp_tdest_next = temp_tdest_reg;
temp_tuser_next = temp_tuser_reg; temp_tuser_next = temp_tuser_reg;
output_axis_tdata_int = {OUTPUT_DATA_WIDTH{1'b0}}; output_axis_tdata_int = {OUTPUT_DATA_WIDTH{1'b0}};
output_axis_tkeep_int = {OUTPUT_KEEP_WIDTH{1'b0}}; output_axis_tkeep_int = {OUTPUT_KEEP_WIDTH{1'b0}};
output_axis_tvalid_int = 1'b0; output_axis_tvalid_int = 1'b0;
output_axis_tlast_int = 1'b0; output_axis_tlast_int = 1'b0;
output_axis_tuser_int = 1'b0; output_axis_tid_int = {ID_WIDTH{1'b0}};
output_axis_tdest_int = {DEST_WIDTH{1'b0}};
output_axis_tuser_int = {USER_WIDTH{1'b0}};
input_axis_tready_next = 1'b0; input_axis_tready_next = 1'b0;
@ -151,11 +175,13 @@ always @* begin
input_axis_tready_next = output_axis_tready_int_early; input_axis_tready_next = output_axis_tready_int_early;
// transfer through // transfer through
output_axis_tdata_int = input_axis_tdata; output_axis_tdata_int = input_axis_tdata;
output_axis_tkeep_int = input_axis_tkeep; output_axis_tkeep_int = INPUT_KEEP_ENABLE ? input_axis_tkeep : 1'b1;
output_axis_tvalid_int = input_axis_tvalid; output_axis_tvalid_int = input_axis_tvalid;
output_axis_tlast_int = input_axis_tlast; output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser; output_axis_tid_int = input_axis_tid;
output_axis_tdest_int = input_axis_tdest;
output_axis_tuser_int = input_axis_tuser;
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else if (EXPAND_BUS) begin end else if (EXPAND_BUS) begin
@ -166,11 +192,13 @@ always @* begin
if (input_axis_tready & input_axis_tvalid) begin if (input_axis_tready & input_axis_tvalid) begin
// word transfer in - store it in data register // word transfer in - store it in data register
// pass complete input word, zero-extended to temp register // pass complete input word, zero-extended to temp register
temp_tdata_next = input_axis_tdata; temp_tdata_next = input_axis_tdata;
temp_tkeep_next = input_axis_tkeep; temp_tkeep_next = INPUT_KEEP_ENABLE ? input_axis_tkeep : 1'b1;
temp_tlast_next = input_axis_tlast; temp_tlast_next = input_axis_tlast;
temp_tid_next = input_axis_tid;
temp_tdest_next = input_axis_tdest;
temp_tuser_next = input_axis_tuser; temp_tuser_next = input_axis_tuser;
// first input cycle complete // first input cycle complete
@ -202,10 +230,10 @@ always @* begin
if (CYCLE_COUNT == 1) begin if (CYCLE_COUNT == 1) begin
// last cycle by counter value // last cycle by counter value
last_cycle = 1'b1; last_cycle = 1'b1;
end else if (input_axis_tkeep[CYCLE_KEEP_WIDTH-1:0] != {CYCLE_KEEP_WIDTH{1'b1}}) begin end else if (INPUT_KEEP_ENABLE && input_axis_tkeep[CYCLE_KEEP_WIDTH-1:0] != {CYCLE_KEEP_WIDTH{1'b1}}) begin
// last cycle by tkeep fall in current cycle // last cycle by tkeep fall in current cycle
last_cycle = 1'b1; last_cycle = 1'b1;
end else if (input_axis_tkeep[(CYCLE_KEEP_WIDTH*2)-1:CYCLE_KEEP_WIDTH] == {CYCLE_KEEP_WIDTH{1'b0}}) begin end else if (INPUT_KEEP_ENABLE && input_axis_tkeep[(CYCLE_KEEP_WIDTH*2)-1:CYCLE_KEEP_WIDTH] == {CYCLE_KEEP_WIDTH{1'b0}}) begin
// last cycle by tkeep fall at end of current cycle // last cycle by tkeep fall at end of current cycle
last_cycle = 1'b1; last_cycle = 1'b1;
end else begin end else begin
@ -214,16 +242,20 @@ always @* begin
// pass complete input word, zero-extended to temp register // pass complete input word, zero-extended to temp register
temp_tdata_next = input_axis_tdata; temp_tdata_next = input_axis_tdata;
temp_tkeep_next = input_axis_tkeep; temp_tkeep_next = INPUT_KEEP_ENABLE ? input_axis_tkeep : 1'b1;
temp_tlast_next = input_axis_tlast; temp_tlast_next = input_axis_tlast;
temp_tid_next = input_axis_tid;
temp_tdest_next = input_axis_tdest;
temp_tuser_next = input_axis_tuser; temp_tuser_next = input_axis_tuser;
// short-circuit and get first word out the door // short-circuit and get first word out the door
output_axis_tdata_int = input_axis_tdata[CYCLE_DATA_WIDTH-1:0]; output_axis_tdata_int = input_axis_tdata[CYCLE_DATA_WIDTH-1:0];
output_axis_tkeep_int = input_axis_tkeep[CYCLE_KEEP_WIDTH-1:0]; output_axis_tkeep_int = input_axis_tkeep[CYCLE_KEEP_WIDTH-1:0];
output_axis_tvalid_int = 1'b1; output_axis_tvalid_int = 1'b1;
output_axis_tlast_int = input_axis_tlast & last_cycle; output_axis_tlast_int = input_axis_tlast & last_cycle;
output_axis_tuser_int = input_axis_tuser & last_cycle; output_axis_tid_int = input_axis_tid;
output_axis_tdest_int = input_axis_tdest;
output_axis_tuser_int = input_axis_tuser;
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
// if output register is ready for first word, then move on to the next one // if output register is ready for first word, then move on to the next one
@ -251,14 +283,16 @@ always @* begin
if (input_axis_tready & input_axis_tvalid) begin if (input_axis_tready & input_axis_tvalid) begin
// word transfer in - store in data register // word transfer in - store in data register
temp_tdata_next[cycle_count_reg*CYCLE_DATA_WIDTH +: CYCLE_DATA_WIDTH] = input_axis_tdata; temp_tdata_next[cycle_count_reg*CYCLE_DATA_WIDTH +: CYCLE_DATA_WIDTH] = input_axis_tdata;
temp_tkeep_next[cycle_count_reg*CYCLE_KEEP_WIDTH +: CYCLE_KEEP_WIDTH] = input_axis_tkeep; temp_tkeep_next[cycle_count_reg*CYCLE_KEEP_WIDTH +: CYCLE_KEEP_WIDTH] = INPUT_KEEP_ENABLE ? input_axis_tkeep : 1'b1;
temp_tlast_next = input_axis_tlast; temp_tlast_next = input_axis_tlast;
temp_tid_next = input_axis_tid;
temp_tdest_next = input_axis_tdest;
temp_tuser_next = input_axis_tuser; temp_tuser_next = input_axis_tuser;
cycle_count_next = cycle_count_reg + 1; cycle_count_next = cycle_count_reg + 1;
if ((cycle_count_reg == CYCLE_COUNT-1) | input_axis_tlast) begin if ((cycle_count_reg == CYCLE_COUNT-1) | input_axis_tlast) begin
// terminated by counter or tlast signal, output complete word // terminated by counter or tlast signal, output complete word
// read input word next cycle if output will be ready // read input word next cycle if output will be ready
@ -278,17 +312,19 @@ always @* begin
if (EXPAND_BUS) begin if (EXPAND_BUS) begin
// output bus is wider // output bus is wider
// do not accept new data // do not accept new data
input_axis_tready_next = 1'b0; input_axis_tready_next = 1'b0;
// single-cycle output of entire stored word (output wider) // single-cycle output of entire stored word (output wider)
output_axis_tdata_int = temp_tdata_reg; output_axis_tdata_int = temp_tdata_reg;
output_axis_tkeep_int = temp_tkeep_reg; output_axis_tkeep_int = temp_tkeep_reg;
output_axis_tvalid_int = 1'b1; output_axis_tvalid_int = 1'b1;
output_axis_tlast_int = temp_tlast_reg; output_axis_tlast_int = temp_tlast_reg;
output_axis_tuser_int = temp_tuser_reg; output_axis_tid_int = temp_tid_reg;
output_axis_tdest_int = temp_tdest_reg;
output_axis_tuser_int = temp_tuser_reg;
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
// word transfer out // word transfer out
@ -297,8 +333,10 @@ always @* begin
// pass complete input word, zero-extended to temp register // pass complete input word, zero-extended to temp register
temp_tdata_next = input_axis_tdata; temp_tdata_next = input_axis_tdata;
temp_tkeep_next = input_axis_tkeep; temp_tkeep_next = INPUT_KEEP_ENABLE ? input_axis_tkeep : 1'b1;
temp_tlast_next = input_axis_tlast; temp_tlast_next = input_axis_tlast;
temp_tid_next = input_axis_tid;
temp_tdest_next = input_axis_tdest;
temp_tuser_next = input_axis_tuser; temp_tuser_next = input_axis_tuser;
// first input cycle complete // first input cycle complete
@ -341,11 +379,13 @@ always @* begin
end end
// output current part of stored word (output narrower) // output current part of stored word (output narrower)
output_axis_tdata_int = temp_tdata_reg[cycle_count_reg*CYCLE_DATA_WIDTH +: CYCLE_DATA_WIDTH]; output_axis_tdata_int = temp_tdata_reg[cycle_count_reg*CYCLE_DATA_WIDTH +: CYCLE_DATA_WIDTH];
output_axis_tkeep_int = temp_tkeep_reg[cycle_count_reg*CYCLE_KEEP_WIDTH +: CYCLE_KEEP_WIDTH]; output_axis_tkeep_int = temp_tkeep_reg[cycle_count_reg*CYCLE_KEEP_WIDTH +: CYCLE_KEEP_WIDTH];
output_axis_tvalid_int = 1'b1; output_axis_tvalid_int = 1'b1;
output_axis_tlast_int = temp_tlast_reg & last_cycle; output_axis_tlast_int = temp_tlast_reg & last_cycle;
output_axis_tuser_int = temp_tuser_reg & last_cycle; output_axis_tid_int = temp_tid_reg;
output_axis_tdest_int = temp_tdest_reg;
output_axis_tuser_int = temp_tuser_reg;
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
// word transfer out // word transfer out
@ -354,7 +394,7 @@ always @* begin
if (last_cycle) begin if (last_cycle) begin
// terminated by counter or tlast signal // terminated by counter or tlast signal
input_axis_tready_next = 1'b1; input_axis_tready_next = 1'b1;
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else begin end else begin
@ -363,7 +403,7 @@ always @* begin
end end
end else begin end else begin
state_next = STATE_TRANSFER_OUT; state_next = STATE_TRANSFER_OUT;
end end
end end
end end
endcase endcase
@ -385,32 +425,40 @@ always @(posedge clk) begin
temp_tdata_reg <= temp_tdata_next; temp_tdata_reg <= temp_tdata_next;
temp_tkeep_reg <= temp_tkeep_next; temp_tkeep_reg <= temp_tkeep_next;
temp_tlast_reg <= temp_tlast_next; temp_tlast_reg <= temp_tlast_next;
temp_tuser_reg <= temp_tuser_next; temp_tid_reg <= temp_tid_next;
temp_tdest_reg <= temp_tdest_next;
temp_tuser_reg <= temp_tuser_next;
end end
// output datapath logic // output datapath logic
reg [OUTPUT_DATA_WIDTH-1:0] output_axis_tdata_reg = {OUTPUT_DATA_WIDTH{1'b0}}; reg [OUTPUT_DATA_WIDTH-1:0] output_axis_tdata_reg = {OUTPUT_DATA_WIDTH{1'b0}};
reg [OUTPUT_KEEP_WIDTH-1:0] output_axis_tkeep_reg = {OUTPUT_KEEP_WIDTH{1'b0}}; reg [OUTPUT_KEEP_WIDTH-1:0] output_axis_tkeep_reg = {OUTPUT_KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next; reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0; reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] output_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] output_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [OUTPUT_DATA_WIDTH-1:0] temp_axis_tdata_reg = {OUTPUT_DATA_WIDTH{1'b0}}; reg [OUTPUT_DATA_WIDTH-1:0] temp_axis_tdata_reg = {OUTPUT_DATA_WIDTH{1'b0}};
reg [OUTPUT_KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {OUTPUT_KEEP_WIDTH{1'b0}}; reg [OUTPUT_KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {OUTPUT_KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next; reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0; reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] temp_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control // datapath control
reg store_axis_int_to_output; reg store_axis_int_to_output;
reg store_axis_int_to_temp; reg store_axis_int_to_temp;
reg store_axis_temp_to_output; reg store_axis_temp_to_output;
assign output_axis_tdata = output_axis_tdata_reg; assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = output_axis_tkeep_reg; assign output_axis_tkeep = OUTPUT_KEEP_ENABLE ? output_axis_tkeep_reg : {OUTPUT_KEEP_WIDTH{1'b1}};
assign output_axis_tvalid = output_axis_tvalid_reg; assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg; assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg; assign output_axis_tid = ID_ENABLE ? output_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_axis_tdest = DEST_ENABLE ? output_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign output_axis_tuser = USER_ENABLE ? output_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int)); assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
@ -423,7 +471,7 @@ always @* begin
store_axis_int_to_output = 1'b0; store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0; store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0; store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
// input is ready // input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin if (output_axis_tready | ~output_axis_tvalid_reg) begin
@ -459,11 +507,15 @@ always @(posedge clk) begin
output_axis_tdata_reg <= output_axis_tdata_int; output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int; output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tlast_reg <= output_axis_tlast_int; output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tid_reg <= output_axis_tid_int;
output_axis_tdest_reg <= output_axis_tdest_int;
output_axis_tuser_reg <= output_axis_tuser_int; output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg; output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg; output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg; output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tid_reg <= temp_axis_tid_reg;
output_axis_tdest_reg <= temp_axis_tdest_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg; output_axis_tuser_reg <= temp_axis_tuser_reg;
end end
@ -471,6 +523,8 @@ always @(posedge clk) begin
temp_axis_tdata_reg <= output_axis_tdata_int; temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int; temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tlast_reg <= output_axis_tlast_int; temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tid_reg <= output_axis_tid_int;
temp_axis_tdest_reg <= output_axis_tdest_int;
temp_axis_tuser_reg <= output_axis_tuser_int; temp_axis_tuser_reg <= output_axis_tuser_int;
end end
end end

40
lib/axis/rtl/axis_arb_mux.py
View File

@ -72,6 +72,14 @@ THE SOFTWARE.
module {{name}} # module {{name}} #
( (
parameter DATA_WIDTH = 8, parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
// arbitration type: "PRIORITY" or "ROUND_ROBIN" // arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY", parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH" // LSB priority: "LOW", "HIGH"
@ -80,25 +88,31 @@ module {{name}} #
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
/* /*
* AXI inputs * AXI inputs
*/ */
{%- for p in ports %} {%- for p in ports %}
input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata, input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep,
input wire input_{{p}}_axis_tvalid, input wire input_{{p}}_axis_tvalid,
output wire input_{{p}}_axis_tready, output wire input_{{p}}_axis_tready,
input wire input_{{p}}_axis_tlast, input wire input_{{p}}_axis_tlast,
input wire input_{{p}}_axis_tuser, input wire [ID_WIDTH-1:0] input_{{p}}_axis_tid,
input wire [DEST_WIDTH-1:0] input_{{p}}_axis_tdest,
input wire [USER_WIDTH-1:0] input_{{p}}_axis_tuser,
{% endfor %} {% endfor %}
/* /*
* AXI output * AXI output
*/ */
output wire [DATA_WIDTH-1:0] output_axis_tdata, output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid, output wire output_axis_tvalid,
input wire output_axis_tready, input wire output_axis_tready,
output wire output_axis_tlast, output wire output_axis_tlast,
output wire output_axis_tuser output wire [ID_WIDTH-1:0] output_axis_tid,
output wire [DEST_WIDTH-1:0] output_axis_tdest,
output wire [USER_WIDTH-1:0] output_axis_tuser
); );
wire [{{n-1}}:0] request; wire [{{n-1}}:0] request;
@ -113,22 +127,36 @@ assign request[{{p}}] = input_{{p}}_axis_tvalid & ~acknowledge[{{p}}];
// mux instance // mux instance
axis_mux_{{n}} #( axis_mux_{{n}} #(
.DATA_WIDTH(DATA_WIDTH) .DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) )
mux_inst ( mux_inst (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
{%- for p in ports %} {%- for p in ports %}
.input_{{p}}_axis_tdata(input_{{p}}_axis_tdata), .input_{{p}}_axis_tdata(input_{{p}}_axis_tdata),
.input_{{p}}_axis_tkeep(input_{{p}}_axis_tkeep),
.input_{{p}}_axis_tvalid(input_{{p}}_axis_tvalid & grant[{{p}}]), .input_{{p}}_axis_tvalid(input_{{p}}_axis_tvalid & grant[{{p}}]),
.input_{{p}}_axis_tready(input_{{p}}_axis_tready), .input_{{p}}_axis_tready(input_{{p}}_axis_tready),
.input_{{p}}_axis_tlast(input_{{p}}_axis_tlast), .input_{{p}}_axis_tlast(input_{{p}}_axis_tlast),
.input_{{p}}_axis_tid(input_{{p}}_axis_tid),
.input_{{p}}_axis_tdest(input_{{p}}_axis_tdest),
.input_{{p}}_axis_tuser(input_{{p}}_axis_tuser), .input_{{p}}_axis_tuser(input_{{p}}_axis_tuser),
{%- endfor %} {%- endfor %}
.output_axis_tdata(output_axis_tdata), .output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser), .output_axis_tuser(output_axis_tuser),
.enable(grant_valid), .enable(grant_valid),
.select(grant_encoded) .select(grant_encoded)
@ -154,14 +182,14 @@ arb_inst (
endmodule endmodule
""") """)
output_file.write(t.render( output_file.write(t.render(
n=ports, n=ports,
w=select_width, w=select_width,
name=name, name=name,
ports=range(ports) ports=range(ports)
)) ))
print("Done") print("Done")
if __name__ == "__main__": if __name__ == "__main__":

60
lib/axis/rtl/axis_arb_mux_4.v
View File

@ -32,6 +32,14 @@ THE SOFTWARE.
module axis_arb_mux_4 # module axis_arb_mux_4 #
( (
parameter DATA_WIDTH = 8, parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
// arbitration type: "PRIORITY" or "ROUND_ROBIN" // arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY", parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH" // LSB priority: "LOW", "HIGH"
@ -40,42 +48,57 @@ module axis_arb_mux_4 #
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
/* /*
* AXI inputs * AXI inputs
*/ */
input wire [DATA_WIDTH-1:0] input_0_axis_tdata, input wire [DATA_WIDTH-1:0] input_0_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_0_axis_tkeep,
input wire input_0_axis_tvalid, input wire input_0_axis_tvalid,
output wire input_0_axis_tready, output wire input_0_axis_tready,
input wire input_0_axis_tlast, input wire input_0_axis_tlast,
input wire input_0_axis_tuser, input wire [ID_WIDTH-1:0] input_0_axis_tid,
input wire [DEST_WIDTH-1:0] input_0_axis_tdest,
input wire [USER_WIDTH-1:0] input_0_axis_tuser,
input wire [DATA_WIDTH-1:0] input_1_axis_tdata, input wire [DATA_WIDTH-1:0] input_1_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_1_axis_tkeep,
input wire input_1_axis_tvalid, input wire input_1_axis_tvalid,
output wire input_1_axis_tready, output wire input_1_axis_tready,
input wire input_1_axis_tlast, input wire input_1_axis_tlast,
input wire input_1_axis_tuser, input wire [ID_WIDTH-1:0] input_1_axis_tid,
input wire [DEST_WIDTH-1:0] input_1_axis_tdest,
input wire [USER_WIDTH-1:0] input_1_axis_tuser,
input wire [DATA_WIDTH-1:0] input_2_axis_tdata, input wire [DATA_WIDTH-1:0] input_2_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_2_axis_tkeep,
input wire input_2_axis_tvalid, input wire input_2_axis_tvalid,
output wire input_2_axis_tready, output wire input_2_axis_tready,
input wire input_2_axis_tlast, input wire input_2_axis_tlast,
input wire input_2_axis_tuser, input wire [ID_WIDTH-1:0] input_2_axis_tid,
input wire [DEST_WIDTH-1:0] input_2_axis_tdest,
input wire [USER_WIDTH-1:0] input_2_axis_tuser,
input wire [DATA_WIDTH-1:0] input_3_axis_tdata, input wire [DATA_WIDTH-1:0] input_3_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_3_axis_tkeep,
input wire input_3_axis_tvalid, input wire input_3_axis_tvalid,
output wire input_3_axis_tready, output wire input_3_axis_tready,
input wire input_3_axis_tlast, input wire input_3_axis_tlast,
input wire input_3_axis_tuser, input wire [ID_WIDTH-1:0] input_3_axis_tid,
input wire [DEST_WIDTH-1:0] input_3_axis_tdest,
input wire [USER_WIDTH-1:0] input_3_axis_tuser,
/* /*
* AXI output * AXI output
*/ */
output wire [DATA_WIDTH-1:0] output_axis_tdata, output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid, output wire output_axis_tvalid,
input wire output_axis_tready, input wire output_axis_tready,
output wire output_axis_tlast, output wire output_axis_tlast,
output wire output_axis_tuser output wire [ID_WIDTH-1:0] output_axis_tid,
output wire [DEST_WIDTH-1:0] output_axis_tdest,
output wire [USER_WIDTH-1:0] output_axis_tuser
); );
wire [3:0] request; wire [3:0] request;
@ -95,35 +118,58 @@ assign request[3] = input_3_axis_tvalid & ~acknowledge[3];
// mux instance // mux instance
axis_mux_4 #( axis_mux_4 #(
.DATA_WIDTH(DATA_WIDTH) .DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) )
mux_inst ( mux_inst (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
.input_0_axis_tdata(input_0_axis_tdata), .input_0_axis_tdata(input_0_axis_tdata),
.input_0_axis_tkeep(input_0_axis_tkeep),
.input_0_axis_tvalid(input_0_axis_tvalid & grant[0]), .input_0_axis_tvalid(input_0_axis_tvalid & grant[0]),
.input_0_axis_tready(input_0_axis_tready), .input_0_axis_tready(input_0_axis_tready),
.input_0_axis_tlast(input_0_axis_tlast), .input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tid(input_0_axis_tid),
.input_0_axis_tdest(input_0_axis_tdest),
.input_0_axis_tuser(input_0_axis_tuser), .input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata), .input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tkeep(input_1_axis_tkeep),
.input_1_axis_tvalid(input_1_axis_tvalid & grant[1]), .input_1_axis_tvalid(input_1_axis_tvalid & grant[1]),
.input_1_axis_tready(input_1_axis_tready), .input_1_axis_tready(input_1_axis_tready),
.input_1_axis_tlast(input_1_axis_tlast), .input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tid(input_1_axis_tid),
.input_1_axis_tdest(input_1_axis_tdest),
.input_1_axis_tuser(input_1_axis_tuser), .input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata), .input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tkeep(input_2_axis_tkeep),
.input_2_axis_tvalid(input_2_axis_tvalid & grant[2]), .input_2_axis_tvalid(input_2_axis_tvalid & grant[2]),
.input_2_axis_tready(input_2_axis_tready), .input_2_axis_tready(input_2_axis_tready),
.input_2_axis_tlast(input_2_axis_tlast), .input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tid(input_2_axis_tid),
.input_2_axis_tdest(input_2_axis_tdest),
.input_2_axis_tuser(input_2_axis_tuser), .input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata), .input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tkeep(input_3_axis_tkeep),
.input_3_axis_tvalid(input_3_axis_tvalid & grant[3]), .input_3_axis_tvalid(input_3_axis_tvalid & grant[3]),
.input_3_axis_tready(input_3_axis_tready), .input_3_axis_tready(input_3_axis_tready),
.input_3_axis_tlast(input_3_axis_tlast), .input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tid(input_3_axis_tid),
.input_3_axis_tdest(input_3_axis_tdest),
.input_3_axis_tuser(input_3_axis_tuser), .input_3_axis_tuser(input_3_axis_tuser),
.output_axis_tdata(output_axis_tdata), .output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser), .output_axis_tuser(output_axis_tuser),
.enable(grant_valid), .enable(grant_valid),
.select(grant_encoded) .select(grant_encoded)

174
lib/axis/rtl/axis_arb_mux_64.py
View File

@ -1,174 +0,0 @@
#!/usr/bin/env python
"""
Generates an arbitrated AXI Stream mux with the specified number of ports
"""
from __future__ import print_function
import argparse
import math
from jinja2 import Template
def main():
parser = argparse.ArgumentParser(description=__doc__.strip())
parser.add_argument('-p', '--ports', type=int, default=4, help="number of ports")
parser.add_argument('-n', '--name', type=str, help="module name")
parser.add_argument('-o', '--output', type=str, help="output file name")
args = parser.parse_args()
try:
generate(**args.__dict__)
except IOError as ex:
print(ex)
exit(1)
def generate(ports=4, name=None, output=None):
if name is None:
name = "axis_arb_mux_64_{0}".format(ports)
if output is None:
output = name + ".v"
print("Opening file '{0}'...".format(output))
output_file = open(output, 'w')
print("Generating {0} port AXI Stream arbitrated mux {1}...".format(ports, name))
select_width = int(math.ceil(math.log(ports, 2)))
t = Template(u"""/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream {{n}} port arbitrated multiplexer (64 bit datapath)
*/
module {{name}} #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
)
(
input wire clk,
input wire rst,
/*
* AXI inputs
*/
{%- for p in ports %}
input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep,
input wire input_{{p}}_axis_tvalid,
output wire input_{{p}}_axis_tready,
input wire input_{{p}}_axis_tlast,
input wire input_{{p}}_axis_tuser,
{% endfor %}
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
wire [{{n-1}}:0] request;
wire [{{n-1}}:0] acknowledge;
wire [{{n-1}}:0] grant;
wire grant_valid;
wire [{{w-1}}:0] grant_encoded;
{% for p in ports %}
assign acknowledge[{{p}}] = input_{{p}}_axis_tvalid & input_{{p}}_axis_tready & input_{{p}}_axis_tlast;
assign request[{{p}}] = input_{{p}}_axis_tvalid & ~acknowledge[{{p}}];
{%- endfor %}
// mux instance
axis_mux_64_{{n}} #(
.DATA_WIDTH(DATA_WIDTH)
)
mux_inst (
.clk(clk),
.rst(rst),
{%- for p in ports %}
.input_{{p}}_axis_tdata(input_{{p}}_axis_tdata),
.input_{{p}}_axis_tkeep(input_{{p}}_axis_tkeep),
.input_{{p}}_axis_tvalid(input_{{p}}_axis_tvalid & grant[{{p}}]),
.input_{{p}}_axis_tready(input_{{p}}_axis_tready),
.input_{{p}}_axis_tlast(input_{{p}}_axis_tlast),
.input_{{p}}_axis_tuser(input_{{p}}_axis_tuser),
{%- endfor %}
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
.enable(grant_valid),
.select(grant_encoded)
);
// arbiter instance
arbiter #(
.PORTS({{n}}),
.TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
)
arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
endmodule
""")
output_file.write(t.render(
n=ports,
w=select_width,
name=name,
ports=range(ports)
))
print("Done")
if __name__ == "__main__":
main()

160
lib/axis/rtl/axis_arb_mux_64_4.v
View File

@ -1,160 +0,0 @@
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream 4 port arbitrated multiplexer (64 bit datapath)
*/
module axis_arb_mux_64_4 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
)
(
input wire clk,
input wire rst,
/*
* AXI inputs
*/
input wire [DATA_WIDTH-1:0] input_0_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_0_axis_tkeep,
input wire input_0_axis_tvalid,
output wire input_0_axis_tready,
input wire input_0_axis_tlast,
input wire input_0_axis_tuser,
input wire [DATA_WIDTH-1:0] input_1_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_1_axis_tkeep,
input wire input_1_axis_tvalid,
output wire input_1_axis_tready,
input wire input_1_axis_tlast,
input wire input_1_axis_tuser,
input wire [DATA_WIDTH-1:0] input_2_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_2_axis_tkeep,
input wire input_2_axis_tvalid,
output wire input_2_axis_tready,
input wire input_2_axis_tlast,
input wire input_2_axis_tuser,
input wire [DATA_WIDTH-1:0] input_3_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_3_axis_tkeep,
input wire input_3_axis_tvalid,
output wire input_3_axis_tready,
input wire input_3_axis_tlast,
input wire input_3_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
wire [3:0] request;
wire [3:0] acknowledge;
wire [3:0] grant;
wire grant_valid;
wire [1:0] grant_encoded;
assign acknowledge[0] = input_0_axis_tvalid & input_0_axis_tready & input_0_axis_tlast;
assign request[0] = input_0_axis_tvalid & ~acknowledge[0];
assign acknowledge[1] = input_1_axis_tvalid & input_1_axis_tready & input_1_axis_tlast;
assign request[1] = input_1_axis_tvalid & ~acknowledge[1];
assign acknowledge[2] = input_2_axis_tvalid & input_2_axis_tready & input_2_axis_tlast;
assign request[2] = input_2_axis_tvalid & ~acknowledge[2];
assign acknowledge[3] = input_3_axis_tvalid & input_3_axis_tready & input_3_axis_tlast;
assign request[3] = input_3_axis_tvalid & ~acknowledge[3];
// mux instance
axis_mux_64_4 #(
.DATA_WIDTH(DATA_WIDTH)
)
mux_inst (
.clk(clk),
.rst(rst),
.input_0_axis_tdata(input_0_axis_tdata),
.input_0_axis_tkeep(input_0_axis_tkeep),
.input_0_axis_tvalid(input_0_axis_tvalid & grant[0]),
.input_0_axis_tready(input_0_axis_tready),
.input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tkeep(input_1_axis_tkeep),
.input_1_axis_tvalid(input_1_axis_tvalid & grant[1]),
.input_1_axis_tready(input_1_axis_tready),
.input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tkeep(input_2_axis_tkeep),
.input_2_axis_tvalid(input_2_axis_tvalid & grant[2]),
.input_2_axis_tready(input_2_axis_tready),
.input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tkeep(input_3_axis_tkeep),
.input_3_axis_tvalid(input_3_axis_tvalid & grant[3]),
.input_3_axis_tready(input_3_axis_tready),
.input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tuser(input_3_axis_tuser),
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
.enable(grant_valid),
.select(grant_encoded)
);
// arbiter instance
arbiter #(
.PORTS(4),
.TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
)
arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
endmodule

59
lib/axis/rtl/axis_async_fifo.v
View File

@ -32,7 +32,16 @@ THE SOFTWARE.
module axis_async_fifo # module axis_async_fifo #
( (
parameter ADDR_WIDTH = 12, parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 8 parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter LAST_ENABLE = 1,
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
) )
( (
/* /*
@ -45,22 +54,35 @@ module axis_async_fifo #
*/ */
input wire input_clk, input wire input_clk,
input wire [DATA_WIDTH-1:0] input_axis_tdata, input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid, input wire input_axis_tvalid,
output wire input_axis_tready, output wire input_axis_tready,
input wire input_axis_tlast, input wire input_axis_tlast,
input wire input_axis_tuser, input wire [ID_WIDTH-1:0] input_axis_tid,
input wire [DEST_WIDTH-1:0] input_axis_tdest,
input wire [USER_WIDTH-1:0] input_axis_tuser,
/* /*
* AXI output * AXI output
*/ */
input wire output_clk, input wire output_clk,
output wire [DATA_WIDTH-1:0] output_axis_tdata, output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid, output wire output_axis_tvalid,
input wire output_axis_tready, input wire output_axis_tready,
output wire output_axis_tlast, output wire output_axis_tlast,
output wire output_axis_tuser output wire [ID_WIDTH-1:0] output_axis_tid,
output wire [DEST_WIDTH-1:0] output_axis_tdest,
output wire [USER_WIDTH-1:0] output_axis_tuser
); );
localparam KEEP_OFFSET = DATA_WIDTH;
localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0);
localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next; reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next; reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next;
reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}}; reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
@ -80,13 +102,13 @@ reg output_rst_sync1_reg = 1'b1;
reg output_rst_sync2_reg = 1'b1; reg output_rst_sync2_reg = 1'b1;
reg output_rst_sync3_reg = 1'b1; reg output_rst_sync3_reg = 1'b1;
reg [DATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0]; reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+2-1:0] mem_read_data_reg = {DATA_WIDTH+2{1'b0}}; reg [WIDTH-1:0] mem_read_data_reg;
reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next; reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
wire [DATA_WIDTH+2-1:0] mem_write_data;
reg [DATA_WIDTH+2-1:0] output_data_reg = {DATA_WIDTH+2{1'b0}}; wire [WIDTH-1:0] input_axis;
reg [WIDTH-1:0] output_axis_reg;
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next; reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
// full when first TWO MSBs do NOT match, but rest matches // full when first TWO MSBs do NOT match, but rest matches
@ -104,10 +126,23 @@ reg store_output;
assign input_axis_tready = ~full & ~input_rst_sync3_reg; assign input_axis_tready = ~full & ~input_rst_sync3_reg;
generate
assign input_axis[DATA_WIDTH-1:0] = input_axis_tdata;
if (KEEP_ENABLE) assign input_axis[KEEP_OFFSET +: KEEP_WIDTH] = input_axis_tkeep;
if (LAST_ENABLE) assign input_axis[LAST_OFFSET] = input_axis_tlast;
if (ID_ENABLE) assign input_axis[ID_OFFSET +: ID_WIDTH] = input_axis_tid;
if (DEST_ENABLE) assign input_axis[DEST_OFFSET +: DEST_WIDTH] = input_axis_tdest;
if (USER_ENABLE) assign input_axis[USER_OFFSET +: USER_WIDTH] = input_axis_tuser;
endgenerate
assign output_axis_tvalid = output_axis_tvalid_reg; assign output_axis_tvalid = output_axis_tvalid_reg;
assign mem_write_data = {input_axis_tlast, input_axis_tuser, input_axis_tdata}; assign output_axis_tdata = output_axis_reg[DATA_WIDTH-1:0];
assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = output_data_reg; assign output_axis_tkeep = KEEP_ENABLE ? output_axis_reg[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
assign output_axis_tlast = LAST_ENABLE ? output_axis_reg[LAST_OFFSET] : 1'b1;
assign output_axis_tid = ID_ENABLE ? output_axis_reg[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}};
assign output_axis_tdest = DEST_ENABLE ? output_axis_reg[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
assign output_axis_tuser = USER_ENABLE ? output_axis_reg[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
// reset synchronization // reset synchronization
always @(posedge input_clk or posedge async_rst) begin always @(posedge input_clk or posedge async_rst) begin
@ -164,7 +199,7 @@ always @(posedge input_clk) begin
wr_addr_reg <= wr_ptr_next; wr_addr_reg <= wr_ptr_next;
if (write) begin if (write) begin
mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data; mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= input_axis;
end end
end end
@ -251,7 +286,7 @@ always @(posedge output_clk) begin
end end
if (store_output) begin if (store_output) begin
output_data_reg <= mem_read_data_reg; output_axis_reg <= mem_read_data_reg;
end end
end end

261
lib/axis/rtl/axis_async_fifo_64.v
View File

@ -1,261 +0,0 @@
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream asynchronous FIFO (64 bit datapath)
*/
module axis_async_fifo_64 #
(
parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
/*
* Common asynchronous reset
*/
input wire async_rst,
/*
* AXI input
*/
input wire input_clk,
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
input wire output_clk,
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next;
reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_gray_next;
reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
reg input_rst_sync1_reg = 1'b1;
reg input_rst_sync2_reg = 1'b1;
reg input_rst_sync3_reg = 1'b1;
reg output_rst_sync1_reg = 1'b1;
reg output_rst_sync2_reg = 1'b1;
reg output_rst_sync3_reg = 1'b1;
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem_read_data_reg = {DATA_WIDTH+KEEP_WIDTH+2{1'b0}};
reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
wire [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem_write_data;
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] output_data_reg = {DATA_WIDTH+KEEP_WIDTH+2{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
// full when first TWO MSBs do NOT match, but rest matches
// (gray code equivalent of first MSB different but rest same)
wire full = ((wr_ptr_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) &&
(wr_ptr_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) &&
(wr_ptr_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0]));
// empty when pointers match exactly
wire empty = rd_ptr_gray_reg == wr_ptr_gray_sync2_reg;
// control signals
reg write;
reg read;
reg store_output;
assign input_axis_tready = ~full & ~input_rst_sync3_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign mem_write_data = {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};
assign {output_axis_tlast, output_axis_tuser, output_axis_tkeep, output_axis_tdata} = output_data_reg;
// reset synchronization
always @(posedge input_clk or posedge async_rst) begin
if (async_rst) begin
input_rst_sync1_reg <= 1'b1;
input_rst_sync2_reg <= 1'b1;
input_rst_sync3_reg <= 1'b1;
end else begin
input_rst_sync1_reg <= 1'b0;
input_rst_sync2_reg <= input_rst_sync1_reg | output_rst_sync1_reg;
input_rst_sync3_reg <= input_rst_sync2_reg;
end
end
always @(posedge output_clk or posedge async_rst) begin
if (async_rst) begin
output_rst_sync1_reg <= 1'b1;
output_rst_sync2_reg <= 1'b1;
output_rst_sync3_reg <= 1'b1;
end else begin
output_rst_sync1_reg <= 1'b0;
output_rst_sync2_reg <= input_rst_sync1_reg | output_rst_sync1_reg;
output_rst_sync3_reg <= output_rst_sync2_reg;
end
end
// Write logic
always @* begin
write = 1'b0;
wr_ptr_next = wr_ptr_reg;
wr_ptr_gray_next = wr_ptr_gray_reg;
if (input_axis_tvalid) begin
// input data valid
if (~full) begin
// not full, perform write
write = 1'b1;
wr_ptr_next = wr_ptr_reg + 1;
wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1);
end
end
end
always @(posedge input_clk) begin
if (input_rst_sync3_reg) begin
wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
end else begin
wr_ptr_reg <= wr_ptr_next;
wr_ptr_gray_reg <= wr_ptr_gray_next;
end
wr_addr_reg <= wr_ptr_next;
if (write) begin
mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
// pointer synchronization
always @(posedge input_clk) begin
if (input_rst_sync3_reg) begin
rd_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
rd_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
end else begin
rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg;
rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg;
end
end
always @(posedge output_clk) begin
if (output_rst_sync3_reg) begin
wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
end else begin
wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg;
wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg;
end
end
// Read logic
always @* begin
read = 1'b0;
rd_ptr_next = rd_ptr_reg;
rd_ptr_gray_next = rd_ptr_gray_reg;
mem_read_data_valid_next = mem_read_data_valid_reg;
if (store_output | ~mem_read_data_valid_reg) begin
// output data not valid OR currently being transferred
if (~empty) begin
// not empty, perform read
read = 1'b1;
mem_read_data_valid_next = 1'b1;
rd_ptr_next = rd_ptr_reg + 1;
rd_ptr_gray_next = rd_ptr_next ^ (rd_ptr_next >> 1);
end else begin
// empty, invalidate
mem_read_data_valid_next = 1'b0;
end
end
end
always @(posedge output_clk) begin
if (output_rst_sync3_reg) begin
rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
rd_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
mem_read_data_valid_reg <= 1'b0;
end else begin
rd_ptr_reg <= rd_ptr_next;
rd_ptr_gray_reg <= rd_ptr_gray_next;
mem_read_data_valid_reg <= mem_read_data_valid_next;
end
rd_addr_reg <= rd_ptr_next;
if (read) begin
mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]];
end
end
// Output register
always @* begin
store_output = 1'b0;
output_axis_tvalid_next = output_axis_tvalid_reg;
if (output_axis_tready | ~output_axis_tvalid) begin
store_output = 1'b1;
output_axis_tvalid_next = mem_read_data_valid_reg;
end
end
always @(posedge output_clk) begin
if (output_rst_sync3_reg) begin
output_axis_tvalid_reg <= 1'b0;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
end
if (store_output) begin
output_data_reg <= mem_read_data_reg;
end
end
endmodule

60
lib/axis/rtl/axis_async_frame_fifo.v
View File

@ -33,6 +33,17 @@ module axis_async_frame_fifo #
( (
parameter ADDR_WIDTH = 12, parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 8, parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
parameter USER_BAD_FRAME_VALUE = 1'b1,
parameter USER_BAD_FRAME_MASK = 1'b1,
parameter DROP_BAD_FRAME = 1,
parameter DROP_WHEN_FULL = 0 parameter DROP_WHEN_FULL = 0
) )
( (
@ -46,19 +57,26 @@ module axis_async_frame_fifo #
*/ */
input wire input_clk, input wire input_clk,
input wire [DATA_WIDTH-1:0] input_axis_tdata, input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid, input wire input_axis_tvalid,
output wire input_axis_tready, output wire input_axis_tready,
input wire input_axis_tlast, input wire input_axis_tlast,
input wire input_axis_tuser, input wire [ID_WIDTH-1:0] input_axis_tid,
input wire [DEST_WIDTH-1:0] input_axis_tdest,
input wire [USER_WIDTH-1:0] input_axis_tuser,
/* /*
* AXI output * AXI output
*/ */
input wire output_clk, input wire output_clk,
output wire [DATA_WIDTH-1:0] output_axis_tdata, output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid, output wire output_axis_tvalid,
input wire output_axis_tready, input wire output_axis_tready,
output wire output_axis_tlast, output wire output_axis_tlast,
output wire [ID_WIDTH-1:0] output_axis_tid,
output wire [DEST_WIDTH-1:0] output_axis_tdest,
output wire [USER_WIDTH-1:0] output_axis_tuser,
/* /*
* Status * Status
@ -71,6 +89,13 @@ module axis_async_frame_fifo #
output wire output_status_good_frame output wire output_status_good_frame
); );
localparam KEEP_OFFSET = DATA_WIDTH;
localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
localparam ID_OFFSET = LAST_OFFSET + 1;
localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next; reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next; reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next;
reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next; reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next;
@ -91,13 +116,13 @@ reg output_rst_sync1_reg = 1'b1;
reg output_rst_sync2_reg = 1'b1; reg output_rst_sync2_reg = 1'b1;
reg output_rst_sync3_reg = 1'b1; reg output_rst_sync3_reg = 1'b1;
reg [DATA_WIDTH+1-1:0] mem[(2**ADDR_WIDTH)-1:0]; reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+1-1:0] mem_read_data_reg = {DATA_WIDTH+1{1'b0}}; reg [WIDTH-1:0] mem_read_data_reg;
reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next; reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
wire [DATA_WIDTH+1-1:0] mem_write_data;
reg [DATA_WIDTH+1-1:0] output_data_reg = {DATA_WIDTH+1{1'b0}}; wire [WIDTH-1:0] input_axis;
reg [WIDTH-1:0] output_axis_reg;
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next; reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
// full when first TWO MSBs do NOT match, but rest matches // full when first TWO MSBs do NOT match, but rest matches
@ -136,10 +161,23 @@ reg good_frame_sync4_reg = 1'b0;
assign input_axis_tready = (~full | DROP_WHEN_FULL) & ~input_rst_sync3_reg; assign input_axis_tready = (~full | DROP_WHEN_FULL) & ~input_rst_sync3_reg;
generate
assign input_axis[DATA_WIDTH-1:0] = input_axis_tdata;
if (KEEP_ENABLE) assign input_axis[KEEP_OFFSET +: KEEP_WIDTH] = input_axis_tkeep;
assign input_axis[LAST_OFFSET] = input_axis_tlast;
if (ID_ENABLE) assign input_axis[ID_OFFSET +: ID_WIDTH] = input_axis_tid;
if (DEST_ENABLE) assign input_axis[DEST_OFFSET +: DEST_WIDTH] = input_axis_tdest;
if (USER_ENABLE) assign input_axis[USER_OFFSET +: USER_WIDTH] = input_axis_tuser;
endgenerate
assign output_axis_tvalid = output_axis_tvalid_reg; assign output_axis_tvalid = output_axis_tvalid_reg;
assign mem_write_data = {input_axis_tlast, input_axis_tdata}; assign output_axis_tdata = output_axis_reg[DATA_WIDTH-1:0];
assign {output_axis_tlast, output_axis_tdata} = output_data_reg; assign output_axis_tkeep = KEEP_ENABLE ? output_axis_reg[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
assign output_axis_tlast = output_axis_reg[LAST_OFFSET];
assign output_axis_tid = ID_ENABLE ? output_axis_reg[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}};
assign output_axis_tdest = DEST_ENABLE ? output_axis_reg[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
assign output_axis_tuser = USER_ENABLE ? output_axis_reg[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
assign input_status_overflow = overflow_reg; assign input_status_overflow = overflow_reg;
assign input_status_bad_frame = bad_frame_reg; assign input_status_bad_frame = bad_frame_reg;
@ -206,7 +244,7 @@ always @* begin
wr_ptr_cur_next = wr_ptr_cur_reg + 1; wr_ptr_cur_next = wr_ptr_cur_reg + 1;
if (input_axis_tlast) begin if (input_axis_tlast) begin
// end of frame // end of frame
if (input_axis_tuser) begin if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & input_axis_tuser == USER_BAD_FRAME_VALUE)) begin
// bad packet, reset write pointer // bad packet, reset write pointer
wr_ptr_cur_next = wr_ptr_reg; wr_ptr_cur_next = wr_ptr_reg;
bad_frame_next = 1'b1; bad_frame_next = 1'b1;
@ -246,7 +284,7 @@ always @(posedge input_clk) begin
wr_addr_reg <= wr_ptr_cur_next; wr_addr_reg <= wr_ptr_cur_next;
if (write) begin if (write) begin
mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data; mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= input_axis;
end end
end end
@ -367,7 +405,7 @@ always @(posedge output_clk) begin
end end
if (store_output) begin if (store_output) begin
output_data_reg <= mem_read_data_reg; output_axis_reg <= mem_read_data_reg;
end end
end end

377
lib/axis/rtl/axis_async_frame_fifo_64.v
View File

@ -1,377 +0,0 @@
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream asynchronous frame FIFO (64 bit datapath)
*/
module axis_async_frame_fifo_64 #
(
parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter DROP_WHEN_FULL = 0
)
(
/*
* Common asynchronous reset
*/
input wire async_rst,
/*
* AXI input
*/
input wire input_clk,
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
input wire output_clk,
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
/*
* Status
*/
output wire input_status_overflow,
output wire input_status_bad_frame,
output wire input_status_good_frame,
output wire output_status_overflow,
output wire output_status_bad_frame,
output wire output_status_good_frame
);
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next;
reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next;
reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_gray_next;
reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
reg input_rst_sync1_reg = 1'b1;
reg input_rst_sync2_reg = 1'b1;
reg input_rst_sync3_reg = 1'b1;
reg output_rst_sync1_reg = 1'b1;
reg output_rst_sync2_reg = 1'b1;
reg output_rst_sync3_reg = 1'b1;
reg [DATA_WIDTH+KEEP_WIDTH+1-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+KEEP_WIDTH+1-1:0] mem_read_data_reg = {DATA_WIDTH+KEEP_WIDTH+1{1'b0}};
reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
wire [DATA_WIDTH+KEEP_WIDTH+1-1:0] mem_write_data;
reg [DATA_WIDTH+KEEP_WIDTH+1-1:0] output_data_reg = {DATA_WIDTH+KEEP_WIDTH+1{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
// full when first TWO MSBs do NOT match, but rest matches
// (gray code equivalent of first MSB different but rest same)
wire full = ((wr_ptr_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) &&
(wr_ptr_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) &&
(wr_ptr_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0]));
// empty when pointers match exactly
wire empty = rd_ptr_gray_reg == wr_ptr_gray_sync2_reg;
// overflow within packet
wire full_cur = ((wr_ptr_reg[ADDR_WIDTH] != wr_ptr_cur_reg[ADDR_WIDTH]) &&
(wr_ptr_reg[ADDR_WIDTH-1:0] == wr_ptr_cur_reg[ADDR_WIDTH-1:0]));
// control signals
reg write;
reg read;
reg store_output;
reg drop_frame_reg = 1'b0, drop_frame_next;
reg overflow_reg = 1'b0, overflow_next;
reg bad_frame_reg = 1'b0, bad_frame_next;
reg good_frame_reg = 1'b0, good_frame_next;
reg overflow_sync1_reg = 1'b0;
reg overflow_sync2_reg = 1'b0;
reg overflow_sync3_reg = 1'b0;
reg overflow_sync4_reg = 1'b0;
reg bad_frame_sync1_reg = 1'b0;
reg bad_frame_sync2_reg = 1'b0;
reg bad_frame_sync3_reg = 1'b0;
reg bad_frame_sync4_reg = 1'b0;
reg good_frame_sync1_reg = 1'b0;
reg good_frame_sync2_reg = 1'b0;
reg good_frame_sync3_reg = 1'b0;
reg good_frame_sync4_reg = 1'b0;
assign input_axis_tready = (~full | DROP_WHEN_FULL) & ~input_rst_sync3_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign mem_write_data = {input_axis_tlast, input_axis_tkeep, input_axis_tdata};
assign {output_axis_tlast, output_axis_tkeep, output_axis_tdata} = output_data_reg;
assign input_status_overflow = overflow_reg;
assign input_status_bad_frame = bad_frame_reg;
assign input_status_good_frame = good_frame_reg;
assign output_status_overflow = overflow_sync3_reg ^ overflow_sync4_reg;
assign output_status_bad_frame = bad_frame_sync3_reg ^ bad_frame_sync4_reg;
assign output_status_good_frame = good_frame_sync3_reg ^ good_frame_sync4_reg;
// reset synchronization
always @(posedge input_clk or posedge async_rst) begin
if (async_rst) begin
input_rst_sync1_reg <= 1'b1;
input_rst_sync2_reg <= 1'b1;
input_rst_sync3_reg <= 1'b1;
end else begin
input_rst_sync1_reg <= 1'b0;
input_rst_sync2_reg <= input_rst_sync1_reg | output_rst_sync1_reg;
input_rst_sync3_reg <= input_rst_sync2_reg;
end
end
always @(posedge output_clk or posedge async_rst) begin
if (async_rst) begin
output_rst_sync1_reg <= 1'b1;
output_rst_sync2_reg <= 1'b1;
output_rst_sync3_reg <= 1'b1;
end else begin
output_rst_sync1_reg <= 1'b0;
output_rst_sync2_reg <= input_rst_sync1_reg | output_rst_sync1_reg;
output_rst_sync3_reg <= output_rst_sync2_reg;
end
end
// Write logic
always @* begin
write = 1'b0;
drop_frame_next = 1'b0;
overflow_next = 1'b0;
bad_frame_next = 1'b0;
good_frame_next = 1'b0;
wr_ptr_next = wr_ptr_reg;
wr_ptr_cur_next = wr_ptr_cur_reg;
wr_ptr_gray_next = wr_ptr_gray_reg;
if (input_axis_tvalid) begin
// input data valid
if (~full | DROP_WHEN_FULL) begin
// not full, perform write
if (full | full_cur | drop_frame_reg) begin
// full, packet overflow, or currently dropping frame
// drop frame
drop_frame_next = 1'b1;
if (input_axis_tlast) begin
// end of frame, reset write pointer
wr_ptr_cur_next = wr_ptr_reg;
drop_frame_next = 1'b0;
overflow_next = 1'b1;
end
end else begin
write = 1'b1;
wr_ptr_cur_next = wr_ptr_cur_reg + 1;
if (input_axis_tlast) begin
// end of frame
if (input_axis_tuser) begin
// bad packet, reset write pointer
wr_ptr_cur_next = wr_ptr_reg;
bad_frame_next = 1'b1;
end else begin
// good packet, update write pointer
wr_ptr_next = wr_ptr_cur_reg + 1;
wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1);
good_frame_next = 1'b1;
end
end
end
end
end
end
always @(posedge input_clk) begin
if (input_rst_sync3_reg) begin
wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
end else begin
wr_ptr_reg <= wr_ptr_next;
wr_ptr_cur_reg <= wr_ptr_cur_next;
wr_ptr_gray_reg <= wr_ptr_gray_next;
drop_frame_reg <= drop_frame_next;
overflow_reg <= overflow_next;
bad_frame_reg <= bad_frame_next;
good_frame_reg <= good_frame_next;
end
wr_addr_reg <= wr_ptr_cur_next;
if (write) begin
mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
// pointer synchronization
always @(posedge input_clk) begin
if (input_rst_sync3_reg) begin
rd_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
rd_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
end else begin
rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg;
rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg;
end
end
always @(posedge output_clk) begin
if (output_rst_sync3_reg) begin
wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
end else begin
wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg;
wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg;
end
end
// status synchronization
always @(posedge input_clk) begin
if (input_rst_sync3_reg) begin
overflow_sync1_reg <= 1'b0;
bad_frame_sync1_reg <= 1'b0;
good_frame_sync1_reg <= 1'b0;
end else begin
overflow_sync1_reg <= overflow_sync1_reg ^ overflow_reg;
bad_frame_sync1_reg <= bad_frame_sync1_reg ^ bad_frame_reg;
good_frame_sync1_reg <= good_frame_sync1_reg ^ good_frame_reg;
end
end
always @(posedge output_clk) begin
if (output_rst_sync3_reg) begin
overflow_sync2_reg <= 1'b0;
overflow_sync3_reg <= 1'b0;
bad_frame_sync2_reg <= 1'b0;
bad_frame_sync3_reg <= 1'b0;
good_frame_sync2_reg <= 1'b0;
good_frame_sync3_reg <= 1'b0;
end else begin
overflow_sync2_reg <= overflow_sync1_reg;
overflow_sync3_reg <= overflow_sync2_reg;
overflow_sync4_reg <= overflow_sync3_reg;
bad_frame_sync2_reg <= bad_frame_sync1_reg;
bad_frame_sync3_reg <= bad_frame_sync2_reg;
bad_frame_sync4_reg <= bad_frame_sync3_reg;
good_frame_sync2_reg <= good_frame_sync1_reg;
good_frame_sync3_reg <= good_frame_sync2_reg;
good_frame_sync4_reg <= good_frame_sync3_reg;
end
end
// Read logic
always @* begin
read = 1'b0;
rd_ptr_next = rd_ptr_reg;
rd_ptr_gray_next = rd_ptr_gray_reg;
mem_read_data_valid_next = mem_read_data_valid_reg;
if (store_output | ~mem_read_data_valid_reg) begin
// output data not valid OR currently being transferred
if (~empty) begin
// not empty, perform read
read = 1'b1;
mem_read_data_valid_next = 1'b1;
rd_ptr_next = rd_ptr_reg + 1;
rd_ptr_gray_next = rd_ptr_next ^ (rd_ptr_next >> 1);
end else begin
// empty, invalidate
mem_read_data_valid_next = 1'b0;
end
end
end
always @(posedge output_clk) begin
if (output_rst_sync3_reg) begin
rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
rd_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
mem_read_data_valid_reg <= 1'b0;
end else begin
rd_ptr_reg <= rd_ptr_next;
rd_ptr_gray_reg <= rd_ptr_gray_next;
mem_read_data_valid_reg <= mem_read_data_valid_next;
end
rd_addr_reg <= rd_ptr_next;
if (read) begin
mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]];
end
end
// Output register
always @* begin
store_output = 1'b0;
output_axis_tvalid_next = output_axis_tvalid_reg;
if (output_axis_tready | ~output_axis_tvalid) begin
store_output = 1'b1;
output_axis_tvalid_next = mem_read_data_valid_reg;
end
end
always @(posedge output_clk) begin
if (output_rst_sync3_reg) begin
output_axis_tvalid_reg <= 1'b0;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
end
if (store_output) begin
output_data_reg <= mem_read_data_reg;
end
end
endmodule

2
lib/axis/rtl/axis_cobs_decode.v
View File

@ -276,7 +276,7 @@ always @* begin
store_axis_int_to_output = 1'b0; store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0; store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0; store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
// input is ready // input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin if (output_axis_tready | ~output_axis_tvalid_reg) begin

35
lib/axis/rtl/axis_cobs_encode.v
View File

@ -102,22 +102,34 @@ reg code_fifo_out_tready;
axis_fifo #( axis_fifo #(
.ADDR_WIDTH(8), .ADDR_WIDTH(8),
.DATA_WIDTH(8) .DATA_WIDTH(8),
.KEEP_ENABLE(0),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
) )
code_fifo_inst ( code_fifo_inst (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
// AXI input // AXI input
.input_axis_tdata(code_fifo_in_tdata), .input_axis_tdata(code_fifo_in_tdata),
.input_axis_tkeep(0),
.input_axis_tvalid(code_fifo_in_tvalid), .input_axis_tvalid(code_fifo_in_tvalid),
.input_axis_tready(code_fifo_in_tready), .input_axis_tready(code_fifo_in_tready),
.input_axis_tlast(code_fifo_in_tlast), .input_axis_tlast(code_fifo_in_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(code_fifo_in_tuser), .input_axis_tuser(code_fifo_in_tuser),
// AXI output // AXI output
.output_axis_tdata(code_fifo_out_tdata), .output_axis_tdata(code_fifo_out_tdata),
.output_axis_tkeep(),
.output_axis_tvalid(code_fifo_out_tvalid), .output_axis_tvalid(code_fifo_out_tvalid),
.output_axis_tready(code_fifo_out_tready), .output_axis_tready(code_fifo_out_tready),
.output_axis_tlast(code_fifo_out_tlast), .output_axis_tlast(code_fifo_out_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(code_fifo_out_tuser) .output_axis_tuser(code_fifo_out_tuser)
); );
@ -133,22 +145,33 @@ reg data_fifo_out_tready;
axis_fifo #( axis_fifo #(
.ADDR_WIDTH(8), .ADDR_WIDTH(8),
.DATA_WIDTH(8) .DATA_WIDTH(8),
.KEEP_ENABLE(0),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0)
) )
data_fifo_inst ( data_fifo_inst (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
// AXI input // AXI input
.input_axis_tdata(data_fifo_in_tdata), .input_axis_tdata(data_fifo_in_tdata),
.input_axis_tkeep(0),
.input_axis_tvalid(data_fifo_in_tvalid), .input_axis_tvalid(data_fifo_in_tvalid),
.input_axis_tready(data_fifo_in_tready), .input_axis_tready(data_fifo_in_tready),
.input_axis_tlast(data_fifo_in_tlast), .input_axis_tlast(data_fifo_in_tlast),
.input_axis_tuser(1'b0), .input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(0),
// AXI output // AXI output
.output_axis_tdata(data_fifo_out_tdata), .output_axis_tdata(data_fifo_out_tdata),
.output_axis_tkeep(),
.output_axis_tvalid(data_fifo_out_tvalid), .output_axis_tvalid(data_fifo_out_tvalid),
.output_axis_tready(data_fifo_out_tready), .output_axis_tready(data_fifo_out_tready),
.output_axis_tlast(data_fifo_out_tlast), .output_axis_tlast(data_fifo_out_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser() .output_axis_tuser()
); );
@ -178,7 +201,7 @@ always @* begin
if (input_axis_tready & input_axis_tvalid) begin if (input_axis_tready & input_axis_tvalid) begin
// valid input data // valid input data
if (input_axis_tdata == 8'd0 || (input_axis_tlast & input_axis_tuser)) begin if (input_axis_tdata == 8'd0 || (input_axis_tlast & input_axis_tuser)) begin
// got a zero or propagated error, so store a zero code // got a zero or propagated error, so store a zero code
code_fifo_in_tdata = 8'd1; code_fifo_in_tdata = 8'd1;
@ -224,7 +247,7 @@ always @* begin
if (input_axis_tready & input_axis_tvalid) begin if (input_axis_tready & input_axis_tvalid) begin
// valid input data // valid input data
if (input_axis_tdata == 8'd0 || (input_axis_tlast & input_axis_tuser)) begin if (input_axis_tdata == 8'd0 || (input_axis_tlast & input_axis_tuser)) begin
// got a zero or propagated error, so store the code // got a zero or propagated error, so store the code
code_fifo_in_tdata = input_count_reg; code_fifo_in_tdata = input_count_reg;
@ -421,7 +444,7 @@ always @* begin
store_axis_int_to_output = 1'b0; store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0; store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0; store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
// input is ready // input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin if (output_axis_tready | ~output_axis_tvalid_reg) begin

63
lib/axis/rtl/axis_crosspoint.py
View File

@ -78,29 +78,44 @@ THE SOFTWARE.
*/ */
module {{name}} # module {{name}} #
( (
parameter DATA_WIDTH = 8 parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter LAST_ENABLE = 1,
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
) )
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
/* /*
* AXI Stream inputs * AXI Stream inputs
*/ */
{%- for p in range(m) %} {%- for p in range(m) %}
input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata, input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep,
input wire input_{{p}}_axis_tvalid, input wire input_{{p}}_axis_tvalid,
input wire input_{{p}}_axis_tlast, input wire input_{{p}}_axis_tlast,
input wire input_{{p}}_axis_tuser, input wire [ID_WIDTH-1:0] input_{{p}}_axis_tid,
input wire [DEST_WIDTH-1:0] input_{{p}}_axis_tdest,
input wire [USER_WIDTH-1:0] input_{{p}}_axis_tuser,
{% endfor %} {% endfor %}
/* /*
* AXI Stream outputs * AXI Stream outputs
*/ */
{%- for p in range(n) %} {%- for p in range(n) %}
output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata, output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep,
output wire output_{{p}}_axis_tvalid, output wire output_{{p}}_axis_tvalid,
output wire output_{{p}}_axis_tlast, output wire output_{{p}}_axis_tlast,
output wire output_{{p}}_axis_tuser, output wire [ID_WIDTH-1:0] output_{{p}}_axis_tid,
output wire [DEST_WIDTH-1:0] output_{{p}}_axis_tdest,
output wire [USER_WIDTH-1:0] output_{{p}}_axis_tuser,
{% endfor %} {% endfor %}
/* /*
* Control * Control
@ -110,29 +125,37 @@ module {{name}} #
{%- endfor %} {%- endfor %}
); );
{% for p in range(m) %} {% for p in range(m) %}
reg [DATA_WIDTH-1:0] input_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] input_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg input_{{p}}_axis_tvalid_reg = 1'b0; reg input_{{p}}_axis_tvalid_reg = 1'b0;
reg input_{{p}}_axis_tlast_reg = 1'b0; reg input_{{p}}_axis_tlast_reg = 1'b0;
reg input_{{p}}_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] input_{{p}}_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] input_{{p}}_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] input_{{p}}_axis_tuser_reg = {USER_WIDTH{1'b0}};
{% endfor %} {% endfor %}
{%- for p in range(n) %} {%- for p in range(n) %}
reg [DATA_WIDTH-1:0] output_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] output_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_{{p}}_axis_tvalid_reg = 1'b0; reg output_{{p}}_axis_tvalid_reg = 1'b0;
reg output_{{p}}_axis_tlast_reg = 1'b0; reg output_{{p}}_axis_tlast_reg = 1'b0;
reg output_{{p}}_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] output_{{p}}_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] output_{{p}}_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_{{p}}_axis_tuser_reg = {USER_WIDTH{1'b0}};
{% endfor %} {% endfor %}
{%- for p in range(n) %} {%- for p in range(n) %}
reg [{{w-1}}:0] output_{{p}}_select_reg = {{w}}'d0; reg [{{w-1}}:0] output_{{p}}_select_reg = {{w}}'d0;
{%- endfor %} {%- endfor %}
{% for p in range(n) %} {% for p in range(n) %}
assign output_{{p}}_axis_tdata = output_{{p}}_axis_tdata_reg; assign output_{{p}}_axis_tdata = output_{{p}}_axis_tdata_reg;
assign output_{{p}}_axis_tkeep = KEEP_ENABLE ? output_{{p}}_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg; assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg;
assign output_{{p}}_axis_tlast = output_{{p}}_axis_tlast_reg; assign output_{{p}}_axis_tlast = LAST_ENABLE ? output_{{p}}_axis_tlast_reg : 1'b1;
assign output_{{p}}_axis_tuser = output_{{p}}_axis_tuser_reg; assign output_{{p}}_axis_tid = ID_ENABLE ? output_{{p}}_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_{{p}}_axis_tdest = DEST_ENABLE ? output_{{p}}_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign output_{{p}}_axis_tuser = USER_ENABLE ? output_{{p}}_axis_tuser_reg : {USER_WIDTH{1'b0}};
{% endfor %} {% endfor %}
always @(posedge clk) begin always @(posedge clk) begin
if (rst) begin if (rst) begin
{%- for p in range(n) %} {%- for p in range(n) %}
@ -163,7 +186,10 @@ always @(posedge clk) begin
{%- for p in range(m) %} {%- for p in range(m) %}
input_{{p}}_axis_tdata_reg <= input_{{p}}_axis_tdata; input_{{p}}_axis_tdata_reg <= input_{{p}}_axis_tdata;
input_{{p}}_axis_tkeep_reg <= input_{{p}}_axis_tkeep;
input_{{p}}_axis_tlast_reg <= input_{{p}}_axis_tlast; input_{{p}}_axis_tlast_reg <= input_{{p}}_axis_tlast;
input_{{p}}_axis_tid_reg <= input_{{p}}_axis_tid;
input_{{p}}_axis_tdest_reg <= input_{{p}}_axis_tdest;
input_{{p}}_axis_tuser_reg <= input_{{p}}_axis_tuser; input_{{p}}_axis_tuser_reg <= input_{{p}}_axis_tuser;
{%- endfor %} {%- endfor %}
{%- for p in range(n) %} {%- for p in range(n) %}
@ -172,7 +198,10 @@ always @(posedge clk) begin
{%- for q in range(m) %} {%- for q in range(m) %}
{{w}}'d{{q}}: begin {{w}}'d{{q}}: begin
output_{{p}}_axis_tdata_reg <= input_{{q}}_axis_tdata_reg; output_{{p}}_axis_tdata_reg <= input_{{q}}_axis_tdata_reg;
output_{{p}}_axis_tkeep_reg <= input_{{q}}_axis_tkeep_reg;
output_{{p}}_axis_tlast_reg <= input_{{q}}_axis_tlast_reg; output_{{p}}_axis_tlast_reg <= input_{{q}}_axis_tlast_reg;
output_{{p}}_axis_tid_reg <= input_{{q}}_axis_tid_reg;
output_{{p}}_axis_tdest_reg <= input_{{q}}_axis_tdest_reg;
output_{{p}}_axis_tuser_reg <= input_{{q}}_axis_tuser_reg; output_{{p}}_axis_tuser_reg <= input_{{q}}_axis_tuser_reg;
end end
{%- endfor %} {%- endfor %}
@ -183,14 +212,14 @@ end
endmodule endmodule
""") """)
output_file.write(t.render( output_file.write(t.render(
m=m, m=m,
n=n, n=n,
w=select_width, w=select_width,
name=name name=name
)) ))
print("Done") print("Done")
if __name__ == "__main__": if __name__ == "__main__":

224
lib/axis/rtl/axis_crosspoint_4x4.v
View File

@ -31,57 +31,90 @@ THE SOFTWARE.
*/ */
module axis_crosspoint_4x4 # module axis_crosspoint_4x4 #
( (
parameter DATA_WIDTH = 8 parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter LAST_ENABLE = 1,
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
) )
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
/* /*
* AXI Stream inputs * AXI Stream inputs
*/ */
input wire [DATA_WIDTH-1:0] input_0_axis_tdata, input wire [DATA_WIDTH-1:0] input_0_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_0_axis_tkeep,
input wire input_0_axis_tvalid, input wire input_0_axis_tvalid,
input wire input_0_axis_tlast, input wire input_0_axis_tlast,
input wire input_0_axis_tuser, input wire [ID_WIDTH-1:0] input_0_axis_tid,
input wire [DEST_WIDTH-1:0] input_0_axis_tdest,
input wire [USER_WIDTH-1:0] input_0_axis_tuser,
input wire [DATA_WIDTH-1:0] input_1_axis_tdata, input wire [DATA_WIDTH-1:0] input_1_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_1_axis_tkeep,
input wire input_1_axis_tvalid, input wire input_1_axis_tvalid,
input wire input_1_axis_tlast, input wire input_1_axis_tlast,
input wire input_1_axis_tuser, input wire [ID_WIDTH-1:0] input_1_axis_tid,
input wire [DEST_WIDTH-1:0] input_1_axis_tdest,
input wire [USER_WIDTH-1:0] input_1_axis_tuser,
input wire [DATA_WIDTH-1:0] input_2_axis_tdata, input wire [DATA_WIDTH-1:0] input_2_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_2_axis_tkeep,
input wire input_2_axis_tvalid, input wire input_2_axis_tvalid,
input wire input_2_axis_tlast, input wire input_2_axis_tlast,
input wire input_2_axis_tuser, input wire [ID_WIDTH-1:0] input_2_axis_tid,
input wire [DEST_WIDTH-1:0] input_2_axis_tdest,
input wire [USER_WIDTH-1:0] input_2_axis_tuser,
input wire [DATA_WIDTH-1:0] input_3_axis_tdata, input wire [DATA_WIDTH-1:0] input_3_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_3_axis_tkeep,
input wire input_3_axis_tvalid, input wire input_3_axis_tvalid,
input wire input_3_axis_tlast, input wire input_3_axis_tlast,
input wire input_3_axis_tuser, input wire [ID_WIDTH-1:0] input_3_axis_tid,
input wire [DEST_WIDTH-1:0] input_3_axis_tdest,
input wire [USER_WIDTH-1:0] input_3_axis_tuser,
/* /*
* AXI Stream outputs * AXI Stream outputs
*/ */
output wire [DATA_WIDTH-1:0] output_0_axis_tdata, output wire [DATA_WIDTH-1:0] output_0_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_0_axis_tkeep,
output wire output_0_axis_tvalid, output wire output_0_axis_tvalid,
output wire output_0_axis_tlast, output wire output_0_axis_tlast,
output wire output_0_axis_tuser, output wire [ID_WIDTH-1:0] output_0_axis_tid,
output wire [DEST_WIDTH-1:0] output_0_axis_tdest,
output wire [USER_WIDTH-1:0] output_0_axis_tuser,
output wire [DATA_WIDTH-1:0] output_1_axis_tdata, output wire [DATA_WIDTH-1:0] output_1_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_1_axis_tkeep,
output wire output_1_axis_tvalid, output wire output_1_axis_tvalid,
output wire output_1_axis_tlast, output wire output_1_axis_tlast,
output wire output_1_axis_tuser, output wire [ID_WIDTH-1:0] output_1_axis_tid,
output wire [DEST_WIDTH-1:0] output_1_axis_tdest,
output wire [USER_WIDTH-1:0] output_1_axis_tuser,
output wire [DATA_WIDTH-1:0] output_2_axis_tdata, output wire [DATA_WIDTH-1:0] output_2_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_2_axis_tkeep,
output wire output_2_axis_tvalid, output wire output_2_axis_tvalid,
output wire output_2_axis_tlast, output wire output_2_axis_tlast,
output wire output_2_axis_tuser, output wire [ID_WIDTH-1:0] output_2_axis_tid,
output wire [DEST_WIDTH-1:0] output_2_axis_tdest,
output wire [USER_WIDTH-1:0] output_2_axis_tuser,
output wire [DATA_WIDTH-1:0] output_3_axis_tdata, output wire [DATA_WIDTH-1:0] output_3_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_3_axis_tkeep,
output wire output_3_axis_tvalid, output wire output_3_axis_tvalid,
output wire output_3_axis_tlast, output wire output_3_axis_tlast,
output wire output_3_axis_tuser, output wire [ID_WIDTH-1:0] output_3_axis_tid,
output wire [DEST_WIDTH-1:0] output_3_axis_tdest,
output wire [USER_WIDTH-1:0] output_3_axis_tuser,
/* /*
* Control * Control
@ -92,71 +125,106 @@ module axis_crosspoint_4x4 #
input wire [1:0] output_3_select input wire [1:0] output_3_select
); );
reg [DATA_WIDTH-1:0] input_0_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] input_0_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] input_0_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg input_0_axis_tvalid_reg = 1'b0; reg input_0_axis_tvalid_reg = 1'b0;
reg input_0_axis_tlast_reg = 1'b0; reg input_0_axis_tlast_reg = 1'b0;
reg input_0_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] input_0_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] input_0_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] input_0_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] input_1_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] input_1_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] input_1_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg input_1_axis_tvalid_reg = 1'b0; reg input_1_axis_tvalid_reg = 1'b0;
reg input_1_axis_tlast_reg = 1'b0; reg input_1_axis_tlast_reg = 1'b0;
reg input_1_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] input_1_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] input_1_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] input_1_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] input_2_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] input_2_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] input_2_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg input_2_axis_tvalid_reg = 1'b0; reg input_2_axis_tvalid_reg = 1'b0;
reg input_2_axis_tlast_reg = 1'b0; reg input_2_axis_tlast_reg = 1'b0;
reg input_2_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] input_2_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] input_2_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] input_2_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] input_3_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] input_3_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] input_3_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg input_3_axis_tvalid_reg = 1'b0; reg input_3_axis_tvalid_reg = 1'b0;
reg input_3_axis_tlast_reg = 1'b0; reg input_3_axis_tlast_reg = 1'b0;
reg input_3_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] input_3_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] input_3_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] input_3_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] output_0_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] output_0_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_0_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_0_axis_tvalid_reg = 1'b0; reg output_0_axis_tvalid_reg = 1'b0;
reg output_0_axis_tlast_reg = 1'b0; reg output_0_axis_tlast_reg = 1'b0;
reg output_0_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] output_0_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] output_0_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_0_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] output_1_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] output_1_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_1_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_1_axis_tvalid_reg = 1'b0; reg output_1_axis_tvalid_reg = 1'b0;
reg output_1_axis_tlast_reg = 1'b0; reg output_1_axis_tlast_reg = 1'b0;
reg output_1_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] output_1_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] output_1_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_1_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] output_2_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] output_2_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_2_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_2_axis_tvalid_reg = 1'b0; reg output_2_axis_tvalid_reg = 1'b0;
reg output_2_axis_tlast_reg = 1'b0; reg output_2_axis_tlast_reg = 1'b0;
reg output_2_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] output_2_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] output_2_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_2_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] output_3_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] output_3_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_3_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_3_axis_tvalid_reg = 1'b0; reg output_3_axis_tvalid_reg = 1'b0;
reg output_3_axis_tlast_reg = 1'b0; reg output_3_axis_tlast_reg = 1'b0;
reg output_3_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] output_3_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] output_3_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_3_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [1:0] output_0_select_reg = 2'd0; reg [1:0] output_0_select_reg = 2'd0;
reg [1:0] output_1_select_reg = 2'd0; reg [1:0] output_1_select_reg = 2'd0;
reg [1:0] output_2_select_reg = 2'd0; reg [1:0] output_2_select_reg = 2'd0;
reg [1:0] output_3_select_reg = 2'd0; reg [1:0] output_3_select_reg = 2'd0;
assign output_0_axis_tdata = output_0_axis_tdata_reg; assign output_0_axis_tdata = output_0_axis_tdata_reg;
assign output_0_axis_tkeep = KEEP_ENABLE ? output_0_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_0_axis_tvalid = output_0_axis_tvalid_reg; assign output_0_axis_tvalid = output_0_axis_tvalid_reg;
assign output_0_axis_tlast = output_0_axis_tlast_reg; assign output_0_axis_tlast = LAST_ENABLE ? output_0_axis_tlast_reg : 1'b1;
assign output_0_axis_tuser = output_0_axis_tuser_reg; assign output_0_axis_tid = ID_ENABLE ? output_0_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_0_axis_tdest = DEST_ENABLE ? output_0_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign output_0_axis_tuser = USER_ENABLE ? output_0_axis_tuser_reg : {USER_WIDTH{1'b0}};
assign output_1_axis_tdata = output_1_axis_tdata_reg; assign output_1_axis_tdata = output_1_axis_tdata_reg;
assign output_1_axis_tkeep = KEEP_ENABLE ? output_1_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_1_axis_tvalid = output_1_axis_tvalid_reg; assign output_1_axis_tvalid = output_1_axis_tvalid_reg;
assign output_1_axis_tlast = output_1_axis_tlast_reg; assign output_1_axis_tlast = LAST_ENABLE ? output_1_axis_tlast_reg : 1'b1;
assign output_1_axis_tuser = output_1_axis_tuser_reg; assign output_1_axis_tid = ID_ENABLE ? output_1_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_1_axis_tdest = DEST_ENABLE ? output_1_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign output_1_axis_tuser = USER_ENABLE ? output_1_axis_tuser_reg : {USER_WIDTH{1'b0}};
assign output_2_axis_tdata = output_2_axis_tdata_reg; assign output_2_axis_tdata = output_2_axis_tdata_reg;
assign output_2_axis_tkeep = KEEP_ENABLE ? output_2_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_2_axis_tvalid = output_2_axis_tvalid_reg; assign output_2_axis_tvalid = output_2_axis_tvalid_reg;
assign output_2_axis_tlast = output_2_axis_tlast_reg; assign output_2_axis_tlast = LAST_ENABLE ? output_2_axis_tlast_reg : 1'b1;
assign output_2_axis_tuser = output_2_axis_tuser_reg; assign output_2_axis_tid = ID_ENABLE ? output_2_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_2_axis_tdest = DEST_ENABLE ? output_2_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign output_2_axis_tuser = USER_ENABLE ? output_2_axis_tuser_reg : {USER_WIDTH{1'b0}};
assign output_3_axis_tdata = output_3_axis_tdata_reg; assign output_3_axis_tdata = output_3_axis_tdata_reg;
assign output_3_axis_tkeep = KEEP_ENABLE ? output_3_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_3_axis_tvalid = output_3_axis_tvalid_reg; assign output_3_axis_tvalid = output_3_axis_tvalid_reg;
assign output_3_axis_tlast = output_3_axis_tlast_reg; assign output_3_axis_tlast = LAST_ENABLE ? output_3_axis_tlast_reg : 1'b1;
assign output_3_axis_tuser = output_3_axis_tuser_reg; assign output_3_axis_tid = ID_ENABLE ? output_3_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_3_axis_tdest = DEST_ENABLE ? output_3_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign output_3_axis_tuser = USER_ENABLE ? output_3_axis_tuser_reg : {USER_WIDTH{1'b0}};
always @(posedge clk) begin always @(posedge clk) begin
if (rst) begin if (rst) begin
@ -215,40 +283,64 @@ always @(posedge clk) begin
end end
input_0_axis_tdata_reg <= input_0_axis_tdata; input_0_axis_tdata_reg <= input_0_axis_tdata;
input_0_axis_tkeep_reg <= input_0_axis_tkeep;
input_0_axis_tlast_reg <= input_0_axis_tlast; input_0_axis_tlast_reg <= input_0_axis_tlast;
input_0_axis_tid_reg <= input_0_axis_tid;
input_0_axis_tdest_reg <= input_0_axis_tdest;
input_0_axis_tuser_reg <= input_0_axis_tuser; input_0_axis_tuser_reg <= input_0_axis_tuser;
input_1_axis_tdata_reg <= input_1_axis_tdata; input_1_axis_tdata_reg <= input_1_axis_tdata;
input_1_axis_tkeep_reg <= input_1_axis_tkeep;
input_1_axis_tlast_reg <= input_1_axis_tlast; input_1_axis_tlast_reg <= input_1_axis_tlast;
input_1_axis_tid_reg <= input_1_axis_tid;
input_1_axis_tdest_reg <= input_1_axis_tdest;
input_1_axis_tuser_reg <= input_1_axis_tuser; input_1_axis_tuser_reg <= input_1_axis_tuser;
input_2_axis_tdata_reg <= input_2_axis_tdata; input_2_axis_tdata_reg <= input_2_axis_tdata;
input_2_axis_tkeep_reg <= input_2_axis_tkeep;
input_2_axis_tlast_reg <= input_2_axis_tlast; input_2_axis_tlast_reg <= input_2_axis_tlast;
input_2_axis_tid_reg <= input_2_axis_tid;
input_2_axis_tdest_reg <= input_2_axis_tdest;
input_2_axis_tuser_reg <= input_2_axis_tuser; input_2_axis_tuser_reg <= input_2_axis_tuser;
input_3_axis_tdata_reg <= input_3_axis_tdata; input_3_axis_tdata_reg <= input_3_axis_tdata;
input_3_axis_tkeep_reg <= input_3_axis_tkeep;
input_3_axis_tlast_reg <= input_3_axis_tlast; input_3_axis_tlast_reg <= input_3_axis_tlast;
input_3_axis_tid_reg <= input_3_axis_tid;
input_3_axis_tdest_reg <= input_3_axis_tdest;
input_3_axis_tuser_reg <= input_3_axis_tuser; input_3_axis_tuser_reg <= input_3_axis_tuser;
case (output_0_select_reg) case (output_0_select_reg)
2'd0: begin 2'd0: begin
output_0_axis_tdata_reg <= input_0_axis_tdata_reg; output_0_axis_tdata_reg <= input_0_axis_tdata_reg;
output_0_axis_tkeep_reg <= input_0_axis_tkeep_reg;
output_0_axis_tlast_reg <= input_0_axis_tlast_reg; output_0_axis_tlast_reg <= input_0_axis_tlast_reg;
output_0_axis_tid_reg <= input_0_axis_tid_reg;
output_0_axis_tdest_reg <= input_0_axis_tdest_reg;
output_0_axis_tuser_reg <= input_0_axis_tuser_reg; output_0_axis_tuser_reg <= input_0_axis_tuser_reg;
end end
2'd1: begin 2'd1: begin
output_0_axis_tdata_reg <= input_1_axis_tdata_reg; output_0_axis_tdata_reg <= input_1_axis_tdata_reg;
output_0_axis_tkeep_reg <= input_1_axis_tkeep_reg;
output_0_axis_tlast_reg <= input_1_axis_tlast_reg; output_0_axis_tlast_reg <= input_1_axis_tlast_reg;
output_0_axis_tid_reg <= input_1_axis_tid_reg;
output_0_axis_tdest_reg <= input_1_axis_tdest_reg;
output_0_axis_tuser_reg <= input_1_axis_tuser_reg; output_0_axis_tuser_reg <= input_1_axis_tuser_reg;
end end
2'd2: begin 2'd2: begin
output_0_axis_tdata_reg <= input_2_axis_tdata_reg; output_0_axis_tdata_reg <= input_2_axis_tdata_reg;
output_0_axis_tkeep_reg <= input_2_axis_tkeep_reg;
output_0_axis_tlast_reg <= input_2_axis_tlast_reg; output_0_axis_tlast_reg <= input_2_axis_tlast_reg;
output_0_axis_tid_reg <= input_2_axis_tid_reg;
output_0_axis_tdest_reg <= input_2_axis_tdest_reg;
output_0_axis_tuser_reg <= input_2_axis_tuser_reg; output_0_axis_tuser_reg <= input_2_axis_tuser_reg;
end end
2'd3: begin 2'd3: begin
output_0_axis_tdata_reg <= input_3_axis_tdata_reg; output_0_axis_tdata_reg <= input_3_axis_tdata_reg;
output_0_axis_tkeep_reg <= input_3_axis_tkeep_reg;
output_0_axis_tlast_reg <= input_3_axis_tlast_reg; output_0_axis_tlast_reg <= input_3_axis_tlast_reg;
output_0_axis_tid_reg <= input_3_axis_tid_reg;
output_0_axis_tdest_reg <= input_3_axis_tdest_reg;
output_0_axis_tuser_reg <= input_3_axis_tuser_reg; output_0_axis_tuser_reg <= input_3_axis_tuser_reg;
end end
endcase endcase
@ -256,22 +348,34 @@ always @(posedge clk) begin
case (output_1_select_reg) case (output_1_select_reg)
2'd0: begin 2'd0: begin
output_1_axis_tdata_reg <= input_0_axis_tdata_reg; output_1_axis_tdata_reg <= input_0_axis_tdata_reg;
output_1_axis_tkeep_reg <= input_0_axis_tkeep_reg;
output_1_axis_tlast_reg <= input_0_axis_tlast_reg; output_1_axis_tlast_reg <= input_0_axis_tlast_reg;
output_1_axis_tid_reg <= input_0_axis_tid_reg;
output_1_axis_tdest_reg <= input_0_axis_tdest_reg;
output_1_axis_tuser_reg <= input_0_axis_tuser_reg; output_1_axis_tuser_reg <= input_0_axis_tuser_reg;
end end
2'd1: begin 2'd1: begin
output_1_axis_tdata_reg <= input_1_axis_tdata_reg; output_1_axis_tdata_reg <= input_1_axis_tdata_reg;
output_1_axis_tkeep_reg <= input_1_axis_tkeep_reg;
output_1_axis_tlast_reg <= input_1_axis_tlast_reg; output_1_axis_tlast_reg <= input_1_axis_tlast_reg;
output_1_axis_tid_reg <= input_1_axis_tid_reg;
output_1_axis_tdest_reg <= input_1_axis_tdest_reg;
output_1_axis_tuser_reg <= input_1_axis_tuser_reg; output_1_axis_tuser_reg <= input_1_axis_tuser_reg;
end end
2'd2: begin 2'd2: begin
output_1_axis_tdata_reg <= input_2_axis_tdata_reg; output_1_axis_tdata_reg <= input_2_axis_tdata_reg;
output_1_axis_tkeep_reg <= input_2_axis_tkeep_reg;
output_1_axis_tlast_reg <= input_2_axis_tlast_reg; output_1_axis_tlast_reg <= input_2_axis_tlast_reg;
output_1_axis_tid_reg <= input_2_axis_tid_reg;
output_1_axis_tdest_reg <= input_2_axis_tdest_reg;
output_1_axis_tuser_reg <= input_2_axis_tuser_reg; output_1_axis_tuser_reg <= input_2_axis_tuser_reg;
end end
2'd3: begin 2'd3: begin
output_1_axis_tdata_reg <= input_3_axis_tdata_reg; output_1_axis_tdata_reg <= input_3_axis_tdata_reg;
output_1_axis_tkeep_reg <= input_3_axis_tkeep_reg;
output_1_axis_tlast_reg <= input_3_axis_tlast_reg; output_1_axis_tlast_reg <= input_3_axis_tlast_reg;
output_1_axis_tid_reg <= input_3_axis_tid_reg;
output_1_axis_tdest_reg <= input_3_axis_tdest_reg;
output_1_axis_tuser_reg <= input_3_axis_tuser_reg; output_1_axis_tuser_reg <= input_3_axis_tuser_reg;
end end
endcase endcase
@ -279,22 +383,34 @@ always @(posedge clk) begin
case (output_2_select_reg) case (output_2_select_reg)
2'd0: begin 2'd0: begin
output_2_axis_tdata_reg <= input_0_axis_tdata_reg; output_2_axis_tdata_reg <= input_0_axis_tdata_reg;
output_2_axis_tkeep_reg <= input_0_axis_tkeep_reg;
output_2_axis_tlast_reg <= input_0_axis_tlast_reg; output_2_axis_tlast_reg <= input_0_axis_tlast_reg;
output_2_axis_tid_reg <= input_0_axis_tid_reg;
output_2_axis_tdest_reg <= input_0_axis_tdest_reg;
output_2_axis_tuser_reg <= input_0_axis_tuser_reg; output_2_axis_tuser_reg <= input_0_axis_tuser_reg;
end end
2'd1: begin 2'd1: begin
output_2_axis_tdata_reg <= input_1_axis_tdata_reg; output_2_axis_tdata_reg <= input_1_axis_tdata_reg;
output_2_axis_tkeep_reg <= input_1_axis_tkeep_reg;
output_2_axis_tlast_reg <= input_1_axis_tlast_reg; output_2_axis_tlast_reg <= input_1_axis_tlast_reg;
output_2_axis_tid_reg <= input_1_axis_tid_reg;
output_2_axis_tdest_reg <= input_1_axis_tdest_reg;
output_2_axis_tuser_reg <= input_1_axis_tuser_reg; output_2_axis_tuser_reg <= input_1_axis_tuser_reg;
end end
2'd2: begin 2'd2: begin
output_2_axis_tdata_reg <= input_2_axis_tdata_reg; output_2_axis_tdata_reg <= input_2_axis_tdata_reg;
output_2_axis_tkeep_reg <= input_2_axis_tkeep_reg;
output_2_axis_tlast_reg <= input_2_axis_tlast_reg; output_2_axis_tlast_reg <= input_2_axis_tlast_reg;
output_2_axis_tid_reg <= input_2_axis_tid_reg;
output_2_axis_tdest_reg <= input_2_axis_tdest_reg;
output_2_axis_tuser_reg <= input_2_axis_tuser_reg; output_2_axis_tuser_reg <= input_2_axis_tuser_reg;
end end
2'd3: begin 2'd3: begin
output_2_axis_tdata_reg <= input_3_axis_tdata_reg; output_2_axis_tdata_reg <= input_3_axis_tdata_reg;
output_2_axis_tkeep_reg <= input_3_axis_tkeep_reg;
output_2_axis_tlast_reg <= input_3_axis_tlast_reg; output_2_axis_tlast_reg <= input_3_axis_tlast_reg;
output_2_axis_tid_reg <= input_3_axis_tid_reg;
output_2_axis_tdest_reg <= input_3_axis_tdest_reg;
output_2_axis_tuser_reg <= input_3_axis_tuser_reg; output_2_axis_tuser_reg <= input_3_axis_tuser_reg;
end end
endcase endcase
@ -302,22 +418,34 @@ always @(posedge clk) begin
case (output_3_select_reg) case (output_3_select_reg)
2'd0: begin 2'd0: begin
output_3_axis_tdata_reg <= input_0_axis_tdata_reg; output_3_axis_tdata_reg <= input_0_axis_tdata_reg;
output_3_axis_tkeep_reg <= input_0_axis_tkeep_reg;
output_3_axis_tlast_reg <= input_0_axis_tlast_reg; output_3_axis_tlast_reg <= input_0_axis_tlast_reg;
output_3_axis_tid_reg <= input_0_axis_tid_reg;
output_3_axis_tdest_reg <= input_0_axis_tdest_reg;
output_3_axis_tuser_reg <= input_0_axis_tuser_reg; output_3_axis_tuser_reg <= input_0_axis_tuser_reg;
end end
2'd1: begin 2'd1: begin
output_3_axis_tdata_reg <= input_1_axis_tdata_reg; output_3_axis_tdata_reg <= input_1_axis_tdata_reg;
output_3_axis_tkeep_reg <= input_1_axis_tkeep_reg;
output_3_axis_tlast_reg <= input_1_axis_tlast_reg; output_3_axis_tlast_reg <= input_1_axis_tlast_reg;
output_3_axis_tid_reg <= input_1_axis_tid_reg;
output_3_axis_tdest_reg <= input_1_axis_tdest_reg;
output_3_axis_tuser_reg <= input_1_axis_tuser_reg; output_3_axis_tuser_reg <= input_1_axis_tuser_reg;
end end
2'd2: begin 2'd2: begin
output_3_axis_tdata_reg <= input_2_axis_tdata_reg; output_3_axis_tdata_reg <= input_2_axis_tdata_reg;
output_3_axis_tkeep_reg <= input_2_axis_tkeep_reg;
output_3_axis_tlast_reg <= input_2_axis_tlast_reg; output_3_axis_tlast_reg <= input_2_axis_tlast_reg;
output_3_axis_tid_reg <= input_2_axis_tid_reg;
output_3_axis_tdest_reg <= input_2_axis_tdest_reg;
output_3_axis_tuser_reg <= input_2_axis_tuser_reg; output_3_axis_tuser_reg <= input_2_axis_tuser_reg;
end end
2'd3: begin 2'd3: begin
output_3_axis_tdata_reg <= input_3_axis_tdata_reg; output_3_axis_tdata_reg <= input_3_axis_tdata_reg;
output_3_axis_tkeep_reg <= input_3_axis_tkeep_reg;
output_3_axis_tlast_reg <= input_3_axis_tlast_reg; output_3_axis_tlast_reg <= input_3_axis_tlast_reg;
output_3_axis_tid_reg <= input_3_axis_tid_reg;
output_3_axis_tdest_reg <= input_3_axis_tdest_reg;
output_3_axis_tuser_reg <= input_3_axis_tuser_reg; output_3_axis_tuser_reg <= input_3_axis_tuser_reg;
end end
endcase endcase

206
lib/axis/rtl/axis_crosspoint_64.py
View File

@ -1,206 +0,0 @@
#!/usr/bin/env python
"""
Generates an AXI Stream crosspoint switch with the specified number of ports
"""
from __future__ import print_function
import argparse
import math
from jinja2 import Template
def main():
parser = argparse.ArgumentParser(description=__doc__.strip())
parser.add_argument('-p', '--ports', type=int, default=[4], nargs='+', help="number of ports")
parser.add_argument('-n', '--name', type=str, help="module name")
parser.add_argument('-o', '--output', type=str, help="output file name")
args = parser.parse_args()
try:
generate(**args.__dict__)
except IOError as ex:
print(ex)
exit(1)
def generate(ports=4, name=None, output=None):
if type(ports) is int:
m = n = ports
elif len(ports) == 1:
m = n = ports[0]
else:
m, n = ports
if name is None:
name = "axis_crosspoint_64_{0}x{1}".format(m, n)
if output is None:
output = name + ".v"
print("Opening file '{0}'...".format(output))
output_file = open(output, 'w')
print("Generating {0}x{1} port AXI Stream crosspoint {2}...".format(m, n, name))
select_width = int(math.ceil(math.log(m, 2)))
t = Template(u"""/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream {{m}}x{{n}} crosspoint (64 bit datapath)
*/
module {{name}} #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI Stream inputs
*/
{%- for p in range(m) %}
input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep,
input wire input_{{p}}_axis_tvalid,
input wire input_{{p}}_axis_tlast,
input wire input_{{p}}_axis_tuser,
{% endfor %}
/*
* AXI Stream outputs
*/
{%- for p in range(n) %}
output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep,
output wire output_{{p}}_axis_tvalid,
output wire output_{{p}}_axis_tlast,
output wire output_{{p}}_axis_tuser,
{% endfor %}
/*
* Control
*/
{%- for p in range(n) %}
input wire [{{w-1}}:0] output_{{p}}_select{% if not loop.last %},{% endif %}
{%- endfor %}
);
{% for p in range(m) %}
reg [DATA_WIDTH-1:0] input_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg input_{{p}}_axis_tvalid_reg = 1'b0;
reg input_{{p}}_axis_tlast_reg = 1'b0;
reg input_{{p}}_axis_tuser_reg = 1'b0;
{% endfor %}
{%- for p in range(n) %}
reg [DATA_WIDTH-1:0] output_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_{{p}}_axis_tvalid_reg = 1'b0;
reg output_{{p}}_axis_tlast_reg = 1'b0;
reg output_{{p}}_axis_tuser_reg = 1'b0;
{% endfor %}
{%- for p in range(n) %}
reg [{{w-1}}:0] output_{{p}}_select_reg = {{w}}'d0;
{%- endfor %}
{% for p in range(n) %}
assign output_{{p}}_axis_tdata = output_{{p}}_axis_tdata_reg;
assign output_{{p}}_axis_tkeep = output_{{p}}_axis_tkeep_reg;
assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg;
assign output_{{p}}_axis_tlast = output_{{p}}_axis_tlast_reg;
assign output_{{p}}_axis_tuser = output_{{p}}_axis_tuser_reg;
{% endfor %}
always @(posedge clk) begin
if (rst) begin
{%- for p in range(n) %}
output_{{p}}_select_reg <= {{w}}'d0;
{%- endfor %}
{% for p in range(m) %}
input_{{p}}_axis_tvalid_reg <= 1'b0;
{%- endfor %}
{% for p in range(n) %}
output_{{p}}_axis_tvalid_reg <= 1'b0;
{%- endfor %}
end else begin
{%- for p in range(m) %}
input_{{p}}_axis_tvalid_reg <= input_{{p}}_axis_tvalid;
{%- endfor %}
{% for p in range(n) %}
output_{{p}}_select_reg <= output_{{p}}_select;
{%- endfor %}
{%- for p in range(n) %}
case (output_{{p}}_select_reg)
{%- for q in range(m) %}
{{w}}'d{{q}}: output_{{p}}_axis_tvalid_reg <= input_{{q}}_axis_tvalid_reg;
{%- endfor %}
endcase
{%- endfor %}
end
{%- for p in range(m) %}
input_{{p}}_axis_tdata_reg <= input_{{p}}_axis_tdata;
input_{{p}}_axis_tkeep_reg <= input_{{p}}_axis_tkeep;
input_{{p}}_axis_tlast_reg <= input_{{p}}_axis_tlast;
input_{{p}}_axis_tuser_reg <= input_{{p}}_axis_tuser;
{%- endfor %}
{%- for p in range(n) %}
case (output_{{p}}_select_reg)
{%- for q in range(m) %}
{{w}}'d{{q}}: begin
output_{{p}}_axis_tdata_reg <= input_{{q}}_axis_tdata_reg;
output_{{p}}_axis_tkeep_reg <= input_{{q}}_axis_tkeep_reg;
output_{{p}}_axis_tlast_reg <= input_{{q}}_axis_tlast_reg;
output_{{p}}_axis_tuser_reg <= input_{{q}}_axis_tuser_reg;
end
{%- endfor %}
endcase
{%- endfor %}
end
endmodule
""")
output_file.write(t.render(
m=m,
n=n,
w=select_width,
name=name
))
print("Done")
if __name__ == "__main__":
main()

367
lib/axis/rtl/axis_crosspoint_64_4x4.v
View File

@ -1,367 +0,0 @@
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream 4x4 crosspoint (64 bit datapath)
*/
module axis_crosspoint_64_4x4 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI Stream inputs
*/
input wire [DATA_WIDTH-1:0] input_0_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_0_axis_tkeep,
input wire input_0_axis_tvalid,
input wire input_0_axis_tlast,
input wire input_0_axis_tuser,
input wire [DATA_WIDTH-1:0] input_1_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_1_axis_tkeep,
input wire input_1_axis_tvalid,
input wire input_1_axis_tlast,
input wire input_1_axis_tuser,
input wire [DATA_WIDTH-1:0] input_2_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_2_axis_tkeep,
input wire input_2_axis_tvalid,
input wire input_2_axis_tlast,
input wire input_2_axis_tuser,
input wire [DATA_WIDTH-1:0] input_3_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_3_axis_tkeep,
input wire input_3_axis_tvalid,
input wire input_3_axis_tlast,
input wire input_3_axis_tuser,
/*
* AXI Stream outputs
*/
output wire [DATA_WIDTH-1:0] output_0_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_0_axis_tkeep,
output wire output_0_axis_tvalid,
output wire output_0_axis_tlast,
output wire output_0_axis_tuser,
output wire [DATA_WIDTH-1:0] output_1_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_1_axis_tkeep,
output wire output_1_axis_tvalid,
output wire output_1_axis_tlast,
output wire output_1_axis_tuser,
output wire [DATA_WIDTH-1:0] output_2_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_2_axis_tkeep,
output wire output_2_axis_tvalid,
output wire output_2_axis_tlast,
output wire output_2_axis_tuser,
output wire [DATA_WIDTH-1:0] output_3_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_3_axis_tkeep,
output wire output_3_axis_tvalid,
output wire output_3_axis_tlast,
output wire output_3_axis_tuser,
/*
* Control
*/
input wire [1:0] output_0_select,
input wire [1:0] output_1_select,
input wire [1:0] output_2_select,
input wire [1:0] output_3_select
);
reg [DATA_WIDTH-1:0] input_0_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] input_0_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg input_0_axis_tvalid_reg = 1'b0;
reg input_0_axis_tlast_reg = 1'b0;
reg input_0_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] input_1_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] input_1_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg input_1_axis_tvalid_reg = 1'b0;
reg input_1_axis_tlast_reg = 1'b0;
reg input_1_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] input_2_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] input_2_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg input_2_axis_tvalid_reg = 1'b0;
reg input_2_axis_tlast_reg = 1'b0;
reg input_2_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] input_3_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] input_3_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg input_3_axis_tvalid_reg = 1'b0;
reg input_3_axis_tlast_reg = 1'b0;
reg input_3_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] output_0_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_0_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_0_axis_tvalid_reg = 1'b0;
reg output_0_axis_tlast_reg = 1'b0;
reg output_0_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] output_1_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_1_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_1_axis_tvalid_reg = 1'b0;
reg output_1_axis_tlast_reg = 1'b0;
reg output_1_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] output_2_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_2_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_2_axis_tvalid_reg = 1'b0;
reg output_2_axis_tlast_reg = 1'b0;
reg output_2_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] output_3_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_3_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_3_axis_tvalid_reg = 1'b0;
reg output_3_axis_tlast_reg = 1'b0;
reg output_3_axis_tuser_reg = 1'b0;
reg [1:0] output_0_select_reg = 2'd0;
reg [1:0] output_1_select_reg = 2'd0;
reg [1:0] output_2_select_reg = 2'd0;
reg [1:0] output_3_select_reg = 2'd0;
assign output_0_axis_tdata = output_0_axis_tdata_reg;
assign output_0_axis_tkeep = output_0_axis_tkeep_reg;
assign output_0_axis_tvalid = output_0_axis_tvalid_reg;
assign output_0_axis_tlast = output_0_axis_tlast_reg;
assign output_0_axis_tuser = output_0_axis_tuser_reg;
assign output_1_axis_tdata = output_1_axis_tdata_reg;
assign output_1_axis_tkeep = output_1_axis_tkeep_reg;
assign output_1_axis_tvalid = output_1_axis_tvalid_reg;
assign output_1_axis_tlast = output_1_axis_tlast_reg;
assign output_1_axis_tuser = output_1_axis_tuser_reg;
assign output_2_axis_tdata = output_2_axis_tdata_reg;
assign output_2_axis_tkeep = output_2_axis_tkeep_reg;
assign output_2_axis_tvalid = output_2_axis_tvalid_reg;
assign output_2_axis_tlast = output_2_axis_tlast_reg;
assign output_2_axis_tuser = output_2_axis_tuser_reg;
assign output_3_axis_tdata = output_3_axis_tdata_reg;
assign output_3_axis_tkeep = output_3_axis_tkeep_reg;
assign output_3_axis_tvalid = output_3_axis_tvalid_reg;
assign output_3_axis_tlast = output_3_axis_tlast_reg;
assign output_3_axis_tuser = output_3_axis_tuser_reg;
always @(posedge clk) begin
if (rst) begin
output_0_select_reg <= 2'd0;
output_1_select_reg <= 2'd0;
output_2_select_reg <= 2'd0;
output_3_select_reg <= 2'd0;
input_0_axis_tvalid_reg <= 1'b0;
input_1_axis_tvalid_reg <= 1'b0;
input_2_axis_tvalid_reg <= 1'b0;
input_3_axis_tvalid_reg <= 1'b0;
output_0_axis_tvalid_reg <= 1'b0;
output_1_axis_tvalid_reg <= 1'b0;
output_2_axis_tvalid_reg <= 1'b0;
output_3_axis_tvalid_reg <= 1'b0;
end else begin
input_0_axis_tvalid_reg <= input_0_axis_tvalid;
input_1_axis_tvalid_reg <= input_1_axis_tvalid;
input_2_axis_tvalid_reg <= input_2_axis_tvalid;
input_3_axis_tvalid_reg <= input_3_axis_tvalid;
output_0_select_reg <= output_0_select;
output_1_select_reg <= output_1_select;
output_2_select_reg <= output_2_select;
output_3_select_reg <= output_3_select;
case (output_0_select_reg)
2'd0: output_0_axis_tvalid_reg <= input_0_axis_tvalid_reg;
2'd1: output_0_axis_tvalid_reg <= input_1_axis_tvalid_reg;
2'd2: output_0_axis_tvalid_reg <= input_2_axis_tvalid_reg;
2'd3: output_0_axis_tvalid_reg <= input_3_axis_tvalid_reg;
endcase
case (output_1_select_reg)
2'd0: output_1_axis_tvalid_reg <= input_0_axis_tvalid_reg;
2'd1: output_1_axis_tvalid_reg <= input_1_axis_tvalid_reg;
2'd2: output_1_axis_tvalid_reg <= input_2_axis_tvalid_reg;
2'd3: output_1_axis_tvalid_reg <= input_3_axis_tvalid_reg;
endcase
case (output_2_select_reg)
2'd0: output_2_axis_tvalid_reg <= input_0_axis_tvalid_reg;
2'd1: output_2_axis_tvalid_reg <= input_1_axis_tvalid_reg;
2'd2: output_2_axis_tvalid_reg <= input_2_axis_tvalid_reg;
2'd3: output_2_axis_tvalid_reg <= input_3_axis_tvalid_reg;
endcase
case (output_3_select_reg)
2'd0: output_3_axis_tvalid_reg <= input_0_axis_tvalid_reg;
2'd1: output_3_axis_tvalid_reg <= input_1_axis_tvalid_reg;
2'd2: output_3_axis_tvalid_reg <= input_2_axis_tvalid_reg;
2'd3: output_3_axis_tvalid_reg <= input_3_axis_tvalid_reg;
endcase
end
input_0_axis_tdata_reg <= input_0_axis_tdata;
input_0_axis_tkeep_reg <= input_0_axis_tkeep;
input_0_axis_tlast_reg <= input_0_axis_tlast;
input_0_axis_tuser_reg <= input_0_axis_tuser;
input_1_axis_tdata_reg <= input_1_axis_tdata;
input_1_axis_tkeep_reg <= input_1_axis_tkeep;
input_1_axis_tlast_reg <= input_1_axis_tlast;
input_1_axis_tuser_reg <= input_1_axis_tuser;
input_2_axis_tdata_reg <= input_2_axis_tdata;
input_2_axis_tkeep_reg <= input_2_axis_tkeep;
input_2_axis_tlast_reg <= input_2_axis_tlast;
input_2_axis_tuser_reg <= input_2_axis_tuser;
input_3_axis_tdata_reg <= input_3_axis_tdata;
input_3_axis_tkeep_reg <= input_3_axis_tkeep;
input_3_axis_tlast_reg <= input_3_axis_tlast;
input_3_axis_tuser_reg <= input_3_axis_tuser;
case (output_0_select_reg)
2'd0: begin
output_0_axis_tdata_reg <= input_0_axis_tdata_reg;
output_0_axis_tkeep_reg <= input_0_axis_tkeep_reg;
output_0_axis_tlast_reg <= input_0_axis_tlast_reg;
output_0_axis_tuser_reg <= input_0_axis_tuser_reg;
end
2'd1: begin
output_0_axis_tdata_reg <= input_1_axis_tdata_reg;
output_0_axis_tkeep_reg <= input_1_axis_tkeep_reg;
output_0_axis_tlast_reg <= input_1_axis_tlast_reg;
output_0_axis_tuser_reg <= input_1_axis_tuser_reg;
end
2'd2: begin
output_0_axis_tdata_reg <= input_2_axis_tdata_reg;
output_0_axis_tkeep_reg <= input_2_axis_tkeep_reg;
output_0_axis_tlast_reg <= input_2_axis_tlast_reg;
output_0_axis_tuser_reg <= input_2_axis_tuser_reg;
end
2'd3: begin
output_0_axis_tdata_reg <= input_3_axis_tdata_reg;
output_0_axis_tkeep_reg <= input_3_axis_tkeep_reg;
output_0_axis_tlast_reg <= input_3_axis_tlast_reg;
output_0_axis_tuser_reg <= input_3_axis_tuser_reg;
end
endcase
case (output_1_select_reg)
2'd0: begin
output_1_axis_tdata_reg <= input_0_axis_tdata_reg;
output_1_axis_tkeep_reg <= input_0_axis_tkeep_reg;
output_1_axis_tlast_reg <= input_0_axis_tlast_reg;
output_1_axis_tuser_reg <= input_0_axis_tuser_reg;
end
2'd1: begin
output_1_axis_tdata_reg <= input_1_axis_tdata_reg;
output_1_axis_tkeep_reg <= input_1_axis_tkeep_reg;
output_1_axis_tlast_reg <= input_1_axis_tlast_reg;
output_1_axis_tuser_reg <= input_1_axis_tuser_reg;
end
2'd2: begin
output_1_axis_tdata_reg <= input_2_axis_tdata_reg;
output_1_axis_tkeep_reg <= input_2_axis_tkeep_reg;
output_1_axis_tlast_reg <= input_2_axis_tlast_reg;
output_1_axis_tuser_reg <= input_2_axis_tuser_reg;
end
2'd3: begin
output_1_axis_tdata_reg <= input_3_axis_tdata_reg;
output_1_axis_tkeep_reg <= input_3_axis_tkeep_reg;
output_1_axis_tlast_reg <= input_3_axis_tlast_reg;
output_1_axis_tuser_reg <= input_3_axis_tuser_reg;
end
endcase
case (output_2_select_reg)
2'd0: begin
output_2_axis_tdata_reg <= input_0_axis_tdata_reg;
output_2_axis_tkeep_reg <= input_0_axis_tkeep_reg;
output_2_axis_tlast_reg <= input_0_axis_tlast_reg;
output_2_axis_tuser_reg <= input_0_axis_tuser_reg;
end
2'd1: begin
output_2_axis_tdata_reg <= input_1_axis_tdata_reg;
output_2_axis_tkeep_reg <= input_1_axis_tkeep_reg;
output_2_axis_tlast_reg <= input_1_axis_tlast_reg;
output_2_axis_tuser_reg <= input_1_axis_tuser_reg;
end
2'd2: begin
output_2_axis_tdata_reg <= input_2_axis_tdata_reg;
output_2_axis_tkeep_reg <= input_2_axis_tkeep_reg;
output_2_axis_tlast_reg <= input_2_axis_tlast_reg;
output_2_axis_tuser_reg <= input_2_axis_tuser_reg;
end
2'd3: begin
output_2_axis_tdata_reg <= input_3_axis_tdata_reg;
output_2_axis_tkeep_reg <= input_3_axis_tkeep_reg;
output_2_axis_tlast_reg <= input_3_axis_tlast_reg;
output_2_axis_tuser_reg <= input_3_axis_tuser_reg;
end
endcase
case (output_3_select_reg)
2'd0: begin
output_3_axis_tdata_reg <= input_0_axis_tdata_reg;
output_3_axis_tkeep_reg <= input_0_axis_tkeep_reg;
output_3_axis_tlast_reg <= input_0_axis_tlast_reg;
output_3_axis_tuser_reg <= input_0_axis_tuser_reg;
end
2'd1: begin
output_3_axis_tdata_reg <= input_1_axis_tdata_reg;
output_3_axis_tkeep_reg <= input_1_axis_tkeep_reg;
output_3_axis_tlast_reg <= input_1_axis_tlast_reg;
output_3_axis_tuser_reg <= input_1_axis_tuser_reg;
end
2'd2: begin
output_3_axis_tdata_reg <= input_2_axis_tdata_reg;
output_3_axis_tkeep_reg <= input_2_axis_tkeep_reg;
output_3_axis_tlast_reg <= input_2_axis_tlast_reg;
output_3_axis_tuser_reg <= input_2_axis_tuser_reg;
end
2'd3: begin
output_3_axis_tdata_reg <= input_3_axis_tdata_reg;
output_3_axis_tkeep_reg <= input_3_axis_tkeep_reg;
output_3_axis_tlast_reg <= input_3_axis_tlast_reg;
output_3_axis_tuser_reg <= input_3_axis_tuser_reg;
end
endcase
end
endmodule

90
lib/axis/rtl/axis_demux.py
View File

@ -71,30 +71,44 @@ THE SOFTWARE.
*/ */
module {{name}} # module {{name}} #
( (
parameter DATA_WIDTH = 8 parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
) )
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
/* /*
* AXI input * AXI input
*/ */
input wire [DATA_WIDTH-1:0] input_axis_tdata, input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid, input wire input_axis_tvalid,
output wire input_axis_tready, output wire input_axis_tready,
input wire input_axis_tlast, input wire input_axis_tlast,
input wire input_axis_tuser, input wire [ID_WIDTH-1:0] input_axis_tid,
input wire [DEST_WIDTH-1:0] input_axis_tdest,
input wire [USER_WIDTH-1:0] input_axis_tuser,
/* /*
* AXI outputs * AXI outputs
*/ */
{%- for p in ports %} {%- for p in ports %}
output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata, output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep,
output wire output_{{p}}_axis_tvalid, output wire output_{{p}}_axis_tvalid,
input wire output_{{p}}_axis_tready, input wire output_{{p}}_axis_tready,
output wire output_{{p}}_axis_tlast, output wire output_{{p}}_axis_tlast,
output wire output_{{p}}_axis_tuser, output wire [ID_WIDTH-1:0] output_{{p}}_axis_tid,
output wire [DEST_WIDTH-1:0] output_{{p}}_axis_tdest,
output wire [USER_WIDTH-1:0] output_{{p}}_axis_tuser,
{% endfor %} {% endfor %}
/* /*
* Control * Control
@ -109,12 +123,15 @@ reg frame_reg = 1'b0, frame_next;
reg input_axis_tready_reg = 1'b0, input_axis_tready_next; reg input_axis_tready_reg = 1'b0, input_axis_tready_next;
// internal datapath // internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int; reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg output_axis_tvalid_int; reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tready_int_reg = 1'b0; reg output_axis_tvalid_int;
reg output_axis_tlast_int; reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tuser_int; reg output_axis_tlast_int;
wire output_axis_tready_int_early; reg [ID_WIDTH-1:0] output_axis_tid_int;
reg [DEST_WIDTH-1:0] output_axis_tdest_int;
reg [USER_WIDTH-1:0] output_axis_tuser_int;
wire output_axis_tready_int_early;
assign input_axis_tready = input_axis_tready_reg; assign input_axis_tready = input_axis_tready_reg;
@ -157,10 +174,13 @@ always @* begin
input_axis_tready_next = output_axis_tready_int_early & frame_next; input_axis_tready_next = output_axis_tready_int_early & frame_next;
output_axis_tdata_int = input_axis_tdata; output_axis_tdata_int = input_axis_tdata;
output_axis_tkeep_int = input_axis_tkeep;
output_axis_tvalid_int = input_axis_tvalid & input_axis_tready; output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
output_axis_tlast_int = input_axis_tlast; output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser; output_axis_tid_int = input_axis_tid;
output_axis_tdest_int = input_axis_tdest;
output_axis_tuser_int = input_axis_tuser;
end end
always @(posedge clk) begin always @(posedge clk) begin
@ -176,27 +196,36 @@ always @(posedge clk) begin
end end
// output datapath logic // output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
{%- for p in ports %} {%- for p in ports %}
reg output_{{p}}_axis_tvalid_reg = 1'b0, output_{{p}}_axis_tvalid_next; reg output_{{p}}_axis_tvalid_reg = 1'b0, output_{{p}}_axis_tvalid_next;
{%- endfor %} {%- endfor %}
reg output_axis_tlast_reg = 1'b0; reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] output_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] output_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next; reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0; reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] temp_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control // datapath control
reg store_axis_int_to_output; reg store_axis_int_to_output;
reg store_axis_int_to_temp; reg store_axis_int_to_temp;
reg store_axis_temp_to_output; reg store_axis_temp_to_output;
{% for p in ports %} {% for p in ports %}
assign output_{{p}}_axis_tdata = output_axis_tdata_reg; assign output_{{p}}_axis_tdata = output_axis_tdata_reg;
assign output_{{p}}_axis_tkeep = KEEP_ENABLE ? output_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg; assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg;
assign output_{{p}}_axis_tlast = output_axis_tlast_reg; assign output_{{p}}_axis_tlast = output_axis_tlast_reg;
assign output_{{p}}_axis_tuser = output_axis_tuser_reg; assign output_{{p}}_axis_tid = ID_ENABLE ? output_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_{{p}}_axis_tdest = DEST_ENABLE ? output_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign output_{{p}}_axis_tuser = USER_ENABLE ? output_axis_tuser_int : {USER_WIDTH{1'b0}};
{% endfor %} {% endfor %}
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = current_output_tready | (~temp_axis_tvalid_reg & (~current_output_tvalid | ~output_axis_tvalid_int)); assign output_axis_tready_int_early = current_output_tready | (~temp_axis_tvalid_reg & (~current_output_tvalid | ~output_axis_tvalid_int));
@ -211,7 +240,7 @@ always @* begin
store_axis_int_to_output = 1'b0; store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0; store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0; store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
// input is ready // input is ready
if (current_output_tready | ~current_output_tvalid) begin if (current_output_tready | ~current_output_tvalid) begin
@ -253,17 +282,26 @@ always @(posedge clk) begin
// datapath // datapath
if (store_axis_int_to_output) begin if (store_axis_int_to_output) begin
output_axis_tdata_reg <= output_axis_tdata_int; output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tlast_reg <= output_axis_tlast_int; output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tid_reg <= output_axis_tid_int;
output_axis_tdest_reg <= output_axis_tdest_int;
output_axis_tuser_reg <= output_axis_tuser_int; output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg; output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg; output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tid_reg <= temp_axis_tid_reg;
output_axis_tdest_reg <= temp_axis_tdest_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg; output_axis_tuser_reg <= temp_axis_tuser_reg;
end end
if (store_axis_int_to_temp) begin if (store_axis_int_to_temp) begin
temp_axis_tdata_reg <= output_axis_tdata_int; temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tlast_reg <= output_axis_tlast_int; temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tid_reg <= output_axis_tid_int;
temp_axis_tdest_reg <= output_axis_tdest_int;
temp_axis_tuser_reg <= output_axis_tuser_int; temp_axis_tuser_reg <= output_axis_tuser_int;
end end
end end
@ -271,14 +309,14 @@ end
endmodule endmodule
""") """)
output_file.write(t.render( output_file.write(t.render(
n=ports, n=ports,
w=select_width, w=select_width,
name=name, name=name,
ports=range(ports) ports=range(ports)
)) ))
print("Done") print("Done")
if __name__ == "__main__": if __name__ == "__main__":

128
lib/axis/rtl/axis_demux_4.v
View File

@ -31,47 +31,70 @@ THE SOFTWARE.
*/ */
module axis_demux_4 # module axis_demux_4 #
( (
parameter DATA_WIDTH = 8 parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
) )
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
/* /*
* AXI input * AXI input
*/ */
input wire [DATA_WIDTH-1:0] input_axis_tdata, input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid, input wire input_axis_tvalid,
output wire input_axis_tready, output wire input_axis_tready,
input wire input_axis_tlast, input wire input_axis_tlast,
input wire input_axis_tuser, input wire [ID_WIDTH-1:0] input_axis_tid,
input wire [DEST_WIDTH-1:0] input_axis_tdest,
input wire [USER_WIDTH-1:0] input_axis_tuser,
/* /*
* AXI outputs * AXI outputs
*/ */
output wire [DATA_WIDTH-1:0] output_0_axis_tdata, output wire [DATA_WIDTH-1:0] output_0_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_0_axis_tkeep,
output wire output_0_axis_tvalid, output wire output_0_axis_tvalid,
input wire output_0_axis_tready, input wire output_0_axis_tready,
output wire output_0_axis_tlast, output wire output_0_axis_tlast,
output wire output_0_axis_tuser, output wire [ID_WIDTH-1:0] output_0_axis_tid,
output wire [DEST_WIDTH-1:0] output_0_axis_tdest,
output wire [USER_WIDTH-1:0] output_0_axis_tuser,
output wire [DATA_WIDTH-1:0] output_1_axis_tdata, output wire [DATA_WIDTH-1:0] output_1_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_1_axis_tkeep,
output wire output_1_axis_tvalid, output wire output_1_axis_tvalid,
input wire output_1_axis_tready, input wire output_1_axis_tready,
output wire output_1_axis_tlast, output wire output_1_axis_tlast,
output wire output_1_axis_tuser, output wire [ID_WIDTH-1:0] output_1_axis_tid,
output wire [DEST_WIDTH-1:0] output_1_axis_tdest,
output wire [USER_WIDTH-1:0] output_1_axis_tuser,
output wire [DATA_WIDTH-1:0] output_2_axis_tdata, output wire [DATA_WIDTH-1:0] output_2_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_2_axis_tkeep,
output wire output_2_axis_tvalid, output wire output_2_axis_tvalid,
input wire output_2_axis_tready, input wire output_2_axis_tready,
output wire output_2_axis_tlast, output wire output_2_axis_tlast,
output wire output_2_axis_tuser, output wire [ID_WIDTH-1:0] output_2_axis_tid,
output wire [DEST_WIDTH-1:0] output_2_axis_tdest,
output wire [USER_WIDTH-1:0] output_2_axis_tuser,
output wire [DATA_WIDTH-1:0] output_3_axis_tdata, output wire [DATA_WIDTH-1:0] output_3_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_3_axis_tkeep,
output wire output_3_axis_tvalid, output wire output_3_axis_tvalid,
input wire output_3_axis_tready, input wire output_3_axis_tready,
output wire output_3_axis_tlast, output wire output_3_axis_tlast,
output wire output_3_axis_tuser, output wire [ID_WIDTH-1:0] output_3_axis_tid,
output wire [DEST_WIDTH-1:0] output_3_axis_tdest,
output wire [USER_WIDTH-1:0] output_3_axis_tuser,
/* /*
* Control * Control
@ -86,12 +109,15 @@ reg frame_reg = 1'b0, frame_next;
reg input_axis_tready_reg = 1'b0, input_axis_tready_next; reg input_axis_tready_reg = 1'b0, input_axis_tready_next;
// internal datapath // internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int; reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg output_axis_tvalid_int; reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tready_int_reg = 1'b0; reg output_axis_tvalid_int;
reg output_axis_tlast_int; reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tuser_int; reg output_axis_tlast_int;
wire output_axis_tready_int_early; reg [ID_WIDTH-1:0] output_axis_tid_int;
reg [DEST_WIDTH-1:0] output_axis_tdest_int;
reg [USER_WIDTH-1:0] output_axis_tuser_int;
wire output_axis_tready_int_early;
assign input_axis_tready = input_axis_tready_reg; assign input_axis_tready = input_axis_tready_reg;
@ -144,10 +170,13 @@ always @* begin
input_axis_tready_next = output_axis_tready_int_early & frame_next; input_axis_tready_next = output_axis_tready_int_early & frame_next;
output_axis_tdata_int = input_axis_tdata; output_axis_tdata_int = input_axis_tdata;
output_axis_tkeep_int = input_axis_tkeep;
output_axis_tvalid_int = input_axis_tvalid & input_axis_tready; output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
output_axis_tlast_int = input_axis_tlast; output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser; output_axis_tid_int = input_axis_tid;
output_axis_tdest_int = input_axis_tdest;
output_axis_tuser_int = input_axis_tuser;
end end
always @(posedge clk) begin always @(posedge clk) begin
@ -163,43 +192,61 @@ always @(posedge clk) begin
end end
// output datapath logic // output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_0_axis_tvalid_reg = 1'b0, output_0_axis_tvalid_next; reg output_0_axis_tvalid_reg = 1'b0, output_0_axis_tvalid_next;
reg output_1_axis_tvalid_reg = 1'b0, output_1_axis_tvalid_next; reg output_1_axis_tvalid_reg = 1'b0, output_1_axis_tvalid_next;
reg output_2_axis_tvalid_reg = 1'b0, output_2_axis_tvalid_next; reg output_2_axis_tvalid_reg = 1'b0, output_2_axis_tvalid_next;
reg output_3_axis_tvalid_reg = 1'b0, output_3_axis_tvalid_next; reg output_3_axis_tvalid_reg = 1'b0, output_3_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0; reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] output_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] output_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next; reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0; reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] temp_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control // datapath control
reg store_axis_int_to_output; reg store_axis_int_to_output;
reg store_axis_int_to_temp; reg store_axis_int_to_temp;
reg store_axis_temp_to_output; reg store_axis_temp_to_output;
assign output_0_axis_tdata = output_axis_tdata_reg; assign output_0_axis_tdata = output_axis_tdata_reg;
assign output_0_axis_tkeep = KEEP_ENABLE ? output_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_0_axis_tvalid = output_0_axis_tvalid_reg; assign output_0_axis_tvalid = output_0_axis_tvalid_reg;
assign output_0_axis_tlast = output_axis_tlast_reg; assign output_0_axis_tlast = output_axis_tlast_reg;
assign output_0_axis_tuser = output_axis_tuser_reg; assign output_0_axis_tid = ID_ENABLE ? output_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_0_axis_tdest = DEST_ENABLE ? output_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign output_0_axis_tuser = USER_ENABLE ? output_axis_tuser_int : {USER_WIDTH{1'b0}};
assign output_1_axis_tdata = output_axis_tdata_reg; assign output_1_axis_tdata = output_axis_tdata_reg;
assign output_1_axis_tkeep = KEEP_ENABLE ? output_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_1_axis_tvalid = output_1_axis_tvalid_reg; assign output_1_axis_tvalid = output_1_axis_tvalid_reg;
assign output_1_axis_tlast = output_axis_tlast_reg; assign output_1_axis_tlast = output_axis_tlast_reg;
assign output_1_axis_tuser = output_axis_tuser_reg; assign output_1_axis_tid = ID_ENABLE ? output_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_1_axis_tdest = DEST_ENABLE ? output_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign output_1_axis_tuser = USER_ENABLE ? output_axis_tuser_int : {USER_WIDTH{1'b0}};
assign output_2_axis_tdata = output_axis_tdata_reg; assign output_2_axis_tdata = output_axis_tdata_reg;
assign output_2_axis_tkeep = KEEP_ENABLE ? output_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_2_axis_tvalid = output_2_axis_tvalid_reg; assign output_2_axis_tvalid = output_2_axis_tvalid_reg;
assign output_2_axis_tlast = output_axis_tlast_reg; assign output_2_axis_tlast = output_axis_tlast_reg;
assign output_2_axis_tuser = output_axis_tuser_reg; assign output_2_axis_tid = ID_ENABLE ? output_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_2_axis_tdest = DEST_ENABLE ? output_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign output_2_axis_tuser = USER_ENABLE ? output_axis_tuser_int : {USER_WIDTH{1'b0}};
assign output_3_axis_tdata = output_axis_tdata_reg; assign output_3_axis_tdata = output_axis_tdata_reg;
assign output_3_axis_tkeep = KEEP_ENABLE ? output_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_3_axis_tvalid = output_3_axis_tvalid_reg; assign output_3_axis_tvalid = output_3_axis_tvalid_reg;
assign output_3_axis_tlast = output_axis_tlast_reg; assign output_3_axis_tlast = output_axis_tlast_reg;
assign output_3_axis_tuser = output_axis_tuser_reg; assign output_3_axis_tid = ID_ENABLE ? output_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_3_axis_tdest = DEST_ENABLE ? output_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign output_3_axis_tuser = USER_ENABLE ? output_axis_tuser_int : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = current_output_tready | (~temp_axis_tvalid_reg & (~current_output_tvalid | ~output_axis_tvalid_int)); assign output_axis_tready_int_early = current_output_tready | (~temp_axis_tvalid_reg & (~current_output_tvalid | ~output_axis_tvalid_int));
@ -215,7 +262,7 @@ always @* begin
store_axis_int_to_output = 1'b0; store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0; store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0; store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
// input is ready // input is ready
if (current_output_tready | ~current_output_tvalid) begin if (current_output_tready | ~current_output_tvalid) begin
@ -261,17 +308,26 @@ always @(posedge clk) begin
// datapath // datapath
if (store_axis_int_to_output) begin if (store_axis_int_to_output) begin
output_axis_tdata_reg <= output_axis_tdata_int; output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tlast_reg <= output_axis_tlast_int; output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tid_reg <= output_axis_tid_int;
output_axis_tdest_reg <= output_axis_tdest_int;
output_axis_tuser_reg <= output_axis_tuser_int; output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg; output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg; output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tid_reg <= temp_axis_tid_reg;
output_axis_tdest_reg <= temp_axis_tdest_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg; output_axis_tuser_reg <= temp_axis_tuser_reg;
end end
if (store_axis_int_to_temp) begin if (store_axis_int_to_temp) begin
temp_axis_tdata_reg <= output_axis_tdata_int; temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tlast_reg <= output_axis_tlast_int; temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tid_reg <= output_axis_tid_int;
temp_axis_tdest_reg <= output_axis_tdest_int;
temp_axis_tuser_reg <= output_axis_tuser_int; temp_axis_tuser_reg <= output_axis_tuser_int;
end end
end end

297
lib/axis/rtl/axis_demux_64.py
View File

@ -1,297 +0,0 @@
#!/usr/bin/env python
"""
Generates an AXI Stream demux with the specified number of ports
"""
from __future__ import print_function
import argparse
import math
from jinja2 import Template
def main():
parser = argparse.ArgumentParser(description=__doc__.strip())
parser.add_argument('-p', '--ports', type=int, default=4, help="number of ports")
parser.add_argument('-n', '--name', type=str, help="module name")
parser.add_argument('-o', '--output', type=str, help="output file name")
args = parser.parse_args()
try:
generate(**args.__dict__)
except IOError as ex:
print(ex)
exit(1)
def generate(ports=4, name=None, output=None):
if name is None:
name = "axis_demux_64_{0}".format(ports)
if output is None:
output = name + ".v"
print("Opening file '{0}'...".format(output))
output_file = open(output, 'w')
print("Generating {0} port AXI Stream demux {1}...".format(ports, name))
select_width = int(math.ceil(math.log(ports, 2)))
t = Template(u"""/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream {{n}} port demultiplexer (64 bit datapath)
*/
module {{name}} #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI outputs
*/
{%- for p in ports %}
output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep,
output wire output_{{p}}_axis_tvalid,
input wire output_{{p}}_axis_tready,
output wire output_{{p}}_axis_tlast,
output wire output_{{p}}_axis_tuser,
{% endfor %}
/*
* Control
*/
input wire enable,
input wire [{{w-1}}:0] select
);
reg [{{w-1}}:0] select_reg = {{w}}'d0, select_next;
reg frame_reg = 1'b0, frame_next;
reg input_axis_tready_reg = 1'b0, input_axis_tready_next;
// internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
assign input_axis_tready = input_axis_tready_reg;
// mux for output control signals
reg current_output_tready;
reg current_output_tvalid;
always @* begin
case (select_reg)
{%- for p in ports %}
{{w}}'d{{p}}: begin
current_output_tvalid = output_{{p}}_axis_tvalid;
current_output_tready = output_{{p}}_axis_tready;
end
{%- endfor %}
default: begin
current_output_tvalid = 1'b0;
current_output_tready = 1'b0;
end
endcase
end
always @* begin
select_next = select_reg;
frame_next = frame_reg;
input_axis_tready_next = 1'b0;
if (input_axis_tvalid & input_axis_tready) begin
// end of frame detection
if (input_axis_tlast) begin
frame_next = 1'b0;
end
end
if (~frame_reg & enable & input_axis_tvalid & ~current_output_tvalid) begin
// start of frame, grab select value
frame_next = 1'b1;
select_next = select;
end
input_axis_tready_next = output_axis_tready_int_early & frame_next;
output_axis_tdata_int = input_axis_tdata;
output_axis_tkeep_int = input_axis_tkeep;
output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= {{w}}'d0;
frame_reg <= 1'b0;
input_axis_tready_reg <= 1'b0;
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
input_axis_tready_reg <= input_axis_tready_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
{%- for p in ports %}
reg output_{{p}}_axis_tvalid_reg = 1'b0, output_{{p}}_axis_tvalid_next;
{%- endfor %}
reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
{% for p in ports %}
assign output_{{p}}_axis_tdata = output_axis_tdata_reg;
assign output_{{p}}_axis_tkeep = output_axis_tkeep_reg;
assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg;
assign output_{{p}}_axis_tlast = output_axis_tlast_reg;
assign output_{{p}}_axis_tuser = output_axis_tuser_reg;
{% endfor %}
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = current_output_tready | (~temp_axis_tvalid_reg & (~current_output_tvalid | ~output_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
{%- for p in ports %}
output_{{p}}_axis_tvalid_next = output_{{p}}_axis_tvalid_reg;
{%- endfor %}
temp_axis_tvalid_next = temp_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin
// input is ready
if (current_output_tready | ~current_output_tvalid) begin
// output is ready or currently not valid, transfer data to output
{%- for p in ports %}
output_{{p}}_axis_tvalid_next = output_axis_tvalid_int & (select_reg == {{w}}'d{{p}});
{%- endfor %}
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_axis_tvalid_next = output_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (current_output_tready) begin
// input is not ready, but output is ready
{%- for p in ports %}
output_{{p}}_axis_tvalid_next = temp_axis_tvalid_reg & (select_reg == {{w}}'d{{p}});
{%- endfor %}
temp_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
{%- for p in ports %}
output_{{p}}_axis_tvalid_reg <= 1'b0;
{%- endfor %}
output_axis_tready_int_reg <= 1'b0;
temp_axis_tvalid_reg <= 1'b0;
end else begin
{%- for p in ports %}
output_{{p}}_axis_tvalid_reg <= output_{{p}}_axis_tvalid_next;
{%- endfor %}
output_axis_tready_int_reg <= output_axis_tready_int_early;
temp_axis_tvalid_reg <= temp_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end
endmodule
""")
output_file.write(t.render(
n=ports,
w=select_width,
name=name,
ports=range(ports)
))
print("Done")
if __name__ == "__main__":
main()

296
lib/axis/rtl/axis_demux_64_4.v
View File

@ -1,296 +0,0 @@
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream 4 port demultiplexer (64 bit datapath)
*/
module axis_demux_64_4 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI outputs
*/
output wire [DATA_WIDTH-1:0] output_0_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_0_axis_tkeep,
output wire output_0_axis_tvalid,
input wire output_0_axis_tready,
output wire output_0_axis_tlast,
output wire output_0_axis_tuser,
output wire [DATA_WIDTH-1:0] output_1_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_1_axis_tkeep,
output wire output_1_axis_tvalid,
input wire output_1_axis_tready,
output wire output_1_axis_tlast,
output wire output_1_axis_tuser,
output wire [DATA_WIDTH-1:0] output_2_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_2_axis_tkeep,
output wire output_2_axis_tvalid,
input wire output_2_axis_tready,
output wire output_2_axis_tlast,
output wire output_2_axis_tuser,
output wire [DATA_WIDTH-1:0] output_3_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_3_axis_tkeep,
output wire output_3_axis_tvalid,
input wire output_3_axis_tready,
output wire output_3_axis_tlast,
output wire output_3_axis_tuser,
/*
* Control
*/
input wire enable,
input wire [1:0] select
);
reg [1:0] select_reg = 2'd0, select_next;
reg frame_reg = 1'b0, frame_next;
reg input_axis_tready_reg = 1'b0, input_axis_tready_next;
// internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
assign input_axis_tready = input_axis_tready_reg;
// mux for output control signals
reg current_output_tready;
reg current_output_tvalid;
always @* begin
case (select_reg)
2'd0: begin
current_output_tvalid = output_0_axis_tvalid;
current_output_tready = output_0_axis_tready;
end
2'd1: begin
current_output_tvalid = output_1_axis_tvalid;
current_output_tready = output_1_axis_tready;
end
2'd2: begin
current_output_tvalid = output_2_axis_tvalid;
current_output_tready = output_2_axis_tready;
end
2'd3: begin
current_output_tvalid = output_3_axis_tvalid;
current_output_tready = output_3_axis_tready;
end
default: begin
current_output_tvalid = 1'b0;
current_output_tready = 1'b0;
end
endcase
end
always @* begin
select_next = select_reg;
frame_next = frame_reg;
input_axis_tready_next = 1'b0;
if (input_axis_tvalid & input_axis_tready) begin
// end of frame detection
if (input_axis_tlast) begin
frame_next = 1'b0;
end
end
if (~frame_reg & enable & input_axis_tvalid & ~current_output_tvalid) begin
// start of frame, grab select value
frame_next = 1'b1;
select_next = select;
end
input_axis_tready_next = output_axis_tready_int_early & frame_next;
output_axis_tdata_int = input_axis_tdata;
output_axis_tkeep_int = input_axis_tkeep;
output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= 2'd0;
frame_reg <= 1'b0;
input_axis_tready_reg <= 1'b0;
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
input_axis_tready_reg <= input_axis_tready_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_0_axis_tvalid_reg = 1'b0, output_0_axis_tvalid_next;
reg output_1_axis_tvalid_reg = 1'b0, output_1_axis_tvalid_next;
reg output_2_axis_tvalid_reg = 1'b0, output_2_axis_tvalid_next;
reg output_3_axis_tvalid_reg = 1'b0, output_3_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign output_0_axis_tdata = output_axis_tdata_reg;
assign output_0_axis_tkeep = output_axis_tkeep_reg;
assign output_0_axis_tvalid = output_0_axis_tvalid_reg;
assign output_0_axis_tlast = output_axis_tlast_reg;
assign output_0_axis_tuser = output_axis_tuser_reg;
assign output_1_axis_tdata = output_axis_tdata_reg;
assign output_1_axis_tkeep = output_axis_tkeep_reg;
assign output_1_axis_tvalid = output_1_axis_tvalid_reg;
assign output_1_axis_tlast = output_axis_tlast_reg;
assign output_1_axis_tuser = output_axis_tuser_reg;
assign output_2_axis_tdata = output_axis_tdata_reg;
assign output_2_axis_tkeep = output_axis_tkeep_reg;
assign output_2_axis_tvalid = output_2_axis_tvalid_reg;
assign output_2_axis_tlast = output_axis_tlast_reg;
assign output_2_axis_tuser = output_axis_tuser_reg;
assign output_3_axis_tdata = output_axis_tdata_reg;
assign output_3_axis_tkeep = output_axis_tkeep_reg;
assign output_3_axis_tvalid = output_3_axis_tvalid_reg;
assign output_3_axis_tlast = output_axis_tlast_reg;
assign output_3_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = current_output_tready | (~temp_axis_tvalid_reg & (~current_output_tvalid | ~output_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
output_0_axis_tvalid_next = output_0_axis_tvalid_reg;
output_1_axis_tvalid_next = output_1_axis_tvalid_reg;
output_2_axis_tvalid_next = output_2_axis_tvalid_reg;
output_3_axis_tvalid_next = output_3_axis_tvalid_reg;
temp_axis_tvalid_next = temp_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin
// input is ready
if (current_output_tready | ~current_output_tvalid) begin
// output is ready or currently not valid, transfer data to output
output_0_axis_tvalid_next = output_axis_tvalid_int & (select_reg == 2'd0);
output_1_axis_tvalid_next = output_axis_tvalid_int & (select_reg == 2'd1);
output_2_axis_tvalid_next = output_axis_tvalid_int & (select_reg == 2'd2);
output_3_axis_tvalid_next = output_axis_tvalid_int & (select_reg == 2'd3);
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_axis_tvalid_next = output_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (current_output_tready) begin
// input is not ready, but output is ready
output_0_axis_tvalid_next = temp_axis_tvalid_reg & (select_reg == 2'd0);
output_1_axis_tvalid_next = temp_axis_tvalid_reg & (select_reg == 2'd1);
output_2_axis_tvalid_next = temp_axis_tvalid_reg & (select_reg == 2'd2);
output_3_axis_tvalid_next = temp_axis_tvalid_reg & (select_reg == 2'd3);
temp_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
output_0_axis_tvalid_reg <= 1'b0;
output_1_axis_tvalid_reg <= 1'b0;
output_2_axis_tvalid_reg <= 1'b0;
output_3_axis_tvalid_reg <= 1'b0;
output_axis_tready_int_reg <= 1'b0;
temp_axis_tvalid_reg <= 1'b0;
end else begin
output_0_axis_tvalid_reg <= output_0_axis_tvalid_next;
output_1_axis_tvalid_reg <= output_1_axis_tvalid_next;
output_2_axis_tvalid_reg <= output_2_axis_tvalid_next;
output_3_axis_tvalid_reg <= output_3_axis_tvalid_next;
output_axis_tready_int_reg <= output_axis_tready_int_early;
temp_axis_tvalid_reg <= temp_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end
endmodule

61
lib/axis/rtl/axis_fifo.v
View File

@ -32,43 +32,65 @@ THE SOFTWARE.
module axis_fifo # module axis_fifo #
( (
parameter ADDR_WIDTH = 12, parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 8 parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter LAST_ENABLE = 1,
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
) )
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
/* /*
* AXI input * AXI input
*/ */
input wire [DATA_WIDTH-1:0] input_axis_tdata, input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid, input wire input_axis_tvalid,
output wire input_axis_tready, output wire input_axis_tready,
input wire input_axis_tlast, input wire input_axis_tlast,
input wire input_axis_tuser, input wire [ID_WIDTH-1:0] input_axis_tid,
input wire [DEST_WIDTH-1:0] input_axis_tdest,
input wire [USER_WIDTH-1:0] input_axis_tuser,
/* /*
* AXI output * AXI output
*/ */
output wire [DATA_WIDTH-1:0] output_axis_tdata, output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid, output wire output_axis_tvalid,
input wire output_axis_tready, input wire output_axis_tready,
output wire output_axis_tlast, output wire output_axis_tlast,
output wire output_axis_tuser output wire [ID_WIDTH-1:0] output_axis_tid,
output wire [DEST_WIDTH-1:0] output_axis_tdest,
output wire [USER_WIDTH-1:0] output_axis_tuser
); );
localparam KEEP_OFFSET = DATA_WIDTH;
localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0);
localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next; reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}}; reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next; reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}}; reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [DATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0]; reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+2-1:0] mem_read_data_reg = {DATA_WIDTH+2{1'b0}}; reg [WIDTH-1:0] mem_read_data_reg;
reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next; reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
wire [DATA_WIDTH+2-1:0] mem_write_data;
reg [DATA_WIDTH+2-1:0] output_data_reg = {DATA_WIDTH+2{1'b0}}; wire [WIDTH-1:0] input_axis;
reg [WIDTH-1:0] output_axis_reg;
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next; reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
// full when first MSB different but rest same // full when first MSB different but rest same
@ -84,10 +106,23 @@ reg store_output;
assign input_axis_tready = ~full; assign input_axis_tready = ~full;
generate
assign input_axis[DATA_WIDTH-1:0] = input_axis_tdata;
if (KEEP_ENABLE) assign input_axis[KEEP_OFFSET +: KEEP_WIDTH] = input_axis_tkeep;
if (LAST_ENABLE) assign input_axis[LAST_OFFSET] = input_axis_tlast;
if (ID_ENABLE) assign input_axis[ID_OFFSET +: ID_WIDTH] = input_axis_tid;
if (DEST_ENABLE) assign input_axis[DEST_OFFSET +: DEST_WIDTH] = input_axis_tdest;
if (USER_ENABLE) assign input_axis[USER_OFFSET +: USER_WIDTH] = input_axis_tuser;
endgenerate
assign output_axis_tvalid = output_axis_tvalid_reg; assign output_axis_tvalid = output_axis_tvalid_reg;
assign mem_write_data = {input_axis_tlast, input_axis_tuser, input_axis_tdata}; assign output_axis_tdata = output_axis_reg[DATA_WIDTH-1:0];
assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = output_data_reg; assign output_axis_tkeep = KEEP_ENABLE ? output_axis_reg[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
assign output_axis_tlast = LAST_ENABLE ? output_axis_reg[LAST_OFFSET] : 1'b1;
assign output_axis_tid = ID_ENABLE ? output_axis_reg[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}};
assign output_axis_tdest = DEST_ENABLE ? output_axis_reg[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
assign output_axis_tuser = USER_ENABLE ? output_axis_reg[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
// Write logic // Write logic
always @* begin always @* begin
@ -115,7 +150,7 @@ always @(posedge clk) begin
wr_addr_reg <= wr_ptr_next; wr_addr_reg <= wr_ptr_next;
if (write) begin if (write) begin
mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data; mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= input_axis;
end end
end end
@ -177,7 +212,7 @@ always @(posedge clk) begin
end end
if (store_output) begin if (store_output) begin
output_data_reg <= mem_read_data_reg; output_axis_reg <= mem_read_data_reg;
end end
end end

187
lib/axis/rtl/axis_fifo_64.v
View File

@ -1,187 +0,0 @@
/*
Copyright (c) 2013-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream FIFO (64 bit datapath)
*/
module axis_fifo_64 #
(
parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem_read_data_reg = {DATA_WIDTH+KEEP_WIDTH+2{1'b0}};
reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
wire [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem_write_data;
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] output_data_reg = {DATA_WIDTH+KEEP_WIDTH+2{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
// full when first MSB different but rest same
wire full = ((wr_ptr_reg[ADDR_WIDTH] != rd_ptr_reg[ADDR_WIDTH]) &&
(wr_ptr_reg[ADDR_WIDTH-1:0] == rd_ptr_reg[ADDR_WIDTH-1:0]));
// empty when pointers match exactly
wire empty = wr_ptr_reg == rd_ptr_reg;
// control signals
reg write;
reg read;
reg store_output;
assign input_axis_tready = ~full;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign mem_write_data = {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};
assign {output_axis_tlast, output_axis_tuser, output_axis_tkeep, output_axis_tdata} = output_data_reg;
// Write logic
always @* begin
write = 1'b0;
wr_ptr_next = wr_ptr_reg;
if (input_axis_tvalid) begin
// input data valid
if (~full) begin
// not full, perform write
write = 1'b1;
wr_ptr_next = wr_ptr_reg + 1;
end
end
end
always @(posedge clk) begin
if (rst) begin
wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
end else begin
wr_ptr_reg <= wr_ptr_next;
end
wr_addr_reg <= wr_ptr_next;
if (write) begin
mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
// Read logic
always @* begin
read = 1'b0;
rd_ptr_next = rd_ptr_reg;
mem_read_data_valid_next = mem_read_data_valid_reg;
if (store_output | ~mem_read_data_valid_reg) begin
// output data not valid OR currently being transferred
if (~empty) begin
// not empty, perform read
read = 1'b1;
mem_read_data_valid_next = 1'b1;
rd_ptr_next = rd_ptr_reg + 1;
end else begin
// empty, invalidate
mem_read_data_valid_next = 1'b0;
end
end
end
always @(posedge clk) begin
if (rst) begin
rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
mem_read_data_valid_reg <= 1'b0;
end else begin
rd_ptr_reg <= rd_ptr_next;
mem_read_data_valid_reg <= mem_read_data_valid_next;
end
rd_addr_reg <= rd_ptr_next;
if (read) begin
mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]];
end
end
// Output register
always @* begin
store_output = 1'b0;
output_axis_tvalid_next = output_axis_tvalid_reg;
if (output_axis_tready | ~output_axis_tvalid) begin
store_output = 1'b1;
output_axis_tvalid_next = mem_read_data_valid_reg;
end
end
always @(posedge clk) begin
if (rst) begin
output_axis_tvalid_reg <= 1'b0;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
end
if (store_output) begin
output_data_reg <= mem_read_data_reg;
end
end
endmodule

62
lib/axis/rtl/axis_frame_fifo.v
View File

@ -33,28 +33,46 @@ module axis_frame_fifo #
( (
parameter ADDR_WIDTH = 12, parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 8, parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
parameter USER_BAD_FRAME_VALUE = 1'b1,
parameter USER_BAD_FRAME_MASK = 1'b1,
parameter DROP_BAD_FRAME = 1,
parameter DROP_WHEN_FULL = 0 parameter DROP_WHEN_FULL = 0
) )
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
/* /*
* AXI input * AXI input
*/ */
input wire [DATA_WIDTH-1:0] input_axis_tdata, input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid, input wire input_axis_tvalid,
output wire input_axis_tready, output wire input_axis_tready,
input wire input_axis_tlast, input wire input_axis_tlast,
input wire input_axis_tuser, input wire [ID_WIDTH-1:0] input_axis_tid,
input wire [DEST_WIDTH-1:0] input_axis_tdest,
input wire [USER_WIDTH-1:0] input_axis_tuser,
/* /*
* AXI output * AXI output
*/ */
output wire [DATA_WIDTH-1:0] output_axis_tdata, output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid, output wire output_axis_tvalid,
input wire output_axis_tready, input wire output_axis_tready,
output wire output_axis_tlast, output wire output_axis_tlast,
output wire [ID_WIDTH-1:0] output_axis_tid,
output wire [DEST_WIDTH-1:0] output_axis_tdest,
output wire [USER_WIDTH-1:0] output_axis_tuser,
/* /*
* Status * Status
@ -64,19 +82,26 @@ module axis_frame_fifo #
output wire good_frame output wire good_frame
); );
localparam KEEP_OFFSET = DATA_WIDTH;
localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
localparam ID_OFFSET = LAST_OFFSET + 1;
localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next; reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next; reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next;
reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}}; reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next; reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}}; reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [DATA_WIDTH+1-1:0] mem[(2**ADDR_WIDTH)-1:0]; reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+1-1:0] mem_read_data_reg = {DATA_WIDTH+1{1'b0}}; reg [WIDTH-1:0] mem_read_data_reg;
reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next; reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
wire [DATA_WIDTH+1-1:0] mem_write_data;
reg [DATA_WIDTH+1-1:0] output_data_reg = {DATA_WIDTH+1{1'b0}}; wire [WIDTH-1:0] input_axis;
reg [WIDTH-1:0] output_axis_reg;
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next; reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
// full when first MSB different but rest same // full when first MSB different but rest same
@ -100,10 +125,23 @@ reg good_frame_reg = 1'b0, good_frame_next;
assign input_axis_tready = (~full | DROP_WHEN_FULL); assign input_axis_tready = (~full | DROP_WHEN_FULL);
generate
assign input_axis[DATA_WIDTH-1:0] = input_axis_tdata;
if (KEEP_ENABLE) assign input_axis[KEEP_OFFSET +: KEEP_WIDTH] = input_axis_tkeep;
assign input_axis[LAST_OFFSET] = input_axis_tlast;
if (ID_ENABLE) assign input_axis[ID_OFFSET +: ID_WIDTH] = input_axis_tid;
if (DEST_ENABLE) assign input_axis[DEST_OFFSET +: DEST_WIDTH] = input_axis_tdest;
if (USER_ENABLE) assign input_axis[USER_OFFSET +: USER_WIDTH] = input_axis_tuser;
endgenerate
assign output_axis_tvalid = output_axis_tvalid_reg; assign output_axis_tvalid = output_axis_tvalid_reg;
assign mem_write_data = {input_axis_tlast, input_axis_tdata}; assign output_axis_tdata = output_axis_reg[DATA_WIDTH-1:0];
assign {output_axis_tlast, output_axis_tdata} = output_data_reg; assign output_axis_tkeep = KEEP_ENABLE ? output_axis_reg[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
assign output_axis_tlast = output_axis_reg[LAST_OFFSET];
assign output_axis_tid = ID_ENABLE ? output_axis_reg[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}};
assign output_axis_tdest = DEST_ENABLE ? output_axis_reg[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
assign output_axis_tuser = USER_ENABLE ? output_axis_reg[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
assign overflow = overflow_reg; assign overflow = overflow_reg;
assign bad_frame = bad_frame_reg; assign bad_frame = bad_frame_reg;
@ -140,7 +178,7 @@ always @* begin
wr_ptr_cur_next = wr_ptr_cur_reg + 1; wr_ptr_cur_next = wr_ptr_cur_reg + 1;
if (input_axis_tlast) begin if (input_axis_tlast) begin
// end of frame // end of frame
if (input_axis_tuser) begin if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & input_axis_tuser == USER_BAD_FRAME_VALUE)) begin
// bad packet, reset write pointer // bad packet, reset write pointer
wr_ptr_cur_next = wr_ptr_reg; wr_ptr_cur_next = wr_ptr_reg;
bad_frame_next = 1'b1; bad_frame_next = 1'b1;
@ -177,7 +215,7 @@ always @(posedge clk) begin
wr_addr_reg <= wr_ptr_cur_next; wr_addr_reg <= wr_ptr_cur_next;
if (write) begin if (write) begin
mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data; mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= input_axis;
end end
end end
@ -239,7 +277,7 @@ always @(posedge clk) begin
end end
if (store_output) begin if (store_output) begin
output_data_reg <= mem_read_data_reg; output_axis_reg <= mem_read_data_reg;
end end
end end

249
lib/axis/rtl/axis_frame_fifo_64.v
View File

@ -1,249 +0,0 @@
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream frame FIFO (64 bit datapath)
*/
module axis_frame_fifo_64 #
(
parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter DROP_WHEN_FULL = 0
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
/*
* Status
*/
output wire overflow,
output wire bad_frame,
output wire good_frame
);
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next;
reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [DATA_WIDTH+KEEP_WIDTH+1-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+KEEP_WIDTH+1-1:0] mem_read_data_reg = {DATA_WIDTH+KEEP_WIDTH+1{1'b0}};
reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
wire [DATA_WIDTH+KEEP_WIDTH+1-1:0] mem_write_data;
reg [DATA_WIDTH+KEEP_WIDTH+1-1:0] output_data_reg = {DATA_WIDTH+KEEP_WIDTH+1{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
// full when first MSB different but rest same
wire full = ((wr_ptr_reg[ADDR_WIDTH] != rd_ptr_reg[ADDR_WIDTH]) &&
(wr_ptr_reg[ADDR_WIDTH-1:0] == rd_ptr_reg[ADDR_WIDTH-1:0]));
// empty when pointers match exactly
wire empty = wr_ptr_reg == rd_ptr_reg;
// overflow within packet
wire full_cur = ((wr_ptr_reg[ADDR_WIDTH] != wr_ptr_cur_reg[ADDR_WIDTH]) &&
(wr_ptr_reg[ADDR_WIDTH-1:0] == wr_ptr_cur_reg[ADDR_WIDTH-1:0]));
// control signals
reg write;
reg read;
reg store_output;
reg drop_frame_reg = 1'b0, drop_frame_next;
reg overflow_reg = 1'b0, overflow_next;
reg bad_frame_reg = 1'b0, bad_frame_next;
reg good_frame_reg = 1'b0, good_frame_next;
assign input_axis_tready = (~full | DROP_WHEN_FULL);
assign output_axis_tvalid = output_axis_tvalid_reg;
assign mem_write_data = {input_axis_tlast, input_axis_tkeep, input_axis_tdata};
assign {output_axis_tlast, output_axis_tkeep, output_axis_tdata} = output_data_reg;
assign overflow = overflow_reg;
assign bad_frame = bad_frame_reg;
assign good_frame = good_frame_reg;
// Write logic
always @* begin
write = 1'b0;
drop_frame_next = 1'b0;
overflow_next = 1'b0;
bad_frame_next = 1'b0;
good_frame_next = 1'b0;
wr_ptr_next = wr_ptr_reg;
wr_ptr_cur_next = wr_ptr_cur_reg;
if (input_axis_tvalid) begin
// input data valid
if (~full | DROP_WHEN_FULL) begin
// not full, perform write
if (full | full_cur | drop_frame_reg) begin
// full, packet overflow, or currently dropping frame
// drop frame
drop_frame_next = 1'b1;
if (input_axis_tlast) begin
// end of frame, reset write pointer
wr_ptr_cur_next = wr_ptr_reg;
drop_frame_next = 1'b0;
overflow_next = 1'b1;
end
end else begin
write = 1'b1;
wr_ptr_cur_next = wr_ptr_cur_reg + 1;
if (input_axis_tlast) begin
// end of frame
if (input_axis_tuser) begin
// bad packet, reset write pointer
wr_ptr_cur_next = wr_ptr_reg;
bad_frame_next = 1'b1;
end else begin
// good packet, update write pointer
wr_ptr_next = wr_ptr_cur_reg + 1;
good_frame_next = 1'b1;
end
end
end
end
end
end
always @(posedge clk) begin
if (rst) begin
wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}};
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
end else begin
wr_ptr_reg <= wr_ptr_next;
wr_ptr_cur_reg <= wr_ptr_cur_next;
drop_frame_reg <= drop_frame_next;
overflow_reg <= overflow_next;
bad_frame_reg <= bad_frame_next;
good_frame_reg <= good_frame_next;
end
wr_addr_reg <= wr_ptr_cur_next;
if (write) begin
mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
// Read logic
always @* begin
read = 1'b0;
rd_ptr_next = rd_ptr_reg;
mem_read_data_valid_next = mem_read_data_valid_reg;
if (store_output | ~mem_read_data_valid_reg) begin
// output data not valid OR currently being transferred
if (~empty) begin
// not empty, perform read
read = 1'b1;
mem_read_data_valid_next = 1'b1;
rd_ptr_next = rd_ptr_reg + 1;
end else begin
// empty, invalidate
mem_read_data_valid_next = 1'b0;
end
end
end
always @(posedge clk) begin
if (rst) begin
rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
mem_read_data_valid_reg <= 1'b0;
end else begin
rd_ptr_reg <= rd_ptr_next;
mem_read_data_valid_reg <= mem_read_data_valid_next;
end
rd_addr_reg <= rd_ptr_next;
if (read) begin
mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]];
end
end
// Output register
always @* begin
store_output = 1'b0;
output_axis_tvalid_next = output_axis_tvalid_reg;
if (output_axis_tready | ~output_axis_tvalid) begin
store_output = 1'b1;
output_axis_tvalid_next = mem_read_data_valid_reg;
end
end
always @(posedge clk) begin
if (rst) begin
output_axis_tvalid_reg <= 1'b0;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
end
if (store_output) begin
output_data_reg <= mem_read_data_reg;
end
end
endmodule

16
lib/axis/rtl/axis_frame_join.py
View File

@ -33,11 +33,11 @@ def generate(ports=4, name=None, output=None):
print("Opening file '{0}'...".format(output)) print("Opening file '{0}'...".format(output))
output_file = open(output, 'w') output_file = open(output, 'w')
print("Generating {0} port AXI Stream frame joiner {1}...".format(ports, name)) print("Generating {0} port AXI Stream frame joiner {1}...".format(ports, name))
select_width = int(math.ceil(math.log(ports, 2))) select_width = int(math.ceil(math.log(ports, 2)))
t = Template(u"""/* t = Template(u"""/*
Copyright (c) 2014-2017 Alex Forencich Copyright (c) 2014-2017 Alex Forencich
@ -192,7 +192,7 @@ always @* begin
// next cycle if started will send data, so enable input // next cycle if started will send data, so enable input
input_0_axis_tready_next = output_axis_tready_int_early; input_0_axis_tready_next = output_axis_tready_int_early;
end end
if (input_0_axis_tvalid) begin if (input_0_axis_tvalid) begin
// input 0 valid; start transferring data // input 0 valid; start transferring data
if (TAG_ENABLE) begin if (TAG_ENABLE) begin
@ -284,7 +284,7 @@ always @* begin
end end
end else begin end else begin
state_next = STATE_TRANSFER; state_next = STATE_TRANSFER;
end end
end end
endcase endcase
end end
@ -347,7 +347,7 @@ always @* begin
store_axis_int_to_output = 1'b0; store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0; store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0; store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
// input is ready // input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin if (output_axis_tready | ~output_axis_tvalid_reg) begin
@ -399,14 +399,14 @@ end
endmodule endmodule
""") """)
output_file.write(t.render( output_file.write(t.render(
n=ports, n=ports,
w=select_width, w=select_width,
name=name, name=name,
ports=range(ports) ports=range(ports)
)) ))
print("Done") print("Done")
if __name__ == "__main__": if __name__ == "__main__":

6
lib/axis/rtl/axis_frame_join_4.v
View File

@ -191,7 +191,7 @@ always @* begin
// next cycle if started will send data, so enable input // next cycle if started will send data, so enable input
input_0_axis_tready_next = output_axis_tready_int_early; input_0_axis_tready_next = output_axis_tready_int_early;
end end
if (input_0_axis_tvalid) begin if (input_0_axis_tvalid) begin
// input 0 valid; start transferring data // input 0 valid; start transferring data
if (TAG_ENABLE) begin if (TAG_ENABLE) begin
@ -286,7 +286,7 @@ always @* begin
end end
end else begin end else begin
state_next = STATE_TRANSFER; state_next = STATE_TRANSFER;
end end
end end
endcase endcase
end end
@ -352,7 +352,7 @@ always @* begin
store_axis_int_to_output = 1'b0; store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0; store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0; store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
// input is ready // input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin if (output_axis_tready | ~output_axis_tvalid_reg) begin

112
lib/axis/rtl/axis_frame_length_adjust.v
View File

@ -31,8 +31,15 @@ THE SOFTWARE.
*/ */
module axis_frame_length_adjust # module axis_frame_length_adjust #
( (
parameter DATA_WIDTH = 1, parameter DATA_WIDTH = 8,
parameter KEEP_WIDTH = (DATA_WIDTH/8) parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
) )
( (
input wire clk, input wire clk,
@ -46,7 +53,9 @@ module axis_frame_length_adjust #
input wire input_axis_tvalid, input wire input_axis_tvalid,
output wire input_axis_tready, output wire input_axis_tready,
input wire input_axis_tlast, input wire input_axis_tlast,
input wire input_axis_tuser, input wire [ID_WIDTH-1:0] input_axis_tid,
input wire [DEST_WIDTH-1:0] input_axis_tdest,
input wire [USER_WIDTH-1:0] input_axis_tuser,
/* /*
* AXI output * AXI output
@ -56,7 +65,9 @@ module axis_frame_length_adjust #
output wire output_axis_tvalid, output wire output_axis_tvalid,
input wire output_axis_tready, input wire output_axis_tready,
output wire output_axis_tlast, output wire output_axis_tlast,
output wire output_axis_tuser, output wire [ID_WIDTH-1:0] output_axis_tid,
output wire [DEST_WIDTH-1:0] output_axis_tdest,
output wire [USER_WIDTH-1:0] output_axis_tuser,
/* /*
* Status * Status
@ -106,8 +117,9 @@ reg [15:0] long_counter_reg = 16'd0, long_counter_next = 16'd0;
reg [DATA_WIDTH-1:0] last_word_data_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] last_word_data_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] last_word_keep_reg = {KEEP_WIDTH{1'b0}}; reg [KEEP_WIDTH-1:0] last_word_keep_reg = {KEEP_WIDTH{1'b0}};
reg [ID_WIDTH-1:0] last_word_id_reg = {ID_WIDTH{1'b0}};
reg last_cycle_tuser_reg = 1'b0, last_cycle_tuser_next; reg [DEST_WIDTH-1:0] last_word_dest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] last_word_user_reg = {USER_WIDTH{1'b0}};
reg status_valid_reg = 1'b0, status_valid_next; reg status_valid_reg = 1'b0, status_valid_next;
reg status_frame_pad_reg = 1'b0, status_frame_pad_next; reg status_frame_pad_reg = 1'b0, status_frame_pad_next;
@ -116,13 +128,15 @@ reg [15:0] status_frame_length_reg = 16'd0, status_frame_length_next;
reg [15:0] status_frame_original_length_reg = 16'd0, status_frame_original_length_next; reg [15:0] status_frame_original_length_reg = 16'd0, status_frame_original_length_next;
// internal datapath // internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int; reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_int; reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tvalid_int; reg output_axis_tvalid_int;
reg output_axis_tready_int_reg = 1'b0; reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tlast_int; reg output_axis_tlast_int;
reg output_axis_tuser_int; reg [ID_WIDTH-1:0] output_axis_tid_int;
wire output_axis_tready_int_early; reg [DEST_WIDTH-1:0] output_axis_tdest_int;
reg [USER_WIDTH-1:0] output_axis_tuser_int;
wire output_axis_tready_int_early;
reg input_axis_tready_reg = 1'b0, input_axis_tready_next; reg input_axis_tready_reg = 1'b0, input_axis_tready_next;
assign input_axis_tready = input_axis_tready_reg; assign input_axis_tready = input_axis_tready_reg;
@ -145,16 +159,16 @@ always @* begin
short_counter_next = short_counter_reg; short_counter_next = short_counter_reg;
long_counter_next = long_counter_reg; long_counter_next = long_counter_reg;
output_axis_tdata_int = {DATA_WIDTH{1'b0}}; output_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_axis_tkeep_int = {KEEP_WIDTH{1'b0}}; output_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
output_axis_tvalid_int = 1'b0; output_axis_tvalid_int = 1'b0;
output_axis_tlast_int = 1'b0; output_axis_tlast_int = 1'b0;
output_axis_tuser_int = 1'b0; output_axis_tid_int = {ID_WIDTH{1'b0}};
output_axis_tdest_int = {DEST_WIDTH{1'b0}};
output_axis_tuser_int = {USER_WIDTH{1'b0}};
input_axis_tready_next = 1'b0; input_axis_tready_next = 1'b0;
last_cycle_tuser_next = last_cycle_tuser_reg;
status_valid_next = status_valid_reg & ~status_ready; status_valid_next = status_valid_reg & ~status_ready;
status_frame_pad_next = status_frame_pad_reg; status_frame_pad_next = status_frame_pad_reg;
status_frame_truncate_next = status_frame_truncate_reg; status_frame_truncate_next = status_frame_truncate_reg;
@ -171,6 +185,8 @@ always @* begin
output_axis_tkeep_int = input_axis_tkeep; output_axis_tkeep_int = input_axis_tkeep;
output_axis_tvalid_int = input_axis_tvalid; output_axis_tvalid_int = input_axis_tvalid;
output_axis_tlast_int = input_axis_tlast; output_axis_tlast_int = input_axis_tlast;
output_axis_tid_int = input_axis_tid;
output_axis_tdest_int = input_axis_tdest;
output_axis_tuser_int = input_axis_tuser; output_axis_tuser_int = input_axis_tuser;
short_counter_next = length_min; short_counter_next = length_min;
@ -224,8 +240,7 @@ always @* begin
input_axis_tready_next = 1'b0; input_axis_tready_next = 1'b0;
output_axis_tkeep_int = {KEEP_WIDTH{1'b1}}; output_axis_tkeep_int = {KEEP_WIDTH{1'b1}};
output_axis_tlast_int = 1'b0; output_axis_tlast_int = 1'b0;
output_axis_tuser_int = 1'b0; store_last_word = 1'b1;
last_cycle_tuser_next = input_axis_tuser;
state_next = STATE_PAD; state_next = STATE_PAD;
end else begin end else begin
status_valid_next = 1'b1; status_valid_next = 1'b1;
@ -268,6 +283,8 @@ always @* begin
output_axis_tkeep_int = input_axis_tkeep; output_axis_tkeep_int = input_axis_tkeep;
output_axis_tvalid_int = input_axis_tvalid; output_axis_tvalid_int = input_axis_tvalid;
output_axis_tlast_int = input_axis_tlast; output_axis_tlast_int = input_axis_tlast;
output_axis_tid_int = input_axis_tid;
output_axis_tdest_int = input_axis_tdest;
output_axis_tuser_int = input_axis_tuser; output_axis_tuser_int = input_axis_tuser;
if (input_axis_tready & input_axis_tvalid) begin if (input_axis_tready & input_axis_tvalid) begin
@ -318,8 +335,7 @@ always @* begin
input_axis_tready_next = 1'b0; input_axis_tready_next = 1'b0;
output_axis_tkeep_int = {KEEP_WIDTH{1'b1}}; output_axis_tkeep_int = {KEEP_WIDTH{1'b1}};
output_axis_tlast_int = 1'b0; output_axis_tlast_int = 1'b0;
output_axis_tuser_int = 1'b0; store_last_word = 1'b1;
last_cycle_tuser_next = input_axis_tuser;
state_next = STATE_PAD; state_next = STATE_PAD;
end else begin end else begin
status_valid_next = 1'b1; status_valid_next = 1'b1;
@ -361,7 +377,9 @@ always @* begin
output_axis_tkeep_int = {KEEP_WIDTH{1'b1}}; output_axis_tkeep_int = {KEEP_WIDTH{1'b1}};
output_axis_tvalid_int = 1'b1; output_axis_tvalid_int = 1'b1;
output_axis_tlast_int = 1'b0; output_axis_tlast_int = 1'b0;
output_axis_tuser_int = 1'b0; output_axis_tid_int = last_word_id_reg;
output_axis_tdest_int = last_word_dest_reg;
output_axis_tuser_int = last_word_user_reg;
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
frame_ptr_next = frame_ptr_reg + KEEP_WIDTH; frame_ptr_next = frame_ptr_reg + KEEP_WIDTH;
@ -386,7 +404,6 @@ always @* begin
input_axis_tready_next = output_axis_tready_int_early & status_ready; input_axis_tready_next = output_axis_tready_int_early & status_ready;
output_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-short_counter_reg); output_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-short_counter_reg);
output_axis_tlast_int = 1'b1; output_axis_tlast_int = 1'b1;
output_axis_tuser_int = last_cycle_tuser_reg;
frame_ptr_next = 16'd0; frame_ptr_next = 16'd0;
short_counter_next = length_min; short_counter_next = length_min;
long_counter_next = length_max; long_counter_next = length_max;
@ -406,6 +423,8 @@ always @* begin
output_axis_tkeep_int = last_word_keep_reg; output_axis_tkeep_int = last_word_keep_reg;
output_axis_tvalid_int = input_axis_tvalid & input_axis_tlast; output_axis_tvalid_int = input_axis_tvalid & input_axis_tlast;
output_axis_tlast_int = input_axis_tlast; output_axis_tlast_int = input_axis_tlast;
output_axis_tid_int = last_word_id_reg;
output_axis_tdest_int = last_word_dest_reg;
output_axis_tuser_int = input_axis_tuser; output_axis_tuser_int = input_axis_tuser;
if (input_axis_tready & input_axis_tvalid) begin if (input_axis_tready & input_axis_tvalid) begin
@ -458,8 +477,6 @@ always @(posedge clk) begin
status_valid_reg <= status_valid_next; status_valid_reg <= status_valid_next;
end end
last_cycle_tuser_reg <= last_cycle_tuser_next;
status_frame_pad_reg <= status_frame_pad_next; status_frame_pad_reg <= status_frame_pad_next;
status_frame_truncate_reg <= status_frame_truncate_next; status_frame_truncate_reg <= status_frame_truncate_next;
status_frame_length_reg <= status_frame_length_next; status_frame_length_reg <= status_frame_length_next;
@ -468,32 +485,41 @@ always @(posedge clk) begin
if (store_last_word) begin if (store_last_word) begin
last_word_data_reg <= output_axis_tdata_int; last_word_data_reg <= output_axis_tdata_int;
last_word_keep_reg <= output_axis_tkeep_int; last_word_keep_reg <= output_axis_tkeep_int;
last_word_id_reg <= output_axis_tid_int;
last_word_dest_reg <= output_axis_tdest_int;
last_word_user_reg <= output_axis_tuser_int;
end end
end end
// output datapath logic // output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next; reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0; reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] output_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] output_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next; reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0; reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] temp_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control // datapath control
reg store_axis_int_to_output; reg store_axis_int_to_output;
reg store_axis_int_to_temp; reg store_axis_int_to_temp;
reg store_axis_temp_to_output; reg store_axis_temp_to_output;
assign output_axis_tdata = output_axis_tdata_reg; assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = output_axis_tkeep_reg; assign output_axis_tkeep = KEEP_ENABLE ? output_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_axis_tvalid = output_axis_tvalid_reg; assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg; assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg; assign output_axis_tid = ID_ENABLE ? output_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_axis_tdest = DEST_ENABLE ? output_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign output_axis_tuser = USER_ENABLE ? output_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int)); assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
@ -506,7 +532,7 @@ always @* begin
store_axis_int_to_output = 1'b0; store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0; store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0; store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
// input is ready // input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin if (output_axis_tready | ~output_axis_tvalid_reg) begin
@ -542,11 +568,15 @@ always @(posedge clk) begin
output_axis_tdata_reg <= output_axis_tdata_int; output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int; output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tlast_reg <= output_axis_tlast_int; output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tid_reg <= output_axis_tid_int;
output_axis_tdest_reg <= output_axis_tdest_int;
output_axis_tuser_reg <= output_axis_tuser_int; output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg; output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg; output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg; output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tid_reg <= temp_axis_tid_reg;
output_axis_tdest_reg <= temp_axis_tdest_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg; output_axis_tuser_reg <= temp_axis_tuser_reg;
end end
@ -554,6 +584,8 @@ always @(posedge clk) begin
temp_axis_tdata_reg <= output_axis_tdata_int; temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int; temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tlast_reg <= output_axis_tlast_int; temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tid_reg <= output_axis_tid_int;
temp_axis_tdest_reg <= output_axis_tdest_int;
temp_axis_tuser_reg <= output_axis_tuser_int; temp_axis_tuser_reg <= output_axis_tuser_int;
end end
end end

71
lib/axis/rtl/axis_frame_length_adjust_fifo.v
View File

@ -32,6 +32,14 @@ THE SOFTWARE.
module axis_frame_length_adjust_fifo # module axis_frame_length_adjust_fifo #
( (
parameter DATA_WIDTH = 8, parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
parameter FRAME_FIFO_ADDR_WIDTH = 12, parameter FRAME_FIFO_ADDR_WIDTH = 12,
parameter HEADER_FIFO_ADDR_WIDTH = 3 parameter HEADER_FIFO_ADDR_WIDTH = 3
) )
@ -43,10 +51,13 @@ module axis_frame_length_adjust_fifo #
* AXI input * AXI input
*/ */
input wire [DATA_WIDTH-1:0] input_axis_tdata, input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid, input wire input_axis_tvalid,
output wire input_axis_tready, output wire input_axis_tready,
input wire input_axis_tlast, input wire input_axis_tlast,
input wire input_axis_tuser, input wire [ID_WIDTH-1:0] input_axis_tid,
input wire [DEST_WIDTH-1:0] input_axis_tdest,
input wire [USER_WIDTH-1:0] input_axis_tuser,
/* /*
* AXI output * AXI output
@ -58,10 +69,13 @@ module axis_frame_length_adjust_fifo #
output wire [15:0] output_axis_hdr_length, output wire [15:0] output_axis_hdr_length,
output wire [15:0] output_axis_hdr_original_length, output wire [15:0] output_axis_hdr_original_length,
output wire [DATA_WIDTH-1:0] output_axis_tdata, output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid, output wire output_axis_tvalid,
input wire output_axis_tready, input wire output_axis_tready,
output wire output_axis_tlast, output wire output_axis_tlast,
output wire output_axis_tuser, output wire [ID_WIDTH-1:0] output_axis_tid,
output wire [DEST_WIDTH-1:0] output_axis_tdest,
output wire [USER_WIDTH-1:0] output_axis_tuser,
/* /*
* Configuration * Configuration
@ -71,10 +85,13 @@ module axis_frame_length_adjust_fifo #
); );
wire [DATA_WIDTH-1:0] fifo_axis_tdata; wire [DATA_WIDTH-1:0] fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] fifo_axis_tkeep;
wire fifo_axis_tvalid; wire fifo_axis_tvalid;
wire fifo_axis_tready; wire fifo_axis_tready;
wire fifo_axis_tlast; wire fifo_axis_tlast;
wire fifo_axis_tuser; wire [ID_WIDTH-1:0] fifo_axis_tid;
wire [DEST_WIDTH-1:0] fifo_axis_tdest;
wire [USER_WIDTH-1:0] fifo_axis_tuser;
wire status_valid; wire status_valid;
wire status_ready; wire status_ready;
@ -85,24 +102,35 @@ wire [15:0] status_frame_original_length;
axis_frame_length_adjust #( axis_frame_length_adjust #(
.DATA_WIDTH(DATA_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(1) .KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) )
axis_frame_length_adjust_inst ( axis_frame_length_adjust_inst (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
// AXI input // AXI input
.input_axis_tdata(input_axis_tdata), .input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(1), .input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid), .input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready), .input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast), .input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser), .input_axis_tuser(input_axis_tuser),
// AXI output // AXI output
.output_axis_tdata(fifo_axis_tdata), .output_axis_tdata(fifo_axis_tdata),
.output_axis_tkeep(), .output_axis_tkeep(fifo_axis_tkeep),
.output_axis_tvalid(fifo_axis_tvalid), .output_axis_tvalid(fifo_axis_tvalid),
.output_axis_tready(fifo_axis_tready), .output_axis_tready(fifo_axis_tready),
.output_axis_tlast(fifo_axis_tlast), .output_axis_tlast(fifo_axis_tlast),
.output_axis_tid(fifo_axis_tid),
.output_axis_tdest(fifo_axis_tdest),
.output_axis_tuser(fifo_axis_tuser), .output_axis_tuser(fifo_axis_tuser),
// Status // Status
.status_valid(status_valid), .status_valid(status_valid),
@ -118,45 +146,70 @@ axis_frame_length_adjust_inst (
axis_fifo #( axis_fifo #(
.ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH), .ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH) .DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) )
frame_fifo_inst ( frame_fifo_inst (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
// AXI input // AXI input
.input_axis_tdata(fifo_axis_tdata), .input_axis_tdata(fifo_axis_tdata),
.input_axis_tkeep(fifo_axis_tkeep),
.input_axis_tvalid(fifo_axis_tvalid), .input_axis_tvalid(fifo_axis_tvalid),
.input_axis_tready(fifo_axis_tready), .input_axis_tready(fifo_axis_tready),
.input_axis_tlast(fifo_axis_tlast), .input_axis_tlast(fifo_axis_tlast),
.input_axis_tid(fifo_axis_tid),
.input_axis_tdest(fifo_axis_tdest),
.input_axis_tuser(fifo_axis_tuser), .input_axis_tuser(fifo_axis_tuser),
// AXI output // AXI output
.output_axis_tdata(output_axis_tdata), .output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser) .output_axis_tuser(output_axis_tuser)
); );
axis_fifo #( axis_fifo #(
.ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH), .ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH),
.DATA_WIDTH(1+1+16+16) .DATA_WIDTH(1+1+16+16),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0)
) )
header_fifo_inst ( header_fifo_inst (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
// AXI input // AXI input
.input_axis_tdata({status_frame_pad, status_frame_truncate, status_frame_length, status_frame_original_length}), .input_axis_tdata({status_frame_pad, status_frame_truncate, status_frame_length, status_frame_original_length}),
.input_axis_tkeep(0),
.input_axis_tvalid(status_valid), .input_axis_tvalid(status_valid),
.input_axis_tready(status_ready), .input_axis_tready(status_ready),
.input_axis_tlast(0), .input_axis_tlast(0),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(0), .input_axis_tuser(0),
// AXI output // AXI output
.output_axis_tdata({output_axis_hdr_pad, output_axis_hdr_truncate, output_axis_hdr_length, output_axis_hdr_original_length}), .output_axis_tdata({output_axis_hdr_pad, output_axis_hdr_truncate, output_axis_hdr_length, output_axis_hdr_original_length}),
.output_axis_tkeep(),
.output_axis_tvalid(output_axis_hdr_valid), .output_axis_tvalid(output_axis_hdr_valid),
.output_axis_tready(output_axis_hdr_ready), .output_axis_tready(output_axis_hdr_ready),
.output_axis_tlast(), .output_axis_tlast(),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser() .output_axis_tuser()
); );
endmodule endmodule

169
lib/axis/rtl/axis_frame_length_adjust_fifo_64.v
View File

@ -1,169 +0,0 @@
/*
Copyright (c) 2015-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream frame length adjuster with FIFO (64 bit datapath)
*/
module axis_frame_length_adjust_fifo_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter FRAME_FIFO_ADDR_WIDTH = 12,
parameter HEADER_FIFO_ADDR_WIDTH = 3
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire output_axis_hdr_valid,
input wire output_axis_hdr_ready,
output wire output_axis_hdr_pad,
output wire output_axis_hdr_truncate,
output wire [15:0] output_axis_hdr_length,
output wire [15:0] output_axis_hdr_original_length,
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Configuration
*/
input wire [15:0] length_min,
input wire [15:0] length_max
);
wire [DATA_WIDTH-1:0] fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] fifo_axis_tkeep;
wire fifo_axis_tvalid;
wire fifo_axis_tready;
wire fifo_axis_tlast;
wire fifo_axis_tuser;
wire status_valid;
wire status_ready;
wire status_frame_pad;
wire status_frame_truncate;
wire [15:0] status_frame_length;
wire [15:0] status_frame_original_length;
axis_frame_length_adjust #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
)
axis_frame_length_adjust_inst (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(fifo_axis_tdata),
.output_axis_tkeep(fifo_axis_tkeep),
.output_axis_tvalid(fifo_axis_tvalid),
.output_axis_tready(fifo_axis_tready),
.output_axis_tlast(fifo_axis_tlast),
.output_axis_tuser(fifo_axis_tuser),
// Status
.status_valid(status_valid),
.status_ready(status_ready),
.status_frame_pad(status_frame_pad),
.status_frame_truncate(status_frame_truncate),
.status_frame_length(status_frame_length),
.status_frame_original_length(status_frame_original_length),
// Configuration
.length_min(length_min),
.length_max(length_max)
);
axis_fifo_64 #(
.ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
)
frame_fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(fifo_axis_tdata),
.input_axis_tkeep(fifo_axis_tkeep),
.input_axis_tvalid(fifo_axis_tvalid),
.input_axis_tready(fifo_axis_tready),
.input_axis_tlast(fifo_axis_tlast),
.input_axis_tuser(fifo_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser)
);
axis_fifo #(
.ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH),
.DATA_WIDTH(1+1+16+16)
)
header_fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata({status_frame_pad, status_frame_truncate, status_frame_length, status_frame_original_length}),
.input_axis_tvalid(status_valid),
.input_axis_tready(status_ready),
.input_axis_tlast(0),
.input_axis_tuser(0),
// AXI output
.output_axis_tdata({output_axis_hdr_pad, output_axis_hdr_truncate, output_axis_hdr_length, output_axis_hdr_original_length}),
.output_axis_tvalid(output_axis_hdr_valid),
.output_axis_tready(output_axis_hdr_ready),
.output_axis_tlast(),
.output_axis_tuser()
);
endmodule

4
lib/axis/rtl/axis_ll_bridge.v
View File

@ -36,7 +36,7 @@ module axis_ll_bridge #
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
/* /*
* AXI input * AXI input
*/ */
@ -44,7 +44,7 @@ module axis_ll_bridge #
input wire axis_tvalid, input wire axis_tvalid,
output wire axis_tready, output wire axis_tready,
input wire axis_tlast, input wire axis_tlast,
/* /*
* LocalLink output * LocalLink output
*/ */

117
lib/axis/rtl/axis_mux.py
View File

@ -71,30 +71,44 @@ THE SOFTWARE.
*/ */
module {{name}} # module {{name}} #
( (
parameter DATA_WIDTH = 8 parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
) )
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
/* /*
* AXI inputs * AXI inputs
*/ */
{%- for p in ports %} {%- for p in ports %}
input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata, input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep,
input wire input_{{p}}_axis_tvalid, input wire input_{{p}}_axis_tvalid,
output wire input_{{p}}_axis_tready, output wire input_{{p}}_axis_tready,
input wire input_{{p}}_axis_tlast, input wire input_{{p}}_axis_tlast,
input wire input_{{p}}_axis_tuser, input wire [ID_WIDTH-1:0] input_{{p}}_axis_tid,
input wire [DEST_WIDTH-1:0] input_{{p}}_axis_tdest,
input wire [USER_WIDTH-1:0] input_{{p}}_axis_tuser,
{% endfor %} {% endfor %}
/* /*
* AXI output * AXI output
*/ */
output wire [DATA_WIDTH-1:0] output_axis_tdata, output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid, output wire output_axis_tvalid,
input wire output_axis_tready, input wire output_axis_tready,
output wire output_axis_tlast, output wire output_axis_tlast,
output wire output_axis_tuser, output wire [ID_WIDTH-1:0] output_axis_tid,
output wire [DEST_WIDTH-1:0] output_axis_tdest,
output wire [USER_WIDTH-1:0] output_axis_tuser,
/* /*
* Control * Control
@ -110,12 +124,15 @@ reg input_{{p}}_axis_tready_reg = 1'b0, input_{{p}}_axis_tready_next;
{%- endfor %} {%- endfor %}
// internal datapath // internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int; reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg output_axis_tvalid_int; reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tready_int_reg = 1'b0; reg output_axis_tvalid_int;
reg output_axis_tlast_int; reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tuser_int; reg output_axis_tlast_int;
wire output_axis_tready_int_early; reg [ID_WIDTH-1:0] output_axis_tid_int;
reg [DEST_WIDTH-1:0] output_axis_tdest_int;
reg [USER_WIDTH-1:0] output_axis_tuser_int;
wire output_axis_tready_int_early;
{% for p in ports %} {% for p in ports %}
assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg; assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg;
{%- endfor %} {%- endfor %}
@ -133,27 +150,36 @@ end
// mux for incoming packet // mux for incoming packet
reg [DATA_WIDTH-1:0] current_input_tdata; reg [DATA_WIDTH-1:0] current_input_tdata;
reg current_input_tvalid; reg [KEEP_WIDTH-1:0] current_input_tkeep;
reg current_input_tready; reg current_input_tvalid;
reg current_input_tlast; reg current_input_tready;
reg current_input_tuser; reg current_input_tlast;
reg [ID_WIDTH-1:0] current_input_tid;
reg [DEST_WIDTH-1:0] current_input_tdest;
reg [USER_WIDTH-1:0] current_input_tuser;
always @* begin always @* begin
case (select_reg) case (select_reg)
{%- for p in ports %} {%- for p in ports %}
{{w}}'d{{p}}: begin {{w}}'d{{p}}: begin
current_input_tdata = input_{{p}}_axis_tdata; current_input_tdata = input_{{p}}_axis_tdata;
current_input_tkeep = input_{{p}}_axis_tkeep;
current_input_tvalid = input_{{p}}_axis_tvalid; current_input_tvalid = input_{{p}}_axis_tvalid;
current_input_tready = input_{{p}}_axis_tready; current_input_tready = input_{{p}}_axis_tready;
current_input_tlast = input_{{p}}_axis_tlast; current_input_tlast = input_{{p}}_axis_tlast;
current_input_tuser = input_{{p}}_axis_tuser; current_input_tid = input_{{p}}_axis_tid;
current_input_tdest = input_{{p}}_axis_tdest;
current_input_tuser = input_{{p}}_axis_tuser;
end end
{%- endfor %} {%- endfor %}
default: begin default: begin
current_input_tdata = {DATA_WIDTH{1'b0}}; current_input_tdata = {DATA_WIDTH{1'b0}};
current_input_tkeep = {KEEP_WIDTH{1'b0}};
current_input_tvalid = 1'b0; current_input_tvalid = 1'b0;
current_input_tready = 1'b0; current_input_tready = 1'b0;
current_input_tlast = 1'b0; current_input_tlast = 1'b0;
current_input_tuser = 1'b0; current_input_tid = {ID_WIDTH{1'b0}};
current_input_tdest = {DEST_WIDTH{1'b0}};
current_input_tuser = {USER_WIDTH{1'b0}};
end end
endcase endcase
end end
@ -186,10 +212,13 @@ always @* begin
endcase endcase
// pass through selected packet data // pass through selected packet data
output_axis_tdata_int = current_input_tdata; output_axis_tdata_int = current_input_tdata;
output_axis_tkeep_int = current_input_tkeep;
output_axis_tvalid_int = current_input_tvalid & current_input_tready & frame_reg; output_axis_tvalid_int = current_input_tvalid & current_input_tready & frame_reg;
output_axis_tlast_int = current_input_tlast; output_axis_tlast_int = current_input_tlast;
output_axis_tuser_int = current_input_tuser; output_axis_tid_int = current_input_tid;
output_axis_tdest_int = current_input_tdest;
output_axis_tuser_int = current_input_tuser;
end end
always @(posedge clk) begin always @(posedge clk) begin
@ -209,25 +238,34 @@ always @(posedge clk) begin
end end
// output datapath logic // output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next; reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0; reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] output_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] output_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next; reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0; reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] temp_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control // datapath control
reg store_axis_int_to_output; reg store_axis_int_to_output;
reg store_axis_int_to_temp; reg store_axis_int_to_temp;
reg store_axis_temp_to_output; reg store_axis_temp_to_output;
assign output_axis_tdata = output_axis_tdata_reg; assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = KEEP_ENABLE ? output_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_axis_tvalid = output_axis_tvalid_reg; assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg; assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg; assign output_axis_tid = ID_ENABLE ? output_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_axis_tdest = DEST_ENABLE ? output_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign output_axis_tuser = USER_ENABLE ? output_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int)); assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
@ -240,7 +278,7 @@ always @* begin
store_axis_int_to_output = 1'b0; store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0; store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0; store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
// input is ready // input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin if (output_axis_tready | ~output_axis_tvalid_reg) begin
@ -274,17 +312,26 @@ always @(posedge clk) begin
// datapath // datapath
if (store_axis_int_to_output) begin if (store_axis_int_to_output) begin
output_axis_tdata_reg <= output_axis_tdata_int; output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tlast_reg <= output_axis_tlast_int; output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tid_reg <= output_axis_tid_int;
output_axis_tdest_reg <= output_axis_tdest_int;
output_axis_tuser_reg <= output_axis_tuser_int; output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg; output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg; output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tid_reg <= temp_axis_tid_reg;
output_axis_tdest_reg <= temp_axis_tdest_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg; output_axis_tuser_reg <= temp_axis_tuser_reg;
end end
if (store_axis_int_to_temp) begin if (store_axis_int_to_temp) begin
temp_axis_tdata_reg <= output_axis_tdata_int; temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tlast_reg <= output_axis_tlast_int; temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tid_reg <= output_axis_tid_int;
temp_axis_tdest_reg <= output_axis_tdest_int;
temp_axis_tuser_reg <= output_axis_tuser_int; temp_axis_tuser_reg <= output_axis_tuser_int;
end end
end end
@ -292,14 +339,14 @@ end
endmodule endmodule
""") """)
output_file.write(t.render( output_file.write(t.render(
n=ports, n=ports,
w=select_width, w=select_width,
name=name, name=name,
ports=range(ports) ports=range(ports)
)) ))
print("Done") print("Done")
if __name__ == "__main__": if __name__ == "__main__":

155
lib/axis/rtl/axis_mux_4.v
View File

@ -31,47 +31,70 @@ THE SOFTWARE.
*/ */
module axis_mux_4 # module axis_mux_4 #
( (
parameter DATA_WIDTH = 8 parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
) )
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
/* /*
* AXI inputs * AXI inputs
*/ */
input wire [DATA_WIDTH-1:0] input_0_axis_tdata, input wire [DATA_WIDTH-1:0] input_0_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_0_axis_tkeep,
input wire input_0_axis_tvalid, input wire input_0_axis_tvalid,
output wire input_0_axis_tready, output wire input_0_axis_tready,
input wire input_0_axis_tlast, input wire input_0_axis_tlast,
input wire input_0_axis_tuser, input wire [ID_WIDTH-1:0] input_0_axis_tid,
input wire [DEST_WIDTH-1:0] input_0_axis_tdest,
input wire [USER_WIDTH-1:0] input_0_axis_tuser,
input wire [DATA_WIDTH-1:0] input_1_axis_tdata, input wire [DATA_WIDTH-1:0] input_1_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_1_axis_tkeep,
input wire input_1_axis_tvalid, input wire input_1_axis_tvalid,
output wire input_1_axis_tready, output wire input_1_axis_tready,
input wire input_1_axis_tlast, input wire input_1_axis_tlast,
input wire input_1_axis_tuser, input wire [ID_WIDTH-1:0] input_1_axis_tid,
input wire [DEST_WIDTH-1:0] input_1_axis_tdest,
input wire [USER_WIDTH-1:0] input_1_axis_tuser,
input wire [DATA_WIDTH-1:0] input_2_axis_tdata, input wire [DATA_WIDTH-1:0] input_2_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_2_axis_tkeep,
input wire input_2_axis_tvalid, input wire input_2_axis_tvalid,
output wire input_2_axis_tready, output wire input_2_axis_tready,
input wire input_2_axis_tlast, input wire input_2_axis_tlast,
input wire input_2_axis_tuser, input wire [ID_WIDTH-1:0] input_2_axis_tid,
input wire [DEST_WIDTH-1:0] input_2_axis_tdest,
input wire [USER_WIDTH-1:0] input_2_axis_tuser,
input wire [DATA_WIDTH-1:0] input_3_axis_tdata, input wire [DATA_WIDTH-1:0] input_3_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_3_axis_tkeep,
input wire input_3_axis_tvalid, input wire input_3_axis_tvalid,
output wire input_3_axis_tready, output wire input_3_axis_tready,
input wire input_3_axis_tlast, input wire input_3_axis_tlast,
input wire input_3_axis_tuser, input wire [ID_WIDTH-1:0] input_3_axis_tid,
input wire [DEST_WIDTH-1:0] input_3_axis_tdest,
input wire [USER_WIDTH-1:0] input_3_axis_tuser,
/* /*
* AXI output * AXI output
*/ */
output wire [DATA_WIDTH-1:0] output_axis_tdata, output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid, output wire output_axis_tvalid,
input wire output_axis_tready, input wire output_axis_tready,
output wire output_axis_tlast, output wire output_axis_tlast,
output wire output_axis_tuser, output wire [ID_WIDTH-1:0] output_axis_tid,
output wire [DEST_WIDTH-1:0] output_axis_tdest,
output wire [USER_WIDTH-1:0] output_axis_tuser,
/* /*
* Control * Control
@ -89,12 +112,15 @@ reg input_2_axis_tready_reg = 1'b0, input_2_axis_tready_next;
reg input_3_axis_tready_reg = 1'b0, input_3_axis_tready_next; reg input_3_axis_tready_reg = 1'b0, input_3_axis_tready_next;
// internal datapath // internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int; reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg output_axis_tvalid_int; reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tready_int_reg = 1'b0; reg output_axis_tvalid_int;
reg output_axis_tlast_int; reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tuser_int; reg output_axis_tlast_int;
wire output_axis_tready_int_early; reg [ID_WIDTH-1:0] output_axis_tid_int;
reg [DEST_WIDTH-1:0] output_axis_tdest_int;
reg [USER_WIDTH-1:0] output_axis_tuser_int;
wire output_axis_tready_int_early;
assign input_0_axis_tready = input_0_axis_tready_reg; assign input_0_axis_tready = input_0_axis_tready_reg;
assign input_1_axis_tready = input_1_axis_tready_reg; assign input_1_axis_tready = input_1_axis_tready_reg;
@ -115,46 +141,64 @@ end
// mux for incoming packet // mux for incoming packet
reg [DATA_WIDTH-1:0] current_input_tdata; reg [DATA_WIDTH-1:0] current_input_tdata;
reg current_input_tvalid; reg [KEEP_WIDTH-1:0] current_input_tkeep;
reg current_input_tready; reg current_input_tvalid;
reg current_input_tlast; reg current_input_tready;
reg current_input_tuser; reg current_input_tlast;
reg [ID_WIDTH-1:0] current_input_tid;
reg [DEST_WIDTH-1:0] current_input_tdest;
reg [USER_WIDTH-1:0] current_input_tuser;
always @* begin always @* begin
case (select_reg) case (select_reg)
2'd0: begin 2'd0: begin
current_input_tdata = input_0_axis_tdata; current_input_tdata = input_0_axis_tdata;
current_input_tkeep = input_0_axis_tkeep;
current_input_tvalid = input_0_axis_tvalid; current_input_tvalid = input_0_axis_tvalid;
current_input_tready = input_0_axis_tready; current_input_tready = input_0_axis_tready;
current_input_tlast = input_0_axis_tlast; current_input_tlast = input_0_axis_tlast;
current_input_tuser = input_0_axis_tuser; current_input_tid = input_0_axis_tid;
current_input_tdest = input_0_axis_tdest;
current_input_tuser = input_0_axis_tuser;
end end
2'd1: begin 2'd1: begin
current_input_tdata = input_1_axis_tdata; current_input_tdata = input_1_axis_tdata;
current_input_tkeep = input_1_axis_tkeep;
current_input_tvalid = input_1_axis_tvalid; current_input_tvalid = input_1_axis_tvalid;
current_input_tready = input_1_axis_tready; current_input_tready = input_1_axis_tready;
current_input_tlast = input_1_axis_tlast; current_input_tlast = input_1_axis_tlast;
current_input_tuser = input_1_axis_tuser; current_input_tid = input_1_axis_tid;
current_input_tdest = input_1_axis_tdest;
current_input_tuser = input_1_axis_tuser;
end end
2'd2: begin 2'd2: begin
current_input_tdata = input_2_axis_tdata; current_input_tdata = input_2_axis_tdata;
current_input_tkeep = input_2_axis_tkeep;
current_input_tvalid = input_2_axis_tvalid; current_input_tvalid = input_2_axis_tvalid;
current_input_tready = input_2_axis_tready; current_input_tready = input_2_axis_tready;
current_input_tlast = input_2_axis_tlast; current_input_tlast = input_2_axis_tlast;
current_input_tuser = input_2_axis_tuser; current_input_tid = input_2_axis_tid;
current_input_tdest = input_2_axis_tdest;
current_input_tuser = input_2_axis_tuser;
end end
2'd3: begin 2'd3: begin
current_input_tdata = input_3_axis_tdata; current_input_tdata = input_3_axis_tdata;
current_input_tkeep = input_3_axis_tkeep;
current_input_tvalid = input_3_axis_tvalid; current_input_tvalid = input_3_axis_tvalid;
current_input_tready = input_3_axis_tready; current_input_tready = input_3_axis_tready;
current_input_tlast = input_3_axis_tlast; current_input_tlast = input_3_axis_tlast;
current_input_tuser = input_3_axis_tuser; current_input_tid = input_3_axis_tid;
current_input_tdest = input_3_axis_tdest;
current_input_tuser = input_3_axis_tuser;
end end
default: begin default: begin
current_input_tdata = {DATA_WIDTH{1'b0}}; current_input_tdata = {DATA_WIDTH{1'b0}};
current_input_tkeep = {KEEP_WIDTH{1'b0}};
current_input_tvalid = 1'b0; current_input_tvalid = 1'b0;
current_input_tready = 1'b0; current_input_tready = 1'b0;
current_input_tlast = 1'b0; current_input_tlast = 1'b0;
current_input_tuser = 1'b0; current_input_tid = {ID_WIDTH{1'b0}};
current_input_tdest = {DEST_WIDTH{1'b0}};
current_input_tuser = {USER_WIDTH{1'b0}};
end end
endcase endcase
end end
@ -190,10 +234,13 @@ always @* begin
endcase endcase
// pass through selected packet data // pass through selected packet data
output_axis_tdata_int = current_input_tdata; output_axis_tdata_int = current_input_tdata;
output_axis_tkeep_int = current_input_tkeep;
output_axis_tvalid_int = current_input_tvalid & current_input_tready & frame_reg; output_axis_tvalid_int = current_input_tvalid & current_input_tready & frame_reg;
output_axis_tlast_int = current_input_tlast; output_axis_tlast_int = current_input_tlast;
output_axis_tuser_int = current_input_tuser; output_axis_tid_int = current_input_tid;
output_axis_tdest_int = current_input_tdest;
output_axis_tuser_int = current_input_tuser;
end end
always @(posedge clk) begin always @(posedge clk) begin
@ -215,25 +262,34 @@ always @(posedge clk) begin
end end
// output datapath logic // output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next; reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0; reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] output_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] output_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next; reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0; reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] temp_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control // datapath control
reg store_axis_int_to_output; reg store_axis_int_to_output;
reg store_axis_int_to_temp; reg store_axis_int_to_temp;
reg store_axis_temp_to_output; reg store_axis_temp_to_output;
assign output_axis_tdata = output_axis_tdata_reg; assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = KEEP_ENABLE ? output_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_axis_tvalid = output_axis_tvalid_reg; assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg; assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg; assign output_axis_tid = ID_ENABLE ? output_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_axis_tdest = DEST_ENABLE ? output_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign output_axis_tuser = USER_ENABLE ? output_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int)); assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
@ -246,7 +302,7 @@ always @* begin
store_axis_int_to_output = 1'b0; store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0; store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0; store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
// input is ready // input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin if (output_axis_tready | ~output_axis_tvalid_reg) begin
@ -280,17 +336,26 @@ always @(posedge clk) begin
// datapath // datapath
if (store_axis_int_to_output) begin if (store_axis_int_to_output) begin
output_axis_tdata_reg <= output_axis_tdata_int; output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tlast_reg <= output_axis_tlast_int; output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tid_reg <= output_axis_tid_int;
output_axis_tdest_reg <= output_axis_tdest_int;
output_axis_tuser_reg <= output_axis_tuser_int; output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg; output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg; output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tid_reg <= temp_axis_tid_reg;
output_axis_tdest_reg <= temp_axis_tdest_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg; output_axis_tuser_reg <= temp_axis_tuser_reg;
end end
if (store_axis_int_to_temp) begin if (store_axis_int_to_temp) begin
temp_axis_tdata_reg <= output_axis_tdata_int; temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tlast_reg <= output_axis_tlast_int; temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tid_reg <= output_axis_tid_int;
temp_axis_tdest_reg <= output_axis_tdest_int;
temp_axis_tuser_reg <= output_axis_tuser_int; temp_axis_tuser_reg <= output_axis_tuser_int;
end end
end end

321
lib/axis/rtl/axis_mux_64.py
View File

@ -1,321 +0,0 @@
#!/usr/bin/env python
"""
Generates an AXI Stream mux with the specified number of ports
"""
from __future__ import print_function
import argparse
import math
from jinja2 import Template
def main():
parser = argparse.ArgumentParser(description=__doc__.strip())
parser.add_argument('-p', '--ports', type=int, default=4, help="number of ports")
parser.add_argument('-n', '--name', type=str, help="module name")
parser.add_argument('-o', '--output', type=str, help="output file name")
args = parser.parse_args()
try:
generate(**args.__dict__)
except IOError as ex:
print(ex)
exit(1)
def generate(ports=4, name=None, output=None):
if name is None:
name = "axis_mux_64_{0}".format(ports)
if output is None:
output = name + ".v"
print("Opening file '{0}'...".format(output))
output_file = open(output, 'w')
print("Generating {0} port AXI Stream mux {1}...".format(ports, name))
select_width = int(math.ceil(math.log(ports, 2)))
t = Template(u"""/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream {{n}} port multiplexer (64 bit datapath)
*/
module {{name}} #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI inputs
*/
{%- for p in ports %}
input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep,
input wire input_{{p}}_axis_tvalid,
output wire input_{{p}}_axis_tready,
input wire input_{{p}}_axis_tlast,
input wire input_{{p}}_axis_tuser,
{% endfor %}
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Control
*/
input wire enable,
input wire [{{w-1}}:0] select
);
reg [{{w-1}}:0] select_reg = {{w}}'d0, select_next;
reg frame_reg = 1'b0, frame_next;
{% for p in ports %}
reg input_{{p}}_axis_tready_reg = 1'b0, input_{{p}}_axis_tready_next;
{%- endfor %}
// internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
{% for p in ports %}
assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg;
{%- endfor %}
// mux for start of packet detection
reg selected_input_tvalid;
always @* begin
case (select)
{%- for p in ports %}
{{w}}'d{{p}}: selected_input_tvalid = input_{{p}}_axis_tvalid;
{%- endfor %}
default: selected_input_tvalid = 1'b0;
endcase
end
// mux for incoming packet
reg [DATA_WIDTH-1:0] current_input_tdata;
reg [KEEP_WIDTH-1:0] current_input_tkeep;
reg current_input_tvalid;
reg current_input_tready;
reg current_input_tlast;
reg current_input_tuser;
always @* begin
case (select_reg)
{%- for p in ports %}
{{w}}'d{{p}}: begin
current_input_tdata = input_{{p}}_axis_tdata;
current_input_tkeep = input_{{p}}_axis_tkeep;
current_input_tvalid = input_{{p}}_axis_tvalid;
current_input_tready = input_{{p}}_axis_tready;
current_input_tlast = input_{{p}}_axis_tlast;
current_input_tuser = input_{{p}}_axis_tuser;
end
{%- endfor %}
default: begin
current_input_tdata = {DATA_WIDTH{1'b0}};
current_input_tkeep = {KEEP_WIDTH{1'b0}};
current_input_tvalid = 1'b0;
current_input_tready = 1'b0;
current_input_tlast = 1'b0;
current_input_tuser = 1'b0;
end
endcase
end
always @* begin
select_next = select_reg;
frame_next = frame_reg;
{% for p in ports %}
input_{{p}}_axis_tready_next = 1'b0;
{%- endfor %}
if (current_input_tvalid & current_input_tready) begin
// end of frame detection
if (current_input_tlast) begin
frame_next = 1'b0;
end
end
if (~frame_reg & enable & selected_input_tvalid) begin
// start of frame, grab select value
frame_next = 1'b1;
select_next = select;
end
// generate ready signal on selected port
case (select_next)
{%- for p in ports %}
{{w}}'d{{p}}: input_{{p}}_axis_tready_next = output_axis_tready_int_early & frame_next;
{%- endfor %}
endcase
// pass through selected packet data
output_axis_tdata_int = current_input_tdata;
output_axis_tkeep_int = current_input_tkeep;
output_axis_tvalid_int = current_input_tvalid & current_input_tready & frame_reg;
output_axis_tlast_int = current_input_tlast;
output_axis_tuser_int = current_input_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= {{w}}'d0;
frame_reg <= 1'b0;
{%- for p in ports %}
input_{{p}}_axis_tready_reg <= 1'b0;
{%- endfor %}
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
{%- for p in ports %}
input_{{p}}_axis_tready_reg <= input_{{p}}_axis_tready_next;
{%- endfor %}
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = output_axis_tkeep_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
output_axis_tvalid_next = output_axis_tvalid_reg;
temp_axis_tvalid_next = temp_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_axis_tvalid_next = output_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_axis_tvalid_next = output_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (output_axis_tready) begin
// input is not ready, but output is ready
output_axis_tvalid_next = temp_axis_tvalid_reg;
temp_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
output_axis_tvalid_reg <= 1'b0;
output_axis_tready_int_reg <= 1'b0;
temp_axis_tvalid_reg <= 1'b0;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
output_axis_tready_int_reg <= output_axis_tready_int_early;
temp_axis_tvalid_reg <= temp_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end
endmodule
""")
output_file.write(t.render(
n=ports,
w=select_width,
name=name,
ports=range(ports)
))
print("Done")
if __name__ == "__main__":
main()

318
lib/axis/rtl/axis_mux_64_4.v
View File

@ -1,318 +0,0 @@
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream 4 port multiplexer (64 bit datapath)
*/
module axis_mux_64_4 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI inputs
*/
input wire [DATA_WIDTH-1:0] input_0_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_0_axis_tkeep,
input wire input_0_axis_tvalid,
output wire input_0_axis_tready,
input wire input_0_axis_tlast,
input wire input_0_axis_tuser,
input wire [DATA_WIDTH-1:0] input_1_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_1_axis_tkeep,
input wire input_1_axis_tvalid,
output wire input_1_axis_tready,
input wire input_1_axis_tlast,
input wire input_1_axis_tuser,
input wire [DATA_WIDTH-1:0] input_2_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_2_axis_tkeep,
input wire input_2_axis_tvalid,
output wire input_2_axis_tready,
input wire input_2_axis_tlast,
input wire input_2_axis_tuser,
input wire [DATA_WIDTH-1:0] input_3_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_3_axis_tkeep,
input wire input_3_axis_tvalid,
output wire input_3_axis_tready,
input wire input_3_axis_tlast,
input wire input_3_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Control
*/
input wire enable,
input wire [1:0] select
);
reg [1:0] select_reg = 2'd0, select_next;
reg frame_reg = 1'b0, frame_next;
reg input_0_axis_tready_reg = 1'b0, input_0_axis_tready_next;
reg input_1_axis_tready_reg = 1'b0, input_1_axis_tready_next;
reg input_2_axis_tready_reg = 1'b0, input_2_axis_tready_next;
reg input_3_axis_tready_reg = 1'b0, input_3_axis_tready_next;
// internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
assign input_0_axis_tready = input_0_axis_tready_reg;
assign input_1_axis_tready = input_1_axis_tready_reg;
assign input_2_axis_tready = input_2_axis_tready_reg;
assign input_3_axis_tready = input_3_axis_tready_reg;
// mux for start of packet detection
reg selected_input_tvalid;
always @* begin
case (select)
2'd0: selected_input_tvalid = input_0_axis_tvalid;
2'd1: selected_input_tvalid = input_1_axis_tvalid;
2'd2: selected_input_tvalid = input_2_axis_tvalid;
2'd3: selected_input_tvalid = input_3_axis_tvalid;
default: selected_input_tvalid = 1'b0;
endcase
end
// mux for incoming packet
reg [DATA_WIDTH-1:0] current_input_tdata;
reg [KEEP_WIDTH-1:0] current_input_tkeep;
reg current_input_tvalid;
reg current_input_tready;
reg current_input_tlast;
reg current_input_tuser;
always @* begin
case (select_reg)
2'd0: begin
current_input_tdata = input_0_axis_tdata;
current_input_tkeep = input_0_axis_tkeep;
current_input_tvalid = input_0_axis_tvalid;
current_input_tready = input_0_axis_tready;
current_input_tlast = input_0_axis_tlast;
current_input_tuser = input_0_axis_tuser;
end
2'd1: begin
current_input_tdata = input_1_axis_tdata;
current_input_tkeep = input_1_axis_tkeep;
current_input_tvalid = input_1_axis_tvalid;
current_input_tready = input_1_axis_tready;
current_input_tlast = input_1_axis_tlast;
current_input_tuser = input_1_axis_tuser;
end
2'd2: begin
current_input_tdata = input_2_axis_tdata;
current_input_tkeep = input_2_axis_tkeep;
current_input_tvalid = input_2_axis_tvalid;
current_input_tready = input_2_axis_tready;
current_input_tlast = input_2_axis_tlast;
current_input_tuser = input_2_axis_tuser;
end
2'd3: begin
current_input_tdata = input_3_axis_tdata;
current_input_tkeep = input_3_axis_tkeep;
current_input_tvalid = input_3_axis_tvalid;
current_input_tready = input_3_axis_tready;
current_input_tlast = input_3_axis_tlast;
current_input_tuser = input_3_axis_tuser;
end
default: begin
current_input_tdata = {DATA_WIDTH{1'b0}};
current_input_tkeep = {KEEP_WIDTH{1'b0}};
current_input_tvalid = 1'b0;
current_input_tready = 1'b0;
current_input_tlast = 1'b0;
current_input_tuser = 1'b0;
end
endcase
end
always @* begin
select_next = select_reg;
frame_next = frame_reg;
input_0_axis_tready_next = 1'b0;
input_1_axis_tready_next = 1'b0;
input_2_axis_tready_next = 1'b0;
input_3_axis_tready_next = 1'b0;
if (current_input_tvalid & current_input_tready) begin
// end of frame detection
if (current_input_tlast) begin
frame_next = 1'b0;
end
end
if (~frame_reg & enable & selected_input_tvalid) begin
// start of frame, grab select value
frame_next = 1'b1;
select_next = select;
end
// generate ready signal on selected port
case (select_next)
2'd0: input_0_axis_tready_next = output_axis_tready_int_early & frame_next;
2'd1: input_1_axis_tready_next = output_axis_tready_int_early & frame_next;
2'd2: input_2_axis_tready_next = output_axis_tready_int_early & frame_next;
2'd3: input_3_axis_tready_next = output_axis_tready_int_early & frame_next;
endcase
// pass through selected packet data
output_axis_tdata_int = current_input_tdata;
output_axis_tkeep_int = current_input_tkeep;
output_axis_tvalid_int = current_input_tvalid & current_input_tready & frame_reg;
output_axis_tlast_int = current_input_tlast;
output_axis_tuser_int = current_input_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= 2'd0;
frame_reg <= 1'b0;
input_0_axis_tready_reg <= 1'b0;
input_1_axis_tready_reg <= 1'b0;
input_2_axis_tready_reg <= 1'b0;
input_3_axis_tready_reg <= 1'b0;
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
input_0_axis_tready_reg <= input_0_axis_tready_next;
input_1_axis_tready_reg <= input_1_axis_tready_next;
input_2_axis_tready_reg <= input_2_axis_tready_next;
input_3_axis_tready_reg <= input_3_axis_tready_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = output_axis_tkeep_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
output_axis_tvalid_next = output_axis_tvalid_reg;
temp_axis_tvalid_next = temp_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_axis_tvalid_next = output_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_axis_tvalid_next = output_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (output_axis_tready) begin
// input is not ready, but output is ready
output_axis_tvalid_next = temp_axis_tvalid_reg;
temp_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
output_axis_tvalid_reg <= 1'b0;
output_axis_tready_int_reg <= 1'b0;
temp_axis_tvalid_reg <= 1'b0;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
output_axis_tready_int_reg <= output_axis_tready_int_early;
temp_axis_tvalid_reg <= temp_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end
endmodule

85
lib/axis/rtl/axis_rate_limit.v
View File

@ -31,7 +31,16 @@ THE SOFTWARE.
*/ */
module axis_rate_limit # module axis_rate_limit #
( (
parameter DATA_WIDTH = 8 parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter LAST_ENABLE = 1,
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
) )
( (
input wire clk, input wire clk,
@ -41,19 +50,25 @@ module axis_rate_limit #
* AXI input * AXI input
*/ */
input wire [DATA_WIDTH-1:0] input_axis_tdata, input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid, input wire input_axis_tvalid,
output wire input_axis_tready, output wire input_axis_tready,
input wire input_axis_tlast, input wire input_axis_tlast,
input wire input_axis_tuser, input wire [ID_WIDTH-1:0] input_axis_tid,
input wire [DEST_WIDTH-1:0] input_axis_tdest,
input wire [USER_WIDTH-1:0] input_axis_tuser,
/* /*
* AXI output * AXI output
*/ */
output wire [DATA_WIDTH-1:0] output_axis_tdata, output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid, output wire output_axis_tvalid,
input wire output_axis_tready, input wire output_axis_tready,
output wire output_axis_tlast, output wire output_axis_tlast,
output wire output_axis_tuser, output wire [ID_WIDTH-1:0] output_axis_tid,
output wire [DEST_WIDTH-1:0] output_axis_tdest,
output wire [USER_WIDTH-1:0] output_axis_tuser,
/* /*
* Configuration * Configuration
@ -64,12 +79,15 @@ module axis_rate_limit #
); );
// internal datapath // internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int; reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg output_axis_tvalid_int; reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tready_int_reg = 1'b0; reg output_axis_tvalid_int;
reg output_axis_tlast_int; reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tuser_int; reg output_axis_tlast_int;
wire output_axis_tready_int_early; reg [ID_WIDTH-1:0] output_axis_tid_int;
reg [DEST_WIDTH-1:0] output_axis_tdest_int;
reg [USER_WIDTH-1:0] output_axis_tuser_int;
wire output_axis_tready_int_early;
reg [23:0] acc_reg = 24'd0, acc_next; reg [23:0] acc_reg = 24'd0, acc_next;
reg pause; reg pause;
@ -95,7 +113,7 @@ always @* begin
end end
if (acc_next >= rate_num) begin if (acc_next >= rate_num) begin
if (rate_by_frame) begin if (LAST_ENABLE && rate_by_frame) begin
pause = ~frame_next; pause = ~frame_next;
end else begin end else begin
pause = 1'b1; pause = 1'b1;
@ -104,10 +122,13 @@ always @* begin
input_axis_tready_next = output_axis_tready_int_early & ~pause; input_axis_tready_next = output_axis_tready_int_early & ~pause;
output_axis_tdata_int = input_axis_tdata; output_axis_tdata_int = input_axis_tdata;
output_axis_tkeep_int = input_axis_tkeep;
output_axis_tvalid_int = input_axis_tvalid & input_axis_tready; output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
output_axis_tlast_int = input_axis_tlast; output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser; output_axis_tid_int = input_axis_tid;
output_axis_tdest_int = input_axis_tdest;
output_axis_tuser_int = input_axis_tuser;
end end
always @(posedge clk) begin always @(posedge clk) begin
@ -123,25 +144,34 @@ always @(posedge clk) begin
end end
// output datapath logic // output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next; reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0; reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] output_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] output_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next; reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0; reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] temp_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control // datapath control
reg store_axis_int_to_output; reg store_axis_int_to_output;
reg store_axis_int_to_temp; reg store_axis_int_to_temp;
reg store_axis_temp_to_output; reg store_axis_temp_to_output;
assign output_axis_tdata = output_axis_tdata_reg; assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = KEEP_ENABLE ? output_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_axis_tvalid = output_axis_tvalid_reg; assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg; assign output_axis_tlast = LAST_ENABLE ? output_axis_tlast_reg : 1'b1;
assign output_axis_tuser = output_axis_tuser_reg; assign output_axis_tid = ID_ENABLE ? output_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_axis_tdest = DEST_ENABLE ? output_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign output_axis_tuser = USER_ENABLE ? output_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int)); assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
@ -154,7 +184,7 @@ always @* begin
store_axis_int_to_output = 1'b0; store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0; store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0; store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
// input is ready // input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin if (output_axis_tready | ~output_axis_tvalid_reg) begin
@ -188,17 +218,26 @@ always @(posedge clk) begin
// datapath // datapath
if (store_axis_int_to_output) begin if (store_axis_int_to_output) begin
output_axis_tdata_reg <= output_axis_tdata_int; output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tlast_reg <= output_axis_tlast_int; output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tid_reg <= output_axis_tid_int;
output_axis_tdest_reg <= output_axis_tdest_int;
output_axis_tuser_reg <= output_axis_tuser_int; output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg; output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg; output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tid_reg <= temp_axis_tid_reg;
output_axis_tdest_reg <= temp_axis_tdest_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg; output_axis_tuser_reg <= temp_axis_tuser_reg;
end end
if (store_axis_int_to_temp) begin if (store_axis_int_to_temp) begin
temp_axis_tdata_reg <= output_axis_tdata_int; temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tlast_reg <= output_axis_tlast_int; temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tid_reg <= output_axis_tid_int;
temp_axis_tdest_reg <= output_axis_tdest_int;
temp_axis_tuser_reg <= output_axis_tuser_int; temp_axis_tuser_reg <= output_axis_tuser_int;
end end
end end

217
lib/axis/rtl/axis_rate_limit_64.v
View File

@ -1,217 +0,0 @@
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream rate limiter (64 bit datapath)
*/
module axis_rate_limit_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Configuration
*/
input wire [7:0] rate_num,
input wire [7:0] rate_denom,
input wire rate_by_frame
);
// internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
reg [23:0] acc_reg = 24'd0, acc_next;
reg pause;
reg frame_reg = 1'b0, frame_next;
reg input_axis_tready_reg = 1'b0, input_axis_tready_next;
assign input_axis_tready = input_axis_tready_reg;
always @* begin
acc_next = acc_reg;
pause = 1'b0;
frame_next = frame_reg;
if (acc_reg >= rate_num) begin
acc_next = acc_reg - rate_num;
end
if (input_axis_tready & input_axis_tvalid) begin
// read input
frame_next = ~input_axis_tlast;
acc_next = acc_reg + (rate_denom - rate_num);
end
if (acc_next >= rate_num) begin
if (rate_by_frame) begin
pause = ~frame_next;
end else begin
pause = 1'b1;
end
end
input_axis_tready_next = output_axis_tready_int_early & ~pause;
output_axis_tdata_int = input_axis_tdata;
output_axis_tkeep_int = input_axis_tkeep;
output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser;
end
always @(posedge clk) begin
if (rst) begin
acc_reg <= 24'd0;
frame_reg <= 1'b0;
input_axis_tready_reg <= 1'b0;
end else begin
acc_reg <= acc_next;
frame_reg <= frame_next;
input_axis_tready_reg <= input_axis_tready_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = output_axis_tkeep_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
output_axis_tvalid_next = output_axis_tvalid_reg;
temp_axis_tvalid_next = temp_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_axis_tvalid_next = output_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_axis_tvalid_next = output_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (output_axis_tready) begin
// input is not ready, but output is ready
output_axis_tvalid_next = temp_axis_tvalid_reg;
temp_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
output_axis_tvalid_reg <= 1'b0;
output_axis_tready_int_reg <= 1'b0;
temp_axis_tvalid_reg <= 1'b0;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
output_axis_tready_int_reg <= output_axis_tready_int_early;
temp_axis_tvalid_reg <= temp_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end
endmodule

59
lib/axis/rtl/axis_register.v
View File

@ -31,7 +31,16 @@ THE SOFTWARE.
*/ */
module axis_register # module axis_register #
( (
parameter DATA_WIDTH = 8 parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter LAST_ENABLE = 1,
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
) )
( (
input wire clk, input wire clk,
@ -41,33 +50,45 @@ module axis_register #
* AXI input * AXI input
*/ */
input wire [DATA_WIDTH-1:0] input_axis_tdata, input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid, input wire input_axis_tvalid,
output wire input_axis_tready, output wire input_axis_tready,
input wire input_axis_tlast, input wire input_axis_tlast,
input wire input_axis_tuser, input wire [ID_WIDTH-1:0] input_axis_tid,
input wire [DEST_WIDTH-1:0] input_axis_tdest,
input wire [USER_WIDTH-1:0] input_axis_tuser,
/* /*
* AXI output * AXI output
*/ */
output wire [DATA_WIDTH-1:0] output_axis_tdata, output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid, output wire output_axis_tvalid,
input wire output_axis_tready, input wire output_axis_tready,
output wire output_axis_tlast, output wire output_axis_tlast,
output wire output_axis_tuser output wire [ID_WIDTH-1:0] output_axis_tid,
output wire [DEST_WIDTH-1:0] output_axis_tdest,
output wire [USER_WIDTH-1:0] output_axis_tuser
); );
// datapath registers // datapath registers
reg input_axis_tready_reg = 1'b0; reg input_axis_tready_reg = 1'b0;
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next; reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0; reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] output_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] output_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next; reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0; reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] temp_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control // datapath control
reg store_axis_input_to_output; reg store_axis_input_to_output;
@ -76,10 +97,13 @@ reg store_axis_temp_to_output;
assign input_axis_tready = input_axis_tready_reg; assign input_axis_tready = input_axis_tready_reg;
assign output_axis_tdata = output_axis_tdata_reg; assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = KEEP_ENABLE ? output_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_axis_tvalid = output_axis_tvalid_reg; assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg; assign output_axis_tlast = LAST_ENABLE ? output_axis_tlast_reg : 1'b1;
assign output_axis_tuser = output_axis_tuser_reg; assign output_axis_tid = ID_ENABLE ? output_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_axis_tdest = DEST_ENABLE ? output_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign output_axis_tuser = USER_ENABLE ? output_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
wire input_axis_tready_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~input_axis_tvalid)); wire input_axis_tready_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~input_axis_tvalid));
@ -92,7 +116,7 @@ always @* begin
store_axis_input_to_output = 1'b0; store_axis_input_to_output = 1'b0;
store_axis_input_to_temp = 1'b0; store_axis_input_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0; store_axis_temp_to_output = 1'b0;
if (input_axis_tready_reg) begin if (input_axis_tready_reg) begin
// input is ready // input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin if (output_axis_tready | ~output_axis_tvalid_reg) begin
@ -126,17 +150,26 @@ always @(posedge clk) begin
// datapath // datapath
if (store_axis_input_to_output) begin if (store_axis_input_to_output) begin
output_axis_tdata_reg <= input_axis_tdata; output_axis_tdata_reg <= input_axis_tdata;
output_axis_tkeep_reg <= input_axis_tkeep;
output_axis_tlast_reg <= input_axis_tlast; output_axis_tlast_reg <= input_axis_tlast;
output_axis_tid_reg <= input_axis_tid;
output_axis_tdest_reg <= input_axis_tdest;
output_axis_tuser_reg <= input_axis_tuser; output_axis_tuser_reg <= input_axis_tuser;
end else if (store_axis_temp_to_output) begin end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg; output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg; output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tid_reg <= temp_axis_tid_reg;
output_axis_tdest_reg <= temp_axis_tdest_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg; output_axis_tuser_reg <= temp_axis_tuser_reg;
end end
if (store_axis_input_to_temp) begin if (store_axis_input_to_temp) begin
temp_axis_tdata_reg <= input_axis_tdata; temp_axis_tdata_reg <= input_axis_tdata;
temp_axis_tkeep_reg <= input_axis_tkeep;
temp_axis_tlast_reg <= input_axis_tlast; temp_axis_tlast_reg <= input_axis_tlast;
temp_axis_tid_reg <= input_axis_tid;
temp_axis_tdest_reg <= input_axis_tdest;
temp_axis_tuser_reg <= input_axis_tuser; temp_axis_tuser_reg <= input_axis_tuser;
end end
end end

153
lib/axis/rtl/axis_register_64.v
View File

@ -1,153 +0,0 @@
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream register (64 bit datapath)
*/
module axis_register_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
// datapath registers
reg input_axis_tready_reg = 1'b0;
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_input_to_output;
reg store_axis_input_to_temp;
reg store_axis_temp_to_output;
assign input_axis_tready = input_axis_tready_reg;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = output_axis_tkeep_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
wire input_axis_tready_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~input_axis_tvalid));
always @* begin
// transfer sink ready state to source
output_axis_tvalid_next = output_axis_tvalid_reg;
temp_axis_tvalid_next = temp_axis_tvalid_reg;
store_axis_input_to_output = 1'b0;
store_axis_input_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (input_axis_tready_reg) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_axis_tvalid_next = input_axis_tvalid;
store_axis_input_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_axis_tvalid_next = input_axis_tvalid;
store_axis_input_to_temp = 1'b1;
end
end else if (output_axis_tready) begin
// input is not ready, but output is ready
output_axis_tvalid_next = temp_axis_tvalid_reg;
temp_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
input_axis_tready_reg <= 1'b0;
output_axis_tvalid_reg <= 1'b0;
temp_axis_tvalid_reg <= 1'b0;
end else begin
input_axis_tready_reg <= input_axis_tready_early;
output_axis_tvalid_reg <= output_axis_tvalid_next;
temp_axis_tvalid_reg <= temp_axis_tvalid_next;
end
// datapath
if (store_axis_input_to_output) begin
output_axis_tdata_reg <= input_axis_tdata;
output_axis_tkeep_reg <= input_axis_tkeep;
output_axis_tlast_reg <= input_axis_tlast;
output_axis_tuser_reg <= input_axis_tuser;
end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
end
if (store_axis_input_to_temp) begin
temp_axis_tdata_reg <= input_axis_tdata;
temp_axis_tkeep_reg <= input_axis_tkeep;
temp_axis_tlast_reg <= input_axis_tlast;
temp_axis_tuser_reg <= input_axis_tuser;
end
end
endmodule

53
lib/axis/rtl/axis_srl_fifo.v
View File

@ -32,6 +32,15 @@ THE SOFTWARE.
module axis_srl_fifo # module axis_srl_fifo #
( (
parameter DATA_WIDTH = 8, parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter LAST_ENABLE = 1,
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
parameter DEPTH = 16 parameter DEPTH = 16
) )
( (
@ -42,19 +51,25 @@ module axis_srl_fifo #
* AXI input * AXI input
*/ */
input wire [DATA_WIDTH-1:0] input_axis_tdata, input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid, input wire input_axis_tvalid,
output wire input_axis_tready, output wire input_axis_tready,
input wire input_axis_tlast, input wire input_axis_tlast,
input wire input_axis_tuser, input wire [ID_WIDTH-1:0] input_axis_tid,
input wire [DEST_WIDTH-1:0] input_axis_tdest,
input wire [USER_WIDTH-1:0] input_axis_tuser,
/* /*
* AXI output * AXI output
*/ */
output wire [DATA_WIDTH-1:0] output_axis_tdata, output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid, output wire output_axis_tvalid,
input wire output_axis_tready, input wire output_axis_tready,
output wire output_axis_tlast, output wire output_axis_tlast,
output wire output_axis_tuser, output wire [ID_WIDTH-1:0] output_axis_tid,
output wire [DEST_WIDTH-1:0] output_axis_tdest,
output wire [USER_WIDTH-1:0] output_axis_tuser,
/* /*
* Status * Status
@ -62,14 +77,42 @@ module axis_srl_fifo #
output wire [$clog2(DEPTH+1)-1:0] count output wire [$clog2(DEPTH+1)-1:0] count
); );
reg [DATA_WIDTH+2-1:0] data_reg[DEPTH-1:0]; localparam KEEP_OFFSET = DATA_WIDTH;
localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0);
localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
reg [WIDTH-1:0] data_reg[DEPTH-1:0];
reg [$clog2(DEPTH+1)-1:0] ptr_reg = 0; reg [$clog2(DEPTH+1)-1:0] ptr_reg = 0;
reg full_reg = 0, full_next; reg full_reg = 0, full_next;
reg empty_reg = 1, empty_next; reg empty_reg = 1, empty_next;
assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = data_reg[ptr_reg-1]; wire [WIDTH-1:0] input_axis;
wire [WIDTH-1:0] output_axis = data_reg[ptr_reg-1];
assign input_axis_tready = ~full_reg; assign input_axis_tready = ~full_reg;
generate
assign input_axis[DATA_WIDTH-1:0] = input_axis_tdata;
if (KEEP_ENABLE) assign input_axis[KEEP_OFFSET +: KEEP_WIDTH] = input_axis_tkeep;
if (LAST_ENABLE) assign input_axis[LAST_OFFSET] = input_axis_tlast;
if (ID_ENABLE) assign input_axis[ID_OFFSET +: ID_WIDTH] = input_axis_tid;
if (DEST_ENABLE) assign input_axis[DEST_OFFSET +: DEST_WIDTH] = input_axis_tdest;
if (USER_ENABLE) assign input_axis[USER_OFFSET +: USER_WIDTH] = input_axis_tuser;
endgenerate
assign output_axis_tvalid = ~empty_reg; assign output_axis_tvalid = ~empty_reg;
assign output_axis_tdata = output_axis[DATA_WIDTH-1:0];
assign output_axis_tkeep = KEEP_ENABLE ? output_axis[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
assign output_axis_tlast = LAST_ENABLE ? output_axis[LAST_OFFSET] : 1'b1;
assign output_axis_tid = ID_ENABLE ? output_axis[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}};
assign output_axis_tdest = DEST_ENABLE ? output_axis[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
assign output_axis_tuser = USER_ENABLE ? output_axis[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
assign count = ptr_reg; assign count = ptr_reg;
wire ptr_empty = ptr_reg == 0; wire ptr_empty = ptr_reg == 0;
@ -131,7 +174,7 @@ always @(posedge clk) begin
end end
if (shift) begin if (shift) begin
data_reg[0] <= {input_axis_tlast, input_axis_tuser, input_axis_tdata}; data_reg[0] <= input_axis;
for (i = 0; i < DEPTH-1; i = i + 1) begin for (i = 0; i < DEPTH-1; i = i + 1) begin
data_reg[i+1] <= data_reg[i]; data_reg[i+1] <= data_reg[i];
end end

144
lib/axis/rtl/axis_srl_fifo_64.v
View File

@ -1,144 +0,0 @@
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream SRL-based FIFO (64 bit datapath)
*/
module axis_srl_fifo_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter DEPTH = 16
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Status
*/
output wire [$clog2(DEPTH+1)-1:0] count
);
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_reg[DEPTH-1:0];
reg [$clog2(DEPTH+1)-1:0] ptr_reg = 0;
reg full_reg = 0, full_next;
reg empty_reg = 1, empty_next;
assign {output_axis_tlast, output_axis_tuser, output_axis_tkeep, output_axis_tdata} = data_reg[ptr_reg-1];
assign input_axis_tready = ~full_reg;
assign output_axis_tvalid = ~empty_reg;
assign count = ptr_reg;
wire ptr_empty = ptr_reg == 0;
wire ptr_empty1 = ptr_reg == 1;
wire ptr_full = ptr_reg == DEPTH;
wire ptr_full1 = ptr_reg == DEPTH-1;
reg shift;
reg inc;
reg dec;
integer i;
initial begin
for (i = 0; i < DEPTH; i = i + 1) begin
data_reg[i] <= 0;
end
end
always @* begin
shift = 0;
inc = 0;
dec = 0;
full_next = full_reg;
empty_next = empty_reg;
if (output_axis_tready & input_axis_tvalid & ~full_reg) begin
shift = 1;
inc = ptr_empty;
empty_next = 0;
end else if (output_axis_tready & output_axis_tvalid) begin
dec = 1;
full_next = 0;
empty_next = ptr_empty1;
end else if (input_axis_tvalid & input_axis_tready) begin
shift = 1;
inc = 1;
full_next = ptr_full1;
empty_next = 0;
end
end
always @(posedge clk) begin
if (rst) begin
ptr_reg <= 0;
full_reg <= 0;
empty_reg <= 1;
end else begin
if (inc) begin
ptr_reg <= ptr_reg + 1;
end else if (dec) begin
ptr_reg <= ptr_reg - 1;
end else begin
ptr_reg <= ptr_reg;
end
full_reg <= full_next;
empty_reg <= empty_next;
end
if (shift) begin
data_reg[0] <= {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};
for (i = 0; i < DEPTH-1; i = i + 1) begin
data_reg[i+1] <= data_reg[i];
end
end
end
endmodule

54
lib/axis/rtl/axis_srl_register.v
View File

@ -31,7 +31,16 @@ THE SOFTWARE.
*/ */
module axis_srl_register # module axis_srl_register #
( (
parameter DATA_WIDTH = 8 parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter LAST_ENABLE = 1,
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
) )
( (
input wire clk, input wire clk,
@ -41,30 +50,63 @@ module axis_srl_register #
* AXI input * AXI input
*/ */
input wire [DATA_WIDTH-1:0] input_axis_tdata, input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid, input wire input_axis_tvalid,
output wire input_axis_tready, output wire input_axis_tready,
input wire input_axis_tlast, input wire input_axis_tlast,
input wire input_axis_tuser, input wire [ID_WIDTH-1:0] input_axis_tid,
input wire [DEST_WIDTH-1:0] input_axis_tdest,
input wire [USER_WIDTH-1:0] input_axis_tuser,
/* /*
* AXI output * AXI output
*/ */
output wire [DATA_WIDTH-1:0] output_axis_tdata, output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid, output wire output_axis_tvalid,
input wire output_axis_tready, input wire output_axis_tready,
output wire output_axis_tlast, output wire output_axis_tlast,
output wire output_axis_tuser output wire [ID_WIDTH-1:0] output_axis_tid,
output wire [DEST_WIDTH-1:0] output_axis_tdest,
output wire [USER_WIDTH-1:0] output_axis_tuser
); );
reg [DATA_WIDTH+2-1:0] data_reg[1:0]; localparam KEEP_OFFSET = DATA_WIDTH;
localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0);
localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
reg [WIDTH-1:0] data_reg[1:0];
reg valid_reg[1:0]; reg valid_reg[1:0];
reg ptr_reg = 0; reg ptr_reg = 0;
reg full_reg = 0; reg full_reg = 0;
assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = data_reg[ptr_reg]; wire [WIDTH-1:0] input_axis;
wire [WIDTH-1:0] output_axis = data_reg[ptr_reg];
assign input_axis_tready = ~full_reg; assign input_axis_tready = ~full_reg;
generate
assign input_axis[DATA_WIDTH-1:0] = input_axis_tdata;
if (KEEP_ENABLE) assign input_axis[KEEP_OFFSET +: KEEP_WIDTH] = input_axis_tkeep;
if (LAST_ENABLE) assign input_axis[LAST_OFFSET] = input_axis_tlast;
if (ID_ENABLE) assign input_axis[ID_OFFSET +: ID_WIDTH] = input_axis_tid;
if (DEST_ENABLE) assign input_axis[DEST_OFFSET +: DEST_WIDTH] = input_axis_tdest;
if (USER_ENABLE) assign input_axis[USER_OFFSET +: USER_WIDTH] = input_axis_tuser;
endgenerate
assign output_axis_tvalid = valid_reg[ptr_reg]; assign output_axis_tvalid = valid_reg[ptr_reg];
assign output_axis_tdata = output_axis[DATA_WIDTH-1:0];
assign output_axis_tkeep = KEEP_ENABLE ? output_axis[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
assign output_axis_tlast = LAST_ENABLE ? output_axis[LAST_OFFSET] : 1'b1;
assign output_axis_tid = ID_ENABLE ? output_axis[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}};
assign output_axis_tdest = DEST_ENABLE ? output_axis[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
assign output_axis_tuser = USER_ENABLE ? output_axis[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
integer i; integer i;
initial begin initial begin
@ -84,7 +126,7 @@ always @(posedge clk) begin
// transfer in if not full // transfer in if not full
if (input_axis_tready) begin if (input_axis_tready) begin
data_reg[0] <= {input_axis_tlast, input_axis_tuser, input_axis_tdata}; data_reg[0] <= input_axis;
valid_reg[0] <= input_axis_tvalid; valid_reg[0] <= input_axis_tvalid;
for (i = 0; i < 1; i = i + 1) begin for (i = 0; i < 1; i = i + 1) begin
data_reg[i+1] <= data_reg[i]; data_reg[i+1] <= data_reg[i];

105
lib/axis/rtl/axis_srl_register_64.v
View File

@ -1,105 +0,0 @@
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream SRL-based FIFO register (64 bit datapath)
*/
module axis_srl_register_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_reg[1:0];
reg valid_reg[1:0];
reg ptr_reg = 0;
reg full_reg = 0;
assign {output_axis_tlast, output_axis_tuser, output_axis_tkeep, output_axis_tdata} = data_reg[ptr_reg];
assign input_axis_tready = ~full_reg;
assign output_axis_tvalid = valid_reg[ptr_reg];
integer i;
initial begin
for (i = 0; i < 2; i = i + 1) begin
data_reg[i] <= 0;
valid_reg[i] <= 0;
end
end
always @(posedge clk) begin
if (rst) begin
ptr_reg <= 0;
full_reg <= 0;
end else begin
// transfer empty to full
full_reg <= ~output_axis_tready & output_axis_tvalid;
// transfer in if not full
if (input_axis_tready) begin
data_reg[0] <= {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};
valid_reg[0] <= input_axis_tvalid;
for (i = 0; i < 1; i = i + 1) begin
data_reg[i+1] <= data_reg[i];
valid_reg[i+1] <= valid_reg[i];
end
ptr_reg <= valid_reg[0];
end
if (output_axis_tready) begin
ptr_reg <= 0;
end
end
end
endmodule

35
lib/axis/rtl/axis_stat_counter.v
View File

@ -32,6 +32,7 @@ THE SOFTWARE.
module axis_stat_counter # module axis_stat_counter #
( (
parameter DATA_WIDTH = 64, parameter DATA_WIDTH = 64,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8), parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter TAG_ENABLE = 1, parameter TAG_ENABLE = 1,
parameter TAG_WIDTH = 16, parameter TAG_WIDTH = 16,
@ -57,22 +58,22 @@ module axis_stat_counter #
/* /*
* AXI status data output * AXI status data output
*/ */
output wire [7:0] output_axis_tdata, output wire [7:0] output_axis_tdata,
output wire output_axis_tvalid, output wire output_axis_tvalid,
input wire output_axis_tready, input wire output_axis_tready,
output wire output_axis_tlast, output wire output_axis_tlast,
output wire output_axis_tuser, output wire output_axis_tuser,
/* /*
* Configuration * Configuration
*/ */
input wire [TAG_WIDTH-1:0] tag, input wire [TAG_WIDTH-1:0] tag,
input wire trigger, input wire trigger,
/* /*
* Status * Status
*/ */
output wire busy output wire busy
); );
localparam TAG_BYTE_WIDTH = (TAG_WIDTH + 7) / 8; localparam TAG_BYTE_WIDTH = (TAG_WIDTH + 7) / 8;
@ -213,18 +214,22 @@ always @* begin
// stats collection // stats collection
// increment tick count by number of words that can be transferred per cycle // increment tick count by number of words that can be transferred per cycle
tick_count_next = tick_count_next + KEEP_WIDTH; tick_count_next = tick_count_next + (KEEP_ENABLE ? KEEP_WIDTH : 1);
if (monitor_axis_tready & monitor_axis_tvalid) begin if (monitor_axis_tready & monitor_axis_tvalid) begin
// valid transfer cycle // valid transfer cycle
// increment byte count by number of words transferred // increment byte count by number of words transferred
bit_cnt = 0; if (KEEP_ENABLE) begin
for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin bit_cnt = 0;
//bit_cnt = bit_cnt + monitor_axis_tkeep[i]; for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin
if (monitor_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) bit_cnt = i; //bit_cnt = bit_cnt + monitor_axis_tkeep[i];
if (monitor_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) bit_cnt = i;
end
byte_count_next = byte_count_next + bit_cnt;
end else begin
byte_count_next = byte_count_next + 1;
end end
byte_count_next = byte_count_next + bit_cnt;
// count frames // count frames
if (monitor_axis_tlast) begin if (monitor_axis_tlast) begin
@ -298,7 +303,7 @@ always @* begin
store_axis_int_to_output = 1'b0; store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0; store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0; store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
// input is ready // input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin if (output_axis_tready | ~output_axis_tvalid_reg) begin

122
lib/axis/rtl/axis_switch.py
View File

@ -80,7 +80,13 @@ THE SOFTWARE.
module {{name}} # module {{name}} #
( (
parameter DATA_WIDTH = 8, parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_WIDTH = {{cn}}, parameter DEST_WIDTH = {{cn}},
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
{%- for p in range(n) %} {%- for p in range(n) %}
parameter OUT_{{p}}_BASE = {{p}}, parameter OUT_{{p}}_BASE = {{p}},
parameter OUT_{{p}}_TOP = {{p}}, parameter OUT_{{p}}_TOP = {{p}},
@ -100,22 +106,26 @@ module {{name}} #
*/ */
{%- for p in range(m) %} {%- for p in range(m) %}
input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata, input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep,
input wire input_{{p}}_axis_tvalid, input wire input_{{p}}_axis_tvalid,
output wire input_{{p}}_axis_tready, output wire input_{{p}}_axis_tready,
input wire input_{{p}}_axis_tlast, input wire input_{{p}}_axis_tlast,
input wire [ID_WIDTH-1:0] input_{{p}}_axis_tid,
input wire [DEST_WIDTH-1:0] input_{{p}}_axis_tdest, input wire [DEST_WIDTH-1:0] input_{{p}}_axis_tdest,
input wire input_{{p}}_axis_tuser, input wire [USER_WIDTH-1:0] input_{{p}}_axis_tuser,
{% endfor %} {% endfor %}
/* /*
* AXI Stream outputs * AXI Stream outputs
*/ */
{%- for p in range(n) %} {%- for p in range(n) %}
output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata, output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep,
output wire output_{{p}}_axis_tvalid, output wire output_{{p}}_axis_tvalid,
input wire output_{{p}}_axis_tready, input wire output_{{p}}_axis_tready,
output wire output_{{p}}_axis_tlast, output wire output_{{p}}_axis_tlast,
output wire [ID_WIDTH-1:0] output_{{p}}_axis_tid,
output wire [DEST_WIDTH-1:0] output_{{p}}_axis_tdest, output wire [DEST_WIDTH-1:0] output_{{p}}_axis_tdest,
output wire output_{{p}}_axis_tuser{% if not loop.last %},{% endif %} output wire [USER_WIDTH-1:0] output_{{p}}_axis_tuser{% if not loop.last %},{% endif %}
{% endfor -%} {% endfor -%}
); );
@ -162,13 +172,15 @@ reg input_{{p}}_axis_tready_reg = 1'b0, input_{{p}}_axis_tready_next;
// internal datapath // internal datapath
{%- for p in range(n) %} {%- for p in range(n) %}
reg [DATA_WIDTH-1:0] output_{{p}}_axis_tdata_int; reg [DATA_WIDTH-1:0] output_{{p}}_axis_tdata_int;
reg output_{{p}}_axis_tvalid_int; reg [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep_int;
reg output_{{p}}_axis_tready_int_reg = 1'b0; reg output_{{p}}_axis_tvalid_int;
reg output_{{p}}_axis_tlast_int; reg output_{{p}}_axis_tready_int_reg = 1'b0;
reg [DEST_WIDTH-1:0] output_{{p}}_axis_tdest_int; reg output_{{p}}_axis_tlast_int;
reg output_{{p}}_axis_tuser_int; reg [ID_WIDTH-1:0] output_{{p}}_axis_tid_int;
wire output_{{p}}_axis_tready_int_early; reg [DEST_WIDTH-1:0] output_{{p}}_axis_tdest_int;
reg [USER_WIDTH-1:0] output_{{p}}_axis_tuser_int;
wire output_{{p}}_axis_tready_int_early;
{% endfor %} {% endfor %}
{%- for p in range(m) %} {%- for p in range(m) %}
assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg; assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg;
@ -177,31 +189,37 @@ assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg;
// mux for incoming packet // mux for incoming packet
{% for p in range(n) %} {% for p in range(n) %}
reg [DATA_WIDTH-1:0] current_input_{{p}}_axis_tdata; reg [DATA_WIDTH-1:0] current_input_{{p}}_axis_tdata;
reg current_input_{{p}}_axis_tvalid; reg [DATA_WIDTH-1:0] current_input_{{p}}_axis_tkeep;
reg current_input_{{p}}_axis_tready; reg current_input_{{p}}_axis_tvalid;
reg current_input_{{p}}_axis_tlast; reg current_input_{{p}}_axis_tready;
reg current_input_{{p}}_axis_tlast;
reg [ID_WIDTH-1:0] current_input_{{p}}_axis_tid;
reg [DEST_WIDTH-1:0] current_input_{{p}}_axis_tdest; reg [DEST_WIDTH-1:0] current_input_{{p}}_axis_tdest;
reg current_input_{{p}}_axis_tuser; reg [USER_WIDTH-1:0] current_input_{{p}}_axis_tuser;
always @* begin always @* begin
case (select_{{p}}_reg) case (select_{{p}}_reg)
{%- for q in range(m) %} {%- for q in range(m) %}
{{cm}}'d{{q}}: begin {{cm}}'d{{q}}: begin
current_input_{{p}}_axis_tdata = input_{{q}}_axis_tdata; current_input_{{p}}_axis_tdata = input_{{q}}_axis_tdata;
current_input_{{p}}_axis_tkeep = input_{{q}}_axis_tkeep;
current_input_{{p}}_axis_tvalid = input_{{q}}_axis_tvalid; current_input_{{p}}_axis_tvalid = input_{{q}}_axis_tvalid;
current_input_{{p}}_axis_tready = input_{{q}}_axis_tready; current_input_{{p}}_axis_tready = input_{{q}}_axis_tready;
current_input_{{p}}_axis_tlast = input_{{q}}_axis_tlast; current_input_{{p}}_axis_tlast = input_{{q}}_axis_tlast;
current_input_{{p}}_axis_tdest = input_{{q}}_axis_tdest; current_input_{{p}}_axis_tid = input_{{q}}_axis_tid;
current_input_{{p}}_axis_tuser = input_{{q}}_axis_tuser; current_input_{{p}}_axis_tdest = input_{{q}}_axis_tdest;
current_input_{{p}}_axis_tuser = input_{{q}}_axis_tuser;
end end
{%- endfor %} {%- endfor %}
default: begin default: begin
current_input_{{p}}_axis_tdata = {DATA_WIDTH{1'b0}}; current_input_{{p}}_axis_tdata = {DATA_WIDTH{1'b0}};
current_input_{{p}}_axis_tkeep = {KEEP_WIDTH{1'b0}};
current_input_{{p}}_axis_tvalid = 1'b0; current_input_{{p}}_axis_tvalid = 1'b0;
current_input_{{p}}_axis_tready = 1'b0; current_input_{{p}}_axis_tready = 1'b0;
current_input_{{p}}_axis_tlast = 1'b0; current_input_{{p}}_axis_tlast = 1'b0;
current_input_{{p}}_axis_tdest = {DEST_WIDTH{1'b0}}; current_input_{{p}}_axis_tid = {ID_WIDTH{1'b0}};
current_input_{{p}}_axis_tuser = 1'b0; current_input_{{p}}_axis_tdest = {DEST_WIDTH{1'b0}};
current_input_{{p}}_axis_tuser = {USER_WIDTH{1'b0}};
end end
endcase endcase
end end
@ -260,11 +278,13 @@ always @* begin
input_{{p}}_axis_tready_next = 1'b0; input_{{p}}_axis_tready_next = 1'b0;
{%- endfor %} {%- endfor %}
{% for p in range(n) %} {% for p in range(n) %}
output_{{p}}_axis_tdata_int = {DATA_WIDTH{1'b0}}; output_{{p}}_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_{{p}}_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
output_{{p}}_axis_tvalid_int = 1'b0; output_{{p}}_axis_tvalid_int = 1'b0;
output_{{p}}_axis_tlast_int = 1'b0; output_{{p}}_axis_tlast_int = 1'b0;
output_{{p}}_axis_tdest_int = {DEST_WIDTH{1'b0}}; output_{{p}}_axis_tid_int = {ID_WIDTH{1'b0}};
output_{{p}}_axis_tuser_int = 1'b0; output_{{p}}_axis_tdest_int = {DEST_WIDTH{1'b0}};
output_{{p}}_axis_tuser_int = {USER_WIDTH{1'b0}};
{% endfor %} {% endfor %}
// input decoding // input decoding
{% for p in range(m) %} {% for p in range(m) %}
@ -316,11 +336,13 @@ always @* begin
// pass through selected packet data // pass through selected packet data
{% for p in range(n) %} {% for p in range(n) %}
output_{{p}}_axis_tdata_int = current_input_{{p}}_axis_tdata; output_{{p}}_axis_tdata_int = current_input_{{p}}_axis_tdata;
output_{{p}}_axis_tkeep_int = current_input_{{p}}_axis_tkeep;
output_{{p}}_axis_tvalid_int = current_input_{{p}}_axis_tvalid & current_input_{{p}}_axis_tready & enable_{{p}}_reg; output_{{p}}_axis_tvalid_int = current_input_{{p}}_axis_tvalid & current_input_{{p}}_axis_tready & enable_{{p}}_reg;
output_{{p}}_axis_tlast_int = current_input_{{p}}_axis_tlast; output_{{p}}_axis_tlast_int = current_input_{{p}}_axis_tlast;
output_{{p}}_axis_tdest_int = current_input_{{p}}_axis_tdest; output_{{p}}_axis_tid_int = current_input_{{p}}_axis_tid;
output_{{p}}_axis_tuser_int = current_input_{{p}}_axis_tuser; output_{{p}}_axis_tdest_int = current_input_{{p}}_axis_tdest;
output_{{p}}_axis_tuser_int = current_input_{{p}}_axis_tuser;
{% endfor -%} {% endfor -%}
end end
@ -359,28 +381,34 @@ always @(posedge clk) begin
end end
{% for p in range(n) %} {% for p in range(n) %}
// output {{p}} datapath logic // output {{p}} datapath logic
reg [DATA_WIDTH-1:0] output_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] output_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_{{p}}_axis_tvalid_reg = 1'b0, output_{{p}}_axis_tvalid_next; reg output_{{p}}_axis_tvalid_reg = 1'b0, output_{{p}}_axis_tvalid_next;
reg output_{{p}}_axis_tlast_reg = 1'b0; reg output_{{p}}_axis_tlast_reg = 1'b0;
reg [DEST_WIDTH-1:0] output_{{p}}_axis_tdest_reg = {DEST_WIDTH{1'b0}}; reg [ID_WIDTH-1:0] output_{{p}}_axis_tid_reg = {ID_WIDTH{1'b0}};
reg output_{{p}}_axis_tuser_reg = 1'b0; reg [DEST_WIDTH-1:0] output_{{p}}_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_{{p}}_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] temp_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_{{p}}_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_{{p}}_axis_tvalid_reg = 1'b0, temp_{{p}}_axis_tvalid_next; reg temp_{{p}}_axis_tvalid_reg = 1'b0, temp_{{p}}_axis_tvalid_next;
reg temp_{{p}}_axis_tlast_reg = 1'b0; reg temp_{{p}}_axis_tlast_reg = 1'b0;
reg [DEST_WIDTH-1:0] temp_{{p}}_axis_tdest_reg = {DEST_WIDTH{1'b0}}; reg [ID_WIDTH-1:0] temp_{{p}}_axis_tid_reg = {ID_WIDTH{1'b0}};
reg temp_{{p}}_axis_tuser_reg = 1'b0; reg [DEST_WIDTH-1:0] temp_{{p}}_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_{{p}}_axis_tuser_reg = 1'b0;
// datapath control // datapath control
reg store_{{p}}_axis_int_to_output; reg store_{{p}}_axis_int_to_output;
reg store_{{p}}_axis_int_to_temp; reg store_{{p}}_axis_int_to_temp;
reg store_{{p}}_axis_temp_to_output; reg store_{{p}}_axis_temp_to_output;
assign output_{{p}}_axis_tdata = output_{{p}}_axis_tdata_reg; assign output_{{p}}_axis_tdata = output_{{p}}_axis_tdata_reg;
assign output_{{p}}_axis_tkeep = KEEP_ENABLE ? output_{{p}}_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg; assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg;
assign output_{{p}}_axis_tlast = output_{{p}}_axis_tlast_reg; assign output_{{p}}_axis_tlast = output_{{p}}_axis_tlast_reg;
assign output_{{p}}_axis_tdest = output_{{p}}_axis_tdest_reg; assign output_{{p}}_axis_tid = ID_ENABLE ? output_{{p}}_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_{{p}}_axis_tuser = output_{{p}}_axis_tuser_reg; assign output_{{p}}_axis_tdest = output_{{p}}_axis_tdest_reg;
assign output_{{p}}_axis_tuser = USER_ENABLE ? output_{{p}}_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_{{p}}_axis_tready_int_early = output_{{p}}_axis_tready | (~temp_{{p}}_axis_tvalid_reg & (~output_{{p}}_axis_tvalid_reg | ~output_{{p}}_axis_tvalid_int)); assign output_{{p}}_axis_tready_int_early = output_{{p}}_axis_tready | (~temp_{{p}}_axis_tvalid_reg & (~output_{{p}}_axis_tvalid_reg | ~output_{{p}}_axis_tvalid_int));
@ -393,7 +421,7 @@ always @* begin
store_{{p}}_axis_int_to_output = 1'b0; store_{{p}}_axis_int_to_output = 1'b0;
store_{{p}}_axis_int_to_temp = 1'b0; store_{{p}}_axis_int_to_temp = 1'b0;
store_{{p}}_axis_temp_to_output = 1'b0; store_{{p}}_axis_temp_to_output = 1'b0;
if (output_{{p}}_axis_tready_int_reg) begin if (output_{{p}}_axis_tready_int_reg) begin
// input is ready // input is ready
if (output_{{p}}_axis_tready | ~output_{{p}}_axis_tvalid_reg) begin if (output_{{p}}_axis_tready | ~output_{{p}}_axis_tvalid_reg) begin
@ -427,19 +455,25 @@ always @(posedge clk) begin
// datapath // datapath
if (store_{{p}}_axis_int_to_output) begin if (store_{{p}}_axis_int_to_output) begin
output_{{p}}_axis_tdata_reg <= output_{{p}}_axis_tdata_int; output_{{p}}_axis_tdata_reg <= output_{{p}}_axis_tdata_int;
output_{{p}}_axis_tkeep_reg <= output_{{p}}_axis_tkeep_int;
output_{{p}}_axis_tlast_reg <= output_{{p}}_axis_tlast_int; output_{{p}}_axis_tlast_reg <= output_{{p}}_axis_tlast_int;
output_{{p}}_axis_tid_reg <= output_{{p}}_axis_tid_int;
output_{{p}}_axis_tdest_reg <= output_{{p}}_axis_tdest_int; output_{{p}}_axis_tdest_reg <= output_{{p}}_axis_tdest_int;
output_{{p}}_axis_tuser_reg <= output_{{p}}_axis_tuser_int; output_{{p}}_axis_tuser_reg <= output_{{p}}_axis_tuser_int;
end else if (store_{{p}}_axis_temp_to_output) begin end else if (store_{{p}}_axis_temp_to_output) begin
output_{{p}}_axis_tdata_reg <= temp_{{p}}_axis_tdata_reg; output_{{p}}_axis_tdata_reg <= temp_{{p}}_axis_tdata_reg;
output_{{p}}_axis_tkeep_reg <= temp_{{p}}_axis_tkeep_reg;
output_{{p}}_axis_tlast_reg <= temp_{{p}}_axis_tlast_reg; output_{{p}}_axis_tlast_reg <= temp_{{p}}_axis_tlast_reg;
output_{{p}}_axis_tid_reg <= temp_{{p}}_axis_tid_reg;
output_{{p}}_axis_tdest_reg <= temp_{{p}}_axis_tdest_reg; output_{{p}}_axis_tdest_reg <= temp_{{p}}_axis_tdest_reg;
output_{{p}}_axis_tuser_reg <= temp_{{p}}_axis_tuser_reg; output_{{p}}_axis_tuser_reg <= temp_{{p}}_axis_tuser_reg;
end end
if (store_{{p}}_axis_int_to_temp) begin if (store_{{p}}_axis_int_to_temp) begin
temp_{{p}}_axis_tdata_reg <= output_{{p}}_axis_tdata_int; temp_{{p}}_axis_tdata_reg <= output_{{p}}_axis_tdata_int;
temp_{{p}}_axis_tkeep_reg <= output_{{p}}_axis_tkeep_int;
temp_{{p}}_axis_tlast_reg <= output_{{p}}_axis_tlast_int; temp_{{p}}_axis_tlast_reg <= output_{{p}}_axis_tlast_int;
temp_{{p}}_axis_tid_reg <= output_{{p}}_axis_tid_int;
temp_{{p}}_axis_tdest_reg <= output_{{p}}_axis_tdest_int; temp_{{p}}_axis_tdest_reg <= output_{{p}}_axis_tdest_int;
temp_{{p}}_axis_tuser_reg <= output_{{p}}_axis_tuser_int; temp_{{p}}_axis_tuser_reg <= output_{{p}}_axis_tuser_int;
end end
@ -448,7 +482,7 @@ end
endmodule endmodule
""") """)
output_file.write(t.render( output_file.write(t.render(
m=m, m=m,
n=n, n=n,
@ -456,7 +490,7 @@ endmodule
cn=cn, cn=cn,
name=name name=name
)) ))
print("Done") print("Done")
if __name__ == "__main__": if __name__ == "__main__":

574
lib/axis/rtl/axis_switch_4x4.v
View File

@ -32,7 +32,13 @@ THE SOFTWARE.
module axis_switch_4x4 # module axis_switch_4x4 #
( (
parameter DATA_WIDTH = 8, parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_WIDTH = 2, parameter DEST_WIDTH = 2,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
parameter OUT_0_BASE = 0, parameter OUT_0_BASE = 0,
parameter OUT_0_TOP = 0, parameter OUT_0_TOP = 0,
parameter OUT_0_CONNECT = 4'b1111, parameter OUT_0_CONNECT = 4'b1111,
@ -58,63 +64,79 @@ module axis_switch_4x4 #
* AXI Stream inputs * AXI Stream inputs
*/ */
input wire [DATA_WIDTH-1:0] input_0_axis_tdata, input wire [DATA_WIDTH-1:0] input_0_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_0_axis_tkeep,
input wire input_0_axis_tvalid, input wire input_0_axis_tvalid,
output wire input_0_axis_tready, output wire input_0_axis_tready,
input wire input_0_axis_tlast, input wire input_0_axis_tlast,
input wire [ID_WIDTH-1:0] input_0_axis_tid,
input wire [DEST_WIDTH-1:0] input_0_axis_tdest, input wire [DEST_WIDTH-1:0] input_0_axis_tdest,
input wire input_0_axis_tuser, input wire [USER_WIDTH-1:0] input_0_axis_tuser,
input wire [DATA_WIDTH-1:0] input_1_axis_tdata, input wire [DATA_WIDTH-1:0] input_1_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_1_axis_tkeep,
input wire input_1_axis_tvalid, input wire input_1_axis_tvalid,
output wire input_1_axis_tready, output wire input_1_axis_tready,
input wire input_1_axis_tlast, input wire input_1_axis_tlast,
input wire [ID_WIDTH-1:0] input_1_axis_tid,
input wire [DEST_WIDTH-1:0] input_1_axis_tdest, input wire [DEST_WIDTH-1:0] input_1_axis_tdest,
input wire input_1_axis_tuser, input wire [USER_WIDTH-1:0] input_1_axis_tuser,
input wire [DATA_WIDTH-1:0] input_2_axis_tdata, input wire [DATA_WIDTH-1:0] input_2_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_2_axis_tkeep,
input wire input_2_axis_tvalid, input wire input_2_axis_tvalid,
output wire input_2_axis_tready, output wire input_2_axis_tready,
input wire input_2_axis_tlast, input wire input_2_axis_tlast,
input wire [ID_WIDTH-1:0] input_2_axis_tid,
input wire [DEST_WIDTH-1:0] input_2_axis_tdest, input wire [DEST_WIDTH-1:0] input_2_axis_tdest,
input wire input_2_axis_tuser, input wire [USER_WIDTH-1:0] input_2_axis_tuser,
input wire [DATA_WIDTH-1:0] input_3_axis_tdata, input wire [DATA_WIDTH-1:0] input_3_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_3_axis_tkeep,
input wire input_3_axis_tvalid, input wire input_3_axis_tvalid,
output wire input_3_axis_tready, output wire input_3_axis_tready,
input wire input_3_axis_tlast, input wire input_3_axis_tlast,
input wire [ID_WIDTH-1:0] input_3_axis_tid,
input wire [DEST_WIDTH-1:0] input_3_axis_tdest, input wire [DEST_WIDTH-1:0] input_3_axis_tdest,
input wire input_3_axis_tuser, input wire [USER_WIDTH-1:0] input_3_axis_tuser,
/* /*
* AXI Stream outputs * AXI Stream outputs
*/ */
output wire [DATA_WIDTH-1:0] output_0_axis_tdata, output wire [DATA_WIDTH-1:0] output_0_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_0_axis_tkeep,
output wire output_0_axis_tvalid, output wire output_0_axis_tvalid,
input wire output_0_axis_tready, input wire output_0_axis_tready,
output wire output_0_axis_tlast, output wire output_0_axis_tlast,
output wire [ID_WIDTH-1:0] output_0_axis_tid,
output wire [DEST_WIDTH-1:0] output_0_axis_tdest, output wire [DEST_WIDTH-1:0] output_0_axis_tdest,
output wire output_0_axis_tuser, output wire [USER_WIDTH-1:0] output_0_axis_tuser,
output wire [DATA_WIDTH-1:0] output_1_axis_tdata, output wire [DATA_WIDTH-1:0] output_1_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_1_axis_tkeep,
output wire output_1_axis_tvalid, output wire output_1_axis_tvalid,
input wire output_1_axis_tready, input wire output_1_axis_tready,
output wire output_1_axis_tlast, output wire output_1_axis_tlast,
output wire [ID_WIDTH-1:0] output_1_axis_tid,
output wire [DEST_WIDTH-1:0] output_1_axis_tdest, output wire [DEST_WIDTH-1:0] output_1_axis_tdest,
output wire output_1_axis_tuser, output wire [USER_WIDTH-1:0] output_1_axis_tuser,
output wire [DATA_WIDTH-1:0] output_2_axis_tdata, output wire [DATA_WIDTH-1:0] output_2_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_2_axis_tkeep,
output wire output_2_axis_tvalid, output wire output_2_axis_tvalid,
input wire output_2_axis_tready, input wire output_2_axis_tready,
output wire output_2_axis_tlast, output wire output_2_axis_tlast,
output wire [ID_WIDTH-1:0] output_2_axis_tid,
output wire [DEST_WIDTH-1:0] output_2_axis_tdest, output wire [DEST_WIDTH-1:0] output_2_axis_tdest,
output wire output_2_axis_tuser, output wire [USER_WIDTH-1:0] output_2_axis_tuser,
output wire [DATA_WIDTH-1:0] output_3_axis_tdata, output wire [DATA_WIDTH-1:0] output_3_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_3_axis_tkeep,
output wire output_3_axis_tvalid, output wire output_3_axis_tvalid,
input wire output_3_axis_tready, input wire output_3_axis_tready,
output wire output_3_axis_tlast, output wire output_3_axis_tlast,
output wire [ID_WIDTH-1:0] output_3_axis_tid,
output wire [DEST_WIDTH-1:0] output_3_axis_tdest, output wire [DEST_WIDTH-1:0] output_3_axis_tdest,
output wire output_3_axis_tuser output wire [USER_WIDTH-1:0] output_3_axis_tuser
); );
// check configuration // check configuration
@ -183,37 +205,45 @@ reg input_2_axis_tready_reg = 1'b0, input_2_axis_tready_next;
reg input_3_axis_tready_reg = 1'b0, input_3_axis_tready_next; reg input_3_axis_tready_reg = 1'b0, input_3_axis_tready_next;
// internal datapath // internal datapath
reg [DATA_WIDTH-1:0] output_0_axis_tdata_int; reg [DATA_WIDTH-1:0] output_0_axis_tdata_int;
reg output_0_axis_tvalid_int; reg [KEEP_WIDTH-1:0] output_0_axis_tkeep_int;
reg output_0_axis_tready_int_reg = 1'b0; reg output_0_axis_tvalid_int;
reg output_0_axis_tlast_int; reg output_0_axis_tready_int_reg = 1'b0;
reg [DEST_WIDTH-1:0] output_0_axis_tdest_int; reg output_0_axis_tlast_int;
reg output_0_axis_tuser_int; reg [ID_WIDTH-1:0] output_0_axis_tid_int;
wire output_0_axis_tready_int_early; reg [DEST_WIDTH-1:0] output_0_axis_tdest_int;
reg [USER_WIDTH-1:0] output_0_axis_tuser_int;
wire output_0_axis_tready_int_early;
reg [DATA_WIDTH-1:0] output_1_axis_tdata_int; reg [DATA_WIDTH-1:0] output_1_axis_tdata_int;
reg output_1_axis_tvalid_int; reg [KEEP_WIDTH-1:0] output_1_axis_tkeep_int;
reg output_1_axis_tready_int_reg = 1'b0; reg output_1_axis_tvalid_int;
reg output_1_axis_tlast_int; reg output_1_axis_tready_int_reg = 1'b0;
reg [DEST_WIDTH-1:0] output_1_axis_tdest_int; reg output_1_axis_tlast_int;
reg output_1_axis_tuser_int; reg [ID_WIDTH-1:0] output_1_axis_tid_int;
wire output_1_axis_tready_int_early; reg [DEST_WIDTH-1:0] output_1_axis_tdest_int;
reg [USER_WIDTH-1:0] output_1_axis_tuser_int;
wire output_1_axis_tready_int_early;
reg [DATA_WIDTH-1:0] output_2_axis_tdata_int; reg [DATA_WIDTH-1:0] output_2_axis_tdata_int;
reg output_2_axis_tvalid_int; reg [KEEP_WIDTH-1:0] output_2_axis_tkeep_int;
reg output_2_axis_tready_int_reg = 1'b0; reg output_2_axis_tvalid_int;
reg output_2_axis_tlast_int; reg output_2_axis_tready_int_reg = 1'b0;
reg [DEST_WIDTH-1:0] output_2_axis_tdest_int; reg output_2_axis_tlast_int;
reg output_2_axis_tuser_int; reg [ID_WIDTH-1:0] output_2_axis_tid_int;
wire output_2_axis_tready_int_early; reg [DEST_WIDTH-1:0] output_2_axis_tdest_int;
reg [USER_WIDTH-1:0] output_2_axis_tuser_int;
wire output_2_axis_tready_int_early;
reg [DATA_WIDTH-1:0] output_3_axis_tdata_int; reg [DATA_WIDTH-1:0] output_3_axis_tdata_int;
reg output_3_axis_tvalid_int; reg [KEEP_WIDTH-1:0] output_3_axis_tkeep_int;
reg output_3_axis_tready_int_reg = 1'b0; reg output_3_axis_tvalid_int;
reg output_3_axis_tlast_int; reg output_3_axis_tready_int_reg = 1'b0;
reg [DEST_WIDTH-1:0] output_3_axis_tdest_int; reg output_3_axis_tlast_int;
reg output_3_axis_tuser_int; reg [ID_WIDTH-1:0] output_3_axis_tid_int;
wire output_3_axis_tready_int_early; reg [DEST_WIDTH-1:0] output_3_axis_tdest_int;
reg [USER_WIDTH-1:0] output_3_axis_tuser_int;
wire output_3_axis_tready_int_early;
assign input_0_axis_tready = input_0_axis_tready_reg; assign input_0_axis_tready = input_0_axis_tready_reg;
assign input_1_axis_tready = input_1_axis_tready_reg; assign input_1_axis_tready = input_1_axis_tready_reg;
@ -223,209 +253,257 @@ assign input_3_axis_tready = input_3_axis_tready_reg;
// mux for incoming packet // mux for incoming packet
reg [DATA_WIDTH-1:0] current_input_0_axis_tdata; reg [DATA_WIDTH-1:0] current_input_0_axis_tdata;
reg current_input_0_axis_tvalid; reg [DATA_WIDTH-1:0] current_input_0_axis_tkeep;
reg current_input_0_axis_tready; reg current_input_0_axis_tvalid;
reg current_input_0_axis_tlast; reg current_input_0_axis_tready;
reg current_input_0_axis_tlast;
reg [ID_WIDTH-1:0] current_input_0_axis_tid;
reg [DEST_WIDTH-1:0] current_input_0_axis_tdest; reg [DEST_WIDTH-1:0] current_input_0_axis_tdest;
reg current_input_0_axis_tuser; reg [USER_WIDTH-1:0] current_input_0_axis_tuser;
always @* begin always @* begin
case (select_0_reg) case (select_0_reg)
2'd0: begin 2'd0: begin
current_input_0_axis_tdata = input_0_axis_tdata; current_input_0_axis_tdata = input_0_axis_tdata;
current_input_0_axis_tkeep = input_0_axis_tkeep;
current_input_0_axis_tvalid = input_0_axis_tvalid; current_input_0_axis_tvalid = input_0_axis_tvalid;
current_input_0_axis_tready = input_0_axis_tready; current_input_0_axis_tready = input_0_axis_tready;
current_input_0_axis_tlast = input_0_axis_tlast; current_input_0_axis_tlast = input_0_axis_tlast;
current_input_0_axis_tdest = input_0_axis_tdest; current_input_0_axis_tid = input_0_axis_tid;
current_input_0_axis_tuser = input_0_axis_tuser; current_input_0_axis_tdest = input_0_axis_tdest;
current_input_0_axis_tuser = input_0_axis_tuser;
end end
2'd1: begin 2'd1: begin
current_input_0_axis_tdata = input_1_axis_tdata; current_input_0_axis_tdata = input_1_axis_tdata;
current_input_0_axis_tkeep = input_1_axis_tkeep;
current_input_0_axis_tvalid = input_1_axis_tvalid; current_input_0_axis_tvalid = input_1_axis_tvalid;
current_input_0_axis_tready = input_1_axis_tready; current_input_0_axis_tready = input_1_axis_tready;
current_input_0_axis_tlast = input_1_axis_tlast; current_input_0_axis_tlast = input_1_axis_tlast;
current_input_0_axis_tdest = input_1_axis_tdest; current_input_0_axis_tid = input_1_axis_tid;
current_input_0_axis_tuser = input_1_axis_tuser; current_input_0_axis_tdest = input_1_axis_tdest;
current_input_0_axis_tuser = input_1_axis_tuser;
end end
2'd2: begin 2'd2: begin
current_input_0_axis_tdata = input_2_axis_tdata; current_input_0_axis_tdata = input_2_axis_tdata;
current_input_0_axis_tkeep = input_2_axis_tkeep;
current_input_0_axis_tvalid = input_2_axis_tvalid; current_input_0_axis_tvalid = input_2_axis_tvalid;
current_input_0_axis_tready = input_2_axis_tready; current_input_0_axis_tready = input_2_axis_tready;
current_input_0_axis_tlast = input_2_axis_tlast; current_input_0_axis_tlast = input_2_axis_tlast;
current_input_0_axis_tdest = input_2_axis_tdest; current_input_0_axis_tid = input_2_axis_tid;
current_input_0_axis_tuser = input_2_axis_tuser; current_input_0_axis_tdest = input_2_axis_tdest;
current_input_0_axis_tuser = input_2_axis_tuser;
end end
2'd3: begin 2'd3: begin
current_input_0_axis_tdata = input_3_axis_tdata; current_input_0_axis_tdata = input_3_axis_tdata;
current_input_0_axis_tkeep = input_3_axis_tkeep;
current_input_0_axis_tvalid = input_3_axis_tvalid; current_input_0_axis_tvalid = input_3_axis_tvalid;
current_input_0_axis_tready = input_3_axis_tready; current_input_0_axis_tready = input_3_axis_tready;
current_input_0_axis_tlast = input_3_axis_tlast; current_input_0_axis_tlast = input_3_axis_tlast;
current_input_0_axis_tdest = input_3_axis_tdest; current_input_0_axis_tid = input_3_axis_tid;
current_input_0_axis_tuser = input_3_axis_tuser; current_input_0_axis_tdest = input_3_axis_tdest;
current_input_0_axis_tuser = input_3_axis_tuser;
end end
default: begin default: begin
current_input_0_axis_tdata = {DATA_WIDTH{1'b0}}; current_input_0_axis_tdata = {DATA_WIDTH{1'b0}};
current_input_0_axis_tkeep = {KEEP_WIDTH{1'b0}};
current_input_0_axis_tvalid = 1'b0; current_input_0_axis_tvalid = 1'b0;
current_input_0_axis_tready = 1'b0; current_input_0_axis_tready = 1'b0;
current_input_0_axis_tlast = 1'b0; current_input_0_axis_tlast = 1'b0;
current_input_0_axis_tdest = {DEST_WIDTH{1'b0}}; current_input_0_axis_tid = {ID_WIDTH{1'b0}};
current_input_0_axis_tuser = 1'b0; current_input_0_axis_tdest = {DEST_WIDTH{1'b0}};
current_input_0_axis_tuser = {USER_WIDTH{1'b0}};
end end
endcase endcase
end end
reg [DATA_WIDTH-1:0] current_input_1_axis_tdata; reg [DATA_WIDTH-1:0] current_input_1_axis_tdata;
reg current_input_1_axis_tvalid; reg [DATA_WIDTH-1:0] current_input_1_axis_tkeep;
reg current_input_1_axis_tready; reg current_input_1_axis_tvalid;
reg current_input_1_axis_tlast; reg current_input_1_axis_tready;
reg current_input_1_axis_tlast;
reg [ID_WIDTH-1:0] current_input_1_axis_tid;
reg [DEST_WIDTH-1:0] current_input_1_axis_tdest; reg [DEST_WIDTH-1:0] current_input_1_axis_tdest;
reg current_input_1_axis_tuser; reg [USER_WIDTH-1:0] current_input_1_axis_tuser;
always @* begin always @* begin
case (select_1_reg) case (select_1_reg)
2'd0: begin 2'd0: begin
current_input_1_axis_tdata = input_0_axis_tdata; current_input_1_axis_tdata = input_0_axis_tdata;
current_input_1_axis_tkeep = input_0_axis_tkeep;
current_input_1_axis_tvalid = input_0_axis_tvalid; current_input_1_axis_tvalid = input_0_axis_tvalid;
current_input_1_axis_tready = input_0_axis_tready; current_input_1_axis_tready = input_0_axis_tready;
current_input_1_axis_tlast = input_0_axis_tlast; current_input_1_axis_tlast = input_0_axis_tlast;
current_input_1_axis_tdest = input_0_axis_tdest; current_input_1_axis_tid = input_0_axis_tid;
current_input_1_axis_tuser = input_0_axis_tuser; current_input_1_axis_tdest = input_0_axis_tdest;
current_input_1_axis_tuser = input_0_axis_tuser;
end end
2'd1: begin 2'd1: begin
current_input_1_axis_tdata = input_1_axis_tdata; current_input_1_axis_tdata = input_1_axis_tdata;
current_input_1_axis_tkeep = input_1_axis_tkeep;
current_input_1_axis_tvalid = input_1_axis_tvalid; current_input_1_axis_tvalid = input_1_axis_tvalid;
current_input_1_axis_tready = input_1_axis_tready; current_input_1_axis_tready = input_1_axis_tready;
current_input_1_axis_tlast = input_1_axis_tlast; current_input_1_axis_tlast = input_1_axis_tlast;
current_input_1_axis_tdest = input_1_axis_tdest; current_input_1_axis_tid = input_1_axis_tid;
current_input_1_axis_tuser = input_1_axis_tuser; current_input_1_axis_tdest = input_1_axis_tdest;
current_input_1_axis_tuser = input_1_axis_tuser;
end end
2'd2: begin 2'd2: begin
current_input_1_axis_tdata = input_2_axis_tdata; current_input_1_axis_tdata = input_2_axis_tdata;
current_input_1_axis_tkeep = input_2_axis_tkeep;
current_input_1_axis_tvalid = input_2_axis_tvalid; current_input_1_axis_tvalid = input_2_axis_tvalid;
current_input_1_axis_tready = input_2_axis_tready; current_input_1_axis_tready = input_2_axis_tready;
current_input_1_axis_tlast = input_2_axis_tlast; current_input_1_axis_tlast = input_2_axis_tlast;
current_input_1_axis_tdest = input_2_axis_tdest; current_input_1_axis_tid = input_2_axis_tid;
current_input_1_axis_tuser = input_2_axis_tuser; current_input_1_axis_tdest = input_2_axis_tdest;
current_input_1_axis_tuser = input_2_axis_tuser;
end end
2'd3: begin 2'd3: begin
current_input_1_axis_tdata = input_3_axis_tdata; current_input_1_axis_tdata = input_3_axis_tdata;
current_input_1_axis_tkeep = input_3_axis_tkeep;
current_input_1_axis_tvalid = input_3_axis_tvalid; current_input_1_axis_tvalid = input_3_axis_tvalid;
current_input_1_axis_tready = input_3_axis_tready; current_input_1_axis_tready = input_3_axis_tready;
current_input_1_axis_tlast = input_3_axis_tlast; current_input_1_axis_tlast = input_3_axis_tlast;
current_input_1_axis_tdest = input_3_axis_tdest; current_input_1_axis_tid = input_3_axis_tid;
current_input_1_axis_tuser = input_3_axis_tuser; current_input_1_axis_tdest = input_3_axis_tdest;
current_input_1_axis_tuser = input_3_axis_tuser;
end end
default: begin default: begin
current_input_1_axis_tdata = {DATA_WIDTH{1'b0}}; current_input_1_axis_tdata = {DATA_WIDTH{1'b0}};
current_input_1_axis_tkeep = {KEEP_WIDTH{1'b0}};
current_input_1_axis_tvalid = 1'b0; current_input_1_axis_tvalid = 1'b0;
current_input_1_axis_tready = 1'b0; current_input_1_axis_tready = 1'b0;
current_input_1_axis_tlast = 1'b0; current_input_1_axis_tlast = 1'b0;
current_input_1_axis_tdest = {DEST_WIDTH{1'b0}}; current_input_1_axis_tid = {ID_WIDTH{1'b0}};
current_input_1_axis_tuser = 1'b0; current_input_1_axis_tdest = {DEST_WIDTH{1'b0}};
current_input_1_axis_tuser = {USER_WIDTH{1'b0}};
end end
endcase endcase
end end
reg [DATA_WIDTH-1:0] current_input_2_axis_tdata; reg [DATA_WIDTH-1:0] current_input_2_axis_tdata;
reg current_input_2_axis_tvalid; reg [DATA_WIDTH-1:0] current_input_2_axis_tkeep;
reg current_input_2_axis_tready; reg current_input_2_axis_tvalid;
reg current_input_2_axis_tlast; reg current_input_2_axis_tready;
reg current_input_2_axis_tlast;
reg [ID_WIDTH-1:0] current_input_2_axis_tid;
reg [DEST_WIDTH-1:0] current_input_2_axis_tdest; reg [DEST_WIDTH-1:0] current_input_2_axis_tdest;
reg current_input_2_axis_tuser; reg [USER_WIDTH-1:0] current_input_2_axis_tuser;
always @* begin always @* begin
case (select_2_reg) case (select_2_reg)
2'd0: begin 2'd0: begin
current_input_2_axis_tdata = input_0_axis_tdata; current_input_2_axis_tdata = input_0_axis_tdata;
current_input_2_axis_tkeep = input_0_axis_tkeep;
current_input_2_axis_tvalid = input_0_axis_tvalid; current_input_2_axis_tvalid = input_0_axis_tvalid;
current_input_2_axis_tready = input_0_axis_tready; current_input_2_axis_tready = input_0_axis_tready;
current_input_2_axis_tlast = input_0_axis_tlast; current_input_2_axis_tlast = input_0_axis_tlast;
current_input_2_axis_tdest = input_0_axis_tdest; current_input_2_axis_tid = input_0_axis_tid;
current_input_2_axis_tuser = input_0_axis_tuser; current_input_2_axis_tdest = input_0_axis_tdest;
current_input_2_axis_tuser = input_0_axis_tuser;
end end
2'd1: begin 2'd1: begin
current_input_2_axis_tdata = input_1_axis_tdata; current_input_2_axis_tdata = input_1_axis_tdata;
current_input_2_axis_tkeep = input_1_axis_tkeep;
current_input_2_axis_tvalid = input_1_axis_tvalid; current_input_2_axis_tvalid = input_1_axis_tvalid;
current_input_2_axis_tready = input_1_axis_tready; current_input_2_axis_tready = input_1_axis_tready;
current_input_2_axis_tlast = input_1_axis_tlast; current_input_2_axis_tlast = input_1_axis_tlast;
current_input_2_axis_tdest = input_1_axis_tdest; current_input_2_axis_tid = input_1_axis_tid;
current_input_2_axis_tuser = input_1_axis_tuser; current_input_2_axis_tdest = input_1_axis_tdest;
current_input_2_axis_tuser = input_1_axis_tuser;
end end
2'd2: begin 2'd2: begin
current_input_2_axis_tdata = input_2_axis_tdata; current_input_2_axis_tdata = input_2_axis_tdata;
current_input_2_axis_tkeep = input_2_axis_tkeep;
current_input_2_axis_tvalid = input_2_axis_tvalid; current_input_2_axis_tvalid = input_2_axis_tvalid;
current_input_2_axis_tready = input_2_axis_tready; current_input_2_axis_tready = input_2_axis_tready;
current_input_2_axis_tlast = input_2_axis_tlast; current_input_2_axis_tlast = input_2_axis_tlast;
current_input_2_axis_tdest = input_2_axis_tdest; current_input_2_axis_tid = input_2_axis_tid;
current_input_2_axis_tuser = input_2_axis_tuser; current_input_2_axis_tdest = input_2_axis_tdest;
current_input_2_axis_tuser = input_2_axis_tuser;
end end
2'd3: begin 2'd3: begin
current_input_2_axis_tdata = input_3_axis_tdata; current_input_2_axis_tdata = input_3_axis_tdata;
current_input_2_axis_tkeep = input_3_axis_tkeep;
current_input_2_axis_tvalid = input_3_axis_tvalid; current_input_2_axis_tvalid = input_3_axis_tvalid;
current_input_2_axis_tready = input_3_axis_tready; current_input_2_axis_tready = input_3_axis_tready;
current_input_2_axis_tlast = input_3_axis_tlast; current_input_2_axis_tlast = input_3_axis_tlast;
current_input_2_axis_tdest = input_3_axis_tdest; current_input_2_axis_tid = input_3_axis_tid;
current_input_2_axis_tuser = input_3_axis_tuser; current_input_2_axis_tdest = input_3_axis_tdest;
current_input_2_axis_tuser = input_3_axis_tuser;
end end
default: begin default: begin
current_input_2_axis_tdata = {DATA_WIDTH{1'b0}}; current_input_2_axis_tdata = {DATA_WIDTH{1'b0}};
current_input_2_axis_tkeep = {KEEP_WIDTH{1'b0}};
current_input_2_axis_tvalid = 1'b0; current_input_2_axis_tvalid = 1'b0;
current_input_2_axis_tready = 1'b0; current_input_2_axis_tready = 1'b0;
current_input_2_axis_tlast = 1'b0; current_input_2_axis_tlast = 1'b0;
current_input_2_axis_tdest = {DEST_WIDTH{1'b0}}; current_input_2_axis_tid = {ID_WIDTH{1'b0}};
current_input_2_axis_tuser = 1'b0; current_input_2_axis_tdest = {DEST_WIDTH{1'b0}};
current_input_2_axis_tuser = {USER_WIDTH{1'b0}};
end end
endcase endcase
end end
reg [DATA_WIDTH-1:0] current_input_3_axis_tdata; reg [DATA_WIDTH-1:0] current_input_3_axis_tdata;
reg current_input_3_axis_tvalid; reg [DATA_WIDTH-1:0] current_input_3_axis_tkeep;
reg current_input_3_axis_tready; reg current_input_3_axis_tvalid;
reg current_input_3_axis_tlast; reg current_input_3_axis_tready;
reg current_input_3_axis_tlast;
reg [ID_WIDTH-1:0] current_input_3_axis_tid;
reg [DEST_WIDTH-1:0] current_input_3_axis_tdest; reg [DEST_WIDTH-1:0] current_input_3_axis_tdest;
reg current_input_3_axis_tuser; reg [USER_WIDTH-1:0] current_input_3_axis_tuser;
always @* begin always @* begin
case (select_3_reg) case (select_3_reg)
2'd0: begin 2'd0: begin
current_input_3_axis_tdata = input_0_axis_tdata; current_input_3_axis_tdata = input_0_axis_tdata;
current_input_3_axis_tkeep = input_0_axis_tkeep;
current_input_3_axis_tvalid = input_0_axis_tvalid; current_input_3_axis_tvalid = input_0_axis_tvalid;
current_input_3_axis_tready = input_0_axis_tready; current_input_3_axis_tready = input_0_axis_tready;
current_input_3_axis_tlast = input_0_axis_tlast; current_input_3_axis_tlast = input_0_axis_tlast;
current_input_3_axis_tdest = input_0_axis_tdest; current_input_3_axis_tid = input_0_axis_tid;
current_input_3_axis_tuser = input_0_axis_tuser; current_input_3_axis_tdest = input_0_axis_tdest;
current_input_3_axis_tuser = input_0_axis_tuser;
end end
2'd1: begin 2'd1: begin
current_input_3_axis_tdata = input_1_axis_tdata; current_input_3_axis_tdata = input_1_axis_tdata;
current_input_3_axis_tkeep = input_1_axis_tkeep;
current_input_3_axis_tvalid = input_1_axis_tvalid; current_input_3_axis_tvalid = input_1_axis_tvalid;
current_input_3_axis_tready = input_1_axis_tready; current_input_3_axis_tready = input_1_axis_tready;
current_input_3_axis_tlast = input_1_axis_tlast; current_input_3_axis_tlast = input_1_axis_tlast;
current_input_3_axis_tdest = input_1_axis_tdest; current_input_3_axis_tid = input_1_axis_tid;
current_input_3_axis_tuser = input_1_axis_tuser; current_input_3_axis_tdest = input_1_axis_tdest;
current_input_3_axis_tuser = input_1_axis_tuser;
end end
2'd2: begin 2'd2: begin
current_input_3_axis_tdata = input_2_axis_tdata; current_input_3_axis_tdata = input_2_axis_tdata;
current_input_3_axis_tkeep = input_2_axis_tkeep;
current_input_3_axis_tvalid = input_2_axis_tvalid; current_input_3_axis_tvalid = input_2_axis_tvalid;
current_input_3_axis_tready = input_2_axis_tready; current_input_3_axis_tready = input_2_axis_tready;
current_input_3_axis_tlast = input_2_axis_tlast; current_input_3_axis_tlast = input_2_axis_tlast;
current_input_3_axis_tdest = input_2_axis_tdest; current_input_3_axis_tid = input_2_axis_tid;
current_input_3_axis_tuser = input_2_axis_tuser; current_input_3_axis_tdest = input_2_axis_tdest;
current_input_3_axis_tuser = input_2_axis_tuser;
end end
2'd3: begin 2'd3: begin
current_input_3_axis_tdata = input_3_axis_tdata; current_input_3_axis_tdata = input_3_axis_tdata;
current_input_3_axis_tkeep = input_3_axis_tkeep;
current_input_3_axis_tvalid = input_3_axis_tvalid; current_input_3_axis_tvalid = input_3_axis_tvalid;
current_input_3_axis_tready = input_3_axis_tready; current_input_3_axis_tready = input_3_axis_tready;
current_input_3_axis_tlast = input_3_axis_tlast; current_input_3_axis_tlast = input_3_axis_tlast;
current_input_3_axis_tdest = input_3_axis_tdest; current_input_3_axis_tid = input_3_axis_tid;
current_input_3_axis_tuser = input_3_axis_tuser; current_input_3_axis_tdest = input_3_axis_tdest;
current_input_3_axis_tuser = input_3_axis_tuser;
end end
default: begin default: begin
current_input_3_axis_tdata = {DATA_WIDTH{1'b0}}; current_input_3_axis_tdata = {DATA_WIDTH{1'b0}};
current_input_3_axis_tkeep = {KEEP_WIDTH{1'b0}};
current_input_3_axis_tvalid = 1'b0; current_input_3_axis_tvalid = 1'b0;
current_input_3_axis_tready = 1'b0; current_input_3_axis_tready = 1'b0;
current_input_3_axis_tlast = 1'b0; current_input_3_axis_tlast = 1'b0;
current_input_3_axis_tdest = {DEST_WIDTH{1'b0}}; current_input_3_axis_tid = {ID_WIDTH{1'b0}};
current_input_3_axis_tuser = 1'b0; current_input_3_axis_tdest = {DEST_WIDTH{1'b0}};
current_input_3_axis_tuser = {USER_WIDTH{1'b0}};
end end
endcase endcase
end end
@ -594,29 +672,37 @@ always @* begin
input_2_axis_tready_next = 1'b0; input_2_axis_tready_next = 1'b0;
input_3_axis_tready_next = 1'b0; input_3_axis_tready_next = 1'b0;
output_0_axis_tdata_int = {DATA_WIDTH{1'b0}}; output_0_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_0_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
output_0_axis_tvalid_int = 1'b0; output_0_axis_tvalid_int = 1'b0;
output_0_axis_tlast_int = 1'b0; output_0_axis_tlast_int = 1'b0;
output_0_axis_tdest_int = {DEST_WIDTH{1'b0}}; output_0_axis_tid_int = {ID_WIDTH{1'b0}};
output_0_axis_tuser_int = 1'b0; output_0_axis_tdest_int = {DEST_WIDTH{1'b0}};
output_0_axis_tuser_int = {USER_WIDTH{1'b0}};
output_1_axis_tdata_int = {DATA_WIDTH{1'b0}}; output_1_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_1_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
output_1_axis_tvalid_int = 1'b0; output_1_axis_tvalid_int = 1'b0;
output_1_axis_tlast_int = 1'b0; output_1_axis_tlast_int = 1'b0;
output_1_axis_tdest_int = {DEST_WIDTH{1'b0}}; output_1_axis_tid_int = {ID_WIDTH{1'b0}};
output_1_axis_tuser_int = 1'b0; output_1_axis_tdest_int = {DEST_WIDTH{1'b0}};
output_1_axis_tuser_int = {USER_WIDTH{1'b0}};
output_2_axis_tdata_int = {DATA_WIDTH{1'b0}}; output_2_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_2_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
output_2_axis_tvalid_int = 1'b0; output_2_axis_tvalid_int = 1'b0;
output_2_axis_tlast_int = 1'b0; output_2_axis_tlast_int = 1'b0;
output_2_axis_tdest_int = {DEST_WIDTH{1'b0}}; output_2_axis_tid_int = {ID_WIDTH{1'b0}};
output_2_axis_tuser_int = 1'b0; output_2_axis_tdest_int = {DEST_WIDTH{1'b0}};
output_2_axis_tuser_int = {USER_WIDTH{1'b0}};
output_3_axis_tdata_int = {DATA_WIDTH{1'b0}}; output_3_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_3_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
output_3_axis_tvalid_int = 1'b0; output_3_axis_tvalid_int = 1'b0;
output_3_axis_tlast_int = 1'b0; output_3_axis_tlast_int = 1'b0;
output_3_axis_tdest_int = {DEST_WIDTH{1'b0}}; output_3_axis_tid_int = {ID_WIDTH{1'b0}};
output_3_axis_tuser_int = 1'b0; output_3_axis_tdest_int = {DEST_WIDTH{1'b0}};
output_3_axis_tuser_int = {USER_WIDTH{1'b0}};
// input decoding // input decoding
@ -787,29 +873,37 @@ always @* begin
// pass through selected packet data // pass through selected packet data
output_0_axis_tdata_int = current_input_0_axis_tdata; output_0_axis_tdata_int = current_input_0_axis_tdata;
output_0_axis_tkeep_int = current_input_0_axis_tkeep;
output_0_axis_tvalid_int = current_input_0_axis_tvalid & current_input_0_axis_tready & enable_0_reg; output_0_axis_tvalid_int = current_input_0_axis_tvalid & current_input_0_axis_tready & enable_0_reg;
output_0_axis_tlast_int = current_input_0_axis_tlast; output_0_axis_tlast_int = current_input_0_axis_tlast;
output_0_axis_tdest_int = current_input_0_axis_tdest; output_0_axis_tid_int = current_input_0_axis_tid;
output_0_axis_tuser_int = current_input_0_axis_tuser; output_0_axis_tdest_int = current_input_0_axis_tdest;
output_0_axis_tuser_int = current_input_0_axis_tuser;
output_1_axis_tdata_int = current_input_1_axis_tdata; output_1_axis_tdata_int = current_input_1_axis_tdata;
output_1_axis_tkeep_int = current_input_1_axis_tkeep;
output_1_axis_tvalid_int = current_input_1_axis_tvalid & current_input_1_axis_tready & enable_1_reg; output_1_axis_tvalid_int = current_input_1_axis_tvalid & current_input_1_axis_tready & enable_1_reg;
output_1_axis_tlast_int = current_input_1_axis_tlast; output_1_axis_tlast_int = current_input_1_axis_tlast;
output_1_axis_tdest_int = current_input_1_axis_tdest; output_1_axis_tid_int = current_input_1_axis_tid;
output_1_axis_tuser_int = current_input_1_axis_tuser; output_1_axis_tdest_int = current_input_1_axis_tdest;
output_1_axis_tuser_int = current_input_1_axis_tuser;
output_2_axis_tdata_int = current_input_2_axis_tdata; output_2_axis_tdata_int = current_input_2_axis_tdata;
output_2_axis_tkeep_int = current_input_2_axis_tkeep;
output_2_axis_tvalid_int = current_input_2_axis_tvalid & current_input_2_axis_tready & enable_2_reg; output_2_axis_tvalid_int = current_input_2_axis_tvalid & current_input_2_axis_tready & enable_2_reg;
output_2_axis_tlast_int = current_input_2_axis_tlast; output_2_axis_tlast_int = current_input_2_axis_tlast;
output_2_axis_tdest_int = current_input_2_axis_tdest; output_2_axis_tid_int = current_input_2_axis_tid;
output_2_axis_tuser_int = current_input_2_axis_tuser; output_2_axis_tdest_int = current_input_2_axis_tdest;
output_2_axis_tuser_int = current_input_2_axis_tuser;
output_3_axis_tdata_int = current_input_3_axis_tdata; output_3_axis_tdata_int = current_input_3_axis_tdata;
output_3_axis_tkeep_int = current_input_3_axis_tkeep;
output_3_axis_tvalid_int = current_input_3_axis_tvalid & current_input_3_axis_tready & enable_3_reg; output_3_axis_tvalid_int = current_input_3_axis_tvalid & current_input_3_axis_tready & enable_3_reg;
output_3_axis_tlast_int = current_input_3_axis_tlast; output_3_axis_tlast_int = current_input_3_axis_tlast;
output_3_axis_tdest_int = current_input_3_axis_tdest; output_3_axis_tid_int = current_input_3_axis_tid;
output_3_axis_tuser_int = current_input_3_axis_tuser; output_3_axis_tdest_int = current_input_3_axis_tdest;
output_3_axis_tuser_int = current_input_3_axis_tuser;
end end
always @(posedge clk) begin always @(posedge clk) begin
@ -867,28 +961,34 @@ always @(posedge clk) begin
end end
// output 0 datapath logic // output 0 datapath logic
reg [DATA_WIDTH-1:0] output_0_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] output_0_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_0_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_0_axis_tvalid_reg = 1'b0, output_0_axis_tvalid_next; reg output_0_axis_tvalid_reg = 1'b0, output_0_axis_tvalid_next;
reg output_0_axis_tlast_reg = 1'b0; reg output_0_axis_tlast_reg = 1'b0;
reg [DEST_WIDTH-1:0] output_0_axis_tdest_reg = {DEST_WIDTH{1'b0}}; reg [ID_WIDTH-1:0] output_0_axis_tid_reg = {ID_WIDTH{1'b0}};
reg output_0_axis_tuser_reg = 1'b0; reg [DEST_WIDTH-1:0] output_0_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_0_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_0_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] temp_0_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_0_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_0_axis_tvalid_reg = 1'b0, temp_0_axis_tvalid_next; reg temp_0_axis_tvalid_reg = 1'b0, temp_0_axis_tvalid_next;
reg temp_0_axis_tlast_reg = 1'b0; reg temp_0_axis_tlast_reg = 1'b0;
reg [DEST_WIDTH-1:0] temp_0_axis_tdest_reg = {DEST_WIDTH{1'b0}}; reg [ID_WIDTH-1:0] temp_0_axis_tid_reg = {ID_WIDTH{1'b0}};
reg temp_0_axis_tuser_reg = 1'b0; reg [DEST_WIDTH-1:0] temp_0_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_0_axis_tuser_reg = 1'b0;
// datapath control // datapath control
reg store_0_axis_int_to_output; reg store_0_axis_int_to_output;
reg store_0_axis_int_to_temp; reg store_0_axis_int_to_temp;
reg store_0_axis_temp_to_output; reg store_0_axis_temp_to_output;
assign output_0_axis_tdata = output_0_axis_tdata_reg; assign output_0_axis_tdata = output_0_axis_tdata_reg;
assign output_0_axis_tkeep = KEEP_ENABLE ? output_0_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_0_axis_tvalid = output_0_axis_tvalid_reg; assign output_0_axis_tvalid = output_0_axis_tvalid_reg;
assign output_0_axis_tlast = output_0_axis_tlast_reg; assign output_0_axis_tlast = output_0_axis_tlast_reg;
assign output_0_axis_tdest = output_0_axis_tdest_reg; assign output_0_axis_tid = ID_ENABLE ? output_0_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_0_axis_tuser = output_0_axis_tuser_reg; assign output_0_axis_tdest = output_0_axis_tdest_reg;
assign output_0_axis_tuser = USER_ENABLE ? output_0_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_0_axis_tready_int_early = output_0_axis_tready | (~temp_0_axis_tvalid_reg & (~output_0_axis_tvalid_reg | ~output_0_axis_tvalid_int)); assign output_0_axis_tready_int_early = output_0_axis_tready | (~temp_0_axis_tvalid_reg & (~output_0_axis_tvalid_reg | ~output_0_axis_tvalid_int));
@ -901,7 +1001,7 @@ always @* begin
store_0_axis_int_to_output = 1'b0; store_0_axis_int_to_output = 1'b0;
store_0_axis_int_to_temp = 1'b0; store_0_axis_int_to_temp = 1'b0;
store_0_axis_temp_to_output = 1'b0; store_0_axis_temp_to_output = 1'b0;
if (output_0_axis_tready_int_reg) begin if (output_0_axis_tready_int_reg) begin
// input is ready // input is ready
if (output_0_axis_tready | ~output_0_axis_tvalid_reg) begin if (output_0_axis_tready | ~output_0_axis_tvalid_reg) begin
@ -935,47 +1035,59 @@ always @(posedge clk) begin
// datapath // datapath
if (store_0_axis_int_to_output) begin if (store_0_axis_int_to_output) begin
output_0_axis_tdata_reg <= output_0_axis_tdata_int; output_0_axis_tdata_reg <= output_0_axis_tdata_int;
output_0_axis_tkeep_reg <= output_0_axis_tkeep_int;
output_0_axis_tlast_reg <= output_0_axis_tlast_int; output_0_axis_tlast_reg <= output_0_axis_tlast_int;
output_0_axis_tid_reg <= output_0_axis_tid_int;
output_0_axis_tdest_reg <= output_0_axis_tdest_int; output_0_axis_tdest_reg <= output_0_axis_tdest_int;
output_0_axis_tuser_reg <= output_0_axis_tuser_int; output_0_axis_tuser_reg <= output_0_axis_tuser_int;
end else if (store_0_axis_temp_to_output) begin end else if (store_0_axis_temp_to_output) begin
output_0_axis_tdata_reg <= temp_0_axis_tdata_reg; output_0_axis_tdata_reg <= temp_0_axis_tdata_reg;
output_0_axis_tkeep_reg <= temp_0_axis_tkeep_reg;
output_0_axis_tlast_reg <= temp_0_axis_tlast_reg; output_0_axis_tlast_reg <= temp_0_axis_tlast_reg;
output_0_axis_tid_reg <= temp_0_axis_tid_reg;
output_0_axis_tdest_reg <= temp_0_axis_tdest_reg; output_0_axis_tdest_reg <= temp_0_axis_tdest_reg;
output_0_axis_tuser_reg <= temp_0_axis_tuser_reg; output_0_axis_tuser_reg <= temp_0_axis_tuser_reg;
end end
if (store_0_axis_int_to_temp) begin if (store_0_axis_int_to_temp) begin
temp_0_axis_tdata_reg <= output_0_axis_tdata_int; temp_0_axis_tdata_reg <= output_0_axis_tdata_int;
temp_0_axis_tkeep_reg <= output_0_axis_tkeep_int;
temp_0_axis_tlast_reg <= output_0_axis_tlast_int; temp_0_axis_tlast_reg <= output_0_axis_tlast_int;
temp_0_axis_tid_reg <= output_0_axis_tid_int;
temp_0_axis_tdest_reg <= output_0_axis_tdest_int; temp_0_axis_tdest_reg <= output_0_axis_tdest_int;
temp_0_axis_tuser_reg <= output_0_axis_tuser_int; temp_0_axis_tuser_reg <= output_0_axis_tuser_int;
end end
end end
// output 1 datapath logic // output 1 datapath logic
reg [DATA_WIDTH-1:0] output_1_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] output_1_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_1_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_1_axis_tvalid_reg = 1'b0, output_1_axis_tvalid_next; reg output_1_axis_tvalid_reg = 1'b0, output_1_axis_tvalid_next;
reg output_1_axis_tlast_reg = 1'b0; reg output_1_axis_tlast_reg = 1'b0;
reg [DEST_WIDTH-1:0] output_1_axis_tdest_reg = {DEST_WIDTH{1'b0}}; reg [ID_WIDTH-1:0] output_1_axis_tid_reg = {ID_WIDTH{1'b0}};
reg output_1_axis_tuser_reg = 1'b0; reg [DEST_WIDTH-1:0] output_1_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_1_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_1_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] temp_1_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_1_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_1_axis_tvalid_reg = 1'b0, temp_1_axis_tvalid_next; reg temp_1_axis_tvalid_reg = 1'b0, temp_1_axis_tvalid_next;
reg temp_1_axis_tlast_reg = 1'b0; reg temp_1_axis_tlast_reg = 1'b0;
reg [DEST_WIDTH-1:0] temp_1_axis_tdest_reg = {DEST_WIDTH{1'b0}}; reg [ID_WIDTH-1:0] temp_1_axis_tid_reg = {ID_WIDTH{1'b0}};
reg temp_1_axis_tuser_reg = 1'b0; reg [DEST_WIDTH-1:0] temp_1_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_1_axis_tuser_reg = 1'b0;
// datapath control // datapath control
reg store_1_axis_int_to_output; reg store_1_axis_int_to_output;
reg store_1_axis_int_to_temp; reg store_1_axis_int_to_temp;
reg store_1_axis_temp_to_output; reg store_1_axis_temp_to_output;
assign output_1_axis_tdata = output_1_axis_tdata_reg; assign output_1_axis_tdata = output_1_axis_tdata_reg;
assign output_1_axis_tkeep = KEEP_ENABLE ? output_1_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_1_axis_tvalid = output_1_axis_tvalid_reg; assign output_1_axis_tvalid = output_1_axis_tvalid_reg;
assign output_1_axis_tlast = output_1_axis_tlast_reg; assign output_1_axis_tlast = output_1_axis_tlast_reg;
assign output_1_axis_tdest = output_1_axis_tdest_reg; assign output_1_axis_tid = ID_ENABLE ? output_1_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_1_axis_tuser = output_1_axis_tuser_reg; assign output_1_axis_tdest = output_1_axis_tdest_reg;
assign output_1_axis_tuser = USER_ENABLE ? output_1_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_1_axis_tready_int_early = output_1_axis_tready | (~temp_1_axis_tvalid_reg & (~output_1_axis_tvalid_reg | ~output_1_axis_tvalid_int)); assign output_1_axis_tready_int_early = output_1_axis_tready | (~temp_1_axis_tvalid_reg & (~output_1_axis_tvalid_reg | ~output_1_axis_tvalid_int));
@ -988,7 +1100,7 @@ always @* begin
store_1_axis_int_to_output = 1'b0; store_1_axis_int_to_output = 1'b0;
store_1_axis_int_to_temp = 1'b0; store_1_axis_int_to_temp = 1'b0;
store_1_axis_temp_to_output = 1'b0; store_1_axis_temp_to_output = 1'b0;
if (output_1_axis_tready_int_reg) begin if (output_1_axis_tready_int_reg) begin
// input is ready // input is ready
if (output_1_axis_tready | ~output_1_axis_tvalid_reg) begin if (output_1_axis_tready | ~output_1_axis_tvalid_reg) begin
@ -1022,47 +1134,59 @@ always @(posedge clk) begin
// datapath // datapath
if (store_1_axis_int_to_output) begin if (store_1_axis_int_to_output) begin
output_1_axis_tdata_reg <= output_1_axis_tdata_int; output_1_axis_tdata_reg <= output_1_axis_tdata_int;
output_1_axis_tkeep_reg <= output_1_axis_tkeep_int;
output_1_axis_tlast_reg <= output_1_axis_tlast_int; output_1_axis_tlast_reg <= output_1_axis_tlast_int;
output_1_axis_tid_reg <= output_1_axis_tid_int;
output_1_axis_tdest_reg <= output_1_axis_tdest_int; output_1_axis_tdest_reg <= output_1_axis_tdest_int;
output_1_axis_tuser_reg <= output_1_axis_tuser_int; output_1_axis_tuser_reg <= output_1_axis_tuser_int;
end else if (store_1_axis_temp_to_output) begin end else if (store_1_axis_temp_to_output) begin
output_1_axis_tdata_reg <= temp_1_axis_tdata_reg; output_1_axis_tdata_reg <= temp_1_axis_tdata_reg;
output_1_axis_tkeep_reg <= temp_1_axis_tkeep_reg;
output_1_axis_tlast_reg <= temp_1_axis_tlast_reg; output_1_axis_tlast_reg <= temp_1_axis_tlast_reg;
output_1_axis_tid_reg <= temp_1_axis_tid_reg;
output_1_axis_tdest_reg <= temp_1_axis_tdest_reg; output_1_axis_tdest_reg <= temp_1_axis_tdest_reg;
output_1_axis_tuser_reg <= temp_1_axis_tuser_reg; output_1_axis_tuser_reg <= temp_1_axis_tuser_reg;
end end
if (store_1_axis_int_to_temp) begin if (store_1_axis_int_to_temp) begin
temp_1_axis_tdata_reg <= output_1_axis_tdata_int; temp_1_axis_tdata_reg <= output_1_axis_tdata_int;
temp_1_axis_tkeep_reg <= output_1_axis_tkeep_int;
temp_1_axis_tlast_reg <= output_1_axis_tlast_int; temp_1_axis_tlast_reg <= output_1_axis_tlast_int;
temp_1_axis_tid_reg <= output_1_axis_tid_int;
temp_1_axis_tdest_reg <= output_1_axis_tdest_int; temp_1_axis_tdest_reg <= output_1_axis_tdest_int;
temp_1_axis_tuser_reg <= output_1_axis_tuser_int; temp_1_axis_tuser_reg <= output_1_axis_tuser_int;
end end
end end
// output 2 datapath logic // output 2 datapath logic
reg [DATA_WIDTH-1:0] output_2_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] output_2_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_2_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_2_axis_tvalid_reg = 1'b0, output_2_axis_tvalid_next; reg output_2_axis_tvalid_reg = 1'b0, output_2_axis_tvalid_next;
reg output_2_axis_tlast_reg = 1'b0; reg output_2_axis_tlast_reg = 1'b0;
reg [DEST_WIDTH-1:0] output_2_axis_tdest_reg = {DEST_WIDTH{1'b0}}; reg [ID_WIDTH-1:0] output_2_axis_tid_reg = {ID_WIDTH{1'b0}};
reg output_2_axis_tuser_reg = 1'b0; reg [DEST_WIDTH-1:0] output_2_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_2_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_2_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] temp_2_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_2_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_2_axis_tvalid_reg = 1'b0, temp_2_axis_tvalid_next; reg temp_2_axis_tvalid_reg = 1'b0, temp_2_axis_tvalid_next;
reg temp_2_axis_tlast_reg = 1'b0; reg temp_2_axis_tlast_reg = 1'b0;
reg [DEST_WIDTH-1:0] temp_2_axis_tdest_reg = {DEST_WIDTH{1'b0}}; reg [ID_WIDTH-1:0] temp_2_axis_tid_reg = {ID_WIDTH{1'b0}};
reg temp_2_axis_tuser_reg = 1'b0; reg [DEST_WIDTH-1:0] temp_2_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_2_axis_tuser_reg = 1'b0;
// datapath control // datapath control
reg store_2_axis_int_to_output; reg store_2_axis_int_to_output;
reg store_2_axis_int_to_temp; reg store_2_axis_int_to_temp;
reg store_2_axis_temp_to_output; reg store_2_axis_temp_to_output;
assign output_2_axis_tdata = output_2_axis_tdata_reg; assign output_2_axis_tdata = output_2_axis_tdata_reg;
assign output_2_axis_tkeep = KEEP_ENABLE ? output_2_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_2_axis_tvalid = output_2_axis_tvalid_reg; assign output_2_axis_tvalid = output_2_axis_tvalid_reg;
assign output_2_axis_tlast = output_2_axis_tlast_reg; assign output_2_axis_tlast = output_2_axis_tlast_reg;
assign output_2_axis_tdest = output_2_axis_tdest_reg; assign output_2_axis_tid = ID_ENABLE ? output_2_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_2_axis_tuser = output_2_axis_tuser_reg; assign output_2_axis_tdest = output_2_axis_tdest_reg;
assign output_2_axis_tuser = USER_ENABLE ? output_2_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_2_axis_tready_int_early = output_2_axis_tready | (~temp_2_axis_tvalid_reg & (~output_2_axis_tvalid_reg | ~output_2_axis_tvalid_int)); assign output_2_axis_tready_int_early = output_2_axis_tready | (~temp_2_axis_tvalid_reg & (~output_2_axis_tvalid_reg | ~output_2_axis_tvalid_int));
@ -1075,7 +1199,7 @@ always @* begin
store_2_axis_int_to_output = 1'b0; store_2_axis_int_to_output = 1'b0;
store_2_axis_int_to_temp = 1'b0; store_2_axis_int_to_temp = 1'b0;
store_2_axis_temp_to_output = 1'b0; store_2_axis_temp_to_output = 1'b0;
if (output_2_axis_tready_int_reg) begin if (output_2_axis_tready_int_reg) begin
// input is ready // input is ready
if (output_2_axis_tready | ~output_2_axis_tvalid_reg) begin if (output_2_axis_tready | ~output_2_axis_tvalid_reg) begin
@ -1109,47 +1233,59 @@ always @(posedge clk) begin
// datapath // datapath
if (store_2_axis_int_to_output) begin if (store_2_axis_int_to_output) begin
output_2_axis_tdata_reg <= output_2_axis_tdata_int; output_2_axis_tdata_reg <= output_2_axis_tdata_int;
output_2_axis_tkeep_reg <= output_2_axis_tkeep_int;
output_2_axis_tlast_reg <= output_2_axis_tlast_int; output_2_axis_tlast_reg <= output_2_axis_tlast_int;
output_2_axis_tid_reg <= output_2_axis_tid_int;
output_2_axis_tdest_reg <= output_2_axis_tdest_int; output_2_axis_tdest_reg <= output_2_axis_tdest_int;
output_2_axis_tuser_reg <= output_2_axis_tuser_int; output_2_axis_tuser_reg <= output_2_axis_tuser_int;
end else if (store_2_axis_temp_to_output) begin end else if (store_2_axis_temp_to_output) begin
output_2_axis_tdata_reg <= temp_2_axis_tdata_reg; output_2_axis_tdata_reg <= temp_2_axis_tdata_reg;
output_2_axis_tkeep_reg <= temp_2_axis_tkeep_reg;
output_2_axis_tlast_reg <= temp_2_axis_tlast_reg; output_2_axis_tlast_reg <= temp_2_axis_tlast_reg;
output_2_axis_tid_reg <= temp_2_axis_tid_reg;
output_2_axis_tdest_reg <= temp_2_axis_tdest_reg; output_2_axis_tdest_reg <= temp_2_axis_tdest_reg;
output_2_axis_tuser_reg <= temp_2_axis_tuser_reg; output_2_axis_tuser_reg <= temp_2_axis_tuser_reg;
end end
if (store_2_axis_int_to_temp) begin if (store_2_axis_int_to_temp) begin
temp_2_axis_tdata_reg <= output_2_axis_tdata_int; temp_2_axis_tdata_reg <= output_2_axis_tdata_int;
temp_2_axis_tkeep_reg <= output_2_axis_tkeep_int;
temp_2_axis_tlast_reg <= output_2_axis_tlast_int; temp_2_axis_tlast_reg <= output_2_axis_tlast_int;
temp_2_axis_tid_reg <= output_2_axis_tid_int;
temp_2_axis_tdest_reg <= output_2_axis_tdest_int; temp_2_axis_tdest_reg <= output_2_axis_tdest_int;
temp_2_axis_tuser_reg <= output_2_axis_tuser_int; temp_2_axis_tuser_reg <= output_2_axis_tuser_int;
end end
end end
// output 3 datapath logic // output 3 datapath logic
reg [DATA_WIDTH-1:0] output_3_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] output_3_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_3_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_3_axis_tvalid_reg = 1'b0, output_3_axis_tvalid_next; reg output_3_axis_tvalid_reg = 1'b0, output_3_axis_tvalid_next;
reg output_3_axis_tlast_reg = 1'b0; reg output_3_axis_tlast_reg = 1'b0;
reg [DEST_WIDTH-1:0] output_3_axis_tdest_reg = {DEST_WIDTH{1'b0}}; reg [ID_WIDTH-1:0] output_3_axis_tid_reg = {ID_WIDTH{1'b0}};
reg output_3_axis_tuser_reg = 1'b0; reg [DEST_WIDTH-1:0] output_3_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_3_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_3_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] temp_3_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_3_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_3_axis_tvalid_reg = 1'b0, temp_3_axis_tvalid_next; reg temp_3_axis_tvalid_reg = 1'b0, temp_3_axis_tvalid_next;
reg temp_3_axis_tlast_reg = 1'b0; reg temp_3_axis_tlast_reg = 1'b0;
reg [DEST_WIDTH-1:0] temp_3_axis_tdest_reg = {DEST_WIDTH{1'b0}}; reg [ID_WIDTH-1:0] temp_3_axis_tid_reg = {ID_WIDTH{1'b0}};
reg temp_3_axis_tuser_reg = 1'b0; reg [DEST_WIDTH-1:0] temp_3_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_3_axis_tuser_reg = 1'b0;
// datapath control // datapath control
reg store_3_axis_int_to_output; reg store_3_axis_int_to_output;
reg store_3_axis_int_to_temp; reg store_3_axis_int_to_temp;
reg store_3_axis_temp_to_output; reg store_3_axis_temp_to_output;
assign output_3_axis_tdata = output_3_axis_tdata_reg; assign output_3_axis_tdata = output_3_axis_tdata_reg;
assign output_3_axis_tkeep = KEEP_ENABLE ? output_3_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_3_axis_tvalid = output_3_axis_tvalid_reg; assign output_3_axis_tvalid = output_3_axis_tvalid_reg;
assign output_3_axis_tlast = output_3_axis_tlast_reg; assign output_3_axis_tlast = output_3_axis_tlast_reg;
assign output_3_axis_tdest = output_3_axis_tdest_reg; assign output_3_axis_tid = ID_ENABLE ? output_3_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_3_axis_tuser = output_3_axis_tuser_reg; assign output_3_axis_tdest = output_3_axis_tdest_reg;
assign output_3_axis_tuser = USER_ENABLE ? output_3_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_3_axis_tready_int_early = output_3_axis_tready | (~temp_3_axis_tvalid_reg & (~output_3_axis_tvalid_reg | ~output_3_axis_tvalid_int)); assign output_3_axis_tready_int_early = output_3_axis_tready | (~temp_3_axis_tvalid_reg & (~output_3_axis_tvalid_reg | ~output_3_axis_tvalid_int));
@ -1162,7 +1298,7 @@ always @* begin
store_3_axis_int_to_output = 1'b0; store_3_axis_int_to_output = 1'b0;
store_3_axis_int_to_temp = 1'b0; store_3_axis_int_to_temp = 1'b0;
store_3_axis_temp_to_output = 1'b0; store_3_axis_temp_to_output = 1'b0;
if (output_3_axis_tready_int_reg) begin if (output_3_axis_tready_int_reg) begin
// input is ready // input is ready
if (output_3_axis_tready | ~output_3_axis_tvalid_reg) begin if (output_3_axis_tready | ~output_3_axis_tvalid_reg) begin
@ -1196,19 +1332,25 @@ always @(posedge clk) begin
// datapath // datapath
if (store_3_axis_int_to_output) begin if (store_3_axis_int_to_output) begin
output_3_axis_tdata_reg <= output_3_axis_tdata_int; output_3_axis_tdata_reg <= output_3_axis_tdata_int;
output_3_axis_tkeep_reg <= output_3_axis_tkeep_int;
output_3_axis_tlast_reg <= output_3_axis_tlast_int; output_3_axis_tlast_reg <= output_3_axis_tlast_int;
output_3_axis_tid_reg <= output_3_axis_tid_int;
output_3_axis_tdest_reg <= output_3_axis_tdest_int; output_3_axis_tdest_reg <= output_3_axis_tdest_int;
output_3_axis_tuser_reg <= output_3_axis_tuser_int; output_3_axis_tuser_reg <= output_3_axis_tuser_int;
end else if (store_3_axis_temp_to_output) begin end else if (store_3_axis_temp_to_output) begin
output_3_axis_tdata_reg <= temp_3_axis_tdata_reg; output_3_axis_tdata_reg <= temp_3_axis_tdata_reg;
output_3_axis_tkeep_reg <= temp_3_axis_tkeep_reg;
output_3_axis_tlast_reg <= temp_3_axis_tlast_reg; output_3_axis_tlast_reg <= temp_3_axis_tlast_reg;
output_3_axis_tid_reg <= temp_3_axis_tid_reg;
output_3_axis_tdest_reg <= temp_3_axis_tdest_reg; output_3_axis_tdest_reg <= temp_3_axis_tdest_reg;
output_3_axis_tuser_reg <= temp_3_axis_tuser_reg; output_3_axis_tuser_reg <= temp_3_axis_tuser_reg;
end end
if (store_3_axis_int_to_temp) begin if (store_3_axis_int_to_temp) begin
temp_3_axis_tdata_reg <= output_3_axis_tdata_int; temp_3_axis_tdata_reg <= output_3_axis_tdata_int;
temp_3_axis_tkeep_reg <= output_3_axis_tkeep_int;
temp_3_axis_tlast_reg <= output_3_axis_tlast_int; temp_3_axis_tlast_reg <= output_3_axis_tlast_int;
temp_3_axis_tid_reg <= output_3_axis_tid_int;
temp_3_axis_tdest_reg <= output_3_axis_tdest_int; temp_3_axis_tdest_reg <= output_3_axis_tdest_int;
temp_3_axis_tuser_reg <= output_3_axis_tuser_int; temp_3_axis_tuser_reg <= output_3_axis_tuser_int;
end end

479
lib/axis/rtl/axis_switch_64.py
View File

@ -1,479 +0,0 @@
#!/usr/bin/env python
"""
Generates an AXI Stream switch with the specified number of ports
"""
from __future__ import print_function
import argparse
import math
from jinja2 import Template
def main():
parser = argparse.ArgumentParser(description=__doc__.strip())
parser.add_argument('-p', '--ports', type=int, default=[4], nargs='+', help="number of ports")
parser.add_argument('-n', '--name', type=str, help="module name")
parser.add_argument('-o', '--output', type=str, help="output file name")
args = parser.parse_args()
try:
generate(**args.__dict__)
except IOError as ex:
print(ex)
exit(1)
def generate(ports=4, name=None, output=None):
if type(ports) is int:
m = n = ports
elif len(ports) == 1:
m = n = ports[0]
else:
m, n = ports
if name is None:
name = "axis_switch_64_{0}x{1}".format(m, n)
if output is None:
output = name + ".v"
print("Opening file '{0}'...".format(output))
output_file = open(output, 'w')
print("Generating {0}x{1} port AXI Stream switch {2}...".format(m, n, name))
cm = int(math.ceil(math.log(m, 2)))
cn = int(math.ceil(math.log(n, 2)))
t = Template(u"""/*
Copyright (c) 2016-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream {{m}}x{{n}} switch (64 bit datapath)
*/
module {{name}} #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter DEST_WIDTH = {{cn}},
{%- for p in range(n) %}
parameter OUT_{{p}}_BASE = {{p}},
parameter OUT_{{p}}_TOP = {{p}},
parameter OUT_{{p}}_CONNECT = {{m}}'b{% for p in range(m) %}1{% endfor %},
{%- endfor %}
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "ROUND_ROBIN",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
)
(
input wire clk,
input wire rst,
/*
* AXI Stream inputs
*/
{%- for p in range(m) %}
input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep,
input wire input_{{p}}_axis_tvalid,
output wire input_{{p}}_axis_tready,
input wire input_{{p}}_axis_tlast,
input wire [DEST_WIDTH-1:0] input_{{p}}_axis_tdest,
input wire input_{{p}}_axis_tuser,
{% endfor %}
/*
* AXI Stream outputs
*/
{%- for p in range(n) %}
output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep,
output wire output_{{p}}_axis_tvalid,
input wire output_{{p}}_axis_tready,
output wire output_{{p}}_axis_tlast,
output wire [DEST_WIDTH-1:0] output_{{p}}_axis_tdest,
output wire output_{{p}}_axis_tuser{% if not loop.last %},{% endif %}
{% endfor -%}
);
// check configuration
initial begin
if (2**DEST_WIDTH < {{n}}) begin
$error("Error: DEST_WIDTH too small for port count");
$finish;
end
if ({%- for p in range(n) %}(OUT_{{p}}_BASE & 2**DEST_WIDTH-1) != OUT_{{p}}_BASE || (OUT_{{p}}_TOP & 2**DEST_WIDTH-1) != OUT_{{p}}_TOP{% if not loop.last %} ||
{% endif %}{% endfor -%}) begin
$error("Error: value out of range");
$finish;
end
if ({%- for p in range(n) %}OUT_{{p}}_BASE > OUT_{{p}}_TOP{% if not loop.last %} ||
{% endif %}{% endfor -%}) begin
$error("Error: invalid range");
$finish;
end
if ({%- for p in range(n-1) %}{% set outer_loop = loop %}{%- for q in range(p+1,n) %}(OUT_{{p}}_BASE <= OUT_{{q}}_TOP && OUT_{{q}}_BASE <= OUT_{{p}}_TOP){% if not (loop.last and outer_loop.last) %} ||
{% endif %}{% endfor -%}{% endfor -%}) begin
$error("Error: ranges overlap");
$finish;
end
end
{%- for p in range(m) %}
reg [{{n-1}}:0] input_{{p}}_request_reg = {{n}}'d0, input_{{p}}_request_next;
reg input_{{p}}_request_valid_reg = 1'b0, input_{{p}}_request_valid_next;
reg input_{{p}}_request_error_reg = 1'b0, input_{{p}}_request_error_next;
{%- endfor %}
{% for p in range(n) %}
reg [{{cm-1}}:0] select_{{p}}_reg = {{cm}}'d0, select_{{p}}_next;
{%- endfor %}
{% for p in range(n) %}
reg enable_{{p}}_reg = 1'b0, enable_{{p}}_next;
{%- endfor %}
{% for p in range(m) %}
reg input_{{p}}_axis_tready_reg = 1'b0, input_{{p}}_axis_tready_next;
{%- endfor %}
// internal datapath
{%- for p in range(n) %}
reg [DATA_WIDTH-1:0] output_{{p}}_axis_tdata_int;
reg [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep_int;
reg output_{{p}}_axis_tvalid_int;
reg output_{{p}}_axis_tready_int_reg = 1'b0;
reg output_{{p}}_axis_tlast_int;
reg [DEST_WIDTH-1:0] output_{{p}}_axis_tdest_int;
reg output_{{p}}_axis_tuser_int;
wire output_{{p}}_axis_tready_int_early;
{% endfor %}
{%- for p in range(m) %}
assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg;
{%- endfor %}
// mux for incoming packet
{% for p in range(n) %}
reg [DATA_WIDTH-1:0] current_input_{{p}}_axis_tdata;
reg [KEEP_WIDTH-1:0] current_input_{{p}}_axis_tkeep;
reg current_input_{{p}}_axis_tvalid;
reg current_input_{{p}}_axis_tready;
reg current_input_{{p}}_axis_tlast;
reg [DEST_WIDTH-1:0] current_input_{{p}}_axis_tdest;
reg current_input_{{p}}_axis_tuser;
always @* begin
case (select_{{p}}_reg)
{%- for q in range(m) %}
{{cm}}'d{{q}}: begin
current_input_{{p}}_axis_tdata = input_{{q}}_axis_tdata;
current_input_{{p}}_axis_tkeep = input_{{q}}_axis_tkeep;
current_input_{{p}}_axis_tvalid = input_{{q}}_axis_tvalid;
current_input_{{p}}_axis_tready = input_{{q}}_axis_tready;
current_input_{{p}}_axis_tlast = input_{{q}}_axis_tlast;
current_input_{{p}}_axis_tdest = input_{{q}}_axis_tdest;
current_input_{{p}}_axis_tuser = input_{{q}}_axis_tuser;
end
{%- endfor %}
default: begin
current_input_{{p}}_axis_tdata = {DATA_WIDTH{1'b0}};
current_input_{{p}}_axis_tkeep = {KEEP_WIDTH{1'b0}};
current_input_{{p}}_axis_tvalid = 1'b0;
current_input_{{p}}_axis_tready = 1'b0;
current_input_{{p}}_axis_tlast = 1'b0;
current_input_{{p}}_axis_tdest = {DEST_WIDTH{1'b0}};
current_input_{{p}}_axis_tuser = 1'b0;
end
endcase
end
{% endfor %}
// arbiter instances
{% for p in range(n) %}
wire [{{m-1}}:0] request_{{p}};
wire [{{m-1}}:0] acknowledge_{{p}};
wire [{{m-1}}:0] grant_{{p}};
wire grant_valid_{{p}};
wire [{{cm-1}}:0] grant_encoded_{{p}};
{% endfor %}
{%- for p in range(n) %}
arbiter #(
.PORTS({{m}}),
.TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
)
arb_{{p}}_inst (
.clk(clk),
.rst(rst),
.request(request_{{p}}),
.acknowledge(acknowledge_{{p}}),
.grant(grant_{{p}}),
.grant_valid(grant_valid_{{p}}),
.grant_encoded(grant_encoded_{{p}})
);
{% endfor %}
// request generation
{%- for p in range(n) %}
{%- for q in range(m) %}
assign request_{{p}}[{{q}}] = input_{{q}}_request_reg[{{p}}] & ~acknowledge_{{p}}[{{q}}];
{%- endfor %}
{% endfor %}
// acknowledge generation
{%- for p in range(n) %}
{%- for q in range(m) %}
assign acknowledge_{{p}}[{{q}}] = grant_{{p}}[{{q}}] & input_{{q}}_axis_tvalid & input_{{q}}_axis_tready & input_{{q}}_axis_tlast;
{%- endfor %}
{% endfor %}
always @* begin
{%- for p in range(n) %}
select_{{p}}_next = select_{{p}}_reg;
{%- endfor %}
{% for p in range(n) %}
enable_{{p}}_next = enable_{{p}}_reg;
{%- endfor %}
{% for p in range(m) %}
input_{{p}}_request_next = input_{{p}}_request_reg;
input_{{p}}_request_valid_next = input_{{p}}_request_valid_reg;
input_{{p}}_request_error_next = input_{{p}}_request_error_reg;
{% endfor %}
{%- for p in range(m) %}
input_{{p}}_axis_tready_next = 1'b0;
{%- endfor %}
{% for p in range(n) %}
output_{{p}}_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_{{p}}_axis_tkeep_int = {DATA_WIDTH{1'b0}};
output_{{p}}_axis_tvalid_int = 1'b0;
output_{{p}}_axis_tlast_int = 1'b0;
output_{{p}}_axis_tdest_int = {DEST_WIDTH{1'b0}};
output_{{p}}_axis_tuser_int = 1'b0;
{% endfor %}
// input decoding
{% for p in range(m) %}
if (input_{{p}}_request_valid_reg | input_{{p}}_request_error_reg) begin
if (input_{{p}}_axis_tvalid & input_{{p}}_axis_tready & input_{{p}}_axis_tlast) begin
input_{{p}}_request_next = {DEST_WIDTH{1'b0}};
input_{{p}}_request_valid_next = 1'b0;
input_{{p}}_request_error_next = 1'b0;
end
end else if (input_{{p}}_axis_tvalid) begin
{%- for q in range(n) %}
input_{{p}}_request_next[{{q}}] = (input_{{p}}_axis_tdest >= OUT_{{q}}_BASE) & (input_{{p}}_axis_tdest <= OUT_{{q}}_TOP) & OUT_{{q}}_CONNECT[{{p}}];
{%- endfor %}
if (input_{{p}}_request_next) begin
input_{{p}}_request_valid_next = 1'b1;
end else begin
input_{{p}}_request_error_next = 1'b1;
end
end
{% endfor %}
// output control
{% for p in range(n) %}
if (current_input_{{p}}_axis_tvalid & current_input_{{p}}_axis_tready) begin
if (current_input_{{p}}_axis_tlast) begin
enable_{{p}}_next = 1'b0;
end
end
if (~enable_{{p}}_reg & grant_valid_{{p}}) begin
enable_{{p}}_next = 1'b1;
select_{{p}}_next = grant_encoded_{{p}};
end
{% endfor %}
// generate ready signal on selected port
{% for p in range(n) %}
if (enable_{{p}}_next) begin
case (select_{{p}}_next)
{%- for q in range(m) %}
{{cm}}'d{{q}}: input_{{q}}_axis_tready_next = output_{{p}}_axis_tready_int_early;
{%- endfor %}
endcase
end
{% endfor %}
{%- for p in range(m) %}
if (input_{{p}}_request_error_next)
input_{{p}}_axis_tready_next = 1'b1;
{%- endfor %}
// pass through selected packet data
{% for p in range(n) %}
output_{{p}}_axis_tdata_int = current_input_{{p}}_axis_tdata;
output_{{p}}_axis_tkeep_int = current_input_{{p}}_axis_tkeep;
output_{{p}}_axis_tvalid_int = current_input_{{p}}_axis_tvalid & current_input_{{p}}_axis_tready & enable_{{p}}_reg;
output_{{p}}_axis_tlast_int = current_input_{{p}}_axis_tlast;
output_{{p}}_axis_tdest_int = current_input_{{p}}_axis_tdest;
output_{{p}}_axis_tuser_int = current_input_{{p}}_axis_tuser;
{% endfor -%}
end
always @(posedge clk) begin
if (rst) begin
{%- for p in range(m) %}
input_{{p}}_request_reg <= {{n}}'d0;
input_{{p}}_request_valid_reg <= 1'b0;
input_{{p}}_request_error_reg <= 1'b0;
{%- endfor %}
{%- for p in range(n) %}
select_{{p}}_reg <= 2'd0;
{%- endfor %}
{%- for p in range(n) %}
enable_{{p}}_reg <= 1'b0;
{%- endfor %}
{%- for p in range(m) %}
input_{{p}}_axis_tready_reg <= 1'b0;
{%- endfor %}
end else begin
{%- for p in range(m) %}
input_{{p}}_request_reg <= input_{{p}}_request_next;
input_{{p}}_request_valid_reg <= input_{{p}}_request_valid_next;
input_{{p}}_request_error_reg <= input_{{p}}_request_error_next;
{%- endfor %}
{%- for p in range(n) %}
select_{{p}}_reg <= select_{{p}}_next;
{%- endfor %}
{%- for p in range(n) %}
enable_{{p}}_reg <= enable_{{p}}_next;
{%- endfor %}
{%- for p in range(m) %}
input_{{p}}_axis_tready_reg <= input_{{p}}_axis_tready_next;
{%- endfor %}
end
end
{% for p in range(n) %}
// output {{p}} datapath logic
reg [DATA_WIDTH-1:0] output_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_{{p}}_axis_tvalid_reg = 1'b0, output_{{p}}_axis_tvalid_next;
reg output_{{p}}_axis_tlast_reg = 1'b0;
reg [DEST_WIDTH-1:0] output_{{p}}_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg output_{{p}}_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_{{p}}_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_{{p}}_axis_tvalid_reg = 1'b0, temp_{{p}}_axis_tvalid_next;
reg temp_{{p}}_axis_tlast_reg = 1'b0;
reg [DEST_WIDTH-1:0] temp_{{p}}_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg temp_{{p}}_axis_tuser_reg = 1'b0;
// datapath control
reg store_{{p}}_axis_int_to_output;
reg store_{{p}}_axis_int_to_temp;
reg store_{{p}}_axis_temp_to_output;
assign output_{{p}}_axis_tdata = output_{{p}}_axis_tdata_reg;
assign output_{{p}}_axis_tkeep = output_{{p}}_axis_tkeep_reg;
assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg;
assign output_{{p}}_axis_tlast = output_{{p}}_axis_tlast_reg;
assign output_{{p}}_axis_tdest = output_{{p}}_axis_tdest_reg;
assign output_{{p}}_axis_tuser = output_{{p}}_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_{{p}}_axis_tready_int_early = output_{{p}}_axis_tready | (~temp_{{p}}_axis_tvalid_reg & (~output_{{p}}_axis_tvalid_reg | ~output_{{p}}_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
output_{{p}}_axis_tvalid_next = output_{{p}}_axis_tvalid_reg;
temp_{{p}}_axis_tvalid_next = temp_{{p}}_axis_tvalid_reg;
store_{{p}}_axis_int_to_output = 1'b0;
store_{{p}}_axis_int_to_temp = 1'b0;
store_{{p}}_axis_temp_to_output = 1'b0;
if (output_{{p}}_axis_tready_int_reg) begin
// input is ready
if (output_{{p}}_axis_tready | ~output_{{p}}_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_{{p}}_axis_tvalid_next = output_{{p}}_axis_tvalid_int;
store_{{p}}_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_{{p}}_axis_tvalid_next = output_{{p}}_axis_tvalid_int;
store_{{p}}_axis_int_to_temp = 1'b1;
end
end else if (output_{{p}}_axis_tready) begin
// input is not ready, but output is ready
output_{{p}}_axis_tvalid_next = temp_{{p}}_axis_tvalid_reg;
temp_{{p}}_axis_tvalid_next = 1'b0;
store_{{p}}_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
output_{{p}}_axis_tvalid_reg <= 1'b0;
output_{{p}}_axis_tready_int_reg <= 1'b0;
temp_{{p}}_axis_tvalid_reg <= 1'b0;
end else begin
output_{{p}}_axis_tvalid_reg <= output_{{p}}_axis_tvalid_next;
output_{{p}}_axis_tready_int_reg <= output_{{p}}_axis_tready_int_early;
temp_{{p}}_axis_tvalid_reg <= temp_{{p}}_axis_tvalid_next;
end
// datapath
if (store_{{p}}_axis_int_to_output) begin
output_{{p}}_axis_tdata_reg <= output_{{p}}_axis_tdata_int;
output_{{p}}_axis_tkeep_reg <= output_{{p}}_axis_tkeep_int;
output_{{p}}_axis_tlast_reg <= output_{{p}}_axis_tlast_int;
output_{{p}}_axis_tdest_reg <= output_{{p}}_axis_tdest_int;
output_{{p}}_axis_tuser_reg <= output_{{p}}_axis_tuser_int;
end else if (store_{{p}}_axis_temp_to_output) begin
output_{{p}}_axis_tdata_reg <= temp_{{p}}_axis_tdata_reg;
output_{{p}}_axis_tkeep_reg <= temp_{{p}}_axis_tkeep_reg;
output_{{p}}_axis_tlast_reg <= temp_{{p}}_axis_tlast_reg;
output_{{p}}_axis_tdest_reg <= temp_{{p}}_axis_tdest_reg;
output_{{p}}_axis_tuser_reg <= temp_{{p}}_axis_tuser_reg;
end
if (store_{{p}}_axis_int_to_temp) begin
temp_{{p}}_axis_tdata_reg <= output_{{p}}_axis_tdata_int;
temp_{{p}}_axis_tkeep_reg <= output_{{p}}_axis_tkeep_int;
temp_{{p}}_axis_tlast_reg <= output_{{p}}_axis_tlast_int;
temp_{{p}}_axis_tdest_reg <= output_{{p}}_axis_tdest_int;
temp_{{p}}_axis_tuser_reg <= output_{{p}}_axis_tuser_int;
end
end
{% endfor %}
endmodule
""")
output_file.write(t.render(
m=m,
n=n,
cm=cm,
cn=cn,
name=name
))
print("Done")
if __name__ == "__main__":
main()

1286
lib/axis/rtl/axis_switch_64_4x4.v
View File

File diff suppressed because it is too large Load Diff

127
lib/axis/rtl/axis_tap.v
View File

@ -31,7 +31,17 @@ THE SOFTWARE.
*/ */
module axis_tap # module axis_tap #
( (
parameter DATA_WIDTH = 8 parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
parameter USER_BAD_FRAME_VALUE = 1'b1,
parameter USER_BAD_FRAME_MASK = 1'b1
) )
( (
input wire clk, input wire clk,
@ -41,28 +51,44 @@ module axis_tap #
* AXI tap * AXI tap
*/ */
input wire [DATA_WIDTH-1:0] tap_axis_tdata, input wire [DATA_WIDTH-1:0] tap_axis_tdata,
input wire [KEEP_WIDTH-1:0] tap_axis_tkeep,
input wire tap_axis_tvalid, input wire tap_axis_tvalid,
input wire tap_axis_tready, input wire tap_axis_tready,
input wire tap_axis_tlast, input wire tap_axis_tlast,
input wire tap_axis_tuser, input wire [ID_WIDTH-1:0] tap_axis_tid,
input wire [DEST_WIDTH-1:0] tap_axis_tdest,
input wire [USER_WIDTH-1:0] tap_axis_tuser,
/* /*
* AXI output * AXI output
*/ */
output wire [DATA_WIDTH-1:0] output_axis_tdata, output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid, output wire output_axis_tvalid,
input wire output_axis_tready, input wire output_axis_tready,
output wire output_axis_tlast, output wire output_axis_tlast,
output wire output_axis_tuser output wire [ID_WIDTH-1:0] output_axis_tid,
output wire [DEST_WIDTH-1:0] output_axis_tdest,
output wire [USER_WIDTH-1:0] output_axis_tuser
); );
// datapath control signals
reg store_last_word;
reg [ID_WIDTH-1:0] last_word_id_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] last_word_dest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] last_word_user_reg = {USER_WIDTH{1'b0}};
// internal datapath // internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int; reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg output_axis_tvalid_int; reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tready_int_reg = 1'b0; reg output_axis_tvalid_int;
reg output_axis_tlast_int; reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tuser_int; reg output_axis_tlast_int;
wire output_axis_tready_int_early; reg [ID_WIDTH-1:0] output_axis_tid_int;
reg [DEST_WIDTH-1:0] output_axis_tdest_int;
reg [USER_WIDTH-1:0] output_axis_tuser_int;
wire output_axis_tready_int_early;
localparam [1:0] localparam [1:0]
STATE_IDLE = 2'd0, STATE_IDLE = 2'd0,
@ -77,12 +103,17 @@ reg frame_reg = 1'b0, frame_next;
always @* begin always @* begin
state_next = STATE_IDLE; state_next = STATE_IDLE;
store_last_word = 1'b0;
frame_next = frame_reg; frame_next = frame_reg;
output_axis_tdata_int = {DATA_WIDTH{1'b0}}; output_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
output_axis_tvalid_int = 1'b0; output_axis_tvalid_int = 1'b0;
output_axis_tlast_int = 1'b0; output_axis_tlast_int = 1'b0;
output_axis_tuser_int = 1'b0; output_axis_tid_int = {ID_WIDTH{1'b0}};
output_axis_tdest_int = {DEST_WIDTH{1'b0}};
output_axis_tuser_int = {USER_WIDTH{1'b0}};
if (tap_axis_tready & tap_axis_tvalid) begin if (tap_axis_tready & tap_axis_tvalid) begin
frame_next = ~tap_axis_tlast; frame_next = ~tap_axis_tlast;
@ -93,10 +124,13 @@ always @* begin
if (tap_axis_tready & tap_axis_tvalid) begin if (tap_axis_tready & tap_axis_tvalid) begin
// start of frame // start of frame
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
output_axis_tdata_int = tap_axis_tdata; output_axis_tdata_int = tap_axis_tdata;
output_axis_tkeep_int = tap_axis_tkeep;
output_axis_tvalid_int = tap_axis_tvalid & tap_axis_tready; output_axis_tvalid_int = tap_axis_tvalid & tap_axis_tready;
output_axis_tlast_int = tap_axis_tlast; output_axis_tlast_int = tap_axis_tlast;
output_axis_tuser_int = tap_axis_tuser; output_axis_tid_int = tap_axis_tid;
output_axis_tdest_int = tap_axis_tdest;
output_axis_tuser_int = tap_axis_tuser;
if (tap_axis_tlast) begin if (tap_axis_tlast) begin
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else begin end else begin
@ -113,16 +147,20 @@ always @* begin
if (tap_axis_tready & tap_axis_tvalid) begin if (tap_axis_tready & tap_axis_tvalid) begin
// transfer data // transfer data
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
output_axis_tdata_int = tap_axis_tdata; output_axis_tdata_int = tap_axis_tdata;
output_axis_tkeep_int = tap_axis_tkeep;
output_axis_tvalid_int = tap_axis_tvalid & tap_axis_tready; output_axis_tvalid_int = tap_axis_tvalid & tap_axis_tready;
output_axis_tlast_int = tap_axis_tlast; output_axis_tlast_int = tap_axis_tlast;
output_axis_tuser_int = tap_axis_tuser; output_axis_tid_int = tap_axis_tid;
output_axis_tdest_int = tap_axis_tdest;
output_axis_tuser_int = tap_axis_tuser;
if (tap_axis_tlast) begin if (tap_axis_tlast) begin
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else begin end else begin
state_next = STATE_TRANSFER; state_next = STATE_TRANSFER;
end end
end else begin end else begin
store_last_word = 1'b1;
state_next = STATE_TRUNCATE; state_next = STATE_TRUNCATE;
end end
end else begin end else begin
@ -131,10 +169,13 @@ always @* begin
end end
STATE_TRUNCATE: begin STATE_TRUNCATE: begin
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
output_axis_tdata_int = {DATA_WIDTH{1'b0}}; output_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_axis_tkeep_int = {{KEEP_WIDTH-1{1'b0}}, 1'b1};
output_axis_tvalid_int = 1'b1; output_axis_tvalid_int = 1'b1;
output_axis_tlast_int = 1'b1; output_axis_tlast_int = 1'b1;
output_axis_tuser_int = 1'b1; output_axis_tid_int = last_word_id_reg;
output_axis_tdest_int = last_word_dest_reg;
output_axis_tuser_int = (last_word_user_reg & ~USER_BAD_FRAME_MASK) | (USER_BAD_FRAME_VALUE & USER_BAD_FRAME_MASK);
if (frame_next) begin if (frame_next) begin
state_next = STATE_WAIT; state_next = STATE_WAIT;
end else begin end else begin
@ -166,28 +207,43 @@ always @(posedge clk) begin
state_reg <= state_next; state_reg <= state_next;
frame_reg <= frame_next; frame_reg <= frame_next;
end end
if (store_last_word) begin
last_word_id_reg <= tap_axis_tid;
last_word_dest_reg <= tap_axis_tdest;
last_word_user_reg <= tap_axis_tuser;
end
end end
// output datapath logic // output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next; reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0; reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] output_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] output_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}}; reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next; reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0; reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0; reg [ID_WIDTH-1:0] temp_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control // datapath control
reg store_axis_int_to_output; reg store_axis_int_to_output;
reg store_axis_int_to_temp; reg store_axis_int_to_temp;
reg store_axis_temp_to_output; reg store_axis_temp_to_output;
assign output_axis_tdata = output_axis_tdata_reg; assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = KEEP_ENABLE ? output_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_axis_tvalid = output_axis_tvalid_reg; assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg; assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg; assign output_axis_tid = ID_ENABLE ? output_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_axis_tdest = DEST_ENABLE ? output_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign output_axis_tuser = USER_ENABLE ? output_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int)); assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
@ -200,7 +256,7 @@ always @* begin
store_axis_int_to_output = 1'b0; store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0; store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0; store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin if (output_axis_tready_int_reg) begin
// input is ready // input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin if (output_axis_tready | ~output_axis_tvalid_reg) begin
@ -234,17 +290,26 @@ always @(posedge clk) begin
// datapath // datapath
if (store_axis_int_to_output) begin if (store_axis_int_to_output) begin
output_axis_tdata_reg <= output_axis_tdata_int; output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tlast_reg <= output_axis_tlast_int; output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tid_reg <= output_axis_tid_int;
output_axis_tdest_reg <= output_axis_tdest_int;
output_axis_tuser_reg <= output_axis_tuser_int; output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg; output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg; output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tid_reg <= temp_axis_tid_reg;
output_axis_tdest_reg <= temp_axis_tdest_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg; output_axis_tuser_reg <= temp_axis_tuser_reg;
end end
if (store_axis_int_to_temp) begin if (store_axis_int_to_temp) begin
temp_axis_tdata_reg <= output_axis_tdata_int; temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tlast_reg <= output_axis_tlast_int; temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tid_reg <= output_axis_tid_int;
temp_axis_tdest_reg <= output_axis_tdest_int;
temp_axis_tuser_reg <= output_axis_tuser_int; temp_axis_tuser_reg <= output_axis_tuser_int;
end end
end end

266
lib/axis/rtl/axis_tap_64.v
View File

@ -1,266 +0,0 @@
/*
Copyright (c) 2015-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream tap (64 bit datapath)
*/
module axis_tap_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI tap
*/
input wire [DATA_WIDTH-1:0] tap_axis_tdata,
input wire [KEEP_WIDTH-1:0] tap_axis_tkeep,
input wire tap_axis_tvalid,
input wire tap_axis_tready,
input wire tap_axis_tlast,
input wire tap_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
// internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_TRANSFER = 2'd1,
STATE_TRUNCATE = 2'd2,
STATE_WAIT = 2'd3;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg frame_reg = 1'b0, frame_next;
always @* begin
state_next = STATE_IDLE;
frame_next = frame_reg;
output_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
output_axis_tvalid_int = 1'b0;
output_axis_tlast_int = 1'b0;
output_axis_tuser_int = 1'b0;
if (tap_axis_tready & tap_axis_tvalid) begin
frame_next = ~tap_axis_tlast;
end
case (state_reg)
STATE_IDLE: begin
if (tap_axis_tready & tap_axis_tvalid) begin
// start of frame
if (output_axis_tready_int_reg) begin
output_axis_tdata_int = tap_axis_tdata;
output_axis_tkeep_int = tap_axis_tkeep;
output_axis_tvalid_int = tap_axis_tvalid & tap_axis_tready;
output_axis_tlast_int = tap_axis_tlast;
output_axis_tuser_int = tap_axis_tuser;
if (tap_axis_tlast) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_TRANSFER;
end
end else begin
state_next = STATE_WAIT;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_TRANSFER: begin
if (tap_axis_tready & tap_axis_tvalid) begin
// transfer data
if (output_axis_tready_int_reg) begin
output_axis_tdata_int = tap_axis_tdata;
output_axis_tkeep_int = tap_axis_tkeep;
output_axis_tvalid_int = tap_axis_tvalid & tap_axis_tready;
output_axis_tlast_int = tap_axis_tlast;
output_axis_tuser_int = tap_axis_tuser;
if (tap_axis_tlast) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_TRANSFER;
end
end else begin
state_next = STATE_TRUNCATE;
end
end else begin
state_next = STATE_TRANSFER;
end
end
STATE_TRUNCATE: begin
if (output_axis_tready_int_reg) begin
output_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_axis_tkeep_int = {{KEEP_WIDTH-1{1'b0}}, 1'b1};
output_axis_tvalid_int = 1'b1;
output_axis_tlast_int = 1'b1;
output_axis_tuser_int = 1'b1;
if (frame_next) begin
state_next = STATE_WAIT;
end else begin
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_TRUNCATE;
end
end
STATE_WAIT: begin
if (tap_axis_tready & tap_axis_tvalid) begin
if (tap_axis_tlast) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT;
end
end else begin
state_next = STATE_WAIT;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_reg <= 1'b0;
end else begin
state_reg <= state_next;
frame_reg <= frame_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = output_axis_tkeep_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
output_axis_tvalid_next = output_axis_tvalid_reg;
temp_axis_tvalid_next = temp_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_axis_tvalid_next = output_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_axis_tvalid_next = output_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (output_axis_tready) begin
// input is not ready, but output is ready
output_axis_tvalid_next = temp_axis_tvalid_reg;
temp_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
output_axis_tvalid_reg <= 1'b0;
output_axis_tready_int_reg <= 1'b0;
temp_axis_tvalid_reg <= 1'b0;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
output_axis_tready_int_reg <= output_axis_tready_int_early;
temp_axis_tvalid_reg <= temp_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end
endmodule

4
lib/axis/rtl/ll_axis_bridge.v
View File

@ -36,7 +36,7 @@ module ll_axis_bridge #
( (
input wire clk, input wire clk,
input wire rst, input wire rst,
/* /*
* LocalLink input * LocalLink input
*/ */
@ -45,7 +45,7 @@ module ll_axis_bridge #
input wire ll_eof_in_n, input wire ll_eof_in_n,
input wire ll_src_rdy_in_n, input wire ll_src_rdy_in_n,
output wire ll_dst_rdy_out_n, output wire ll_dst_rdy_out_n,
/* /*
* AXI output * AXI output
*/ */

184
lib/axis/tb/axis_ep.py
View File

@ -27,21 +27,25 @@ from myhdl import *
skip_asserts = False skip_asserts = False
class AXIStreamFrame(object): class AXIStreamFrame(object):
def __init__(self, data=b'', keep=None, dest=None, user=None): def __init__(self, data=b'', keep=None, id=None, dest=None, user=None, last_cycle_user=None):
self.B = 0 self.B = 0
self.N = 8 self.N = 8
self.M = 1 self.M = 1
self.WL = 8 self.WL = 8
self.data = b'' self.data = b''
self.keep = None self.keep = None
self.id = 0
self.dest = 0 self.dest = 0
self.user = None self.user = None
self.last_cycle_user = None
if type(data) is bytes or type(data) is bytearray: if type(data) in (bytes, bytearray):
self.data = bytearray(data) self.data = bytearray(data)
self.keep = keep self.keep = keep
self.id = id
self.dest = dest self.dest = dest
self.user = user self.user = user
self.last_cycle_user = last_cycle_user
elif type(data) is AXIStreamFrame: elif type(data) is AXIStreamFrame:
self.N = data.N self.N = data.N
self.WL = data.WL self.WL = data.WL
@ -51,21 +55,29 @@ class AXIStreamFrame(object):
self.data = list(data.data) self.data = list(data.data)
if data.keep is not None: if data.keep is not None:
self.keep = list(data.keep) self.keep = list(data.keep)
if data.id is not None:
if type(data.id) in (int, bool):
self.id = data.id
else:
self.id = list(data.id)
if data.dest is not None: if data.dest is not None:
if type(data.dest) is int: if type(data.dest) in (int, bool):
self.dest = data.dest self.dest = data.dest
else: else:
self.dest = list(data.dest) self.dest = list(data.dest)
if data.user is not None: if data.user is not None:
if type(data.user) is int or type(data.user) is bool: if type(data.user) in (int, bool):
self.user = data.user self.user = data.user
else: else:
self.user = list(data.user) self.user = list(data.user)
self.last_cycle_user = data.last_cycle_user
else: else:
self.data = list(data) self.data = list(data)
self.keep = keep self.keep = keep
self.id = id
self.dest = dest self.dest = dest
self.user = user self.user = user
self.last_cycle_user = last_cycle_user
def build(self): def build(self):
if self.data is None: if self.data is None:
@ -74,22 +86,13 @@ class AXIStreamFrame(object):
f = list(self.data) f = list(self.data)
tdata = [] tdata = []
tkeep = [] tkeep = []
tid = []
tdest = [] tdest = []
tuser = [] tuser = []
i = 0 i = 0
dest = 0 while len(f) > 0:
if type(self.dest) is int: if self.B == 0:
dest = self.dest
self.dest = None
assert_tuser = False
if (type(self.user) is int or type(self.user) is bool) and self.user:
assert_tuser = True
self.user = None
if self.B == 0:
while len(f) > 0:
data = 0 data = 0
keep = 0 keep = 0
for j in range(self.M): for j in range(self.M):
@ -97,52 +100,53 @@ class AXIStreamFrame(object):
keep = keep | (1 << j) keep = keep | (1 << j)
if len(f) == 0: break if len(f) == 0: break
tdata.append(data) tdata.append(data)
if self.keep is None: if self.keep is None:
tkeep.append(keep) tkeep.append(keep)
else: else:
tkeep.append(self.keep[i]) tkeep.append(self.keep[i])
if self.dest is None: else:
tdest.append(dest) # multiple tdata signals
else:
tdest.append(self.dest[i])
if self.user is None:
tuser.append(0)
else:
tuser.append(self.user[i])
i += 1
else:
# multiple tdata signals
while len(f) > 0:
data = 0 data = 0
tdata.append(f.pop(0)) tdata.append(f.pop(0))
tkeep.append(0) tkeep.append(0)
if self.dest is None:
tdest.append(dest)
else:
tdest.append(self.dest[i])
if self.user is None:
tuser.append(0)
else:
tuser.append(self.user[i])
i += 1
if assert_tuser: if self.id is None:
tuser[-1] = 1 tid.append(0)
self.user = 1 elif type(self.id) is int:
tid.append(self.id)
else:
tid.append(self.id[i])
if self.dest == None: if self.dest is None:
self.dest = dest tdest.append(0)
elif type(self.dest) is int:
tdest.append(self.dest)
else:
tdest.append(self.dest[i])
return tdata, tkeep, tdest, tuser if self.user is None:
tuser.append(0)
elif type(self.user) is int:
tuser.append(self.user)
else:
tuser.append(self.user[i])
i += 1
def parse(self, tdata, tkeep, tdest, tuser): if self.last_cycle_user:
tuser[-1] = self.last_cycle_user
return tdata, tkeep, tid, tdest, tuser
def parse(self, tdata, tkeep, tid, tdest, tuser):
if tdata is None or tkeep is None or tuser is None: if tdata is None or tkeep is None or tuser is None:
return return
if len(tdata) != len(tkeep) or len(tdata) != len(tdest) or len(tdata) != len(tuser): if len(tdata) != len(tkeep) or len(tdata) != len(tid) or len(tdata) != len(tdest) or len(tdata) != len(tuser):
raise Exception("Invalid data") raise Exception("Invalid data")
self.data = [] self.data = []
self.keep = [] self.keep = []
self.id = []
self.dest = [] self.dest = []
self.user = [] self.user = []
@ -154,25 +158,89 @@ class AXIStreamFrame(object):
if tkeep[i] & (1 << j): if tkeep[i] & (1 << j):
self.data.append((tdata[i] >> (j*self.WL)) & mask) self.data.append((tdata[i] >> (j*self.WL)) & mask)
self.keep.append(tkeep[i]) self.keep.append(tkeep[i])
self.id.append(tid[i])
self.dest.append(tdest[i]) self.dest.append(tdest[i])
self.user.append(tuser[i]) self.user.append(tuser[i])
else: else:
for i in range(len(tdata)): for i in range(len(tdata)):
self.data.append(tdata[i]) self.data.append(tdata[i])
self.keep.append(tkeep[i]) self.keep.append(tkeep[i])
self.id.append(tid[i])
self.dest.append(tdest[i]) self.dest.append(tdest[i])
self.user.append(tuser[i]) self.user.append(tuser[i])
if self.WL == 8: if self.WL == 8:
self.data = bytearray(self.data) self.data = bytearray(self.data)
self.last_cycle_user = self.user[-1]
def __eq__(self, other): def __eq__(self, other):
if type(other) is AXIStreamFrame: if not isinstance(other, AXIStreamFrame):
return self.data == other.data return False
return False if self.data != other.data:
return False
if self.keep is not None and other.keep is not None:
if self.keep != other.keep:
return False
if self.id is not None and other.id is not None:
if type(self.id) in (int, bool) and type(other.id) is list:
for k in other.id:
if self.id != k:
return False
elif type(other.id) in (int, bool) and type(self.id) is list:
for k in self.id:
if other.id != k:
return False
elif self.id != other.id:
return False
if self.dest is not None and other.dest is not None:
if type(self.dest) in (int, bool) and type(other.dest) is list:
for k in other.dest:
if self.dest != k:
return False
elif type(other.dest) in (int, bool) and type(self.dest) is list:
for k in self.dest:
if other.dest != k:
return False
elif self.dest != other.dest:
return False
if self.last_cycle_user is not None and other.last_cycle_user is not None:
if self.last_cycle_user != other.last_cycle_user:
return False
if self.user is not None and other.user is not None:
if type(self.user) in (int, bool) and type(other.user) is list:
for k in other.user[:-1]:
if self.user != k:
return False
elif type(other.user) in (int, bool) and type(self.user) is list:
for k in self.user[:-1]:
if other.user != k:
return False
elif self.user != other.user:
return False
else:
if self.user is not None and other.user is not None:
if type(self.user) in (int, bool) and type(other.user) is list:
for k in other.user:
if self.user != k:
return False
elif type(other.user) in (int, bool) and type(self.user) is list:
for k in self.user:
if other.user != k:
return False
elif self.user != other.user:
return False
return True
def __repr__(self): def __repr__(self):
return 'AXIStreamFrame(data=%s, keep=%s, dest=%s, user=%s)' % (repr(self.data), repr(self.keep), repr(self.dest), repr(self.user)) return (
('AXIStreamFrame(data=%s, ' % repr(self.data)) +
('keep=%s, ' % repr(self.keep)) +
('id=%s, ' % repr(self.id)) +
('dest=%s, ' % repr(self.dest)) +
('user=%s, ' % repr(self.user)) +
('last_cycle_user=%s)' % repr(self.last_cycle_user))
)
def __iter__(self): def __iter__(self):
return self.data.__iter__() return self.data.__iter__()
@ -203,8 +271,9 @@ class AXIStreamSource(object):
tvalid=Signal(bool(False)), tvalid=Signal(bool(False)),
tready=Signal(bool(True)), tready=Signal(bool(True)),
tlast=Signal(bool(False)), tlast=Signal(bool(False)),
tid=Signal(intbv(0)),
tdest=Signal(intbv(0)), tdest=Signal(intbv(0)),
tuser=Signal(bool(False)), tuser=Signal(intbv(0)),
pause=0, pause=0,
name=None name=None
): ):
@ -226,6 +295,7 @@ class AXIStreamSource(object):
frame = AXIStreamFrame() frame = AXIStreamFrame()
data = [] data = []
keep = [] keep = []
id = []
dest = [] dest = []
user = [] user = []
B = 0 B = 0
@ -250,6 +320,7 @@ class AXIStreamSource(object):
else: else:
tdata.next = 0 tdata.next = 0
tkeep.next = 0 tkeep.next = 0
tid.next = 0
tdest.next = 0 tdest.next = 0
tuser.next = False tuser.next = False
tvalid_int.next = False tvalid_int.next = False
@ -264,6 +335,7 @@ class AXIStreamSource(object):
else: else:
tdata.next = data.pop(0) tdata.next = data.pop(0)
tkeep.next = keep.pop(0) tkeep.next = keep.pop(0)
tid.next = id.pop(0)
tdest.next = dest.pop(0) tdest.next = dest.pop(0)
tuser.next = user.pop(0) tuser.next = user.pop(0)
tvalid_int.next = True tvalid_int.next = True
@ -278,7 +350,7 @@ class AXIStreamSource(object):
frame.N = N frame.N = N
frame.M = M frame.M = M
frame.WL = WL frame.WL = WL
data, keep, dest, user = frame.build() data, keep, id, dest, user = frame.build()
if name is not None: if name is not None:
print("[%s] Sending frame %s" % (name, repr(frame))) print("[%s] Sending frame %s" % (name, repr(frame)))
if B > 0: if B > 0:
@ -288,6 +360,7 @@ class AXIStreamSource(object):
else: else:
tdata.next = data.pop(0) tdata.next = data.pop(0)
tkeep.next = keep.pop(0) tkeep.next = keep.pop(0)
tid.next = id.pop(0)
tdest.next = dest.pop(0) tdest.next = dest.pop(0)
tuser.next = user.pop(0) tuser.next = user.pop(0)
tvalid_int.next = True tvalid_int.next = True
@ -330,8 +403,9 @@ class AXIStreamSink(object):
tvalid=Signal(bool(False)), tvalid=Signal(bool(False)),
tready=Signal(bool(True)), tready=Signal(bool(True)),
tlast=Signal(bool(True)), tlast=Signal(bool(True)),
tid=Signal(intbv(0)),
tdest=Signal(intbv(0)), tdest=Signal(intbv(0)),
tuser=Signal(bool(False)), tuser=Signal(intbv(0)),
pause=0, pause=0,
name=None name=None
): ):
@ -353,6 +427,7 @@ class AXIStreamSink(object):
frame = AXIStreamFrame() frame = AXIStreamFrame()
data = [] data = []
keep = [] keep = []
id = []
dest = [] dest = []
user = [] user = []
B = 0 B = 0
@ -376,6 +451,7 @@ class AXIStreamSink(object):
frame = AXIStreamFrame() frame = AXIStreamFrame()
data = [] data = []
keep = [] keep = []
id = []
dest = [] dest = []
user = [] user = []
first = True first = True
@ -411,6 +487,7 @@ class AXIStreamSink(object):
else: else:
data.append(int(tdata)) data.append(int(tdata))
keep.append(int(tkeep)) keep.append(int(tkeep))
id.append(int(tid))
dest.append(int(tdest)) dest.append(int(tdest))
user.append(int(tuser)) user.append(int(tuser))
first = False first = False
@ -419,13 +496,14 @@ class AXIStreamSink(object):
frame.N = N frame.N = N
frame.M = M frame.M = M
frame.WL = WL frame.WL = WL
frame.parse(data, keep, dest, user) frame.parse(data, keep, id, dest, user)
self.queue.append(frame) self.queue.append(frame)
if name is not None: if name is not None:
print("[%s] Got frame %s" % (name, repr(frame))) print("[%s] Got frame %s" % (name, repr(frame)))
frame = AXIStreamFrame() frame = AXIStreamFrame()
data = [] data = []
keep = [] keep = []
id = []
dest = [] dest = []
user = [] user = []
first = True first = True

93
lib/axis/tb/test_axis_adapter_64_8.py
View File

@ -44,9 +44,17 @@ def bench():
# Parameters # Parameters
INPUT_DATA_WIDTH = 64 INPUT_DATA_WIDTH = 64
INPUT_KEEP_ENABLE = (INPUT_DATA_WIDTH>8)
INPUT_KEEP_WIDTH = (INPUT_DATA_WIDTH/8) INPUT_KEEP_WIDTH = (INPUT_DATA_WIDTH/8)
OUTPUT_DATA_WIDTH = 8 OUTPUT_DATA_WIDTH = 8
OUTPUT_KEEP_ENABLE = (OUTPUT_DATA_WIDTH>8)
OUTPUT_KEEP_WIDTH = (OUTPUT_DATA_WIDTH/8) OUTPUT_KEEP_WIDTH = (OUTPUT_DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))
@ -54,19 +62,23 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[INPUT_DATA_WIDTH:]) input_axis_tdata = Signal(intbv(0)[INPUT_DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[INPUT_KEEP_WIDTH:]) input_axis_tkeep = Signal(intbv(1)[INPUT_KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0)) input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0)) input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0)) input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0)) output_axis_tready = Signal(bool(0))
# Outputs # Outputs
input_axis_tready = Signal(bool(0)) input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[OUTPUT_DATA_WIDTH:]) output_axis_tdata = Signal(intbv(0)[OUTPUT_DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[OUTPUT_KEEP_WIDTH:]) output_axis_tkeep = Signal(intbv(1)[OUTPUT_KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0)) output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0)) output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0)) output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks # sources and sinks
source_pause = Signal(bool(0)) source_pause = Signal(bool(0))
@ -82,6 +94,8 @@ def bench():
tvalid=input_axis_tvalid, tvalid=input_axis_tvalid,
tready=input_axis_tready, tready=input_axis_tready,
tlast=input_axis_tlast, tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser, tuser=input_axis_tuser,
pause=source_pause, pause=source_pause,
name='source' name='source'
@ -97,6 +111,8 @@ def bench():
tvalid=output_axis_tvalid, tvalid=output_axis_tvalid,
tready=output_axis_tready, tready=output_axis_tready,
tlast=output_axis_tlast, tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser, tuser=output_axis_tuser,
pause=sink_pause, pause=sink_pause,
name='sink' name='sink'
@ -117,6 +133,8 @@ def bench():
input_axis_tvalid=input_axis_tvalid, input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready, input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast, input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser, input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata, output_axis_tdata=output_axis_tdata,
@ -124,6 +142,8 @@ def bench():
output_axis_tvalid=output_axis_tvalid, output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready, output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast, output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser output_axis_tuser=output_axis_tuser
) )
@ -169,10 +189,14 @@ def bench():
print("test 1: test packet, length %d" % payload_len) print("test 1: test packet, length %d" % payload_len)
current_test.next = 1 current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(payload_len))) b'\x80\x00' +
bytearray(range(payload_len)),
id=1,
dest=1,
)
for wait in wait_normal, wait_pause_source, wait_pause_sink: for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame) source.send(test_frame)
@ -197,14 +221,22 @@ def bench():
print("test 2: back-to-back packets, length %d" % payload_len) print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2 current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(payload_len))) b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + bytearray(range(payload_len)),
b'\x5A\x51\x52\x53\x54\x55' + id=2,
b'\x80\x00' + dest=1,
bytearray(range(payload_len))) )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(payload_len)),
id=2,
dest=2,
)
for wait in wait_normal, wait_pause_source, wait_pause_sink: for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1) source.send(test_frame1)
@ -234,16 +266,23 @@ def bench():
print("test 3: tuser assert, length %d" % payload_len) print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3 current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(payload_len))) b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + bytearray(range(payload_len)),
b'\x5A\x51\x52\x53\x54\x55' + id=3,
b'\x80\x00' + dest=1,
bytearray(range(payload_len))) last_cycle_user=1
)
test_frame1.user = 1 test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(payload_len)),
id=3,
dest=2,
)
for wait in wait_normal, wait_pause_source, wait_pause_sink: for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1) source.send(test_frame1)
@ -260,7 +299,7 @@ def bench():
rx_frame = sink.recv() rx_frame = sink.recv()
assert rx_frame == test_frame1 assert rx_frame == test_frame1
assert rx_frame.user[-1] assert rx_frame.last_cycle_user
rx_frame = sink.recv() rx_frame = sink.recv()

42
lib/axis/tb/test_axis_adapter_64_8.v
View File

@ -32,10 +32,18 @@ THE SOFTWARE.
module test_axis_adapter_64_8; module test_axis_adapter_64_8;
// Parameters // Parameters
localparam INPUT_DATA_WIDTH = 64; parameter INPUT_DATA_WIDTH = 64;
localparam INPUT_KEEP_WIDTH = (INPUT_DATA_WIDTH/8); parameter INPUT_KEEP_ENABLE = (INPUT_DATA_WIDTH>8);
localparam OUTPUT_DATA_WIDTH = 8; parameter INPUT_KEEP_WIDTH = (INPUT_DATA_WIDTH/8);
localparam OUTPUT_KEEP_WIDTH = (OUTPUT_DATA_WIDTH/8); parameter OUTPUT_DATA_WIDTH = 8;
parameter OUTPUT_KEEP_ENABLE = (OUTPUT_DATA_WIDTH>8);
parameter OUTPUT_KEEP_WIDTH = (OUTPUT_DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -46,7 +54,9 @@ reg [INPUT_DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [INPUT_KEEP_WIDTH-1:0] input_axis_tkeep = 0; reg [INPUT_KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0; reg input_axis_tvalid = 0;
reg input_axis_tlast = 0; reg input_axis_tlast = 0;
reg input_axis_tuser = 0; reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_axis_tready = 0; reg output_axis_tready = 0;
// Outputs // Outputs
@ -55,7 +65,9 @@ wire [OUTPUT_DATA_WIDTH-1:0] output_axis_tdata;
wire [OUTPUT_KEEP_WIDTH-1:0] output_axis_tkeep; wire [OUTPUT_KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid; wire output_axis_tvalid;
wire output_axis_tlast; wire output_axis_tlast;
wire output_axis_tuser; wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
initial begin initial begin
// myhdl integration // myhdl integration
@ -67,6 +79,8 @@ initial begin
input_axis_tkeep, input_axis_tkeep,
input_axis_tvalid, input_axis_tvalid,
input_axis_tlast, input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser, input_axis_tuser,
output_axis_tready output_axis_tready
); );
@ -76,6 +90,8 @@ initial begin
output_axis_tkeep, output_axis_tkeep,
output_axis_tvalid, output_axis_tvalid,
output_axis_tlast, output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser output_axis_tuser
); );
@ -86,9 +102,17 @@ end
axis_adapter #( axis_adapter #(
.INPUT_DATA_WIDTH(INPUT_DATA_WIDTH), .INPUT_DATA_WIDTH(INPUT_DATA_WIDTH),
.INPUT_KEEP_ENABLE(INPUT_KEEP_ENABLE),
.INPUT_KEEP_WIDTH(INPUT_KEEP_WIDTH), .INPUT_KEEP_WIDTH(INPUT_KEEP_WIDTH),
.OUTPUT_DATA_WIDTH(OUTPUT_DATA_WIDTH), .OUTPUT_DATA_WIDTH(OUTPUT_DATA_WIDTH),
.OUTPUT_KEEP_WIDTH(OUTPUT_KEEP_WIDTH) .OUTPUT_KEEP_ENABLE(OUTPUT_KEEP_ENABLE),
.OUTPUT_KEEP_WIDTH(OUTPUT_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) )
UUT ( UUT (
.clk(clk), .clk(clk),
@ -99,6 +123,8 @@ UUT (
.input_axis_tvalid(input_axis_tvalid), .input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready), .input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast), .input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser), .input_axis_tuser(input_axis_tuser),
// AXI output // AXI output
.output_axis_tdata(output_axis_tdata), .output_axis_tdata(output_axis_tdata),
@ -106,6 +132,8 @@ UUT (
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser) .output_axis_tuser(output_axis_tuser)
); );

93
lib/axis/tb/test_axis_adapter_8_64.py
View File

@ -44,9 +44,17 @@ def bench():
# Parameters # Parameters
INPUT_DATA_WIDTH = 8 INPUT_DATA_WIDTH = 8
INPUT_KEEP_ENABLE = (INPUT_DATA_WIDTH>8)
INPUT_KEEP_WIDTH = (INPUT_DATA_WIDTH/8) INPUT_KEEP_WIDTH = (INPUT_DATA_WIDTH/8)
OUTPUT_DATA_WIDTH = 64 OUTPUT_DATA_WIDTH = 64
OUTPUT_KEEP_ENABLE = (OUTPUT_DATA_WIDTH>8)
OUTPUT_KEEP_WIDTH = (OUTPUT_DATA_WIDTH/8) OUTPUT_KEEP_WIDTH = (OUTPUT_DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))
@ -54,19 +62,23 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[INPUT_DATA_WIDTH:]) input_axis_tdata = Signal(intbv(0)[INPUT_DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[INPUT_KEEP_WIDTH:]) input_axis_tkeep = Signal(intbv(1)[INPUT_KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0)) input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0)) input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0)) input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0)) output_axis_tready = Signal(bool(0))
# Outputs # Outputs
input_axis_tready = Signal(bool(0)) input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[OUTPUT_DATA_WIDTH:]) output_axis_tdata = Signal(intbv(0)[OUTPUT_DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[OUTPUT_KEEP_WIDTH:]) output_axis_tkeep = Signal(intbv(1)[OUTPUT_KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0)) output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0)) output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0)) output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks # sources and sinks
source_pause = Signal(bool(0)) source_pause = Signal(bool(0))
@ -82,6 +94,8 @@ def bench():
tvalid=input_axis_tvalid, tvalid=input_axis_tvalid,
tready=input_axis_tready, tready=input_axis_tready,
tlast=input_axis_tlast, tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser, tuser=input_axis_tuser,
pause=source_pause, pause=source_pause,
name='source' name='source'
@ -97,6 +111,8 @@ def bench():
tvalid=output_axis_tvalid, tvalid=output_axis_tvalid,
tready=output_axis_tready, tready=output_axis_tready,
tlast=output_axis_tlast, tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser, tuser=output_axis_tuser,
pause=sink_pause, pause=sink_pause,
name='sink' name='sink'
@ -117,6 +133,8 @@ def bench():
input_axis_tvalid=input_axis_tvalid, input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready, input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast, input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser, input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata, output_axis_tdata=output_axis_tdata,
@ -124,6 +142,8 @@ def bench():
output_axis_tvalid=output_axis_tvalid, output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready, output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast, output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser output_axis_tuser=output_axis_tuser
) )
@ -169,10 +189,14 @@ def bench():
print("test 1: test packet, length %d" % payload_len) print("test 1: test packet, length %d" % payload_len)
current_test.next = 1 current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(payload_len))) b'\x80\x00' +
bytearray(range(payload_len)),
id=1,
dest=1,
)
for wait in wait_normal, wait_pause_source, wait_pause_sink: for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame) source.send(test_frame)
@ -197,14 +221,22 @@ def bench():
print("test 2: back-to-back packets, length %d" % payload_len) print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2 current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(payload_len))) b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + bytearray(range(payload_len)),
b'\x5A\x51\x52\x53\x54\x55' + id=2,
b'\x80\x00' + dest=1,
bytearray(range(payload_len))) )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(payload_len)),
id=2,
dest=2,
)
for wait in wait_normal, wait_pause_source, wait_pause_sink: for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1) source.send(test_frame1)
@ -234,16 +266,23 @@ def bench():
print("test 3: tuser assert, length %d" % payload_len) print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3 current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(payload_len))) b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + bytearray(range(payload_len)),
b'\x5A\x51\x52\x53\x54\x55' + id=3,
b'\x80\x00' + dest=1,
bytearray(range(payload_len))) last_cycle_user=1
)
test_frame1.user = 1 test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(payload_len)),
id=3,
dest=2,
)
for wait in wait_normal, wait_pause_source, wait_pause_sink: for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1) source.send(test_frame1)
@ -260,7 +299,7 @@ def bench():
rx_frame = sink.recv() rx_frame = sink.recv()
assert rx_frame == test_frame1 assert rx_frame == test_frame1
assert rx_frame.user[-1] assert rx_frame.last_cycle_user
rx_frame = sink.recv() rx_frame = sink.recv()

42
lib/axis/tb/test_axis_adapter_8_64.v
View File

@ -32,10 +32,18 @@ THE SOFTWARE.
module test_axis_adapter_8_64; module test_axis_adapter_8_64;
// Parameters // Parameters
localparam INPUT_DATA_WIDTH = 8; parameter INPUT_DATA_WIDTH = 8;
localparam INPUT_KEEP_WIDTH = (INPUT_DATA_WIDTH/8); parameter INPUT_KEEP_ENABLE = (INPUT_DATA_WIDTH>8);
localparam OUTPUT_DATA_WIDTH = 64; parameter INPUT_KEEP_WIDTH = (INPUT_DATA_WIDTH/8);
localparam OUTPUT_KEEP_WIDTH = (OUTPUT_DATA_WIDTH/8); parameter OUTPUT_DATA_WIDTH = 64;
parameter OUTPUT_KEEP_ENABLE = (OUTPUT_DATA_WIDTH>8);
parameter OUTPUT_KEEP_WIDTH = (OUTPUT_DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -46,7 +54,9 @@ reg [INPUT_DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [INPUT_KEEP_WIDTH-1:0] input_axis_tkeep = 0; reg [INPUT_KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0; reg input_axis_tvalid = 0;
reg input_axis_tlast = 0; reg input_axis_tlast = 0;
reg input_axis_tuser = 0; reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_axis_tready = 0; reg output_axis_tready = 0;
// Outputs // Outputs
@ -55,7 +65,9 @@ wire [OUTPUT_DATA_WIDTH-1:0] output_axis_tdata;
wire [OUTPUT_KEEP_WIDTH-1:0] output_axis_tkeep; wire [OUTPUT_KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid; wire output_axis_tvalid;
wire output_axis_tlast; wire output_axis_tlast;
wire output_axis_tuser; wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
initial begin initial begin
// myhdl integration // myhdl integration
@ -67,6 +79,8 @@ initial begin
input_axis_tkeep, input_axis_tkeep,
input_axis_tvalid, input_axis_tvalid,
input_axis_tlast, input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser, input_axis_tuser,
output_axis_tready output_axis_tready
); );
@ -76,6 +90,8 @@ initial begin
output_axis_tkeep, output_axis_tkeep,
output_axis_tvalid, output_axis_tvalid,
output_axis_tlast, output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser output_axis_tuser
); );
@ -86,9 +102,17 @@ end
axis_adapter #( axis_adapter #(
.INPUT_DATA_WIDTH(INPUT_DATA_WIDTH), .INPUT_DATA_WIDTH(INPUT_DATA_WIDTH),
.INPUT_KEEP_ENABLE(INPUT_KEEP_ENABLE),
.INPUT_KEEP_WIDTH(INPUT_KEEP_WIDTH), .INPUT_KEEP_WIDTH(INPUT_KEEP_WIDTH),
.OUTPUT_DATA_WIDTH(OUTPUT_DATA_WIDTH), .OUTPUT_DATA_WIDTH(OUTPUT_DATA_WIDTH),
.OUTPUT_KEEP_WIDTH(OUTPUT_KEEP_WIDTH) .OUTPUT_KEEP_ENABLE(OUTPUT_KEEP_ENABLE),
.OUTPUT_KEEP_WIDTH(OUTPUT_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) )
UUT ( UUT (
.clk(clk), .clk(clk),
@ -99,6 +123,8 @@ UUT (
.input_axis_tvalid(input_axis_tvalid), .input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready), .input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast), .input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser), .input_axis_tuser(input_axis_tuser),
// AXI output // AXI output
.output_axis_tdata(output_axis_tdata), .output_axis_tdata(output_axis_tdata),
@ -106,6 +132,8 @@ UUT (
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser) .output_axis_tuser(output_axis_tuser)
); );

214
lib/axis/tb/test_axis_arb_mux_4.py
View File

@ -47,6 +47,14 @@ def bench():
# Parameters # Parameters
DATA_WIDTH = 8 DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))
@ -54,21 +62,33 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_0_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_0_axis_tvalid = Signal(bool(0)) input_0_axis_tvalid = Signal(bool(0))
input_0_axis_tlast = Signal(bool(0)) input_0_axis_tlast = Signal(bool(0))
input_0_axis_tuser = Signal(bool(0)) input_0_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_0_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_0_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_1_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_1_axis_tvalid = Signal(bool(0)) input_1_axis_tvalid = Signal(bool(0))
input_1_axis_tlast = Signal(bool(0)) input_1_axis_tlast = Signal(bool(0))
input_1_axis_tuser = Signal(bool(0)) input_1_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_1_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_1_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_2_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_2_axis_tvalid = Signal(bool(0)) input_2_axis_tvalid = Signal(bool(0))
input_2_axis_tlast = Signal(bool(0)) input_2_axis_tlast = Signal(bool(0))
input_2_axis_tuser = Signal(bool(0)) input_2_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_2_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_2_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_3_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_3_axis_tvalid = Signal(bool(0)) input_3_axis_tvalid = Signal(bool(0))
input_3_axis_tlast = Signal(bool(0)) input_3_axis_tlast = Signal(bool(0))
input_3_axis_tuser = Signal(bool(0)) input_3_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_3_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_3_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0)) output_axis_tready = Signal(bool(0))
@ -79,9 +99,12 @@ def bench():
input_3_axis_tready = Signal(bool(0)) input_3_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0)) output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0)) output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0)) output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks # sources and sinks
source_0_pause = Signal(bool(0)) source_0_pause = Signal(bool(0))
@ -96,9 +119,12 @@ def bench():
clk, clk,
rst, rst,
tdata=input_0_axis_tdata, tdata=input_0_axis_tdata,
tkeep=input_0_axis_tkeep,
tvalid=input_0_axis_tvalid, tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready, tready=input_0_axis_tready,
tlast=input_0_axis_tlast, tlast=input_0_axis_tlast,
tid=input_0_axis_tid,
tdest=input_0_axis_tdest,
tuser=input_0_axis_tuser, tuser=input_0_axis_tuser,
pause=source_0_pause, pause=source_0_pause,
name='source_0' name='source_0'
@ -110,9 +136,12 @@ def bench():
clk, clk,
rst, rst,
tdata=input_1_axis_tdata, tdata=input_1_axis_tdata,
tkeep=input_1_axis_tkeep,
tvalid=input_1_axis_tvalid, tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready, tready=input_1_axis_tready,
tlast=input_1_axis_tlast, tlast=input_1_axis_tlast,
tid=input_1_axis_tid,
tdest=input_1_axis_tdest,
tuser=input_1_axis_tuser, tuser=input_1_axis_tuser,
pause=source_1_pause, pause=source_1_pause,
name='source_1' name='source_1'
@ -124,9 +153,12 @@ def bench():
clk, clk,
rst, rst,
tdata=input_2_axis_tdata, tdata=input_2_axis_tdata,
tkeep=input_2_axis_tkeep,
tvalid=input_2_axis_tvalid, tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready, tready=input_2_axis_tready,
tlast=input_2_axis_tlast, tlast=input_2_axis_tlast,
tid=input_2_axis_tid,
tdest=input_2_axis_tdest,
tuser=input_2_axis_tuser, tuser=input_2_axis_tuser,
pause=source_2_pause, pause=source_2_pause,
name='source_2' name='source_2'
@ -138,9 +170,12 @@ def bench():
clk, clk,
rst, rst,
tdata=input_3_axis_tdata, tdata=input_3_axis_tdata,
tkeep=input_3_axis_tkeep,
tvalid=input_3_axis_tvalid, tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready, tready=input_3_axis_tready,
tlast=input_3_axis_tlast, tlast=input_3_axis_tlast,
tid=input_3_axis_tid,
tdest=input_3_axis_tdest,
tuser=input_3_axis_tuser, tuser=input_3_axis_tuser,
pause=source_3_pause, pause=source_3_pause,
name='source_3' name='source_3'
@ -152,9 +187,12 @@ def bench():
clk, clk,
rst, rst,
tdata=output_axis_tdata, tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid, tvalid=output_axis_tvalid,
tready=output_axis_tready, tready=output_axis_tready,
tlast=output_axis_tlast, tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser, tuser=output_axis_tuser,
pause=sink_pause, pause=sink_pause,
name='sink' name='sink'
@ -171,30 +209,45 @@ def bench():
current_test=current_test, current_test=current_test,
input_0_axis_tdata=input_0_axis_tdata, input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tkeep=input_0_axis_tkeep,
input_0_axis_tvalid=input_0_axis_tvalid, input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready, input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast, input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tid=input_0_axis_tid,
input_0_axis_tdest=input_0_axis_tdest,
input_0_axis_tuser=input_0_axis_tuser, input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata, input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tkeep=input_1_axis_tkeep,
input_1_axis_tvalid=input_1_axis_tvalid, input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready, input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast, input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tid=input_1_axis_tid,
input_1_axis_tdest=input_1_axis_tdest,
input_1_axis_tuser=input_1_axis_tuser, input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata, input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tkeep=input_2_axis_tkeep,
input_2_axis_tvalid=input_2_axis_tvalid, input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready, input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast, input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tid=input_2_axis_tid,
input_2_axis_tdest=input_2_axis_tdest,
input_2_axis_tuser=input_2_axis_tuser, input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata, input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tkeep=input_3_axis_tkeep,
input_3_axis_tvalid=input_3_axis_tvalid, input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready, input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast, input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tid=input_3_axis_tid,
input_3_axis_tdest=input_3_axis_tdest,
input_3_axis_tuser=input_3_axis_tuser, input_3_axis_tuser=input_3_axis_tuser,
output_axis_tdata=output_axis_tdata, output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid, output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready, output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast, output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser output_axis_tuser=output_axis_tuser
) )
@ -219,10 +272,15 @@ def bench():
print("test 1: port 0") print("test 1: port 0")
current_test.next = 1 current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x00\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x00\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
source_0.send(test_frame) source_0.send(test_frame)
yield clk.posedge yield clk.posedge
@ -241,10 +299,15 @@ def bench():
print("test 2: port 1") print("test 2: port 1")
current_test.next = 2 current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x01\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x00\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x01' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=2,
dest=1
)
source_1.send(test_frame) source_1.send(test_frame)
yield clk.posedge yield clk.posedge
@ -263,14 +326,23 @@ def bench():
print("test 3: back-to-back packets, same port") print("test 3: back-to-back packets, same port")
current_test.next = 3 current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x00\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x00\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x00\x52\x53\x54\x55' + id=3,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x00\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=2
)
source_0.send(test_frame1) source_0.send(test_frame1)
source_0.send(test_frame2) source_0.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -294,14 +366,23 @@ def bench():
print("test 4: back-to-back packets, different ports") print("test 4: back-to-back packets, different ports")
current_test.next = 4 current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x01\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x01\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x02\x52\x53\x54\x55' + id=4,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2
)
source_1.send(test_frame1) source_1.send(test_frame1)
source_2.send(test_frame2) source_2.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -325,14 +406,23 @@ def bench():
print("test 5: alterate pause source") print("test 5: alterate pause source")
current_test.next = 5 current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x01\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x01\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x02\x52\x53\x54\x55' + id=5,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=1
)
source_1.send(test_frame1) source_1.send(test_frame1)
source_2.send(test_frame2) source_2.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -367,14 +457,23 @@ def bench():
print("test 6: alterate pause sink") print("test 6: alterate pause sink")
current_test.next = 6 current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x01\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x01\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x02\x52\x53\x54\x55' + id=6,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
source_1.send(test_frame1) source_1.send(test_frame1)
source_2.send(test_frame2) source_2.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -403,14 +502,23 @@ def bench():
print("test 7: back-to-back packets, different ports, arbitration test") print("test 7: back-to-back packets, different ports, arbitration test")
current_test.next = 7 current_test.next = 7
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x01\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x01\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x02\x52\x53\x54\x55' + id=7,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=2
)
source_1.send(test_frame1) source_1.send(test_frame1)
source_2.send(test_frame2) source_2.send(test_frame2)
source_2.send(test_frame2) source_2.send(test_frame2)

75
lib/axis/tb/test_axis_arb_mux_4.v
View File

@ -32,7 +32,15 @@ THE SOFTWARE.
module test_axis_arb_mux_4; module test_axis_arb_mux_4;
// Parameters // Parameters
localparam DATA_WIDTH = 8; parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -40,21 +48,33 @@ reg rst = 0;
reg [7:0] current_test = 0; reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] input_0_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_0_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_0_axis_tkeep = 0;
reg input_0_axis_tvalid = 0; reg input_0_axis_tvalid = 0;
reg input_0_axis_tlast = 0; reg input_0_axis_tlast = 0;
reg input_0_axis_tuser = 0; reg [ID_WIDTH-1:0] input_0_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_0_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_0_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_1_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_1_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_1_axis_tkeep = 0;
reg input_1_axis_tvalid = 0; reg input_1_axis_tvalid = 0;
reg input_1_axis_tlast = 0; reg input_1_axis_tlast = 0;
reg input_1_axis_tuser = 0; reg [ID_WIDTH-1:0] input_1_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_1_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_1_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_2_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_2_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_2_axis_tkeep = 0;
reg input_2_axis_tvalid = 0; reg input_2_axis_tvalid = 0;
reg input_2_axis_tlast = 0; reg input_2_axis_tlast = 0;
reg input_2_axis_tuser = 0; reg [ID_WIDTH-1:0] input_2_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_2_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_2_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_3_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_3_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_3_axis_tkeep = 0;
reg input_3_axis_tvalid = 0; reg input_3_axis_tvalid = 0;
reg input_3_axis_tlast = 0; reg input_3_axis_tlast = 0;
reg input_3_axis_tuser = 0; reg [ID_WIDTH-1:0] input_3_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_3_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_3_axis_tuser = 0;
reg output_axis_tready = 0; reg output_axis_tready = 0;
@ -65,9 +85,12 @@ wire input_2_axis_tready;
wire input_3_axis_tready; wire input_3_axis_tready;
wire [DATA_WIDTH-1:0] output_axis_tdata; wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid; wire output_axis_tvalid;
wire output_axis_tlast; wire output_axis_tlast;
wire output_axis_tuser; wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
initial begin initial begin
// myhdl integration // myhdl integration
@ -76,20 +99,32 @@ initial begin
rst, rst,
current_test, current_test,
input_0_axis_tdata, input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid, input_0_axis_tvalid,
input_0_axis_tlast, input_0_axis_tlast,
input_0_axis_tid,
input_0_axis_tdest,
input_0_axis_tuser, input_0_axis_tuser,
input_1_axis_tdata, input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid, input_1_axis_tvalid,
input_1_axis_tlast, input_1_axis_tlast,
input_1_axis_tid,
input_1_axis_tdest,
input_1_axis_tuser, input_1_axis_tuser,
input_2_axis_tdata, input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid, input_2_axis_tvalid,
input_2_axis_tlast, input_2_axis_tlast,
input_2_axis_tid,
input_2_axis_tdest,
input_2_axis_tuser, input_2_axis_tuser,
input_3_axis_tdata, input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid, input_3_axis_tvalid,
input_3_axis_tlast, input_3_axis_tlast,
input_3_axis_tid,
input_3_axis_tdest,
input_3_axis_tuser, input_3_axis_tuser,
output_axis_tready output_axis_tready
); );
@ -99,8 +134,11 @@ initial begin
input_2_axis_tready, input_2_axis_tready,
input_3_axis_tready, input_3_axis_tready,
output_axis_tdata, output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid, output_axis_tvalid,
output_axis_tlast, output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser output_axis_tuser
); );
@ -110,37 +148,60 @@ initial begin
end end
axis_arb_mux_4 #( axis_arb_mux_4 #(
.DATA_WIDTH(DATA_WIDTH) .DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) )
UUT ( UUT (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
// AXI inputs // AXI inputs
.input_0_axis_tdata(input_0_axis_tdata), .input_0_axis_tdata(input_0_axis_tdata),
.input_0_axis_tkeep(input_0_axis_tkeep),
.input_0_axis_tvalid(input_0_axis_tvalid), .input_0_axis_tvalid(input_0_axis_tvalid),
.input_0_axis_tready(input_0_axis_tready), .input_0_axis_tready(input_0_axis_tready),
.input_0_axis_tlast(input_0_axis_tlast), .input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tid(input_0_axis_tid),
.input_0_axis_tdest(input_0_axis_tdest),
.input_0_axis_tuser(input_0_axis_tuser), .input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata), .input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tkeep(input_1_axis_tkeep),
.input_1_axis_tvalid(input_1_axis_tvalid), .input_1_axis_tvalid(input_1_axis_tvalid),
.input_1_axis_tready(input_1_axis_tready), .input_1_axis_tready(input_1_axis_tready),
.input_1_axis_tlast(input_1_axis_tlast), .input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tid(input_1_axis_tid),
.input_1_axis_tdest(input_1_axis_tdest),
.input_1_axis_tuser(input_1_axis_tuser), .input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata), .input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tkeep(input_2_axis_tkeep),
.input_2_axis_tvalid(input_2_axis_tvalid), .input_2_axis_tvalid(input_2_axis_tvalid),
.input_2_axis_tready(input_2_axis_tready), .input_2_axis_tready(input_2_axis_tready),
.input_2_axis_tlast(input_2_axis_tlast), .input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tid(input_2_axis_tid),
.input_2_axis_tdest(input_2_axis_tdest),
.input_2_axis_tuser(input_2_axis_tuser), .input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata), .input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tkeep(input_3_axis_tkeep),
.input_3_axis_tvalid(input_3_axis_tvalid), .input_3_axis_tvalid(input_3_axis_tvalid),
.input_3_axis_tready(input_3_axis_tready), .input_3_axis_tready(input_3_axis_tready),
.input_3_axis_tlast(input_3_axis_tlast), .input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tid(input_3_axis_tid),
.input_3_axis_tdest(input_3_axis_tdest),
.input_3_axis_tuser(input_3_axis_tuser), .input_3_axis_tuser(input_3_axis_tuser),
// AXI output // AXI output
.output_axis_tdata(output_axis_tdata), .output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser) .output_axis_tuser(output_axis_tuser)
); );

214
lib/axis/tb/test_axis_arb_mux_64_4.py → lib/axis/tb/test_axis_arb_mux_4_64.py
View File

@ -28,13 +28,13 @@ import os
import axis_ep import axis_ep
module = 'axis_arb_mux_64_4' module = 'axis_arb_mux_4'
testbench = 'test_%s' % module testbench = 'test_%s_64' % module
srcs = [] srcs = []
srcs.append("../rtl/%s.v" % module) srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/axis_mux_64_4.v") srcs.append("../rtl/axis_mux_4.v")
srcs.append("../rtl/arbiter.v") srcs.append("../rtl/arbiter.v")
srcs.append("../rtl/priority_encoder.v") srcs.append("../rtl/priority_encoder.v")
srcs.append("%s.v" % testbench) srcs.append("%s.v" % testbench)
@ -47,7 +47,14 @@ def bench():
# Parameters # Parameters
DATA_WIDTH = 64 DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8) KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))
@ -55,25 +62,33 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_0_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_0_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_0_axis_tvalid = Signal(bool(0)) input_0_axis_tvalid = Signal(bool(0))
input_0_axis_tlast = Signal(bool(0)) input_0_axis_tlast = Signal(bool(0))
input_0_axis_tuser = Signal(bool(0)) input_0_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_0_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_0_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_1_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_1_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_1_axis_tvalid = Signal(bool(0)) input_1_axis_tvalid = Signal(bool(0))
input_1_axis_tlast = Signal(bool(0)) input_1_axis_tlast = Signal(bool(0))
input_1_axis_tuser = Signal(bool(0)) input_1_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_1_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_1_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_2_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_2_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_2_axis_tvalid = Signal(bool(0)) input_2_axis_tvalid = Signal(bool(0))
input_2_axis_tlast = Signal(bool(0)) input_2_axis_tlast = Signal(bool(0))
input_2_axis_tuser = Signal(bool(0)) input_2_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_2_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_2_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_3_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_3_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_3_axis_tvalid = Signal(bool(0)) input_3_axis_tvalid = Signal(bool(0))
input_3_axis_tlast = Signal(bool(0)) input_3_axis_tlast = Signal(bool(0))
input_3_axis_tuser = Signal(bool(0)) input_3_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_3_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_3_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0)) output_axis_tready = Signal(bool(0))
@ -84,10 +99,12 @@ def bench():
input_3_axis_tready = Signal(bool(0)) input_3_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0)) output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0)) output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0)) output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks # sources and sinks
source_0_pause = Signal(bool(0)) source_0_pause = Signal(bool(0))
@ -106,6 +123,8 @@ def bench():
tvalid=input_0_axis_tvalid, tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready, tready=input_0_axis_tready,
tlast=input_0_axis_tlast, tlast=input_0_axis_tlast,
tid=input_0_axis_tid,
tdest=input_0_axis_tdest,
tuser=input_0_axis_tuser, tuser=input_0_axis_tuser,
pause=source_0_pause, pause=source_0_pause,
name='source_0' name='source_0'
@ -121,6 +140,8 @@ def bench():
tvalid=input_1_axis_tvalid, tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready, tready=input_1_axis_tready,
tlast=input_1_axis_tlast, tlast=input_1_axis_tlast,
tid=input_1_axis_tid,
tdest=input_1_axis_tdest,
tuser=input_1_axis_tuser, tuser=input_1_axis_tuser,
pause=source_1_pause, pause=source_1_pause,
name='source_1' name='source_1'
@ -136,6 +157,8 @@ def bench():
tvalid=input_2_axis_tvalid, tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready, tready=input_2_axis_tready,
tlast=input_2_axis_tlast, tlast=input_2_axis_tlast,
tid=input_2_axis_tid,
tdest=input_2_axis_tdest,
tuser=input_2_axis_tuser, tuser=input_2_axis_tuser,
pause=source_2_pause, pause=source_2_pause,
name='source_2' name='source_2'
@ -151,6 +174,8 @@ def bench():
tvalid=input_3_axis_tvalid, tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready, tready=input_3_axis_tready,
tlast=input_3_axis_tlast, tlast=input_3_axis_tlast,
tid=input_3_axis_tid,
tdest=input_3_axis_tdest,
tuser=input_3_axis_tuser, tuser=input_3_axis_tuser,
pause=source_3_pause, pause=source_3_pause,
name='source_3' name='source_3'
@ -166,6 +191,8 @@ def bench():
tvalid=output_axis_tvalid, tvalid=output_axis_tvalid,
tready=output_axis_tready, tready=output_axis_tready,
tlast=output_axis_tlast, tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser, tuser=output_axis_tuser,
pause=sink_pause, pause=sink_pause,
name='sink' name='sink'
@ -186,24 +213,32 @@ def bench():
input_0_axis_tvalid=input_0_axis_tvalid, input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready, input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast, input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tid=input_0_axis_tid,
input_0_axis_tdest=input_0_axis_tdest,
input_0_axis_tuser=input_0_axis_tuser, input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata, input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tkeep=input_1_axis_tkeep, input_1_axis_tkeep=input_1_axis_tkeep,
input_1_axis_tvalid=input_1_axis_tvalid, input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready, input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast, input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tid=input_1_axis_tid,
input_1_axis_tdest=input_1_axis_tdest,
input_1_axis_tuser=input_1_axis_tuser, input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata, input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tkeep=input_2_axis_tkeep, input_2_axis_tkeep=input_2_axis_tkeep,
input_2_axis_tvalid=input_2_axis_tvalid, input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready, input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast, input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tid=input_2_axis_tid,
input_2_axis_tdest=input_2_axis_tdest,
input_2_axis_tuser=input_2_axis_tuser, input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata, input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tkeep=input_3_axis_tkeep, input_3_axis_tkeep=input_3_axis_tkeep,
input_3_axis_tvalid=input_3_axis_tvalid, input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready, input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast, input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tid=input_3_axis_tid,
input_3_axis_tdest=input_3_axis_tdest,
input_3_axis_tuser=input_3_axis_tuser, input_3_axis_tuser=input_3_axis_tuser,
output_axis_tdata=output_axis_tdata, output_axis_tdata=output_axis_tdata,
@ -211,6 +246,8 @@ def bench():
output_axis_tvalid=output_axis_tvalid, output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready, output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast, output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser output_axis_tuser=output_axis_tuser
) )
@ -235,10 +272,15 @@ def bench():
print("test 1: port 0") print("test 1: port 0")
current_test.next = 1 current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x00\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x00\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
source_0.send(test_frame) source_0.send(test_frame)
yield clk.posedge yield clk.posedge
@ -257,10 +299,15 @@ def bench():
print("test 2: port 1") print("test 2: port 1")
current_test.next = 2 current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x01\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x00\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x01' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=2,
dest=1
)
source_1.send(test_frame) source_1.send(test_frame)
yield clk.posedge yield clk.posedge
@ -279,14 +326,23 @@ def bench():
print("test 3: back-to-back packets, same port") print("test 3: back-to-back packets, same port")
current_test.next = 3 current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x00\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x00\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x00\x52\x53\x54\x55' + id=3,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x00\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=2
)
source_0.send(test_frame1) source_0.send(test_frame1)
source_0.send(test_frame2) source_0.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -310,14 +366,23 @@ def bench():
print("test 4: back-to-back packets, different ports") print("test 4: back-to-back packets, different ports")
current_test.next = 4 current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x01\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x01\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x02\x52\x53\x54\x55' + id=4,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2
)
source_1.send(test_frame1) source_1.send(test_frame1)
source_2.send(test_frame2) source_2.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -341,14 +406,23 @@ def bench():
print("test 5: alterate pause source") print("test 5: alterate pause source")
current_test.next = 5 current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x01\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x01\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x02\x52\x53\x54\x55' + id=5,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=1
)
source_1.send(test_frame1) source_1.send(test_frame1)
source_2.send(test_frame2) source_2.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -383,14 +457,23 @@ def bench():
print("test 6: alterate pause sink") print("test 6: alterate pause sink")
current_test.next = 6 current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x01\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x01\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x02\x52\x53\x54\x55' + id=6,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
source_1.send(test_frame1) source_1.send(test_frame1)
source_2.send(test_frame2) source_2.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -419,14 +502,23 @@ def bench():
print("test 7: back-to-back packets, different ports, arbitration test") print("test 7: back-to-back packets, different ports, arbitration test")
current_test.next = 7 current_test.next = 7
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x01\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x01\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x02\x52\x53\x54\x55' + id=7,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=2
)
source_1.send(test_frame1) source_1.send(test_frame1)
source_2.send(test_frame2) source_2.send(test_frame2)
source_2.send(test_frame2) source_2.send(test_frame2)

71
lib/axis/tb/test_axis_arb_mux_64_4.v → lib/axis/tb/test_axis_arb_mux_4_64.v
View File

@ -27,13 +27,20 @@ THE SOFTWARE.
`timescale 1ns / 1ps `timescale 1ns / 1ps
/* /*
* Testbench for axis_arb_mux_64_4 * Testbench for axis_arb_mux_4
*/ */
module test_axis_arb_mux_64_4; module test_axis_arb_mux_4_64;
// Parameters // Parameters
localparam DATA_WIDTH = 64; parameter DATA_WIDTH = 64;
localparam KEEP_WIDTH = (DATA_WIDTH/8); parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -44,22 +51,30 @@ reg [DATA_WIDTH-1:0] input_0_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_0_axis_tkeep = 0; reg [KEEP_WIDTH-1:0] input_0_axis_tkeep = 0;
reg input_0_axis_tvalid = 0; reg input_0_axis_tvalid = 0;
reg input_0_axis_tlast = 0; reg input_0_axis_tlast = 0;
reg input_0_axis_tuser = 0; reg [ID_WIDTH-1:0] input_0_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_0_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_0_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_1_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_1_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_1_axis_tkeep = 0; reg [KEEP_WIDTH-1:0] input_1_axis_tkeep = 0;
reg input_1_axis_tvalid = 0; reg input_1_axis_tvalid = 0;
reg input_1_axis_tlast = 0; reg input_1_axis_tlast = 0;
reg input_1_axis_tuser = 0; reg [ID_WIDTH-1:0] input_1_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_1_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_1_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_2_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_2_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_2_axis_tkeep = 0; reg [KEEP_WIDTH-1:0] input_2_axis_tkeep = 0;
reg input_2_axis_tvalid = 0; reg input_2_axis_tvalid = 0;
reg input_2_axis_tlast = 0; reg input_2_axis_tlast = 0;
reg input_2_axis_tuser = 0; reg [ID_WIDTH-1:0] input_2_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_2_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_2_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_3_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_3_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_3_axis_tkeep = 0; reg [KEEP_WIDTH-1:0] input_3_axis_tkeep = 0;
reg input_3_axis_tvalid = 0; reg input_3_axis_tvalid = 0;
reg input_3_axis_tlast = 0; reg input_3_axis_tlast = 0;
reg input_3_axis_tuser = 0; reg [ID_WIDTH-1:0] input_3_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_3_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_3_axis_tuser = 0;
reg output_axis_tready = 0; reg output_axis_tready = 0;
@ -73,7 +88,9 @@ wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep; wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid; wire output_axis_tvalid;
wire output_axis_tlast; wire output_axis_tlast;
wire output_axis_tuser; wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
initial begin initial begin
// myhdl integration // myhdl integration
@ -85,21 +102,29 @@ initial begin
input_0_axis_tkeep, input_0_axis_tkeep,
input_0_axis_tvalid, input_0_axis_tvalid,
input_0_axis_tlast, input_0_axis_tlast,
input_0_axis_tid,
input_0_axis_tdest,
input_0_axis_tuser, input_0_axis_tuser,
input_1_axis_tdata, input_1_axis_tdata,
input_1_axis_tkeep, input_1_axis_tkeep,
input_1_axis_tvalid, input_1_axis_tvalid,
input_1_axis_tlast, input_1_axis_tlast,
input_1_axis_tid,
input_1_axis_tdest,
input_1_axis_tuser, input_1_axis_tuser,
input_2_axis_tdata, input_2_axis_tdata,
input_2_axis_tkeep, input_2_axis_tkeep,
input_2_axis_tvalid, input_2_axis_tvalid,
input_2_axis_tlast, input_2_axis_tlast,
input_2_axis_tid,
input_2_axis_tdest,
input_2_axis_tuser, input_2_axis_tuser,
input_3_axis_tdata, input_3_axis_tdata,
input_3_axis_tkeep, input_3_axis_tkeep,
input_3_axis_tvalid, input_3_axis_tvalid,
input_3_axis_tlast, input_3_axis_tlast,
input_3_axis_tid,
input_3_axis_tdest,
input_3_axis_tuser, input_3_axis_tuser,
output_axis_tready output_axis_tready
); );
@ -112,16 +137,26 @@ initial begin
output_axis_tkeep, output_axis_tkeep,
output_axis_tvalid, output_axis_tvalid,
output_axis_tlast, output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser output_axis_tuser
); );
// dump file // dump file
$dumpfile("test_axis_arb_mux_64_4.lxt"); $dumpfile("test_axis_arb_mux_4_64.lxt");
$dumpvars(0, test_axis_arb_mux_64_4); $dumpvars(0, test_axis_arb_mux_4_64);
end end
axis_arb_mux_64_4 #( axis_arb_mux_4 #(
.DATA_WIDTH(DATA_WIDTH) .DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) )
UUT ( UUT (
.clk(clk), .clk(clk),
@ -132,24 +167,32 @@ UUT (
.input_0_axis_tvalid(input_0_axis_tvalid), .input_0_axis_tvalid(input_0_axis_tvalid),
.input_0_axis_tready(input_0_axis_tready), .input_0_axis_tready(input_0_axis_tready),
.input_0_axis_tlast(input_0_axis_tlast), .input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tid(input_0_axis_tid),
.input_0_axis_tdest(input_0_axis_tdest),
.input_0_axis_tuser(input_0_axis_tuser), .input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata), .input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tkeep(input_1_axis_tkeep), .input_1_axis_tkeep(input_1_axis_tkeep),
.input_1_axis_tvalid(input_1_axis_tvalid), .input_1_axis_tvalid(input_1_axis_tvalid),
.input_1_axis_tready(input_1_axis_tready), .input_1_axis_tready(input_1_axis_tready),
.input_1_axis_tlast(input_1_axis_tlast), .input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tid(input_1_axis_tid),
.input_1_axis_tdest(input_1_axis_tdest),
.input_1_axis_tuser(input_1_axis_tuser), .input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata), .input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tkeep(input_2_axis_tkeep), .input_2_axis_tkeep(input_2_axis_tkeep),
.input_2_axis_tvalid(input_2_axis_tvalid), .input_2_axis_tvalid(input_2_axis_tvalid),
.input_2_axis_tready(input_2_axis_tready), .input_2_axis_tready(input_2_axis_tready),
.input_2_axis_tlast(input_2_axis_tlast), .input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tid(input_2_axis_tid),
.input_2_axis_tdest(input_2_axis_tdest),
.input_2_axis_tuser(input_2_axis_tuser), .input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata), .input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tkeep(input_3_axis_tkeep), .input_3_axis_tkeep(input_3_axis_tkeep),
.input_3_axis_tvalid(input_3_axis_tvalid), .input_3_axis_tvalid(input_3_axis_tvalid),
.input_3_axis_tready(input_3_axis_tready), .input_3_axis_tready(input_3_axis_tready),
.input_3_axis_tlast(input_3_axis_tlast), .input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tid(input_3_axis_tid),
.input_3_axis_tdest(input_3_axis_tdest),
.input_3_axis_tuser(input_3_axis_tuser), .input_3_axis_tuser(input_3_axis_tuser),
// AXI output // AXI output
.output_axis_tdata(output_axis_tdata), .output_axis_tdata(output_axis_tdata),
@ -157,6 +200,8 @@ UUT (
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser) .output_axis_tuser(output_axis_tuser)
); );

177
lib/axis/tb/test_axis_async_fifo.py
View File

@ -45,6 +45,15 @@ def bench():
# Parameters # Parameters
ADDR_WIDTH = 2 ADDR_WIDTH = 2
DATA_WIDTH = 8 DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
LAST_ENABLE = 1
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs # Inputs
async_rst = Signal(bool(0)) async_rst = Signal(bool(0))
@ -53,17 +62,23 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0)) input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0)) input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0)) input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0)) output_axis_tready = Signal(bool(0))
# Outputs # Outputs
input_axis_tready = Signal(bool(0)) input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0)) output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0)) output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0)) output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks # sources and sinks
source_pause = Signal(bool(0)) source_pause = Signal(bool(0))
@ -75,9 +90,12 @@ def bench():
input_clk, input_clk,
async_rst, async_rst,
tdata=input_axis_tdata, tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid, tvalid=input_axis_tvalid,
tready=input_axis_tready, tready=input_axis_tready,
tlast=input_axis_tlast, tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser, tuser=input_axis_tuser,
pause=source_pause, pause=source_pause,
name='source' name='source'
@ -89,9 +107,12 @@ def bench():
output_clk, output_clk,
async_rst, async_rst,
tdata=output_axis_tdata, tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid, tvalid=output_axis_tvalid,
tready=output_axis_tready, tready=output_axis_tready,
tlast=output_axis_tlast, tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser, tuser=output_axis_tuser,
pause=sink_pause, pause=sink_pause,
name='sink' name='sink'
@ -109,15 +130,21 @@ def bench():
current_test=current_test, current_test=current_test,
input_axis_tdata=input_axis_tdata, input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid, input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready, input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast, input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser, input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata, output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid, output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready, output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast, output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser output_axis_tuser=output_axis_tuser
) )
@ -148,10 +175,15 @@ def bench():
print("test 1: test packet") print("test 1: test packet")
current_test.next = 1 current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
source.send(test_frame) source.send(test_frame)
yield input_clk.posedge yield input_clk.posedge
@ -169,10 +201,15 @@ def bench():
print("test 2: longer packet") print("test 2: longer packet")
current_test.next = 2 current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(256))) b'\x80\x00' +
bytearray(range(256)),
id=2,
dest=1
)
source.send(test_frame) source.send(test_frame)
yield input_clk.posedge yield input_clk.posedge
@ -188,10 +225,15 @@ def bench():
print("test 3: test packet with pauses") print("test 3: test packet with pauses")
current_test.next = 3 current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=1
)
source.send(test_frame) source.send(test_frame)
yield input_clk.posedge yield input_clk.posedge
@ -223,14 +265,26 @@ def bench():
print("test 4: back-to-back packets") print("test 4: back-to-back packets")
current_test.next = 4 current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=4,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2
)
test_frame1.id = 4
test_frame1.dest = 1
test_frame2.id = 4
test_frame2.dest = 2
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield input_clk.posedge yield input_clk.posedge
@ -255,14 +309,23 @@ def bench():
print("test 5: alternate pause source") print("test 5: alternate pause source")
current_test.next = 5 current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=5,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2
)
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield input_clk.posedge yield input_clk.posedge
@ -292,14 +355,23 @@ def bench():
print("test 6: alternate pause sink") print("test 6: alternate pause sink")
current_test.next = 6 current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=6,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield input_clk.posedge yield input_clk.posedge
@ -329,11 +401,16 @@ def bench():
print("test 7: tuser assert") print("test 7: tuser assert")
current_test.next = 7 current_test.next = 7
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame.user = 1 b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1,
last_cycle_user=1
)
source.send(test_frame) source.send(test_frame)
yield input_clk.posedge yield input_clk.posedge
@ -344,7 +421,7 @@ def bench():
rx_frame = sink.recv() rx_frame = sink.recv()
assert rx_frame == test_frame assert rx_frame == test_frame
assert rx_frame.user[-1] assert rx_frame.last_cycle_user
yield delay(100) yield delay(100)
@ -352,7 +429,11 @@ def bench():
print("test 8: initial sink pause") print("test 8: initial sink pause")
current_test.next = 8 current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03') test_frame = axis_ep.AXIStreamFrame(
b'\x01\x02\x03',
id=8,
dest=1
)
sink_pause.next = 1 sink_pause.next = 1
source.send(test_frame) source.send(test_frame)
@ -376,7 +457,11 @@ def bench():
print("test 9: initial sink pause, assert reset") print("test 9: initial sink pause, assert reset")
current_test.next = 9 current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03') test_frame = axis_ep.AXIStreamFrame(
b'\x01\x02\x03',
id=9,
dest=1
)
sink_pause.next = 1 sink_pause.next = 1
source.send(test_frame) source.send(test_frame)

42
lib/axis/tb/test_axis_async_fifo.v
View File

@ -34,6 +34,15 @@ module test_axis_async_fifo;
// Parameters // Parameters
parameter ADDR_WIDTH = 2; parameter ADDR_WIDTH = 2;
parameter DATA_WIDTH = 8; parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs // Inputs
reg async_rst = 0; reg async_rst = 0;
@ -42,17 +51,23 @@ reg output_clk = 0;
reg [7:0] current_test = 0; reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0; reg input_axis_tvalid = 0;
reg input_axis_tlast = 0; reg input_axis_tlast = 0;
reg input_axis_tuser = 0; reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_axis_tready = 0; reg output_axis_tready = 0;
// Outputs // Outputs
wire input_axis_tready; wire input_axis_tready;
wire [DATA_WIDTH-1:0] output_axis_tdata; wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid; wire output_axis_tvalid;
wire output_axis_tlast; wire output_axis_tlast;
wire output_axis_tuser; wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
initial begin initial begin
// myhdl integration // myhdl integration
@ -62,16 +77,22 @@ initial begin
output_clk, output_clk,
current_test, current_test,
input_axis_tdata, input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid, input_axis_tvalid,
input_axis_tlast, input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser, input_axis_tuser,
output_axis_tready output_axis_tready
); );
$to_myhdl( $to_myhdl(
input_axis_tready, input_axis_tready,
output_axis_tdata, output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid, output_axis_tvalid,
output_axis_tlast, output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser output_axis_tuser
); );
@ -82,7 +103,16 @@ end
axis_async_fifo #( axis_async_fifo #(
.ADDR_WIDTH(ADDR_WIDTH), .ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH) .DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) )
UUT ( UUT (
// Common reset // Common reset
@ -90,16 +120,22 @@ UUT (
// AXI input // AXI input
.input_clk(input_clk), .input_clk(input_clk),
.input_axis_tdata(input_axis_tdata), .input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid), .input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready), .input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast), .input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser), .input_axis_tuser(input_axis_tuser),
// AXI output // AXI output
.output_clk(output_clk), .output_clk(output_clk),
.output_axis_tdata(output_axis_tdata), .output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser) .output_axis_tuser(output_axis_tuser)
); );

178
lib/axis/tb/test_axis_async_fifo_64.py
View File

@ -28,8 +28,8 @@ import os
import axis_ep import axis_ep
module = 'axis_async_fifo_64' module = 'axis_async_fifo'
testbench = 'test_%s' % module testbench = 'test_%s_64' % module
srcs = [] srcs = []
@ -45,7 +45,15 @@ def bench():
# Parameters # Parameters
ADDR_WIDTH = 2 ADDR_WIDTH = 2
DATA_WIDTH = 64 DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8) KEEP_WIDTH = (DATA_WIDTH/8)
LAST_ENABLE = 1
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs # Inputs
async_rst = Signal(bool(0)) async_rst = Signal(bool(0))
@ -54,19 +62,23 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0)) input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0)) input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0)) input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0)) output_axis_tready = Signal(bool(0))
# Outputs # Outputs
input_axis_tready = Signal(bool(0)) input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0)) output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0)) output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0)) output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks # sources and sinks
source_pause = Signal(bool(0)) source_pause = Signal(bool(0))
@ -82,6 +94,8 @@ def bench():
tvalid=input_axis_tvalid, tvalid=input_axis_tvalid,
tready=input_axis_tready, tready=input_axis_tready,
tlast=input_axis_tlast, tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser, tuser=input_axis_tuser,
pause=source_pause, pause=source_pause,
name='source' name='source'
@ -97,6 +111,8 @@ def bench():
tvalid=output_axis_tvalid, tvalid=output_axis_tvalid,
tready=output_axis_tready, tready=output_axis_tready,
tlast=output_axis_tlast, tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser, tuser=output_axis_tuser,
pause=sink_pause, pause=sink_pause,
name='sink' name='sink'
@ -118,6 +134,8 @@ def bench():
input_axis_tvalid=input_axis_tvalid, input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready, input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast, input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser, input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata, output_axis_tdata=output_axis_tdata,
@ -125,6 +143,8 @@ def bench():
output_axis_tvalid=output_axis_tvalid, output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready, output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast, output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser output_axis_tuser=output_axis_tuser
) )
@ -155,10 +175,15 @@ def bench():
print("test 1: test packet") print("test 1: test packet")
current_test.next = 1 current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
source.send(test_frame) source.send(test_frame)
yield input_clk.posedge yield input_clk.posedge
@ -176,10 +201,15 @@ def bench():
print("test 2: longer packet") print("test 2: longer packet")
current_test.next = 2 current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(256))) b'\x80\x00' +
bytearray(range(256)),
id=2,
dest=1
)
source.send(test_frame) source.send(test_frame)
yield input_clk.posedge yield input_clk.posedge
@ -195,10 +225,15 @@ def bench():
print("test 3: test packet with pauses") print("test 3: test packet with pauses")
current_test.next = 3 current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(256))) b'\x80\x00' +
bytearray(range(256)),
id=3,
dest=1
)
source.send(test_frame) source.send(test_frame)
yield input_clk.posedge yield input_clk.posedge
@ -230,14 +265,26 @@ def bench():
print("test 4: back-to-back packets") print("test 4: back-to-back packets")
current_test.next = 4 current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=4,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=1
)
test_frame1.id = 4
test_frame1.dest = 1
test_frame2.id = 4
test_frame2.dest = 2
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield input_clk.posedge yield input_clk.posedge
@ -262,14 +309,23 @@ def bench():
print("test 5: alternate pause source") print("test 5: alternate pause source")
current_test.next = 5 current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=5,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=1
)
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield input_clk.posedge yield input_clk.posedge
@ -299,14 +355,23 @@ def bench():
print("test 6: alternate pause sink") print("test 6: alternate pause sink")
current_test.next = 6 current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=6,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=1
)
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield input_clk.posedge yield input_clk.posedge
@ -336,11 +401,16 @@ def bench():
print("test 7: tuser assert") print("test 7: tuser assert")
current_test.next = 7 current_test.next = 7
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame.user = 1 b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1,
last_cycle_user=1
)
source.send(test_frame) source.send(test_frame)
yield input_clk.posedge yield input_clk.posedge
@ -351,7 +421,7 @@ def bench():
rx_frame = sink.recv() rx_frame = sink.recv()
assert rx_frame == test_frame assert rx_frame == test_frame
assert rx_frame.user[-1] assert rx_frame.last_cycle_user
yield delay(100) yield delay(100)
@ -359,7 +429,11 @@ def bench():
print("test 8: initial sink pause") print("test 8: initial sink pause")
current_test.next = 8 current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24))) test_frame = axis_ep.AXIStreamFrame(
bytearray(range(24)),
id=8,
dest=1
)
sink_pause.next = 1 sink_pause.next = 1
source.send(test_frame) source.send(test_frame)
@ -383,7 +457,11 @@ def bench():
print("test 9: initial sink pause, assert reset") print("test 9: initial sink pause, assert reset")
current_test.next = 9 current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24))) test_frame = axis_ep.AXIStreamFrame(
bytearray(range(24)),
id=9,
dest=1
)
sink_pause.next = 1 sink_pause.next = 1
source.send(test_frame) source.send(test_frame)

38
lib/axis/tb/test_axis_async_fifo_64.v
View File

@ -27,14 +27,22 @@ THE SOFTWARE.
`timescale 1ns / 1ps `timescale 1ns / 1ps
/* /*
* Testbench for axis_async_fifo_64 * Testbench for axis_async_fifo
*/ */
module test_axis_async_fifo_64; module test_axis_async_fifo_64;
// Parameters // Parameters
parameter ADDR_WIDTH = 2; parameter ADDR_WIDTH = 2;
parameter DATA_WIDTH = 64; parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8); parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs // Inputs
reg async_rst = 0; reg async_rst = 0;
@ -46,7 +54,9 @@ reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0; reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0; reg input_axis_tvalid = 0;
reg input_axis_tlast = 0; reg input_axis_tlast = 0;
reg input_axis_tuser = 0; reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_axis_tready = 0; reg output_axis_tready = 0;
// Outputs // Outputs
@ -55,7 +65,9 @@ wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep; wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid; wire output_axis_tvalid;
wire output_axis_tlast; wire output_axis_tlast;
wire output_axis_tuser; wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
initial begin initial begin
// myhdl integration // myhdl integration
@ -68,6 +80,8 @@ initial begin
input_axis_tkeep, input_axis_tkeep,
input_axis_tvalid, input_axis_tvalid,
input_axis_tlast, input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser, input_axis_tuser,
output_axis_tready output_axis_tready
); );
@ -77,6 +91,8 @@ initial begin
output_axis_tkeep, output_axis_tkeep,
output_axis_tvalid, output_axis_tvalid,
output_axis_tlast, output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser output_axis_tuser
); );
@ -85,10 +101,18 @@ initial begin
$dumpvars(0, test_axis_async_fifo_64); $dumpvars(0, test_axis_async_fifo_64);
end end
axis_async_fifo_64 #( axis_async_fifo #(
.ADDR_WIDTH(ADDR_WIDTH), .ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH) .KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) )
UUT ( UUT (
// Common reset // Common reset
@ -100,6 +124,8 @@ UUT (
.input_axis_tvalid(input_axis_tvalid), .input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready), .input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast), .input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser), .input_axis_tuser(input_axis_tuser),
// AXI output // AXI output
.output_clk(output_clk), .output_clk(output_clk),
@ -108,6 +134,8 @@ UUT (
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser) .output_axis_tuser(output_axis_tuser)
); );

180
lib/axis/tb/test_axis_async_frame_fifo.py
View File

@ -45,6 +45,17 @@ def bench():
# Parameters # Parameters
ADDR_WIDTH = 9 ADDR_WIDTH = 9
DATA_WIDTH = 8 DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
USER_BAD_FRAME_VALUE = 1
USER_BAD_FRAME_MASK = 1
DROP_BAD_FRAME = 1
DROP_WHEN_FULL = 0 DROP_WHEN_FULL = 0
# Inputs # Inputs
@ -54,16 +65,23 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0)) input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0)) input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0)) input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0)) output_axis_tready = Signal(bool(0))
# Outputs # Outputs
input_axis_tready = Signal(bool(0)) input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0)) output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0)) output_axis_tlast = Signal(bool(0))
output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_status_overflow = Signal(bool(0)) input_status_overflow = Signal(bool(0))
input_status_bad_frame = Signal(bool(0)) input_status_bad_frame = Signal(bool(0))
input_status_good_frame = Signal(bool(0)) input_status_good_frame = Signal(bool(0))
@ -81,9 +99,12 @@ def bench():
input_clk, input_clk,
async_rst, async_rst,
tdata=input_axis_tdata, tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid, tvalid=input_axis_tvalid,
tready=input_axis_tready, tready=input_axis_tready,
tlast=input_axis_tlast, tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser, tuser=input_axis_tuser,
pause=source_pause, pause=source_pause,
name='source' name='source'
@ -95,9 +116,13 @@ def bench():
output_clk, output_clk,
async_rst, async_rst,
tdata=output_axis_tdata, tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid, tvalid=output_axis_tvalid,
tready=output_axis_tready, tready=output_axis_tready,
tlast=output_axis_tlast, tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser,
pause=sink_pause, pause=sink_pause,
name='sink' name='sink'
) )
@ -114,15 +139,22 @@ def bench():
current_test=current_test, current_test=current_test,
input_axis_tdata=input_axis_tdata, input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid, input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready, input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast, input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser, input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata, output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid, output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready, output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast, output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser,
input_status_overflow=input_status_overflow, input_status_overflow=input_status_overflow,
input_status_bad_frame=input_status_bad_frame, input_status_bad_frame=input_status_bad_frame,
@ -184,10 +216,14 @@ def bench():
print("test 1: test packet") print("test 1: test packet")
current_test.next = 1 current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
input_status_overflow_asserted.next = 0 input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0 input_status_bad_frame_asserted.next = 0
@ -220,10 +256,14 @@ def bench():
print("test 2: longer packet") print("test 2: longer packet")
current_test.next = 2 current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(256))) b'\x80\x00' +
bytearray(range(256)),
id=2,
dest=1
)
input_status_overflow_asserted.next = 0 input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0 input_status_bad_frame_asserted.next = 0
@ -254,10 +294,14 @@ def bench():
print("test 3: test packet with pauses") print("test 3: test packet with pauses")
current_test.next = 3 current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=1
)
input_status_overflow_asserted.next = 0 input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0 input_status_bad_frame_asserted.next = 0
@ -304,14 +348,22 @@ def bench():
print("test 4: back-to-back packets") print("test 4: back-to-back packets")
current_test.next = 4 current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=4,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2
)
input_status_overflow_asserted.next = 0 input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0 input_status_bad_frame_asserted.next = 0
@ -351,14 +403,22 @@ def bench():
print("test 5: alternate pause source") print("test 5: alternate pause source")
current_test.next = 5 current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=5,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2
)
input_status_overflow_asserted.next = 0 input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0 input_status_bad_frame_asserted.next = 0
@ -407,14 +467,22 @@ def bench():
print("test 6: alternate pause sink") print("test 6: alternate pause sink")
current_test.next = 6 current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=1,
b'\x80\x00' + dest=6
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
input_status_overflow_asserted.next = 0 input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0 input_status_bad_frame_asserted.next = 0
@ -459,11 +527,15 @@ def bench():
print("test 7: tuser assert") print("test 7: tuser assert")
current_test.next = 7 current_test.next = 7
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame.user = 1 b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1,
last_cycle_user=1
)
input_status_overflow_asserted.next = 0 input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0 input_status_bad_frame_asserted.next = 0
@ -492,10 +564,14 @@ def bench():
print("test 8: single packet overflow") print("test 8: single packet overflow")
current_test.next = 8 current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(256))*2) b'\x80\x00' +
bytearray(range(256))*2,
id=8,
dest=1
)
input_status_overflow_asserted.next = 0 input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0 input_status_bad_frame_asserted.next = 0
@ -524,7 +600,11 @@ def bench():
print("test 9: initial sink pause") print("test 9: initial sink pause")
current_test.next = 9 current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03') test_frame = axis_ep.AXIStreamFrame(
b'\x01\x02\x03',
id=9,
dest=1
)
sink_pause.next = 1 sink_pause.next = 1
source.send(test_frame) source.send(test_frame)
@ -548,7 +628,11 @@ def bench():
print("test 10: initial sink pause, assert reset") print("test 10: initial sink pause, assert reset")
current_test.next = 10 current_test.next = 10
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03') test_frame = axis_ep.AXIStreamFrame(
b'\x01\x02\x03',
id=10,
dest=1
)
sink_pause.next = 1 sink_pause.next = 1
source.send(test_frame) source.send(test_frame)

45
lib/axis/tb/test_axis_async_frame_fifo.v
View File

@ -34,6 +34,17 @@ module test_axis_async_frame_fifo;
// Parameters // Parameters
parameter ADDR_WIDTH = 9; parameter ADDR_WIDTH = 9;
parameter DATA_WIDTH = 8; parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 1;
parameter DROP_WHEN_FULL = 0; parameter DROP_WHEN_FULL = 0;
// Inputs // Inputs
@ -43,16 +54,23 @@ reg output_clk = 0;
reg [7:0] current_test = 0; reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0; reg input_axis_tvalid = 0;
reg input_axis_tlast = 0; reg input_axis_tlast = 0;
reg input_axis_tuser = 0; reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_axis_tready = 0; reg output_axis_tready = 0;
// Outputs // Outputs
wire input_axis_tready; wire input_axis_tready;
wire [DATA_WIDTH-1:0] output_axis_tdata; wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid; wire output_axis_tvalid;
wire output_axis_tlast; wire output_axis_tlast;
wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
wire input_status_overflow; wire input_status_overflow;
wire input_status_bad_frame; wire input_status_bad_frame;
wire input_status_good_frame; wire input_status_good_frame;
@ -68,16 +86,23 @@ initial begin
output_clk, output_clk,
current_test, current_test,
input_axis_tdata, input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid, input_axis_tvalid,
input_axis_tlast, input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser, input_axis_tuser,
output_axis_tready output_axis_tready
); );
$to_myhdl( $to_myhdl(
input_axis_tready, input_axis_tready,
output_axis_tdata, output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid, output_axis_tvalid,
output_axis_tlast, output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser,
input_status_overflow, input_status_overflow,
input_status_bad_frame, input_status_bad_frame,
input_status_good_frame, input_status_good_frame,
@ -94,6 +119,17 @@ end
axis_async_frame_fifo #( axis_async_frame_fifo #(
.ADDR_WIDTH(ADDR_WIDTH), .ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL) .DROP_WHEN_FULL(DROP_WHEN_FULL)
) )
UUT ( UUT (
@ -102,16 +138,23 @@ UUT (
// AXI input // AXI input
.input_clk(input_clk), .input_clk(input_clk),
.input_axis_tdata(input_axis_tdata), .input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid), .input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready), .input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast), .input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser), .input_axis_tuser(input_axis_tuser),
// AXI output // AXI output
.output_clk(output_clk), .output_clk(output_clk),
.output_axis_tdata(output_axis_tdata), .output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser),
// Status // Status
.input_status_overflow(input_status_overflow), .input_status_overflow(input_status_overflow),
.input_status_bad_frame(input_status_bad_frame), .input_status_bad_frame(input_status_bad_frame),

181
lib/axis/tb/test_axis_async_frame_fifo_64.py
View File

@ -28,8 +28,8 @@ import os
import axis_ep import axis_ep
module = 'axis_async_frame_fifo_64' module = 'axis_async_frame_fifo'
testbench = 'test_%s' % module testbench = 'test_%s_64' % module
srcs = [] srcs = []
@ -45,7 +45,17 @@ def bench():
# Parameters # Parameters
ADDR_WIDTH = 6 ADDR_WIDTH = 6
DATA_WIDTH = 64 DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8) KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
USER_BAD_FRAME_VALUE = 1
USER_BAD_FRAME_MASK = 1
DROP_BAD_FRAME = 1
DROP_WHEN_FULL = 0 DROP_WHEN_FULL = 0
# Inputs # Inputs
@ -55,18 +65,23 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0)) input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0)) input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0)) input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0)) output_axis_tready = Signal(bool(0))
# Outputs # Outputs
input_axis_tready = Signal(bool(0)) input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0)) output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0)) output_axis_tlast = Signal(bool(0))
output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_status_overflow = Signal(bool(0)) input_status_overflow = Signal(bool(0))
input_status_bad_frame = Signal(bool(0)) input_status_bad_frame = Signal(bool(0))
input_status_good_frame = Signal(bool(0)) input_status_good_frame = Signal(bool(0))
@ -88,6 +103,8 @@ def bench():
tvalid=input_axis_tvalid, tvalid=input_axis_tvalid,
tready=input_axis_tready, tready=input_axis_tready,
tlast=input_axis_tlast, tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser, tuser=input_axis_tuser,
pause=source_pause, pause=source_pause,
name='source' name='source'
@ -103,6 +120,9 @@ def bench():
tvalid=output_axis_tvalid, tvalid=output_axis_tvalid,
tready=output_axis_tready, tready=output_axis_tready,
tlast=output_axis_tlast, tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser,
pause=sink_pause, pause=sink_pause,
name='sink' name='sink'
) )
@ -123,6 +143,8 @@ def bench():
input_axis_tvalid=input_axis_tvalid, input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready, input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast, input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser, input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata, output_axis_tdata=output_axis_tdata,
@ -130,6 +152,9 @@ def bench():
output_axis_tvalid=output_axis_tvalid, output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready, output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast, output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser,
input_status_overflow=input_status_overflow, input_status_overflow=input_status_overflow,
input_status_bad_frame=input_status_bad_frame, input_status_bad_frame=input_status_bad_frame,
@ -191,10 +216,14 @@ def bench():
print("test 1: test packet") print("test 1: test packet")
current_test.next = 1 current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
input_status_overflow_asserted.next = 0 input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0 input_status_bad_frame_asserted.next = 0
@ -227,10 +256,14 @@ def bench():
print("test 2: longer packet") print("test 2: longer packet")
current_test.next = 2 current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(256))) b'\x80\x00' +
bytearray(range(256)),
id=2,
dest=1
)
input_status_overflow_asserted.next = 0 input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0 input_status_bad_frame_asserted.next = 0
@ -261,10 +294,14 @@ def bench():
print("test 3: test packet with pauses") print("test 3: test packet with pauses")
current_test.next = 3 current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(256))) b'\x80\x00' +
bytearray(range(256)),
id=3,
dest=1
)
input_status_overflow_asserted.next = 0 input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0 input_status_bad_frame_asserted.next = 0
@ -311,14 +348,22 @@ def bench():
print("test 4: back-to-back packets") print("test 4: back-to-back packets")
current_test.next = 4 current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=4,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2
)
input_status_overflow_asserted.next = 0 input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0 input_status_bad_frame_asserted.next = 0
@ -358,14 +403,22 @@ def bench():
print("test 5: alternate pause source") print("test 5: alternate pause source")
current_test.next = 5 current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=5,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2
)
input_status_overflow_asserted.next = 0 input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0 input_status_bad_frame_asserted.next = 0
@ -414,14 +467,22 @@ def bench():
print("test 6: alternate pause sink") print("test 6: alternate pause sink")
current_test.next = 6 current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=1,
b'\x80\x00' + dest=6
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
input_status_overflow_asserted.next = 0 input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0 input_status_bad_frame_asserted.next = 0
@ -466,11 +527,15 @@ def bench():
print("test 7: tuser assert") print("test 7: tuser assert")
current_test.next = 7 current_test.next = 7
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame.user = 1 b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1,
last_cycle_user=1
)
input_status_overflow_asserted.next = 0 input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0 input_status_bad_frame_asserted.next = 0
@ -499,10 +564,14 @@ def bench():
print("test 8: single packet overflow") print("test 8: single packet overflow")
current_test.next = 8 current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(256))*2) b'\x80\x00' +
bytearray(range(256))*2,
id=8,
dest=1
)
input_status_overflow_asserted.next = 0 input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0 input_status_bad_frame_asserted.next = 0
@ -531,7 +600,11 @@ def bench():
print("test 9: initial sink pause") print("test 9: initial sink pause")
current_test.next = 9 current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24))) test_frame = axis_ep.AXIStreamFrame(
bytearray(range(24)),
id=9,
dest=1
)
sink_pause.next = 1 sink_pause.next = 1
source.send(test_frame) source.send(test_frame)
@ -555,7 +628,11 @@ def bench():
print("test 10: initial sink pause, assert reset") print("test 10: initial sink pause, assert reset")
current_test.next = 10 current_test.next = 10
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24))) test_frame = axis_ep.AXIStreamFrame(
bytearray(range(24)),
id=10,
dest=1
)
sink_pause.next = 1 sink_pause.next = 1
source.send(test_frame) source.send(test_frame)

41
lib/axis/tb/test_axis_async_frame_fifo_64.v
View File

@ -27,14 +27,24 @@ THE SOFTWARE.
`timescale 1ns / 1ps `timescale 1ns / 1ps
/* /*
* Testbench for axis_async_frame_fifo_64 * Testbench for axis_async_frame_fifo
*/ */
module test_axis_async_frame_fifo_64; module test_axis_async_frame_fifo_64;
// Parameters // Parameters
parameter ADDR_WIDTH = 6; parameter ADDR_WIDTH = 6;
parameter DATA_WIDTH = 64; parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8); parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 1;
parameter DROP_WHEN_FULL = 0; parameter DROP_WHEN_FULL = 0;
// Inputs // Inputs
@ -47,7 +57,9 @@ reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0; reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0; reg input_axis_tvalid = 0;
reg input_axis_tlast = 0; reg input_axis_tlast = 0;
reg input_axis_tuser = 0; reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_axis_tready = 0; reg output_axis_tready = 0;
// Outputs // Outputs
@ -56,6 +68,9 @@ wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep; wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid; wire output_axis_tvalid;
wire output_axis_tlast; wire output_axis_tlast;
wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
wire input_status_overflow; wire input_status_overflow;
wire input_status_bad_frame; wire input_status_bad_frame;
wire input_status_good_frame; wire input_status_good_frame;
@ -74,6 +89,8 @@ initial begin
input_axis_tkeep, input_axis_tkeep,
input_axis_tvalid, input_axis_tvalid,
input_axis_tlast, input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser, input_axis_tuser,
output_axis_tready output_axis_tready
); );
@ -83,6 +100,9 @@ initial begin
output_axis_tkeep, output_axis_tkeep,
output_axis_tvalid, output_axis_tvalid,
output_axis_tlast, output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser,
input_status_overflow, input_status_overflow,
input_status_bad_frame, input_status_bad_frame,
input_status_good_frame, input_status_good_frame,
@ -96,10 +116,20 @@ initial begin
$dumpvars(0, test_axis_async_frame_fifo_64); $dumpvars(0, test_axis_async_frame_fifo_64);
end end
axis_async_frame_fifo_64 #( axis_async_frame_fifo #(
.ADDR_WIDTH(ADDR_WIDTH), .ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH), .KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL) .DROP_WHEN_FULL(DROP_WHEN_FULL)
) )
UUT ( UUT (
@ -112,6 +142,8 @@ UUT (
.input_axis_tvalid(input_axis_tvalid), .input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready), .input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast), .input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser), .input_axis_tuser(input_axis_tuser),
// AXI output // AXI output
.output_clk(output_clk), .output_clk(output_clk),
@ -120,6 +152,9 @@ UUT (
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser),
// Status // Status
.input_status_overflow(input_status_overflow), .input_status_overflow(input_status_overflow),
.input_status_bad_frame(input_status_bad_frame), .input_status_bad_frame(input_status_bad_frame),

28
lib/axis/tb/test_axis_cobs_decode.py
View File

@ -264,7 +264,7 @@ def bench():
assert cobs_decode(enc) == block assert cobs_decode(enc) == block
assert rx_frame.data == block assert rx_frame.data == block
assert not rx_frame.user[-1] assert not rx_frame.last_cycle_user
assert sink.empty() assert sink.empty()
@ -292,7 +292,7 @@ def bench():
assert cobs_decode(enc) == block assert cobs_decode(enc) == block
assert rx_frame.data == block assert rx_frame.data == block
assert not rx_frame.user[-1] assert not rx_frame.last_cycle_user
assert sink.empty() assert sink.empty()
@ -320,13 +320,13 @@ def bench():
assert cobs_decode(enc) == block assert cobs_decode(enc) == block
assert rx_frame.data == block assert rx_frame.data == block
assert not rx_frame.user[-1] assert not rx_frame.last_cycle_user
rx_frame = sink.recv() rx_frame = sink.recv()
assert cobs_decode(enc) == block assert cobs_decode(enc) == block
assert rx_frame.data == block assert rx_frame.data == block
assert not rx_frame.user[-1] assert not rx_frame.last_cycle_user
assert sink.empty() assert sink.empty()
@ -352,13 +352,13 @@ def bench():
assert cobs_decode(enc) == block assert cobs_decode(enc) == block
assert rx_frame.data == block assert rx_frame.data == block
assert not rx_frame.user[-1] assert not rx_frame.last_cycle_user
rx_frame = sink.recv() rx_frame = sink.recv()
assert cobs_decode(enc) == block assert cobs_decode(enc) == block
assert rx_frame.data == block assert rx_frame.data == block
assert not rx_frame.user[-1] assert not rx_frame.last_cycle_user
assert sink.empty() assert sink.empty()
@ -372,7 +372,7 @@ def bench():
test_frame2 = axis_ep.AXIStreamFrame(enc+b'\x02') test_frame2 = axis_ep.AXIStreamFrame(enc+b'\x02')
test_frame3 = axis_ep.AXIStreamFrame(enc) test_frame3 = axis_ep.AXIStreamFrame(enc)
test_frame1.user = 1 test_frame1.last_cycle_user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink: for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1) source.send(test_frame1)
@ -388,17 +388,17 @@ def bench():
rx_frame = sink.recv() rx_frame = sink.recv()
assert rx_frame.user[-1] assert rx_frame.last_cycle_user
rx_frame = sink.recv() rx_frame = sink.recv()
assert rx_frame.user[-1] assert rx_frame.last_cycle_user
rx_frame = sink.recv() rx_frame = sink.recv()
assert cobs_decode(enc) == block assert cobs_decode(enc) == block
assert rx_frame.data == block assert rx_frame.data == block
assert not rx_frame.user[-1] assert not rx_frame.last_cycle_user
assert sink.empty() assert sink.empty()
@ -412,7 +412,7 @@ def bench():
test_frame2 = axis_ep.AXIStreamFrame(enc+b'\x02\x00') test_frame2 = axis_ep.AXIStreamFrame(enc+b'\x02\x00')
test_frame3 = axis_ep.AXIStreamFrame(enc+b'\x00') test_frame3 = axis_ep.AXIStreamFrame(enc+b'\x00')
test_frame1.user = 1 test_frame1.last_cycle_user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink: for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1) source.send(test_frame1)
@ -428,17 +428,17 @@ def bench():
rx_frame = sink.recv() rx_frame = sink.recv()
assert rx_frame.user[-1] assert rx_frame.last_cycle_user
rx_frame = sink.recv() rx_frame = sink.recv()
assert rx_frame.user[-1] assert rx_frame.last_cycle_user
rx_frame = sink.recv() rx_frame = sink.recv()
assert cobs_decode(enc) == block assert cobs_decode(enc) == block
assert rx_frame.data == block assert rx_frame.data == block
assert not rx_frame.user[-1] assert not rx_frame.last_cycle_user
assert sink.empty() assert sink.empty()

12
lib/axis/tb/test_axis_cobs_encode.py
View File

@ -265,7 +265,7 @@ def bench():
assert cobs_decode(enc) == block assert cobs_decode(enc) == block
assert rx_frame.data == enc assert rx_frame.data == enc
assert cobs_decode(rx_frame.data) == block assert cobs_decode(rx_frame.data) == block
assert not rx_frame.user[-1] assert not rx_frame.last_cycle_user
assert sink.empty() assert sink.empty()
@ -294,14 +294,14 @@ def bench():
assert cobs_decode(enc) == block assert cobs_decode(enc) == block
assert rx_frame.data == enc assert rx_frame.data == enc
assert cobs_decode(rx_frame.data) == block assert cobs_decode(rx_frame.data) == block
assert not rx_frame.user[-1] assert not rx_frame.last_cycle_user
rx_frame = sink.recv() rx_frame = sink.recv()
assert cobs_decode(enc) == block assert cobs_decode(enc) == block
assert rx_frame.data == enc assert rx_frame.data == enc
assert cobs_decode(rx_frame.data) == block assert cobs_decode(rx_frame.data) == block
assert not rx_frame.user[-1] assert not rx_frame.last_cycle_user
assert sink.empty() assert sink.empty()
@ -314,7 +314,7 @@ def bench():
test_frame1 = axis_ep.AXIStreamFrame(block) test_frame1 = axis_ep.AXIStreamFrame(block)
test_frame2 = axis_ep.AXIStreamFrame(block) test_frame2 = axis_ep.AXIStreamFrame(block)
test_frame1.user = 1 test_frame1.last_cycle_user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink: for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1) source.send(test_frame1)
@ -330,14 +330,14 @@ def bench():
rx_frame = sink.recv() rx_frame = sink.recv()
assert cobs_decode(rx_frame.data) == None assert cobs_decode(rx_frame.data) == None
assert rx_frame.user[-1] assert rx_frame.last_cycle_user
rx_frame = sink.recv() rx_frame = sink.recv()
assert cobs_decode(enc) == block assert cobs_decode(enc) == block
assert rx_frame.data == enc assert rx_frame.data == enc
assert cobs_decode(rx_frame.data) == block assert cobs_decode(rx_frame.data) == block
assert not rx_frame.user[-1] assert not rx_frame.last_cycle_user
assert sink.empty() assert sink.empty()

12
lib/axis/tb/test_axis_cobs_encode_zero_frame.py
View File

@ -266,7 +266,7 @@ def bench():
assert cobs_decode(enc) == block assert cobs_decode(enc) == block
assert rx_frame.data == enc+b'\x00' assert rx_frame.data == enc+b'\x00'
assert cobs_decode(rx_frame.data[:-1]) == block assert cobs_decode(rx_frame.data[:-1]) == block
assert not rx_frame.user[-1] assert not rx_frame.last_cycle_user
assert sink.empty() assert sink.empty()
@ -295,14 +295,14 @@ def bench():
assert cobs_decode(enc) == block assert cobs_decode(enc) == block
assert rx_frame.data == enc+b'\x00' assert rx_frame.data == enc+b'\x00'
assert cobs_decode(rx_frame.data[:-1]) == block assert cobs_decode(rx_frame.data[:-1]) == block
assert not rx_frame.user[-1] assert not rx_frame.last_cycle_user
rx_frame = sink.recv() rx_frame = sink.recv()
assert cobs_decode(enc) == block assert cobs_decode(enc) == block
assert rx_frame.data == enc+b'\x00' assert rx_frame.data == enc+b'\x00'
assert cobs_decode(rx_frame.data[:-1]) == block assert cobs_decode(rx_frame.data[:-1]) == block
assert not rx_frame.user[-1] assert not rx_frame.last_cycle_user
assert sink.empty() assert sink.empty()
@ -315,7 +315,7 @@ def bench():
test_frame1 = axis_ep.AXIStreamFrame(block) test_frame1 = axis_ep.AXIStreamFrame(block)
test_frame2 = axis_ep.AXIStreamFrame(block) test_frame2 = axis_ep.AXIStreamFrame(block)
test_frame1.user = 1 test_frame1.last_cycle_user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink: for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1) source.send(test_frame1)
@ -331,14 +331,14 @@ def bench():
rx_frame = sink.recv() rx_frame = sink.recv()
assert cobs_decode(rx_frame.data[:-1]) == None assert cobs_decode(rx_frame.data[:-1]) == None
assert rx_frame.user[-1] assert rx_frame.last_cycle_user
rx_frame = sink.recv() rx_frame = sink.recv()
assert cobs_decode(enc) == block assert cobs_decode(enc) == block
assert rx_frame.data == enc+b'\x00' assert rx_frame.data == enc+b'\x00'
assert cobs_decode(rx_frame.data[:-1]) == block assert cobs_decode(rx_frame.data[:-1]) == block
assert not rx_frame.user[-1] assert not rx_frame.last_cycle_user
assert sink.empty() assert sink.empty()

115
lib/axis/tb/test_axis_crosspoint_4x4.py
View File

@ -44,6 +44,15 @@ def bench():
# Parameters # Parameters
DATA_WIDTH = 8 DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
LAST_ENABLE = 1
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))
@ -51,21 +60,33 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_0_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_0_axis_tvalid = Signal(bool(0)) input_0_axis_tvalid = Signal(bool(0))
input_0_axis_tlast = Signal(bool(0)) input_0_axis_tlast = Signal(bool(0))
input_0_axis_tuser = Signal(bool(0)) input_0_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_0_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_0_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_1_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_1_axis_tvalid = Signal(bool(0)) input_1_axis_tvalid = Signal(bool(0))
input_1_axis_tlast = Signal(bool(0)) input_1_axis_tlast = Signal(bool(0))
input_1_axis_tuser = Signal(bool(0)) input_1_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_1_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_1_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_2_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_2_axis_tvalid = Signal(bool(0)) input_2_axis_tvalid = Signal(bool(0))
input_2_axis_tlast = Signal(bool(0)) input_2_axis_tlast = Signal(bool(0))
input_2_axis_tuser = Signal(bool(0)) input_2_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_2_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_2_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_3_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_3_axis_tvalid = Signal(bool(0)) input_3_axis_tvalid = Signal(bool(0))
input_3_axis_tlast = Signal(bool(0)) input_3_axis_tlast = Signal(bool(0))
input_3_axis_tuser = Signal(bool(0)) input_3_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_3_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_3_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_0_select = Signal(intbv(0)[2:]) output_0_select = Signal(intbv(0)[2:])
output_1_select = Signal(intbv(0)[2:]) output_1_select = Signal(intbv(0)[2:])
@ -74,21 +95,33 @@ def bench():
# Outputs # Outputs
output_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_0_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_0_axis_tvalid = Signal(bool(0)) output_0_axis_tvalid = Signal(bool(0))
output_0_axis_tlast = Signal(bool(0)) output_0_axis_tlast = Signal(bool(0))
output_0_axis_tuser = Signal(bool(0)) output_0_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_0_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_0_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_1_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_1_axis_tvalid = Signal(bool(0)) output_1_axis_tvalid = Signal(bool(0))
output_1_axis_tlast = Signal(bool(0)) output_1_axis_tlast = Signal(bool(0))
output_1_axis_tuser = Signal(bool(0)) output_1_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_1_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_1_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_2_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_2_axis_tvalid = Signal(bool(0)) output_2_axis_tvalid = Signal(bool(0))
output_2_axis_tlast = Signal(bool(0)) output_2_axis_tlast = Signal(bool(0))
output_2_axis_tuser = Signal(bool(0)) output_2_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_2_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_2_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_3_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_3_axis_tvalid = Signal(bool(0)) output_3_axis_tvalid = Signal(bool(0))
output_3_axis_tlast = Signal(bool(0)) output_3_axis_tlast = Signal(bool(0))
output_3_axis_tuser = Signal(bool(0)) output_3_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_3_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_3_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks # sources and sinks
source_0_pause = Signal(bool(0)) source_0_pause = Signal(bool(0))
@ -106,8 +139,11 @@ def bench():
clk, clk,
rst, rst,
tdata=input_0_axis_tdata, tdata=input_0_axis_tdata,
tkeep=input_0_axis_tkeep,
tvalid=input_0_axis_tvalid, tvalid=input_0_axis_tvalid,
tlast=input_0_axis_tlast, tlast=input_0_axis_tlast,
tid=input_0_axis_tid,
tdest=input_0_axis_tdest,
tuser=input_0_axis_tuser, tuser=input_0_axis_tuser,
pause=source_0_pause, pause=source_0_pause,
name='source_0' name='source_0'
@ -119,8 +155,11 @@ def bench():
clk, clk,
rst, rst,
tdata=input_1_axis_tdata, tdata=input_1_axis_tdata,
tkeep=input_1_axis_tkeep,
tvalid=input_1_axis_tvalid, tvalid=input_1_axis_tvalid,
tlast=input_1_axis_tlast, tlast=input_1_axis_tlast,
tid=input_1_axis_tid,
tdest=input_1_axis_tdest,
tuser=input_1_axis_tuser, tuser=input_1_axis_tuser,
pause=source_1_pause, pause=source_1_pause,
name='source_1' name='source_1'
@ -132,8 +171,11 @@ def bench():
clk, clk,
rst, rst,
tdata=input_2_axis_tdata, tdata=input_2_axis_tdata,
tkeep=input_2_axis_tkeep,
tvalid=input_2_axis_tvalid, tvalid=input_2_axis_tvalid,
tlast=input_2_axis_tlast, tlast=input_2_axis_tlast,
tid=input_2_axis_tid,
tdest=input_2_axis_tdest,
tuser=input_2_axis_tuser, tuser=input_2_axis_tuser,
pause=source_2_pause, pause=source_2_pause,
name='source_2' name='source_2'
@ -145,8 +187,11 @@ def bench():
clk, clk,
rst, rst,
tdata=input_3_axis_tdata, tdata=input_3_axis_tdata,
tkeep=input_3_axis_tkeep,
tvalid=input_3_axis_tvalid, tvalid=input_3_axis_tvalid,
tlast=input_3_axis_tlast, tlast=input_3_axis_tlast,
tid=input_3_axis_tid,
tdest=input_3_axis_tdest,
tuser=input_3_axis_tuser, tuser=input_3_axis_tuser,
pause=source_3_pause, pause=source_3_pause,
name='source_3' name='source_3'
@ -158,8 +203,11 @@ def bench():
clk, clk,
rst, rst,
tdata=output_0_axis_tdata, tdata=output_0_axis_tdata,
tkeep=output_0_axis_tkeep,
tvalid=output_0_axis_tvalid, tvalid=output_0_axis_tvalid,
tlast=output_0_axis_tlast, tlast=output_0_axis_tlast,
tid=output_0_axis_tid,
tdest=output_0_axis_tdest,
tuser=output_0_axis_tuser, tuser=output_0_axis_tuser,
pause=sink_0_pause, pause=sink_0_pause,
name='sink_0' name='sink_0'
@ -171,8 +219,11 @@ def bench():
clk, clk,
rst, rst,
tdata=output_1_axis_tdata, tdata=output_1_axis_tdata,
tkeep=output_1_axis_tkeep,
tvalid=output_1_axis_tvalid, tvalid=output_1_axis_tvalid,
tlast=output_1_axis_tlast, tlast=output_1_axis_tlast,
tid=output_1_axis_tid,
tdest=output_1_axis_tdest,
tuser=output_1_axis_tuser, tuser=output_1_axis_tuser,
pause=sink_1_pause, pause=sink_1_pause,
name='sink_1' name='sink_1'
@ -184,8 +235,11 @@ def bench():
clk, clk,
rst, rst,
tdata=output_2_axis_tdata, tdata=output_2_axis_tdata,
tkeep=output_2_axis_tkeep,
tvalid=output_2_axis_tvalid, tvalid=output_2_axis_tvalid,
tlast=output_2_axis_tlast, tlast=output_2_axis_tlast,
tid=output_2_axis_tid,
tdest=output_2_axis_tdest,
tuser=output_2_axis_tuser, tuser=output_2_axis_tuser,
pause=sink_2_pause, pause=sink_2_pause,
name='sink_2' name='sink_2'
@ -197,8 +251,11 @@ def bench():
clk, clk,
rst, rst,
tdata=output_3_axis_tdata, tdata=output_3_axis_tdata,
tkeep=output_3_axis_tkeep,
tvalid=output_3_axis_tvalid, tvalid=output_3_axis_tvalid,
tlast=output_3_axis_tlast, tlast=output_3_axis_tlast,
tid=output_3_axis_tid,
tdest=output_3_axis_tdest,
tuser=output_3_axis_tuser, tuser=output_3_axis_tuser,
pause=sink_3_pause, pause=sink_3_pause,
name='sink_3' name='sink_3'
@ -215,37 +272,61 @@ def bench():
current_test=current_test, current_test=current_test,
input_0_axis_tdata=input_0_axis_tdata, input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tkeep=input_0_axis_tkeep,
input_0_axis_tvalid=input_0_axis_tvalid, input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tlast=input_0_axis_tlast, input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tid=input_0_axis_tid,
input_0_axis_tdest=input_0_axis_tdest,
input_0_axis_tuser=input_0_axis_tuser, input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata, input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tkeep=input_1_axis_tkeep,
input_1_axis_tvalid=input_1_axis_tvalid, input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tlast=input_1_axis_tlast, input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tid=input_1_axis_tid,
input_1_axis_tdest=input_1_axis_tdest,
input_1_axis_tuser=input_1_axis_tuser, input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata, input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tkeep=input_2_axis_tkeep,
input_2_axis_tvalid=input_2_axis_tvalid, input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tlast=input_2_axis_tlast, input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tid=input_2_axis_tid,
input_2_axis_tdest=input_2_axis_tdest,
input_2_axis_tuser=input_2_axis_tuser, input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata, input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tkeep=input_3_axis_tkeep,
input_3_axis_tvalid=input_3_axis_tvalid, input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tlast=input_3_axis_tlast, input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tid=input_3_axis_tid,
input_3_axis_tdest=input_3_axis_tdest,
input_3_axis_tuser=input_3_axis_tuser, input_3_axis_tuser=input_3_axis_tuser,
output_0_axis_tdata=output_0_axis_tdata, output_0_axis_tdata=output_0_axis_tdata,
output_0_axis_tkeep=output_0_axis_tkeep,
output_0_axis_tvalid=output_0_axis_tvalid, output_0_axis_tvalid=output_0_axis_tvalid,
output_0_axis_tlast=output_0_axis_tlast, output_0_axis_tlast=output_0_axis_tlast,
output_0_axis_tid=output_0_axis_tid,
output_0_axis_tdest=output_0_axis_tdest,
output_0_axis_tuser=output_0_axis_tuser, output_0_axis_tuser=output_0_axis_tuser,
output_1_axis_tdata=output_1_axis_tdata, output_1_axis_tdata=output_1_axis_tdata,
output_1_axis_tkeep=output_1_axis_tkeep,
output_1_axis_tvalid=output_1_axis_tvalid, output_1_axis_tvalid=output_1_axis_tvalid,
output_1_axis_tlast=output_1_axis_tlast, output_1_axis_tlast=output_1_axis_tlast,
output_1_axis_tid=output_1_axis_tid,
output_1_axis_tdest=output_1_axis_tdest,
output_1_axis_tuser=output_1_axis_tuser, output_1_axis_tuser=output_1_axis_tuser,
output_2_axis_tdata=output_2_axis_tdata, output_2_axis_tdata=output_2_axis_tdata,
output_2_axis_tkeep=output_2_axis_tkeep,
output_2_axis_tvalid=output_2_axis_tvalid, output_2_axis_tvalid=output_2_axis_tvalid,
output_2_axis_tlast=output_2_axis_tlast, output_2_axis_tlast=output_2_axis_tlast,
output_2_axis_tid=output_2_axis_tid,
output_2_axis_tdest=output_2_axis_tdest,
output_2_axis_tuser=output_2_axis_tuser, output_2_axis_tuser=output_2_axis_tuser,
output_3_axis_tdata=output_3_axis_tdata, output_3_axis_tdata=output_3_axis_tdata,
output_3_axis_tkeep=output_3_axis_tkeep,
output_3_axis_tvalid=output_3_axis_tvalid, output_3_axis_tvalid=output_3_axis_tvalid,
output_3_axis_tlast=output_3_axis_tlast, output_3_axis_tlast=output_3_axis_tlast,
output_3_axis_tid=output_3_axis_tid,
output_3_axis_tdest=output_3_axis_tdest,
output_3_axis_tuser=output_3_axis_tuser, output_3_axis_tuser=output_3_axis_tuser,
output_0_select=output_0_select, output_0_select=output_0_select,
@ -280,10 +361,10 @@ def bench():
output_2_select.next = 2 output_2_select.next = 2
output_3_select.next = 3 output_3_select.next = 3
test_frame0 = axis_ep.AXIStreamFrame(b'\x01\x00\x00\xFF\x01\x02\x03\x04') test_frame0 = axis_ep.AXIStreamFrame(b'\x01\x00\x00\xFF\x01\x02\x03\x04', id=0, dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x01\x01\x01\xFF\x01\x02\x03\x04') test_frame1 = axis_ep.AXIStreamFrame(b'\x01\x01\x01\xFF\x01\x02\x03\x04', id=1, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(b'\x01\x02\x02\xFF\x01\x02\x03\x04') test_frame2 = axis_ep.AXIStreamFrame(b'\x01\x02\x02\xFF\x01\x02\x03\x04', id=2, dest=2)
test_frame3 = axis_ep.AXIStreamFrame(b'\x01\x03\x03\xFF\x01\x02\x03\x04') test_frame3 = axis_ep.AXIStreamFrame(b'\x01\x03\x03\xFF\x01\x02\x03\x04', id=3, dest=3)
source_0.send(test_frame0) source_0.send(test_frame0)
source_1.send(test_frame1) source_1.send(test_frame1)
source_2.send(test_frame2) source_2.send(test_frame2)
@ -322,10 +403,10 @@ def bench():
output_2_select.next = 1 output_2_select.next = 1
output_3_select.next = 0 output_3_select.next = 0
test_frame0 = axis_ep.AXIStreamFrame(b'\x02\x00\x03\xFF\x01\x02\x03\x04') test_frame0 = axis_ep.AXIStreamFrame(b'\x02\x00\x03\xFF\x01\x02\x03\x04', id=0, dest=3)
test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x01\x02\xFF\x01\x02\x03\x04') test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x01\x02\xFF\x01\x02\x03\x04', id=1, dest=2)
test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x02\x01\xFF\x01\x02\x03\x04') test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x02\x01\xFF\x01\x02\x03\x04', id=2, dest=1)
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x03\x00\xFF\x01\x02\x03\x04') test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x03\x00\xFF\x01\x02\x03\x04', id=3, dest=0)
source_0.send(test_frame0) source_0.send(test_frame0)
source_1.send(test_frame1) source_1.send(test_frame1)
source_2.send(test_frame2) source_2.send(test_frame2)
@ -364,7 +445,7 @@ def bench():
output_2_select.next = 0 output_2_select.next = 0
output_3_select.next = 0 output_3_select.next = 0
test_frame0 = axis_ep.AXIStreamFrame(b'\x03\x00\xFF\xFF\x01\x02\x03\x04') test_frame0 = axis_ep.AXIStreamFrame(b'\x03\x00\xFF\xFF\x01\x02\x03\x04', id=0, dest=0)
source_0.send(test_frame0) source_0.send(test_frame0)
yield clk.posedge yield clk.posedge

108
lib/axis/tb/test_axis_crosspoint_4x4.v
View File

@ -33,6 +33,15 @@ module test_axis_crosspoint_4x4;
// Parameters // Parameters
parameter DATA_WIDTH = 8; parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -40,21 +49,33 @@ reg rst = 0;
reg [7:0] current_test = 0; reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] input_0_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_0_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_0_axis_tkeep = 0;
reg input_0_axis_tvalid = 0; reg input_0_axis_tvalid = 0;
reg input_0_axis_tlast = 0; reg input_0_axis_tlast = 0;
reg input_0_axis_tuser = 0; reg [ID_WIDTH-1:0] input_0_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_0_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_0_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_1_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_1_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_1_axis_tkeep = 0;
reg input_1_axis_tvalid = 0; reg input_1_axis_tvalid = 0;
reg input_1_axis_tlast = 0; reg input_1_axis_tlast = 0;
reg input_1_axis_tuser = 0; reg [ID_WIDTH-1:0] input_1_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_1_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_1_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_2_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_2_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_2_axis_tkeep = 0;
reg input_2_axis_tvalid = 0; reg input_2_axis_tvalid = 0;
reg input_2_axis_tlast = 0; reg input_2_axis_tlast = 0;
reg input_2_axis_tuser = 0; reg [ID_WIDTH-1:0] input_2_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_2_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_2_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_3_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_3_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_3_axis_tkeep = 0;
reg input_3_axis_tvalid = 0; reg input_3_axis_tvalid = 0;
reg input_3_axis_tlast = 0; reg input_3_axis_tlast = 0;
reg input_3_axis_tuser = 0; reg [ID_WIDTH-1:0] input_3_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_3_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_3_axis_tuser = 0;
reg [1:0] output_0_select = 0; reg [1:0] output_0_select = 0;
reg [1:0] output_1_select = 0; reg [1:0] output_1_select = 0;
@ -63,21 +84,33 @@ reg [1:0] output_3_select = 0;
// Outputs // Outputs
wire [DATA_WIDTH-1:0] output_0_axis_tdata; wire [DATA_WIDTH-1:0] output_0_axis_tdata;
wire [KEEP_WIDTH-1:0] output_0_axis_tkeep;
wire output_0_axis_tvalid; wire output_0_axis_tvalid;
wire output_0_axis_tlast; wire output_0_axis_tlast;
wire output_0_axis_tuser; wire [ID_WIDTH-1:0] output_0_axis_tid;
wire [DEST_WIDTH-1:0] output_0_axis_tdest;
wire [USER_WIDTH-1:0] output_0_axis_tuser;
wire [DATA_WIDTH-1:0] output_1_axis_tdata; wire [DATA_WIDTH-1:0] output_1_axis_tdata;
wire [KEEP_WIDTH-1:0] output_1_axis_tkeep;
wire output_1_axis_tvalid; wire output_1_axis_tvalid;
wire output_1_axis_tlast; wire output_1_axis_tlast;
wire output_1_axis_tuser; wire [ID_WIDTH-1:0] output_1_axis_tid;
wire [DEST_WIDTH-1:0] output_1_axis_tdest;
wire [USER_WIDTH-1:0] output_1_axis_tuser;
wire [DATA_WIDTH-1:0] output_2_axis_tdata; wire [DATA_WIDTH-1:0] output_2_axis_tdata;
wire [KEEP_WIDTH-1:0] output_2_axis_tkeep;
wire output_2_axis_tvalid; wire output_2_axis_tvalid;
wire output_2_axis_tlast; wire output_2_axis_tlast;
wire output_2_axis_tuser; wire [ID_WIDTH-1:0] output_2_axis_tid;
wire [DEST_WIDTH-1:0] output_2_axis_tdest;
wire [USER_WIDTH-1:0] output_2_axis_tuser;
wire [DATA_WIDTH-1:0] output_3_axis_tdata; wire [DATA_WIDTH-1:0] output_3_axis_tdata;
wire [KEEP_WIDTH-1:0] output_3_axis_tkeep;
wire output_3_axis_tvalid; wire output_3_axis_tvalid;
wire output_3_axis_tlast; wire output_3_axis_tlast;
wire output_3_axis_tuser; wire [ID_WIDTH-1:0] output_3_axis_tid;
wire [DEST_WIDTH-1:0] output_3_axis_tdest;
wire [USER_WIDTH-1:0] output_3_axis_tuser;
initial begin initial begin
// myhdl integration // myhdl integration
@ -86,20 +119,32 @@ initial begin
rst, rst,
current_test, current_test,
input_0_axis_tdata, input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid, input_0_axis_tvalid,
input_0_axis_tlast, input_0_axis_tlast,
input_0_axis_tid,
input_0_axis_tdest,
input_0_axis_tuser, input_0_axis_tuser,
input_1_axis_tdata, input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid, input_1_axis_tvalid,
input_1_axis_tlast, input_1_axis_tlast,
input_1_axis_tid,
input_1_axis_tdest,
input_1_axis_tuser, input_1_axis_tuser,
input_2_axis_tdata, input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid, input_2_axis_tvalid,
input_2_axis_tlast, input_2_axis_tlast,
input_2_axis_tid,
input_2_axis_tdest,
input_2_axis_tuser, input_2_axis_tuser,
input_3_axis_tdata, input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid, input_3_axis_tvalid,
input_3_axis_tlast, input_3_axis_tlast,
input_3_axis_tid,
input_3_axis_tdest,
input_3_axis_tuser, input_3_axis_tuser,
output_0_select, output_0_select,
output_1_select, output_1_select,
@ -108,20 +153,32 @@ initial begin
); );
$to_myhdl( $to_myhdl(
output_0_axis_tdata, output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid, output_0_axis_tvalid,
output_0_axis_tlast, output_0_axis_tlast,
output_0_axis_tid,
output_0_axis_tdest,
output_0_axis_tuser, output_0_axis_tuser,
output_1_axis_tdata, output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid, output_1_axis_tvalid,
output_1_axis_tlast, output_1_axis_tlast,
output_1_axis_tid,
output_1_axis_tdest,
output_1_axis_tuser, output_1_axis_tuser,
output_2_axis_tdata, output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid, output_2_axis_tvalid,
output_2_axis_tlast, output_2_axis_tlast,
output_2_axis_tid,
output_2_axis_tdest,
output_2_axis_tuser, output_2_axis_tuser,
output_3_axis_tdata, output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid, output_3_axis_tvalid,
output_3_axis_tlast, output_3_axis_tlast,
output_3_axis_tid,
output_3_axis_tdest,
output_3_axis_tuser output_3_axis_tuser
); );
@ -131,44 +188,77 @@ initial begin
end end
axis_crosspoint_4x4 #( axis_crosspoint_4x4 #(
.DATA_WIDTH(DATA_WIDTH) .DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) )
UUT ( UUT (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
// AXI inputs // AXI inputs
.input_0_axis_tdata(input_0_axis_tdata), .input_0_axis_tdata(input_0_axis_tdata),
.input_0_axis_tkeep(input_0_axis_tkeep),
.input_0_axis_tvalid(input_0_axis_tvalid), .input_0_axis_tvalid(input_0_axis_tvalid),
.input_0_axis_tlast(input_0_axis_tlast), .input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tid(input_0_axis_tid),
.input_0_axis_tdest(input_0_axis_tdest),
.input_0_axis_tuser(input_0_axis_tuser), .input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata), .input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tkeep(input_1_axis_tkeep),
.input_1_axis_tvalid(input_1_axis_tvalid), .input_1_axis_tvalid(input_1_axis_tvalid),
.input_1_axis_tlast(input_1_axis_tlast), .input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tid(input_1_axis_tid),
.input_1_axis_tdest(input_1_axis_tdest),
.input_1_axis_tuser(input_1_axis_tuser), .input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata), .input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tkeep(input_2_axis_tkeep),
.input_2_axis_tvalid(input_2_axis_tvalid), .input_2_axis_tvalid(input_2_axis_tvalid),
.input_2_axis_tlast(input_2_axis_tlast), .input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tid(input_2_axis_tid),
.input_2_axis_tdest(input_2_axis_tdest),
.input_2_axis_tuser(input_2_axis_tuser), .input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata), .input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tkeep(input_3_axis_tkeep),
.input_3_axis_tvalid(input_3_axis_tvalid), .input_3_axis_tvalid(input_3_axis_tvalid),
.input_3_axis_tlast(input_3_axis_tlast), .input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tid(input_3_axis_tid),
.input_3_axis_tdest(input_3_axis_tdest),
.input_3_axis_tuser(input_3_axis_tuser), .input_3_axis_tuser(input_3_axis_tuser),
// AXI outputs // AXI outputs
.output_0_axis_tdata(output_0_axis_tdata), .output_0_axis_tdata(output_0_axis_tdata),
.output_0_axis_tkeep(output_0_axis_tkeep),
.output_0_axis_tvalid(output_0_axis_tvalid), .output_0_axis_tvalid(output_0_axis_tvalid),
.output_0_axis_tlast(output_0_axis_tlast), .output_0_axis_tlast(output_0_axis_tlast),
.output_0_axis_tid(output_0_axis_tid),
.output_0_axis_tdest(output_0_axis_tdest),
.output_0_axis_tuser(output_0_axis_tuser), .output_0_axis_tuser(output_0_axis_tuser),
.output_1_axis_tdata(output_1_axis_tdata), .output_1_axis_tdata(output_1_axis_tdata),
.output_1_axis_tkeep(output_1_axis_tkeep),
.output_1_axis_tvalid(output_1_axis_tvalid), .output_1_axis_tvalid(output_1_axis_tvalid),
.output_1_axis_tlast(output_1_axis_tlast), .output_1_axis_tlast(output_1_axis_tlast),
.output_1_axis_tid(output_1_axis_tid),
.output_1_axis_tdest(output_1_axis_tdest),
.output_1_axis_tuser(output_1_axis_tuser), .output_1_axis_tuser(output_1_axis_tuser),
.output_2_axis_tdata(output_2_axis_tdata), .output_2_axis_tdata(output_2_axis_tdata),
.output_2_axis_tkeep(output_2_axis_tkeep),
.output_2_axis_tvalid(output_2_axis_tvalid), .output_2_axis_tvalid(output_2_axis_tvalid),
.output_2_axis_tlast(output_2_axis_tlast), .output_2_axis_tlast(output_2_axis_tlast),
.output_2_axis_tid(output_2_axis_tid),
.output_2_axis_tdest(output_2_axis_tdest),
.output_2_axis_tuser(output_2_axis_tuser), .output_2_axis_tuser(output_2_axis_tuser),
.output_3_axis_tdata(output_3_axis_tdata), .output_3_axis_tdata(output_3_axis_tdata),
.output_3_axis_tkeep(output_3_axis_tkeep),
.output_3_axis_tvalid(output_3_axis_tvalid), .output_3_axis_tvalid(output_3_axis_tvalid),
.output_3_axis_tlast(output_3_axis_tlast), .output_3_axis_tlast(output_3_axis_tlast),
.output_3_axis_tid(output_3_axis_tid),
.output_3_axis_tdest(output_3_axis_tdest),
.output_3_axis_tuser(output_3_axis_tuser), .output_3_axis_tuser(output_3_axis_tuser),
// Control // Control
.output_0_select(output_0_select), .output_0_select(output_0_select),

110
lib/axis/tb/test_axis_crosspoint_64_4x4.py → lib/axis/tb/test_axis_crosspoint_4x4_64.py
View File

@ -28,8 +28,8 @@ import os
import axis_ep import axis_ep
module = 'axis_crosspoint_64_4x4' module = 'axis_crosspoint_4x4'
testbench = 'test_%s' % module testbench = 'test_%s_64' % module
srcs = [] srcs = []
@ -44,7 +44,15 @@ def bench():
# Parameters # Parameters
DATA_WIDTH = 64 DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8) KEEP_WIDTH = (DATA_WIDTH/8)
LAST_ENABLE = 1
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))
@ -52,25 +60,33 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_0_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_0_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_0_axis_tvalid = Signal(bool(0)) input_0_axis_tvalid = Signal(bool(0))
input_0_axis_tlast = Signal(bool(0)) input_0_axis_tlast = Signal(bool(0))
input_0_axis_tuser = Signal(bool(0)) input_0_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_0_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_0_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_1_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_1_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_1_axis_tvalid = Signal(bool(0)) input_1_axis_tvalid = Signal(bool(0))
input_1_axis_tlast = Signal(bool(0)) input_1_axis_tlast = Signal(bool(0))
input_1_axis_tuser = Signal(bool(0)) input_1_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_1_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_1_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_2_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_2_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_2_axis_tvalid = Signal(bool(0)) input_2_axis_tvalid = Signal(bool(0))
input_2_axis_tlast = Signal(bool(0)) input_2_axis_tlast = Signal(bool(0))
input_2_axis_tuser = Signal(bool(0)) input_2_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_2_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_2_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_3_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_3_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_3_axis_tvalid = Signal(bool(0)) input_3_axis_tvalid = Signal(bool(0))
input_3_axis_tlast = Signal(bool(0)) input_3_axis_tlast = Signal(bool(0))
input_3_axis_tuser = Signal(bool(0)) input_3_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_3_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_3_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_0_select = Signal(intbv(0)[2:]) output_0_select = Signal(intbv(0)[2:])
output_1_select = Signal(intbv(0)[2:]) output_1_select = Signal(intbv(0)[2:])
@ -79,25 +95,33 @@ def bench():
# Outputs # Outputs
output_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_0_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) output_0_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_0_axis_tvalid = Signal(bool(0)) output_0_axis_tvalid = Signal(bool(0))
output_0_axis_tlast = Signal(bool(0)) output_0_axis_tlast = Signal(bool(0))
output_0_axis_tuser = Signal(bool(0)) output_0_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_0_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_0_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_1_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) output_1_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_1_axis_tvalid = Signal(bool(0)) output_1_axis_tvalid = Signal(bool(0))
output_1_axis_tlast = Signal(bool(0)) output_1_axis_tlast = Signal(bool(0))
output_1_axis_tuser = Signal(bool(0)) output_1_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_1_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_1_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_2_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) output_2_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_2_axis_tvalid = Signal(bool(0)) output_2_axis_tvalid = Signal(bool(0))
output_2_axis_tlast = Signal(bool(0)) output_2_axis_tlast = Signal(bool(0))
output_2_axis_tuser = Signal(bool(0)) output_2_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_2_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_2_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_3_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) output_3_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_3_axis_tvalid = Signal(bool(0)) output_3_axis_tvalid = Signal(bool(0))
output_3_axis_tlast = Signal(bool(0)) output_3_axis_tlast = Signal(bool(0))
output_3_axis_tuser = Signal(bool(0)) output_3_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_3_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_3_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks # sources and sinks
source_0_pause = Signal(bool(0)) source_0_pause = Signal(bool(0))
@ -118,6 +142,8 @@ def bench():
tkeep=input_0_axis_tkeep, tkeep=input_0_axis_tkeep,
tvalid=input_0_axis_tvalid, tvalid=input_0_axis_tvalid,
tlast=input_0_axis_tlast, tlast=input_0_axis_tlast,
tid=input_0_axis_tid,
tdest=input_0_axis_tdest,
tuser=input_0_axis_tuser, tuser=input_0_axis_tuser,
pause=source_0_pause, pause=source_0_pause,
name='source_0' name='source_0'
@ -132,6 +158,8 @@ def bench():
tkeep=input_1_axis_tkeep, tkeep=input_1_axis_tkeep,
tvalid=input_1_axis_tvalid, tvalid=input_1_axis_tvalid,
tlast=input_1_axis_tlast, tlast=input_1_axis_tlast,
tid=input_1_axis_tid,
tdest=input_1_axis_tdest,
tuser=input_1_axis_tuser, tuser=input_1_axis_tuser,
pause=source_1_pause, pause=source_1_pause,
name='source_1' name='source_1'
@ -146,6 +174,8 @@ def bench():
tkeep=input_2_axis_tkeep, tkeep=input_2_axis_tkeep,
tvalid=input_2_axis_tvalid, tvalid=input_2_axis_tvalid,
tlast=input_2_axis_tlast, tlast=input_2_axis_tlast,
tid=input_2_axis_tid,
tdest=input_2_axis_tdest,
tuser=input_2_axis_tuser, tuser=input_2_axis_tuser,
pause=source_2_pause, pause=source_2_pause,
name='source_2' name='source_2'
@ -160,6 +190,8 @@ def bench():
tkeep=input_3_axis_tkeep, tkeep=input_3_axis_tkeep,
tvalid=input_3_axis_tvalid, tvalid=input_3_axis_tvalid,
tlast=input_3_axis_tlast, tlast=input_3_axis_tlast,
tid=input_3_axis_tid,
tdest=input_3_axis_tdest,
tuser=input_3_axis_tuser, tuser=input_3_axis_tuser,
pause=source_3_pause, pause=source_3_pause,
name='source_3' name='source_3'
@ -174,6 +206,8 @@ def bench():
tkeep=output_0_axis_tkeep, tkeep=output_0_axis_tkeep,
tvalid=output_0_axis_tvalid, tvalid=output_0_axis_tvalid,
tlast=output_0_axis_tlast, tlast=output_0_axis_tlast,
tid=output_0_axis_tid,
tdest=output_0_axis_tdest,
tuser=output_0_axis_tuser, tuser=output_0_axis_tuser,
pause=sink_0_pause, pause=sink_0_pause,
name='sink_0' name='sink_0'
@ -188,6 +222,8 @@ def bench():
tkeep=output_1_axis_tkeep, tkeep=output_1_axis_tkeep,
tvalid=output_1_axis_tvalid, tvalid=output_1_axis_tvalid,
tlast=output_1_axis_tlast, tlast=output_1_axis_tlast,
tid=output_1_axis_tid,
tdest=output_1_axis_tdest,
tuser=output_1_axis_tuser, tuser=output_1_axis_tuser,
pause=sink_1_pause, pause=sink_1_pause,
name='sink_1' name='sink_1'
@ -202,6 +238,8 @@ def bench():
tkeep=output_2_axis_tkeep, tkeep=output_2_axis_tkeep,
tvalid=output_2_axis_tvalid, tvalid=output_2_axis_tvalid,
tlast=output_2_axis_tlast, tlast=output_2_axis_tlast,
tid=output_2_axis_tid,
tdest=output_2_axis_tdest,
tuser=output_2_axis_tuser, tuser=output_2_axis_tuser,
pause=sink_2_pause, pause=sink_2_pause,
name='sink_2' name='sink_2'
@ -216,6 +254,8 @@ def bench():
tkeep=output_3_axis_tkeep, tkeep=output_3_axis_tkeep,
tvalid=output_3_axis_tvalid, tvalid=output_3_axis_tvalid,
tlast=output_3_axis_tlast, tlast=output_3_axis_tlast,
tid=output_3_axis_tid,
tdest=output_3_axis_tdest,
tuser=output_3_axis_tuser, tuser=output_3_axis_tuser,
pause=sink_3_pause, pause=sink_3_pause,
name='sink_3' name='sink_3'
@ -235,42 +275,58 @@ def bench():
input_0_axis_tkeep=input_0_axis_tkeep, input_0_axis_tkeep=input_0_axis_tkeep,
input_0_axis_tvalid=input_0_axis_tvalid, input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tlast=input_0_axis_tlast, input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tid=input_0_axis_tid,
input_0_axis_tdest=input_0_axis_tdest,
input_0_axis_tuser=input_0_axis_tuser, input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata, input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tkeep=input_1_axis_tkeep, input_1_axis_tkeep=input_1_axis_tkeep,
input_1_axis_tvalid=input_1_axis_tvalid, input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tlast=input_1_axis_tlast, input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tid=input_1_axis_tid,
input_1_axis_tdest=input_1_axis_tdest,
input_1_axis_tuser=input_1_axis_tuser, input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata, input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tkeep=input_2_axis_tkeep, input_2_axis_tkeep=input_2_axis_tkeep,
input_2_axis_tvalid=input_2_axis_tvalid, input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tlast=input_2_axis_tlast, input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tid=input_2_axis_tid,
input_2_axis_tdest=input_2_axis_tdest,
input_2_axis_tuser=input_2_axis_tuser, input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata, input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tkeep=input_3_axis_tkeep, input_3_axis_tkeep=input_3_axis_tkeep,
input_3_axis_tvalid=input_3_axis_tvalid, input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tlast=input_3_axis_tlast, input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tid=input_3_axis_tid,
input_3_axis_tdest=input_3_axis_tdest,
input_3_axis_tuser=input_3_axis_tuser, input_3_axis_tuser=input_3_axis_tuser,
output_0_axis_tdata=output_0_axis_tdata, output_0_axis_tdata=output_0_axis_tdata,
output_0_axis_tkeep=output_0_axis_tkeep, output_0_axis_tkeep=output_0_axis_tkeep,
output_0_axis_tvalid=output_0_axis_tvalid, output_0_axis_tvalid=output_0_axis_tvalid,
output_0_axis_tlast=output_0_axis_tlast, output_0_axis_tlast=output_0_axis_tlast,
output_0_axis_tid=output_0_axis_tid,
output_0_axis_tdest=output_0_axis_tdest,
output_0_axis_tuser=output_0_axis_tuser, output_0_axis_tuser=output_0_axis_tuser,
output_1_axis_tdata=output_1_axis_tdata, output_1_axis_tdata=output_1_axis_tdata,
output_1_axis_tkeep=output_1_axis_tkeep, output_1_axis_tkeep=output_1_axis_tkeep,
output_1_axis_tvalid=output_1_axis_tvalid, output_1_axis_tvalid=output_1_axis_tvalid,
output_1_axis_tlast=output_1_axis_tlast, output_1_axis_tlast=output_1_axis_tlast,
output_1_axis_tid=output_1_axis_tid,
output_1_axis_tdest=output_1_axis_tdest,
output_1_axis_tuser=output_1_axis_tuser, output_1_axis_tuser=output_1_axis_tuser,
output_2_axis_tdata=output_2_axis_tdata, output_2_axis_tdata=output_2_axis_tdata,
output_2_axis_tkeep=output_2_axis_tkeep, output_2_axis_tkeep=output_2_axis_tkeep,
output_2_axis_tvalid=output_2_axis_tvalid, output_2_axis_tvalid=output_2_axis_tvalid,
output_2_axis_tlast=output_2_axis_tlast, output_2_axis_tlast=output_2_axis_tlast,
output_2_axis_tid=output_2_axis_tid,
output_2_axis_tdest=output_2_axis_tdest,
output_2_axis_tuser=output_2_axis_tuser, output_2_axis_tuser=output_2_axis_tuser,
output_3_axis_tdata=output_3_axis_tdata, output_3_axis_tdata=output_3_axis_tdata,
output_3_axis_tkeep=output_3_axis_tkeep, output_3_axis_tkeep=output_3_axis_tkeep,
output_3_axis_tvalid=output_3_axis_tvalid, output_3_axis_tvalid=output_3_axis_tvalid,
output_3_axis_tlast=output_3_axis_tlast, output_3_axis_tlast=output_3_axis_tlast,
output_3_axis_tid=output_3_axis_tid,
output_3_axis_tdest=output_3_axis_tdest,
output_3_axis_tuser=output_3_axis_tuser, output_3_axis_tuser=output_3_axis_tuser,
output_0_select=output_0_select, output_0_select=output_0_select,
@ -305,10 +361,10 @@ def bench():
output_2_select.next = 2 output_2_select.next = 2
output_3_select.next = 3 output_3_select.next = 3
test_frame0 = axis_ep.AXIStreamFrame(b'\x01\x00\x00\xFF\x01\x02\x03\x04') test_frame0 = axis_ep.AXIStreamFrame(b'\x01\x00\x00\xFF\x01\x02\x03\x04', id=0, dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x01\x01\x01\xFF\x01\x02\x03\x04') test_frame1 = axis_ep.AXIStreamFrame(b'\x01\x01\x01\xFF\x01\x02\x03\x04', id=1, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(b'\x01\x02\x02\xFF\x01\x02\x03\x04') test_frame2 = axis_ep.AXIStreamFrame(b'\x01\x02\x02\xFF\x01\x02\x03\x04', id=2, dest=2)
test_frame3 = axis_ep.AXIStreamFrame(b'\x01\x03\x03\xFF\x01\x02\x03\x04') test_frame3 = axis_ep.AXIStreamFrame(b'\x01\x03\x03\xFF\x01\x02\x03\x04', id=3, dest=3)
source_0.send(test_frame0) source_0.send(test_frame0)
source_1.send(test_frame1) source_1.send(test_frame1)
source_2.send(test_frame2) source_2.send(test_frame2)
@ -347,10 +403,10 @@ def bench():
output_2_select.next = 1 output_2_select.next = 1
output_3_select.next = 0 output_3_select.next = 0
test_frame0 = axis_ep.AXIStreamFrame(b'\x02\x00\x03\xFF\x01\x02\x03\x04') test_frame0 = axis_ep.AXIStreamFrame(b'\x02\x00\x03\xFF\x01\x02\x03\x04', id=0, dest=3)
test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x01\x02\xFF\x01\x02\x03\x04') test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x01\x02\xFF\x01\x02\x03\x04', id=1, dest=2)
test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x02\x01\xFF\x01\x02\x03\x04') test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x02\x01\xFF\x01\x02\x03\x04', id=2, dest=1)
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x03\x00\xFF\x01\x02\x03\x04') test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x03\x00\xFF\x01\x02\x03\x04', id=3, dest=0)
source_0.send(test_frame0) source_0.send(test_frame0)
source_1.send(test_frame1) source_1.send(test_frame1)
source_2.send(test_frame2) source_2.send(test_frame2)
@ -389,7 +445,7 @@ def bench():
output_2_select.next = 0 output_2_select.next = 0
output_3_select.next = 0 output_3_select.next = 0
test_frame0 = axis_ep.AXIStreamFrame(b'\x03\x00\xFF\xFF\x01\x02\x03\x04') test_frame0 = axis_ep.AXIStreamFrame(b'\x03\x00\xFF\xFF\x01\x02\x03\x04', id=0, dest=0)
source_0.send(test_frame0) source_0.send(test_frame0)
yield clk.posedge yield clk.posedge

92
lib/axis/tb/test_axis_crosspoint_64_4x4.v → lib/axis/tb/test_axis_crosspoint_4x4_64.v
View File

@ -27,13 +27,21 @@ THE SOFTWARE.
`timescale 1ns / 1ps `timescale 1ns / 1ps
/* /*
* Testbench for axis_crosspoint_64_4x4 * Testbench for axis_crosspoint_4x4
*/ */
module test_axis_crosspoint_64_4x4; module test_axis_crosspoint_4x4_64;
// Parameters // Parameters
parameter DATA_WIDTH = 64; parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8); parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -44,22 +52,30 @@ reg [DATA_WIDTH-1:0] input_0_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_0_axis_tkeep = 0; reg [KEEP_WIDTH-1:0] input_0_axis_tkeep = 0;
reg input_0_axis_tvalid = 0; reg input_0_axis_tvalid = 0;
reg input_0_axis_tlast = 0; reg input_0_axis_tlast = 0;
reg input_0_axis_tuser = 0; reg [ID_WIDTH-1:0] input_0_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_0_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_0_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_1_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_1_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_1_axis_tkeep = 0; reg [KEEP_WIDTH-1:0] input_1_axis_tkeep = 0;
reg input_1_axis_tvalid = 0; reg input_1_axis_tvalid = 0;
reg input_1_axis_tlast = 0; reg input_1_axis_tlast = 0;
reg input_1_axis_tuser = 0; reg [ID_WIDTH-1:0] input_1_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_1_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_1_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_2_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_2_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_2_axis_tkeep = 0; reg [KEEP_WIDTH-1:0] input_2_axis_tkeep = 0;
reg input_2_axis_tvalid = 0; reg input_2_axis_tvalid = 0;
reg input_2_axis_tlast = 0; reg input_2_axis_tlast = 0;
reg input_2_axis_tuser = 0; reg [ID_WIDTH-1:0] input_2_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_2_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_2_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_3_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_3_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_3_axis_tkeep = 0; reg [KEEP_WIDTH-1:0] input_3_axis_tkeep = 0;
reg input_3_axis_tvalid = 0; reg input_3_axis_tvalid = 0;
reg input_3_axis_tlast = 0; reg input_3_axis_tlast = 0;
reg input_3_axis_tuser = 0; reg [ID_WIDTH-1:0] input_3_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_3_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_3_axis_tuser = 0;
reg [1:0] output_0_select = 0; reg [1:0] output_0_select = 0;
reg [1:0] output_1_select = 0; reg [1:0] output_1_select = 0;
@ -71,22 +87,30 @@ wire [DATA_WIDTH-1:0] output_0_axis_tdata;
wire [KEEP_WIDTH-1:0] output_0_axis_tkeep; wire [KEEP_WIDTH-1:0] output_0_axis_tkeep;
wire output_0_axis_tvalid; wire output_0_axis_tvalid;
wire output_0_axis_tlast; wire output_0_axis_tlast;
wire output_0_axis_tuser; wire [ID_WIDTH-1:0] output_0_axis_tid;
wire [DEST_WIDTH-1:0] output_0_axis_tdest;
wire [USER_WIDTH-1:0] output_0_axis_tuser;
wire [DATA_WIDTH-1:0] output_1_axis_tdata; wire [DATA_WIDTH-1:0] output_1_axis_tdata;
wire [KEEP_WIDTH-1:0] output_1_axis_tkeep; wire [KEEP_WIDTH-1:0] output_1_axis_tkeep;
wire output_1_axis_tvalid; wire output_1_axis_tvalid;
wire output_1_axis_tlast; wire output_1_axis_tlast;
wire output_1_axis_tuser; wire [ID_WIDTH-1:0] output_1_axis_tid;
wire [DEST_WIDTH-1:0] output_1_axis_tdest;
wire [USER_WIDTH-1:0] output_1_axis_tuser;
wire [DATA_WIDTH-1:0] output_2_axis_tdata; wire [DATA_WIDTH-1:0] output_2_axis_tdata;
wire [KEEP_WIDTH-1:0] output_2_axis_tkeep; wire [KEEP_WIDTH-1:0] output_2_axis_tkeep;
wire output_2_axis_tvalid; wire output_2_axis_tvalid;
wire output_2_axis_tlast; wire output_2_axis_tlast;
wire output_2_axis_tuser; wire [ID_WIDTH-1:0] output_2_axis_tid;
wire [DEST_WIDTH-1:0] output_2_axis_tdest;
wire [USER_WIDTH-1:0] output_2_axis_tuser;
wire [DATA_WIDTH-1:0] output_3_axis_tdata; wire [DATA_WIDTH-1:0] output_3_axis_tdata;
wire [KEEP_WIDTH-1:0] output_3_axis_tkeep; wire [KEEP_WIDTH-1:0] output_3_axis_tkeep;
wire output_3_axis_tvalid; wire output_3_axis_tvalid;
wire output_3_axis_tlast; wire output_3_axis_tlast;
wire output_3_axis_tuser; wire [ID_WIDTH-1:0] output_3_axis_tid;
wire [DEST_WIDTH-1:0] output_3_axis_tdest;
wire [USER_WIDTH-1:0] output_3_axis_tuser;
initial begin initial begin
// myhdl integration // myhdl integration
@ -98,21 +122,29 @@ initial begin
input_0_axis_tkeep, input_0_axis_tkeep,
input_0_axis_tvalid, input_0_axis_tvalid,
input_0_axis_tlast, input_0_axis_tlast,
input_0_axis_tid,
input_0_axis_tdest,
input_0_axis_tuser, input_0_axis_tuser,
input_1_axis_tdata, input_1_axis_tdata,
input_1_axis_tkeep, input_1_axis_tkeep,
input_1_axis_tvalid, input_1_axis_tvalid,
input_1_axis_tlast, input_1_axis_tlast,
input_1_axis_tid,
input_1_axis_tdest,
input_1_axis_tuser, input_1_axis_tuser,
input_2_axis_tdata, input_2_axis_tdata,
input_2_axis_tkeep, input_2_axis_tkeep,
input_2_axis_tvalid, input_2_axis_tvalid,
input_2_axis_tlast, input_2_axis_tlast,
input_2_axis_tid,
input_2_axis_tdest,
input_2_axis_tuser, input_2_axis_tuser,
input_3_axis_tdata, input_3_axis_tdata,
input_3_axis_tkeep, input_3_axis_tkeep,
input_3_axis_tvalid, input_3_axis_tvalid,
input_3_axis_tlast, input_3_axis_tlast,
input_3_axis_tid,
input_3_axis_tdest,
input_3_axis_tuser, input_3_axis_tuser,
output_0_select, output_0_select,
output_1_select, output_1_select,
@ -124,32 +156,48 @@ initial begin
output_0_axis_tkeep, output_0_axis_tkeep,
output_0_axis_tvalid, output_0_axis_tvalid,
output_0_axis_tlast, output_0_axis_tlast,
output_0_axis_tid,
output_0_axis_tdest,
output_0_axis_tuser, output_0_axis_tuser,
output_1_axis_tdata, output_1_axis_tdata,
output_1_axis_tkeep, output_1_axis_tkeep,
output_1_axis_tvalid, output_1_axis_tvalid,
output_1_axis_tlast, output_1_axis_tlast,
output_1_axis_tid,
output_1_axis_tdest,
output_1_axis_tuser, output_1_axis_tuser,
output_2_axis_tdata, output_2_axis_tdata,
output_2_axis_tkeep, output_2_axis_tkeep,
output_2_axis_tvalid, output_2_axis_tvalid,
output_2_axis_tlast, output_2_axis_tlast,
output_2_axis_tid,
output_2_axis_tdest,
output_2_axis_tuser, output_2_axis_tuser,
output_3_axis_tdata, output_3_axis_tdata,
output_3_axis_tkeep, output_3_axis_tkeep,
output_3_axis_tvalid, output_3_axis_tvalid,
output_3_axis_tlast, output_3_axis_tlast,
output_3_axis_tid,
output_3_axis_tdest,
output_3_axis_tuser output_3_axis_tuser
); );
// dump file // dump file
$dumpfile("test_axis_crosspoint_64_4x4.lxt"); $dumpfile("test_axis_crosspoint_4x4_64.lxt");
$dumpvars(0, test_axis_crosspoint_64_4x4); $dumpvars(0, test_axis_crosspoint_4x4_64);
end end
axis_crosspoint_64_4x4 #( axis_crosspoint_4x4 #(
.DATA_WIDTH(DATA_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH) .KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) )
UUT ( UUT (
.clk(clk), .clk(clk),
@ -159,42 +207,58 @@ UUT (
.input_0_axis_tkeep(input_0_axis_tkeep), .input_0_axis_tkeep(input_0_axis_tkeep),
.input_0_axis_tvalid(input_0_axis_tvalid), .input_0_axis_tvalid(input_0_axis_tvalid),
.input_0_axis_tlast(input_0_axis_tlast), .input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tid(input_0_axis_tid),
.input_0_axis_tdest(input_0_axis_tdest),
.input_0_axis_tuser(input_0_axis_tuser), .input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata), .input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tkeep(input_1_axis_tkeep), .input_1_axis_tkeep(input_1_axis_tkeep),
.input_1_axis_tvalid(input_1_axis_tvalid), .input_1_axis_tvalid(input_1_axis_tvalid),
.input_1_axis_tlast(input_1_axis_tlast), .input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tid(input_1_axis_tid),
.input_1_axis_tdest(input_1_axis_tdest),
.input_1_axis_tuser(input_1_axis_tuser), .input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata), .input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tkeep(input_2_axis_tkeep), .input_2_axis_tkeep(input_2_axis_tkeep),
.input_2_axis_tvalid(input_2_axis_tvalid), .input_2_axis_tvalid(input_2_axis_tvalid),
.input_2_axis_tlast(input_2_axis_tlast), .input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tid(input_2_axis_tid),
.input_2_axis_tdest(input_2_axis_tdest),
.input_2_axis_tuser(input_2_axis_tuser), .input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata), .input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tkeep(input_3_axis_tkeep), .input_3_axis_tkeep(input_3_axis_tkeep),
.input_3_axis_tvalid(input_3_axis_tvalid), .input_3_axis_tvalid(input_3_axis_tvalid),
.input_3_axis_tlast(input_3_axis_tlast), .input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tid(input_3_axis_tid),
.input_3_axis_tdest(input_3_axis_tdest),
.input_3_axis_tuser(input_3_axis_tuser), .input_3_axis_tuser(input_3_axis_tuser),
// AXI outputs // AXI outputs
.output_0_axis_tdata(output_0_axis_tdata), .output_0_axis_tdata(output_0_axis_tdata),
.output_0_axis_tkeep(output_0_axis_tkeep), .output_0_axis_tkeep(output_0_axis_tkeep),
.output_0_axis_tvalid(output_0_axis_tvalid), .output_0_axis_tvalid(output_0_axis_tvalid),
.output_0_axis_tlast(output_0_axis_tlast), .output_0_axis_tlast(output_0_axis_tlast),
.output_0_axis_tid(output_0_axis_tid),
.output_0_axis_tdest(output_0_axis_tdest),
.output_0_axis_tuser(output_0_axis_tuser), .output_0_axis_tuser(output_0_axis_tuser),
.output_1_axis_tdata(output_1_axis_tdata), .output_1_axis_tdata(output_1_axis_tdata),
.output_1_axis_tkeep(output_1_axis_tkeep), .output_1_axis_tkeep(output_1_axis_tkeep),
.output_1_axis_tvalid(output_1_axis_tvalid), .output_1_axis_tvalid(output_1_axis_tvalid),
.output_1_axis_tlast(output_1_axis_tlast), .output_1_axis_tlast(output_1_axis_tlast),
.output_1_axis_tid(output_1_axis_tid),
.output_1_axis_tdest(output_1_axis_tdest),
.output_1_axis_tuser(output_1_axis_tuser), .output_1_axis_tuser(output_1_axis_tuser),
.output_2_axis_tdata(output_2_axis_tdata), .output_2_axis_tdata(output_2_axis_tdata),
.output_2_axis_tkeep(output_2_axis_tkeep), .output_2_axis_tkeep(output_2_axis_tkeep),
.output_2_axis_tvalid(output_2_axis_tvalid), .output_2_axis_tvalid(output_2_axis_tvalid),
.output_2_axis_tlast(output_2_axis_tlast), .output_2_axis_tlast(output_2_axis_tlast),
.output_2_axis_tid(output_2_axis_tid),
.output_2_axis_tdest(output_2_axis_tdest),
.output_2_axis_tuser(output_2_axis_tuser), .output_2_axis_tuser(output_2_axis_tuser),
.output_3_axis_tdata(output_3_axis_tdata), .output_3_axis_tdata(output_3_axis_tdata),
.output_3_axis_tkeep(output_3_axis_tkeep), .output_3_axis_tkeep(output_3_axis_tkeep),
.output_3_axis_tvalid(output_3_axis_tvalid), .output_3_axis_tvalid(output_3_axis_tvalid),
.output_3_axis_tlast(output_3_axis_tlast), .output_3_axis_tlast(output_3_axis_tlast),
.output_3_axis_tid(output_3_axis_tid),
.output_3_axis_tdest(output_3_axis_tdest),
.output_3_axis_tuser(output_3_axis_tuser), .output_3_axis_tuser(output_3_axis_tuser),
// Control // Control
.output_0_select(output_0_select), .output_0_select(output_0_select),

189
lib/axis/tb/test_axis_demux_4.py
View File

@ -44,6 +44,14 @@ def bench():
# Parameters # Parameters
DATA_WIDTH = 8 DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))
@ -51,9 +59,12 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0)) input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0)) input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0)) input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_0_axis_tready = Signal(bool(0)) output_0_axis_tready = Signal(bool(0))
output_1_axis_tready = Signal(bool(0)) output_1_axis_tready = Signal(bool(0))
@ -67,21 +78,33 @@ def bench():
input_axis_tready = Signal(bool(0)) input_axis_tready = Signal(bool(0))
output_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_0_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_0_axis_tvalid = Signal(bool(0)) output_0_axis_tvalid = Signal(bool(0))
output_0_axis_tlast = Signal(bool(0)) output_0_axis_tlast = Signal(bool(0))
output_0_axis_tuser = Signal(bool(0)) output_0_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_0_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_0_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_1_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_1_axis_tvalid = Signal(bool(0)) output_1_axis_tvalid = Signal(bool(0))
output_1_axis_tlast = Signal(bool(0)) output_1_axis_tlast = Signal(bool(0))
output_1_axis_tuser = Signal(bool(0)) output_1_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_1_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_1_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_2_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_2_axis_tvalid = Signal(bool(0)) output_2_axis_tvalid = Signal(bool(0))
output_2_axis_tlast = Signal(bool(0)) output_2_axis_tlast = Signal(bool(0))
output_2_axis_tuser = Signal(bool(0)) output_2_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_2_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_2_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_3_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_3_axis_tvalid = Signal(bool(0)) output_3_axis_tvalid = Signal(bool(0))
output_3_axis_tlast = Signal(bool(0)) output_3_axis_tlast = Signal(bool(0))
output_3_axis_tuser = Signal(bool(0)) output_3_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_3_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_3_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks # sources and sinks
source_pause = Signal(bool(0)) source_pause = Signal(bool(0))
@ -96,9 +119,12 @@ def bench():
clk, clk,
rst, rst,
tdata=input_axis_tdata, tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid, tvalid=input_axis_tvalid,
tready=input_axis_tready, tready=input_axis_tready,
tlast=input_axis_tlast, tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser, tuser=input_axis_tuser,
pause=source_pause, pause=source_pause,
name='source' name='source'
@ -110,9 +136,12 @@ def bench():
clk, clk,
rst, rst,
tdata=output_0_axis_tdata, tdata=output_0_axis_tdata,
tkeep=output_0_axis_tkeep,
tvalid=output_0_axis_tvalid, tvalid=output_0_axis_tvalid,
tready=output_0_axis_tready, tready=output_0_axis_tready,
tlast=output_0_axis_tlast, tlast=output_0_axis_tlast,
tid=output_0_axis_tid,
tdest=output_0_axis_tdest,
tuser=output_0_axis_tuser, tuser=output_0_axis_tuser,
pause=sink_0_pause, pause=sink_0_pause,
name='sink_0' name='sink_0'
@ -124,9 +153,12 @@ def bench():
clk, clk,
rst, rst,
tdata=output_1_axis_tdata, tdata=output_1_axis_tdata,
tkeep=output_1_axis_tkeep,
tvalid=output_1_axis_tvalid, tvalid=output_1_axis_tvalid,
tready=output_1_axis_tready, tready=output_1_axis_tready,
tlast=output_1_axis_tlast, tlast=output_1_axis_tlast,
tid=output_1_axis_tid,
tdest=output_1_axis_tdest,
tuser=output_1_axis_tuser, tuser=output_1_axis_tuser,
pause=sink_1_pause, pause=sink_1_pause,
name='sink_1' name='sink_1'
@ -138,9 +170,12 @@ def bench():
clk, clk,
rst, rst,
tdata=output_2_axis_tdata, tdata=output_2_axis_tdata,
tkeep=output_2_axis_tkeep,
tvalid=output_2_axis_tvalid, tvalid=output_2_axis_tvalid,
tready=output_2_axis_tready, tready=output_2_axis_tready,
tlast=output_2_axis_tlast, tlast=output_2_axis_tlast,
tid=output_2_axis_tid,
tdest=output_2_axis_tdest,
tuser=output_2_axis_tuser, tuser=output_2_axis_tuser,
pause=sink_2_pause, pause=sink_2_pause,
name='sink_2' name='sink_2'
@ -152,9 +187,12 @@ def bench():
clk, clk,
rst, rst,
tdata=output_3_axis_tdata, tdata=output_3_axis_tdata,
tkeep=output_3_axis_tkeep,
tvalid=output_3_axis_tvalid, tvalid=output_3_axis_tvalid,
tready=output_3_axis_tready, tready=output_3_axis_tready,
tlast=output_3_axis_tlast, tlast=output_3_axis_tlast,
tid=output_3_axis_tid,
tdest=output_3_axis_tdest,
tuser=output_3_axis_tuser, tuser=output_3_axis_tuser,
pause=sink_3_pause, pause=sink_3_pause,
name='sink_3' name='sink_3'
@ -171,30 +209,45 @@ def bench():
current_test=current_test, current_test=current_test,
input_axis_tdata=input_axis_tdata, input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid, input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready, input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast, input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser, input_axis_tuser=input_axis_tuser,
output_0_axis_tdata=output_0_axis_tdata, output_0_axis_tdata=output_0_axis_tdata,
output_0_axis_tkeep=output_0_axis_tkeep,
output_0_axis_tvalid=output_0_axis_tvalid, output_0_axis_tvalid=output_0_axis_tvalid,
output_0_axis_tready=output_0_axis_tready, output_0_axis_tready=output_0_axis_tready,
output_0_axis_tlast=output_0_axis_tlast, output_0_axis_tlast=output_0_axis_tlast,
output_0_axis_tid=output_0_axis_tid,
output_0_axis_tdest=output_0_axis_tdest,
output_0_axis_tuser=output_0_axis_tuser, output_0_axis_tuser=output_0_axis_tuser,
output_1_axis_tdata=output_1_axis_tdata, output_1_axis_tdata=output_1_axis_tdata,
output_1_axis_tkeep=output_1_axis_tkeep,
output_1_axis_tvalid=output_1_axis_tvalid, output_1_axis_tvalid=output_1_axis_tvalid,
output_1_axis_tready=output_1_axis_tready, output_1_axis_tready=output_1_axis_tready,
output_1_axis_tlast=output_1_axis_tlast, output_1_axis_tlast=output_1_axis_tlast,
output_1_axis_tid=output_1_axis_tid,
output_1_axis_tdest=output_1_axis_tdest,
output_1_axis_tuser=output_1_axis_tuser, output_1_axis_tuser=output_1_axis_tuser,
output_2_axis_tdata=output_2_axis_tdata, output_2_axis_tdata=output_2_axis_tdata,
output_2_axis_tkeep=output_2_axis_tkeep,
output_2_axis_tvalid=output_2_axis_tvalid, output_2_axis_tvalid=output_2_axis_tvalid,
output_2_axis_tready=output_2_axis_tready, output_2_axis_tready=output_2_axis_tready,
output_2_axis_tlast=output_2_axis_tlast, output_2_axis_tlast=output_2_axis_tlast,
output_2_axis_tid=output_2_axis_tid,
output_2_axis_tdest=output_2_axis_tdest,
output_2_axis_tuser=output_2_axis_tuser, output_2_axis_tuser=output_2_axis_tuser,
output_3_axis_tdata=output_3_axis_tdata, output_3_axis_tdata=output_3_axis_tdata,
output_3_axis_tkeep=output_3_axis_tkeep,
output_3_axis_tvalid=output_3_axis_tvalid, output_3_axis_tvalid=output_3_axis_tvalid,
output_3_axis_tready=output_3_axis_tready, output_3_axis_tready=output_3_axis_tready,
output_3_axis_tlast=output_3_axis_tlast, output_3_axis_tlast=output_3_axis_tlast,
output_3_axis_tid=output_3_axis_tid,
output_3_axis_tdest=output_3_axis_tdest,
output_3_axis_tuser=output_3_axis_tuser, output_3_axis_tuser=output_3_axis_tuser,
enable=enable, enable=enable,
@ -225,10 +278,15 @@ def bench():
select.next = 0 select.next = 0
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
source.send(test_frame) source.send(test_frame)
yield clk.posedge yield clk.posedge
@ -249,10 +307,15 @@ def bench():
select.next = 1 select.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=2,
dest=1
)
source.send(test_frame) source.send(test_frame)
yield clk.posedge yield clk.posedge
@ -273,14 +336,23 @@ def bench():
select.next = 0 select.next = 0
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=3,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=2
)
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -306,14 +378,23 @@ def bench():
select.next = 1 select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=4,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2
)
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -340,14 +421,23 @@ def bench():
select.next = 1 select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=5,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2
)
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -379,14 +469,23 @@ def bench():
select.next = 1 select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=6,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge

73
lib/axis/tb/test_axis_demux_4.v
View File

@ -33,6 +33,14 @@ module test_axis_demux_4;
// Parameters // Parameters
parameter DATA_WIDTH = 8; parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -40,9 +48,12 @@ reg rst = 0;
reg [7:0] current_test = 0; reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0; reg input_axis_tvalid = 0;
reg input_axis_tlast = 0; reg input_axis_tlast = 0;
reg input_axis_tuser = 0; reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_0_axis_tready = 0; reg output_0_axis_tready = 0;
reg output_1_axis_tready = 0; reg output_1_axis_tready = 0;
@ -56,21 +67,33 @@ reg [1:0] select = 0;
wire input_axis_tready; wire input_axis_tready;
wire [DATA_WIDTH-1:0] output_0_axis_tdata; wire [DATA_WIDTH-1:0] output_0_axis_tdata;
wire [KEEP_WIDTH-1:0] output_0_axis_tkeep;
wire output_0_axis_tvalid; wire output_0_axis_tvalid;
wire output_0_axis_tlast; wire output_0_axis_tlast;
wire output_0_axis_tuser; wire [ID_WIDTH-1:0] output_0_axis_tid;
wire [DEST_WIDTH-1:0] output_0_axis_tdest;
wire [USER_WIDTH-1:0] output_0_axis_tuser;
wire [DATA_WIDTH-1:0] output_1_axis_tdata; wire [DATA_WIDTH-1:0] output_1_axis_tdata;
wire [KEEP_WIDTH-1:0] output_1_axis_tkeep;
wire output_1_axis_tvalid; wire output_1_axis_tvalid;
wire output_1_axis_tlast; wire output_1_axis_tlast;
wire output_1_axis_tuser; wire [ID_WIDTH-1:0] output_1_axis_tid;
wire [DEST_WIDTH-1:0] output_1_axis_tdest;
wire [USER_WIDTH-1:0] output_1_axis_tuser;
wire [DATA_WIDTH-1:0] output_2_axis_tdata; wire [DATA_WIDTH-1:0] output_2_axis_tdata;
wire [KEEP_WIDTH-1:0] output_2_axis_tkeep;
wire output_2_axis_tvalid; wire output_2_axis_tvalid;
wire output_2_axis_tlast; wire output_2_axis_tlast;
wire output_2_axis_tuser; wire [ID_WIDTH-1:0] output_2_axis_tid;
wire [DEST_WIDTH-1:0] output_2_axis_tdest;
wire [USER_WIDTH-1:0] output_2_axis_tuser;
wire [DATA_WIDTH-1:0] output_3_axis_tdata; wire [DATA_WIDTH-1:0] output_3_axis_tdata;
wire [KEEP_WIDTH-1:0] output_3_axis_tkeep;
wire output_3_axis_tvalid; wire output_3_axis_tvalid;
wire output_3_axis_tlast; wire output_3_axis_tlast;
wire output_3_axis_tuser; wire [ID_WIDTH-1:0] output_3_axis_tid;
wire [DEST_WIDTH-1:0] output_3_axis_tdest;
wire [USER_WIDTH-1:0] output_3_axis_tuser;
initial begin initial begin
// myhdl integration // myhdl integration
@ -79,8 +102,11 @@ initial begin
rst, rst,
current_test, current_test,
input_axis_tdata, input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid, input_axis_tvalid,
input_axis_tlast, input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser, input_axis_tuser,
output_0_axis_tready, output_0_axis_tready,
output_1_axis_tready, output_1_axis_tready,
@ -92,20 +118,32 @@ initial begin
$to_myhdl( $to_myhdl(
input_axis_tready, input_axis_tready,
output_0_axis_tdata, output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid, output_0_axis_tvalid,
output_0_axis_tlast, output_0_axis_tlast,
output_0_axis_tid,
output_0_axis_tdest,
output_0_axis_tuser, output_0_axis_tuser,
output_1_axis_tdata, output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid, output_1_axis_tvalid,
output_1_axis_tlast, output_1_axis_tlast,
output_1_axis_tid,
output_1_axis_tdest,
output_1_axis_tuser, output_1_axis_tuser,
output_2_axis_tdata, output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid, output_2_axis_tvalid,
output_2_axis_tlast, output_2_axis_tlast,
output_2_axis_tid,
output_2_axis_tdest,
output_2_axis_tuser, output_2_axis_tuser,
output_3_axis_tdata, output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid, output_3_axis_tvalid,
output_3_axis_tlast, output_3_axis_tlast,
output_3_axis_tid,
output_3_axis_tdest,
output_3_axis_tuser output_3_axis_tuser
); );
@ -115,37 +153,60 @@ initial begin
end end
axis_demux_4 #( axis_demux_4 #(
.DATA_WIDTH(DATA_WIDTH) .DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) )
UUT ( UUT (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
// AXI input // AXI input
.input_axis_tdata(input_axis_tdata), .input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid), .input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready), .input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast), .input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser), .input_axis_tuser(input_axis_tuser),
// AXI outputs // AXI outputs
.output_0_axis_tdata(output_0_axis_tdata), .output_0_axis_tdata(output_0_axis_tdata),
.output_0_axis_tkeep(output_0_axis_tkeep),
.output_0_axis_tvalid(output_0_axis_tvalid), .output_0_axis_tvalid(output_0_axis_tvalid),
.output_0_axis_tready(output_0_axis_tready), .output_0_axis_tready(output_0_axis_tready),
.output_0_axis_tlast(output_0_axis_tlast), .output_0_axis_tlast(output_0_axis_tlast),
.output_0_axis_tid(output_0_axis_tid),
.output_0_axis_tdest(output_0_axis_tdest),
.output_0_axis_tuser(output_0_axis_tuser), .output_0_axis_tuser(output_0_axis_tuser),
.output_1_axis_tdata(output_1_axis_tdata), .output_1_axis_tdata(output_1_axis_tdata),
.output_1_axis_tkeep(output_1_axis_tkeep),
.output_1_axis_tvalid(output_1_axis_tvalid), .output_1_axis_tvalid(output_1_axis_tvalid),
.output_1_axis_tready(output_1_axis_tready), .output_1_axis_tready(output_1_axis_tready),
.output_1_axis_tlast(output_1_axis_tlast), .output_1_axis_tlast(output_1_axis_tlast),
.output_1_axis_tid(output_1_axis_tid),
.output_1_axis_tdest(output_1_axis_tdest),
.output_1_axis_tuser(output_1_axis_tuser), .output_1_axis_tuser(output_1_axis_tuser),
.output_2_axis_tdata(output_2_axis_tdata), .output_2_axis_tdata(output_2_axis_tdata),
.output_2_axis_tkeep(output_2_axis_tkeep),
.output_2_axis_tvalid(output_2_axis_tvalid), .output_2_axis_tvalid(output_2_axis_tvalid),
.output_2_axis_tready(output_2_axis_tready), .output_2_axis_tready(output_2_axis_tready),
.output_2_axis_tlast(output_2_axis_tlast), .output_2_axis_tlast(output_2_axis_tlast),
.output_2_axis_tid(output_2_axis_tid),
.output_2_axis_tdest(output_2_axis_tdest),
.output_2_axis_tuser(output_2_axis_tuser), .output_2_axis_tuser(output_2_axis_tuser),
.output_3_axis_tdata(output_3_axis_tdata), .output_3_axis_tdata(output_3_axis_tdata),
.output_3_axis_tkeep(output_3_axis_tkeep),
.output_3_axis_tvalid(output_3_axis_tvalid), .output_3_axis_tvalid(output_3_axis_tvalid),
.output_3_axis_tready(output_3_axis_tready), .output_3_axis_tready(output_3_axis_tready),
.output_3_axis_tlast(output_3_axis_tlast), .output_3_axis_tlast(output_3_axis_tlast),
.output_3_axis_tid(output_3_axis_tid),
.output_3_axis_tdest(output_3_axis_tdest),
.output_3_axis_tuser(output_3_axis_tuser), .output_3_axis_tuser(output_3_axis_tuser),
// Control // Control
.enable(enable), .enable(enable),

187
lib/axis/tb/test_axis_demux_64_4.py → lib/axis/tb/test_axis_demux_4_64.py
View File

@ -28,8 +28,8 @@ import os
import axis_ep import axis_ep
module = 'axis_demux_64_4' module = 'axis_demux_4'
testbench = 'test_%s' % module testbench = 'test_%s_64' % module
srcs = [] srcs = []
@ -44,7 +44,14 @@ def bench():
# Parameters # Parameters
DATA_WIDTH = 64 DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8) KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))
@ -52,10 +59,12 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0)) input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0)) input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0)) input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_0_axis_tready = Signal(bool(0)) output_0_axis_tready = Signal(bool(0))
output_1_axis_tready = Signal(bool(0)) output_1_axis_tready = Signal(bool(0))
@ -69,25 +78,33 @@ def bench():
input_axis_tready = Signal(bool(0)) input_axis_tready = Signal(bool(0))
output_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_0_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) output_0_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_0_axis_tvalid = Signal(bool(0)) output_0_axis_tvalid = Signal(bool(0))
output_0_axis_tlast = Signal(bool(0)) output_0_axis_tlast = Signal(bool(0))
output_0_axis_tuser = Signal(bool(0)) output_0_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_0_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_0_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_1_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) output_1_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_1_axis_tvalid = Signal(bool(0)) output_1_axis_tvalid = Signal(bool(0))
output_1_axis_tlast = Signal(bool(0)) output_1_axis_tlast = Signal(bool(0))
output_1_axis_tuser = Signal(bool(0)) output_1_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_1_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_1_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_2_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) output_2_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_2_axis_tvalid = Signal(bool(0)) output_2_axis_tvalid = Signal(bool(0))
output_2_axis_tlast = Signal(bool(0)) output_2_axis_tlast = Signal(bool(0))
output_2_axis_tuser = Signal(bool(0)) output_2_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_2_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_2_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_3_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) output_3_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_3_axis_tvalid = Signal(bool(0)) output_3_axis_tvalid = Signal(bool(0))
output_3_axis_tlast = Signal(bool(0)) output_3_axis_tlast = Signal(bool(0))
output_3_axis_tuser = Signal(bool(0)) output_3_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_3_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_3_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks # sources and sinks
source_pause = Signal(bool(0)) source_pause = Signal(bool(0))
@ -106,6 +123,8 @@ def bench():
tvalid=input_axis_tvalid, tvalid=input_axis_tvalid,
tready=input_axis_tready, tready=input_axis_tready,
tlast=input_axis_tlast, tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser, tuser=input_axis_tuser,
pause=source_pause, pause=source_pause,
name='source' name='source'
@ -121,6 +140,8 @@ def bench():
tvalid=output_0_axis_tvalid, tvalid=output_0_axis_tvalid,
tready=output_0_axis_tready, tready=output_0_axis_tready,
tlast=output_0_axis_tlast, tlast=output_0_axis_tlast,
tid=output_0_axis_tid,
tdest=output_0_axis_tdest,
tuser=output_0_axis_tuser, tuser=output_0_axis_tuser,
pause=sink_0_pause, pause=sink_0_pause,
name='sink_0' name='sink_0'
@ -136,6 +157,8 @@ def bench():
tvalid=output_1_axis_tvalid, tvalid=output_1_axis_tvalid,
tready=output_1_axis_tready, tready=output_1_axis_tready,
tlast=output_1_axis_tlast, tlast=output_1_axis_tlast,
tid=output_1_axis_tid,
tdest=output_1_axis_tdest,
tuser=output_1_axis_tuser, tuser=output_1_axis_tuser,
pause=sink_1_pause, pause=sink_1_pause,
name='sink_1' name='sink_1'
@ -151,6 +174,8 @@ def bench():
tvalid=output_2_axis_tvalid, tvalid=output_2_axis_tvalid,
tready=output_2_axis_tready, tready=output_2_axis_tready,
tlast=output_2_axis_tlast, tlast=output_2_axis_tlast,
tid=output_2_axis_tid,
tdest=output_2_axis_tdest,
tuser=output_2_axis_tuser, tuser=output_2_axis_tuser,
pause=sink_2_pause, pause=sink_2_pause,
name='sink_2' name='sink_2'
@ -166,6 +191,8 @@ def bench():
tvalid=output_3_axis_tvalid, tvalid=output_3_axis_tvalid,
tready=output_3_axis_tready, tready=output_3_axis_tready,
tlast=output_3_axis_tlast, tlast=output_3_axis_tlast,
tid=output_3_axis_tid,
tdest=output_3_axis_tdest,
tuser=output_3_axis_tuser, tuser=output_3_axis_tuser,
pause=sink_3_pause, pause=sink_3_pause,
name='sink_3' name='sink_3'
@ -186,6 +213,8 @@ def bench():
input_axis_tvalid=input_axis_tvalid, input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready, input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast, input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser, input_axis_tuser=input_axis_tuser,
output_0_axis_tdata=output_0_axis_tdata, output_0_axis_tdata=output_0_axis_tdata,
@ -193,24 +222,32 @@ def bench():
output_0_axis_tvalid=output_0_axis_tvalid, output_0_axis_tvalid=output_0_axis_tvalid,
output_0_axis_tready=output_0_axis_tready, output_0_axis_tready=output_0_axis_tready,
output_0_axis_tlast=output_0_axis_tlast, output_0_axis_tlast=output_0_axis_tlast,
output_0_axis_tid=output_0_axis_tid,
output_0_axis_tdest=output_0_axis_tdest,
output_0_axis_tuser=output_0_axis_tuser, output_0_axis_tuser=output_0_axis_tuser,
output_1_axis_tdata=output_1_axis_tdata, output_1_axis_tdata=output_1_axis_tdata,
output_1_axis_tkeep=output_1_axis_tkeep, output_1_axis_tkeep=output_1_axis_tkeep,
output_1_axis_tvalid=output_1_axis_tvalid, output_1_axis_tvalid=output_1_axis_tvalid,
output_1_axis_tready=output_1_axis_tready, output_1_axis_tready=output_1_axis_tready,
output_1_axis_tlast=output_1_axis_tlast, output_1_axis_tlast=output_1_axis_tlast,
output_1_axis_tid=output_1_axis_tid,
output_1_axis_tdest=output_1_axis_tdest,
output_1_axis_tuser=output_1_axis_tuser, output_1_axis_tuser=output_1_axis_tuser,
output_2_axis_tdata=output_2_axis_tdata, output_2_axis_tdata=output_2_axis_tdata,
output_2_axis_tkeep=output_2_axis_tkeep, output_2_axis_tkeep=output_2_axis_tkeep,
output_2_axis_tvalid=output_2_axis_tvalid, output_2_axis_tvalid=output_2_axis_tvalid,
output_2_axis_tready=output_2_axis_tready, output_2_axis_tready=output_2_axis_tready,
output_2_axis_tlast=output_2_axis_tlast, output_2_axis_tlast=output_2_axis_tlast,
output_2_axis_tid=output_2_axis_tid,
output_2_axis_tdest=output_2_axis_tdest,
output_2_axis_tuser=output_2_axis_tuser, output_2_axis_tuser=output_2_axis_tuser,
output_3_axis_tdata=output_3_axis_tdata, output_3_axis_tdata=output_3_axis_tdata,
output_3_axis_tkeep=output_3_axis_tkeep, output_3_axis_tkeep=output_3_axis_tkeep,
output_3_axis_tvalid=output_3_axis_tvalid, output_3_axis_tvalid=output_3_axis_tvalid,
output_3_axis_tready=output_3_axis_tready, output_3_axis_tready=output_3_axis_tready,
output_3_axis_tlast=output_3_axis_tlast, output_3_axis_tlast=output_3_axis_tlast,
output_3_axis_tid=output_3_axis_tid,
output_3_axis_tdest=output_3_axis_tdest,
output_3_axis_tuser=output_3_axis_tuser, output_3_axis_tuser=output_3_axis_tuser,
enable=enable, enable=enable,
@ -241,10 +278,15 @@ def bench():
select.next = 0 select.next = 0
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
source.send(test_frame) source.send(test_frame)
yield clk.posedge yield clk.posedge
@ -265,10 +307,15 @@ def bench():
select.next = 1 select.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=2,
dest=1
)
source.send(test_frame) source.send(test_frame)
yield clk.posedge yield clk.posedge
@ -289,14 +336,23 @@ def bench():
select.next = 0 select.next = 0
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=3,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=2
)
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -322,14 +378,23 @@ def bench():
select.next = 1 select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=4,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2
)
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -356,14 +421,23 @@ def bench():
select.next = 1 select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=5,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2
)
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -395,14 +469,23 @@ def bench():
select.next = 1 select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=6,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge

66
lib/axis/tb/test_axis_demux_64_4.v → lib/axis/tb/test_axis_demux_4_64.v
View File

@ -27,13 +27,20 @@ THE SOFTWARE.
`timescale 1ns / 1ps `timescale 1ns / 1ps
/* /*
* Testbench for axis_demux_64_4 * Testbench for axis_demux_4
*/ */
module test_axis_demux_64_4; module test_axis_demux_4_64;
// Parameters // Parameters
parameter DATA_WIDTH = 64; parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8); parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -44,7 +51,9 @@ reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0; reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0; reg input_axis_tvalid = 0;
reg input_axis_tlast = 0; reg input_axis_tlast = 0;
reg input_axis_tuser = 0; reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_0_axis_tready = 0; reg output_0_axis_tready = 0;
reg output_1_axis_tready = 0; reg output_1_axis_tready = 0;
@ -61,22 +70,30 @@ wire [DATA_WIDTH-1:0] output_0_axis_tdata;
wire [KEEP_WIDTH-1:0] output_0_axis_tkeep; wire [KEEP_WIDTH-1:0] output_0_axis_tkeep;
wire output_0_axis_tvalid; wire output_0_axis_tvalid;
wire output_0_axis_tlast; wire output_0_axis_tlast;
wire output_0_axis_tuser; wire [ID_WIDTH-1:0] output_0_axis_tid;
wire [DEST_WIDTH-1:0] output_0_axis_tdest;
wire [USER_WIDTH-1:0] output_0_axis_tuser;
wire [DATA_WIDTH-1:0] output_1_axis_tdata; wire [DATA_WIDTH-1:0] output_1_axis_tdata;
wire [KEEP_WIDTH-1:0] output_1_axis_tkeep; wire [KEEP_WIDTH-1:0] output_1_axis_tkeep;
wire output_1_axis_tvalid; wire output_1_axis_tvalid;
wire output_1_axis_tlast; wire output_1_axis_tlast;
wire output_1_axis_tuser; wire [ID_WIDTH-1:0] output_1_axis_tid;
wire [DEST_WIDTH-1:0] output_1_axis_tdest;
wire [USER_WIDTH-1:0] output_1_axis_tuser;
wire [DATA_WIDTH-1:0] output_2_axis_tdata; wire [DATA_WIDTH-1:0] output_2_axis_tdata;
wire [KEEP_WIDTH-1:0] output_2_axis_tkeep; wire [KEEP_WIDTH-1:0] output_2_axis_tkeep;
wire output_2_axis_tvalid; wire output_2_axis_tvalid;
wire output_2_axis_tlast; wire output_2_axis_tlast;
wire output_2_axis_tuser; wire [ID_WIDTH-1:0] output_2_axis_tid;
wire [DEST_WIDTH-1:0] output_2_axis_tdest;
wire [USER_WIDTH-1:0] output_2_axis_tuser;
wire [DATA_WIDTH-1:0] output_3_axis_tdata; wire [DATA_WIDTH-1:0] output_3_axis_tdata;
wire [KEEP_WIDTH-1:0] output_3_axis_tkeep; wire [KEEP_WIDTH-1:0] output_3_axis_tkeep;
wire output_3_axis_tvalid; wire output_3_axis_tvalid;
wire output_3_axis_tlast; wire output_3_axis_tlast;
wire output_3_axis_tuser; wire [ID_WIDTH-1:0] output_3_axis_tid;
wire [DEST_WIDTH-1:0] output_3_axis_tdest;
wire [USER_WIDTH-1:0] output_3_axis_tuser;
initial begin initial begin
// myhdl integration // myhdl integration
@ -88,6 +105,8 @@ initial begin
input_axis_tkeep, input_axis_tkeep,
input_axis_tvalid, input_axis_tvalid,
input_axis_tlast, input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser, input_axis_tuser,
output_0_axis_tready, output_0_axis_tready,
output_1_axis_tready, output_1_axis_tready,
@ -102,32 +121,47 @@ initial begin
output_0_axis_tkeep, output_0_axis_tkeep,
output_0_axis_tvalid, output_0_axis_tvalid,
output_0_axis_tlast, output_0_axis_tlast,
output_0_axis_tid,
output_0_axis_tdest,
output_0_axis_tuser, output_0_axis_tuser,
output_1_axis_tdata, output_1_axis_tdata,
output_1_axis_tkeep, output_1_axis_tkeep,
output_1_axis_tvalid, output_1_axis_tvalid,
output_1_axis_tlast, output_1_axis_tlast,
output_1_axis_tid,
output_1_axis_tdest,
output_1_axis_tuser, output_1_axis_tuser,
output_2_axis_tdata, output_2_axis_tdata,
output_2_axis_tkeep, output_2_axis_tkeep,
output_2_axis_tvalid, output_2_axis_tvalid,
output_2_axis_tlast, output_2_axis_tlast,
output_2_axis_tid,
output_2_axis_tdest,
output_2_axis_tuser, output_2_axis_tuser,
output_3_axis_tdata, output_3_axis_tdata,
output_3_axis_tkeep, output_3_axis_tkeep,
output_3_axis_tvalid, output_3_axis_tvalid,
output_3_axis_tlast, output_3_axis_tlast,
output_3_axis_tid,
output_3_axis_tdest,
output_3_axis_tuser output_3_axis_tuser
); );
// dump file // dump file
$dumpfile("test_axis_demux_64_4.lxt"); $dumpfile("test_axis_demux_4_64.lxt");
$dumpvars(0, test_axis_demux_64_4); $dumpvars(0, test_axis_demux_4_64);
end end
axis_demux_64_4 #( axis_demux_4 #(
.DATA_WIDTH(DATA_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH) .KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) )
UUT ( UUT (
.clk(clk), .clk(clk),
@ -138,6 +172,8 @@ UUT (
.input_axis_tvalid(input_axis_tvalid), .input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready), .input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast), .input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser), .input_axis_tuser(input_axis_tuser),
// AXI outputs // AXI outputs
.output_0_axis_tdata(output_0_axis_tdata), .output_0_axis_tdata(output_0_axis_tdata),
@ -145,24 +181,32 @@ UUT (
.output_0_axis_tvalid(output_0_axis_tvalid), .output_0_axis_tvalid(output_0_axis_tvalid),
.output_0_axis_tready(output_0_axis_tready), .output_0_axis_tready(output_0_axis_tready),
.output_0_axis_tlast(output_0_axis_tlast), .output_0_axis_tlast(output_0_axis_tlast),
.output_0_axis_tid(output_0_axis_tid),
.output_0_axis_tdest(output_0_axis_tdest),
.output_0_axis_tuser(output_0_axis_tuser), .output_0_axis_tuser(output_0_axis_tuser),
.output_1_axis_tdata(output_1_axis_tdata), .output_1_axis_tdata(output_1_axis_tdata),
.output_1_axis_tkeep(output_1_axis_tkeep), .output_1_axis_tkeep(output_1_axis_tkeep),
.output_1_axis_tvalid(output_1_axis_tvalid), .output_1_axis_tvalid(output_1_axis_tvalid),
.output_1_axis_tready(output_1_axis_tready), .output_1_axis_tready(output_1_axis_tready),
.output_1_axis_tlast(output_1_axis_tlast), .output_1_axis_tlast(output_1_axis_tlast),
.output_1_axis_tid(output_1_axis_tid),
.output_1_axis_tdest(output_1_axis_tdest),
.output_1_axis_tuser(output_1_axis_tuser), .output_1_axis_tuser(output_1_axis_tuser),
.output_2_axis_tdata(output_2_axis_tdata), .output_2_axis_tdata(output_2_axis_tdata),
.output_2_axis_tkeep(output_2_axis_tkeep), .output_2_axis_tkeep(output_2_axis_tkeep),
.output_2_axis_tvalid(output_2_axis_tvalid), .output_2_axis_tvalid(output_2_axis_tvalid),
.output_2_axis_tready(output_2_axis_tready), .output_2_axis_tready(output_2_axis_tready),
.output_2_axis_tlast(output_2_axis_tlast), .output_2_axis_tlast(output_2_axis_tlast),
.output_2_axis_tid(output_2_axis_tid),
.output_2_axis_tdest(output_2_axis_tdest),
.output_2_axis_tuser(output_2_axis_tuser), .output_2_axis_tuser(output_2_axis_tuser),
.output_3_axis_tdata(output_3_axis_tdata), .output_3_axis_tdata(output_3_axis_tdata),
.output_3_axis_tkeep(output_3_axis_tkeep), .output_3_axis_tkeep(output_3_axis_tkeep),
.output_3_axis_tvalid(output_3_axis_tvalid), .output_3_axis_tvalid(output_3_axis_tvalid),
.output_3_axis_tready(output_3_axis_tready), .output_3_axis_tready(output_3_axis_tready),
.output_3_axis_tlast(output_3_axis_tlast), .output_3_axis_tlast(output_3_axis_tlast),
.output_3_axis_tid(output_3_axis_tid),
.output_3_axis_tdest(output_3_axis_tdest),
.output_3_axis_tuser(output_3_axis_tuser), .output_3_axis_tuser(output_3_axis_tuser),
// Control // Control
.enable(enable), .enable(enable),

174
lib/axis/tb/test_axis_fifo.py
View File

@ -45,6 +45,15 @@ def bench():
# Parameters # Parameters
ADDR_WIDTH = 2 ADDR_WIDTH = 2
DATA_WIDTH = 8 DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
LAST_ENABLE = 1
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))
@ -52,17 +61,23 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0)) input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0)) input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0)) input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0)) output_axis_tready = Signal(bool(0))
# Outputs # Outputs
input_axis_tready = Signal(bool(0)) input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0)) output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0)) output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0)) output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks # sources and sinks
source_pause = Signal(bool(0)) source_pause = Signal(bool(0))
@ -74,9 +89,12 @@ def bench():
clk, clk,
rst, rst,
tdata=input_axis_tdata, tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid, tvalid=input_axis_tvalid,
tready=input_axis_tready, tready=input_axis_tready,
tlast=input_axis_tlast, tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser, tuser=input_axis_tuser,
pause=source_pause, pause=source_pause,
name='source' name='source'
@ -88,9 +106,12 @@ def bench():
clk, clk,
rst, rst,
tdata=output_axis_tdata, tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid, tvalid=output_axis_tvalid,
tready=output_axis_tready, tready=output_axis_tready,
tlast=output_axis_tlast, tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser, tuser=output_axis_tuser,
pause=sink_pause, pause=sink_pause,
name='sink' name='sink'
@ -107,15 +128,21 @@ def bench():
current_test=current_test, current_test=current_test,
input_axis_tdata=input_axis_tdata, input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid, input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready, input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast, input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser, input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata, output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid, output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready, output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast, output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser output_axis_tuser=output_axis_tuser
) )
@ -140,10 +167,15 @@ def bench():
print("test 1: test packet") print("test 1: test packet")
current_test.next = 1 current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
source.send(test_frame) source.send(test_frame)
yield clk.posedge yield clk.posedge
@ -161,10 +193,15 @@ def bench():
print("test 2: longer packet") print("test 2: longer packet")
current_test.next = 2 current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(256))) b'\x80\x00' +
bytearray(range(256)),
id=2,
dest=1
)
source.send(test_frame) source.send(test_frame)
yield clk.posedge yield clk.posedge
@ -180,10 +217,15 @@ def bench():
print("test 3: test packet with pauses") print("test 3: test packet with pauses")
current_test.next = 3 current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=1
)
source.send(test_frame) source.send(test_frame)
yield clk.posedge yield clk.posedge
@ -215,14 +257,23 @@ def bench():
print("test 4: back-to-back packets") print("test 4: back-to-back packets")
current_test.next = 4 current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=4,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2
)
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -247,14 +298,23 @@ def bench():
print("test 5: alternate pause source") print("test 5: alternate pause source")
current_test.next = 5 current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=5,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2
)
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -284,14 +344,23 @@ def bench():
print("test 6: alternate pause sink") print("test 6: alternate pause sink")
current_test.next = 6 current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=6,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -321,11 +390,16 @@ def bench():
print("test 7: tuser assert") print("test 7: tuser assert")
current_test.next = 7 current_test.next = 7
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame.user = 1 b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1,
last_cycle_user=1
)
source.send(test_frame) source.send(test_frame)
yield clk.posedge yield clk.posedge
@ -336,7 +410,7 @@ def bench():
rx_frame = sink.recv() rx_frame = sink.recv()
assert rx_frame == test_frame assert rx_frame == test_frame
assert rx_frame.user[-1] assert rx_frame.last_cycle_user
yield delay(100) yield delay(100)
@ -344,7 +418,11 @@ def bench():
print("test 8: initial sink pause") print("test 8: initial sink pause")
current_test.next = 8 current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03') test_frame = axis_ep.AXIStreamFrame(
b'\x01\x02\x03',
id=8,
dest=1
)
sink_pause.next = 1 sink_pause.next = 1
source.send(test_frame) source.send(test_frame)
@ -368,7 +446,11 @@ def bench():
print("test 9: initial sink pause, reset") print("test 9: initial sink pause, reset")
current_test.next = 9 current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03') test_frame = axis_ep.AXIStreamFrame(
b'\x01\x02\x03',
id=9,
dest=1
)
sink_pause.next = 1 sink_pause.next = 1
source.send(test_frame) source.send(test_frame)

42
lib/axis/tb/test_axis_fifo.v
View File

@ -34,6 +34,15 @@ module test_axis_fifo;
// Parameters // Parameters
parameter ADDR_WIDTH = 2; parameter ADDR_WIDTH = 2;
parameter DATA_WIDTH = 8; parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -41,17 +50,23 @@ reg rst = 0;
reg [7:0] current_test = 0; reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0; reg input_axis_tvalid = 0;
reg input_axis_tlast = 0; reg input_axis_tlast = 0;
reg input_axis_tuser = 0; reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_axis_tready = 0; reg output_axis_tready = 0;
// Outputs // Outputs
wire input_axis_tready; wire input_axis_tready;
wire [DATA_WIDTH-1:0] output_axis_tdata; wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid; wire output_axis_tvalid;
wire output_axis_tlast; wire output_axis_tlast;
wire output_axis_tuser; wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
initial begin initial begin
// myhdl integration // myhdl integration
@ -60,16 +75,22 @@ initial begin
rst, rst,
current_test, current_test,
input_axis_tdata, input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid, input_axis_tvalid,
input_axis_tlast, input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser, input_axis_tuser,
output_axis_tready output_axis_tready
); );
$to_myhdl( $to_myhdl(
input_axis_tready, input_axis_tready,
output_axis_tdata, output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid, output_axis_tvalid,
output_axis_tlast, output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser output_axis_tuser
); );
@ -80,22 +101,37 @@ end
axis_fifo #( axis_fifo #(
.ADDR_WIDTH(ADDR_WIDTH), .ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH) .DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) )
UUT ( UUT (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
// AXI input // AXI input
.input_axis_tdata(input_axis_tdata), .input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid), .input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready), .input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast), .input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser), .input_axis_tuser(input_axis_tuser),
// AXI output // AXI output
.output_axis_tdata(output_axis_tdata), .output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser) .output_axis_tuser(output_axis_tuser)
); );

175
lib/axis/tb/test_axis_fifo_64.py
View File

@ -28,8 +28,8 @@ import os
import axis_ep import axis_ep
module = 'axis_fifo_64' module = 'axis_fifo'
testbench = 'test_%s' % module testbench = 'test_%s_64' % module
srcs = [] srcs = []
@ -45,7 +45,15 @@ def bench():
# Parameters # Parameters
ADDR_WIDTH = 2 ADDR_WIDTH = 2
DATA_WIDTH = 64 DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8) KEEP_WIDTH = (DATA_WIDTH/8)
LAST_ENABLE = 1
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))
@ -53,19 +61,23 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0)) input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0)) input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0)) input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0)) output_axis_tready = Signal(bool(0))
# Outputs # Outputs
input_axis_tready = Signal(bool(0)) input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0)) output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0)) output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0)) output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks # sources and sinks
source_pause = Signal(bool(0)) source_pause = Signal(bool(0))
@ -81,6 +93,8 @@ def bench():
tvalid=input_axis_tvalid, tvalid=input_axis_tvalid,
tready=input_axis_tready, tready=input_axis_tready,
tlast=input_axis_tlast, tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser, tuser=input_axis_tuser,
pause=source_pause, pause=source_pause,
name='source' name='source'
@ -96,6 +110,8 @@ def bench():
tvalid=output_axis_tvalid, tvalid=output_axis_tvalid,
tready=output_axis_tready, tready=output_axis_tready,
tlast=output_axis_tlast, tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser, tuser=output_axis_tuser,
pause=sink_pause, pause=sink_pause,
name='sink' name='sink'
@ -116,6 +132,8 @@ def bench():
input_axis_tvalid=input_axis_tvalid, input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready, input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast, input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser, input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata, output_axis_tdata=output_axis_tdata,
@ -123,6 +141,8 @@ def bench():
output_axis_tvalid=output_axis_tvalid, output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready, output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast, output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser output_axis_tuser=output_axis_tuser
) )
@ -147,10 +167,15 @@ def bench():
print("test 1: test packet") print("test 1: test packet")
current_test.next = 1 current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
source.send(test_frame) source.send(test_frame)
yield clk.posedge yield clk.posedge
@ -168,10 +193,15 @@ def bench():
print("test 2: longer packet") print("test 2: longer packet")
current_test.next = 2 current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(256))) b'\x80\x00' +
bytearray(range(256)),
id=2,
dest=1
)
source.send(test_frame) source.send(test_frame)
yield clk.posedge yield clk.posedge
@ -187,10 +217,15 @@ def bench():
print("test 3: test packet with pauses") print("test 3: test packet with pauses")
current_test.next = 3 current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(256))) b'\x80\x00' +
bytearray(range(256)),
id=3,
dest=1
)
source.send(test_frame) source.send(test_frame)
yield clk.posedge yield clk.posedge
@ -222,14 +257,23 @@ def bench():
print("test 4: back-to-back packets") print("test 4: back-to-back packets")
current_test.next = 4 current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=4,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2
)
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -254,14 +298,23 @@ def bench():
print("test 5: alternate pause source") print("test 5: alternate pause source")
current_test.next = 5 current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=5,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2
)
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -291,14 +344,23 @@ def bench():
print("test 6: alternate pause sink") print("test 6: alternate pause sink")
current_test.next = 6 current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=6,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -328,11 +390,16 @@ def bench():
print("test 7: tuser assert") print("test 7: tuser assert")
current_test.next = 7 current_test.next = 7
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame.user = 1 b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1,
last_cycle_user=1
)
source.send(test_frame) source.send(test_frame)
yield clk.posedge yield clk.posedge
@ -343,7 +410,7 @@ def bench():
rx_frame = sink.recv() rx_frame = sink.recv()
assert rx_frame == test_frame assert rx_frame == test_frame
assert rx_frame.user[-1] assert rx_frame.last_cycle_user
yield delay(100) yield delay(100)
@ -351,7 +418,11 @@ def bench():
print("test 8: initial sink pause") print("test 8: initial sink pause")
current_test.next = 8 current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24))) test_frame = axis_ep.AXIStreamFrame(
bytearray(range(24)),
id=8,
dest=1
)
sink_pause.next = 1 sink_pause.next = 1
source.send(test_frame) source.send(test_frame)
@ -375,7 +446,11 @@ def bench():
print("test 9: initial sink pause, reset") print("test 9: initial sink pause, reset")
current_test.next = 9 current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24))) test_frame = axis_ep.AXIStreamFrame(
bytearray(range(24)),
id=9,
dest=1
)
sink_pause.next = 1 sink_pause.next = 1
source.send(test_frame) source.send(test_frame)

39
lib/axis/tb/test_axis_fifo_64.v
View File

@ -27,14 +27,22 @@ THE SOFTWARE.
`timescale 1ns / 1ps `timescale 1ns / 1ps
/* /*
* Testbench for axis_fifo_64 * Testbench for axis_fifo
*/ */
module test_axis_fifo_64; module test_axis_fifo_64;
// Parameters // Parameters
parameter ADDR_WIDTH = 2; parameter ADDR_WIDTH = 2;
parameter DATA_WIDTH = 64; parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8); parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -45,7 +53,9 @@ reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0; reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0; reg input_axis_tvalid = 0;
reg input_axis_tlast = 0; reg input_axis_tlast = 0;
reg input_axis_tuser = 0; reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_axis_tready = 0; reg output_axis_tready = 0;
// Outputs // Outputs
@ -54,7 +64,9 @@ wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep; wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid; wire output_axis_tvalid;
wire output_axis_tlast; wire output_axis_tlast;
wire output_axis_tuser; wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
initial begin initial begin
// myhdl integration // myhdl integration
@ -66,6 +78,8 @@ initial begin
input_axis_tkeep, input_axis_tkeep,
input_axis_tvalid, input_axis_tvalid,
input_axis_tlast, input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser, input_axis_tuser,
output_axis_tready output_axis_tready
); );
@ -75,6 +89,8 @@ initial begin
output_axis_tkeep, output_axis_tkeep,
output_axis_tvalid, output_axis_tvalid,
output_axis_tlast, output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser output_axis_tuser
); );
@ -83,9 +99,18 @@ initial begin
$dumpvars(0, test_axis_fifo_64); $dumpvars(0, test_axis_fifo_64);
end end
axis_fifo_64 #( axis_fifo #(
.ADDR_WIDTH(ADDR_WIDTH), .ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH) .DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) )
UUT ( UUT (
.clk(clk), .clk(clk),
@ -96,6 +121,8 @@ UUT (
.input_axis_tvalid(input_axis_tvalid), .input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready), .input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast), .input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser), .input_axis_tuser(input_axis_tuser),
// AXI output // AXI output
.output_axis_tdata(output_axis_tdata), .output_axis_tdata(output_axis_tdata),
@ -103,6 +130,8 @@ UUT (
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser) .output_axis_tuser(output_axis_tuser)
); );

180
lib/axis/tb/test_axis_frame_fifo.py
View File

@ -45,6 +45,17 @@ def bench():
# Parameters # Parameters
ADDR_WIDTH = 9 ADDR_WIDTH = 9
DATA_WIDTH = 8 DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
USER_BAD_FRAME_VALUE = 1
USER_BAD_FRAME_MASK = 1
DROP_BAD_FRAME = 1
DROP_WHEN_FULL = 0 DROP_WHEN_FULL = 0
# Inputs # Inputs
@ -53,16 +64,23 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0)) input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0)) input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0)) input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0)) output_axis_tready = Signal(bool(0))
# Outputs # Outputs
input_axis_tready = Signal(bool(0)) input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0)) output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0)) output_axis_tlast = Signal(bool(0))
output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
overflow = Signal(bool(0)) overflow = Signal(bool(0))
bad_frame = Signal(bool(0)) bad_frame = Signal(bool(0))
good_frame = Signal(bool(0)) good_frame = Signal(bool(0))
@ -77,9 +95,12 @@ def bench():
clk, clk,
rst, rst,
tdata=input_axis_tdata, tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid, tvalid=input_axis_tvalid,
tready=input_axis_tready, tready=input_axis_tready,
tlast=input_axis_tlast, tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser, tuser=input_axis_tuser,
pause=source_pause, pause=source_pause,
name='source' name='source'
@ -91,9 +112,13 @@ def bench():
clk, clk,
rst, rst,
tdata=output_axis_tdata, tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid, tvalid=output_axis_tvalid,
tready=output_axis_tready, tready=output_axis_tready,
tlast=output_axis_tlast, tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser,
pause=sink_pause, pause=sink_pause,
name='sink' name='sink'
) )
@ -109,15 +134,22 @@ def bench():
current_test=current_test, current_test=current_test,
input_axis_tdata=input_axis_tdata, input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid, input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready, input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast, input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser, input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata, output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid, output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready, output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast, output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser,
overflow=overflow, overflow=overflow,
bad_frame=bad_frame, bad_frame=bad_frame,
@ -158,10 +190,14 @@ def bench():
print("test 1: test packet") print("test 1: test packet")
current_test.next = 1 current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
overflow_asserted.next = 0 overflow_asserted.next = 0
bad_frame_asserted.next = 0 bad_frame_asserted.next = 0
@ -188,10 +224,14 @@ def bench():
print("test 2: longer packet") print("test 2: longer packet")
current_test.next = 2 current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(256))) b'\x80\x00' +
bytearray(range(256)),
id=2,
dest=1
)
overflow_asserted.next = 0 overflow_asserted.next = 0
bad_frame_asserted.next = 0 bad_frame_asserted.next = 0
@ -216,10 +256,14 @@ def bench():
print("test 3: test packet with pauses") print("test 3: test packet with pauses")
current_test.next = 3 current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=1
)
overflow_asserted.next = 0 overflow_asserted.next = 0
bad_frame_asserted.next = 0 bad_frame_asserted.next = 0
@ -260,14 +304,22 @@ def bench():
print("test 4: back-to-back packets") print("test 4: back-to-back packets")
current_test.next = 4 current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=4,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2
)
overflow_asserted.next = 0 overflow_asserted.next = 0
bad_frame_asserted.next = 0 bad_frame_asserted.next = 0
@ -301,14 +353,22 @@ def bench():
print("test 5: alternate pause source") print("test 5: alternate pause source")
current_test.next = 5 current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=5,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2
)
overflow_asserted.next = 0 overflow_asserted.next = 0
bad_frame_asserted.next = 0 bad_frame_asserted.next = 0
@ -347,14 +407,22 @@ def bench():
print("test 6: alternate pause sink") print("test 6: alternate pause sink")
current_test.next = 6 current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=6,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
overflow_asserted.next = 0 overflow_asserted.next = 0
bad_frame_asserted.next = 0 bad_frame_asserted.next = 0
@ -393,11 +461,15 @@ def bench():
print("test 7: tuser assert") print("test 7: tuser assert")
current_test.next = 7 current_test.next = 7
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame.user = 1 b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1,
last_cycle_user=1
)
overflow_asserted.next = 0 overflow_asserted.next = 0
bad_frame_asserted.next = 0 bad_frame_asserted.next = 0
@ -420,10 +492,14 @@ def bench():
print("test 8: single packet overflow") print("test 8: single packet overflow")
current_test.next = 8 current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(256))*2) b'\x80\x00' +
bytearray(range(256))*2,
id=8,
dest=1
)
overflow_asserted.next = 0 overflow_asserted.next = 0
bad_frame_asserted.next = 0 bad_frame_asserted.next = 0
@ -446,7 +522,11 @@ def bench():
print("test 9: initial sink pause") print("test 9: initial sink pause")
current_test.next = 9 current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03') test_frame = axis_ep.AXIStreamFrame(
b'\x01\x02\x03',
id=9,
dest=1
)
sink_pause.next = 1 sink_pause.next = 1
source.send(test_frame) source.send(test_frame)
@ -470,7 +550,11 @@ def bench():
print("test 10: initial sink pause, reset") print("test 10: initial sink pause, reset")
current_test.next = 10 current_test.next = 10
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03') test_frame = axis_ep.AXIStreamFrame(
b'\x01\x02\x03',
id=10,
dest=1
)
sink_pause.next = 1 sink_pause.next = 1
source.send(test_frame) source.send(test_frame)

45
lib/axis/tb/test_axis_frame_fifo.v
View File

@ -34,6 +34,17 @@ module test_axis_frame_fifo;
// Parameters // Parameters
parameter ADDR_WIDTH = 9; parameter ADDR_WIDTH = 9;
parameter DATA_WIDTH = 8; parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 1;
parameter DROP_WHEN_FULL = 0; parameter DROP_WHEN_FULL = 0;
// Inputs // Inputs
@ -42,16 +53,23 @@ reg rst = 0;
reg [7:0] current_test = 0; reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0; reg input_axis_tvalid = 0;
reg input_axis_tlast = 0; reg input_axis_tlast = 0;
reg input_axis_tuser = 0; reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_axis_tready = 0; reg output_axis_tready = 0;
// Outputs // Outputs
wire input_axis_tready; wire input_axis_tready;
wire [DATA_WIDTH-1:0] output_axis_tdata; wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid; wire output_axis_tvalid;
wire output_axis_tlast; wire output_axis_tlast;
wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
wire overflow; wire overflow;
wire bad_frame; wire bad_frame;
wire good_frame; wire good_frame;
@ -63,16 +81,23 @@ initial begin
rst, rst,
current_test, current_test,
input_axis_tdata, input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid, input_axis_tvalid,
input_axis_tlast, input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser, input_axis_tuser,
output_axis_tready output_axis_tready
); );
$to_myhdl( $to_myhdl(
input_axis_tready, input_axis_tready,
output_axis_tdata, output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid, output_axis_tvalid,
output_axis_tlast, output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser,
overflow, overflow,
bad_frame, bad_frame,
good_frame good_frame
@ -86,6 +111,17 @@ end
axis_frame_fifo #( axis_frame_fifo #(
.ADDR_WIDTH(ADDR_WIDTH), .ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL) .DROP_WHEN_FULL(DROP_WHEN_FULL)
) )
UUT ( UUT (
@ -93,15 +129,22 @@ UUT (
.rst(rst), .rst(rst),
// AXI input // AXI input
.input_axis_tdata(input_axis_tdata), .input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid), .input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready), .input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast), .input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser), .input_axis_tuser(input_axis_tuser),
// AXI output // AXI output
.output_axis_tdata(output_axis_tdata), .output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser),
// Status // Status
.overflow(overflow), .overflow(overflow),
.bad_frame(bad_frame), .bad_frame(bad_frame),

181
lib/axis/tb/test_axis_frame_fifo_64.py
View File

@ -28,8 +28,8 @@ import os
import axis_ep import axis_ep
module = 'axis_frame_fifo_64' module = 'axis_frame_fifo'
testbench = 'test_%s' % module testbench = 'test_%s_64' % module
srcs = [] srcs = []
@ -45,7 +45,17 @@ def bench():
# Parameters # Parameters
ADDR_WIDTH = 6 ADDR_WIDTH = 6
DATA_WIDTH = 64 DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8) KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
USER_BAD_FRAME_VALUE = 1
USER_BAD_FRAME_MASK = 1
DROP_BAD_FRAME = 1
DROP_WHEN_FULL = 0 DROP_WHEN_FULL = 0
# Inputs # Inputs
@ -54,18 +64,23 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0)) input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0)) input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0)) input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0)) output_axis_tready = Signal(bool(0))
# Outputs # Outputs
input_axis_tready = Signal(bool(0)) input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0)) output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0)) output_axis_tlast = Signal(bool(0))
output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
overflow = Signal(bool(0)) overflow = Signal(bool(0))
bad_frame = Signal(bool(0)) bad_frame = Signal(bool(0))
good_frame = Signal(bool(0)) good_frame = Signal(bool(0))
@ -84,6 +99,8 @@ def bench():
tvalid=input_axis_tvalid, tvalid=input_axis_tvalid,
tready=input_axis_tready, tready=input_axis_tready,
tlast=input_axis_tlast, tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser, tuser=input_axis_tuser,
pause=source_pause, pause=source_pause,
name='source' name='source'
@ -99,6 +116,9 @@ def bench():
tvalid=output_axis_tvalid, tvalid=output_axis_tvalid,
tready=output_axis_tready, tready=output_axis_tready,
tlast=output_axis_tlast, tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser,
pause=sink_pause, pause=sink_pause,
name='sink' name='sink'
) )
@ -118,6 +138,8 @@ def bench():
input_axis_tvalid=input_axis_tvalid, input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready, input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast, input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser, input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata, output_axis_tdata=output_axis_tdata,
@ -125,6 +147,9 @@ def bench():
output_axis_tvalid=output_axis_tvalid, output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready, output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast, output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser,
overflow=overflow, overflow=overflow,
bad_frame=bad_frame, bad_frame=bad_frame,
@ -165,10 +190,14 @@ def bench():
print("test 1: test packet") print("test 1: test packet")
current_test.next = 1 current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
overflow_asserted.next = 0 overflow_asserted.next = 0
bad_frame_asserted.next = 0 bad_frame_asserted.next = 0
@ -195,10 +224,14 @@ def bench():
print("test 2: longer packet") print("test 2: longer packet")
current_test.next = 2 current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(256))) b'\x80\x00' +
bytearray(range(256)),
id=2,
dest=1
)
overflow_asserted.next = 0 overflow_asserted.next = 0
bad_frame_asserted.next = 0 bad_frame_asserted.next = 0
@ -223,10 +256,14 @@ def bench():
print("test 3: test packet with pauses") print("test 3: test packet with pauses")
current_test.next = 3 current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(256))) b'\x80\x00' +
bytearray(range(256)),
id=3,
dest=1
)
overflow_asserted.next = 0 overflow_asserted.next = 0
bad_frame_asserted.next = 0 bad_frame_asserted.next = 0
@ -267,14 +304,22 @@ def bench():
print("test 4: back-to-back packets") print("test 4: back-to-back packets")
current_test.next = 4 current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=4,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2
)
overflow_asserted.next = 0 overflow_asserted.next = 0
bad_frame_asserted.next = 0 bad_frame_asserted.next = 0
@ -308,14 +353,22 @@ def bench():
print("test 5: alternate pause source") print("test 5: alternate pause source")
current_test.next = 5 current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=5,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2
)
overflow_asserted.next = 0 overflow_asserted.next = 0
bad_frame_asserted.next = 0 bad_frame_asserted.next = 0
@ -354,14 +407,22 @@ def bench():
print("test 6: alternate pause sink") print("test 6: alternate pause sink")
current_test.next = 6 current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=6,
b'\x80\x00' + dest=1
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
overflow_asserted.next = 0 overflow_asserted.next = 0
bad_frame_asserted.next = 0 bad_frame_asserted.next = 0
@ -400,11 +461,15 @@ def bench():
print("test 7: tuser assert") print("test 7: tuser assert")
current_test.next = 7 current_test.next = 7
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame.user = 1 b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1,
last_cycle_user=1
)
overflow_asserted.next = 0 overflow_asserted.next = 0
bad_frame_asserted.next = 0 bad_frame_asserted.next = 0
@ -427,10 +492,14 @@ def bench():
print("test 8: single packet overflow") print("test 8: single packet overflow")
current_test.next = 8 current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
bytearray(range(256))*2) b'\x80\x00' +
bytearray(range(256))*2,
id=8,
dest=1
)
overflow_asserted.next = 0 overflow_asserted.next = 0
bad_frame_asserted.next = 0 bad_frame_asserted.next = 0
@ -453,7 +522,11 @@ def bench():
print("test 9: initial sink pause") print("test 9: initial sink pause")
current_test.next = 9 current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24))) test_frame = axis_ep.AXIStreamFrame(
bytearray(range(24)),
id=9,
dest=1
)
sink_pause.next = 1 sink_pause.next = 1
source.send(test_frame) source.send(test_frame)
@ -477,7 +550,11 @@ def bench():
print("test 10: initial sink pause, reset") print("test 10: initial sink pause, reset")
current_test.next = 10 current_test.next = 10
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24))) test_frame = axis_ep.AXIStreamFrame(
bytearray(range(24)),
id=10,
dest=1
)
sink_pause.next = 1 sink_pause.next = 1
source.send(test_frame) source.send(test_frame)

43
lib/axis/tb/test_axis_frame_fifo_64.v
View File

@ -27,14 +27,24 @@ THE SOFTWARE.
`timescale 1ns / 1ps `timescale 1ns / 1ps
/* /*
* Testbench for axis_frame_fifo_64 * Testbench for axis_frame_fifo
*/ */
module test_axis_frame_fifo_64; module test_axis_frame_fifo_64;
// Parameters // Parameters
parameter ADDR_WIDTH = 6; parameter ADDR_WIDTH = 6;
parameter DATA_WIDTH = 64; parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8); parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 1;
parameter DROP_WHEN_FULL = 0; parameter DROP_WHEN_FULL = 0;
// Inputs // Inputs
@ -46,7 +56,9 @@ reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0; reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0; reg input_axis_tvalid = 0;
reg input_axis_tlast = 0; reg input_axis_tlast = 0;
reg input_axis_tuser = 0; reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_axis_tready = 0; reg output_axis_tready = 0;
// Outputs // Outputs
@ -55,6 +67,9 @@ wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep; wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid; wire output_axis_tvalid;
wire output_axis_tlast; wire output_axis_tlast;
wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
wire overflow; wire overflow;
wire bad_frame; wire bad_frame;
wire good_frame; wire good_frame;
@ -69,6 +84,8 @@ initial begin
input_axis_tkeep, input_axis_tkeep,
input_axis_tvalid, input_axis_tvalid,
input_axis_tlast, input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser, input_axis_tuser,
output_axis_tready output_axis_tready
); );
@ -78,6 +95,9 @@ initial begin
output_axis_tkeep, output_axis_tkeep,
output_axis_tvalid, output_axis_tvalid,
output_axis_tlast, output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser,
overflow, overflow,
bad_frame, bad_frame,
good_frame good_frame
@ -88,10 +108,20 @@ initial begin
$dumpvars(0, test_axis_frame_fifo_64); $dumpvars(0, test_axis_frame_fifo_64);
end end
axis_frame_fifo_64 #( axis_frame_fifo #(
.ADDR_WIDTH(ADDR_WIDTH), .ADDR_WIDTH(ADDR_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.DATA_WIDTH(DATA_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL) .DROP_WHEN_FULL(DROP_WHEN_FULL)
) )
UUT ( UUT (
@ -103,6 +133,8 @@ UUT (
.input_axis_tvalid(input_axis_tvalid), .input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready), .input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast), .input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser), .input_axis_tuser(input_axis_tuser),
// AXI output // AXI output
.output_axis_tdata(output_axis_tdata), .output_axis_tdata(output_axis_tdata),
@ -110,6 +142,9 @@ UUT (
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser),
// Status // Status
.overflow(overflow), .overflow(overflow),
.bad_frame(bad_frame), .bad_frame(bad_frame),

4
lib/axis/tb/test_axis_frame_join_4.py
View File

@ -445,7 +445,7 @@ def bench():
test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01') test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02') test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03') test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_0.user = 1 test_frame_0.last_cycle_user = 1
source_0.send(test_frame_0) source_0.send(test_frame_0)
source_1.send(test_frame_1) source_1.send(test_frame_1)
source_2.send(test_frame_2) source_2.send(test_frame_2)
@ -459,7 +459,7 @@ def bench():
rx_frame = sink.recv() rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data assert rx_frame.data == struct.pack('>H', tag) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
assert rx_frame.user[-1] assert rx_frame.last_cycle_user
yield delay(100) yield delay(100)

41
lib/axis/tb/test_axis_frame_length_adjust_64.py
View File

@ -44,7 +44,14 @@ def bench():
# Parameters # Parameters
DATA_WIDTH = 64 DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8) KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))
@ -52,10 +59,12 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0)) input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0)) input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0)) input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0)) output_axis_tready = Signal(bool(0))
status_ready = Signal(bool(0)) status_ready = Signal(bool(0))
length_min = Signal(intbv(0)[16:]) length_min = Signal(intbv(0)[16:])
@ -64,10 +73,12 @@ def bench():
# Outputs # Outputs
input_axis_tready = Signal(bool(0)) input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0)) output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0)) output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0)) output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
status_valid = Signal(bool(0)) status_valid = Signal(bool(0))
status_frame_pad = Signal(bool(0)) status_frame_pad = Signal(bool(0))
status_frame_truncate = Signal(bool(0)) status_frame_truncate = Signal(bool(0))
@ -89,6 +100,8 @@ def bench():
tvalid=input_axis_tvalid, tvalid=input_axis_tvalid,
tready=input_axis_tready, tready=input_axis_tready,
tlast=input_axis_tlast, tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser, tuser=input_axis_tuser,
pause=source_pause, pause=source_pause,
name='source' name='source'
@ -104,6 +117,8 @@ def bench():
tvalid=output_axis_tvalid, tvalid=output_axis_tvalid,
tready=output_axis_tready, tready=output_axis_tready,
tlast=output_axis_tlast, tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser, tuser=output_axis_tuser,
pause=sink_pause, pause=sink_pause,
name='sink' name='sink'
@ -136,6 +151,8 @@ def bench():
input_axis_tvalid=input_axis_tvalid, input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready, input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast, input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser, input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata, output_axis_tdata=output_axis_tdata,
@ -143,6 +160,8 @@ def bench():
output_axis_tvalid=output_axis_tvalid, output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready, output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast, output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser, output_axis_tuser=output_axis_tuser,
status_valid=status_valid, status_valid=status_valid,
@ -206,7 +225,7 @@ def bench():
print("test 1: test packet, length %d" % payload_len) print("test 1: test packet, length %d" % payload_len)
current_test.next = 1 current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=1, dest=1)
for wait in wait_normal, wait_pause_source, wait_pause_sink: for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame) source.send(test_frame)
@ -243,8 +262,8 @@ def bench():
print("test 2: back-to-back packets, length %d" % payload_len) print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2 current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=2, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=2, dest=2)
for wait in wait_normal, wait_pause_source, wait_pause_sink: for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1) source.send(test_frame1)
@ -297,10 +316,10 @@ def bench():
print("test 3: tuser assert, length %d" % payload_len) print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3 current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=3, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=3, dest=2)
test_frame1.user = 1 test_frame1.last_cycle_user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink: for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1) source.send(test_frame1)
@ -323,7 +342,7 @@ def bench():
assert lrx <= lmax assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm] assert rx_frame.data[:lm] == test_frame1.data[:lm]
assert rx_frame.user[-1] assert rx_frame.last_cycle_user
status = status_sink.recv() status = status_sink.recv()
assert status.data[0][0] == (lt < lmin) assert status.data[0][0] == (lt < lmin)

36
lib/axis/tb/test_axis_frame_length_adjust_64.v
View File

@ -32,8 +32,15 @@ THE SOFTWARE.
module test_axis_frame_length_adjust_64; module test_axis_frame_length_adjust_64;
// Parameters // Parameters
localparam DATA_WIDTH = 64; parameter DATA_WIDTH = 64;
localparam KEEP_WIDTH = (DATA_WIDTH/8); parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -44,7 +51,9 @@ reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0; reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0; reg input_axis_tvalid = 0;
reg input_axis_tlast = 0; reg input_axis_tlast = 0;
reg input_axis_tuser = 0; reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_axis_tready = 0; reg output_axis_tready = 0;
reg status_ready = 0; reg status_ready = 0;
reg [15:0] length_min = 0; reg [15:0] length_min = 0;
@ -56,7 +65,9 @@ wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep; wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid; wire output_axis_tvalid;
wire output_axis_tlast; wire output_axis_tlast;
wire output_axis_tuser; wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
wire status_valid; wire status_valid;
wire status_frame_pad; wire status_frame_pad;
wire status_frame_truncate; wire status_frame_truncate;
@ -73,6 +84,8 @@ initial begin
input_axis_tkeep, input_axis_tkeep,
input_axis_tvalid, input_axis_tvalid,
input_axis_tlast, input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser, input_axis_tuser,
output_axis_tready, output_axis_tready,
status_ready, status_ready,
@ -85,6 +98,8 @@ initial begin
output_axis_tkeep, output_axis_tkeep,
output_axis_tvalid, output_axis_tvalid,
output_axis_tlast, output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser, output_axis_tuser,
status_valid, status_valid,
status_frame_pad, status_frame_pad,
@ -100,7 +115,14 @@ end
axis_frame_length_adjust #( axis_frame_length_adjust #(
.DATA_WIDTH(DATA_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH) .KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) )
UUT ( UUT (
.clk(clk), .clk(clk),
@ -111,6 +133,8 @@ UUT (
.input_axis_tvalid(input_axis_tvalid), .input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready), .input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast), .input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser), .input_axis_tuser(input_axis_tuser),
// AXI output // AXI output
.output_axis_tdata(output_axis_tdata), .output_axis_tdata(output_axis_tdata),
@ -118,6 +142,8 @@ UUT (
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser), .output_axis_tuser(output_axis_tuser),
// Status // Status
.status_valid(status_valid), .status_valid(status_valid),

41
lib/axis/tb/test_axis_frame_length_adjust_8.py
View File

@ -44,7 +44,14 @@ def bench():
# Parameters # Parameters
DATA_WIDTH = 8 DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8) KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))
@ -52,10 +59,12 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0)) input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0)) input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0)) input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0)) output_axis_tready = Signal(bool(0))
status_ready = Signal(bool(0)) status_ready = Signal(bool(0))
length_min = Signal(intbv(0)[16:]) length_min = Signal(intbv(0)[16:])
@ -64,10 +73,12 @@ def bench():
# Outputs # Outputs
input_axis_tready = Signal(bool(0)) input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0)) output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0)) output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0)) output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
status_valid = Signal(bool(0)) status_valid = Signal(bool(0))
status_frame_pad = Signal(bool(0)) status_frame_pad = Signal(bool(0))
status_frame_truncate = Signal(bool(0)) status_frame_truncate = Signal(bool(0))
@ -89,6 +100,8 @@ def bench():
tvalid=input_axis_tvalid, tvalid=input_axis_tvalid,
tready=input_axis_tready, tready=input_axis_tready,
tlast=input_axis_tlast, tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser, tuser=input_axis_tuser,
pause=source_pause, pause=source_pause,
name='source' name='source'
@ -104,6 +117,8 @@ def bench():
tvalid=output_axis_tvalid, tvalid=output_axis_tvalid,
tready=output_axis_tready, tready=output_axis_tready,
tlast=output_axis_tlast, tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser, tuser=output_axis_tuser,
pause=sink_pause, pause=sink_pause,
name='sink' name='sink'
@ -136,6 +151,8 @@ def bench():
input_axis_tvalid=input_axis_tvalid, input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready, input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast, input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser, input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata, output_axis_tdata=output_axis_tdata,
@ -143,6 +160,8 @@ def bench():
output_axis_tvalid=output_axis_tvalid, output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready, output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast, output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser, output_axis_tuser=output_axis_tuser,
status_valid=status_valid, status_valid=status_valid,
@ -206,7 +225,7 @@ def bench():
print("test 1: test packet, length %d" % payload_len) print("test 1: test packet, length %d" % payload_len)
current_test.next = 1 current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=1, dest=1)
for wait in wait_normal, wait_pause_source, wait_pause_sink: for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame) source.send(test_frame)
@ -243,8 +262,8 @@ def bench():
print("test 2: back-to-back packets, length %d" % payload_len) print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2 current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=2, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=2, dest=2)
for wait in wait_normal, wait_pause_source, wait_pause_sink: for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1) source.send(test_frame1)
@ -297,10 +316,10 @@ def bench():
print("test 3: tuser assert, length %d" % payload_len) print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3 current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=3, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=3, dest=2)
test_frame1.user = 1 test_frame1.last_cycle_user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink: for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1) source.send(test_frame1)
@ -323,7 +342,7 @@ def bench():
assert lrx <= lmax assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm] assert rx_frame.data[:lm] == test_frame1.data[:lm]
assert rx_frame.user[-1] assert rx_frame.last_cycle_user
status = status_sink.recv() status = status_sink.recv()
assert status.data[0][0] == (lt < lmin) assert status.data[0][0] == (lt < lmin)

36
lib/axis/tb/test_axis_frame_length_adjust_8.v
View File

@ -32,8 +32,15 @@ THE SOFTWARE.
module test_axis_frame_length_adjust_8; module test_axis_frame_length_adjust_8;
// Parameters // Parameters
localparam DATA_WIDTH = 8; parameter DATA_WIDTH = 8;
localparam KEEP_WIDTH = (DATA_WIDTH/8); parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -44,7 +51,9 @@ reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0; reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0; reg input_axis_tvalid = 0;
reg input_axis_tlast = 0; reg input_axis_tlast = 0;
reg input_axis_tuser = 0; reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_axis_tready = 0; reg output_axis_tready = 0;
reg status_ready = 0; reg status_ready = 0;
reg [15:0] length_min = 0; reg [15:0] length_min = 0;
@ -56,7 +65,9 @@ wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep; wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid; wire output_axis_tvalid;
wire output_axis_tlast; wire output_axis_tlast;
wire output_axis_tuser; wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
wire status_valid; wire status_valid;
wire status_frame_pad; wire status_frame_pad;
wire status_frame_truncate; wire status_frame_truncate;
@ -73,6 +84,8 @@ initial begin
input_axis_tkeep, input_axis_tkeep,
input_axis_tvalid, input_axis_tvalid,
input_axis_tlast, input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser, input_axis_tuser,
output_axis_tready, output_axis_tready,
status_ready, status_ready,
@ -85,6 +98,8 @@ initial begin
output_axis_tkeep, output_axis_tkeep,
output_axis_tvalid, output_axis_tvalid,
output_axis_tlast, output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser, output_axis_tuser,
status_valid, status_valid,
status_frame_pad, status_frame_pad,
@ -100,7 +115,14 @@ end
axis_frame_length_adjust #( axis_frame_length_adjust #(
.DATA_WIDTH(DATA_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH) .KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) )
UUT ( UUT (
.clk(clk), .clk(clk),
@ -111,6 +133,8 @@ UUT (
.input_axis_tvalid(input_axis_tvalid), .input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready), .input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast), .input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser), .input_axis_tuser(input_axis_tuser),
// AXI output // AXI output
.output_axis_tdata(output_axis_tdata), .output_axis_tdata(output_axis_tdata),
@ -118,6 +142,8 @@ UUT (
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser), .output_axis_tuser(output_axis_tuser),
// Status // Status
.status_valid(status_valid), .status_valid(status_valid),

44
lib/axis/tb/test_axis_frame_length_adjust_fifo.py
View File

@ -46,6 +46,14 @@ def bench():
# Parameters # Parameters
DATA_WIDTH = 8 DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
FRAME_FIFO_ADDR_WIDTH = 12 FRAME_FIFO_ADDR_WIDTH = 12
HEADER_FIFO_ADDR_WIDTH = 3 HEADER_FIFO_ADDR_WIDTH = 3
@ -55,9 +63,12 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0)) input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0)) input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0)) input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_hdr_ready = Signal(bool(0)) output_axis_hdr_ready = Signal(bool(0))
output_axis_tready = Signal(bool(0)) output_axis_tready = Signal(bool(0))
length_min = Signal(intbv(0)[16:]) length_min = Signal(intbv(0)[16:])
@ -71,9 +82,12 @@ def bench():
output_axis_hdr_length = Signal(intbv(0)[16:]) output_axis_hdr_length = Signal(intbv(0)[16:])
output_axis_hdr_original_length = Signal(intbv(0)[16:]) output_axis_hdr_original_length = Signal(intbv(0)[16:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0)) output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0)) output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0)) output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks # sources and sinks
source_pause = Signal(bool(0)) source_pause = Signal(bool(0))
@ -86,9 +100,12 @@ def bench():
clk, clk,
rst, rst,
tdata=input_axis_tdata, tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid, tvalid=input_axis_tvalid,
tready=input_axis_tready, tready=input_axis_tready,
tlast=input_axis_tlast, tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser, tuser=input_axis_tuser,
pause=source_pause, pause=source_pause,
name='source' name='source'
@ -100,9 +117,12 @@ def bench():
clk, clk,
rst, rst,
tdata=output_axis_tdata, tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid, tvalid=output_axis_tvalid,
tready=output_axis_tready, tready=output_axis_tready,
tlast=output_axis_tlast, tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser, tuser=output_axis_tuser,
pause=sink_pause, pause=sink_pause,
name='sink' name='sink'
@ -131,9 +151,12 @@ def bench():
current_test=current_test, current_test=current_test,
input_axis_tdata=input_axis_tdata, input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid, input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready, input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast, input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser, input_axis_tuser=input_axis_tuser,
output_axis_hdr_valid=output_axis_hdr_valid, output_axis_hdr_valid=output_axis_hdr_valid,
@ -143,9 +166,12 @@ def bench():
output_axis_hdr_length=output_axis_hdr_length, output_axis_hdr_length=output_axis_hdr_length,
output_axis_hdr_original_length=output_axis_hdr_original_length, output_axis_hdr_original_length=output_axis_hdr_original_length,
output_axis_tdata=output_axis_tdata, output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid, output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready, output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast, output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser, output_axis_tuser=output_axis_tuser,
length_min=length_min, length_min=length_min,
@ -184,7 +210,7 @@ def bench():
print("test 1: test packet, length %d" % payload_len) print("test 1: test packet, length %d" % payload_len)
current_test.next = 1 current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=1, dest=1)
for wait in wait_normal,: for wait in wait_normal,:
source.send(test_frame) source.send(test_frame)
@ -225,8 +251,8 @@ def bench():
print("test 2: back-to-back packets, length %d" % payload_len) print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2 current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=2, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=2, dest=2)
for wait in wait_normal,: for wait in wait_normal,:
source.send(test_frame1) source.send(test_frame1)
@ -281,10 +307,10 @@ def bench():
print("test 3: tuser assert, length %d" % payload_len) print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3 current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=3, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=3, dest=2)
test_frame1.user = 1 test_frame1.last_cycle_user = 1
for wait in wait_normal,: for wait in wait_normal,:
source.send(test_frame1) source.send(test_frame1)
@ -314,7 +340,7 @@ def bench():
assert hdr.data[0][1] == (lt > lmax) assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt assert hdr.data[0][3] == lt
assert rx_frame.user[-1] assert rx_frame.last_cycle_user
rx_frame = sink.recv() rx_frame = sink.recv()

44
lib/axis/tb/test_axis_frame_length_adjust_fifo.v
View File

@ -32,9 +32,17 @@ THE SOFTWARE.
module test_axis_frame_length_adjust_fifo; module test_axis_frame_length_adjust_fifo;
// Parameters // Parameters
localparam DATA_WIDTH = 8; parameter DATA_WIDTH = 8;
localparam FRAME_FIFO_ADDR_WIDTH = 12; parameter KEEP_ENABLE = (DATA_WIDTH>8);
localparam HEADER_FIFO_ADDR_WIDTH = 3; parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter FRAME_FIFO_ADDR_WIDTH = 12;
parameter HEADER_FIFO_ADDR_WIDTH = 3;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -42,9 +50,12 @@ reg rst = 0;
reg [7:0] current_test = 0; reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0; reg input_axis_tvalid = 0;
reg input_axis_tlast = 0; reg input_axis_tlast = 0;
reg input_axis_tuser = 0; reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_axis_hdr_ready = 0; reg output_axis_hdr_ready = 0;
reg output_axis_tready = 0; reg output_axis_tready = 0;
reg [15:0] length_min = 0; reg [15:0] length_min = 0;
@ -53,9 +64,12 @@ reg [15:0] length_max = 0;
// Outputs // Outputs
wire input_axis_tready; wire input_axis_tready;
wire [DATA_WIDTH-1:0] output_axis_tdata; wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid; wire output_axis_tvalid;
wire output_axis_tlast; wire output_axis_tlast;
wire output_axis_tuser; wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
wire output_axis_hdr_valid; wire output_axis_hdr_valid;
wire output_axis_hdr_pad; wire output_axis_hdr_pad;
wire output_axis_hdr_truncate; wire output_axis_hdr_truncate;
@ -69,8 +83,11 @@ initial begin
rst, rst,
current_test, current_test,
input_axis_tdata, input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid, input_axis_tvalid,
input_axis_tlast, input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser, input_axis_tuser,
output_axis_hdr_ready, output_axis_hdr_ready,
output_axis_tready, output_axis_tready,
@ -85,8 +102,11 @@ initial begin
output_axis_hdr_length, output_axis_hdr_length,
output_axis_hdr_original_length, output_axis_hdr_original_length,
output_axis_tdata, output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid, output_axis_tvalid,
output_axis_tlast, output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser output_axis_tuser
); );
@ -97,6 +117,14 @@ end
axis_frame_length_adjust_fifo #( axis_frame_length_adjust_fifo #(
.DATA_WIDTH(DATA_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.FRAME_FIFO_ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH), .FRAME_FIFO_ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH),
.HEADER_FIFO_ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH) .HEADER_FIFO_ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH)
) )
@ -105,9 +133,12 @@ UUT (
.rst(rst), .rst(rst),
// AXI input // AXI input
.input_axis_tdata(input_axis_tdata), .input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid), .input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready), .input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast), .input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser), .input_axis_tuser(input_axis_tuser),
// AXI output // AXI output
.output_axis_hdr_valid(output_axis_hdr_valid), .output_axis_hdr_valid(output_axis_hdr_valid),
@ -117,9 +148,12 @@ UUT (
.output_axis_hdr_length(output_axis_hdr_length), .output_axis_hdr_length(output_axis_hdr_length),
.output_axis_hdr_original_length(output_axis_hdr_original_length), .output_axis_hdr_original_length(output_axis_hdr_original_length),
.output_axis_tdata(output_axis_tdata), .output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser), .output_axis_tuser(output_axis_tuser),
// Configuration // Configuration
.length_min(length_min), .length_min(length_min),

46
lib/axis/tb/test_axis_frame_length_adjust_fifo_64.py
View File

@ -28,15 +28,14 @@ import os
import axis_ep import axis_ep
module = 'axis_frame_length_adjust_fifo_64' module = 'axis_frame_length_adjust_fifo'
testbench = 'test_%s' % module testbench = 'test_%s_64' % module
srcs = [] srcs = []
srcs.append("../rtl/%s.v" % module) srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/axis_frame_length_adjust.v") srcs.append("../rtl/axis_frame_length_adjust.v")
srcs.append("../rtl/axis_fifo.v") srcs.append("../rtl/axis_fifo.v")
srcs.append("../rtl/axis_fifo_64.v")
srcs.append("%s.v" % testbench) srcs.append("%s.v" % testbench)
src = ' '.join(srcs) src = ' '.join(srcs)
@ -47,7 +46,14 @@ def bench():
# Parameters # Parameters
DATA_WIDTH = 64 DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8) KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
FRAME_FIFO_ADDR_WIDTH = 9 FRAME_FIFO_ADDR_WIDTH = 9
HEADER_FIFO_ADDR_WIDTH = 3 HEADER_FIFO_ADDR_WIDTH = 3
@ -57,10 +63,12 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0)) input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0)) input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0)) input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_hdr_ready = Signal(bool(0)) output_axis_hdr_ready = Signal(bool(0))
output_axis_tready = Signal(bool(0)) output_axis_tready = Signal(bool(0))
length_min = Signal(intbv(0)[16:]) length_min = Signal(intbv(0)[16:])
@ -74,10 +82,12 @@ def bench():
output_axis_hdr_length = Signal(intbv(0)[16:]) output_axis_hdr_length = Signal(intbv(0)[16:])
output_axis_hdr_original_length = Signal(intbv(0)[16:]) output_axis_hdr_original_length = Signal(intbv(0)[16:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0)) output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0)) output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0)) output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks # sources and sinks
source_pause = Signal(bool(0)) source_pause = Signal(bool(0))
@ -94,6 +104,8 @@ def bench():
tvalid=input_axis_tvalid, tvalid=input_axis_tvalid,
tready=input_axis_tready, tready=input_axis_tready,
tlast=input_axis_tlast, tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser, tuser=input_axis_tuser,
pause=source_pause, pause=source_pause,
name='source' name='source'
@ -109,6 +121,8 @@ def bench():
tvalid=output_axis_tvalid, tvalid=output_axis_tvalid,
tready=output_axis_tready, tready=output_axis_tready,
tlast=output_axis_tlast, tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser, tuser=output_axis_tuser,
pause=sink_pause, pause=sink_pause,
name='sink' name='sink'
@ -141,6 +155,8 @@ def bench():
input_axis_tvalid=input_axis_tvalid, input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready, input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast, input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser, input_axis_tuser=input_axis_tuser,
output_axis_hdr_valid=output_axis_hdr_valid, output_axis_hdr_valid=output_axis_hdr_valid,
@ -154,6 +170,8 @@ def bench():
output_axis_tvalid=output_axis_tvalid, output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready, output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast, output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser, output_axis_tuser=output_axis_tuser,
length_min=length_min, length_min=length_min,
@ -192,7 +210,7 @@ def bench():
print("test 1: test packet, length %d" % payload_len) print("test 1: test packet, length %d" % payload_len)
current_test.next = 1 current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=1, dest=1)
for wait in wait_normal,: for wait in wait_normal,:
source.send(test_frame) source.send(test_frame)
@ -233,8 +251,8 @@ def bench():
print("test 2: back-to-back packets, length %d" % payload_len) print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2 current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=2, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=2, dest=2)
for wait in wait_normal,: for wait in wait_normal,:
source.send(test_frame1) source.send(test_frame1)
@ -289,10 +307,10 @@ def bench():
print("test 3: tuser assert, length %d" % payload_len) print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3 current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=3, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len))) test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=3, dest=2)
test_frame1.user = 1 test_frame1.last_cycle_user = 1
for wait in wait_normal,: for wait in wait_normal,:
source.send(test_frame1) source.send(test_frame1)
@ -322,7 +340,7 @@ def bench():
assert hdr.data[0][1] == (lt > lmax) assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt assert hdr.data[0][3] == lt
assert rx_frame.user[-1] assert rx_frame.last_cycle_user
rx_frame = sink.recv() rx_frame = sink.recv()

42
lib/axis/tb/test_axis_frame_length_adjust_fifo_64.v
View File

@ -27,15 +27,22 @@ THE SOFTWARE.
`timescale 1ns / 1ps `timescale 1ns / 1ps
/* /*
* Testbench for axis_frame_length_adjust_fifo_64 * Testbench for axis_frame_length_adjust_fifo
*/ */
module test_axis_frame_length_adjust_fifo_64; module test_axis_frame_length_adjust_fifo_64;
// Parameters // Parameters
localparam DATA_WIDTH = 64; parameter DATA_WIDTH = 64;
localparam KEEP_WIDTH = (DATA_WIDTH/8); parameter KEEP_ENABLE = (DATA_WIDTH>8);
localparam FRAME_FIFO_ADDR_WIDTH = 9; parameter KEEP_WIDTH = (DATA_WIDTH/8);
localparam HEADER_FIFO_ADDR_WIDTH = 3; parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter FRAME_FIFO_ADDR_WIDTH = 9;
parameter HEADER_FIFO_ADDR_WIDTH = 3;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -46,7 +53,9 @@ reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0; reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0; reg input_axis_tvalid = 0;
reg input_axis_tlast = 0; reg input_axis_tlast = 0;
reg input_axis_tuser = 0; reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_axis_hdr_ready = 0; reg output_axis_hdr_ready = 0;
reg output_axis_tready = 0; reg output_axis_tready = 0;
reg [15:0] length_min = 0; reg [15:0] length_min = 0;
@ -58,7 +67,9 @@ wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep; wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid; wire output_axis_tvalid;
wire output_axis_tlast; wire output_axis_tlast;
wire output_axis_tuser; wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
wire output_axis_hdr_valid; wire output_axis_hdr_valid;
wire output_axis_hdr_pad; wire output_axis_hdr_pad;
wire output_axis_hdr_truncate; wire output_axis_hdr_truncate;
@ -75,6 +86,8 @@ initial begin
input_axis_tkeep, input_axis_tkeep,
input_axis_tvalid, input_axis_tvalid,
input_axis_tlast, input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser, input_axis_tuser,
output_axis_hdr_ready, output_axis_hdr_ready,
output_axis_tready, output_axis_tready,
@ -92,6 +105,8 @@ initial begin
output_axis_tkeep, output_axis_tkeep,
output_axis_tvalid, output_axis_tvalid,
output_axis_tlast, output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser output_axis_tuser
); );
@ -100,9 +115,16 @@ initial begin
$dumpvars(0, test_axis_frame_length_adjust_fifo_64); $dumpvars(0, test_axis_frame_length_adjust_fifo_64);
end end
axis_frame_length_adjust_fifo_64 #( axis_frame_length_adjust_fifo #(
.DATA_WIDTH(DATA_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH), .KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.FRAME_FIFO_ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH), .FRAME_FIFO_ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH),
.HEADER_FIFO_ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH) .HEADER_FIFO_ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH)
) )
@ -115,6 +137,8 @@ UUT (
.input_axis_tvalid(input_axis_tvalid), .input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready), .input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast), .input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser), .input_axis_tuser(input_axis_tuser),
// AXI output // AXI output
.output_axis_hdr_valid(output_axis_hdr_valid), .output_axis_hdr_valid(output_axis_hdr_valid),
@ -128,6 +152,8 @@ UUT (
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser), .output_axis_tuser(output_axis_tuser),
// Configuration // Configuration
.length_min(length_min), .length_min(length_min),

189
lib/axis/tb/test_axis_mux_4.py
View File

@ -44,6 +44,14 @@ def bench():
# Parameters # Parameters
DATA_WIDTH = 8 DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))
@ -51,21 +59,33 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_0_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_0_axis_tvalid = Signal(bool(0)) input_0_axis_tvalid = Signal(bool(0))
input_0_axis_tlast = Signal(bool(0)) input_0_axis_tlast = Signal(bool(0))
input_0_axis_tuser = Signal(bool(0)) input_0_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_0_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_0_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_1_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_1_axis_tvalid = Signal(bool(0)) input_1_axis_tvalid = Signal(bool(0))
input_1_axis_tlast = Signal(bool(0)) input_1_axis_tlast = Signal(bool(0))
input_1_axis_tuser = Signal(bool(0)) input_1_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_1_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_1_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_2_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_2_axis_tvalid = Signal(bool(0)) input_2_axis_tvalid = Signal(bool(0))
input_2_axis_tlast = Signal(bool(0)) input_2_axis_tlast = Signal(bool(0))
input_2_axis_tuser = Signal(bool(0)) input_2_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_2_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_2_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_3_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_3_axis_tvalid = Signal(bool(0)) input_3_axis_tvalid = Signal(bool(0))
input_3_axis_tlast = Signal(bool(0)) input_3_axis_tlast = Signal(bool(0))
input_3_axis_tuser = Signal(bool(0)) input_3_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_3_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_3_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0)) output_axis_tready = Signal(bool(0))
@ -79,9 +99,12 @@ def bench():
input_3_axis_tready = Signal(bool(0)) input_3_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0)) output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0)) output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0)) output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks # sources and sinks
source_0_pause = Signal(bool(0)) source_0_pause = Signal(bool(0))
@ -96,9 +119,12 @@ def bench():
clk, clk,
rst, rst,
tdata=input_0_axis_tdata, tdata=input_0_axis_tdata,
tkeep=input_0_axis_tkeep,
tvalid=input_0_axis_tvalid, tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready, tready=input_0_axis_tready,
tlast=input_0_axis_tlast, tlast=input_0_axis_tlast,
tid=input_0_axis_tid,
tdest=input_0_axis_tdest,
tuser=input_0_axis_tuser, tuser=input_0_axis_tuser,
pause=source_0_pause, pause=source_0_pause,
name='source_0' name='source_0'
@ -110,9 +136,12 @@ def bench():
clk, clk,
rst, rst,
tdata=input_1_axis_tdata, tdata=input_1_axis_tdata,
tkeep=input_1_axis_tkeep,
tvalid=input_1_axis_tvalid, tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready, tready=input_1_axis_tready,
tlast=input_1_axis_tlast, tlast=input_1_axis_tlast,
tid=input_1_axis_tid,
tdest=input_1_axis_tdest,
tuser=input_1_axis_tuser, tuser=input_1_axis_tuser,
pause=source_1_pause, pause=source_1_pause,
name='source_1' name='source_1'
@ -124,9 +153,12 @@ def bench():
clk, clk,
rst, rst,
tdata=input_2_axis_tdata, tdata=input_2_axis_tdata,
tkeep=input_2_axis_tkeep,
tvalid=input_2_axis_tvalid, tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready, tready=input_2_axis_tready,
tlast=input_2_axis_tlast, tlast=input_2_axis_tlast,
tid=input_2_axis_tid,
tdest=input_2_axis_tdest,
tuser=input_2_axis_tuser, tuser=input_2_axis_tuser,
pause=source_2_pause, pause=source_2_pause,
name='source_2' name='source_2'
@ -138,9 +170,12 @@ def bench():
clk, clk,
rst, rst,
tdata=input_3_axis_tdata, tdata=input_3_axis_tdata,
tkeep=input_3_axis_tkeep,
tvalid=input_3_axis_tvalid, tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready, tready=input_3_axis_tready,
tlast=input_3_axis_tlast, tlast=input_3_axis_tlast,
tid=input_3_axis_tid,
tdest=input_3_axis_tdest,
tuser=input_3_axis_tuser, tuser=input_3_axis_tuser,
pause=source_3_pause, pause=source_3_pause,
name='source_3' name='source_3'
@ -152,9 +187,12 @@ def bench():
clk, clk,
rst, rst,
tdata=output_axis_tdata, tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid, tvalid=output_axis_tvalid,
tready=output_axis_tready, tready=output_axis_tready,
tlast=output_axis_tlast, tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser, tuser=output_axis_tuser,
pause=sink_pause, pause=sink_pause,
name='sink' name='sink'
@ -171,30 +209,45 @@ def bench():
current_test=current_test, current_test=current_test,
input_0_axis_tdata=input_0_axis_tdata, input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tkeep=input_0_axis_tkeep,
input_0_axis_tvalid=input_0_axis_tvalid, input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready, input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast, input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tid=input_0_axis_tid,
input_0_axis_tdest=input_0_axis_tdest,
input_0_axis_tuser=input_0_axis_tuser, input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata, input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tkeep=input_1_axis_tkeep,
input_1_axis_tvalid=input_1_axis_tvalid, input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready, input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast, input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tid=input_1_axis_tid,
input_1_axis_tdest=input_1_axis_tdest,
input_1_axis_tuser=input_1_axis_tuser, input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata, input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tkeep=input_2_axis_tkeep,
input_2_axis_tvalid=input_2_axis_tvalid, input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready, input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast, input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tid=input_2_axis_tid,
input_2_axis_tdest=input_2_axis_tdest,
input_2_axis_tuser=input_2_axis_tuser, input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata, input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tkeep=input_3_axis_tkeep,
input_3_axis_tvalid=input_3_axis_tvalid, input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready, input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast, input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tid=input_3_axis_tid,
input_3_axis_tdest=input_3_axis_tdest,
input_3_axis_tuser=input_3_axis_tuser, input_3_axis_tuser=input_3_axis_tuser,
output_axis_tdata=output_axis_tdata, output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid, output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready, output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast, output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser, output_axis_tuser=output_axis_tuser,
enable=enable, enable=enable,
@ -225,10 +278,15 @@ def bench():
select.next = 0 select.next = 0
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
source_0.send(test_frame) source_0.send(test_frame)
yield clk.posedge yield clk.posedge
@ -249,10 +307,15 @@ def bench():
select.next = 1 select.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=2,
dest=1
)
source_1.send(test_frame) source_1.send(test_frame)
yield clk.posedge yield clk.posedge
@ -273,14 +336,23 @@ def bench():
select.next = 0 select.next = 0
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=3,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=2
)
source_0.send(test_frame1) source_0.send(test_frame1)
source_0.send(test_frame2) source_0.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -306,14 +378,23 @@ def bench():
select.next = 1 select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=4,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2
)
source_1.send(test_frame1) source_1.send(test_frame1)
source_2.send(test_frame2) source_2.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -340,14 +421,23 @@ def bench():
select.next = 1 select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=5,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2
)
source_1.send(test_frame1) source_1.send(test_frame1)
source_2.send(test_frame2) source_2.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -385,14 +475,23 @@ def bench():
select.next = 1 select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=6,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
source_1.send(test_frame1) source_1.send(test_frame1)
source_2.send(test_frame2) source_2.send(test_frame2)
yield clk.posedge yield clk.posedge

73
lib/axis/tb/test_axis_mux_4.v
View File

@ -33,6 +33,14 @@ module test_axis_mux_4;
// Parameters // Parameters
parameter DATA_WIDTH = 8; parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -40,21 +48,33 @@ reg rst = 0;
reg [7:0] current_test = 0; reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] input_0_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_0_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_0_axis_tkeep = 0;
reg input_0_axis_tvalid = 0; reg input_0_axis_tvalid = 0;
reg input_0_axis_tlast = 0; reg input_0_axis_tlast = 0;
reg input_0_axis_tuser = 0; reg [ID_WIDTH-1:0] input_0_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_0_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_0_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_1_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_1_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_1_axis_tkeep = 0;
reg input_1_axis_tvalid = 0; reg input_1_axis_tvalid = 0;
reg input_1_axis_tlast = 0; reg input_1_axis_tlast = 0;
reg input_1_axis_tuser = 0; reg [ID_WIDTH-1:0] input_1_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_1_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_1_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_2_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_2_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_2_axis_tkeep = 0;
reg input_2_axis_tvalid = 0; reg input_2_axis_tvalid = 0;
reg input_2_axis_tlast = 0; reg input_2_axis_tlast = 0;
reg input_2_axis_tuser = 0; reg [ID_WIDTH-1:0] input_2_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_2_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_2_axis_tuser = 0;
reg [DATA_WIDTH-1:0] input_3_axis_tdata = 0; reg [DATA_WIDTH-1:0] input_3_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_3_axis_tkeep = 0;
reg input_3_axis_tvalid = 0; reg input_3_axis_tvalid = 0;
reg input_3_axis_tlast = 0; reg input_3_axis_tlast = 0;
reg input_3_axis_tuser = 0; reg [ID_WIDTH-1:0] input_3_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_3_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_3_axis_tuser = 0;
reg output_axis_tready = 0; reg output_axis_tready = 0;
@ -68,9 +88,12 @@ wire input_2_axis_tready;
wire input_3_axis_tready; wire input_3_axis_tready;
wire [DATA_WIDTH-1:0] output_axis_tdata; wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid; wire output_axis_tvalid;
wire output_axis_tlast; wire output_axis_tlast;
wire output_axis_tuser; wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
initial begin initial begin
// myhdl integration // myhdl integration
@ -79,20 +102,32 @@ initial begin
rst, rst,
current_test, current_test,
input_0_axis_tdata, input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid, input_0_axis_tvalid,
input_0_axis_tlast, input_0_axis_tlast,
input_0_axis_tid,
input_0_axis_tdest,
input_0_axis_tuser, input_0_axis_tuser,
input_1_axis_tdata, input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid, input_1_axis_tvalid,
input_1_axis_tlast, input_1_axis_tlast,
input_1_axis_tid,
input_1_axis_tdest,
input_1_axis_tuser, input_1_axis_tuser,
input_2_axis_tdata, input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid, input_2_axis_tvalid,
input_2_axis_tlast, input_2_axis_tlast,
input_2_axis_tid,
input_2_axis_tdest,
input_2_axis_tuser, input_2_axis_tuser,
input_3_axis_tdata, input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid, input_3_axis_tvalid,
input_3_axis_tlast, input_3_axis_tlast,
input_3_axis_tid,
input_3_axis_tdest,
input_3_axis_tuser, input_3_axis_tuser,
output_axis_tready, output_axis_tready,
enable, enable,
@ -104,8 +139,11 @@ initial begin
input_2_axis_tready, input_2_axis_tready,
input_3_axis_tready, input_3_axis_tready,
output_axis_tdata, output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid, output_axis_tvalid,
output_axis_tlast, output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser output_axis_tuser
); );
@ -115,37 +153,60 @@ initial begin
end end
axis_mux_4 #( axis_mux_4 #(
.DATA_WIDTH(DATA_WIDTH) .DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) )
UUT ( UUT (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
// AXI inputs // AXI inputs
.input_0_axis_tdata(input_0_axis_tdata), .input_0_axis_tdata(input_0_axis_tdata),
.input_0_axis_tkeep(input_0_axis_tkeep),
.input_0_axis_tvalid(input_0_axis_tvalid), .input_0_axis_tvalid(input_0_axis_tvalid),
.input_0_axis_tready(input_0_axis_tready), .input_0_axis_tready(input_0_axis_tready),
.input_0_axis_tlast(input_0_axis_tlast), .input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tid(input_0_axis_tid),
.input_0_axis_tdest(input_0_axis_tdest),
.input_0_axis_tuser(input_0_axis_tuser), .input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata), .input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tkeep(input_1_axis_tkeep),
.input_1_axis_tvalid(input_1_axis_tvalid), .input_1_axis_tvalid(input_1_axis_tvalid),
.input_1_axis_tready(input_1_axis_tready), .input_1_axis_tready(input_1_axis_tready),
.input_1_axis_tlast(input_1_axis_tlast), .input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tid(input_1_axis_tid),
.input_1_axis_tdest(input_1_axis_tdest),
.input_1_axis_tuser(input_1_axis_tuser), .input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata), .input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tkeep(input_2_axis_tkeep),
.input_2_axis_tvalid(input_2_axis_tvalid), .input_2_axis_tvalid(input_2_axis_tvalid),
.input_2_axis_tready(input_2_axis_tready), .input_2_axis_tready(input_2_axis_tready),
.input_2_axis_tlast(input_2_axis_tlast), .input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tid(input_2_axis_tid),
.input_2_axis_tdest(input_2_axis_tdest),
.input_2_axis_tuser(input_2_axis_tuser), .input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata), .input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tkeep(input_3_axis_tkeep),
.input_3_axis_tvalid(input_3_axis_tvalid), .input_3_axis_tvalid(input_3_axis_tvalid),
.input_3_axis_tready(input_3_axis_tready), .input_3_axis_tready(input_3_axis_tready),
.input_3_axis_tlast(input_3_axis_tlast), .input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tid(input_3_axis_tid),
.input_3_axis_tdest(input_3_axis_tdest),
.input_3_axis_tuser(input_3_axis_tuser), .input_3_axis_tuser(input_3_axis_tuser),
// AXI output // AXI output
.output_axis_tdata(output_axis_tdata), .output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid), .output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready), .output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast), .output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser), .output_axis_tuser(output_axis_tuser),
// Control // Control
.enable(enable), .enable(enable),

187
lib/axis/tb/test_axis_mux_64_4.py → lib/axis/tb/test_axis_mux_4_64.py
View File

@ -28,8 +28,8 @@ import os
import axis_ep import axis_ep
module = 'axis_mux_64_4' module = 'axis_mux_4'
testbench = 'test_%s' % module testbench = 'test_%s_64' % module
srcs = [] srcs = []
@ -44,7 +44,14 @@ def bench():
# Parameters # Parameters
DATA_WIDTH = 64 DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8) KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))
@ -52,25 +59,33 @@ def bench():
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_0_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_0_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_0_axis_tvalid = Signal(bool(0)) input_0_axis_tvalid = Signal(bool(0))
input_0_axis_tlast = Signal(bool(0)) input_0_axis_tlast = Signal(bool(0))
input_0_axis_tuser = Signal(bool(0)) input_0_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_0_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_0_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_1_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_1_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_1_axis_tvalid = Signal(bool(0)) input_1_axis_tvalid = Signal(bool(0))
input_1_axis_tlast = Signal(bool(0)) input_1_axis_tlast = Signal(bool(0))
input_1_axis_tuser = Signal(bool(0)) input_1_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_1_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_1_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_2_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_2_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_2_axis_tvalid = Signal(bool(0)) input_2_axis_tvalid = Signal(bool(0))
input_2_axis_tlast = Signal(bool(0)) input_2_axis_tlast = Signal(bool(0))
input_2_axis_tuser = Signal(bool(0)) input_2_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_2_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_2_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_3_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) input_3_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_3_axis_tvalid = Signal(bool(0)) input_3_axis_tvalid = Signal(bool(0))
input_3_axis_tlast = Signal(bool(0)) input_3_axis_tlast = Signal(bool(0))
input_3_axis_tuser = Signal(bool(0)) input_3_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_3_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_3_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0)) output_axis_tready = Signal(bool(0))
@ -84,10 +99,12 @@ def bench():
input_3_axis_tready = Signal(bool(0)) input_3_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:]) output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0)) output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0)) output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0)) output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks # sources and sinks
source_0_pause = Signal(bool(0)) source_0_pause = Signal(bool(0))
@ -106,6 +123,8 @@ def bench():
tvalid=input_0_axis_tvalid, tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready, tready=input_0_axis_tready,
tlast=input_0_axis_tlast, tlast=input_0_axis_tlast,
tid=input_0_axis_tid,
tdest=input_0_axis_tdest,
tuser=input_0_axis_tuser, tuser=input_0_axis_tuser,
pause=source_0_pause, pause=source_0_pause,
name='source_0' name='source_0'
@ -121,6 +140,8 @@ def bench():
tvalid=input_1_axis_tvalid, tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready, tready=input_1_axis_tready,
tlast=input_1_axis_tlast, tlast=input_1_axis_tlast,
tid=input_1_axis_tid,
tdest=input_1_axis_tdest,
tuser=input_1_axis_tuser, tuser=input_1_axis_tuser,
pause=source_1_pause, pause=source_1_pause,
name='source_1' name='source_1'
@ -136,6 +157,8 @@ def bench():
tvalid=input_2_axis_tvalid, tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready, tready=input_2_axis_tready,
tlast=input_2_axis_tlast, tlast=input_2_axis_tlast,
tid=input_2_axis_tid,
tdest=input_2_axis_tdest,
tuser=input_2_axis_tuser, tuser=input_2_axis_tuser,
pause=source_2_pause, pause=source_2_pause,
name='source_2' name='source_2'
@ -151,6 +174,8 @@ def bench():
tvalid=input_3_axis_tvalid, tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready, tready=input_3_axis_tready,
tlast=input_3_axis_tlast, tlast=input_3_axis_tlast,
tid=input_3_axis_tid,
tdest=input_3_axis_tdest,
tuser=input_3_axis_tuser, tuser=input_3_axis_tuser,
pause=source_3_pause, pause=source_3_pause,
name='source_3' name='source_3'
@ -166,6 +191,8 @@ def bench():
tvalid=output_axis_tvalid, tvalid=output_axis_tvalid,
tready=output_axis_tready, tready=output_axis_tready,
tlast=output_axis_tlast, tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser, tuser=output_axis_tuser,
pause=sink_pause, pause=sink_pause,
name='sink' name='sink'
@ -186,24 +213,32 @@ def bench():
input_0_axis_tvalid=input_0_axis_tvalid, input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready, input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast, input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tid=input_0_axis_tid,
input_0_axis_tdest=input_0_axis_tdest,
input_0_axis_tuser=input_0_axis_tuser, input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata, input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tkeep=input_1_axis_tkeep, input_1_axis_tkeep=input_1_axis_tkeep,
input_1_axis_tvalid=input_1_axis_tvalid, input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready, input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast, input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tid=input_1_axis_tid,
input_1_axis_tdest=input_1_axis_tdest,
input_1_axis_tuser=input_1_axis_tuser, input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata, input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tkeep=input_2_axis_tkeep, input_2_axis_tkeep=input_2_axis_tkeep,
input_2_axis_tvalid=input_2_axis_tvalid, input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready, input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast, input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tid=input_2_axis_tid,
input_2_axis_tdest=input_2_axis_tdest,
input_2_axis_tuser=input_2_axis_tuser, input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata, input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tkeep=input_3_axis_tkeep, input_3_axis_tkeep=input_3_axis_tkeep,
input_3_axis_tvalid=input_3_axis_tvalid, input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready, input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast, input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tid=input_3_axis_tid,
input_3_axis_tdest=input_3_axis_tdest,
input_3_axis_tuser=input_3_axis_tuser, input_3_axis_tuser=input_3_axis_tuser,
output_axis_tdata=output_axis_tdata, output_axis_tdata=output_axis_tdata,
@ -211,6 +246,8 @@ def bench():
output_axis_tvalid=output_axis_tvalid, output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready, output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast, output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser, output_axis_tuser=output_axis_tuser,
enable=enable, enable=enable,
@ -241,10 +278,15 @@ def bench():
select.next = 0 select.next = 0
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
source_0.send(test_frame) source_0.send(test_frame)
yield clk.posedge yield clk.posedge
@ -265,10 +307,15 @@ def bench():
select.next = 1 select.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=2,
dest=1
)
source_1.send(test_frame) source_1.send(test_frame)
yield clk.posedge yield clk.posedge
@ -289,14 +336,23 @@ def bench():
select.next = 0 select.next = 0
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=3,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=2
)
source_0.send(test_frame1) source_0.send(test_frame1)
source_0.send(test_frame2) source_0.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -322,14 +378,23 @@ def bench():
select.next = 1 select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=4,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2
)
source_1.send(test_frame1) source_1.send(test_frame1)
source_2.send(test_frame2) source_2.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -356,14 +421,23 @@ def bench():
select.next = 1 select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=5,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2
)
source_1.send(test_frame1) source_1.send(test_frame1)
source_2.send(test_frame2) source_2.send(test_frame2)
yield clk.posedge yield clk.posedge
@ -401,14 +475,23 @@ def bench():
select.next = 1 select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + test_frame1 = axis_ep.AXIStreamFrame(
b'\x5A\x51\x52\x53\x54\x55' + b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x80\x00' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') b'\x80\x00' +
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
b'\x5A\x51\x52\x53\x54\x55' + id=6,
b'\x80\x00' + dest=1
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10') )
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
source_1.send(test_frame1) source_1.send(test_frame1)
source_2.send(test_frame2) source_2.send(test_frame2)
yield clk.posedge yield clk.posedge

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