From 18ac7cc4f43b5d656caf0b39354f04cafeb3b05e Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 12 Oct 2023 23:26:08 -0700 Subject: [PATCH] fpga/mqnic: Merge AU200, AU250, and VCU1525 designs Signed-off-by: Alex Forencich --- fpga/mqnic/AU200/fpga_100g/README.md | 9 +- fpga/mqnic/AU200/fpga_100g/fpga.xdc | 6 +- .../fpga_100g/{fpga => fpga_AU200}/Makefile | 3 +- .../fpga_100g/{fpga => fpga_AU200}/config.tcl | 3 + .../Makefile | 3 +- .../config.tcl | 3 + .../fpga_100g/fpga_AU250}/Makefile | 3 +- .../fpga_100g/fpga_AU250}/config.tcl | 3 + .../fpga_AU250_app_dma_bench}/Makefile | 3 +- .../fpga_AU250_app_dma_bench}/config.tcl | 3 + .../fpga_100g/fpga_VCU1525}/Makefile | 2 +- .../fpga_100g/fpga_VCU1525}/config.tcl | 3 + .../fpga_VCU1525_app_dma_bench}/Makefile | 2 +- .../fpga_VCU1525_app_dma_bench}/config.tcl | 3 + .../{placement.xdc => placement_au200.xdc} | 0 .../fpga_100g/placement_au250.xdc} | 0 .../fpga_100g/placement_vcu1525.xdc} | 0 fpga/mqnic/AU200/fpga_100g/rtl/fpga.v | 239 +- fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v | 17 +- fpga/mqnic/AU200/fpga_25g/README.md | 9 +- fpga/mqnic/AU200/fpga_25g/fpga.xdc | 6 +- .../fpga_25g/{fpga => fpga_AU200}/Makefile | 3 +- .../fpga_25g/{fpga => fpga_AU200}/config.tcl | 1 + .../{fpga_10g => fpga_AU200_10g}/Makefile | 3 +- .../{fpga_10g => fpga_AU200_10g}/config.tcl | 1 + .../fpga_25g/fpga_AU250}/Makefile | 3 +- .../fpga_25g/fpga_AU250}/config.tcl | 1 + .../fpga_25g/fpga_AU250_10g}/Makefile | 3 +- .../fpga_25g/fpga_AU250_10g}/config.tcl | 1 + .../fpga_25g/fpga_VCU1525}/Makefile | 4 +- .../fpga_25g/fpga_VCU1525}/config.tcl | 1 + .../fpga_25g/fpga_VCU1525_10g}/Makefile | 4 +- .../fpga_25g/fpga_VCU1525_10g}/config.tcl | 1 + .../{placement.xdc => placement_au200.xdc} | 0 .../fpga_25g/placement_au250.xdc} | 0 .../fpga_25g/placement_vcu1525.xdc} | 0 fpga/mqnic/AU200/fpga_25g/rtl/fpga.v | 235 +- fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v | 15 +- fpga/mqnic/AU250/fpga_100g/Makefile | 25 - fpga/mqnic/AU250/fpga_100g/README.md | 24 - fpga/mqnic/AU250/fpga_100g/app | 1 - fpga/mqnic/AU250/fpga_100g/boot.xdc | 4 - fpga/mqnic/AU250/fpga_100g/cfgmclk.xdc | 4 - fpga/mqnic/AU250/fpga_100g/common/vivado.mk | 137 - fpga/mqnic/AU250/fpga_100g/fpga.xdc | 848 ------ fpga/mqnic/AU250/fpga_100g/ip/cmac_gty.tcl | 106 - fpga/mqnic/AU250/fpga_100g/ip/cmac_usplus.tcl | 21 - fpga/mqnic/AU250/fpga_100g/ip/cms.tcl | 16 - fpga/mqnic/AU250/fpga_100g/ip/ddr4_0.tcl | 17 - .../fpga_100g/ip/pcie4_uscale_plus_0.tcl | 34 - fpga/mqnic/AU250/fpga_100g/lib | 1 - fpga/mqnic/AU250/fpga_100g/rtl/common | 1 - .../AU250/fpga_100g/rtl/debounce_switch.v | 93 - fpga/mqnic/AU250/fpga_100g/rtl/fpga.v | 2441 ---------------- fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v | 1541 ---------- fpga/mqnic/AU250/fpga_100g/rtl/sync_signal.v | 62 - .../AU250/fpga_100g/tb/fpga_core/Makefile | 251 -- .../AU250/fpga_100g/tb/fpga_core/mqnic.py | 1 - .../fpga_100g/tb/fpga_core/test_fpga_core.py | 797 ------ fpga/mqnic/AU250/fpga_25g/Makefile | 25 - fpga/mqnic/AU250/fpga_25g/README.md | 23 - fpga/mqnic/AU250/fpga_25g/app | 1 - fpga/mqnic/AU250/fpga_25g/boot.xdc | 4 - fpga/mqnic/AU250/fpga_25g/cfgmclk.xdc | 4 - fpga/mqnic/AU250/fpga_25g/common/vivado.mk | 137 - fpga/mqnic/AU250/fpga_25g/fpga.xdc | 848 ------ fpga/mqnic/AU250/fpga_25g/ip/cms.tcl | 16 - fpga/mqnic/AU250/fpga_25g/ip/ddr4_0.tcl | 17 - fpga/mqnic/AU250/fpga_25g/ip/eth_xcvr_gty.tcl | 103 - .../AU250/fpga_25g/ip/pcie4_uscale_plus_0.tcl | 34 - fpga/mqnic/AU250/fpga_25g/lib | 1 - fpga/mqnic/AU250/fpga_25g/rtl/common | 1 - .../AU250/fpga_25g/rtl/debounce_switch.v | 93 - fpga/mqnic/AU250/fpga_25g/rtl/fpga.v | 2550 ----------------- fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v | 1740 ----------- fpga/mqnic/AU250/fpga_25g/rtl/sync_signal.v | 62 - .../AU250/fpga_25g/tb/fpga_core/Makefile | 261 -- .../AU250/fpga_25g/tb/fpga_core/mqnic.py | 1 - .../fpga_25g/tb/fpga_core/test_fpga_core.py | 812 ------ fpga/mqnic/VCU1525/fpga_100g/Makefile | 25 - fpga/mqnic/VCU1525/fpga_100g/README.md | 24 - fpga/mqnic/VCU1525/fpga_100g/app | 1 - fpga/mqnic/VCU1525/fpga_100g/boot.xdc | 4 - fpga/mqnic/VCU1525/fpga_100g/cfgmclk.xdc | 4 - fpga/mqnic/VCU1525/fpga_100g/common/vivado.mk | 137 - fpga/mqnic/VCU1525/fpga_100g/fpga.xdc | 833 ------ fpga/mqnic/VCU1525/fpga_100g/ip/cmac_gty.tcl | 106 - .../VCU1525/fpga_100g/ip/cmac_usplus.tcl | 21 - fpga/mqnic/VCU1525/fpga_100g/ip/ddr4_0.tcl | 17 - .../fpga_100g/ip/pcie4_uscale_plus_0.tcl | 34 - fpga/mqnic/VCU1525/fpga_100g/lib | 1 - fpga/mqnic/VCU1525/fpga_100g/rtl/common | 1 - .../VCU1525/fpga_100g/rtl/debounce_switch.v | 93 - fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v | 2261 --------------- fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v | 1464 ---------- .../mqnic/VCU1525/fpga_100g/rtl/sync_signal.v | 62 - .../VCU1525/fpga_100g/tb/fpga_core/Makefile | 251 -- .../VCU1525/fpga_100g/tb/fpga_core/mqnic.py | 1 - .../fpga_100g/tb/fpga_core/test_fpga_core.py | 795 ----- fpga/mqnic/VCU1525/fpga_25g/Makefile | 25 - fpga/mqnic/VCU1525/fpga_25g/README.md | 23 - fpga/mqnic/VCU1525/fpga_25g/app | 1 - fpga/mqnic/VCU1525/fpga_25g/boot.xdc | 4 - fpga/mqnic/VCU1525/fpga_25g/cfgmclk.xdc | 4 - fpga/mqnic/VCU1525/fpga_25g/common/vivado.mk | 137 - fpga/mqnic/VCU1525/fpga_25g/fpga.xdc | 833 ------ fpga/mqnic/VCU1525/fpga_25g/ip/ddr4_0.tcl | 17 - .../VCU1525/fpga_25g/ip/eth_xcvr_gty.tcl | 103 - .../fpga_25g/ip/pcie4_uscale_plus_0.tcl | 34 - fpga/mqnic/VCU1525/fpga_25g/lib | 1 - fpga/mqnic/VCU1525/fpga_25g/rtl/common | 1 - .../VCU1525/fpga_25g/rtl/debounce_switch.v | 93 - fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v | 2370 --------------- fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v | 1663 ----------- fpga/mqnic/VCU1525/fpga_25g/rtl/sync_signal.v | 62 - .../VCU1525/fpga_25g/tb/fpga_core/Makefile | 261 -- .../VCU1525/fpga_25g/tb/fpga_core/mqnic.py | 1 - .../fpga_25g/tb/fpga_core/test_fpga_core.py | 810 ------ 118 files changed, 340 insertions(+), 25992 deletions(-) rename fpga/mqnic/AU200/fpga_100g/{fpga => fpga_AU200}/Makefile (99%) rename fpga/mqnic/AU200/fpga_100g/{fpga => fpga_AU200}/config.tcl (99%) rename fpga/mqnic/AU200/fpga_100g/{fpga_app_dma_bench => fpga_AU200_app_dma_bench}/Makefile (99%) rename fpga/mqnic/AU200/fpga_100g/{fpga_app_dma_bench => fpga_AU200_app_dma_bench}/config.tcl (99%) rename fpga/mqnic/{AU250/fpga_100g/fpga => AU200/fpga_100g/fpga_AU250}/Makefile (99%) rename fpga/mqnic/{AU250/fpga_100g/fpga => AU200/fpga_100g/fpga_AU250}/config.tcl (99%) rename fpga/mqnic/{AU250/fpga_100g/fpga_app_dma_bench => AU200/fpga_100g/fpga_AU250_app_dma_bench}/Makefile (99%) rename fpga/mqnic/{AU250/fpga_100g/fpga_app_dma_bench => AU200/fpga_100g/fpga_AU250_app_dma_bench}/config.tcl (99%) rename fpga/mqnic/{VCU1525/fpga_100g/fpga => AU200/fpga_100g/fpga_VCU1525}/Makefile (99%) rename fpga/mqnic/{VCU1525/fpga_100g/fpga => AU200/fpga_100g/fpga_VCU1525}/config.tcl (99%) rename fpga/mqnic/{VCU1525/fpga_100g/fpga_app_dma_bench => AU200/fpga_100g/fpga_VCU1525_app_dma_bench}/Makefile (99%) rename fpga/mqnic/{VCU1525/fpga_100g/fpga_app_dma_bench => AU200/fpga_100g/fpga_VCU1525_app_dma_bench}/config.tcl (99%) rename fpga/mqnic/AU200/fpga_100g/{placement.xdc => placement_au200.xdc} (100%) rename fpga/mqnic/{AU250/fpga_100g/placement.xdc => AU200/fpga_100g/placement_au250.xdc} (100%) rename fpga/mqnic/{VCU1525/fpga_100g/placement.xdc => AU200/fpga_100g/placement_vcu1525.xdc} (100%) rename fpga/mqnic/AU200/fpga_25g/{fpga => fpga_AU200}/Makefile (99%) rename fpga/mqnic/AU200/fpga_25g/{fpga => fpga_AU200}/config.tcl (99%) rename fpga/mqnic/AU200/fpga_25g/{fpga_10g => fpga_AU200_10g}/Makefile (99%) rename fpga/mqnic/AU200/fpga_25g/{fpga_10g => fpga_AU200_10g}/config.tcl (99%) rename fpga/mqnic/{AU250/fpga_25g/fpga => AU200/fpga_25g/fpga_AU250}/Makefile (99%) rename fpga/mqnic/{AU250/fpga_25g/fpga => AU200/fpga_25g/fpga_AU250}/config.tcl (99%) rename fpga/mqnic/{AU250/fpga_25g/fpga_10g => AU200/fpga_25g/fpga_AU250_10g}/Makefile (99%) rename fpga/mqnic/{AU250/fpga_25g/fpga_10g => AU200/fpga_25g/fpga_AU250_10g}/config.tcl (99%) rename fpga/mqnic/{VCU1525/fpga_25g/fpga => AU200/fpga_25g/fpga_VCU1525}/Makefile (99%) rename fpga/mqnic/{VCU1525/fpga_25g/fpga => AU200/fpga_25g/fpga_VCU1525}/config.tcl (99%) rename fpga/mqnic/{VCU1525/fpga_25g/fpga_10g => AU200/fpga_25g/fpga_VCU1525_10g}/Makefile (99%) rename fpga/mqnic/{VCU1525/fpga_25g/fpga_10g => AU200/fpga_25g/fpga_VCU1525_10g}/config.tcl (99%) rename fpga/mqnic/AU200/fpga_25g/{placement.xdc => placement_au200.xdc} (100%) rename fpga/mqnic/{AU250/fpga_25g/placement.xdc => AU200/fpga_25g/placement_au250.xdc} (100%) rename fpga/mqnic/{VCU1525/fpga_25g/placement.xdc => AU200/fpga_25g/placement_vcu1525.xdc} (100%) delete mode 100644 fpga/mqnic/AU250/fpga_100g/Makefile delete mode 100644 fpga/mqnic/AU250/fpga_100g/README.md delete mode 120000 fpga/mqnic/AU250/fpga_100g/app delete mode 100644 fpga/mqnic/AU250/fpga_100g/boot.xdc delete mode 100644 fpga/mqnic/AU250/fpga_100g/cfgmclk.xdc delete mode 100644 fpga/mqnic/AU250/fpga_100g/common/vivado.mk delete mode 100644 fpga/mqnic/AU250/fpga_100g/fpga.xdc delete mode 100644 fpga/mqnic/AU250/fpga_100g/ip/cmac_gty.tcl delete mode 100644 fpga/mqnic/AU250/fpga_100g/ip/cmac_usplus.tcl delete mode 100644 fpga/mqnic/AU250/fpga_100g/ip/cms.tcl delete mode 100644 fpga/mqnic/AU250/fpga_100g/ip/ddr4_0.tcl delete mode 100644 fpga/mqnic/AU250/fpga_100g/ip/pcie4_uscale_plus_0.tcl delete mode 120000 fpga/mqnic/AU250/fpga_100g/lib delete mode 120000 fpga/mqnic/AU250/fpga_100g/rtl/common delete mode 100644 fpga/mqnic/AU250/fpga_100g/rtl/debounce_switch.v delete mode 100644 fpga/mqnic/AU250/fpga_100g/rtl/fpga.v delete mode 100644 fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v delete mode 100644 fpga/mqnic/AU250/fpga_100g/rtl/sync_signal.v delete mode 100644 fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile delete mode 120000 fpga/mqnic/AU250/fpga_100g/tb/fpga_core/mqnic.py delete mode 100644 fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py delete mode 100644 fpga/mqnic/AU250/fpga_25g/Makefile delete mode 100644 fpga/mqnic/AU250/fpga_25g/README.md delete mode 120000 fpga/mqnic/AU250/fpga_25g/app delete mode 100644 fpga/mqnic/AU250/fpga_25g/boot.xdc delete mode 100644 fpga/mqnic/AU250/fpga_25g/cfgmclk.xdc delete mode 100644 fpga/mqnic/AU250/fpga_25g/common/vivado.mk delete mode 100644 fpga/mqnic/AU250/fpga_25g/fpga.xdc delete mode 100644 fpga/mqnic/AU250/fpga_25g/ip/cms.tcl delete mode 100644 fpga/mqnic/AU250/fpga_25g/ip/ddr4_0.tcl delete mode 100644 fpga/mqnic/AU250/fpga_25g/ip/eth_xcvr_gty.tcl delete mode 100644 fpga/mqnic/AU250/fpga_25g/ip/pcie4_uscale_plus_0.tcl delete mode 120000 fpga/mqnic/AU250/fpga_25g/lib delete mode 120000 fpga/mqnic/AU250/fpga_25g/rtl/common delete mode 100644 fpga/mqnic/AU250/fpga_25g/rtl/debounce_switch.v delete mode 100644 fpga/mqnic/AU250/fpga_25g/rtl/fpga.v delete mode 100644 fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v delete mode 100644 fpga/mqnic/AU250/fpga_25g/rtl/sync_signal.v delete mode 100644 fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile delete mode 120000 fpga/mqnic/AU250/fpga_25g/tb/fpga_core/mqnic.py delete mode 100644 fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py delete mode 100644 fpga/mqnic/VCU1525/fpga_100g/Makefile delete mode 100644 fpga/mqnic/VCU1525/fpga_100g/README.md delete mode 120000 fpga/mqnic/VCU1525/fpga_100g/app delete mode 100644 fpga/mqnic/VCU1525/fpga_100g/boot.xdc delete mode 100644 fpga/mqnic/VCU1525/fpga_100g/cfgmclk.xdc delete mode 100644 fpga/mqnic/VCU1525/fpga_100g/common/vivado.mk delete mode 100644 fpga/mqnic/VCU1525/fpga_100g/fpga.xdc delete mode 100644 fpga/mqnic/VCU1525/fpga_100g/ip/cmac_gty.tcl delete mode 100644 fpga/mqnic/VCU1525/fpga_100g/ip/cmac_usplus.tcl delete mode 100644 fpga/mqnic/VCU1525/fpga_100g/ip/ddr4_0.tcl delete mode 100644 fpga/mqnic/VCU1525/fpga_100g/ip/pcie4_uscale_plus_0.tcl delete mode 120000 fpga/mqnic/VCU1525/fpga_100g/lib delete mode 120000 fpga/mqnic/VCU1525/fpga_100g/rtl/common delete mode 100644 fpga/mqnic/VCU1525/fpga_100g/rtl/debounce_switch.v delete mode 100644 fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v delete mode 100644 fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v delete mode 100644 fpga/mqnic/VCU1525/fpga_100g/rtl/sync_signal.v delete mode 100644 fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile delete mode 120000 fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/mqnic.py delete mode 100644 fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py delete mode 100644 fpga/mqnic/VCU1525/fpga_25g/Makefile delete mode 100644 fpga/mqnic/VCU1525/fpga_25g/README.md delete mode 120000 fpga/mqnic/VCU1525/fpga_25g/app delete mode 100644 fpga/mqnic/VCU1525/fpga_25g/boot.xdc delete mode 100644 fpga/mqnic/VCU1525/fpga_25g/cfgmclk.xdc delete mode 100644 fpga/mqnic/VCU1525/fpga_25g/common/vivado.mk delete mode 100644 fpga/mqnic/VCU1525/fpga_25g/fpga.xdc delete mode 100644 fpga/mqnic/VCU1525/fpga_25g/ip/ddr4_0.tcl delete mode 100644 fpga/mqnic/VCU1525/fpga_25g/ip/eth_xcvr_gty.tcl delete mode 100644 fpga/mqnic/VCU1525/fpga_25g/ip/pcie4_uscale_plus_0.tcl delete mode 120000 fpga/mqnic/VCU1525/fpga_25g/lib delete mode 120000 fpga/mqnic/VCU1525/fpga_25g/rtl/common delete mode 100644 fpga/mqnic/VCU1525/fpga_25g/rtl/debounce_switch.v delete mode 100644 fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v delete mode 100644 fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v delete mode 100644 fpga/mqnic/VCU1525/fpga_25g/rtl/sync_signal.v delete mode 100644 fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile delete mode 120000 fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/mqnic.py delete mode 100644 fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py diff --git a/fpga/mqnic/AU200/fpga_100g/README.md b/fpga/mqnic/AU200/fpga_100g/README.md index 60d77b3d7..ac27f400e 100644 --- a/fpga/mqnic/AU200/fpga_100g/README.md +++ b/fpga/mqnic/AU200/fpga_100g/README.md @@ -1,10 +1,13 @@ -# Corundum mqnic for Alveo U200 +# Corundum mqnic for Alveo U200/Alveo U250/VCU1525 ## Introduction -This design targets the Xilinx Alveo U200 FPGA board. +This design targets the Xilinx Alveo U200/Alveo U250/VCU1525 FPGA board. -* FPGA: xcu200-fsgd2104-2-e +* FPGA + * AU200: xcu200-fsgd2104-2-e + * AU250: xcu250-fsgd2104-2-e + * VCU1525: xcvu9p-fsgd2104-2L-e * MAC: Xilinx 100G CMAC * PHY: 100G CAUI-4 CMAC and internal GTY transceivers * RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM) diff --git a/fpga/mqnic/AU200/fpga_100g/fpga.xdc b/fpga/mqnic/AU200/fpga_100g/fpga.xdc index 73f7243bc..050ad2d3b 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga.xdc +++ b/fpga/mqnic/AU200/fpga_100g/fpga.xdc @@ -1,5 +1,7 @@ -# XDC constraints for the Xilinx Alveo U200 board -# part: xcu200-fsgd2104-2-e +# XDC constraints for Xilinx AU200/AU250/VCU1525 +# AU200 part: xcu200-fsgd2104-2-e +# AU250 part: xcu250-figd2104-2-e +# VCU1525 part: xcvu9p-fsgd2104-2L-e # General configuration set_property CFGBVS GND [current_design] diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga_AU200/Makefile similarity index 99% rename from fpga/mqnic/AU200/fpga_100g/fpga/Makefile rename to fpga/mqnic/AU200/fpga_100g/fpga_AU200/Makefile index 13012d692..0e8ee0bda 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga_AU200/Makefile @@ -116,7 +116,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES += placement_au200.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl @@ -189,4 +189,3 @@ flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm echo "boot_hw_device [current_hw_device]" >> flash.tcl echo "exit" >> flash.tcl vivado -nojournal -nolog -mode batch -source flash.tcl - diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_100g/fpga_AU200/config.tcl similarity index 99% rename from fpga/mqnic/AU200/fpga_100g/fpga/config.tcl rename to fpga/mqnic/AU200/fpga_100g/fpga_AU200/config.tcl index 51ac43431..c086d1e30 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_100g/fpga_AU200/config.tcl @@ -54,6 +54,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params CMS_ENABLE "1" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga_AU200_app_dma_bench/Makefile similarity index 99% rename from fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/Makefile rename to fpga/mqnic/AU200/fpga_100g/fpga_AU200_app_dma_bench/Makefile index b711ebaf6..a2342a13b 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga_AU200_app_dma_bench/Makefile @@ -123,7 +123,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES += placement_au200.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl @@ -200,4 +200,3 @@ flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm echo "boot_hw_device [current_hw_device]" >> flash.tcl echo "exit" >> flash.tcl vivado -nojournal -nolog -mode batch -source flash.tcl - diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU200/fpga_100g/fpga_AU200_app_dma_bench/config.tcl similarity index 99% rename from fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl rename to fpga/mqnic/AU200/fpga_100g/fpga_AU200_app_dma_bench/config.tcl index 8ef19482b..d23679333 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/AU200/fpga_100g/fpga_AU200_app_dma_bench/config.tcl @@ -54,6 +54,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params CMS_ENABLE "1" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga_AU250/Makefile similarity index 99% rename from fpga/mqnic/AU250/fpga_100g/fpga/Makefile rename to fpga/mqnic/AU200/fpga_100g/fpga_AU250/Makefile index 6b7fedba4..31887df11 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga_AU250/Makefile @@ -116,7 +116,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES += placement_au250.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl @@ -189,4 +189,3 @@ flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm echo "boot_hw_device [current_hw_device]" >> flash.tcl echo "exit" >> flash.tcl vivado -nojournal -nolog -mode batch -source flash.tcl - diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_100g/fpga_AU250/config.tcl similarity index 99% rename from fpga/mqnic/AU250/fpga_100g/fpga/config.tcl rename to fpga/mqnic/AU200/fpga_100g/fpga_AU250/config.tcl index 4dbd0886e..bf69da1b9 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_100g/fpga_AU250/config.tcl @@ -54,6 +54,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params CMS_ENABLE "1" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" diff --git a/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga_AU250_app_dma_bench/Makefile similarity index 99% rename from fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/Makefile rename to fpga/mqnic/AU200/fpga_100g/fpga_AU250_app_dma_bench/Makefile index 26a343038..6df9dc60b 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga_AU250_app_dma_bench/Makefile @@ -123,7 +123,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES += placement_au250.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl @@ -200,4 +200,3 @@ flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm echo "boot_hw_device [current_hw_device]" >> flash.tcl echo "exit" >> flash.tcl vivado -nojournal -nolog -mode batch -source flash.tcl - diff --git a/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU200/fpga_100g/fpga_AU250_app_dma_bench/config.tcl similarity index 99% rename from fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl rename to fpga/mqnic/AU200/fpga_100g/fpga_AU250_app_dma_bench/config.tcl index abfea2b14..a0e4b068b 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/AU200/fpga_100g/fpga_AU250_app_dma_bench/config.tcl @@ -54,6 +54,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params CMS_ENABLE "1" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525/Makefile similarity index 99% rename from fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile rename to fpga/mqnic/AU200/fpga_100g/fpga_VCU1525/Makefile index a877125e0..1757b983f 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525/Makefile @@ -113,7 +113,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES += placement_vcu1525.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525/config.tcl similarity index 99% rename from fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl rename to fpga/mqnic/AU200/fpga_100g/fpga_VCU1525/config.tcl index 740c0574e..098d15a86 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525/config.tcl @@ -54,6 +54,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params CMS_ENABLE "0" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile similarity index 99% rename from fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/Makefile rename to fpga/mqnic/AU200/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile index 346cfb50d..21e8e675e 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile @@ -120,7 +120,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES += placement_vcu1525.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525_app_dma_bench/config.tcl similarity index 99% rename from fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/config.tcl rename to fpga/mqnic/AU200/fpga_100g/fpga_VCU1525_app_dma_bench/config.tcl index bac18153f..a64a34152 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525_app_dma_bench/config.tcl @@ -54,6 +54,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params CMS_ENABLE "0" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" diff --git a/fpga/mqnic/AU200/fpga_100g/placement.xdc b/fpga/mqnic/AU200/fpga_100g/placement_au200.xdc similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/placement.xdc rename to fpga/mqnic/AU200/fpga_100g/placement_au200.xdc diff --git a/fpga/mqnic/AU250/fpga_100g/placement.xdc b/fpga/mqnic/AU200/fpga_100g/placement_au250.xdc similarity index 100% rename from fpga/mqnic/AU250/fpga_100g/placement.xdc rename to fpga/mqnic/AU200/fpga_100g/placement_au250.xdc diff --git a/fpga/mqnic/VCU1525/fpga_100g/placement.xdc b/fpga/mqnic/AU200/fpga_100g/placement_vcu1525.xdc similarity index 100% rename from fpga/mqnic/VCU1525/fpga_100g/placement.xdc rename to fpga/mqnic/AU200/fpga_100g/placement_vcu1525.xdc diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v index ab4acad81..0d2f8dbb6 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v @@ -24,6 +24,9 @@ module fpga # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter CMS_ENABLE = 1, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -674,113 +677,136 @@ wire [1:0] axil_cms_rresp; wire axil_cms_rvalid; wire axil_cms_rready; -wire [17:0] axil_cms_awaddr_int; -wire [2:0] axil_cms_awprot_int; -wire axil_cms_awvalid_int; -wire axil_cms_awready_int; -wire [31:0] axil_cms_wdata_int; -wire [3:0] axil_cms_wstrb_int; -wire axil_cms_wvalid_int; -wire axil_cms_wready_int; -wire [1:0] axil_cms_bresp_int; -wire axil_cms_bvalid_int; -wire axil_cms_bready_int; -wire [17:0] axil_cms_araddr_int; -wire [2:0] axil_cms_arprot_int; -wire axil_cms_arvalid_int; -wire axil_cms_arready_int; -wire [31:0] axil_cms_rdata_int; -wire [1:0] axil_cms_rresp_int; -wire axil_cms_rvalid_int; -wire axil_cms_rready_int; +generate -axil_cdc #( - .DATA_WIDTH(32), - .ADDR_WIDTH(18) -) -cms_axil_cdc_inst ( - .s_clk(axil_cms_clk), - .s_rst(axil_cms_rst), - .s_axil_awaddr(axil_cms_awaddr), - .s_axil_awprot(axil_cms_awprot), - .s_axil_awvalid(axil_cms_awvalid), - .s_axil_awready(axil_cms_awready), - .s_axil_wdata(axil_cms_wdata), - .s_axil_wstrb(axil_cms_wstrb), - .s_axil_wvalid(axil_cms_wvalid), - .s_axil_wready(axil_cms_wready), - .s_axil_bresp(axil_cms_bresp), - .s_axil_bvalid(axil_cms_bvalid), - .s_axil_bready(axil_cms_bready), - .s_axil_araddr(axil_cms_araddr), - .s_axil_arprot(axil_cms_arprot), - .s_axil_arvalid(axil_cms_arvalid), - .s_axil_arready(axil_cms_arready), - .s_axil_rdata(axil_cms_rdata), - .s_axil_rresp(axil_cms_rresp), - .s_axil_rvalid(axil_cms_rvalid), - .s_axil_rready(axil_cms_rready), - .m_clk(clk_50mhz_int), - .m_rst(rst_50mhz_int), - .m_axil_awaddr(axil_cms_awaddr_int), - .m_axil_awprot(axil_cms_awprot_int), - .m_axil_awvalid(axil_cms_awvalid_int), - .m_axil_awready(axil_cms_awready_int), - .m_axil_wdata(axil_cms_wdata_int), - .m_axil_wstrb(axil_cms_wstrb_int), - .m_axil_wvalid(axil_cms_wvalid_int), - .m_axil_wready(axil_cms_wready_int), - .m_axil_bresp(axil_cms_bresp_int), - .m_axil_bvalid(axil_cms_bvalid_int), - .m_axil_bready(axil_cms_bready_int), - .m_axil_araddr(axil_cms_araddr_int), - .m_axil_arprot(axil_cms_arprot_int), - .m_axil_arvalid(axil_cms_arvalid_int), - .m_axil_arready(axil_cms_arready_int), - .m_axil_rdata(axil_cms_rdata_int), - .m_axil_rresp(axil_cms_rresp_int), - .m_axil_rvalid(axil_cms_rvalid_int), - .m_axil_rready(axil_cms_rready_int) -); +if (CMS_ENABLE) begin : cms -cms_wrapper -cms_inst ( - .aclk_ctrl_0(clk_50mhz_int), - .aresetn_ctrl_0(~rst_50mhz_int), - .interrupt_host_0(), - .qsfp0_int_l_0(qsfp0_intl), - .qsfp0_lpmode_0(), - .qsfp0_modprs_l_0(qsfp0_modprsl), - .qsfp0_modsel_l_0(), - .qsfp0_reset_l_0(), - .qsfp1_int_l_0(qsfp1_intl), - .qsfp1_lpmode_0(), - .qsfp1_modprs_l_0(qsfp1_modprsl), - .qsfp1_modsel_l_0(), - .qsfp1_reset_l_0(), - .s_axi_ctrl_0_araddr(axil_cms_araddr_int), - .s_axi_ctrl_0_arprot(axil_cms_arprot_int), - .s_axi_ctrl_0_arready(axil_cms_arready_int), - .s_axi_ctrl_0_arvalid(axil_cms_arvalid_int), - .s_axi_ctrl_0_awaddr(axil_cms_awaddr_int), - .s_axi_ctrl_0_awprot(axil_cms_awprot_int), - .s_axi_ctrl_0_awready(axil_cms_awready_int), - .s_axi_ctrl_0_awvalid(axil_cms_awvalid_int), - .s_axi_ctrl_0_bready(axil_cms_bready_int), - .s_axi_ctrl_0_bresp(axil_cms_bresp_int), - .s_axi_ctrl_0_bvalid(axil_cms_bvalid_int), - .s_axi_ctrl_0_rdata(axil_cms_rdata_int), - .s_axi_ctrl_0_rready(axil_cms_rready_int), - .s_axi_ctrl_0_rresp(axil_cms_rresp_int), - .s_axi_ctrl_0_rvalid(axil_cms_rvalid_int), - .s_axi_ctrl_0_wdata(axil_cms_wdata_int), - .s_axi_ctrl_0_wready(axil_cms_wready_int), - .s_axi_ctrl_0_wstrb(axil_cms_wstrb_int), - .s_axi_ctrl_0_wvalid(axil_cms_wvalid_int), - .satellite_gpio_0(msp_gpio), - .satellite_uart_0_rxd(msp_uart_rxd), - .satellite_uart_0_txd(msp_uart_txd) -); + wire [17:0] axil_cms_awaddr_int; + wire [2:0] axil_cms_awprot_int; + wire axil_cms_awvalid_int; + wire axil_cms_awready_int; + wire [31:0] axil_cms_wdata_int; + wire [3:0] axil_cms_wstrb_int; + wire axil_cms_wvalid_int; + wire axil_cms_wready_int; + wire [1:0] axil_cms_bresp_int; + wire axil_cms_bvalid_int; + wire axil_cms_bready_int; + wire [17:0] axil_cms_araddr_int; + wire [2:0] axil_cms_arprot_int; + wire axil_cms_arvalid_int; + wire axil_cms_arready_int; + wire [31:0] axil_cms_rdata_int; + wire [1:0] axil_cms_rresp_int; + wire axil_cms_rvalid_int; + wire axil_cms_rready_int; + + axil_cdc #( + .DATA_WIDTH(32), + .ADDR_WIDTH(18) + ) + cms_axil_cdc_inst ( + .s_clk(axil_cms_clk), + .s_rst(axil_cms_rst), + .s_axil_awaddr(axil_cms_awaddr), + .s_axil_awprot(axil_cms_awprot), + .s_axil_awvalid(axil_cms_awvalid), + .s_axil_awready(axil_cms_awready), + .s_axil_wdata(axil_cms_wdata), + .s_axil_wstrb(axil_cms_wstrb), + .s_axil_wvalid(axil_cms_wvalid), + .s_axil_wready(axil_cms_wready), + .s_axil_bresp(axil_cms_bresp), + .s_axil_bvalid(axil_cms_bvalid), + .s_axil_bready(axil_cms_bready), + .s_axil_araddr(axil_cms_araddr), + .s_axil_arprot(axil_cms_arprot), + .s_axil_arvalid(axil_cms_arvalid), + .s_axil_arready(axil_cms_arready), + .s_axil_rdata(axil_cms_rdata), + .s_axil_rresp(axil_cms_rresp), + .s_axil_rvalid(axil_cms_rvalid), + .s_axil_rready(axil_cms_rready), + .m_clk(clk_50mhz_int), + .m_rst(rst_50mhz_int), + .m_axil_awaddr(axil_cms_awaddr_int), + .m_axil_awprot(axil_cms_awprot_int), + .m_axil_awvalid(axil_cms_awvalid_int), + .m_axil_awready(axil_cms_awready_int), + .m_axil_wdata(axil_cms_wdata_int), + .m_axil_wstrb(axil_cms_wstrb_int), + .m_axil_wvalid(axil_cms_wvalid_int), + .m_axil_wready(axil_cms_wready_int), + .m_axil_bresp(axil_cms_bresp_int), + .m_axil_bvalid(axil_cms_bvalid_int), + .m_axil_bready(axil_cms_bready_int), + .m_axil_araddr(axil_cms_araddr_int), + .m_axil_arprot(axil_cms_arprot_int), + .m_axil_arvalid(axil_cms_arvalid_int), + .m_axil_arready(axil_cms_arready_int), + .m_axil_rdata(axil_cms_rdata_int), + .m_axil_rresp(axil_cms_rresp_int), + .m_axil_rvalid(axil_cms_rvalid_int), + .m_axil_rready(axil_cms_rready_int) + ); + + cms_wrapper + cms_inst ( + .aclk_ctrl_0(clk_50mhz_int), + .aresetn_ctrl_0(~rst_50mhz_int), + .interrupt_host_0(), + .qsfp0_int_l_0(qsfp0_intl), + .qsfp0_lpmode_0(), + .qsfp0_modprs_l_0(qsfp0_modprsl), + .qsfp0_modsel_l_0(), + .qsfp0_reset_l_0(), + .qsfp1_int_l_0(qsfp1_intl), + .qsfp1_lpmode_0(), + .qsfp1_modprs_l_0(qsfp1_modprsl), + .qsfp1_modsel_l_0(), + .qsfp1_reset_l_0(), + .s_axi_ctrl_0_araddr(axil_cms_araddr_int), + .s_axi_ctrl_0_arprot(axil_cms_arprot_int), + .s_axi_ctrl_0_arready(axil_cms_arready_int), + .s_axi_ctrl_0_arvalid(axil_cms_arvalid_int), + .s_axi_ctrl_0_awaddr(axil_cms_awaddr_int), + .s_axi_ctrl_0_awprot(axil_cms_awprot_int), + .s_axi_ctrl_0_awready(axil_cms_awready_int), + .s_axi_ctrl_0_awvalid(axil_cms_awvalid_int), + .s_axi_ctrl_0_bready(axil_cms_bready_int), + .s_axi_ctrl_0_bresp(axil_cms_bresp_int), + .s_axi_ctrl_0_bvalid(axil_cms_bvalid_int), + .s_axi_ctrl_0_rdata(axil_cms_rdata_int), + .s_axi_ctrl_0_rready(axil_cms_rready_int), + .s_axi_ctrl_0_rresp(axil_cms_rresp_int), + .s_axi_ctrl_0_rvalid(axil_cms_rvalid_int), + .s_axi_ctrl_0_wdata(axil_cms_wdata_int), + .s_axi_ctrl_0_wready(axil_cms_wready_int), + .s_axi_ctrl_0_wstrb(axil_cms_wstrb_int), + .s_axi_ctrl_0_wvalid(axil_cms_wvalid_int), + .satellite_gpio_0(msp_gpio), + .satellite_uart_0_rxd(msp_uart_rxd), + .satellite_uart_0_txd(msp_uart_txd) + ); + +end else begin + + assign axil_cms_awready = 0; + assign axil_cms_wdata = 0; + assign axil_cms_wstrb = 0; + assign axil_cms_wvalid = 0; + assign axil_cms_bresp = 0; + assign axil_cms_bvalid = 0; + assign axil_cms_arready = 0; + assign axil_cms_rdata = 0; + assign axil_cms_rresp = 0; + assign axil_cms_rvalid = 0; + + assign msp_uart_txd = 1'bz; + +end + +endgenerate // configure SI5335 clock generators reg qsfp_refclk_reset_reg = 1'b1; @@ -2001,6 +2027,9 @@ fpga_core #( .GIT_HASH(GIT_HASH), .RELEASE_INFO(RELEASE_INFO), + // Board configuration + .CMS_ENABLE(CMS_ENABLE), + // Structural configuration .IF_COUNT(IF_COUNT), .PORTS_PER_IF(PORTS_PER_IF), diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v index aa98d6f89..facbcbf67 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v @@ -24,6 +24,9 @@ module fpga_core # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter CMS_ENABLE = 1, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -655,14 +658,14 @@ always @(posedge clk_250mhz) begin // Alveo BMC RBB+8'h4C: begin // BMC ctrl: Addr - if (!m_axil_cms_arvalid && !m_axil_cms_awvalid) begin + if (CMS_ENABLE && !m_axil_cms_arvalid && !m_axil_cms_awvalid) begin m_axil_cms_addr_reg <= ctrl_reg_wr_data; m_axil_cms_arvalid_reg <= 1'b1; end end RBB+8'h50: begin // BMC ctrl: Data - if (!m_axil_cms_wvalid) begin + if (CMS_ENABLE && !m_axil_cms_wvalid) begin m_axil_cms_awvalid_reg <= 1'b1; m_axil_cms_wdata_reg <= ctrl_reg_wr_data; m_axil_cms_wstrb_reg <= ctrl_reg_wr_strb; @@ -722,11 +725,11 @@ always @(posedge clk_250mhz) begin ctrl_reg_rd_data_reg[17] <= qspi_cs; end // Alveo BMC - RBB+8'h40: ctrl_reg_rd_data_reg <= 32'h0000C140; // BMC ctrl: Type - RBB+8'h44: ctrl_reg_rd_data_reg <= 32'h00000100; // BMC ctrl: Version - RBB+8'h48: ctrl_reg_rd_data_reg <= RB_DRP_QSFP0_BASE; // BMC ctrl: Next header - RBB+8'h4C: ctrl_reg_rd_data_reg <= m_axil_cms_addr_reg; // BMC ctrl: Addr - RBB+8'h50: ctrl_reg_rd_data_reg <= m_axil_cms_rdata; // BMC ctrl: Data + RBB+8'h40: ctrl_reg_rd_data_reg <= CMS_ENABLE ? 32'h0000C140 : 0; // BMC ctrl: Type + RBB+8'h44: ctrl_reg_rd_data_reg <= CMS_ENABLE ? 32'h00000100 : 0; // BMC ctrl: Version + RBB+8'h48: ctrl_reg_rd_data_reg <= RB_DRP_QSFP0_BASE; // BMC ctrl: Next header + RBB+8'h4C: ctrl_reg_rd_data_reg <= CMS_ENABLE ? m_axil_cms_addr_reg : 0; // BMC ctrl: Addr + RBB+8'h50: ctrl_reg_rd_data_reg <= CMS_ENABLE ? m_axil_cms_rdata : 0; // BMC ctrl: Data default: ctrl_reg_rd_ack_reg <= 1'b0; endcase end diff --git a/fpga/mqnic/AU200/fpga_25g/README.md b/fpga/mqnic/AU200/fpga_25g/README.md index 61b7f1a2b..db96227e9 100644 --- a/fpga/mqnic/AU200/fpga_25g/README.md +++ b/fpga/mqnic/AU200/fpga_25g/README.md @@ -1,10 +1,13 @@ -# Corundum mqnic for Alveo U200 +# Corundum mqnic for Alveo U200/Alveo U250/VCU1525 ## Introduction -This design targets the Xilinx Alveo U200 FPGA board. +This design targets the Xilinx Alveo U200/Alveo U250/VCU1525 FPGA board. -* FPGA: xcu200-fsgd2104-2-e +* FPGA + * AU200: xcu200-fsgd2104-2-e + * AU250: xcu250-fsgd2104-2-e + * VCU1525: xcvu9p-fsgd2104-2L-e * PHY: 10G BASE-R PHY IP core and internal GTY transceiver * RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM) diff --git a/fpga/mqnic/AU200/fpga_25g/fpga.xdc b/fpga/mqnic/AU200/fpga_25g/fpga.xdc index 73f7243bc..050ad2d3b 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga.xdc +++ b/fpga/mqnic/AU200/fpga_25g/fpga.xdc @@ -1,5 +1,7 @@ -# XDC constraints for the Xilinx Alveo U200 board -# part: xcu200-fsgd2104-2-e +# XDC constraints for Xilinx AU200/AU250/VCU1525 +# AU200 part: xcu200-fsgd2104-2-e +# AU250 part: xcu250-figd2104-2-e +# VCU1525 part: xcvu9p-fsgd2104-2L-e # General configuration set_property CFGBVS GND [current_design] diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_AU200/Makefile similarity index 99% rename from fpga/mqnic/AU200/fpga_25g/fpga/Makefile rename to fpga/mqnic/AU200/fpga_25g/fpga_AU200/Makefile index 363f3d8a6..dc7930da4 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga_AU200/Makefile @@ -135,7 +135,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES += placement_au200.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl @@ -207,4 +207,3 @@ flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm echo "boot_hw_device [current_hw_device]" >> flash.tcl echo "exit" >> flash.tcl vivado -nojournal -nolog -mode batch -source flash.tcl - diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga_AU200/config.tcl similarity index 99% rename from fpga/mqnic/AU200/fpga_25g/fpga/config.tcl rename to fpga/mqnic/AU200/fpga_25g/fpga_AU200/config.tcl index 07945fddd..8b6c0fa50 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga_AU200/config.tcl @@ -55,6 +55,7 @@ dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] # Board configuration +dict set params CMS_ENABLE "1" dict set params TDMA_BER_ENABLE "0" # Transceiver configuration diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_AU200_10g/Makefile similarity index 99% rename from fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile rename to fpga/mqnic/AU200/fpga_25g/fpga_AU200_10g/Makefile index 363f3d8a6..dc7930da4 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga_AU200_10g/Makefile @@ -135,7 +135,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES += placement_au200.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl @@ -207,4 +207,3 @@ flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm echo "boot_hw_device [current_hw_device]" >> flash.tcl echo "exit" >> flash.tcl vivado -nojournal -nolog -mode batch -source flash.tcl - diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga_AU200_10g/config.tcl similarity index 99% rename from fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl rename to fpga/mqnic/AU200/fpga_25g/fpga_AU200_10g/config.tcl index 8d2b1edea..37ca0cef2 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga_AU200_10g/config.tcl @@ -55,6 +55,7 @@ dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] # Board configuration +dict set params CMS_ENABLE "1" dict set params TDMA_BER_ENABLE "0" # Transceiver configuration diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_AU250/Makefile similarity index 99% rename from fpga/mqnic/AU250/fpga_25g/fpga/Makefile rename to fpga/mqnic/AU200/fpga_25g/fpga_AU250/Makefile index ceb90616f..80eee5316 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga_AU250/Makefile @@ -135,7 +135,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES += placement_au250.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl @@ -207,4 +207,3 @@ flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm echo "boot_hw_device [current_hw_device]" >> flash.tcl echo "exit" >> flash.tcl vivado -nojournal -nolog -mode batch -source flash.tcl - diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga_AU250/config.tcl similarity index 99% rename from fpga/mqnic/AU250/fpga_25g/fpga/config.tcl rename to fpga/mqnic/AU200/fpga_25g/fpga_AU250/config.tcl index bc8ac76ed..d83fc9fe0 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga_AU250/config.tcl @@ -55,6 +55,7 @@ dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] # Board configuration +dict set params CMS_ENABLE "1" dict set params TDMA_BER_ENABLE "0" # Transceiver configuration diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_AU250_10g/Makefile similarity index 99% rename from fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile rename to fpga/mqnic/AU200/fpga_25g/fpga_AU250_10g/Makefile index ceb90616f..80eee5316 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga_AU250_10g/Makefile @@ -135,7 +135,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES += placement_au250.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl @@ -207,4 +207,3 @@ flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm echo "boot_hw_device [current_hw_device]" >> flash.tcl echo "exit" >> flash.tcl vivado -nojournal -nolog -mode batch -source flash.tcl - diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga_AU250_10g/config.tcl similarity index 99% rename from fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl rename to fpga/mqnic/AU200/fpga_25g/fpga_AU250_10g/config.tcl index 7f7c1abdc..4695faa57 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga_AU250_10g/config.tcl @@ -55,6 +55,7 @@ dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] # Board configuration +dict set params CMS_ENABLE "1" dict set params TDMA_BER_ENABLE "0" # Transceiver configuration diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525/Makefile similarity index 99% rename from fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile rename to fpga/mqnic/AU200/fpga_25g/fpga_VCU1525/Makefile index 01aea6547..148471b46 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525/Makefile @@ -132,7 +132,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES += placement_vcu1525.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl @@ -162,7 +162,7 @@ include ../common/vivado.mk echo "set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]" >> generate_fallback_bit.tcl echo "set_property BITSTREAM.CONFIG.TIMER_CFG 0x03000000 [current_design]" >> generate_fallback_bit.tcl echo "set_property BITSTREAM.CONFIG.NEXT_CONFIG_REBOOT ENABLE [current_design]" >> generate_fallback_bit.tcl - echo "set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x02000000 [current_design]" >> generate_fallback_bit.tcl + echo "set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x04000000 [current_design]" >> generate_fallback_bit.tcl echo "endgroup" >> generate_fallback_bit.tcl echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl echo "undo" >> generate_fallback_bit.tcl diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525/config.tcl similarity index 99% rename from fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl rename to fpga/mqnic/AU200/fpga_25g/fpga_VCU1525/config.tcl index 8c85768a4..c3326fc94 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525/config.tcl @@ -55,6 +55,7 @@ dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] # Board configuration +dict set params CMS_ENABLE "0" dict set params TDMA_BER_ENABLE "0" # Transceiver configuration diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525_10g/Makefile similarity index 99% rename from fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile rename to fpga/mqnic/AU200/fpga_25g/fpga_VCU1525_10g/Makefile index 01aea6547..148471b46 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525_10g/Makefile @@ -132,7 +132,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files XDC_FILES = fpga.xdc -XDC_FILES += placement.xdc +XDC_FILES += placement_vcu1525.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl @@ -162,7 +162,7 @@ include ../common/vivado.mk echo "set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]" >> generate_fallback_bit.tcl echo "set_property BITSTREAM.CONFIG.TIMER_CFG 0x03000000 [current_design]" >> generate_fallback_bit.tcl echo "set_property BITSTREAM.CONFIG.NEXT_CONFIG_REBOOT ENABLE [current_design]" >> generate_fallback_bit.tcl - echo "set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x02000000 [current_design]" >> generate_fallback_bit.tcl + echo "set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x04000000 [current_design]" >> generate_fallback_bit.tcl echo "endgroup" >> generate_fallback_bit.tcl echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl echo "undo" >> generate_fallback_bit.tcl diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525_10g/config.tcl similarity index 99% rename from fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl rename to fpga/mqnic/AU200/fpga_25g/fpga_VCU1525_10g/config.tcl index 35dd023ce..4433af012 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525_10g/config.tcl @@ -55,6 +55,7 @@ dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] # Board configuration +dict set params CMS_ENABLE "0" dict set params TDMA_BER_ENABLE "0" # Transceiver configuration diff --git a/fpga/mqnic/AU200/fpga_25g/placement.xdc b/fpga/mqnic/AU200/fpga_25g/placement_au200.xdc similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/placement.xdc rename to fpga/mqnic/AU200/fpga_25g/placement_au200.xdc diff --git a/fpga/mqnic/AU250/fpga_25g/placement.xdc b/fpga/mqnic/AU200/fpga_25g/placement_au250.xdc similarity index 100% rename from fpga/mqnic/AU250/fpga_25g/placement.xdc rename to fpga/mqnic/AU200/fpga_25g/placement_au250.xdc diff --git a/fpga/mqnic/VCU1525/fpga_25g/placement.xdc b/fpga/mqnic/AU200/fpga_25g/placement_vcu1525.xdc similarity index 100% rename from fpga/mqnic/VCU1525/fpga_25g/placement.xdc rename to fpga/mqnic/AU200/fpga_25g/placement_vcu1525.xdc diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v index 97017f21e..0beb3997a 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v @@ -25,6 +25,7 @@ module fpga # parameter RELEASE_INFO = 32'h00000000, // Board configuration + parameter CMS_ENABLE = 1, parameter TDMA_BER_ENABLE = 0, // Structural configuration @@ -684,113 +685,136 @@ wire [1:0] axil_cms_rresp; wire axil_cms_rvalid; wire axil_cms_rready; -wire [17:0] axil_cms_awaddr_int; -wire [2:0] axil_cms_awprot_int; -wire axil_cms_awvalid_int; -wire axil_cms_awready_int; -wire [31:0] axil_cms_wdata_int; -wire [3:0] axil_cms_wstrb_int; -wire axil_cms_wvalid_int; -wire axil_cms_wready_int; -wire [1:0] axil_cms_bresp_int; -wire axil_cms_bvalid_int; -wire axil_cms_bready_int; -wire [17:0] axil_cms_araddr_int; -wire [2:0] axil_cms_arprot_int; -wire axil_cms_arvalid_int; -wire axil_cms_arready_int; -wire [31:0] axil_cms_rdata_int; -wire [1:0] axil_cms_rresp_int; -wire axil_cms_rvalid_int; -wire axil_cms_rready_int; +generate -axil_cdc #( - .DATA_WIDTH(32), - .ADDR_WIDTH(18) -) -cms_axil_cdc_inst ( - .s_clk(axil_cms_clk), - .s_rst(axil_cms_rst), - .s_axil_awaddr(axil_cms_awaddr), - .s_axil_awprot(axil_cms_awprot), - .s_axil_awvalid(axil_cms_awvalid), - .s_axil_awready(axil_cms_awready), - .s_axil_wdata(axil_cms_wdata), - .s_axil_wstrb(axil_cms_wstrb), - .s_axil_wvalid(axil_cms_wvalid), - .s_axil_wready(axil_cms_wready), - .s_axil_bresp(axil_cms_bresp), - .s_axil_bvalid(axil_cms_bvalid), - .s_axil_bready(axil_cms_bready), - .s_axil_araddr(axil_cms_araddr), - .s_axil_arprot(axil_cms_arprot), - .s_axil_arvalid(axil_cms_arvalid), - .s_axil_arready(axil_cms_arready), - .s_axil_rdata(axil_cms_rdata), - .s_axil_rresp(axil_cms_rresp), - .s_axil_rvalid(axil_cms_rvalid), - .s_axil_rready(axil_cms_rready), - .m_clk(clk_50mhz_int), - .m_rst(rst_50mhz_int), - .m_axil_awaddr(axil_cms_awaddr_int), - .m_axil_awprot(axil_cms_awprot_int), - .m_axil_awvalid(axil_cms_awvalid_int), - .m_axil_awready(axil_cms_awready_int), - .m_axil_wdata(axil_cms_wdata_int), - .m_axil_wstrb(axil_cms_wstrb_int), - .m_axil_wvalid(axil_cms_wvalid_int), - .m_axil_wready(axil_cms_wready_int), - .m_axil_bresp(axil_cms_bresp_int), - .m_axil_bvalid(axil_cms_bvalid_int), - .m_axil_bready(axil_cms_bready_int), - .m_axil_araddr(axil_cms_araddr_int), - .m_axil_arprot(axil_cms_arprot_int), - .m_axil_arvalid(axil_cms_arvalid_int), - .m_axil_arready(axil_cms_arready_int), - .m_axil_rdata(axil_cms_rdata_int), - .m_axil_rresp(axil_cms_rresp_int), - .m_axil_rvalid(axil_cms_rvalid_int), - .m_axil_rready(axil_cms_rready_int) -); +if (CMS_ENABLE) begin : cms -cms_wrapper -cms_inst ( - .aclk_ctrl_0(clk_50mhz_int), - .aresetn_ctrl_0(~rst_50mhz_int), - .interrupt_host_0(), - .qsfp0_int_l_0(qsfp0_intl), - .qsfp0_lpmode_0(), - .qsfp0_modprs_l_0(qsfp0_modprsl), - .qsfp0_modsel_l_0(), - .qsfp0_reset_l_0(), - .qsfp1_int_l_0(qsfp1_intl), - .qsfp1_lpmode_0(), - .qsfp1_modprs_l_0(qsfp1_modprsl), - .qsfp1_modsel_l_0(), - .qsfp1_reset_l_0(), - .s_axi_ctrl_0_araddr(axil_cms_araddr_int), - .s_axi_ctrl_0_arprot(axil_cms_arprot_int), - .s_axi_ctrl_0_arready(axil_cms_arready_int), - .s_axi_ctrl_0_arvalid(axil_cms_arvalid_int), - .s_axi_ctrl_0_awaddr(axil_cms_awaddr_int), - .s_axi_ctrl_0_awprot(axil_cms_awprot_int), - .s_axi_ctrl_0_awready(axil_cms_awready_int), - .s_axi_ctrl_0_awvalid(axil_cms_awvalid_int), - .s_axi_ctrl_0_bready(axil_cms_bready_int), - .s_axi_ctrl_0_bresp(axil_cms_bresp_int), - .s_axi_ctrl_0_bvalid(axil_cms_bvalid_int), - .s_axi_ctrl_0_rdata(axil_cms_rdata_int), - .s_axi_ctrl_0_rready(axil_cms_rready_int), - .s_axi_ctrl_0_rresp(axil_cms_rresp_int), - .s_axi_ctrl_0_rvalid(axil_cms_rvalid_int), - .s_axi_ctrl_0_wdata(axil_cms_wdata_int), - .s_axi_ctrl_0_wready(axil_cms_wready_int), - .s_axi_ctrl_0_wstrb(axil_cms_wstrb_int), - .s_axi_ctrl_0_wvalid(axil_cms_wvalid_int), - .satellite_gpio_0(msp_gpio), - .satellite_uart_0_rxd(msp_uart_rxd), - .satellite_uart_0_txd(msp_uart_txd) -); + wire [17:0] axil_cms_awaddr_int; + wire [2:0] axil_cms_awprot_int; + wire axil_cms_awvalid_int; + wire axil_cms_awready_int; + wire [31:0] axil_cms_wdata_int; + wire [3:0] axil_cms_wstrb_int; + wire axil_cms_wvalid_int; + wire axil_cms_wready_int; + wire [1:0] axil_cms_bresp_int; + wire axil_cms_bvalid_int; + wire axil_cms_bready_int; + wire [17:0] axil_cms_araddr_int; + wire [2:0] axil_cms_arprot_int; + wire axil_cms_arvalid_int; + wire axil_cms_arready_int; + wire [31:0] axil_cms_rdata_int; + wire [1:0] axil_cms_rresp_int; + wire axil_cms_rvalid_int; + wire axil_cms_rready_int; + + axil_cdc #( + .DATA_WIDTH(32), + .ADDR_WIDTH(18) + ) + cms_axil_cdc_inst ( + .s_clk(axil_cms_clk), + .s_rst(axil_cms_rst), + .s_axil_awaddr(axil_cms_awaddr), + .s_axil_awprot(axil_cms_awprot), + .s_axil_awvalid(axil_cms_awvalid), + .s_axil_awready(axil_cms_awready), + .s_axil_wdata(axil_cms_wdata), + .s_axil_wstrb(axil_cms_wstrb), + .s_axil_wvalid(axil_cms_wvalid), + .s_axil_wready(axil_cms_wready), + .s_axil_bresp(axil_cms_bresp), + .s_axil_bvalid(axil_cms_bvalid), + .s_axil_bready(axil_cms_bready), + .s_axil_araddr(axil_cms_araddr), + .s_axil_arprot(axil_cms_arprot), + .s_axil_arvalid(axil_cms_arvalid), + .s_axil_arready(axil_cms_arready), + .s_axil_rdata(axil_cms_rdata), + .s_axil_rresp(axil_cms_rresp), + .s_axil_rvalid(axil_cms_rvalid), + .s_axil_rready(axil_cms_rready), + .m_clk(clk_50mhz_int), + .m_rst(rst_50mhz_int), + .m_axil_awaddr(axil_cms_awaddr_int), + .m_axil_awprot(axil_cms_awprot_int), + .m_axil_awvalid(axil_cms_awvalid_int), + .m_axil_awready(axil_cms_awready_int), + .m_axil_wdata(axil_cms_wdata_int), + .m_axil_wstrb(axil_cms_wstrb_int), + .m_axil_wvalid(axil_cms_wvalid_int), + .m_axil_wready(axil_cms_wready_int), + .m_axil_bresp(axil_cms_bresp_int), + .m_axil_bvalid(axil_cms_bvalid_int), + .m_axil_bready(axil_cms_bready_int), + .m_axil_araddr(axil_cms_araddr_int), + .m_axil_arprot(axil_cms_arprot_int), + .m_axil_arvalid(axil_cms_arvalid_int), + .m_axil_arready(axil_cms_arready_int), + .m_axil_rdata(axil_cms_rdata_int), + .m_axil_rresp(axil_cms_rresp_int), + .m_axil_rvalid(axil_cms_rvalid_int), + .m_axil_rready(axil_cms_rready_int) + ); + + cms_wrapper + cms_inst ( + .aclk_ctrl_0(clk_50mhz_int), + .aresetn_ctrl_0(~rst_50mhz_int), + .interrupt_host_0(), + .qsfp0_int_l_0(qsfp0_intl), + .qsfp0_lpmode_0(), + .qsfp0_modprs_l_0(qsfp0_modprsl), + .qsfp0_modsel_l_0(), + .qsfp0_reset_l_0(), + .qsfp1_int_l_0(qsfp1_intl), + .qsfp1_lpmode_0(), + .qsfp1_modprs_l_0(qsfp1_modprsl), + .qsfp1_modsel_l_0(), + .qsfp1_reset_l_0(), + .s_axi_ctrl_0_araddr(axil_cms_araddr_int), + .s_axi_ctrl_0_arprot(axil_cms_arprot_int), + .s_axi_ctrl_0_arready(axil_cms_arready_int), + .s_axi_ctrl_0_arvalid(axil_cms_arvalid_int), + .s_axi_ctrl_0_awaddr(axil_cms_awaddr_int), + .s_axi_ctrl_0_awprot(axil_cms_awprot_int), + .s_axi_ctrl_0_awready(axil_cms_awready_int), + .s_axi_ctrl_0_awvalid(axil_cms_awvalid_int), + .s_axi_ctrl_0_bready(axil_cms_bready_int), + .s_axi_ctrl_0_bresp(axil_cms_bresp_int), + .s_axi_ctrl_0_bvalid(axil_cms_bvalid_int), + .s_axi_ctrl_0_rdata(axil_cms_rdata_int), + .s_axi_ctrl_0_rready(axil_cms_rready_int), + .s_axi_ctrl_0_rresp(axil_cms_rresp_int), + .s_axi_ctrl_0_rvalid(axil_cms_rvalid_int), + .s_axi_ctrl_0_wdata(axil_cms_wdata_int), + .s_axi_ctrl_0_wready(axil_cms_wready_int), + .s_axi_ctrl_0_wstrb(axil_cms_wstrb_int), + .s_axi_ctrl_0_wvalid(axil_cms_wvalid_int), + .satellite_gpio_0(msp_gpio), + .satellite_uart_0_rxd(msp_uart_rxd), + .satellite_uart_0_txd(msp_uart_txd) + ); + +end else begin + + assign axil_cms_awready = 0; + assign axil_cms_wdata = 0; + assign axil_cms_wstrb = 0; + assign axil_cms_wvalid = 0; + assign axil_cms_bresp = 0; + assign axil_cms_bvalid = 0; + assign axil_cms_arready = 0; + assign axil_cms_rdata = 0; + assign axil_cms_rresp = 0; + assign axil_cms_rvalid = 0; + + assign msp_uart_txd = 1'bz; + +end + +endgenerate // configure SI5335 clock generators reg qsfp_refclk_reset_reg = 1'b1; @@ -2084,6 +2108,7 @@ fpga_core #( .RELEASE_INFO(RELEASE_INFO), // Board configuration + .CMS_ENABLE(CMS_ENABLE), .TDMA_BER_ENABLE(TDMA_BER_ENABLE), // Structural configuration diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v index 91b162dbd..255995400 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v @@ -25,6 +25,7 @@ module fpga_core # parameter RELEASE_INFO = 32'h00000000, // Board configuration + parameter CMS_ENABLE = 1, parameter TDMA_BER_ENABLE = 0, // Structural configuration @@ -697,14 +698,14 @@ always @(posedge clk_250mhz) begin // Alveo BMC RBB+8'h4C: begin // BMC ctrl: Addr - if (!m_axil_cms_arvalid && !m_axil_cms_awvalid) begin + if (CMS_ENABLE && !m_axil_cms_arvalid && !m_axil_cms_awvalid) begin m_axil_cms_addr_reg <= ctrl_reg_wr_data; m_axil_cms_arvalid_reg <= 1'b1; end end RBB+8'h50: begin // BMC ctrl: Data - if (!m_axil_cms_wvalid) begin + if (CMS_ENABLE && !m_axil_cms_wvalid) begin m_axil_cms_awvalid_reg <= 1'b1; m_axil_cms_wdata_reg <= ctrl_reg_wr_data; m_axil_cms_wstrb_reg <= ctrl_reg_wr_strb; @@ -764,11 +765,11 @@ always @(posedge clk_250mhz) begin ctrl_reg_rd_data_reg[17] <= qspi_cs; end // Alveo BMC - RBB+8'h40: ctrl_reg_rd_data_reg <= 32'h0000C140; // BMC ctrl: Type - RBB+8'h44: ctrl_reg_rd_data_reg <= 32'h00000100; // BMC ctrl: Version - RBB+8'h48: ctrl_reg_rd_data_reg <= RB_DRP_QSFP0_BASE; // BMC ctrl: Next header - RBB+8'h4C: ctrl_reg_rd_data_reg <= m_axil_cms_addr_reg; // BMC ctrl: Addr - RBB+8'h50: ctrl_reg_rd_data_reg <= m_axil_cms_rdata; // BMC ctrl: Data + RBB+8'h40: ctrl_reg_rd_data_reg <= CMS_ENABLE ? 32'h0000C140 : 0; // BMC ctrl: Type + RBB+8'h44: ctrl_reg_rd_data_reg <= CMS_ENABLE ? 32'h00000100 : 0; // BMC ctrl: Version + RBB+8'h48: ctrl_reg_rd_data_reg <= RB_DRP_QSFP0_BASE; // BMC ctrl: Next header + RBB+8'h4C: ctrl_reg_rd_data_reg <= CMS_ENABLE ? m_axil_cms_addr_reg : 0; // BMC ctrl: Addr + RBB+8'h50: ctrl_reg_rd_data_reg <= CMS_ENABLE ? m_axil_cms_rdata : 0; // BMC ctrl: Data default: ctrl_reg_rd_ack_reg <= 1'b0; endcase end diff --git a/fpga/mqnic/AU250/fpga_100g/Makefile b/fpga/mqnic/AU250/fpga_100g/Makefile deleted file mode 100644 index f504bd06f..000000000 --- a/fpga/mqnic/AU250/fpga_100g/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# Targets -TARGETS:= - -# Subdirectories -SUBDIRS = fpga -SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) - -# Rules -.PHONY: all -all: $(SUBDIRS) $(TARGETS) - -.PHONY: $(SUBDIRS) -$(SUBDIRS): - cd $@ && $(MAKE) - -.PHONY: $(SUBDIRS_CLEAN) -$(SUBDIRS_CLEAN): - cd $(@:.clean=) && $(MAKE) clean - -.PHONY: clean -clean: $(SUBDIRS_CLEAN) - -rm -rf $(TARGETS) - -program: - #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit diff --git a/fpga/mqnic/AU250/fpga_100g/README.md b/fpga/mqnic/AU250/fpga_100g/README.md deleted file mode 100644 index 649c47ae3..000000000 --- a/fpga/mqnic/AU250/fpga_100g/README.md +++ /dev/null @@ -1,24 +0,0 @@ -# Corundum mqnic for Alveo U250 - -## Introduction - -This design targets the Xilinx Alveo U250 FPGA board. - -* FPGA: xcu250-figd2104-2-e -* MAC: Xilinx 100G CMAC -* PHY: 100G CAUI-4 CMAC and internal GTY transceivers -* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM) - -## Quick start - -### Build FPGA bitstream - -Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. - -### Build driver and userspace tools - -On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools. - -### Testing - -Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state. diff --git a/fpga/mqnic/AU250/fpga_100g/app b/fpga/mqnic/AU250/fpga_100g/app deleted file mode 120000 index 4d46690fb..000000000 --- a/fpga/mqnic/AU250/fpga_100g/app +++ /dev/null @@ -1 +0,0 @@ -../../../app/ \ No newline at end of file diff --git a/fpga/mqnic/AU250/fpga_100g/boot.xdc b/fpga/mqnic/AU250/fpga_100g/boot.xdc deleted file mode 100644 index 5fb323e94..000000000 --- a/fpga/mqnic/AU250/fpga_100g/boot.xdc +++ /dev/null @@ -1,4 +0,0 @@ -# Timing constraints for FPGA boot logic - -set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] -set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] diff --git a/fpga/mqnic/AU250/fpga_100g/cfgmclk.xdc b/fpga/mqnic/AU250/fpga_100g/cfgmclk.xdc deleted file mode 100644 index 51f8c2ab1..000000000 --- a/fpga/mqnic/AU250/fpga_100g/cfgmclk.xdc +++ /dev/null @@ -1,4 +0,0 @@ -# Timing constraints for cfgmclk - -# Fcfgmclk is 50 MHz +/- 15%, rounding to 15 ns period -create_clock -period 15 -name cfgmclk [get_pins startupe3_inst/CFGMCLK] diff --git a/fpga/mqnic/AU250/fpga_100g/common/vivado.mk b/fpga/mqnic/AU250/fpga_100g/common/vivado.mk deleted file mode 100644 index 1402e2382..000000000 --- a/fpga/mqnic/AU250/fpga_100g/common/vivado.mk +++ /dev/null @@ -1,137 +0,0 @@ -################################################################### -# -# Xilinx Vivado FPGA Makefile -# -# Copyright (c) 2016 Alex Forencich -# -################################################################### -# -# Parameters: -# FPGA_TOP - Top module name -# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) -# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) -# SYN_FILES - space-separated list of source files -# INC_FILES - space-separated list of include files -# XDC_FILES - space-separated list of timing constraint files -# XCI_FILES - space-separated list of IP XCI files -# -# Example: -# -# FPGA_TOP = fpga -# FPGA_FAMILY = VirtexUltrascale -# FPGA_DEVICE = xcvu095-ffva2104-2-e -# SYN_FILES = rtl/fpga.v -# XDC_FILES = fpga.xdc -# XCI_FILES = ip/pcspma.xci -# include ../common/vivado.mk -# -################################################################### - -# phony targets -.PHONY: fpga vivado tmpclean clean distclean - -# prevent make from deleting intermediate files and reports -.PRECIOUS: %.xpr %.bit %.mcs %.prm -.SECONDARY: - -CONFIG ?= config.mk --include ../$(CONFIG) - -FPGA_TOP ?= fpga -PROJECT ?= $(FPGA_TOP) - -SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) - -ifdef XDC_FILES - XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -else - XDC_FILES_REL = $(PROJECT).xdc -endif - -################################################################### -# Main Targets -# -# all: build everything -# clean: remove output files and project files -################################################################### - -all: fpga - -fpga: $(PROJECT).bit - -vivado: $(PROJECT).xpr - vivado $(PROJECT).xpr - -tmpclean:: - -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl - -clean:: tmpclean - -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl - -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt - -distclean:: clean - -rm -rf rev - -################################################################### -# Target implementations -################################################################### - -# Vivado project file -create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) - rm -rf defines.v - touch defines.v - for x in $(DEFS); do echo '`define' $$x >> defines.v; done - echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ - echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ - echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ - echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ - for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done - for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) - echo "open_project -quiet $(PROJECT).xpr" > $@ - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -$(PROJECT).xpr: create_project.tcl update_config.tcl - vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) - -# synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr - echo "open_project $(PROJECT).xpr" > run_synth.tcl - echo "reset_run synth_1" >> run_synth.tcl - echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl - echo "wait_on_run synth_1" >> run_synth.tcl - vivado -nojournal -nolog -mode batch -source run_synth.tcl - -# implementation run -$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp - echo "open_project $(PROJECT).xpr" > run_impl.tcl - echo "reset_run impl_1" >> run_impl.tcl - echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl - echo "wait_on_run impl_1" >> run_impl.tcl - echo "open_run impl_1" >> run_impl.tcl - echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl - echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl - vivado -nojournal -nolog -mode batch -source run_impl.tcl - -# bit file -$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp - echo "open_project $(PROJECT).xpr" > generate_bit.tcl - echo "open_run impl_1" >> generate_bit.tcl - echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl - echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl - vivado -nojournal -nolog -mode batch -source generate_bit.tcl - ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi - mkdir -p rev - COUNT=100; \ - while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ - do COUNT=$$((COUNT+1)); done; \ - cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/mqnic/AU250/fpga_100g/fpga.xdc b/fpga/mqnic/AU250/fpga_100g/fpga.xdc deleted file mode 100644 index 2a3ff77fc..000000000 --- a/fpga/mqnic/AU250/fpga_100g/fpga.xdc +++ /dev/null @@ -1,848 +0,0 @@ -# XDC constraints for the Xilinx Alveo U250 board -# part: xcu250-figd2104-2-e - -# General configuration -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design] -set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] -set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] -set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] -set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] - -set_operating_conditions -design_power_budget 160 - -# System clocks -# 300 MHz (DDR 0) -set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] -set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] -#create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p] - -# 300 MHz (DDR 1) -set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] -set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] -#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] - -# 300 MHz (DDR 2) -set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] -set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] -#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] - -# 300 MHz (DDR 3) -set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] -set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] -#create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p] - -# SI570 user clock -#set_property -dict {LOC AU19 IOSTANDARD LVDS} [get_ports clk_user_p] -#set_property -dict {LOC AV19 IOSTANDARD LVDS} [get_ports clk_user_n] -#create_clock -period 6.400 -name clk_user [get_ports clk_user_p] - -# LEDs -set_property -dict {LOC BC21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] -set_property -dict {LOC BB21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] -set_property -dict {LOC BA20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}] - -set_false_path -to [get_ports {led[*]}] -set_output_delay 0 [get_ports {led[*]}] - -# Reset button -#set_property -dict {LOC AL20 IOSTANDARD LVCMOS12} [get_ports reset] - -#set_false_path -from [get_ports {reset}] -#set_input_delay 0 [get_ports {reset}] - -# DIP switches -set_property -dict {LOC AN22 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] -set_property -dict {LOC AM19 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] -set_property -dict {LOC AL19 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] -set_property -dict {LOC AP20 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] - -set_false_path -from [get_ports {sw[*]}] -set_input_delay 0 [get_ports {sw[*]}] - -# UART -#set_property -dict {LOC BF18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd] -#set_property -dict {LOC BB20 IOSTANDARD LVCMOS12} [get_ports uart_rxd] - -#set_false_path -to [get_ports {uart_txd}] -#set_output_delay 0 [get_ports {uart_txd}] -#set_false_path -from [get_ports {uart_rxd}] -#set_input_delay 0 [get_ports {uart_rxd}] - -# BMC -set_property -dict {LOC AR20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[0]}] -set_property -dict {LOC AM20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[1]}] -set_property -dict {LOC AM21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[2]}] -set_property -dict {LOC AN21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[3]}] -set_property -dict {LOC BB19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_uart_txd}] -set_property -dict {LOC BA19 IOSTANDARD LVCMOS12} [get_ports {msp_uart_rxd}] - -set_false_path -to [get_ports {msp_uart_txd}] -set_output_delay 0 [get_ports {msp_uart_txd}] -set_false_path -from [get_ports {msp_gpio[*] msp_uart_rxd}] -set_input_delay 0 [get_ports {msp_gpio[*] msp_uart_rxd}] - -# QSFP28 Interfaces -set_property -dict {LOC N4 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC N3 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC N9 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC N8 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC M2 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC M1 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC M7 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC M6 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC L4 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC L3 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC L9 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC L8 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC K2 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC K1 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC K7 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC K6 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13 -#set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14 -set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18 -set_property -dict {LOC K10 } [get_ports qsfp0_mgt_refclk_1_n] ;# MGTREFCLK1N_231 from U9.17 -set_property -dict {LOC BE16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_modsell] -set_property -dict {LOC BE17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl] -set_property -dict {LOC BE20 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_modprsl] -set_property -dict {LOC BE21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_intl] -set_property -dict {LOC BD18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode] -set_property -dict {LOC AT22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_refclk_reset] -set_property -dict {LOC AT20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[0]}] -set_property -dict {LOC AU22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[1]}] - -# 156.25 MHz MGT reference clock (from SI570) -#create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports qsfp0_mgt_refclk_0_p] - -# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) -#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] - -# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) -create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] - -set_false_path -to [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] -set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] -set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}] -set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}] - -set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC U9 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC U8 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC T2 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC T1 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC R4 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC R3 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC R9 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC R8 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC P2 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC P1 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 -#set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15 -#set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16 -set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18 -set_property -dict {LOC P10 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U12.17 -set_property -dict {LOC AY20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_modsell] -set_property -dict {LOC BC18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl] -set_property -dict {LOC BC19 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_modprsl] -set_property -dict {LOC AV21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_intl] -set_property -dict {LOC AV22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode] -set_property -dict {LOC AR21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_refclk_reset] -set_property -dict {LOC AR22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[0]}] -set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[1]}] - -# 156.25 MHz MGT reference clock (from SI570) -#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p] - -# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) -#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] - -# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) -create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] - -set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] -set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] -set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] -set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] - -# I2C interface -#set_property -dict {LOC BF19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset] -set_property -dict {LOC BF20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_scl] -set_property -dict {LOC BF17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_sda] - -set_false_path -to [get_ports {i2c_sda i2c_scl}] -set_output_delay 0 [get_ports {i2c_sda i2c_scl}] -set_false_path -from [get_ports {i2c_sda i2c_scl}] -set_input_delay 0 [get_ports {i2c_sda i2c_scl}] - -# PCIe Interface -set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AG9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AG8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AJ9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AJ8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AL4 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AL3 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AL9 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AL8 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AN4 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AN3 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AN9 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AN8 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AR4 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AR3 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AR9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AR8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AU4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AU3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AU9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AU8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC AV7 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC AV6 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC AW4 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC AW3 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BB5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BB4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BD5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BD4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BF5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BF4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC AM11 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_226 -set_property -dict {LOC AM10 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_226 -set_property -dict {LOC BD21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n] - -# 100 MHz MGT reference clock -create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p] - -set_false_path -from [get_ports {pcie_reset_n}] -set_input_delay 0 [get_ports {pcie_reset_n}] - -# DDR4 C0 -set_property -dict {LOC AT36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] -set_property -dict {LOC AV36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] -set_property -dict {LOC AV37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] -set_property -dict {LOC AW35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] -set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] -set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] -set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] -set_property -dict {LOC BA40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] -set_property -dict {LOC BA37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] -set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] -set_property -dict {LOC AR35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] -set_property -dict {LOC BA39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] -set_property -dict {LOC BB40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] -set_property -dict {LOC AN36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] -set_property -dict {LOC AP35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] -set_property -dict {LOC AP36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] -set_property -dict {LOC AR36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] -set_property -dict {LOC AT35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] -set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] -set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] -set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] -set_property -dict {LOC AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[0]}] -set_property -dict {LOC AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[0]}] -#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[1]}] -#set_property -dict {LOC AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[1]}] -set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}] -#set_property -dict {LOC BC40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}] -set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}] -#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}] -#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}] -#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}] -set_property -dict {LOC BB39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] -set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}] -#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}] -set_property -dict {LOC AU36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] -set_property -dict {LOC AU31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] - -set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] -set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] -set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] -set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] -set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] -set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] -set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] -set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] -set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] -set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] -set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] -set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] -set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] -set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] -set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] -set_property -dict {LOC BF29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] -set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] -set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] -set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] -set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] -set_property -dict {LOC BC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] -set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] -set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] -set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] -set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] -set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] -set_property -dict {LOC AV34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] -set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] -set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] -set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] -set_property -dict {LOC BA35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] -set_property -dict {LOC BA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] -set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] -set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] -set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] -set_property -dict {LOC AT32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] -set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] -set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] -set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] -set_property -dict {LOC AR31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] -set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] -set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] -set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] -set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] -set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] -set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] -set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] -set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] -set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] -set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] -set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] -set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] -set_property -dict {LOC AV29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] -set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] -set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] -set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] -set_property -dict {LOC BD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] -set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] -set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] -set_property -dict {LOC BD35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] -set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] -set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] -set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] -set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] -set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] -set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] -set_property -dict {LOC BF43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] -set_property -dict {LOC BF42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] -set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] -set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] -set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] -set_property -dict {LOC BF41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] -set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] -set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] -set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] -set_property -dict {LOC BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] -set_property -dict {LOC BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] -set_property -dict {LOC BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] -set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] -set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] -set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] -set_property -dict {LOC BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] -set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] -set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] -set_property -dict {LOC AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] -set_property -dict {LOC AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] -set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] -set_property -dict {LOC BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] -set_property -dict {LOC AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] -set_property -dict {LOC AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] -set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}] -set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}] -set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}] -set_property -dict {LOC AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}] -set_property -dict {LOC AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}] -set_property -dict {LOC AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}] -set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}] -set_property -dict {LOC AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}] -set_property -dict {LOC AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}] -set_property -dict {LOC AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}] -set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}] -set_property -dict {LOC BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}] -set_property -dict {LOC BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}] -set_property -dict {LOC BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}] -set_property -dict {LOC BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}] -set_property -dict {LOC BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}] -set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}] -set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}] - -# DDR4 C1 -set_property -dict {LOC AN24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] -set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] -set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] -set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] -set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] -set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] -set_property -dict {LOC AV24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] -set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] -set_property -dict {LOC AY25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] -set_property -dict {LOC BA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] -set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] -set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] -set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] -set_property -dict {LOC AL24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] -set_property -dict {LOC AL25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] -set_property -dict {LOC AM25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] -set_property -dict {LOC AN23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] -set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] -set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] -set_property -dict {LOC BC22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] -set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] -set_property -dict {LOC AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[0]}] -set_property -dict {LOC AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[0]}] -#set_property -dict {LOC AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[1]}] -#set_property -dict {LOC AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[1]}] -set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}] -#set_property -dict {LOC BB24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}] -set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}] -#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}] -#set_property -dict {LOC AR23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}] -#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}] -set_property -dict {LOC AW25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] -set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}] -#set_property -dict {LOC AP24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}] -set_property -dict {LOC AT23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] -set_property -dict {LOC AR17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] - -set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] -set_property -dict {LOC BD7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] -set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] -set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] -set_property -dict {LOC BD10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] -set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] -set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] -set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] -set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] -set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] -set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] -set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] -set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] -set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] -set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] -set_property -dict {LOC BA11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] -set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] -set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] -set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] -set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] -set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] -set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] -set_property -dict {LOC BA7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] -set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] -set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] -set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] -set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] -set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] -set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] -set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] -set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] -set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] -set_property -dict {LOC BE13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] -set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] -set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] -set_property -dict {LOC BD13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] -set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] -set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] -set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] -set_property -dict {LOC BF13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] -set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] -set_property -dict {LOC BA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] -set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] -set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] -set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] -set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] -set_property -dict {LOC BC11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] -set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] -set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] -set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] -set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] -set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] -set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] -set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] -set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] -set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] -set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] -set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] -set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] -set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] -set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] -set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] -set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] -set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] -set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] -set_property -dict {LOC BF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] -set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] -set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] -set_property -dict {LOC BD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] -set_property -dict {LOC BC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] -set_property -dict {LOC BF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] -set_property -dict {LOC BE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] -set_property -dict {LOC BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] -set_property -dict {LOC BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] -set_property -dict {LOC BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] -set_property -dict {LOC BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] -set_property -dict {LOC AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] -set_property -dict {LOC AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] -set_property -dict {LOC AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] -set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] -set_property -dict {LOC BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] -set_property -dict {LOC BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] -set_property -dict {LOC BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] -set_property -dict {LOC BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] -set_property -dict {LOC AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] -set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] -set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] -set_property -dict {LOC AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] -set_property -dict {LOC BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] -set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] -set_property -dict {LOC BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] -set_property -dict {LOC BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] -set_property -dict {LOC BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}] -set_property -dict {LOC BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}] -set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}] -set_property -dict {LOC BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}] -set_property -dict {LOC AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}] -set_property -dict {LOC AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}] -set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}] -set_property -dict {LOC AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}] -set_property -dict {LOC AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}] -set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}] -set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}] -set_property -dict {LOC AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}] -set_property -dict {LOC BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}] -set_property -dict {LOC BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}] -set_property -dict {LOC BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}] -set_property -dict {LOC BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}] - -# DDR4 C2 -set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] -set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] -set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] -set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] -set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] -set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] -set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] -set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] -set_property -dict {LOC A32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] -set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] -set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] -set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] -set_property -dict {LOC M30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] -set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] -set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] -set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] -set_property -dict {LOC K30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] -set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] -set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] -set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] -set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}] -set_property -dict {LOC C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[0]}] -set_property -dict {LOC B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[0]}] -#set_property -dict {LOC D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[1]}] -#set_property -dict {LOC D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[1]}] -set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}] -#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}] -set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}] -#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}] -#set_property -dict {LOC L30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}] -#set_property -dict {LOC K31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}] -set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] -set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}] -#set_property -dict {LOC F34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}] -set_property -dict {LOC M29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] -set_property -dict {LOC D36 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] - -set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] -set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] -set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] -set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] -set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] -set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] -set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] -set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] -set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] -set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] -set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] -set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] -set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] -set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] -set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] -set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] -set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] -set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] -set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] -set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] -set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] -set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] -set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] -set_property -dict {LOC F29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] -set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] -set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] -set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] -set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] -set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] -set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] -set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] -set_property -dict {LOC C28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] -set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] -set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] -set_property -dict {LOC D38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] -set_property -dict {LOC E35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] -set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] -set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] -set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] -set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] -set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] -set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] -set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] -set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] -set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] -set_property -dict {LOC M32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] -set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] -set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] -set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] -set_property -dict {LOC K35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] -set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] -set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] -set_property -dict {LOC J34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] -set_property -dict {LOC J33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] -set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] -set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] -set_property -dict {LOC H36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] -set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] -set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] -set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] -set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] -set_property -dict {LOC K38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] -set_property -dict {LOC G35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] -set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] -set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] -set_property -dict {LOC B37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] -set_property -dict {LOC A37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] -set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] -set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] -set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] -set_property -dict {LOC A40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] -set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] -set_property -dict {LOC N26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] -set_property -dict {LOC M26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] -set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] -set_property -dict {LOC P28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] -set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] -set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] -set_property -dict {LOC M27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] -set_property -dict {LOC L28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] -set_property -dict {LOC D29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] -set_property -dict {LOC D30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] -set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] -set_property -dict {LOC H27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] -set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] -set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] -set_property -dict {LOC C29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] -set_property -dict {LOC B29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] -set_property -dict {LOC E39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] -set_property -dict {LOC E40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] -set_property -dict {LOC G37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] -set_property -dict {LOC F37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] -set_property -dict {LOC N31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}] -set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}] -set_property -dict {LOC T30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}] -set_property -dict {LOC R31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}] -set_property -dict {LOC L35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}] -set_property -dict {LOC L36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}] -set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}] -set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}] -set_property -dict {LOC J38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}] -set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}] -set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}] -set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}] -set_property -dict {LOC B39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}] -set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}] -set_property -dict {LOC C37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}] -set_property -dict {LOC C38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}] - -# DDR4 C3 -set_property -dict {LOC K15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}] -set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}] -set_property -dict {LOC F14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}] -set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}] -set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}] -set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}] -set_property -dict {LOC B14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}] -set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}] -set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}] -set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}] -set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}] -set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}] -set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}] -set_property -dict {LOC K16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}] -set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}] -set_property -dict {LOC E15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}] -set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}] -set_property -dict {LOC J15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}] -set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}] -set_property -dict {LOC D13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}] -set_property -dict {LOC J13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}] -set_property -dict {LOC L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[0]}] -set_property -dict {LOC L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[0]}] -#set_property -dict {LOC G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[1]}] -#set_property -dict {LOC G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[1]}] -set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}] -#set_property -dict {LOC L15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}] -set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}] -#set_property -dict {LOC D16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}] -#set_property -dict {LOC M14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}] -#set_property -dict {LOC M13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}] -set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}] -set_property -dict {LOC C16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}] -#set_property -dict {LOC E16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}] -set_property -dict {LOC J14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}] -set_property -dict {LOC D21 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}] - -set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}] -set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}] -set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}] -set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}] -set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}] -set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}] -set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}] -set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}] -set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}] -set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}] -set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}] -set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}] -set_property -dict {LOC L24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}] -set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}] -set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}] -set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}] -set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}] -set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}] -set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}] -set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}] -set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}] -set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}] -set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}] -set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}] -set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}] -set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}] -set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}] -set_property -dict {LOC R17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}] -set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}] -set_property -dict {LOC T20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}] -set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}] -set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}] -set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}] -set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}] -set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}] -set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}] -set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}] -set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}] -set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}] -set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}] -set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}] -set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}] -set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}] -set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}] -set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}] -set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}] -set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}] -set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}] -set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}] -set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}] -set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}] -set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}] -set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}] -set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}] -set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}] -set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}] -set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}] -set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}] -set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}] -set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}] -set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}] -set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}] -set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}] -set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}] -set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}] -set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}] -set_property -dict {LOC N13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}] -set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}] -set_property -dict {LOC T15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}] -set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}] -set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}] -set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}] -set_property -dict {LOC T22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}] -set_property -dict {LOC R22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}] -set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}] -set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}] -set_property -dict {LOC J21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}] -set_property -dict {LOC H21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}] -set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}] -set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}] -set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}] -set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}] -set_property -dict {LOC K18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}] -set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}] -set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}] -set_property -dict {LOC P18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}] -set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}] -set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}] -set_property -dict {LOC A25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}] -set_property -dict {LOC A24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}] -set_property -dict {LOC D24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}] -set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}] -set_property -dict {LOC C17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}] -set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}] -set_property -dict {LOC B19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}] -set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}] -set_property -dict {LOC F18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}] -set_property -dict {LOC F17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}] -set_property -dict {LOC H19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}] -set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}] -set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}] -set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}] -set_property -dict {LOC H23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}] -set_property -dict {LOC H22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}] -set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}] -set_property -dict {LOC P15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}] -set_property -dict {LOC T13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}] -set_property -dict {LOC R13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}] diff --git a/fpga/mqnic/AU250/fpga_100g/ip/cmac_gty.tcl b/fpga/mqnic/AU250/fpga_100g/ip/cmac_gty.tcl deleted file mode 100644 index 6a14c1f28..000000000 --- a/fpga/mqnic/AU250/fpga_100g/ip/cmac_gty.tcl +++ /dev/null @@ -1,106 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2022-2023 The Regents of the University of California - -set base_name {cmac_gty} - -set preset {GTY-CAUI_4} - -set freerun_freq {125} -set line_rate {25.78125} -set sec_line_rate {0} -set refclk_freq {161.1328125} -set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set user_data_width {80} -set int_data_width $user_data_width -set rx_eq_mode {LPM} -set extra_ports [list] -set extra_pll_ports [list] -# DRP connections -lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out -lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out -# PLL reset and power down -lappend extra_pll_ports qpll0reset_in qpll1reset_in -lappend extra_pll_ports qpll0pd_in qpll1pd_in -# PLL clocking -lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out -lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out -# channel reset -lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out -lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out -# channel power down -lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in -# channel clock selection -lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in -# channel polarity -lappend extra_ports txpolarity_in rxpolarity_in -# channel TX driver -lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in -# channel CDR -lappend extra_ports rxcdrlock_out rxcdrhold_in -# channel EQ -lappend extra_ports rxlpmen_in -# channel digital monitor -lappend extra_ports dmonitorout_out -# channel PRBS -lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out -# channel eye scan -lappend extra_ports eyescandataerror_out -# channel loopback -lappend extra_ports loopback_in - -set config [dict create] - -dict set config TX_LINE_RATE $line_rate -dict set config TX_REFCLK_FREQUENCY $refclk_freq -dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config TX_USER_DATA_WIDTH $user_data_width -dict set config TX_INT_DATA_WIDTH $int_data_width -dict set config RX_LINE_RATE $line_rate -dict set config RX_REFCLK_FREQUENCY $refclk_freq -dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config RX_USER_DATA_WIDTH $user_data_width -dict set config RX_INT_DATA_WIDTH $int_data_width -dict set config RX_EQ_MODE $rx_eq_mode -if {$sec_line_rate != 0} { - dict set config SECONDARY_QPLL_ENABLE true - dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn - dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq -} else { - dict set config SECONDARY_QPLL_ENABLE false -} -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} -dict set config LOCATE_TX_USER_CLOCKING {EXAMPLE_DESIGN} -dict set config LOCATE_RX_USER_CLOCKING {EXAMPLE_DESIGN} -dict set config LOCATE_USER_DATA_WIDTH_SIZING {EXAMPLE_DESIGN} -dict set config FREERUN_FREQUENCY $freerun_freq -dict set config DISABLE_LOC_XDC {1} - -proc create_gtwizard_ip {name preset config} { - create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name - set ip [get_ips $name] - set_property CONFIG.preset $preset $ip - set config_list {} - dict for {name value} $config { - lappend config_list "CONFIG.${name}" $value - } - set_property -dict $config_list $ip - - # enable only one site - set_property CONFIG.CHANNEL_ENABLE [lindex [get_property CONFIG.CHANNEL_ENABLE $ip] 0] $ip -} - -# variant with channel and common -dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports] -dict set config LOCATE_COMMON {CORE} - -create_gtwizard_ip "${base_name}_full" $preset $config - -# variant with channel only -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {EXAMPLE_DESIGN} - -create_gtwizard_ip "${base_name}_channel" $preset $config diff --git a/fpga/mqnic/AU250/fpga_100g/ip/cmac_usplus.tcl b/fpga/mqnic/AU250/fpga_100g/ip/cmac_usplus.tcl deleted file mode 100644 index af9cc8265..000000000 --- a/fpga/mqnic/AU250/fpga_100g/ip/cmac_usplus.tcl +++ /dev/null @@ -1,21 +0,0 @@ - -create_ip -name cmac_usplus -vendor xilinx.com -library ip -module_name cmac_usplus - -set_property -dict [list \ - CONFIG.CMAC_CAUI4_MODE {1} \ - CONFIG.NUM_LANES {4x25} \ - CONFIG.USER_INTERFACE {AXIS} \ - CONFIG.GT_DRP_CLK {125} \ - CONFIG.GT_LOCATION {0} \ - CONFIG.TX_FLOW_CONTROL {1} \ - CONFIG.RX_FLOW_CONTROL {1} \ - CONFIG.RX_FORWARD_CONTROL_FRAMES {0} \ - CONFIG.RX_CHECK_ACK {1} \ - CONFIG.INCLUDE_RS_FEC {1} \ - CONFIG.ENABLE_TIME_STAMPING {1} -] [get_ips cmac_usplus] - -# disable LOC constraint -set_property generate_synth_checkpoint false [get_files [get_property IP_FILE [get_ips cmac_usplus]]] -generate_target synthesis [get_files [get_property IP_FILE [get_ips cmac_usplus]]] -set_property is_enabled false [get_files -of_objects [get_files [get_property IP_FILE [get_ips cmac_usplus]]] cmac_usplus.xdc] diff --git a/fpga/mqnic/AU250/fpga_100g/ip/cms.tcl b/fpga/mqnic/AU250/fpga_100g/ip/cms.tcl deleted file mode 100644 index 22126d4d6..000000000 --- a/fpga/mqnic/AU250/fpga_100g/ip/cms.tcl +++ /dev/null @@ -1,16 +0,0 @@ - -# create block design -create_bd_design "cms" - -# create CMS IP -set cms_block [create_bd_cell -type ip -vlnv xilinx.com:ip:cms_subsystem cms_subsystem_0] -make_bd_pins_external $cms_block -make_bd_intf_pins_external $cms_block - -# assign addresses -assign_bd_address -target_address_space /s_axi_ctrl_0 [get_bd_addr_segs $cms_block/s_axi_ctrl/Mem0] -force - -# save block design and create HDL wrapper -save_bd_design [current_bd_design] -add_files -norecurse [make_wrapper -files [get_files [get_property FILE_NAME [current_bd_design]]] -top] -close_bd_design [current_bd_design] diff --git a/fpga/mqnic/AU250/fpga_100g/ip/ddr4_0.tcl b/fpga/mqnic/AU250/fpga_100g/ip/ddr4_0.tcl deleted file mode 100644 index 27252f502..000000000 --- a/fpga/mqnic/AU250/fpga_100g/ip/ddr4_0.tcl +++ /dev/null @@ -1,17 +0,0 @@ - -create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 - -set_property -dict [list \ - CONFIG.C0.DDR4_AxiSelection {true} \ - CONFIG.C0.DDR4_AxiDataWidth {512} \ - CONFIG.C0.DDR4_AxiIDWidth {8} \ - CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ - CONFIG.C0.DDR4_TimePeriod {833} \ - CONFIG.C0.DDR4_InputClockPeriod {3332} \ - CONFIG.C0.DDR4_MemoryType {RDIMMs} \ - CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ - CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ - CONFIG.C0.DDR4_CasLatency {17} \ - CONFIG.C0.DDR4_CasWriteLatency {12} \ - CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} -] [get_ips ddr4_0] diff --git a/fpga/mqnic/AU250/fpga_100g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/AU250/fpga_100g/ip/pcie4_uscale_plus_0.tcl deleted file mode 100644 index 8d998b95c..000000000 --- a/fpga/mqnic/AU250/fpga_100g/ip/pcie4_uscale_plus_0.tcl +++ /dev/null @@ -1,34 +0,0 @@ - -create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 - -set_property -dict [list \ - CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ - CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ - CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \ - CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \ - CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \ - CONFIG.axisten_if_enable_client_tag {true} \ - CONFIG.axisten_if_width {512_bit} \ - CONFIG.extended_tag_field {true} \ - CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ - CONFIG.axisten_freq {250} \ - CONFIG.PF0_Use_Class_Code_Lookup_Assistant {false} \ - CONFIG.PF0_CLASS_CODE {020000} \ - CONFIG.PF0_DEVICE_ID {1001} \ - CONFIG.PF0_SUBSYSTEM_ID {90fa} \ - CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ - CONFIG.pf0_bar0_64bit {true} \ - CONFIG.pf0_bar0_prefetchable {true} \ - CONFIG.pf0_bar0_scale {Megabytes} \ - CONFIG.pf0_bar0_size {16} \ - CONFIG.pf0_msi_enabled {false} \ - CONFIG.pf0_msix_enabled {true} \ - CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ - CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \ - CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \ - CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \ - CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \ - CONFIG.MSI_X_OPTIONS {MSI-X_External} \ - CONFIG.vendor_id {1234} \ - CONFIG.mode_selection {Advanced} \ -] [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/AU250/fpga_100g/lib b/fpga/mqnic/AU250/fpga_100g/lib deleted file mode 120000 index 9512b3d5e..000000000 --- a/fpga/mqnic/AU250/fpga_100g/lib +++ /dev/null @@ -1 +0,0 @@ -../../../lib/ \ No newline at end of file diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/common b/fpga/mqnic/AU250/fpga_100g/rtl/common deleted file mode 120000 index 449c9409c..000000000 --- a/fpga/mqnic/AU250/fpga_100g/rtl/common +++ /dev/null @@ -1 +0,0 @@ -../../../../common/rtl/ \ No newline at end of file diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/debounce_switch.v b/fpga/mqnic/AU250/fpga_100g/rtl/debounce_switch.v deleted file mode 100644 index 8e93a50c4..000000000 --- a/fpga/mqnic/AU250/fpga_100g/rtl/debounce_switch.v +++ /dev/null @@ -1,93 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog-2001 - -`resetall -`timescale 1 ns / 1 ps -`default_nettype none - -/* - * Synchronizes switch and button inputs with a slow sampled shift register - */ -module debounce_switch #( - parameter WIDTH=1, // width of the input and output signals - parameter N=3, // length of shift register - parameter RATE=125000 // clock division factor -)( - input wire clk, - input wire rst, - input wire [WIDTH-1:0] in, - output wire [WIDTH-1:0] out -); - -reg [23:0] cnt_reg = 24'd0; - -reg [N-1:0] debounce_reg[WIDTH-1:0]; - -reg [WIDTH-1:0] state; - -/* - * The synchronized output is the state register - */ -assign out = state; - -integer k; - -always @(posedge clk or posedge rst) begin - if (rst) begin - cnt_reg <= 0; - state <= 0; - - for (k = 0; k < WIDTH; k = k + 1) begin - debounce_reg[k] <= 0; - end - end else begin - if (cnt_reg < RATE) begin - cnt_reg <= cnt_reg + 24'd1; - end else begin - cnt_reg <= 24'd0; - end - - if (cnt_reg == 24'd0) begin - for (k = 0; k < WIDTH; k = k + 1) begin - debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]}; - end - end - - for (k = 0; k < WIDTH; k = k + 1) begin - if (|debounce_reg[k] == 0) begin - state[k] <= 0; - end else if (&debounce_reg[k] == 1) begin - state[k] <= 1; - end else begin - state[k] <= state[k]; - end - end - end -end - -endmodule - -`resetall diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v deleted file mode 100644 index a7ceb611e..000000000 --- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v +++ /dev/null @@ -1,2441 +0,0 @@ -// SPDX-License-Identifier: BSD-2-Clause-Views -/* - * Copyright (c) 2019-2023 The Regents of the University of California - */ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA top-level module - */ -module fpga # -( - // FW and board IDs - parameter FPGA_ID = 32'h4B57093, - parameter FW_ID = 32'h00000000, - parameter FW_VER = 32'h00_00_01_00, - parameter BOARD_ID = 32'h10ee_90fa, - parameter BOARD_VER = 32'h01_00_00_00, - parameter BUILD_DATE = 32'd602976000, - parameter GIT_HASH = 32'hdce357bf, - parameter RELEASE_INFO = 32'h00000000, - - // Structural configuration - parameter IF_COUNT = 2, - parameter PORTS_PER_IF = 1, - parameter SCHED_PER_IF = PORTS_PER_IF, - parameter PORT_MASK = 0, - - // Clock configuration - parameter CLK_PERIOD_NS_NUM = 4, - parameter CLK_PERIOD_NS_DENOM = 1, - - // PTP configuration - parameter PTP_CLOCK_PIPELINE = 0, - parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_PORT_CDC_PIPELINE = 0, - parameter PTP_PEROUT_ENABLE = 0, - parameter PTP_PEROUT_COUNT = 1, - - // Queue manager configuration - parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_QUEUE_OP_TABLE_SIZE = 32, - parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter CQ_OP_TABLE_SIZE = 32, - parameter EQN_WIDTH = 5, - parameter TX_QUEUE_INDEX_WIDTH = 13, - parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, - parameter EQ_PIPELINE = 3, - parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), - parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), - - // TX and RX engine configuration - parameter TX_DESC_TABLE_SIZE = 32, - parameter RX_DESC_TABLE_SIZE = 32, - parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, - - // Scheduler configuration - parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, - parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, - parameter TDMA_INDEX_WIDTH = 6, - - // Interface configuration - parameter PTP_TS_ENABLE = 1, - parameter TX_CPL_FIFO_DEPTH = 32, - parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_HASH_ENABLE = 1, - parameter RX_CHECKSUM_ENABLE = 1, - parameter PFC_ENABLE = 1, - parameter LFC_ENABLE = PFC_ENABLE, - parameter TX_FIFO_DEPTH = 32768, - parameter RX_FIFO_DEPTH = 131072, - parameter MAX_TX_SIZE = 9214, - parameter MAX_RX_SIZE = 9214, - parameter TX_RAM_SIZE = 131072, - parameter RX_RAM_SIZE = 131072, - - // RAM configuration - parameter DDR_CH = 4, - parameter DDR_ENABLE = 0, - parameter AXI_DDR_DATA_WIDTH = 512, - parameter AXI_DDR_ADDR_WIDTH = 34, - parameter AXI_DDR_ID_WIDTH = 8, - parameter AXI_DDR_MAX_BURST_LEN = 256, - parameter AXI_DDR_NARROW_BURST = 0, - - // Application block configuration - parameter APP_ID = 32'h00000000, - parameter APP_ENABLE = 0, - parameter APP_CTRL_ENABLE = 1, - parameter APP_DMA_ENABLE = 1, - parameter APP_AXIS_DIRECT_ENABLE = 1, - parameter APP_AXIS_SYNC_ENABLE = 1, - parameter APP_AXIS_IF_ENABLE = 1, - parameter APP_STAT_ENABLE = 1, - - // DMA interface configuration - parameter DMA_IMM_ENABLE = 0, - parameter DMA_IMM_WIDTH = 32, - parameter DMA_LEN_WIDTH = 16, - parameter DMA_TAG_WIDTH = 16, - parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), - parameter RAM_PIPELINE = 2, - - // PCIe interface configuration - parameter AXIS_PCIE_DATA_WIDTH = 512, - parameter PF_COUNT = 1, - parameter VF_COUNT = 0, - - // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EQN_WIDTH, - - // AXI lite interface configuration (control) - parameter AXIL_CTRL_DATA_WIDTH = 32, - parameter AXIL_CTRL_ADDR_WIDTH = 24, - - // AXI lite interface configuration (application control) - parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, - parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, - - // Ethernet interface configuration - parameter AXIS_ETH_TX_PIPELINE = 4, - parameter AXIS_ETH_TX_FIFO_PIPELINE = 4, - parameter AXIS_ETH_TX_TS_PIPELINE = 4, - parameter AXIS_ETH_RX_PIPELINE = 4, - parameter AXIS_ETH_RX_FIFO_PIPELINE = 4, - - // Statistics counter subsystem - parameter STAT_ENABLE = 1, - parameter STAT_DMA_ENABLE = 1, - parameter STAT_PCIE_ENABLE = 1, - parameter STAT_INC_WIDTH = 24, - parameter STAT_ID_WIDTH = 12 -) -( - /* - * Clock and reset - */ - input wire clk_300mhz_0_p, - input wire clk_300mhz_0_n, - input wire clk_300mhz_1_p, - input wire clk_300mhz_1_n, - input wire clk_300mhz_2_p, - input wire clk_300mhz_2_n, - input wire clk_300mhz_3_p, - input wire clk_300mhz_3_n, - - /* - * GPIO - */ - input wire [3:0] sw, - output wire [2:0] led, - input wire [3:0] msp_gpio, - output wire msp_uart_txd, - input wire msp_uart_rxd, - - /* - * I2C for board management - */ - inout wire i2c_scl, - inout wire i2c_sda, - - /* - * PCI express - */ - input wire [15:0] pcie_rx_p, - input wire [15:0] pcie_rx_n, - output wire [15:0] pcie_tx_p, - output wire [15:0] pcie_tx_n, - input wire pcie_refclk_p, - input wire pcie_refclk_n, - input wire pcie_reset_n, - - /* - * Ethernet: QSFP28 - */ - output wire [3:0] qsfp0_tx_p, - output wire [3:0] qsfp0_tx_n, - input wire [3:0] qsfp0_rx_p, - input wire [3:0] qsfp0_rx_n, - // input wire qsfp0_mgt_refclk_0_p, - // input wire qsfp0_mgt_refclk_0_n, - input wire qsfp0_mgt_refclk_1_p, - input wire qsfp0_mgt_refclk_1_n, - output wire qsfp0_modsell, - output wire qsfp0_resetl, - input wire qsfp0_modprsl, - input wire qsfp0_intl, - output wire qsfp0_lpmode, - output wire qsfp0_refclk_reset, - output wire [1:0] qsfp0_fs, - - output wire [3:0] qsfp1_tx_p, - output wire [3:0] qsfp1_tx_n, - input wire [3:0] qsfp1_rx_p, - input wire [3:0] qsfp1_rx_n, - // input wire qsfp1_mgt_refclk_0_p, - // input wire qsfp1_mgt_refclk_0_n, - input wire qsfp1_mgt_refclk_1_p, - input wire qsfp1_mgt_refclk_1_n, - output wire qsfp1_modsell, - output wire qsfp1_resetl, - input wire qsfp1_modprsl, - input wire qsfp1_intl, - output wire qsfp1_lpmode, - output wire qsfp1_refclk_reset, - output wire [1:0] qsfp1_fs, - - /* - * DDR4 - */ - output wire [16:0] ddr4_c0_adr, - output wire [1:0] ddr4_c0_ba, - output wire [1:0] ddr4_c0_bg, - output wire [0:0] ddr4_c0_ck_t, - output wire [0:0] ddr4_c0_ck_c, - output wire [0:0] ddr4_c0_cke, - output wire [0:0] ddr4_c0_cs_n, - output wire ddr4_c0_act_n, - output wire [0:0] ddr4_c0_odt, - output wire ddr4_c0_par, - output wire ddr4_c0_reset_n, - inout wire [71:0] ddr4_c0_dq, - inout wire [17:0] ddr4_c0_dqs_t, - inout wire [17:0] ddr4_c0_dqs_c, - - output wire [16:0] ddr4_c1_adr, - output wire [1:0] ddr4_c1_ba, - output wire [1:0] ddr4_c1_bg, - output wire [0:0] ddr4_c1_ck_t, - output wire [0:0] ddr4_c1_ck_c, - output wire [0:0] ddr4_c1_cke, - output wire [0:0] ddr4_c1_cs_n, - output wire ddr4_c1_act_n, - output wire [0:0] ddr4_c1_odt, - output wire ddr4_c1_par, - output wire ddr4_c1_reset_n, - inout wire [71:0] ddr4_c1_dq, - inout wire [17:0] ddr4_c1_dqs_t, - inout wire [17:0] ddr4_c1_dqs_c, - - output wire [16:0] ddr4_c2_adr, - output wire [1:0] ddr4_c2_ba, - output wire [1:0] ddr4_c2_bg, - output wire [0:0] ddr4_c2_ck_t, - output wire [0:0] ddr4_c2_ck_c, - output wire [0:0] ddr4_c2_cke, - output wire [0:0] ddr4_c2_cs_n, - output wire ddr4_c2_act_n, - output wire [0:0] ddr4_c2_odt, - output wire ddr4_c2_par, - output wire ddr4_c2_reset_n, - inout wire [71:0] ddr4_c2_dq, - inout wire [17:0] ddr4_c2_dqs_t, - inout wire [17:0] ddr4_c2_dqs_c, - - output wire [16:0] ddr4_c3_adr, - output wire [1:0] ddr4_c3_ba, - output wire [1:0] ddr4_c3_bg, - output wire [0:0] ddr4_c3_ck_t, - output wire [0:0] ddr4_c3_ck_c, - output wire [0:0] ddr4_c3_cke, - output wire [0:0] ddr4_c3_cs_n, - output wire ddr4_c3_act_n, - output wire [0:0] ddr4_c3_odt, - output wire ddr4_c3_par, - output wire ddr4_c3_reset_n, - inout wire [71:0] ddr4_c3_dq, - inout wire [17:0] ddr4_c3_dqs_t, - inout wire [17:0] ddr4_c3_dqs_c -); - -// PTP configuration -parameter PTP_CLK_PERIOD_NS_NUM = 1024; -parameter PTP_CLK_PERIOD_NS_DENOM = 165; -parameter PTP_TS_WIDTH = 96; -parameter PTP_SEPARATE_RX_CLOCK = 1; - -// Interface configuration -parameter TX_TAG_WIDTH = 16; - -// RAM configuration -parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); - -// PCIe interface configuration -parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); -parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161; -parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137; -parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183; -parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81; -parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256; -parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; -parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; -parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; -parameter RQ_SEQ_NUM_WIDTH = 6; -parameter PCIE_TAG_COUNT = 256; - -// Ethernet interface configuration -parameter AXIS_ETH_DATA_WIDTH = 512; -parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; -parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH; -parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1; -parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; - -// Clock and reset -wire pcie_user_clk; -wire pcie_user_reset; - -wire cfgmclk_int; - -wire clk_161mhz_ref_int; - -wire clk_50mhz_mmcm_out; -wire clk_125mhz_mmcm_out; - -// Internal 50 MHz clock -wire clk_50mhz_int; -wire rst_50mhz_int; - -// Internal 125 MHz clock -wire clk_125mhz_int; -wire rst_125mhz_int; - -wire mmcm_rst; -wire mmcm_locked; -wire mmcm_clkfb; - -// MMCM instance -// 161.13 MHz in, 50 MHz + 125 MHz out -// PFD range: 10 MHz to 500 MHz -// VCO range: 800 MHz to 1600 MHz -// M = 128, D = 15 sets Fvco = 1375 MHz (in range) -// Divide by 27.5 to get output frequency of 50 MHz -// Divide by 11 to get output frequency of 125 MHz -MMCME4_BASE #( - .BANDWIDTH("OPTIMIZED"), - .CLKOUT0_DIVIDE_F(27.5), - .CLKOUT0_DUTY_CYCLE(0.5), - .CLKOUT0_PHASE(0), - .CLKOUT1_DIVIDE(11), - .CLKOUT1_DUTY_CYCLE(0.5), - .CLKOUT1_PHASE(0), - .CLKOUT2_DIVIDE(1), - .CLKOUT2_DUTY_CYCLE(0.5), - .CLKOUT2_PHASE(0), - .CLKOUT3_DIVIDE(1), - .CLKOUT3_DUTY_CYCLE(0.5), - .CLKOUT3_PHASE(0), - .CLKOUT4_DIVIDE(1), - .CLKOUT4_DUTY_CYCLE(0.5), - .CLKOUT4_PHASE(0), - .CLKOUT5_DIVIDE(1), - .CLKOUT5_DUTY_CYCLE(0.5), - .CLKOUT5_PHASE(0), - .CLKOUT6_DIVIDE(1), - .CLKOUT6_DUTY_CYCLE(0.5), - .CLKOUT6_PHASE(0), - .CLKFBOUT_MULT_F(128), - .CLKFBOUT_PHASE(0), - .DIVCLK_DIVIDE(15), - .REF_JITTER1(0.010), - .CLKIN1_PERIOD(6.206), - .STARTUP_WAIT("FALSE"), - .CLKOUT4_CASCADE("FALSE") -) -clk_mmcm_inst ( - .CLKIN1(clk_161mhz_ref_int), - .CLKFBIN(mmcm_clkfb), - .RST(mmcm_rst), - .PWRDWN(1'b0), - .CLKOUT0(clk_50mhz_mmcm_out), - .CLKOUT0B(), - .CLKOUT1(clk_125mhz_mmcm_out), - .CLKOUT1B(), - .CLKOUT2(), - .CLKOUT2B(), - .CLKOUT3(), - .CLKOUT3B(), - .CLKOUT4(), - .CLKOUT5(), - .CLKOUT6(), - .CLKFBOUT(mmcm_clkfb), - .CLKFBOUTB(), - .LOCKED(mmcm_locked) -); - -BUFG -clk_50mhz_bufg_inst ( - .I(clk_50mhz_mmcm_out), - .O(clk_50mhz_int) -); - -BUFG -clk_125mhz_bufg_inst ( - .I(clk_125mhz_mmcm_out), - .O(clk_125mhz_int) -); - -sync_reset #( - .N(4) -) -sync_reset_50mhz_inst ( - .clk(clk_50mhz_int), - .rst(~mmcm_locked), - .out(rst_50mhz_int) -); - -sync_reset #( - .N(4) -) -sync_reset_125mhz_inst ( - .clk(clk_125mhz_int), - .rst(~mmcm_locked), - .out(rst_125mhz_int) -); - -// GPIO -wire btnu_int; -wire btnl_int; -wire btnd_int; -wire btnr_int; -wire btnc_int; -wire [3:0] sw_int; -wire qsfp0_modprsl_int; -wire qsfp1_modprsl_int; -wire qsfp0_intl_int; -wire qsfp1_intl_int; -wire i2c_scl_i; -wire i2c_scl_o; -wire i2c_scl_t; -wire i2c_sda_i; -wire i2c_sda_o; -wire i2c_sda_t; - -reg i2c_scl_o_reg; -reg i2c_scl_t_reg; -reg i2c_sda_o_reg; -reg i2c_sda_t_reg; - -always @(posedge pcie_user_clk) begin - i2c_scl_o_reg <= i2c_scl_o; - i2c_scl_t_reg <= i2c_scl_t; - i2c_sda_o_reg <= i2c_sda_o; - i2c_sda_t_reg <= i2c_sda_t; -end - -debounce_switch #( - .WIDTH(4), - .N(4), - .RATE(250000) -) -debounce_switch_inst ( - .clk(pcie_user_clk), - .rst(pcie_user_reset), - .in({sw}), - .out({sw_int}) -); - -sync_signal #( - .WIDTH(6), - .N(2) -) -sync_signal_inst ( - .clk(pcie_user_clk), - .in({qsfp0_modprsl, qsfp1_modprsl, qsfp0_intl, qsfp1_intl, - i2c_scl, i2c_sda}), - .out({qsfp0_modprsl_int, qsfp1_modprsl_int, qsfp0_intl_int, qsfp1_intl_int, - i2c_scl_i, i2c_sda_i}) -); - -assign i2c_scl = i2c_scl_t_reg ? 1'bz : i2c_scl_o_reg; -assign i2c_sda = i2c_sda_t_reg ? 1'bz : i2c_sda_o_reg; - -// Flash -wire qspi_clk_int; -wire [3:0] qspi_dq_int; -wire [3:0] qspi_dq_i_int; -wire [3:0] qspi_dq_o_int; -wire [3:0] qspi_dq_oe_int; -wire qspi_cs_int; - -reg qspi_clk_reg; -reg [3:0] qspi_dq_o_reg; -reg [3:0] qspi_dq_oe_reg; -reg qspi_cs_reg; - -always @(posedge pcie_user_clk) begin - qspi_clk_reg <= qspi_clk_int; - qspi_dq_o_reg <= qspi_dq_o_int; - qspi_dq_oe_reg <= qspi_dq_oe_int; - qspi_cs_reg <= qspi_cs_int; -end - -sync_signal #( - .WIDTH(4), - .N(2) -) -flash_sync_signal_inst ( - .clk(pcie_user_clk), - .in({qspi_dq_int}), - .out({qspi_dq_i_int}) -); - -// startupe3 instance -wire cfgmclk; - -STARTUPE3 -startupe3_inst ( - .CFGCLK(), - .CFGMCLK(cfgmclk), - .DI(qspi_dq_int), - .DO(qspi_dq_o_reg), - .DTS(~qspi_dq_oe_reg), - .EOS(), - .FCSBO(qspi_cs_reg), - .FCSBTS(1'b0), - .GSR(1'b0), - .GTS(1'b0), - .KEYCLEARB(1'b1), - .PACK(1'b0), - .PREQ(), - .USRCCLKO(qspi_clk_reg), - .USRCCLKTS(1'b0), - .USRDONEO(1'b0), - .USRDONETS(1'b1) -); - -BUFG -cfgmclk_bufg_inst ( - .I(cfgmclk), - .O(cfgmclk_int) -); - -// FPGA boot -wire fpga_boot; - -reg fpga_boot_sync_reg_0 = 1'b0; -reg fpga_boot_sync_reg_1 = 1'b0; -reg fpga_boot_sync_reg_2 = 1'b0; - -wire icap_avail; -reg [2:0] icap_state = 0; -reg icap_csib_reg = 1'b1; -reg icap_rdwrb_reg = 1'b0; -reg [31:0] icap_di_reg = 32'hffffffff; - -wire [31:0] icap_di_rev; - -assign icap_di_rev[ 7] = icap_di_reg[ 0]; -assign icap_di_rev[ 6] = icap_di_reg[ 1]; -assign icap_di_rev[ 5] = icap_di_reg[ 2]; -assign icap_di_rev[ 4] = icap_di_reg[ 3]; -assign icap_di_rev[ 3] = icap_di_reg[ 4]; -assign icap_di_rev[ 2] = icap_di_reg[ 5]; -assign icap_di_rev[ 1] = icap_di_reg[ 6]; -assign icap_di_rev[ 0] = icap_di_reg[ 7]; - -assign icap_di_rev[15] = icap_di_reg[ 8]; -assign icap_di_rev[14] = icap_di_reg[ 9]; -assign icap_di_rev[13] = icap_di_reg[10]; -assign icap_di_rev[12] = icap_di_reg[11]; -assign icap_di_rev[11] = icap_di_reg[12]; -assign icap_di_rev[10] = icap_di_reg[13]; -assign icap_di_rev[ 9] = icap_di_reg[14]; -assign icap_di_rev[ 8] = icap_di_reg[15]; - -assign icap_di_rev[23] = icap_di_reg[16]; -assign icap_di_rev[22] = icap_di_reg[17]; -assign icap_di_rev[21] = icap_di_reg[18]; -assign icap_di_rev[20] = icap_di_reg[19]; -assign icap_di_rev[19] = icap_di_reg[20]; -assign icap_di_rev[18] = icap_di_reg[21]; -assign icap_di_rev[17] = icap_di_reg[22]; -assign icap_di_rev[16] = icap_di_reg[23]; - -assign icap_di_rev[31] = icap_di_reg[24]; -assign icap_di_rev[30] = icap_di_reg[25]; -assign icap_di_rev[29] = icap_di_reg[26]; -assign icap_di_rev[28] = icap_di_reg[27]; -assign icap_di_rev[27] = icap_di_reg[28]; -assign icap_di_rev[26] = icap_di_reg[29]; -assign icap_di_rev[25] = icap_di_reg[30]; -assign icap_di_rev[24] = icap_di_reg[31]; - -always @(posedge clk_125mhz_int) begin - case (icap_state) - 0: begin - icap_state <= 0; - icap_csib_reg <= 1'b1; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hffffffff; // dummy word - - if (fpga_boot_sync_reg_2 && icap_avail) begin - icap_state <= 1; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hffffffff; // dummy word - end - end - 1: begin - icap_state <= 2; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hAA995566; // sync word - end - 2: begin - icap_state <= 3; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h20000000; // type 1 noop - end - 3: begin - icap_state <= 4; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h30008001; // write 1 word to CMD - end - 4: begin - icap_state <= 5; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h0000000F; // IPROG - end - 5: begin - icap_state <= 0; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h20000000; // type 1 noop - end - endcase - - fpga_boot_sync_reg_0 <= fpga_boot; - fpga_boot_sync_reg_1 <= fpga_boot_sync_reg_0; - fpga_boot_sync_reg_2 <= fpga_boot_sync_reg_1; -end - -ICAPE3 -icape3_inst ( - .AVAIL(icap_avail), - .CLK(clk_125mhz_int), - .CSIB(icap_csib_reg), - .I(icap_di_rev), - .O(), - .PRDONE(), - .PRERROR(), - .RDWRB(icap_rdwrb_reg) -); - -// BMC -wire axil_cms_clk; -wire axil_cms_rst; -wire [17:0] axil_cms_awaddr; -wire [2:0] axil_cms_awprot; -wire axil_cms_awvalid; -wire axil_cms_awready; -wire [31:0] axil_cms_wdata; -wire [3:0] axil_cms_wstrb; -wire axil_cms_wvalid; -wire axil_cms_wready; -wire [1:0] axil_cms_bresp; -wire axil_cms_bvalid; -wire axil_cms_bready; -wire [17:0] axil_cms_araddr; -wire [2:0] axil_cms_arprot; -wire axil_cms_arvalid; -wire axil_cms_arready; -wire [31:0] axil_cms_rdata; -wire [1:0] axil_cms_rresp; -wire axil_cms_rvalid; -wire axil_cms_rready; - -wire [17:0] axil_cms_awaddr_int; -wire [2:0] axil_cms_awprot_int; -wire axil_cms_awvalid_int; -wire axil_cms_awready_int; -wire [31:0] axil_cms_wdata_int; -wire [3:0] axil_cms_wstrb_int; -wire axil_cms_wvalid_int; -wire axil_cms_wready_int; -wire [1:0] axil_cms_bresp_int; -wire axil_cms_bvalid_int; -wire axil_cms_bready_int; -wire [17:0] axil_cms_araddr_int; -wire [2:0] axil_cms_arprot_int; -wire axil_cms_arvalid_int; -wire axil_cms_arready_int; -wire [31:0] axil_cms_rdata_int; -wire [1:0] axil_cms_rresp_int; -wire axil_cms_rvalid_int; -wire axil_cms_rready_int; - -axil_cdc #( - .DATA_WIDTH(32), - .ADDR_WIDTH(18) -) -cms_axil_cdc_inst ( - .s_clk(axil_cms_clk), - .s_rst(axil_cms_rst), - .s_axil_awaddr(axil_cms_awaddr), - .s_axil_awprot(axil_cms_awprot), - .s_axil_awvalid(axil_cms_awvalid), - .s_axil_awready(axil_cms_awready), - .s_axil_wdata(axil_cms_wdata), - .s_axil_wstrb(axil_cms_wstrb), - .s_axil_wvalid(axil_cms_wvalid), - .s_axil_wready(axil_cms_wready), - .s_axil_bresp(axil_cms_bresp), - .s_axil_bvalid(axil_cms_bvalid), - .s_axil_bready(axil_cms_bready), - .s_axil_araddr(axil_cms_araddr), - .s_axil_arprot(axil_cms_arprot), - .s_axil_arvalid(axil_cms_arvalid), - .s_axil_arready(axil_cms_arready), - .s_axil_rdata(axil_cms_rdata), - .s_axil_rresp(axil_cms_rresp), - .s_axil_rvalid(axil_cms_rvalid), - .s_axil_rready(axil_cms_rready), - .m_clk(clk_50mhz_int), - .m_rst(rst_50mhz_int), - .m_axil_awaddr(axil_cms_awaddr_int), - .m_axil_awprot(axil_cms_awprot_int), - .m_axil_awvalid(axil_cms_awvalid_int), - .m_axil_awready(axil_cms_awready_int), - .m_axil_wdata(axil_cms_wdata_int), - .m_axil_wstrb(axil_cms_wstrb_int), - .m_axil_wvalid(axil_cms_wvalid_int), - .m_axil_wready(axil_cms_wready_int), - .m_axil_bresp(axil_cms_bresp_int), - .m_axil_bvalid(axil_cms_bvalid_int), - .m_axil_bready(axil_cms_bready_int), - .m_axil_araddr(axil_cms_araddr_int), - .m_axil_arprot(axil_cms_arprot_int), - .m_axil_arvalid(axil_cms_arvalid_int), - .m_axil_arready(axil_cms_arready_int), - .m_axil_rdata(axil_cms_rdata_int), - .m_axil_rresp(axil_cms_rresp_int), - .m_axil_rvalid(axil_cms_rvalid_int), - .m_axil_rready(axil_cms_rready_int) -); - -cms_wrapper -cms_inst ( - .aclk_ctrl_0(clk_50mhz_int), - .aresetn_ctrl_0(~rst_50mhz_int), - .interrupt_host_0(), - .qsfp0_int_l_0(qsfp0_intl), - .qsfp0_lpmode_0(), - .qsfp0_modprs_l_0(qsfp0_modprsl), - .qsfp0_modsel_l_0(), - .qsfp0_reset_l_0(), - .qsfp1_int_l_0(qsfp1_intl), - .qsfp1_lpmode_0(), - .qsfp1_modprs_l_0(qsfp1_modprsl), - .qsfp1_modsel_l_0(), - .qsfp1_reset_l_0(), - .s_axi_ctrl_0_araddr(axil_cms_araddr_int), - .s_axi_ctrl_0_arprot(axil_cms_arprot_int), - .s_axi_ctrl_0_arready(axil_cms_arready_int), - .s_axi_ctrl_0_arvalid(axil_cms_arvalid_int), - .s_axi_ctrl_0_awaddr(axil_cms_awaddr_int), - .s_axi_ctrl_0_awprot(axil_cms_awprot_int), - .s_axi_ctrl_0_awready(axil_cms_awready_int), - .s_axi_ctrl_0_awvalid(axil_cms_awvalid_int), - .s_axi_ctrl_0_bready(axil_cms_bready_int), - .s_axi_ctrl_0_bresp(axil_cms_bresp_int), - .s_axi_ctrl_0_bvalid(axil_cms_bvalid_int), - .s_axi_ctrl_0_rdata(axil_cms_rdata_int), - .s_axi_ctrl_0_rready(axil_cms_rready_int), - .s_axi_ctrl_0_rresp(axil_cms_rresp_int), - .s_axi_ctrl_0_rvalid(axil_cms_rvalid_int), - .s_axi_ctrl_0_wdata(axil_cms_wdata_int), - .s_axi_ctrl_0_wready(axil_cms_wready_int), - .s_axi_ctrl_0_wstrb(axil_cms_wstrb_int), - .s_axi_ctrl_0_wvalid(axil_cms_wvalid_int), - .satellite_gpio_0(msp_gpio), - .satellite_uart_0_rxd(msp_uart_rxd), - .satellite_uart_0_txd(msp_uart_txd) -); - -// configure SI5335 clock generators -reg qsfp_refclk_reset_reg = 1'b1; -reg sys_reset_reg = 1'b1; - -reg [9:0] reset_timer_reg = 0; - -assign mmcm_rst = sys_reset_reg | pcie_user_reset; - -always @(posedge cfgmclk_int) begin - if (&reset_timer_reg) begin - if (qsfp_refclk_reset_reg) begin - qsfp_refclk_reset_reg <= 1'b0; - reset_timer_reg <= 0; - end else begin - qsfp_refclk_reset_reg <= 1'b0; - sys_reset_reg <= 1'b0; - end - end else begin - reset_timer_reg <= reset_timer_reg + 1; - end -end - -// PCIe -wire pcie_sys_clk; -wire pcie_sys_clk_gt; - -IBUFDS_GTE4 #( - .REFCLK_HROW_CK_SEL(2'b00) -) -ibufds_gte4_pcie_mgt_refclk_inst ( - .I (pcie_refclk_p), - .IB (pcie_refclk_n), - .CEB (1'b0), - .O (pcie_sys_clk_gt), - .ODIV2 (pcie_sys_clk) -); - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep; -wire axis_rq_tlast; -wire axis_rq_tready; -wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser; -wire axis_rq_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep; -wire axis_rc_tlast; -wire axis_rc_tready; -wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser; -wire axis_rc_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep; -wire axis_cq_tlast; -wire axis_cq_tready; -wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser; -wire axis_cq_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep; -wire axis_cc_tlast; -wire axis_cc_tready; -wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser; -wire axis_cc_tvalid; - -wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num0; -wire pcie_rq_seq_num_vld0; -wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num1; -wire pcie_rq_seq_num_vld1; - -wire [3:0] pcie_tfc_nph_av; -wire [3:0] pcie_tfc_npd_av; - -wire [2:0] cfg_max_payload; -wire [2:0] cfg_max_read_req; -wire [3:0] cfg_rcb_status; - -wire [9:0] cfg_mgmt_addr; -wire [7:0] cfg_mgmt_function_number; -wire cfg_mgmt_write; -wire [31:0] cfg_mgmt_write_data; -wire [3:0] cfg_mgmt_byte_enable; -wire cfg_mgmt_read; -wire [31:0] cfg_mgmt_read_data; -wire cfg_mgmt_read_write_done; - -wire [7:0] cfg_fc_ph; -wire [11:0] cfg_fc_pd; -wire [7:0] cfg_fc_nph; -wire [11:0] cfg_fc_npd; -wire [7:0] cfg_fc_cplh; -wire [11:0] cfg_fc_cpld; -wire [2:0] cfg_fc_sel; - -wire [3:0] cfg_interrupt_msix_enable; -wire [3:0] cfg_interrupt_msix_mask; -wire [251:0] cfg_interrupt_msix_vf_enable; -wire [251:0] cfg_interrupt_msix_vf_mask; -wire [63:0] cfg_interrupt_msix_address; -wire [31:0] cfg_interrupt_msix_data; -wire cfg_interrupt_msix_int; -wire [1:0] cfg_interrupt_msix_vec_pending; -wire cfg_interrupt_msix_vec_pending_status; -wire cfg_interrupt_msix_sent; -wire cfg_interrupt_msix_fail; -wire [7:0] cfg_interrupt_msi_function_number; - -wire status_error_cor; -wire status_error_uncor; - -// extra register for pcie_user_reset signal -wire pcie_user_reset_int; -(* shreg_extract = "no" *) -reg pcie_user_reset_reg_1 = 1'b1; -(* shreg_extract = "no" *) -reg pcie_user_reset_reg_2 = 1'b1; - -always @(posedge pcie_user_clk) begin - pcie_user_reset_reg_1 <= pcie_user_reset_int; - pcie_user_reset_reg_2 <= pcie_user_reset_reg_1; -end - -BUFG -pcie_user_reset_bufg_inst ( - .I(pcie_user_reset_reg_2), - .O(pcie_user_reset) -); - -pcie4_uscale_plus_0 -pcie4_uscale_plus_inst ( - .pci_exp_txn(pcie_tx_n), - .pci_exp_txp(pcie_tx_p), - .pci_exp_rxn(pcie_rx_n), - .pci_exp_rxp(pcie_rx_p), - .user_clk(pcie_user_clk), - .user_reset(pcie_user_reset_int), - .user_lnk_up(), - - .s_axis_rq_tdata(axis_rq_tdata), - .s_axis_rq_tkeep(axis_rq_tkeep), - .s_axis_rq_tlast(axis_rq_tlast), - .s_axis_rq_tready(axis_rq_tready), - .s_axis_rq_tuser(axis_rq_tuser), - .s_axis_rq_tvalid(axis_rq_tvalid), - - .m_axis_rc_tdata(axis_rc_tdata), - .m_axis_rc_tkeep(axis_rc_tkeep), - .m_axis_rc_tlast(axis_rc_tlast), - .m_axis_rc_tready(axis_rc_tready), - .m_axis_rc_tuser(axis_rc_tuser), - .m_axis_rc_tvalid(axis_rc_tvalid), - - .m_axis_cq_tdata(axis_cq_tdata), - .m_axis_cq_tkeep(axis_cq_tkeep), - .m_axis_cq_tlast(axis_cq_tlast), - .m_axis_cq_tready(axis_cq_tready), - .m_axis_cq_tuser(axis_cq_tuser), - .m_axis_cq_tvalid(axis_cq_tvalid), - - .s_axis_cc_tdata(axis_cc_tdata), - .s_axis_cc_tkeep(axis_cc_tkeep), - .s_axis_cc_tlast(axis_cc_tlast), - .s_axis_cc_tready(axis_cc_tready), - .s_axis_cc_tuser(axis_cc_tuser), - .s_axis_cc_tvalid(axis_cc_tvalid), - - .pcie_rq_seq_num0(pcie_rq_seq_num0), - .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0), - .pcie_rq_seq_num1(pcie_rq_seq_num1), - .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1), - .pcie_rq_tag0(), - .pcie_rq_tag1(), - .pcie_rq_tag_av(), - .pcie_rq_tag_vld0(), - .pcie_rq_tag_vld1(), - - .pcie_tfc_nph_av(pcie_tfc_nph_av), - .pcie_tfc_npd_av(pcie_tfc_npd_av), - - .pcie_cq_np_req(1'b1), - .pcie_cq_np_req_count(), - - .cfg_phy_link_down(), - .cfg_phy_link_status(), - .cfg_negotiated_width(), - .cfg_current_speed(), - .cfg_max_payload(cfg_max_payload), - .cfg_max_read_req(cfg_max_read_req), - .cfg_function_status(), - .cfg_function_power_state(), - .cfg_vf_status(), - .cfg_vf_power_state(), - .cfg_link_power_state(), - - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - .cfg_mgmt_debug_access(1'b0), - - .cfg_err_cor_out(), - .cfg_err_nonfatal_out(), - .cfg_err_fatal_out(), - .cfg_local_error_valid(), - .cfg_local_error_out(), - .cfg_ltssm_state(), - .cfg_rx_pm_state(), - .cfg_tx_pm_state(), - .cfg_rcb_status(cfg_rcb_status), - .cfg_obff_enable(), - .cfg_pl_status_change(), - .cfg_tph_requester_enable(), - .cfg_tph_st_mode(), - .cfg_vf_tph_requester_enable(), - .cfg_vf_tph_st_mode(), - - .cfg_msg_received(), - .cfg_msg_received_data(), - .cfg_msg_received_type(), - .cfg_msg_transmit(1'b0), - .cfg_msg_transmit_type(3'd0), - .cfg_msg_transmit_data(32'd0), - .cfg_msg_transmit_done(), - - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - .cfg_dsn(64'd0), - - .cfg_power_state_change_ack(1'b1), - .cfg_power_state_change_interrupt(), - - .cfg_err_cor_in(status_error_cor), - .cfg_err_uncor_in(status_error_uncor), - .cfg_flr_in_process(), - .cfg_flr_done(4'd0), - .cfg_vf_flr_in_process(), - .cfg_vf_flr_func_num(8'd0), - .cfg_vf_flr_done(8'd0), - - .cfg_link_training_enable(1'b1), - - .cfg_interrupt_int(4'd0), - .cfg_interrupt_pending(4'd0), - .cfg_interrupt_sent(), - .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), - .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), - .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), - .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), - .cfg_interrupt_msix_address(cfg_interrupt_msix_address), - .cfg_interrupt_msix_data(cfg_interrupt_msix_data), - .cfg_interrupt_msix_int(cfg_interrupt_msix_int), - .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), - .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), - .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent), - .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - .cfg_pm_aspm_l1_entry_reject(1'b0), - .cfg_pm_aspm_tx_l0s_entry_disable(1'b0), - - .cfg_hot_reset_out(), - - .cfg_config_space_enable(1'b1), - .cfg_req_pm_transition_l23_ready(1'b0), - .cfg_hot_reset_in(1'b0), - - .cfg_ds_port_number(8'd0), - .cfg_ds_bus_number(8'd0), - .cfg_ds_device_number(5'd0), - - .sys_clk(pcie_sys_clk), - .sys_clk_gt(pcie_sys_clk_gt), - .sys_reset(pcie_reset_n), - - .phy_rdy_out() -); - -// QSFP0 CMAC -assign qsfp0_refclk_reset = qsfp_refclk_reset_reg; -assign qsfp0_fs = 2'b10; - -wire qsfp0_tx_clk_int; -wire qsfp0_tx_rst_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_tx_axis_tkeep_int; -wire qsfp0_tx_axis_tvalid_int; -wire qsfp0_tx_axis_tready_int; -wire qsfp0_tx_axis_tlast_int; -wire [16+1-1:0] qsfp0_tx_axis_tuser_int; - -wire [79:0] qsfp0_tx_ptp_time_int; -wire [79:0] qsfp0_tx_ptp_ts_int; -wire [15:0] qsfp0_tx_ptp_ts_tag_int; -wire qsfp0_tx_ptp_ts_valid_int; - -wire qsfp0_rx_clk_int; -wire qsfp0_rx_rst_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_rx_axis_tkeep_int; -wire qsfp0_rx_axis_tvalid_int; -wire qsfp0_rx_axis_tlast_int; -wire [80+1-1:0] qsfp0_rx_axis_tuser_int; - -wire qsfp0_rx_ptp_clk_int; -wire qsfp0_rx_ptp_rst_int; -wire [79:0] qsfp0_rx_ptp_time_int; - -wire qsfp0_drp_clk = clk_125mhz_int; -wire qsfp0_drp_rst = rst_125mhz_int; -wire [23:0] qsfp0_drp_addr; -wire [15:0] qsfp0_drp_di; -wire qsfp0_drp_en; -wire qsfp0_drp_we; -wire [15:0] qsfp0_drp_do; -wire qsfp0_drp_rdy; - -wire qsfp0_tx_enable; -wire qsfp0_tx_lfc_en; -wire qsfp0_tx_lfc_req; -wire [7:0] qsfp0_tx_pfc_en; -wire [7:0] qsfp0_tx_pfc_req; - -wire qsfp0_rx_enable; -wire qsfp0_rx_status; -wire qsfp0_rx_lfc_en; -wire qsfp0_rx_lfc_req; -wire qsfp0_rx_lfc_ack; -wire [7:0] qsfp0_rx_pfc_en; -wire [7:0] qsfp0_rx_pfc_req; -wire [7:0] qsfp0_rx_pfc_ack; - -wire qsfp0_gtpowergood; - -wire qsfp0_mgt_refclk_1; -wire qsfp0_mgt_refclk_1_int; -wire qsfp0_mgt_refclk_1_bufg; - -assign clk_161mhz_ref_int = qsfp0_mgt_refclk_1_bufg; - -IBUFDS_GTE4 ibufds_gte4_qsfp0_mgt_refclk_1_inst ( - .I (qsfp0_mgt_refclk_1_p), - .IB (qsfp0_mgt_refclk_1_n), - .CEB (1'b0), - .O (qsfp0_mgt_refclk_1), - .ODIV2 (qsfp0_mgt_refclk_1_int) -); - -BUFG_GT bufg_gt_qsfp0_mgt_refclk_1_inst ( - .CE (qsfp0_gtpowergood), - .CEMASK (1'b1), - .CLR (1'b0), - .CLRMASK (1'b1), - .DIV (3'd0), - .I (qsfp0_mgt_refclk_1_int), - .O (qsfp0_mgt_refclk_1_bufg) -); - -wire qsfp0_rst; - -sync_reset #( - .N(4) -) -qsfp0_sync_reset_inst ( - .clk(qsfp0_mgt_refclk_1_bufg), - .rst(rst_125mhz_int), - .out(qsfp0_rst) -); - -cmac_gty_wrapper #( - .DRP_CLK_FREQ_HZ(125000000), - .AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .TX_SERDES_PIPELINE(0), - .RX_SERDES_PIPELINE(0), - .RS_FEC_ENABLE(1) -) -qsfp0_cmac_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp0_rst), - - /* - * Common - */ - .xcvr_gtpowergood_out(qsfp0_gtpowergood), - .xcvr_ref_clk(qsfp0_mgt_refclk_1), - - /* - * DRP - */ - .drp_clk(qsfp0_drp_clk), - .drp_rst(qsfp0_drp_rst), - .drp_addr(qsfp0_drp_addr), - .drp_di(qsfp0_drp_di), - .drp_en(qsfp0_drp_en), - .drp_we(qsfp0_drp_we), - .drp_do(qsfp0_drp_do), - .drp_rdy(qsfp0_drp_rdy), - - /* - * Serial data - */ - .xcvr_txp(qsfp0_tx_p), - .xcvr_txn(qsfp0_tx_n), - .xcvr_rxp(qsfp0_rx_p), - .xcvr_rxn(qsfp0_rx_n), - - /* - * CMAC connections - */ - .tx_clk(qsfp0_tx_clk_int), - .tx_rst(qsfp0_tx_rst_int), - - .tx_axis_tdata(qsfp0_tx_axis_tdata_int), - .tx_axis_tkeep(qsfp0_tx_axis_tkeep_int), - .tx_axis_tvalid(qsfp0_tx_axis_tvalid_int), - .tx_axis_tready(qsfp0_tx_axis_tready_int), - .tx_axis_tlast(qsfp0_tx_axis_tlast_int), - .tx_axis_tuser(qsfp0_tx_axis_tuser_int), - - .tx_ptp_time(qsfp0_tx_ptp_time_int), - .tx_ptp_ts(qsfp0_tx_ptp_ts_int), - .tx_ptp_ts_tag(qsfp0_tx_ptp_ts_tag_int), - .tx_ptp_ts_valid(qsfp0_tx_ptp_ts_valid_int), - - .tx_enable(qsfp0_tx_enable), - .tx_lfc_en(qsfp0_tx_lfc_en), - .tx_lfc_req(qsfp0_tx_lfc_req), - .tx_pfc_en(qsfp0_tx_pfc_en), - .tx_pfc_req(qsfp0_tx_pfc_req), - - .rx_clk(qsfp0_rx_clk_int), - .rx_rst(qsfp0_rx_rst_int), - - .rx_axis_tdata(qsfp0_rx_axis_tdata_int), - .rx_axis_tkeep(qsfp0_rx_axis_tkeep_int), - .rx_axis_tvalid(qsfp0_rx_axis_tvalid_int), - .rx_axis_tlast(qsfp0_rx_axis_tlast_int), - .rx_axis_tuser(qsfp0_rx_axis_tuser_int), - - .rx_ptp_clk(qsfp0_rx_ptp_clk_int), - .rx_ptp_rst(qsfp0_rx_ptp_rst_int), - .rx_ptp_time(qsfp0_rx_ptp_time_int), - - .rx_enable(qsfp0_rx_enable), - .rx_status(qsfp0_rx_status), - .rx_lfc_en(qsfp0_rx_lfc_en), - .rx_lfc_req(qsfp0_rx_lfc_req), - .rx_lfc_ack(qsfp0_rx_lfc_ack), - .rx_pfc_en(qsfp0_rx_pfc_en), - .rx_pfc_req(qsfp0_rx_pfc_req), - .rx_pfc_ack(qsfp0_rx_pfc_ack) -); - -// QSFP1 CMAC -assign qsfp1_refclk_reset = qsfp_refclk_reset_reg; -assign qsfp1_fs = 2'b10; - -wire qsfp1_tx_clk_int; -wire qsfp1_tx_rst_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_tx_axis_tkeep_int; -wire qsfp1_tx_axis_tvalid_int; -wire qsfp1_tx_axis_tready_int; -wire qsfp1_tx_axis_tlast_int; -wire [16+1-1:0] qsfp1_tx_axis_tuser_int; - -wire [79:0] qsfp1_tx_ptp_time_int; -wire [79:0] qsfp1_tx_ptp_ts_int; -wire [15:0] qsfp1_tx_ptp_ts_tag_int; -wire qsfp1_tx_ptp_ts_valid_int; - -wire qsfp1_rx_clk_int; -wire qsfp1_rx_rst_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_rx_axis_tkeep_int; -wire qsfp1_rx_axis_tvalid_int; -wire qsfp1_rx_axis_tlast_int; -wire [80+1-1:0] qsfp1_rx_axis_tuser_int; - -wire qsfp1_rx_ptp_clk_int; -wire qsfp1_rx_ptp_rst_int; -wire [79:0] qsfp1_rx_ptp_time_int; - -wire qsfp1_drp_clk = clk_125mhz_int; -wire qsfp1_drp_rst = rst_125mhz_int; -wire [23:0] qsfp1_drp_addr; -wire [15:0] qsfp1_drp_di; -wire qsfp1_drp_en; -wire qsfp1_drp_we; -wire [15:0] qsfp1_drp_do; -wire qsfp1_drp_rdy; - -wire qsfp1_tx_enable; -wire qsfp1_tx_lfc_en; -wire qsfp1_tx_lfc_req; -wire [7:0] qsfp1_tx_pfc_en; -wire [7:0] qsfp1_tx_pfc_req; - -wire qsfp1_rx_enable; -wire qsfp1_rx_status; -wire qsfp1_rx_lfc_en; -wire qsfp1_rx_lfc_req; -wire qsfp1_rx_lfc_ack; -wire [7:0] qsfp1_rx_pfc_en; -wire [7:0] qsfp1_rx_pfc_req; -wire [7:0] qsfp1_rx_pfc_ack; - -wire qsfp1_gtpowergood; - -wire qsfp1_mgt_refclk_1; -wire qsfp1_mgt_refclk_1_int; -wire qsfp1_mgt_refclk_1_bufg; - -IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_1_inst ( - .I (qsfp1_mgt_refclk_1_p), - .IB (qsfp1_mgt_refclk_1_n), - .CEB (1'b0), - .O (qsfp1_mgt_refclk_1), - .ODIV2 (qsfp1_mgt_refclk_1_int) -); - -BUFG_GT bufg_gt_qsfp1_mgt_refclk_1_inst ( - .CE (qsfp1_gtpowergood), - .CEMASK (1'b1), - .CLR (1'b0), - .CLRMASK (1'b1), - .DIV (3'd0), - .I (qsfp1_mgt_refclk_1_int), - .O (qsfp1_mgt_refclk_1_bufg) -); - -wire qsfp1_rst; - -sync_reset #( - .N(4) -) -qsfp1_sync_reset_inst ( - .clk(qsfp1_mgt_refclk_1_bufg), - .rst(rst_125mhz_int), - .out(qsfp1_rst) -); - -cmac_gty_wrapper #( - .DRP_CLK_FREQ_HZ(125000000), - .AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .TX_SERDES_PIPELINE(0), - .RX_SERDES_PIPELINE(0), - .RS_FEC_ENABLE(1) -) -qsfp1_cmac_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp1_rst), - - /* - * Common - */ - .xcvr_gtpowergood_out(qsfp1_gtpowergood), - .xcvr_ref_clk(qsfp1_mgt_refclk_1), - - /* - * DRP - */ - .drp_clk(qsfp1_drp_clk), - .drp_rst(qsfp1_drp_rst), - .drp_addr(qsfp1_drp_addr), - .drp_di(qsfp1_drp_di), - .drp_en(qsfp1_drp_en), - .drp_we(qsfp1_drp_we), - .drp_do(qsfp1_drp_do), - .drp_rdy(qsfp1_drp_rdy), - - /* - * Serial data - */ - .xcvr_txp(qsfp1_tx_p), - .xcvr_txn(qsfp1_tx_n), - .xcvr_rxp(qsfp1_rx_p), - .xcvr_rxn(qsfp1_rx_n), - - /* - * CMAC connections - */ - .tx_clk(qsfp1_tx_clk_int), - .tx_rst(qsfp1_tx_rst_int), - - .tx_axis_tdata(qsfp1_tx_axis_tdata_int), - .tx_axis_tkeep(qsfp1_tx_axis_tkeep_int), - .tx_axis_tvalid(qsfp1_tx_axis_tvalid_int), - .tx_axis_tready(qsfp1_tx_axis_tready_int), - .tx_axis_tlast(qsfp1_tx_axis_tlast_int), - .tx_axis_tuser(qsfp1_tx_axis_tuser_int), - - .tx_ptp_time(qsfp1_tx_ptp_time_int), - .tx_ptp_ts(qsfp1_tx_ptp_ts_int), - .tx_ptp_ts_tag(qsfp1_tx_ptp_ts_tag_int), - .tx_ptp_ts_valid(qsfp1_tx_ptp_ts_valid_int), - - .tx_enable(qsfp1_tx_enable), - .tx_lfc_en(qsfp1_tx_lfc_en), - .tx_lfc_req(qsfp1_tx_lfc_req), - .tx_pfc_en(qsfp1_tx_pfc_en), - .tx_pfc_req(qsfp1_tx_pfc_req), - - .rx_clk(qsfp1_rx_clk_int), - .rx_rst(qsfp1_rx_rst_int), - - .rx_axis_tdata(qsfp1_rx_axis_tdata_int), - .rx_axis_tkeep(qsfp1_rx_axis_tkeep_int), - .rx_axis_tvalid(qsfp1_rx_axis_tvalid_int), - .rx_axis_tlast(qsfp1_rx_axis_tlast_int), - .rx_axis_tuser(qsfp1_rx_axis_tuser_int), - - .rx_ptp_clk(qsfp1_rx_ptp_clk_int), - .rx_ptp_rst(qsfp1_rx_ptp_rst_int), - .rx_ptp_time(qsfp1_rx_ptp_time_int), - - .rx_enable(qsfp1_rx_enable), - .rx_status(qsfp1_rx_status), - .rx_lfc_en(qsfp1_rx_lfc_en), - .rx_lfc_req(qsfp1_rx_lfc_req), - .rx_lfc_ack(qsfp1_rx_lfc_ack), - .rx_pfc_en(qsfp1_rx_pfc_en), - .rx_pfc_req(qsfp1_rx_pfc_req), - .rx_pfc_ack(qsfp1_rx_pfc_ack) -); - -wire ptp_clk; -wire ptp_rst; -wire ptp_sample_clk; - -assign ptp_clk = qsfp0_mgt_refclk_1_bufg; -assign ptp_rst = qsfp0_rst; -assign ptp_sample_clk = clk_125mhz_int; - -wire [2:0] led_int; - -assign led[0] = led_int[0]; // red -assign led[1] = qsfp1_rx_status; // yellow -assign led[2] = qsfp0_rx_status; // green - -// DDR4 -wire [DDR_CH-1:0] ddr_clk; -wire [DDR_CH-1:0] ddr_rst; - -wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; -wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; -wire [DDR_CH*8-1:0] m_axi_ddr_awlen; -wire [DDR_CH*3-1:0] m_axi_ddr_awsize; -wire [DDR_CH*2-1:0] m_axi_ddr_awburst; -wire [DDR_CH-1:0] m_axi_ddr_awlock; -wire [DDR_CH*4-1:0] m_axi_ddr_awcache; -wire [DDR_CH*3-1:0] m_axi_ddr_awprot; -wire [DDR_CH*4-1:0] m_axi_ddr_awqos; -wire [DDR_CH-1:0] m_axi_ddr_awvalid; -wire [DDR_CH-1:0] m_axi_ddr_awready; -wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; -wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; -wire [DDR_CH-1:0] m_axi_ddr_wlast; -wire [DDR_CH-1:0] m_axi_ddr_wvalid; -wire [DDR_CH-1:0] m_axi_ddr_wready; -wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; -wire [DDR_CH*2-1:0] m_axi_ddr_bresp; -wire [DDR_CH-1:0] m_axi_ddr_bvalid; -wire [DDR_CH-1:0] m_axi_ddr_bready; -wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; -wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; -wire [DDR_CH*8-1:0] m_axi_ddr_arlen; -wire [DDR_CH*3-1:0] m_axi_ddr_arsize; -wire [DDR_CH*2-1:0] m_axi_ddr_arburst; -wire [DDR_CH-1:0] m_axi_ddr_arlock; -wire [DDR_CH*4-1:0] m_axi_ddr_arcache; -wire [DDR_CH*3-1:0] m_axi_ddr_arprot; -wire [DDR_CH*4-1:0] m_axi_ddr_arqos; -wire [DDR_CH-1:0] m_axi_ddr_arvalid; -wire [DDR_CH-1:0] m_axi_ddr_arready; -wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; -wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; -wire [DDR_CH*2-1:0] m_axi_ddr_rresp; -wire [DDR_CH-1:0] m_axi_ddr_rlast; -wire [DDR_CH-1:0] m_axi_ddr_rvalid; -wire [DDR_CH-1:0] m_axi_ddr_rready; - -wire [DDR_CH-1:0] ddr_status; - -generate - -if (DDR_ENABLE && DDR_CH > 0) begin - -reg ddr4_rst_reg = 1'b1; - -always @(posedge pcie_user_clk or posedge pcie_user_reset) begin - if (pcie_user_reset) begin - ddr4_rst_reg <= 1'b1; - end else begin - ddr4_rst_reg <= 1'b0; - end -end - -ddr4_0 ddr4_c0_inst ( - .c0_sys_clk_p(clk_300mhz_0_p), - .c0_sys_clk_n(clk_300mhz_0_n), - .sys_rst(ddr4_rst_reg), - - .c0_init_calib_complete(ddr_status[0 +: 1]), - .c0_ddr4_interrupt(), - .dbg_clk(), - .dbg_bus(), - - .c0_ddr4_adr(ddr4_c0_adr), - .c0_ddr4_ba(ddr4_c0_ba), - .c0_ddr4_cke(ddr4_c0_cke), - .c0_ddr4_cs_n(ddr4_c0_cs_n), - .c0_ddr4_dq(ddr4_c0_dq), - .c0_ddr4_dqs_t(ddr4_c0_dqs_t), - .c0_ddr4_dqs_c(ddr4_c0_dqs_c), - .c0_ddr4_odt(ddr4_c0_odt), - .c0_ddr4_parity(ddr4_c0_par), - .c0_ddr4_bg(ddr4_c0_bg), - .c0_ddr4_reset_n(ddr4_c0_reset_n), - .c0_ddr4_act_n(ddr4_c0_act_n), - .c0_ddr4_ck_t(ddr4_c0_ck_t), - .c0_ddr4_ck_c(ddr4_c0_ck_c), - - .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), - .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), - - .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), - - .c0_ddr4_s_axi_ctrl_awvalid(1'b0), - .c0_ddr4_s_axi_ctrl_awready(), - .c0_ddr4_s_axi_ctrl_awaddr(32'd0), - .c0_ddr4_s_axi_ctrl_wvalid(1'b0), - .c0_ddr4_s_axi_ctrl_wready(), - .c0_ddr4_s_axi_ctrl_wdata(32'd0), - .c0_ddr4_s_axi_ctrl_bvalid(), - .c0_ddr4_s_axi_ctrl_bready(1'b1), - .c0_ddr4_s_axi_ctrl_bresp(), - .c0_ddr4_s_axi_ctrl_arvalid(1'b0), - .c0_ddr4_s_axi_ctrl_arready(), - .c0_ddr4_s_axi_ctrl_araddr(31'd0), - .c0_ddr4_s_axi_ctrl_rvalid(), - .c0_ddr4_s_axi_ctrl_rready(1'b1), - .c0_ddr4_s_axi_ctrl_rdata(), - .c0_ddr4_s_axi_ctrl_rresp(), - - .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), - .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), - .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), - .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), - .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), - .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), - .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), - .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), - .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), - .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), - .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), - .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), - .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), - .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), - .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), - .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), - .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), - .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), - .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), - .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), - .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), - .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), - .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), - .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), - .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), - .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), - .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), - .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), - .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), - .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), - .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) -); - -end else begin - -assign ddr4_c0_adr = {17{1'bz}}; -assign ddr4_c0_ba = {2{1'bz}}; -assign ddr4_c0_bg = {2{1'bz}}; -assign ddr4_c0_cke = 1'bz; -assign ddr4_c0_cs_n = 1'bz; -assign ddr4_c0_act_n = 1'bz; -assign ddr4_c0_odt = 1'bz; -assign ddr4_c0_par = 1'bz; -assign ddr4_c0_reset_n = 1'b0; -assign ddr4_c0_dq = {72{1'bz}}; -assign ddr4_c0_dqs_t = {18{1'bz}}; -assign ddr4_c0_dqs_c = {18{1'bz}}; - -OBUFTDS ddr4_c0_ck_obuftds_inst ( - .I(1'b0), - .T(1'b1), - .O(ddr4_c0_ck_t), - .OB(ddr4_c0_ck_c) -); - -assign ddr_clk = 0; -assign ddr_rst = 0; - -assign m_axi_ddr_awready = 0; -assign m_axi_ddr_wready = 0; -assign m_axi_ddr_bid = 0; -assign m_axi_ddr_bresp = 0; -assign m_axi_ddr_bvalid = 0; -assign m_axi_ddr_arready = 0; -assign m_axi_ddr_rid = 0; -assign m_axi_ddr_rdata = 0; -assign m_axi_ddr_rresp = 0; -assign m_axi_ddr_rlast = 0; -assign m_axi_ddr_rvalid = 0; - -assign ddr_status = 0; - -end - -if (DDR_ENABLE && DDR_CH > 1) begin - -reg ddr4_rst_reg = 1'b1; - -always @(posedge pcie_user_clk or posedge pcie_user_reset) begin - if (pcie_user_reset) begin - ddr4_rst_reg <= 1'b1; - end else begin - ddr4_rst_reg <= 1'b0; - end -end - -ddr4_0 ddr4_c1_inst ( - .c0_sys_clk_p(clk_300mhz_1_p), - .c0_sys_clk_n(clk_300mhz_1_n), - .sys_rst(ddr4_rst_reg), - - .c0_init_calib_complete(ddr_status[1 +: 1]), - .c0_ddr4_interrupt(), - .dbg_clk(), - .dbg_bus(), - - .c0_ddr4_adr(ddr4_c1_adr), - .c0_ddr4_ba(ddr4_c1_ba), - .c0_ddr4_cke(ddr4_c1_cke), - .c0_ddr4_cs_n(ddr4_c1_cs_n), - .c0_ddr4_dq(ddr4_c1_dq), - .c0_ddr4_dqs_t(ddr4_c1_dqs_t), - .c0_ddr4_dqs_c(ddr4_c1_dqs_c), - .c0_ddr4_odt(ddr4_c1_odt), - .c0_ddr4_parity(ddr4_c1_par), - .c0_ddr4_bg(ddr4_c1_bg), - .c0_ddr4_reset_n(ddr4_c1_reset_n), - .c0_ddr4_act_n(ddr4_c1_act_n), - .c0_ddr4_ck_t(ddr4_c1_ck_t), - .c0_ddr4_ck_c(ddr4_c1_ck_c), - - .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), - .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), - - .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), - - .c0_ddr4_s_axi_ctrl_awvalid(1'b0), - .c0_ddr4_s_axi_ctrl_awready(), - .c0_ddr4_s_axi_ctrl_awaddr(32'd0), - .c0_ddr4_s_axi_ctrl_wvalid(1'b0), - .c0_ddr4_s_axi_ctrl_wready(), - .c0_ddr4_s_axi_ctrl_wdata(32'd0), - .c0_ddr4_s_axi_ctrl_bvalid(), - .c0_ddr4_s_axi_ctrl_bready(1'b1), - .c0_ddr4_s_axi_ctrl_bresp(), - .c0_ddr4_s_axi_ctrl_arvalid(1'b0), - .c0_ddr4_s_axi_ctrl_arready(), - .c0_ddr4_s_axi_ctrl_araddr(31'd0), - .c0_ddr4_s_axi_ctrl_rvalid(), - .c0_ddr4_s_axi_ctrl_rready(1'b1), - .c0_ddr4_s_axi_ctrl_rdata(), - .c0_ddr4_s_axi_ctrl_rresp(), - - .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), - .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), - .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), - .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), - .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), - .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), - .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), - .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), - .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), - .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), - .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), - .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), - .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), - .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), - .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), - .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), - .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), - .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), - .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), - .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), - .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), - .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), - .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), - .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), - .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), - .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), - .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), - .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), - .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), - .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), - .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) -); - -end else begin - -assign ddr4_c1_adr = {17{1'bz}}; -assign ddr4_c1_ba = {2{1'bz}}; -assign ddr4_c1_bg = {2{1'bz}}; -assign ddr4_c1_cke = 1'bz; -assign ddr4_c1_cs_n = 1'bz; -assign ddr4_c1_act_n = 1'bz; -assign ddr4_c1_odt = 1'bz; -assign ddr4_c1_par = 1'bz; -assign ddr4_c1_reset_n = 1'b0; -assign ddr4_c1_dq = {72{1'bz}}; -assign ddr4_c1_dqs_t = {18{1'bz}}; -assign ddr4_c1_dqs_c = {18{1'bz}}; - -OBUFTDS ddr4_c1_ck_obuftds_inst ( - .I(1'b0), - .T(1'b1), - .O(ddr4_c1_ck_t), - .OB(ddr4_c1_ck_c) -); - -end - -if (DDR_ENABLE && DDR_CH > 2) begin - -reg ddr4_rst_reg = 1'b1; - -always @(posedge pcie_user_clk or posedge pcie_user_reset) begin - if (pcie_user_reset) begin - ddr4_rst_reg <= 1'b1; - end else begin - ddr4_rst_reg <= 1'b0; - end -end - -ddr4_0 ddr4_c2_inst ( - .c0_sys_clk_p(clk_300mhz_2_p), - .c0_sys_clk_n(clk_300mhz_2_n), - .sys_rst(ddr4_rst_reg), - - .c0_init_calib_complete(ddr_status[2 +: 1]), - .c0_ddr4_interrupt(), - .dbg_clk(), - .dbg_bus(), - - .c0_ddr4_adr(ddr4_c2_adr), - .c0_ddr4_ba(ddr4_c2_ba), - .c0_ddr4_cke(ddr4_c2_cke), - .c0_ddr4_cs_n(ddr4_c2_cs_n), - .c0_ddr4_dq(ddr4_c2_dq), - .c0_ddr4_dqs_t(ddr4_c2_dqs_t), - .c0_ddr4_dqs_c(ddr4_c2_dqs_c), - .c0_ddr4_odt(ddr4_c2_odt), - .c0_ddr4_parity(ddr4_c2_par), - .c0_ddr4_bg(ddr4_c2_bg), - .c0_ddr4_reset_n(ddr4_c2_reset_n), - .c0_ddr4_act_n(ddr4_c2_act_n), - .c0_ddr4_ck_t(ddr4_c2_ck_t), - .c0_ddr4_ck_c(ddr4_c2_ck_c), - - .c0_ddr4_ui_clk(ddr_clk[2 +: 1]), - .c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]), - - .c0_ddr4_aresetn(!ddr_rst[2 +: 1]), - - .c0_ddr4_s_axi_ctrl_awvalid(1'b0), - .c0_ddr4_s_axi_ctrl_awready(), - .c0_ddr4_s_axi_ctrl_awaddr(32'd0), - .c0_ddr4_s_axi_ctrl_wvalid(1'b0), - .c0_ddr4_s_axi_ctrl_wready(), - .c0_ddr4_s_axi_ctrl_wdata(32'd0), - .c0_ddr4_s_axi_ctrl_bvalid(), - .c0_ddr4_s_axi_ctrl_bready(1'b1), - .c0_ddr4_s_axi_ctrl_bresp(), - .c0_ddr4_s_axi_ctrl_arvalid(1'b0), - .c0_ddr4_s_axi_ctrl_arready(), - .c0_ddr4_s_axi_ctrl_araddr(31'd0), - .c0_ddr4_s_axi_ctrl_rvalid(), - .c0_ddr4_s_axi_ctrl_rready(1'b1), - .c0_ddr4_s_axi_ctrl_rdata(), - .c0_ddr4_s_axi_ctrl_rresp(), - - .c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]), - .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]), - .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]), - .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]), - .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]), - .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]), - .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]), - .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]), - .c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]), - .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), - .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), - .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]), - .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]), - .c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]), - .c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]), - .c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]), - .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]), - .c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]), - .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]), - .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]), - .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]), - .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]), - .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]), - .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]), - .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]), - .c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]), - .c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]), - .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]), - .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]), - .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]), - .c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) -); - -end else begin - -assign ddr4_c2_adr = {17{1'bz}}; -assign ddr4_c2_ba = {2{1'bz}}; -assign ddr4_c2_bg = {2{1'bz}}; -assign ddr4_c2_cke = 1'bz; -assign ddr4_c2_cs_n = 1'bz; -assign ddr4_c2_act_n = 1'bz; -assign ddr4_c2_odt = 1'bz; -assign ddr4_c2_par = 1'bz; -assign ddr4_c2_reset_n = 1'b0; -assign ddr4_c2_dq = {72{1'bz}}; -assign ddr4_c2_dqs_t = {18{1'bz}}; -assign ddr4_c2_dqs_c = {18{1'bz}}; - -OBUFTDS ddr4_c2_ck_obuftds_inst ( - .I(1'b0), - .T(1'b1), - .O(ddr4_c2_ck_t), - .OB(ddr4_c2_ck_c) -); - -end - -if (DDR_ENABLE && DDR_CH > 3) begin - -reg ddr4_rst_reg = 1'b1; - -always @(posedge pcie_user_clk or posedge pcie_user_reset) begin - if (pcie_user_reset) begin - ddr4_rst_reg <= 1'b1; - end else begin - ddr4_rst_reg <= 1'b0; - end -end - -ddr4_0 ddr4_c3_inst ( - .c0_sys_clk_p(clk_300mhz_3_p), - .c0_sys_clk_n(clk_300mhz_3_n), - .sys_rst(ddr4_rst_reg), - - .c0_init_calib_complete(ddr_status[3 +: 1]), - .c0_ddr4_interrupt(), - .dbg_clk(), - .dbg_bus(), - - .c0_ddr4_adr(ddr4_c3_adr), - .c0_ddr4_ba(ddr4_c3_ba), - .c0_ddr4_cke(ddr4_c3_cke), - .c0_ddr4_cs_n(ddr4_c3_cs_n), - .c0_ddr4_dq(ddr4_c3_dq), - .c0_ddr4_dqs_t(ddr4_c3_dqs_t), - .c0_ddr4_dqs_c(ddr4_c3_dqs_c), - .c0_ddr4_odt(ddr4_c3_odt), - .c0_ddr4_parity(ddr4_c3_par), - .c0_ddr4_bg(ddr4_c3_bg), - .c0_ddr4_reset_n(ddr4_c3_reset_n), - .c0_ddr4_act_n(ddr4_c3_act_n), - .c0_ddr4_ck_t(ddr4_c3_ck_t), - .c0_ddr4_ck_c(ddr4_c3_ck_c), - - .c0_ddr4_ui_clk(ddr_clk[3 +: 1]), - .c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]), - - .c0_ddr4_aresetn(!ddr_rst[3 +: 1]), - - .c0_ddr4_s_axi_ctrl_awvalid(1'b0), - .c0_ddr4_s_axi_ctrl_awready(), - .c0_ddr4_s_axi_ctrl_awaddr(32'd0), - .c0_ddr4_s_axi_ctrl_wvalid(1'b0), - .c0_ddr4_s_axi_ctrl_wready(), - .c0_ddr4_s_axi_ctrl_wdata(32'd0), - .c0_ddr4_s_axi_ctrl_bvalid(), - .c0_ddr4_s_axi_ctrl_bready(1'b1), - .c0_ddr4_s_axi_ctrl_bresp(), - .c0_ddr4_s_axi_ctrl_arvalid(1'b0), - .c0_ddr4_s_axi_ctrl_arready(), - .c0_ddr4_s_axi_ctrl_araddr(31'd0), - .c0_ddr4_s_axi_ctrl_rvalid(), - .c0_ddr4_s_axi_ctrl_rready(1'b1), - .c0_ddr4_s_axi_ctrl_rdata(), - .c0_ddr4_s_axi_ctrl_rresp(), - - .c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]), - .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]), - .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]), - .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]), - .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]), - .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]), - .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]), - .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]), - .c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]), - .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), - .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), - .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]), - .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]), - .c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]), - .c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]), - .c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]), - .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]), - .c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]), - .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]), - .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]), - .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]), - .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]), - .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]), - .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]), - .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]), - .c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]), - .c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]), - .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]), - .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]), - .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]), - .c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) -); - -end else begin - -assign ddr4_c3_adr = {17{1'bz}}; -assign ddr4_c3_ba = {2{1'bz}}; -assign ddr4_c3_bg = {2{1'bz}}; -assign ddr4_c3_cke = 1'bz; -assign ddr4_c3_cs_n = 1'bz; -assign ddr4_c3_act_n = 1'bz; -assign ddr4_c3_odt = 1'bz; -assign ddr4_c3_par = 1'bz; -assign ddr4_c3_reset_n = 1'b0; -assign ddr4_c3_dq = {72{1'bz}}; -assign ddr4_c3_dqs_t = {18{1'bz}}; -assign ddr4_c3_dqs_c = {18{1'bz}}; - -OBUFTDS ddr4_c3_ck_obuftds_inst ( - .I(1'b0), - .T(1'b1), - .O(ddr4_c3_ck_t), - .OB(ddr4_c3_ck_c) -); - -end - -endgenerate - -fpga_core #( - // FW and board IDs - .FPGA_ID(FPGA_ID), - .FW_ID(FW_ID), - .FW_VER(FW_VER), - .BOARD_ID(BOARD_ID), - .BOARD_VER(BOARD_VER), - .BUILD_DATE(BUILD_DATE), - .GIT_HASH(GIT_HASH), - .RELEASE_INFO(RELEASE_INFO), - - // Structural configuration - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - .SCHED_PER_IF(SCHED_PER_IF), - .PORT_MASK(PORT_MASK), - - // Clock configuration - .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), - .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), - - // PTP configuration - .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), - .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), - .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), - .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), - - // Queue manager configuration - .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), - .EQN_WIDTH(EQN_WIDTH), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .CQN_WIDTH(CQN_WIDTH), - .EQ_PIPELINE(EQ_PIPELINE), - .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), - .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .CQ_PIPELINE(CQ_PIPELINE), - - // TX and RX engine configuration - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), - - // Scheduler configuration - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - - // Interface configuration - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), - .TX_TAG_WIDTH(TX_TAG_WIDTH), - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .PFC_ENABLE(PFC_ENABLE), - .LFC_ENABLE(LFC_ENABLE), - .TX_FIFO_DEPTH(TX_FIFO_DEPTH), - .RX_FIFO_DEPTH(RX_FIFO_DEPTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - - // RAM configuration - .DDR_CH(DDR_CH), - .DDR_ENABLE(DDR_ENABLE), - .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), - .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), - .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), - .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), - .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), - .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), - - // Application block configuration - .APP_ID(APP_ID), - .APP_ENABLE(APP_ENABLE), - .APP_CTRL_ENABLE(APP_CTRL_ENABLE), - .APP_DMA_ENABLE(APP_DMA_ENABLE), - .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), - .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), - .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), - .APP_STAT_ENABLE(APP_STAT_ENABLE), - - // DMA interface configuration - .DMA_IMM_ENABLE(DMA_IMM_ENABLE), - .DMA_IMM_WIDTH(DMA_IMM_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - - // PCIe interface configuration - .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), - .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), - .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), - .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), - .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), - .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), - .RC_STRADDLE(RC_STRADDLE), - .RQ_STRADDLE(RQ_STRADDLE), - .CQ_STRADDLE(CQ_STRADDLE), - .CC_STRADDLE(CC_STRADDLE), - .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), - .PF_COUNT(PF_COUNT), - .VF_COUNT(VF_COUNT), - .PCIE_TAG_COUNT(PCIE_TAG_COUNT), - - // Interrupt configuration - .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), - - // AXI lite interface configuration (control) - .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - - // AXI lite interface configuration (application control) - .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), - .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), - - // Ethernet interface configuration - .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), - .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), - .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), - .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), - .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), - .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), - - // Statistics counter subsystem - .STAT_ENABLE(STAT_ENABLE), - .STAT_DMA_ENABLE(STAT_DMA_ENABLE), - .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), - .STAT_INC_WIDTH(STAT_INC_WIDTH), - .STAT_ID_WIDTH(STAT_ID_WIDTH) -) -core_inst ( - /* - * Clock: 250 MHz - * Synchronous reset - */ - .clk_250mhz(pcie_user_clk), - .rst_250mhz(pcie_user_reset), - - /* - * PTP clock - */ - .ptp_clk(ptp_clk), - .ptp_rst(ptp_rst), - .ptp_sample_clk(ptp_sample_clk), - - /* - * GPIO - */ - .sw(sw_int), - .led(led_int), - - /* - * I2C - */ - .i2c_scl_i(i2c_scl_i), - .i2c_scl_o(i2c_scl_o), - .i2c_scl_t(i2c_scl_t), - .i2c_sda_i(i2c_sda_i), - .i2c_sda_o(i2c_sda_o), - .i2c_sda_t(i2c_sda_t), - - /* - * PCIe - */ - .m_axis_rq_tdata(axis_rq_tdata), - .m_axis_rq_tkeep(axis_rq_tkeep), - .m_axis_rq_tlast(axis_rq_tlast), - .m_axis_rq_tready(axis_rq_tready), - .m_axis_rq_tuser(axis_rq_tuser), - .m_axis_rq_tvalid(axis_rq_tvalid), - - .s_axis_rc_tdata(axis_rc_tdata), - .s_axis_rc_tkeep(axis_rc_tkeep), - .s_axis_rc_tlast(axis_rc_tlast), - .s_axis_rc_tready(axis_rc_tready), - .s_axis_rc_tuser(axis_rc_tuser), - .s_axis_rc_tvalid(axis_rc_tvalid), - - .s_axis_cq_tdata(axis_cq_tdata), - .s_axis_cq_tkeep(axis_cq_tkeep), - .s_axis_cq_tlast(axis_cq_tlast), - .s_axis_cq_tready(axis_cq_tready), - .s_axis_cq_tuser(axis_cq_tuser), - .s_axis_cq_tvalid(axis_cq_tvalid), - - .m_axis_cc_tdata(axis_cc_tdata), - .m_axis_cc_tkeep(axis_cc_tkeep), - .m_axis_cc_tlast(axis_cc_tlast), - .m_axis_cc_tready(axis_cc_tready), - .m_axis_cc_tuser(axis_cc_tuser), - .m_axis_cc_tvalid(axis_cc_tvalid), - - .s_axis_rq_seq_num_0(pcie_rq_seq_num0), - .s_axis_rq_seq_num_valid_0(pcie_rq_seq_num_vld0), - .s_axis_rq_seq_num_1(pcie_rq_seq_num1), - .s_axis_rq_seq_num_valid_1(pcie_rq_seq_num_vld1), - - .pcie_tfc_nph_av(pcie_tfc_nph_av), - .pcie_tfc_npd_av(pcie_tfc_npd_av), - - .cfg_max_payload(cfg_max_payload), - .cfg_max_read_req(cfg_max_read_req), - .cfg_rcb_status(cfg_rcb_status), - - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), - .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), - .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), - .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), - .cfg_interrupt_msix_address(cfg_interrupt_msix_address), - .cfg_interrupt_msix_data(cfg_interrupt_msix_data), - .cfg_interrupt_msix_int(cfg_interrupt_msix_int), - .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), - .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), - .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), - .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - .status_error_cor(status_error_cor), - .status_error_uncor(status_error_uncor), - - /* - * Ethernet: QSFP28 - */ - .qsfp0_tx_clk(qsfp0_tx_clk_int), - .qsfp0_tx_rst(qsfp0_tx_rst_int), - .qsfp0_tx_axis_tdata(qsfp0_tx_axis_tdata_int), - .qsfp0_tx_axis_tkeep(qsfp0_tx_axis_tkeep_int), - .qsfp0_tx_axis_tvalid(qsfp0_tx_axis_tvalid_int), - .qsfp0_tx_axis_tready(qsfp0_tx_axis_tready_int), - .qsfp0_tx_axis_tlast(qsfp0_tx_axis_tlast_int), - .qsfp0_tx_axis_tuser(qsfp0_tx_axis_tuser_int), - .qsfp0_tx_ptp_time(qsfp0_tx_ptp_time_int), - .qsfp0_tx_ptp_ts(qsfp0_tx_ptp_ts_int), - .qsfp0_tx_ptp_ts_tag(qsfp0_tx_ptp_ts_tag_int), - .qsfp0_tx_ptp_ts_valid(qsfp0_tx_ptp_ts_valid_int), - - .qsfp0_tx_enable(qsfp0_tx_enable), - .qsfp0_tx_lfc_en(qsfp0_tx_lfc_en), - .qsfp0_tx_lfc_req(qsfp0_tx_lfc_req), - .qsfp0_tx_pfc_en(qsfp0_tx_pfc_en), - .qsfp0_tx_pfc_req(qsfp0_tx_pfc_req), - - .qsfp0_rx_clk(qsfp0_rx_clk_int), - .qsfp0_rx_rst(qsfp0_rx_rst_int), - .qsfp0_rx_axis_tdata(qsfp0_rx_axis_tdata_int), - .qsfp0_rx_axis_tkeep(qsfp0_rx_axis_tkeep_int), - .qsfp0_rx_axis_tvalid(qsfp0_rx_axis_tvalid_int), - .qsfp0_rx_axis_tlast(qsfp0_rx_axis_tlast_int), - .qsfp0_rx_axis_tuser(qsfp0_rx_axis_tuser_int), - .qsfp0_rx_ptp_clk(qsfp0_rx_ptp_clk_int), - .qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int), - .qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int), - - .qsfp0_rx_enable(qsfp0_rx_enable), - .qsfp0_rx_status(qsfp0_rx_status), - .qsfp0_rx_lfc_en(qsfp0_rx_lfc_en), - .qsfp0_rx_lfc_req(qsfp0_rx_lfc_req), - .qsfp0_rx_lfc_ack(qsfp0_rx_lfc_ack), - .qsfp0_rx_pfc_en(qsfp0_rx_pfc_en), - .qsfp0_rx_pfc_req(qsfp0_rx_pfc_req), - .qsfp0_rx_pfc_ack(qsfp0_rx_pfc_ack), - - .qsfp0_drp_clk(qsfp0_drp_clk), - .qsfp0_drp_rst(qsfp0_drp_rst), - .qsfp0_drp_addr(qsfp0_drp_addr), - .qsfp0_drp_di(qsfp0_drp_di), - .qsfp0_drp_en(qsfp0_drp_en), - .qsfp0_drp_we(qsfp0_drp_we), - .qsfp0_drp_do(qsfp0_drp_do), - .qsfp0_drp_rdy(qsfp0_drp_rdy), - - .qsfp0_modprsl(qsfp0_modprsl_int), - .qsfp0_modsell(qsfp0_modsell), - .qsfp0_resetl(qsfp0_resetl), - .qsfp0_intl(qsfp0_intl_int), - .qsfp0_lpmode(qsfp0_lpmode), - - .qsfp1_tx_clk(qsfp1_tx_clk_int), - .qsfp1_tx_rst(qsfp1_tx_rst_int), - .qsfp1_tx_axis_tdata(qsfp1_tx_axis_tdata_int), - .qsfp1_tx_axis_tkeep(qsfp1_tx_axis_tkeep_int), - .qsfp1_tx_axis_tvalid(qsfp1_tx_axis_tvalid_int), - .qsfp1_tx_axis_tready(qsfp1_tx_axis_tready_int), - .qsfp1_tx_axis_tlast(qsfp1_tx_axis_tlast_int), - .qsfp1_tx_axis_tuser(qsfp1_tx_axis_tuser_int), - .qsfp1_tx_ptp_time(qsfp1_tx_ptp_time_int), - .qsfp1_tx_ptp_ts(qsfp1_tx_ptp_ts_int), - .qsfp1_tx_ptp_ts_tag(qsfp1_tx_ptp_ts_tag_int), - .qsfp1_tx_ptp_ts_valid(qsfp1_tx_ptp_ts_valid_int), - - .qsfp1_tx_enable(qsfp1_tx_enable), - .qsfp1_tx_lfc_en(qsfp1_tx_lfc_en), - .qsfp1_tx_lfc_req(qsfp1_tx_lfc_req), - .qsfp1_tx_pfc_en(qsfp1_tx_pfc_en), - .qsfp1_tx_pfc_req(qsfp1_tx_pfc_req), - - .qsfp1_rx_clk(qsfp1_rx_clk_int), - .qsfp1_rx_rst(qsfp1_rx_rst_int), - .qsfp1_rx_axis_tdata(qsfp1_rx_axis_tdata_int), - .qsfp1_rx_axis_tkeep(qsfp1_rx_axis_tkeep_int), - .qsfp1_rx_axis_tvalid(qsfp1_rx_axis_tvalid_int), - .qsfp1_rx_axis_tlast(qsfp1_rx_axis_tlast_int), - .qsfp1_rx_axis_tuser(qsfp1_rx_axis_tuser_int), - .qsfp1_rx_ptp_clk(qsfp1_rx_ptp_clk_int), - .qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int), - .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int), - - .qsfp1_rx_enable(qsfp1_rx_enable), - .qsfp1_rx_status(qsfp1_rx_status), - .qsfp1_rx_lfc_en(qsfp1_rx_lfc_en), - .qsfp1_rx_lfc_req(qsfp1_rx_lfc_req), - .qsfp1_rx_lfc_ack(qsfp1_rx_lfc_ack), - .qsfp1_rx_pfc_en(qsfp1_rx_pfc_en), - .qsfp1_rx_pfc_req(qsfp1_rx_pfc_req), - .qsfp1_rx_pfc_ack(qsfp1_rx_pfc_ack), - - .qsfp1_drp_clk(qsfp1_drp_clk), - .qsfp1_drp_rst(qsfp1_drp_rst), - .qsfp1_drp_addr(qsfp1_drp_addr), - .qsfp1_drp_di(qsfp1_drp_di), - .qsfp1_drp_en(qsfp1_drp_en), - .qsfp1_drp_we(qsfp1_drp_we), - .qsfp1_drp_do(qsfp1_drp_do), - .qsfp1_drp_rdy(qsfp1_drp_rdy), - - .qsfp1_modprsl(qsfp1_modprsl_int), - .qsfp1_modsell(qsfp1_modsell), - .qsfp1_resetl(qsfp1_resetl), - .qsfp1_intl(qsfp1_intl_int), - .qsfp1_lpmode(qsfp1_lpmode), - - /* - * DDR - */ - .ddr_clk(ddr_clk), - .ddr_rst(ddr_rst), - - .m_axi_ddr_awid(m_axi_ddr_awid), - .m_axi_ddr_awaddr(m_axi_ddr_awaddr), - .m_axi_ddr_awlen(m_axi_ddr_awlen), - .m_axi_ddr_awsize(m_axi_ddr_awsize), - .m_axi_ddr_awburst(m_axi_ddr_awburst), - .m_axi_ddr_awlock(m_axi_ddr_awlock), - .m_axi_ddr_awcache(m_axi_ddr_awcache), - .m_axi_ddr_awprot(m_axi_ddr_awprot), - .m_axi_ddr_awqos(m_axi_ddr_awqos), - .m_axi_ddr_awvalid(m_axi_ddr_awvalid), - .m_axi_ddr_awready(m_axi_ddr_awready), - .m_axi_ddr_wdata(m_axi_ddr_wdata), - .m_axi_ddr_wstrb(m_axi_ddr_wstrb), - .m_axi_ddr_wlast(m_axi_ddr_wlast), - .m_axi_ddr_wvalid(m_axi_ddr_wvalid), - .m_axi_ddr_wready(m_axi_ddr_wready), - .m_axi_ddr_bid(m_axi_ddr_bid), - .m_axi_ddr_bresp(m_axi_ddr_bresp), - .m_axi_ddr_bvalid(m_axi_ddr_bvalid), - .m_axi_ddr_bready(m_axi_ddr_bready), - .m_axi_ddr_arid(m_axi_ddr_arid), - .m_axi_ddr_araddr(m_axi_ddr_araddr), - .m_axi_ddr_arlen(m_axi_ddr_arlen), - .m_axi_ddr_arsize(m_axi_ddr_arsize), - .m_axi_ddr_arburst(m_axi_ddr_arburst), - .m_axi_ddr_arlock(m_axi_ddr_arlock), - .m_axi_ddr_arcache(m_axi_ddr_arcache), - .m_axi_ddr_arprot(m_axi_ddr_arprot), - .m_axi_ddr_arqos(m_axi_ddr_arqos), - .m_axi_ddr_arvalid(m_axi_ddr_arvalid), - .m_axi_ddr_arready(m_axi_ddr_arready), - .m_axi_ddr_rid(m_axi_ddr_rid), - .m_axi_ddr_rdata(m_axi_ddr_rdata), - .m_axi_ddr_rresp(m_axi_ddr_rresp), - .m_axi_ddr_rlast(m_axi_ddr_rlast), - .m_axi_ddr_rvalid(m_axi_ddr_rvalid), - .m_axi_ddr_rready(m_axi_ddr_rready), - - .ddr_status(ddr_status), - - /* - * QSPI flash - */ - .fpga_boot(fpga_boot), - .qspi_clk(qspi_clk_int), - .qspi_dq_i(qspi_dq_i_int), - .qspi_dq_o(qspi_dq_o_int), - .qspi_dq_oe(qspi_dq_oe_int), - .qspi_cs(qspi_cs_int), - - /* - * AXI-Lite interface to CMS - */ - .m_axil_cms_clk(axil_cms_clk), - .m_axil_cms_rst(axil_cms_rst), - .m_axil_cms_awaddr(axil_cms_awaddr), - .m_axil_cms_awprot(axil_cms_awprot), - .m_axil_cms_awvalid(axil_cms_awvalid), - .m_axil_cms_awready(axil_cms_awready), - .m_axil_cms_wdata(axil_cms_wdata), - .m_axil_cms_wstrb(axil_cms_wstrb), - .m_axil_cms_wvalid(axil_cms_wvalid), - .m_axil_cms_wready(axil_cms_wready), - .m_axil_cms_bresp(axil_cms_bresp), - .m_axil_cms_bvalid(axil_cms_bvalid), - .m_axil_cms_bready(axil_cms_bready), - .m_axil_cms_araddr(axil_cms_araddr), - .m_axil_cms_arprot(axil_cms_arprot), - .m_axil_cms_arvalid(axil_cms_arvalid), - .m_axil_cms_arready(axil_cms_arready), - .m_axil_cms_rdata(axil_cms_rdata), - .m_axil_cms_rresp(axil_cms_rresp), - .m_axil_cms_rvalid(axil_cms_rvalid), - .m_axil_cms_rready(axil_cms_rready) -); - -endmodule - -`resetall diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v deleted file mode 100644 index ff0930b2a..000000000 --- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v +++ /dev/null @@ -1,1541 +0,0 @@ -// SPDX-License-Identifier: BSD-2-Clause-Views -/* - * Copyright (c) 2019-2023 The Regents of the University of California - */ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA core logic - */ -module fpga_core # -( - // FW and board IDs - parameter FPGA_ID = 32'h4B57093, - parameter FW_ID = 32'h00000000, - parameter FW_VER = 32'h00_00_01_00, - parameter BOARD_ID = 32'h10ee_90fa, - parameter BOARD_VER = 32'h01_00_00_00, - parameter BUILD_DATE = 32'd602976000, - parameter GIT_HASH = 32'hdce357bf, - parameter RELEASE_INFO = 32'h00000000, - - // Structural configuration - parameter IF_COUNT = 2, - parameter PORTS_PER_IF = 1, - parameter SCHED_PER_IF = PORTS_PER_IF, - parameter PORT_MASK = 0, - - // Clock configuration - parameter CLK_PERIOD_NS_NUM = 4, - parameter CLK_PERIOD_NS_DENOM = 1, - - // PTP configuration - parameter PTP_CLK_PERIOD_NS_NUM = 1024, - parameter PTP_CLK_PERIOD_NS_DENOM = 165, - parameter PTP_TS_WIDTH = 96, - parameter PTP_CLOCK_PIPELINE = 0, - parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_SEPARATE_RX_CLOCK = 0, - parameter PTP_PORT_CDC_PIPELINE = 0, - parameter PTP_PEROUT_ENABLE = 0, - parameter PTP_PEROUT_COUNT = 1, - - // Queue manager configuration - parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_QUEUE_OP_TABLE_SIZE = 32, - parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter CQ_OP_TABLE_SIZE = 32, - parameter EQN_WIDTH = 5, - parameter TX_QUEUE_INDEX_WIDTH = 13, - parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, - parameter EQ_PIPELINE = 3, - parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), - parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), - - // TX and RX engine configuration - parameter TX_DESC_TABLE_SIZE = 32, - parameter RX_DESC_TABLE_SIZE = 32, - parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, - - // Scheduler configuration - parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, - parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, - parameter TDMA_INDEX_WIDTH = 6, - - // Interface configuration - parameter PTP_TS_ENABLE = 1, - parameter TX_CPL_FIFO_DEPTH = 32, - parameter TX_TAG_WIDTH = 16, - parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_HASH_ENABLE = 1, - parameter RX_CHECKSUM_ENABLE = 1, - parameter PFC_ENABLE = 1, - parameter LFC_ENABLE = PFC_ENABLE, - parameter TX_FIFO_DEPTH = 32768, - parameter RX_FIFO_DEPTH = 131072, - parameter MAX_TX_SIZE = 9214, - parameter MAX_RX_SIZE = 9214, - parameter TX_RAM_SIZE = 131072, - parameter RX_RAM_SIZE = 131072, - - // RAM configuration - parameter DDR_CH = 4, - parameter DDR_ENABLE = 0, - parameter AXI_DDR_DATA_WIDTH = 512, - parameter AXI_DDR_ADDR_WIDTH = 34, - parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), - parameter AXI_DDR_ID_WIDTH = 8, - parameter AXI_DDR_MAX_BURST_LEN = 256, - parameter AXI_DDR_NARROW_BURST = 0, - - // Application block configuration - parameter APP_ID = 32'h00000000, - parameter APP_ENABLE = 0, - parameter APP_CTRL_ENABLE = 1, - parameter APP_DMA_ENABLE = 1, - parameter APP_AXIS_DIRECT_ENABLE = 1, - parameter APP_AXIS_SYNC_ENABLE = 1, - parameter APP_AXIS_IF_ENABLE = 1, - parameter APP_STAT_ENABLE = 1, - - // DMA interface configuration - parameter DMA_IMM_ENABLE = 0, - parameter DMA_IMM_WIDTH = 32, - parameter DMA_LEN_WIDTH = 16, - parameter DMA_TAG_WIDTH = 16, - parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), - parameter RAM_PIPELINE = 2, - - // PCIe interface configuration - parameter AXIS_PCIE_DATA_WIDTH = 512, - parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), - parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161, - parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137, - parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183, - parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81, - parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256, - parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6, - parameter PF_COUNT = 1, - parameter VF_COUNT = 0, - parameter PCIE_TAG_COUNT = 256, - - // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EQN_WIDTH, - - // AXI lite interface configuration (control) - parameter AXIL_CTRL_DATA_WIDTH = 32, - parameter AXIL_CTRL_ADDR_WIDTH = 24, - - // AXI lite interface configuration (application control) - parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, - parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, - - // Ethernet interface configuration - parameter AXIS_ETH_DATA_WIDTH = 512, - parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, - parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH, - parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1, - parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, - parameter AXIS_ETH_TX_PIPELINE = 4, - parameter AXIS_ETH_TX_FIFO_PIPELINE = 4, - parameter AXIS_ETH_TX_TS_PIPELINE = 4, - parameter AXIS_ETH_RX_PIPELINE = 4, - parameter AXIS_ETH_RX_FIFO_PIPELINE = 4, - - // Statistics counter subsystem - parameter STAT_ENABLE = 1, - parameter STAT_DMA_ENABLE = 1, - parameter STAT_PCIE_ENABLE = 1, - parameter STAT_INC_WIDTH = 24, - parameter STAT_ID_WIDTH = 12 -) -( - /* - * Clock: 250 MHz - * Synchronous reset - */ - input wire clk_250mhz, - input wire rst_250mhz, - - /* - * PTP clock - */ - input wire ptp_clk, - input wire ptp_rst, - input wire ptp_sample_clk, - - /* - * GPIO - */ - input wire [3:0] sw, - output wire [2:0] led, - - /* - * I2C - */ - input wire i2c_scl_i, - output wire i2c_scl_o, - output wire i2c_scl_t, - input wire i2c_sda_i, - output wire i2c_sda_o, - output wire i2c_sda_t, - - /* - * PCIe - */ - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, - output wire m_axis_rq_tlast, - input wire m_axis_rq_tready, - output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser, - output wire m_axis_rq_tvalid, - - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, - input wire s_axis_rc_tlast, - output wire s_axis_rc_tready, - input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser, - input wire s_axis_rc_tvalid, - - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, - input wire s_axis_cq_tlast, - output wire s_axis_cq_tready, - input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser, - input wire s_axis_cq_tvalid, - - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, - output wire m_axis_cc_tlast, - input wire m_axis_cc_tready, - output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser, - output wire m_axis_cc_tvalid, - - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0, - input wire s_axis_rq_seq_num_valid_0, - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1, - input wire s_axis_rq_seq_num_valid_1, - - input wire [1:0] pcie_tfc_nph_av, - input wire [1:0] pcie_tfc_npd_av, - - input wire [2:0] cfg_max_payload, - input wire [2:0] cfg_max_read_req, - input wire [3:0] cfg_rcb_status, - - output wire [9:0] cfg_mgmt_addr, - output wire [7:0] cfg_mgmt_function_number, - output wire cfg_mgmt_write, - output wire [31:0] cfg_mgmt_write_data, - output wire [3:0] cfg_mgmt_byte_enable, - output wire cfg_mgmt_read, - input wire [31:0] cfg_mgmt_read_data, - input wire cfg_mgmt_read_write_done, - - input wire [7:0] cfg_fc_ph, - input wire [11:0] cfg_fc_pd, - input wire [7:0] cfg_fc_nph, - input wire [11:0] cfg_fc_npd, - input wire [7:0] cfg_fc_cplh, - input wire [11:0] cfg_fc_cpld, - output wire [2:0] cfg_fc_sel, - - input wire [3:0] cfg_interrupt_msix_enable, - input wire [3:0] cfg_interrupt_msix_mask, - input wire [251:0] cfg_interrupt_msix_vf_enable, - input wire [251:0] cfg_interrupt_msix_vf_mask, - output wire [63:0] cfg_interrupt_msix_address, - output wire [31:0] cfg_interrupt_msix_data, - output wire cfg_interrupt_msix_int, - output wire [1:0] cfg_interrupt_msix_vec_pending, - input wire cfg_interrupt_msix_vec_pending_status, - input wire cfg_interrupt_msix_sent, - input wire cfg_interrupt_msix_fail, - output wire [7:0] cfg_interrupt_msi_function_number, - - output wire status_error_cor, - output wire status_error_uncor, - - /* - * Ethernet: QSFP28 - */ - input wire qsfp0_tx_clk, - input wire qsfp0_tx_rst, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_tx_axis_tkeep, - output wire qsfp0_tx_axis_tvalid, - input wire qsfp0_tx_axis_tready, - output wire qsfp0_tx_axis_tlast, - output wire [16+1-1:0] qsfp0_tx_axis_tuser, - - output wire [79:0] qsfp0_tx_ptp_time, - input wire [79:0] qsfp0_tx_ptp_ts, - input wire [15:0] qsfp0_tx_ptp_ts_tag, - input wire qsfp0_tx_ptp_ts_valid, - - output wire qsfp0_tx_enable, - output wire qsfp0_tx_lfc_en, - output wire qsfp0_tx_lfc_req, - output wire [7:0] qsfp0_tx_pfc_en, - output wire [7:0] qsfp0_tx_pfc_req, - - input wire qsfp0_rx_clk, - input wire qsfp0_rx_rst, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_rx_axis_tkeep, - input wire qsfp0_rx_axis_tvalid, - input wire qsfp0_rx_axis_tlast, - input wire [80+1-1:0] qsfp0_rx_axis_tuser, - - input wire qsfp0_rx_ptp_clk, - input wire qsfp0_rx_ptp_rst, - output wire [79:0] qsfp0_rx_ptp_time, - - output wire qsfp0_rx_enable, - input wire qsfp0_rx_status, - output wire qsfp0_rx_lfc_en, - input wire qsfp0_rx_lfc_req, - output wire qsfp0_rx_lfc_ack, - output wire [7:0] qsfp0_rx_pfc_en, - input wire [7:0] qsfp0_rx_pfc_req, - output wire [7:0] qsfp0_rx_pfc_ack, - - input wire qsfp0_drp_clk, - input wire qsfp0_drp_rst, - output wire [23:0] qsfp0_drp_addr, - output wire [15:0] qsfp0_drp_di, - output wire qsfp0_drp_en, - output wire qsfp0_drp_we, - input wire [15:0] qsfp0_drp_do, - input wire qsfp0_drp_rdy, - - output wire qsfp0_modsell, - output wire qsfp0_resetl, - input wire qsfp0_modprsl, - input wire qsfp0_intl, - output wire qsfp0_lpmode, - - input wire qsfp1_tx_clk, - input wire qsfp1_tx_rst, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_tx_axis_tkeep, - output wire qsfp1_tx_axis_tvalid, - input wire qsfp1_tx_axis_tready, - output wire qsfp1_tx_axis_tlast, - output wire [16+1-1:0] qsfp1_tx_axis_tuser, - - output wire [79:0] qsfp1_tx_ptp_time, - input wire [79:0] qsfp1_tx_ptp_ts, - input wire [15:0] qsfp1_tx_ptp_ts_tag, - input wire qsfp1_tx_ptp_ts_valid, - - output wire qsfp1_tx_enable, - output wire qsfp1_tx_lfc_en, - output wire qsfp1_tx_lfc_req, - output wire [7:0] qsfp1_tx_pfc_en, - output wire [7:0] qsfp1_tx_pfc_req, - - input wire qsfp1_rx_clk, - input wire qsfp1_rx_rst, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_rx_axis_tkeep, - input wire qsfp1_rx_axis_tvalid, - input wire qsfp1_rx_axis_tlast, - input wire [80+1-1:0] qsfp1_rx_axis_tuser, - - input wire qsfp1_rx_ptp_clk, - input wire qsfp1_rx_ptp_rst, - output wire [79:0] qsfp1_rx_ptp_time, - - output wire qsfp1_rx_enable, - input wire qsfp1_rx_status, - output wire qsfp1_rx_lfc_en, - input wire qsfp1_rx_lfc_req, - output wire qsfp1_rx_lfc_ack, - output wire [7:0] qsfp1_rx_pfc_en, - input wire [7:0] qsfp1_rx_pfc_req, - output wire [7:0] qsfp1_rx_pfc_ack, - - input wire qsfp1_drp_clk, - input wire qsfp1_drp_rst, - output wire [23:0] qsfp1_drp_addr, - output wire [15:0] qsfp1_drp_di, - output wire qsfp1_drp_en, - output wire qsfp1_drp_we, - input wire [15:0] qsfp1_drp_do, - input wire qsfp1_drp_rdy, - - output wire qsfp1_modsell, - output wire qsfp1_resetl, - input wire qsfp1_modprsl, - input wire qsfp1_intl, - output wire qsfp1_lpmode, - - /* - * DDR - */ - input wire [DDR_CH-1:0] ddr_clk, - input wire [DDR_CH-1:0] ddr_rst, - - output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, - output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, - output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, - output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, - output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, - output wire [DDR_CH-1:0] m_axi_ddr_awlock, - output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, - output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, - output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, - output wire [DDR_CH-1:0] m_axi_ddr_awvalid, - input wire [DDR_CH-1:0] m_axi_ddr_awready, - output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, - output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, - output wire [DDR_CH-1:0] m_axi_ddr_wlast, - output wire [DDR_CH-1:0] m_axi_ddr_wvalid, - input wire [DDR_CH-1:0] m_axi_ddr_wready, - input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, - input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, - input wire [DDR_CH-1:0] m_axi_ddr_bvalid, - output wire [DDR_CH-1:0] m_axi_ddr_bready, - output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, - output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, - output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, - output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, - output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, - output wire [DDR_CH-1:0] m_axi_ddr_arlock, - output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, - output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, - output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, - output wire [DDR_CH-1:0] m_axi_ddr_arvalid, - input wire [DDR_CH-1:0] m_axi_ddr_arready, - input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, - input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, - input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, - input wire [DDR_CH-1:0] m_axi_ddr_rlast, - input wire [DDR_CH-1:0] m_axi_ddr_rvalid, - output wire [DDR_CH-1:0] m_axi_ddr_rready, - - input wire [DDR_CH-1:0] ddr_status, - - /* - * QSPI flash - */ - output wire fpga_boot, - output wire qspi_clk, - input wire [3:0] qspi_dq_i, - output wire [3:0] qspi_dq_o, - output wire [3:0] qspi_dq_oe, - output wire qspi_cs, - - /* - * AXI-Lite interface to CMS - */ - output wire m_axil_cms_clk, - output wire m_axil_cms_rst, - output wire [17:0] m_axil_cms_awaddr, - output wire [2:0] m_axil_cms_awprot, - output wire m_axil_cms_awvalid, - input wire m_axil_cms_awready, - output wire [31:0] m_axil_cms_wdata, - output wire [3:0] m_axil_cms_wstrb, - output wire m_axil_cms_wvalid, - input wire m_axil_cms_wready, - input wire [1:0] m_axil_cms_bresp, - input wire m_axil_cms_bvalid, - output wire m_axil_cms_bready, - output wire [17:0] m_axil_cms_araddr, - output wire [2:0] m_axil_cms_arprot, - output wire m_axil_cms_arvalid, - input wire m_axil_cms_arready, - input wire [31:0] m_axil_cms_rdata, - input wire [1:0] m_axil_cms_rresp, - input wire m_axil_cms_rvalid, - output wire m_axil_cms_rready -); - -parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; - -parameter F_COUNT = PF_COUNT+VF_COUNT; - -parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8); -parameter AXIL_IF_CTRL_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT); -parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8); - -localparam RB_BASE_ADDR = 16'h1000; -localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; - -localparam RB_DRP_QSFP0_BASE = RB_BASE_ADDR + 16'h60; -localparam RB_DRP_QSFP1_BASE = RB_DRP_QSFP0_BASE + 16'h20; - -initial begin - if (PORT_COUNT > 2) begin - $error("Error: Max port count exceeded (instance %m)"); - $finish; - end -end - -// PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; - -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse; - -// control registers -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_wr_addr; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_wr_data; -wire [AXIL_CTRL_STRB_WIDTH-1:0] ctrl_reg_wr_strb; -wire ctrl_reg_wr_en; -wire ctrl_reg_wr_wait; -wire ctrl_reg_wr_ack; -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_rd_addr; -wire ctrl_reg_rd_en; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data; -wire ctrl_reg_rd_wait; -wire ctrl_reg_rd_ack; - -wire qsfp0_drp_reg_wr_wait; -wire qsfp0_drp_reg_wr_ack; -wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp0_drp_reg_rd_data; -wire qsfp0_drp_reg_rd_wait; -wire qsfp0_drp_reg_rd_ack; - -wire qsfp1_drp_reg_wr_wait; -wire qsfp1_drp_reg_wr_ack; -wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp1_drp_reg_rd_data; -wire qsfp1_drp_reg_rd_wait; -wire qsfp1_drp_reg_rd_ack; - -reg ctrl_reg_wr_ack_reg = 1'b0; -reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; -reg ctrl_reg_rd_ack_reg = 1'b0; - -reg qsfp0_reset_reg = 1'b0; -reg qsfp1_reset_reg = 1'b0; - -reg qsfp0_lpmode_reg = 1'b0; -reg qsfp1_lpmode_reg = 1'b0; - -reg i2c_scl_o_reg = 1'b1; -reg i2c_sda_o_reg = 1'b1; - -reg fpga_boot_reg = 1'b0; - -reg qspi_clk_reg = 1'b0; -reg qspi_cs_reg = 1'b1; -reg [3:0] qspi_dq_o_reg = 4'd0; -reg [3:0] qspi_dq_oe_reg = 4'd0; - -reg [17:0] m_axil_cms_addr_reg = 18'd0; -reg m_axil_cms_awvalid_reg = 1'b0; -reg [31:0] m_axil_cms_wdata_reg = 32'd0; -reg [3:0] m_axil_cms_wstrb_reg = 4'b0000; -reg m_axil_cms_wvalid_reg = 1'b0; -reg m_axil_cms_arvalid_reg = 1'b0; - -assign ctrl_reg_wr_wait = qsfp0_drp_reg_wr_wait | qsfp1_drp_reg_wr_wait; -assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp0_drp_reg_wr_ack | qsfp1_drp_reg_wr_ack; -assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp0_drp_reg_rd_data | qsfp1_drp_reg_rd_data; -assign ctrl_reg_rd_wait = qsfp0_drp_reg_rd_wait | qsfp1_drp_reg_rd_wait; -assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp0_drp_reg_rd_ack | qsfp1_drp_reg_rd_ack; - -assign qsfp0_modsell = 1'b0; -assign qsfp1_modsell = 1'b0; - -assign qsfp0_resetl = !qsfp0_reset_reg; -assign qsfp1_resetl = !qsfp1_reset_reg; - -assign qsfp0_lpmode = qsfp0_lpmode_reg; -assign qsfp1_lpmode = qsfp1_lpmode_reg; - -assign i2c_scl_o = i2c_scl_o_reg; -assign i2c_scl_t = i2c_scl_o_reg; -assign i2c_sda_o = i2c_sda_o_reg; -assign i2c_sda_t = i2c_sda_o_reg; - -assign fpga_boot = fpga_boot_reg; - -assign qspi_clk = qspi_clk_reg; -assign qspi_cs = qspi_cs_reg; -assign qspi_dq_o = qspi_dq_o_reg; -assign qspi_dq_oe = qspi_dq_oe_reg; - -assign m_axil_cms_clk = clk_250mhz; -assign m_axil_cms_rst = rst_250mhz; -assign m_axil_cms_awaddr = m_axil_cms_addr_reg; -assign m_axil_cms_awprot = 3'b000; -assign m_axil_cms_awvalid = m_axil_cms_awvalid_reg; -assign m_axil_cms_wdata = m_axil_cms_wdata_reg; -assign m_axil_cms_wstrb = m_axil_cms_wstrb_reg; -assign m_axil_cms_wvalid = m_axil_cms_wvalid_reg; -assign m_axil_cms_bready = 1'b1; -assign m_axil_cms_araddr = m_axil_cms_addr_reg; -assign m_axil_cms_arprot = 3'b000; -assign m_axil_cms_arvalid = m_axil_cms_arvalid_reg; -assign m_axil_cms_rready = 1'b1; - -always @(posedge clk_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; - ctrl_reg_rd_ack_reg <= 1'b0; - - m_axil_cms_awvalid_reg <= m_axil_cms_awvalid_reg && !m_axil_cms_awready; - m_axil_cms_wvalid_reg <= m_axil_cms_wvalid_reg && !m_axil_cms_wready; - m_axil_cms_arvalid_reg <= m_axil_cms_arvalid_reg && !m_axil_cms_arready; - - if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin - // write operation - ctrl_reg_wr_ack_reg <= 1'b0; - case ({ctrl_reg_wr_addr >> 2, 2'b00}) - // FW ID - 8'h0C: begin - // FW ID: FPGA JTAG ID - fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD; - end - // I2C 0 - RBB+8'h0C: begin - // I2C ctrl: control - if (ctrl_reg_wr_strb[0]) begin - i2c_scl_o_reg <= ctrl_reg_wr_data[1]; - end - if (ctrl_reg_wr_strb[1]) begin - i2c_sda_o_reg <= ctrl_reg_wr_data[9]; - end - end - // XCVR GPIO - RBB+8'h1C: begin - // XCVR GPIO: control 0123 - if (ctrl_reg_wr_strb[0]) begin - qsfp0_reset_reg <= ctrl_reg_wr_data[4]; - qsfp0_lpmode_reg <= ctrl_reg_wr_data[5]; - end - if (ctrl_reg_wr_strb[1]) begin - qsfp1_reset_reg <= ctrl_reg_wr_data[12]; - qsfp1_lpmode_reg <= ctrl_reg_wr_data[13]; - end - end - // QSPI flash - RBB+8'h2C: begin - // SPI flash ctrl: format - fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD; - end - RBB+8'h30: begin - // SPI flash ctrl: control 0 - if (ctrl_reg_wr_strb[0]) begin - qspi_dq_o_reg <= ctrl_reg_wr_data[3:0]; - end - if (ctrl_reg_wr_strb[1]) begin - qspi_dq_oe_reg <= ctrl_reg_wr_data[11:8]; - end - if (ctrl_reg_wr_strb[2]) begin - qspi_clk_reg <= ctrl_reg_wr_data[16]; - qspi_cs_reg <= ctrl_reg_wr_data[17]; - end - end - // Alveo BMC - RBB+8'h4C: begin - // BMC ctrl: Addr - if (!m_axil_cms_arvalid && !m_axil_cms_awvalid) begin - m_axil_cms_addr_reg <= ctrl_reg_wr_data; - m_axil_cms_arvalid_reg <= 1'b1; - end - end - RBB+8'h50: begin - // BMC ctrl: Data - if (!m_axil_cms_wvalid) begin - m_axil_cms_awvalid_reg <= 1'b1; - m_axil_cms_wdata_reg <= ctrl_reg_wr_data; - m_axil_cms_wstrb_reg <= ctrl_reg_wr_strb; - m_axil_cms_wvalid_reg <= 1'b1; - end - end - default: ctrl_reg_wr_ack_reg <= 1'b0; - endcase - end - - if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin - // read operation - ctrl_reg_rd_ack_reg <= 1'b1; - case ({ctrl_reg_rd_addr >> 2, 2'b00}) - // I2C 0 - RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type - RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version - RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // I2C ctrl: Next header - RBB+8'h0C: begin - // I2C ctrl: control - ctrl_reg_rd_data_reg[0] <= i2c_scl_i; - ctrl_reg_rd_data_reg[1] <= i2c_scl_o_reg; - ctrl_reg_rd_data_reg[8] <= i2c_sda_i; - ctrl_reg_rd_data_reg[9] <= i2c_sda_o_reg; - end - // XCVR GPIO - RBB+8'h10: ctrl_reg_rd_data_reg <= 32'h0000C101; // XCVR GPIO: Type - RBB+8'h14: ctrl_reg_rd_data_reg <= 32'h00000100; // XCVR GPIO: Version - RBB+8'h18: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // XCVR GPIO: Next header - RBB+8'h1C: begin - // XCVR GPIO: control 0123 - ctrl_reg_rd_data_reg[0] <= !qsfp0_modprsl; - ctrl_reg_rd_data_reg[1] <= !qsfp0_intl; - ctrl_reg_rd_data_reg[4] <= qsfp0_reset_reg; - ctrl_reg_rd_data_reg[5] <= qsfp0_lpmode_reg; - ctrl_reg_rd_data_reg[8] <= !qsfp1_modprsl; - ctrl_reg_rd_data_reg[9] <= !qsfp1_intl; - ctrl_reg_rd_data_reg[12] <= qsfp1_reset_reg; - ctrl_reg_rd_data_reg[13] <= qsfp1_lpmode_reg; - end - // QSPI flash - RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type - RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version - RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // SPI flash ctrl: Next header - RBB+8'h2C: begin - // SPI flash ctrl: format - ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments) - ctrl_reg_rd_data_reg[7:4] <= 1; // default segment - ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment - ctrl_reg_rd_data_reg[31:12] <= 32'h01002000 >> 12; // first segment size (Alveo default) - end - RBB+8'h30: begin - // SPI flash ctrl: control 0 - ctrl_reg_rd_data_reg[3:0] <= qspi_dq_i; - ctrl_reg_rd_data_reg[11:8] <= qspi_dq_oe; - ctrl_reg_rd_data_reg[16] <= qspi_clk; - ctrl_reg_rd_data_reg[17] <= qspi_cs; - end - // Alveo BMC - RBB+8'h40: ctrl_reg_rd_data_reg <= 32'h0000C140; // BMC ctrl: Type - RBB+8'h44: ctrl_reg_rd_data_reg <= 32'h00000100; // BMC ctrl: Version - RBB+8'h48: ctrl_reg_rd_data_reg <= RB_DRP_QSFP0_BASE; // BMC ctrl: Next header - RBB+8'h4C: ctrl_reg_rd_data_reg <= m_axil_cms_addr_reg; // BMC ctrl: Addr - RBB+8'h50: ctrl_reg_rd_data_reg <= m_axil_cms_rdata; // BMC ctrl: Data - default: ctrl_reg_rd_ack_reg <= 1'b0; - endcase - end - - if (rst_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_ack_reg <= 1'b0; - - qsfp0_reset_reg <= 1'b0; - qsfp1_reset_reg <= 1'b0; - - qsfp0_lpmode_reg <= 1'b0; - qsfp1_lpmode_reg <= 1'b0; - - i2c_scl_o_reg <= 1'b1; - i2c_sda_o_reg <= 1'b1; - - fpga_boot_reg <= 1'b0; - - qspi_clk_reg <= 1'b0; - qspi_cs_reg <= 1'b1; - qspi_dq_o_reg <= 4'd0; - qspi_dq_oe_reg <= 4'd0; - - m_axil_cms_awvalid_reg <= 1'b0; - m_axil_cms_wvalid_reg <= 1'b0; - m_axil_cms_arvalid_reg <= 1'b0; - end -end - -rb_drp #( - .DRP_ADDR_WIDTH(24), - .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h09, 8'h03, 8'd2, 8'd4}), - .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .RB_BASE_ADDR(RB_DRP_QSFP0_BASE), - .RB_NEXT_PTR(RB_DRP_QSFP1_BASE) -) -qsfp0_rb_drp_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * Register interface - */ - .reg_wr_addr(ctrl_reg_wr_addr), - .reg_wr_data(ctrl_reg_wr_data), - .reg_wr_strb(ctrl_reg_wr_strb), - .reg_wr_en(ctrl_reg_wr_en), - .reg_wr_wait(qsfp0_drp_reg_wr_wait), - .reg_wr_ack(qsfp0_drp_reg_wr_ack), - .reg_rd_addr(ctrl_reg_rd_addr), - .reg_rd_en(ctrl_reg_rd_en), - .reg_rd_data(qsfp0_drp_reg_rd_data), - .reg_rd_wait(qsfp0_drp_reg_rd_wait), - .reg_rd_ack(qsfp0_drp_reg_rd_ack), - - /* - * DRP - */ - .drp_clk(qsfp0_drp_clk), - .drp_rst(qsfp0_drp_rst), - .drp_addr(qsfp0_drp_addr), - .drp_di(qsfp0_drp_di), - .drp_en(qsfp0_drp_en), - .drp_we(qsfp0_drp_we), - .drp_do(qsfp0_drp_do), - .drp_rdy(qsfp0_drp_rdy) -); - -rb_drp #( - .DRP_ADDR_WIDTH(24), - .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h09, 8'h03, 8'd2, 8'd4}), - .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .RB_BASE_ADDR(RB_DRP_QSFP1_BASE), - .RB_NEXT_PTR(0) -) -qsfp1_rb_drp_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * Register interface - */ - .reg_wr_addr(ctrl_reg_wr_addr), - .reg_wr_data(ctrl_reg_wr_data), - .reg_wr_strb(ctrl_reg_wr_strb), - .reg_wr_en(ctrl_reg_wr_en), - .reg_wr_wait(qsfp1_drp_reg_wr_wait), - .reg_wr_ack(qsfp1_drp_reg_wr_ack), - .reg_rd_addr(ctrl_reg_rd_addr), - .reg_rd_en(ctrl_reg_rd_en), - .reg_rd_data(qsfp1_drp_reg_rd_data), - .reg_rd_wait(qsfp1_drp_reg_rd_wait), - .reg_rd_ack(qsfp1_drp_reg_rd_ack), - - /* - * DRP - */ - .drp_clk(qsfp1_drp_clk), - .drp_rst(qsfp1_drp_rst), - .drp_addr(qsfp1_drp_addr), - .drp_di(qsfp1_drp_di), - .drp_en(qsfp1_drp_en), - .drp_we(qsfp1_drp_we), - .drp_do(qsfp1_drp_do), - .drp_rdy(qsfp1_drp_rdy) -); - -assign led[0] = ptp_pps_str; -assign led[2:1] = 0; - -wire [PORT_COUNT-1:0] eth_tx_clk; -wire [PORT_COUNT-1:0] eth_tx_rst; - -wire [PORT_COUNT-1:0] eth_tx_ptp_clk; -wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_tx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_tx_tready; -wire [PORT_COUNT-1:0] axis_eth_tx_tlast; -wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts; -wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; - -wire [PORT_COUNT-1:0] eth_tx_enable; -wire [PORT_COUNT-1:0] eth_tx_status; -wire [PORT_COUNT-1:0] eth_tx_lfc_en; -wire [PORT_COUNT-1:0] eth_tx_lfc_req; -wire [PORT_COUNT*8-1:0] eth_tx_pfc_en; -wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; - -wire [PORT_COUNT-1:0] eth_rx_clk; -wire [PORT_COUNT-1:0] eth_rx_rst; - -wire [PORT_COUNT-1:0] eth_rx_ptp_clk; -wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_rx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_rx_tready; -wire [PORT_COUNT-1:0] axis_eth_rx_tlast; -wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; - -wire [PORT_COUNT-1:0] eth_rx_enable; -wire [PORT_COUNT-1:0] eth_rx_status; -wire [PORT_COUNT-1:0] eth_rx_lfc_en; -wire [PORT_COUNT-1:0] eth_rx_lfc_req; -wire [PORT_COUNT-1:0] eth_rx_lfc_ack; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_en; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_req; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack; - -wire [PTP_TS_WIDTH-1:0] qsfp0_tx_ptp_time_int; -wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int; -wire [PTP_TS_WIDTH-1:0] qsfp0_rx_ptp_time_int; -wire [PTP_TS_WIDTH-1:0] qsfp1_rx_ptp_time_int; - -assign qsfp0_tx_ptp_time = qsfp0_tx_ptp_time_int >> 16; -assign qsfp1_tx_ptp_time = qsfp1_tx_ptp_time_int >> 16; -assign qsfp0_rx_ptp_time = qsfp0_rx_ptp_time_int >> 16; -assign qsfp1_rx_ptp_time = qsfp1_rx_ptp_time_int >> 16; - -mqnic_port_map_mac_axis #( - .MAC_COUNT(2), - .PORT_MASK(PORT_MASK), - .PORT_GROUP_SIZE(1), - - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - - .PORT_COUNT(PORT_COUNT), - - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_TAG_WIDTH(TX_TAG_WIDTH), - .AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) -) -mqnic_port_map_mac_axis_inst ( - // towards MAC - .mac_tx_clk({qsfp1_tx_clk, qsfp0_tx_clk}), - .mac_tx_rst({qsfp1_tx_rst, qsfp0_tx_rst}), - - .mac_tx_ptp_clk(2'b00), - .mac_tx_ptp_rst(2'b00), - .mac_tx_ptp_ts_96({qsfp1_tx_ptp_time_int, qsfp0_tx_ptp_time_int}), - .mac_tx_ptp_ts_step(), - - .m_axis_mac_tx_tdata({qsfp1_tx_axis_tdata, qsfp0_tx_axis_tdata}), - .m_axis_mac_tx_tkeep({qsfp1_tx_axis_tkeep, qsfp0_tx_axis_tkeep}), - .m_axis_mac_tx_tvalid({qsfp1_tx_axis_tvalid, qsfp0_tx_axis_tvalid}), - .m_axis_mac_tx_tready({qsfp1_tx_axis_tready, qsfp0_tx_axis_tready}), - .m_axis_mac_tx_tlast({qsfp1_tx_axis_tlast, qsfp0_tx_axis_tlast}), - .m_axis_mac_tx_tuser({qsfp1_tx_axis_tuser, qsfp0_tx_axis_tuser}), - - .s_axis_mac_tx_ptp_ts({{qsfp1_tx_ptp_ts, 16'd0}, {qsfp0_tx_ptp_ts, 16'd0}}), - .s_axis_mac_tx_ptp_ts_tag({qsfp1_tx_ptp_ts_tag, qsfp0_tx_ptp_ts_tag}), - .s_axis_mac_tx_ptp_ts_valid({qsfp1_tx_ptp_ts_valid, qsfp0_tx_ptp_ts_valid}), - .s_axis_mac_tx_ptp_ts_ready(), - - .mac_tx_enable({qsfp1_tx_enable, qsfp0_tx_enable}), - .mac_tx_status(2'b11), - .mac_tx_lfc_en({qsfp1_tx_lfc_en, qsfp0_tx_lfc_en}), - .mac_tx_lfc_req({qsfp1_tx_lfc_req, qsfp0_tx_lfc_req}), - .mac_tx_pfc_en({qsfp1_tx_pfc_en, qsfp0_tx_pfc_en}), - .mac_tx_pfc_req({qsfp1_tx_pfc_req, qsfp0_tx_pfc_req}), - - .mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}), - .mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}), - - .mac_rx_ptp_clk({qsfp1_rx_ptp_clk, qsfp0_rx_ptp_clk}), - .mac_rx_ptp_rst({qsfp1_rx_ptp_rst, qsfp0_rx_ptp_rst}), - .mac_rx_ptp_ts_96({qsfp1_rx_ptp_time_int, qsfp0_rx_ptp_time_int}), - .mac_rx_ptp_ts_step(), - - .s_axis_mac_rx_tdata({qsfp1_rx_axis_tdata, qsfp0_rx_axis_tdata}), - .s_axis_mac_rx_tkeep({qsfp1_rx_axis_tkeep, qsfp0_rx_axis_tkeep}), - .s_axis_mac_rx_tvalid({qsfp1_rx_axis_tvalid, qsfp0_rx_axis_tvalid}), - .s_axis_mac_rx_tready(), - .s_axis_mac_rx_tlast({qsfp1_rx_axis_tlast, qsfp0_rx_axis_tlast}), - .s_axis_mac_rx_tuser({{qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}, {qsfp0_rx_axis_tuser[80:1], 16'd0, qsfp0_rx_axis_tuser[0]}}), - - .mac_rx_enable({qsfp1_rx_enable, qsfp0_rx_enable}), - .mac_rx_status({qsfp1_rx_status, qsfp0_rx_status}), - .mac_rx_lfc_en({qsfp1_rx_lfc_en, qsfp0_rx_lfc_en}), - .mac_rx_lfc_req({qsfp1_rx_lfc_req, qsfp0_rx_lfc_req}), - .mac_rx_lfc_ack({qsfp1_rx_lfc_ack, qsfp0_rx_lfc_ack}), - .mac_rx_pfc_en({qsfp1_rx_pfc_en, qsfp0_rx_pfc_en}), - .mac_rx_pfc_req({qsfp1_rx_pfc_req, qsfp0_rx_pfc_req}), - .mac_rx_pfc_ack({qsfp1_rx_pfc_ack, qsfp0_rx_pfc_ack}), - - // towards datapath - .tx_clk(eth_tx_clk), - .tx_rst(eth_tx_rst), - - .tx_ptp_clk(eth_tx_ptp_clk), - .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), - - .s_axis_tx_tdata(axis_eth_tx_tdata), - .s_axis_tx_tkeep(axis_eth_tx_tkeep), - .s_axis_tx_tvalid(axis_eth_tx_tvalid), - .s_axis_tx_tready(axis_eth_tx_tready), - .s_axis_tx_tlast(axis_eth_tx_tlast), - .s_axis_tx_tuser(axis_eth_tx_tuser), - - .m_axis_tx_ptp_ts(axis_eth_tx_ptp_ts), - .m_axis_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag), - .m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid), - .m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready), - - .tx_enable(eth_tx_enable), - .tx_status(eth_tx_status), - .tx_lfc_en(eth_tx_lfc_en), - .tx_lfc_req(eth_tx_lfc_req), - .tx_pfc_en(eth_tx_pfc_en), - .tx_pfc_req(eth_tx_pfc_req), - - .rx_clk(eth_rx_clk), - .rx_rst(eth_rx_rst), - - .rx_ptp_clk(eth_rx_ptp_clk), - .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), - - .m_axis_rx_tdata(axis_eth_rx_tdata), - .m_axis_rx_tkeep(axis_eth_rx_tkeep), - .m_axis_rx_tvalid(axis_eth_rx_tvalid), - .m_axis_rx_tready(axis_eth_rx_tready), - .m_axis_rx_tlast(axis_eth_rx_tlast), - .m_axis_rx_tuser(axis_eth_rx_tuser), - - .rx_enable(eth_rx_enable), - .rx_status(eth_rx_status), - .rx_lfc_en(eth_rx_lfc_en), - .rx_lfc_req(eth_rx_lfc_req), - .rx_lfc_ack(eth_rx_lfc_ack), - .rx_pfc_en(eth_rx_pfc_en), - .rx_pfc_req(eth_rx_pfc_req), - .rx_pfc_ack(eth_rx_pfc_ack) -); - -mqnic_core_pcie_us #( - // FW and board IDs - .FPGA_ID(FPGA_ID), - .FW_ID(FW_ID), - .FW_VER(FW_VER), - .BOARD_ID(BOARD_ID), - .BOARD_VER(BOARD_VER), - .BUILD_DATE(BUILD_DATE), - .GIT_HASH(GIT_HASH), - .RELEASE_INFO(RELEASE_INFO), - - // Structural configuration - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - .SCHED_PER_IF(SCHED_PER_IF), - - .PORT_COUNT(PORT_COUNT), - - // Clock configuration - .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), - .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), - - // PTP configuration - .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), - .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), - .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_TX_CLOCK(0), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), - .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), - - // Queue manager configuration - .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), - .EQN_WIDTH(EQN_WIDTH), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .CQN_WIDTH(CQN_WIDTH), - .EQ_PIPELINE(EQ_PIPELINE), - .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), - .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .CQ_PIPELINE(CQ_PIPELINE), - - // TX and RX engine configuration - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), - - // Scheduler configuration - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - - // Interface configuration - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_CPL_ENABLE(PTP_TS_ENABLE), - .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), - .TX_TAG_WIDTH(TX_TAG_WIDTH), - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .PFC_ENABLE(PFC_ENABLE), - .LFC_ENABLE(LFC_ENABLE), - .MAC_CTRL_ENABLE(0), - .TX_FIFO_DEPTH(TX_FIFO_DEPTH), - .RX_FIFO_DEPTH(RX_FIFO_DEPTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - - // RAM configuration - .DDR_CH(DDR_CH), - .DDR_ENABLE(DDR_ENABLE), - .DDR_GROUP_SIZE(1), - .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), - .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), - .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), - .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), - .AXI_DDR_AWUSER_ENABLE(0), - .AXI_DDR_WUSER_ENABLE(0), - .AXI_DDR_BUSER_ENABLE(0), - .AXI_DDR_ARUSER_ENABLE(0), - .AXI_DDR_RUSER_ENABLE(0), - .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), - .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), - .AXI_DDR_FIXED_BURST(0), - .AXI_DDR_WRAP_BURST(1), - .HBM_ENABLE(0), - - // Application block configuration - .APP_ID(APP_ID), - .APP_ENABLE(APP_ENABLE), - .APP_CTRL_ENABLE(APP_CTRL_ENABLE), - .APP_DMA_ENABLE(APP_DMA_ENABLE), - .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), - .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), - .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), - .APP_STAT_ENABLE(APP_STAT_ENABLE), - .APP_GPIO_IN_WIDTH(32), - .APP_GPIO_OUT_WIDTH(32), - - // DMA interface configuration - .DMA_IMM_ENABLE(DMA_IMM_ENABLE), - .DMA_IMM_WIDTH(DMA_IMM_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - - // PCIe interface configuration - .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), - .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), - .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), - .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), - .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), - .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), - .RC_STRADDLE(RC_STRADDLE), - .RQ_STRADDLE(RQ_STRADDLE), - .CQ_STRADDLE(CQ_STRADDLE), - .CC_STRADDLE(CC_STRADDLE), - .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), - .PF_COUNT(PF_COUNT), - .VF_COUNT(VF_COUNT), - .F_COUNT(F_COUNT), - .PCIE_TAG_COUNT(PCIE_TAG_COUNT), - - // Interrupt configuration - .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), - - // AXI lite interface configuration (control) - .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), - .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(0), - .RB_NEXT_PTR(RB_BASE_ADDR), - - // AXI lite interface configuration (application control) - .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), - .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), - - // Ethernet interface configuration - .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), - .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .AXIS_ETH_RX_USE_READY(0), - .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), - .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), - .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), - .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), - .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), - - // Statistics counter subsystem - .STAT_ENABLE(STAT_ENABLE), - .STAT_DMA_ENABLE(STAT_DMA_ENABLE), - .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), - .STAT_INC_WIDTH(STAT_INC_WIDTH), - .STAT_ID_WIDTH(STAT_ID_WIDTH) -) -core_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * AXI input (RC) - */ - .s_axis_rc_tdata(s_axis_rc_tdata), - .s_axis_rc_tkeep(s_axis_rc_tkeep), - .s_axis_rc_tvalid(s_axis_rc_tvalid), - .s_axis_rc_tready(s_axis_rc_tready), - .s_axis_rc_tlast(s_axis_rc_tlast), - .s_axis_rc_tuser(s_axis_rc_tuser), - - /* - * AXI output (RQ) - */ - .m_axis_rq_tdata(m_axis_rq_tdata), - .m_axis_rq_tkeep(m_axis_rq_tkeep), - .m_axis_rq_tvalid(m_axis_rq_tvalid), - .m_axis_rq_tready(m_axis_rq_tready), - .m_axis_rq_tlast(m_axis_rq_tlast), - .m_axis_rq_tuser(m_axis_rq_tuser), - - /* - * AXI input (CQ) - */ - .s_axis_cq_tdata(s_axis_cq_tdata), - .s_axis_cq_tkeep(s_axis_cq_tkeep), - .s_axis_cq_tvalid(s_axis_cq_tvalid), - .s_axis_cq_tready(s_axis_cq_tready), - .s_axis_cq_tlast(s_axis_cq_tlast), - .s_axis_cq_tuser(s_axis_cq_tuser), - - /* - * AXI output (CC) - */ - .m_axis_cc_tdata(m_axis_cc_tdata), - .m_axis_cc_tkeep(m_axis_cc_tkeep), - .m_axis_cc_tvalid(m_axis_cc_tvalid), - .m_axis_cc_tready(m_axis_cc_tready), - .m_axis_cc_tlast(m_axis_cc_tlast), - .m_axis_cc_tuser(m_axis_cc_tuser), - - /* - * Transmit sequence number input - */ - .s_axis_rq_seq_num_0(s_axis_rq_seq_num_0), - .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), - .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), - .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), - - /* - * Flow control - */ - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - /* - * Configuration inputs - */ - .cfg_max_read_req(cfg_max_read_req), - .cfg_max_payload(cfg_max_payload), - .cfg_rcb_status(cfg_rcb_status), - - /* - * Configuration interface - */ - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - - /* - * Interrupt interface - */ - .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), - .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), - .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), - .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), - .cfg_interrupt_msix_address(cfg_interrupt_msix_address), - .cfg_interrupt_msix_data(cfg_interrupt_msix_data), - .cfg_interrupt_msix_int(cfg_interrupt_msix_int), - .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), - .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), - .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), - .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - /* - * PCIe error outputs - */ - .status_error_cor(status_error_cor), - .status_error_uncor(status_error_uncor), - - /* - * AXI-Lite master interface (passthrough for NIC control and status) - */ - .m_axil_csr_awaddr(), - .m_axil_csr_awprot(), - .m_axil_csr_awvalid(), - .m_axil_csr_awready(1), - .m_axil_csr_wdata(), - .m_axil_csr_wstrb(), - .m_axil_csr_wvalid(), - .m_axil_csr_wready(1), - .m_axil_csr_bresp(0), - .m_axil_csr_bvalid(0), - .m_axil_csr_bready(), - .m_axil_csr_araddr(), - .m_axil_csr_arprot(), - .m_axil_csr_arvalid(), - .m_axil_csr_arready(1), - .m_axil_csr_rdata(0), - .m_axil_csr_rresp(0), - .m_axil_csr_rvalid(0), - .m_axil_csr_rready(), - - /* - * Control register interface - */ - .ctrl_reg_wr_addr(ctrl_reg_wr_addr), - .ctrl_reg_wr_data(ctrl_reg_wr_data), - .ctrl_reg_wr_strb(ctrl_reg_wr_strb), - .ctrl_reg_wr_en(ctrl_reg_wr_en), - .ctrl_reg_wr_wait(ctrl_reg_wr_wait), - .ctrl_reg_wr_ack(ctrl_reg_wr_ack), - .ctrl_reg_rd_addr(ctrl_reg_rd_addr), - .ctrl_reg_rd_en(ctrl_reg_rd_en), - .ctrl_reg_rd_data(ctrl_reg_rd_data), - .ctrl_reg_rd_wait(ctrl_reg_rd_wait), - .ctrl_reg_rd_ack(ctrl_reg_rd_ack), - - /* - * PTP clock - */ - .ptp_clk(ptp_clk), - .ptp_rst(ptp_rst), - .ptp_sample_clk(ptp_sample_clk), - .ptp_pps(ptp_pps), - .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), - .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), - .ptp_perout_locked(ptp_perout_locked), - .ptp_perout_error(ptp_perout_error), - .ptp_perout_pulse(ptp_perout_pulse), - - /* - * Ethernet - */ - .eth_tx_clk(eth_tx_clk), - .eth_tx_rst(eth_tx_rst), - - .eth_tx_ptp_clk(eth_tx_ptp_clk), - .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), - - .m_axis_eth_tx_tdata(axis_eth_tx_tdata), - .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), - .m_axis_eth_tx_tvalid(axis_eth_tx_tvalid), - .m_axis_eth_tx_tready(axis_eth_tx_tready), - .m_axis_eth_tx_tlast(axis_eth_tx_tlast), - .m_axis_eth_tx_tuser(axis_eth_tx_tuser), - - .s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts), - .s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag), - .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), - .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), - - .eth_tx_enable(eth_tx_enable), - .eth_tx_status(eth_tx_status), - .eth_tx_lfc_en(eth_tx_lfc_en), - .eth_tx_lfc_req(eth_tx_lfc_req), - .eth_tx_pfc_en(eth_tx_pfc_en), - .eth_tx_pfc_req(eth_tx_pfc_req), - .eth_tx_fc_quanta_clk_en(0), - - .eth_rx_clk(eth_rx_clk), - .eth_rx_rst(eth_rx_rst), - - .eth_rx_ptp_clk(eth_rx_ptp_clk), - .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), - - .s_axis_eth_rx_tdata(axis_eth_rx_tdata), - .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), - .s_axis_eth_rx_tvalid(axis_eth_rx_tvalid), - .s_axis_eth_rx_tready(axis_eth_rx_tready), - .s_axis_eth_rx_tlast(axis_eth_rx_tlast), - .s_axis_eth_rx_tuser(axis_eth_rx_tuser), - - .eth_rx_enable(eth_rx_enable), - .eth_rx_status(eth_rx_status), - .eth_rx_lfc_en(eth_rx_lfc_en), - .eth_rx_lfc_req(eth_rx_lfc_req), - .eth_rx_lfc_ack(eth_rx_lfc_ack), - .eth_rx_pfc_en(eth_rx_pfc_en), - .eth_rx_pfc_req(eth_rx_pfc_req), - .eth_rx_pfc_ack(eth_rx_pfc_ack), - .eth_rx_fc_quanta_clk_en(0), - - /* - * DDR - */ - .ddr_clk(ddr_clk), - .ddr_rst(ddr_rst), - - .m_axi_ddr_awid(m_axi_ddr_awid), - .m_axi_ddr_awaddr(m_axi_ddr_awaddr), - .m_axi_ddr_awlen(m_axi_ddr_awlen), - .m_axi_ddr_awsize(m_axi_ddr_awsize), - .m_axi_ddr_awburst(m_axi_ddr_awburst), - .m_axi_ddr_awlock(m_axi_ddr_awlock), - .m_axi_ddr_awcache(m_axi_ddr_awcache), - .m_axi_ddr_awprot(m_axi_ddr_awprot), - .m_axi_ddr_awqos(m_axi_ddr_awqos), - .m_axi_ddr_awuser(), - .m_axi_ddr_awvalid(m_axi_ddr_awvalid), - .m_axi_ddr_awready(m_axi_ddr_awready), - .m_axi_ddr_wdata(m_axi_ddr_wdata), - .m_axi_ddr_wstrb(m_axi_ddr_wstrb), - .m_axi_ddr_wlast(m_axi_ddr_wlast), - .m_axi_ddr_wuser(), - .m_axi_ddr_wvalid(m_axi_ddr_wvalid), - .m_axi_ddr_wready(m_axi_ddr_wready), - .m_axi_ddr_bid(m_axi_ddr_bid), - .m_axi_ddr_bresp(m_axi_ddr_bresp), - .m_axi_ddr_buser(0), - .m_axi_ddr_bvalid(m_axi_ddr_bvalid), - .m_axi_ddr_bready(m_axi_ddr_bready), - .m_axi_ddr_arid(m_axi_ddr_arid), - .m_axi_ddr_araddr(m_axi_ddr_araddr), - .m_axi_ddr_arlen(m_axi_ddr_arlen), - .m_axi_ddr_arsize(m_axi_ddr_arsize), - .m_axi_ddr_arburst(m_axi_ddr_arburst), - .m_axi_ddr_arlock(m_axi_ddr_arlock), - .m_axi_ddr_arcache(m_axi_ddr_arcache), - .m_axi_ddr_arprot(m_axi_ddr_arprot), - .m_axi_ddr_arqos(m_axi_ddr_arqos), - .m_axi_ddr_aruser(), - .m_axi_ddr_arvalid(m_axi_ddr_arvalid), - .m_axi_ddr_arready(m_axi_ddr_arready), - .m_axi_ddr_rid(m_axi_ddr_rid), - .m_axi_ddr_rdata(m_axi_ddr_rdata), - .m_axi_ddr_rresp(m_axi_ddr_rresp), - .m_axi_ddr_rlast(m_axi_ddr_rlast), - .m_axi_ddr_ruser(0), - .m_axi_ddr_rvalid(m_axi_ddr_rvalid), - .m_axi_ddr_rready(m_axi_ddr_rready), - - .ddr_status(ddr_status), - - /* - * HBM - */ - .hbm_clk(0), - .hbm_rst(0), - - .m_axi_hbm_awid(), - .m_axi_hbm_awaddr(), - .m_axi_hbm_awlen(), - .m_axi_hbm_awsize(), - .m_axi_hbm_awburst(), - .m_axi_hbm_awlock(), - .m_axi_hbm_awcache(), - .m_axi_hbm_awprot(), - .m_axi_hbm_awqos(), - .m_axi_hbm_awuser(), - .m_axi_hbm_awvalid(), - .m_axi_hbm_awready(0), - .m_axi_hbm_wdata(), - .m_axi_hbm_wstrb(), - .m_axi_hbm_wlast(), - .m_axi_hbm_wuser(), - .m_axi_hbm_wvalid(), - .m_axi_hbm_wready(0), - .m_axi_hbm_bid(0), - .m_axi_hbm_bresp(0), - .m_axi_hbm_buser(0), - .m_axi_hbm_bvalid(0), - .m_axi_hbm_bready(), - .m_axi_hbm_arid(), - .m_axi_hbm_araddr(), - .m_axi_hbm_arlen(), - .m_axi_hbm_arsize(), - .m_axi_hbm_arburst(), - .m_axi_hbm_arlock(), - .m_axi_hbm_arcache(), - .m_axi_hbm_arprot(), - .m_axi_hbm_arqos(), - .m_axi_hbm_aruser(), - .m_axi_hbm_arvalid(), - .m_axi_hbm_arready(0), - .m_axi_hbm_rid(0), - .m_axi_hbm_rdata(0), - .m_axi_hbm_rresp(0), - .m_axi_hbm_rlast(0), - .m_axi_hbm_ruser(0), - .m_axi_hbm_rvalid(0), - .m_axi_hbm_rready(), - - .hbm_status(0), - - /* - * Statistics input - */ - .s_axis_stat_tdata(0), - .s_axis_stat_tid(0), - .s_axis_stat_tvalid(1'b0), - .s_axis_stat_tready(), - - /* - * GPIO - */ - .app_gpio_in(0), - .app_gpio_out(), - - /* - * JTAG - */ - .app_jtag_tdi(1'b0), - .app_jtag_tdo(), - .app_jtag_tms(1'b0), - .app_jtag_tck(1'b0) -); - -endmodule - -`resetall diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/sync_signal.v b/fpga/mqnic/AU250/fpga_100g/rtl/sync_signal.v deleted file mode 100644 index 74b855fa1..000000000 --- a/fpga/mqnic/AU250/fpga_100g/rtl/sync_signal.v +++ /dev/null @@ -1,62 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog-2001 - -`resetall -`timescale 1 ns / 1 ps -`default_nettype none - -/* - * Synchronizes an asyncronous signal to a given clock by using a pipeline of - * two registers. - */ -module sync_signal #( - parameter WIDTH=1, // width of the input and output signals - parameter N=2 // depth of synchronizer -)( - input wire clk, - input wire [WIDTH-1:0] in, - output wire [WIDTH-1:0] out -); - -reg [WIDTH-1:0] sync_reg[N-1:0]; - -/* - * The synchronized output is the last register in the pipeline. - */ -assign out = sync_reg[N-1]; - -integer k; - -always @(posedge clk) begin - sync_reg[0] <= in; - for (k = 1; k < N; k = k + 1) begin - sync_reg[k] <= sync_reg[k-1]; - end -end - -endmodule - -`resetall diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile deleted file mode 100644 index 6b3457a52..000000000 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile +++ /dev/null @@ -1,251 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2020-2023 The Regents of the University of California - -TOPLEVEL_LANG = verilog - -SIM ?= icarus -WAVES ?= 0 - -COCOTB_HDL_TIMEUNIT = 1ns -COCOTB_HDL_TIMEPRECISION = 1ps - -DUT = fpga_core -TOPLEVEL = $(DUT) -MODULE = test_$(DUT) -VERILOG_SOURCES += ../../rtl/$(DUT).v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core.v -VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v -VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v -VERILOG_SOURCES += ../../rtl/common/cpl_write.v -VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v -VERILOG_SOURCES += ../../rtl/common/desc_fetch.v -VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/queue_manager.v -VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v -VERILOG_SOURCES += ../../rtl/common/tx_fifo.v -VERILOG_SOURCES += ../../rtl/common/rx_fifo.v -VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v -VERILOG_SOURCES += ../../rtl/common/tx_engine.v -VERILOG_SOURCES += ../../rtl/common/rx_engine.v -VERILOG_SOURCES += ../../rtl/common/tx_checksum.v -VERILOG_SOURCES += ../../rtl/common/rx_hash.v -VERILOG_SOURCES += ../../rtl/common/rx_checksum.v -VERILOG_SOURCES += ../../rtl/common/rb_drp.v -VERILOG_SOURCES += ../../rtl/common/stats_counter.v -VERILOG_SOURCES += ../../rtl/common/stats_collect.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v -VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v -VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v -VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v -VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v - -# module parameters - -# Structural configuration -export PARAM_IF_COUNT := 2 -export PARAM_PORTS_PER_IF := 1 -export PARAM_SCHED_PER_IF := $(PARAM_PORTS_PER_IF) -export PARAM_PORT_MASK := 0 - -# Clock configuration -export PARAM_CLK_PERIOD_NS_NUM := 4 -export PARAM_CLK_PERIOD_NS_DENOM := 1 - -# PTP configuration -export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 -export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 -export PARAM_PTP_CLOCK_PIPELINE := 0 -export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_SEPARATE_RX_CLOCK := 0 -export PARAM_PTP_PORT_CDC_PIPELINE := 0 -export PARAM_PTP_PEROUT_ENABLE := 0 -export PARAM_PTP_PEROUT_COUNT := 1 - -# Queue manager configuration -export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_CQ_OP_TABLE_SIZE := 32 -export PARAM_EQN_WIDTH := 6 -export PARAM_TX_QUEUE_INDEX_WIDTH := 13 -export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") -export PARAM_EQ_PIPELINE := 3 -export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") - -# TX and RX engine configuration -export PARAM_TX_DESC_TABLE_SIZE := 32 -export PARAM_RX_DESC_TABLE_SIZE := 32 -export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") - -# Scheduler configuration -export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) -export PARAM_TX_SCHEDULER_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_TDMA_INDEX_WIDTH := 6 - -# Interface configuration -export PARAM_PTP_TS_ENABLE := 1 -export PARAM_TX_CPL_FIFO_DEPTH := 32 -export PARAM_TX_CHECKSUM_ENABLE := 1 -export PARAM_RX_HASH_ENABLE := 1 -export PARAM_RX_CHECKSUM_ENABLE := 1 -export PARAM_LFC_ENABLE := 1 -export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) -export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 131072 -export PARAM_MAX_TX_SIZE := 9214 -export PARAM_MAX_RX_SIZE := 9214 -export PARAM_TX_RAM_SIZE := 131072 -export PARAM_RX_RAM_SIZE := 131072 - -# Application block configuration -export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) -export PARAM_APP_ENABLE := 0 -export PARAM_APP_CTRL_ENABLE := 1 -export PARAM_APP_DMA_ENABLE := 1 -export PARAM_APP_AXIS_DIRECT_ENABLE := 1 -export PARAM_APP_AXIS_SYNC_ENABLE := 1 -export PARAM_APP_AXIS_IF_ENABLE := 1 -export PARAM_APP_STAT_ENABLE := 1 - -# DMA interface configuration -export PARAM_DMA_IMM_ENABLE := 0 -export PARAM_DMA_IMM_WIDTH := 32 -export PARAM_DMA_LEN_WIDTH := 16 -export PARAM_DMA_TAG_WIDTH := 16 -export PARAM_RAM_ADDR_WIDTH := $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())") -export PARAM_RAM_PIPELINE := 2 - -# PCIe interface configuration -export PARAM_AXIS_PCIE_DATA_WIDTH := 512 -export PARAM_PF_COUNT := 1 -export PARAM_VF_COUNT := 0 - -# Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) - -# AXI lite interface configuration (control) -export PARAM_AXIL_CTRL_DATA_WIDTH := 32 -export PARAM_AXIL_CTRL_ADDR_WIDTH := 24 - -# AXI lite interface configuration (application control) -export PARAM_AXIL_APP_CTRL_DATA_WIDTH := $(PARAM_AXIL_CTRL_DATA_WIDTH) -export PARAM_AXIL_APP_CTRL_ADDR_WIDTH := 24 - -# Ethernet interface configuration -export PARAM_AXIS_ETH_TX_PIPELINE := 4 -export PARAM_AXIS_ETH_TX_FIFO_PIPELINE := 4 -export PARAM_AXIS_ETH_TX_TS_PIPELINE := 4 -export PARAM_AXIS_ETH_RX_PIPELINE := 4 -export PARAM_AXIS_ETH_RX_FIFO_PIPELINE := 4 - -# Statistics counter subsystem -export PARAM_STAT_ENABLE := 1 -export PARAM_STAT_DMA_ENABLE := 1 -export PARAM_STAT_PCIE_ENABLE := 1 -export PARAM_STAT_INC_WIDTH := 24 -export PARAM_STAT_ID_WIDTH := 12 - -ifeq ($(SIM), icarus) - PLUSARGS += -fst - - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif -else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - COMPILE_ARGS += --trace-fst - endif -endif - -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/mqnic.py b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/mqnic.py deleted file mode 120000 index dfa8522e7..000000000 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/mqnic.py +++ /dev/null @@ -1 +0,0 @@ -../../../../../common/tb/mqnic.py \ No newline at end of file diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py deleted file mode 100644 index 87569e0dc..000000000 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py +++ /dev/null @@ -1,797 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2020-2023 The Regents of the University of California - -import logging -import os -import sys - -import scapy.utils -from scapy.layers.l2 import Ether -from scapy.layers.inet import IP, UDP - -import cocotb_test.simulator - -import cocotb -from cocotb.log import SimLog -from cocotb.clock import Clock -from cocotb.triggers import RisingEdge, FallingEdge, Timer - -from cocotbext.axi import AxiStreamBus, AxiLiteBus, AxiLiteRam -from cocotbext.eth import EthMac -from cocotbext.pcie.core import RootComplex -from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice - -try: - import mqnic -except ImportError: - # attempt import from current directory - sys.path.insert(0, os.path.join(os.path.dirname(__file__))) - try: - import mqnic - finally: - del sys.path[0] - - -class TB(object): - def __init__(self, dut, msix_count=32): - self.dut = dut - - self.log = SimLog("cocotb.tb") - self.log.setLevel(logging.DEBUG) - - # PCIe - self.rc = RootComplex() - - self.rc.max_payload_size = 0x1 # 256 bytes - self.rc.max_read_request_size = 0x2 # 512 bytes - - self.dev = UltraScalePlusPcieDevice( - # configuration options - pcie_generation=3, - pcie_link_width=16, - user_clk_frequency=250e6, - alignment="dword", - cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1, - cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1, - rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1, - rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1, - rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2, - pf_count=1, - max_payload_size=1024, - enable_client_tag=True, - enable_extended_tag=True, - enable_parity=False, - enable_rx_msg_interface=False, - enable_sriov=False, - enable_extended_configuration=False, - - pf0_msi_enable=False, - pf0_msi_count=32, - pf1_msi_enable=False, - pf1_msi_count=1, - pf2_msi_enable=False, - pf2_msi_count=1, - pf3_msi_enable=False, - pf3_msi_count=1, - pf0_msix_enable=True, - pf0_msix_table_size=msix_count-1, - pf0_msix_table_bir=0, - pf0_msix_table_offset=0x00010000, - pf0_msix_pba_bir=0, - pf0_msix_pba_offset=0x00018000, - pf1_msix_enable=False, - pf1_msix_table_size=0, - pf1_msix_table_bir=0, - pf1_msix_table_offset=0x00000000, - pf1_msix_pba_bir=0, - pf1_msix_pba_offset=0x00000000, - pf2_msix_enable=False, - pf2_msix_table_size=0, - pf2_msix_table_bir=0, - pf2_msix_table_offset=0x00000000, - pf2_msix_pba_bir=0, - pf2_msix_pba_offset=0x00000000, - pf3_msix_enable=False, - pf3_msix_table_size=0, - pf3_msix_table_bir=0, - pf3_msix_table_offset=0x00000000, - pf3_msix_pba_bir=0, - pf3_msix_pba_offset=0x00000000, - - # signals - # Clock and Reset Interface - user_clk=dut.clk_250mhz, - user_reset=dut.rst_250mhz, - # user_lnk_up - # sys_clk - # sys_clk_gt - # sys_reset - # phy_rdy_out - - # Requester reQuest Interface - rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), - pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, - pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, - pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, - pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, - # pcie_rq_tag0 - # pcie_rq_tag1 - # pcie_rq_tag_av - # pcie_rq_tag_vld0 - # pcie_rq_tag_vld1 - - # Requester Completion Interface - rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), - - # Completer reQuest Interface - cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), - # pcie_cq_np_req - # pcie_cq_np_req_count - - # Completer Completion Interface - cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), - - # Transmit Flow Control Interface - # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, - # pcie_tfc_npd_av=dut.pcie_tfc_npd_av, - - # Configuration Management Interface - cfg_mgmt_addr=dut.cfg_mgmt_addr, - cfg_mgmt_function_number=dut.cfg_mgmt_function_number, - cfg_mgmt_write=dut.cfg_mgmt_write, - cfg_mgmt_write_data=dut.cfg_mgmt_write_data, - cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable, - cfg_mgmt_read=dut.cfg_mgmt_read, - cfg_mgmt_read_data=dut.cfg_mgmt_read_data, - cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done, - # cfg_mgmt_debug_access - - # Configuration Status Interface - # cfg_phy_link_down - # cfg_phy_link_status - # cfg_negotiated_width - # cfg_current_speed - cfg_max_payload=dut.cfg_max_payload, - cfg_max_read_req=dut.cfg_max_read_req, - # cfg_function_status - # cfg_vf_status - # cfg_function_power_state - # cfg_vf_power_state - # cfg_link_power_state - # cfg_err_cor_out - # cfg_err_nonfatal_out - # cfg_err_fatal_out - # cfg_local_error_out - # cfg_local_error_valid - # cfg_rx_pm_state - # cfg_tx_pm_state - # cfg_ltssm_state - cfg_rcb_status=dut.cfg_rcb_status, - # cfg_obff_enable - # cfg_pl_status_change - # cfg_tph_requester_enable - # cfg_tph_st_mode - # cfg_vf_tph_requester_enable - # cfg_vf_tph_st_mode - - # Configuration Received Message Interface - # cfg_msg_received - # cfg_msg_received_data - # cfg_msg_received_type - - # Configuration Transmit Message Interface - # cfg_msg_transmit - # cfg_msg_transmit_type - # cfg_msg_transmit_data - # cfg_msg_transmit_done - - # Configuration Flow Control Interface - cfg_fc_ph=dut.cfg_fc_ph, - cfg_fc_pd=dut.cfg_fc_pd, - cfg_fc_nph=dut.cfg_fc_nph, - cfg_fc_npd=dut.cfg_fc_npd, - cfg_fc_cplh=dut.cfg_fc_cplh, - cfg_fc_cpld=dut.cfg_fc_cpld, - cfg_fc_sel=dut.cfg_fc_sel, - - # Configuration Control Interface - # cfg_hot_reset_in - # cfg_hot_reset_out - # cfg_config_space_enable - # cfg_dsn - # cfg_bus_number - # cfg_ds_port_number - # cfg_ds_bus_number - # cfg_ds_device_number - # cfg_ds_function_number - # cfg_power_state_change_ack - # cfg_power_state_change_interrupt - cfg_err_cor_in=dut.status_error_cor, - cfg_err_uncor_in=dut.status_error_uncor, - # cfg_flr_in_process - # cfg_flr_done - # cfg_vf_flr_in_process - # cfg_vf_flr_func_num - # cfg_vf_flr_done - # cfg_pm_aspm_l1_entry_reject - # cfg_pm_aspm_tx_l0s_entry_disable - # cfg_req_pm_transition_l23_ready - # cfg_link_training_enable - - # Configuration Interrupt Controller Interface - # cfg_interrupt_int - # cfg_interrupt_sent - # cfg_interrupt_pending - # cfg_interrupt_msi_enable - # cfg_interrupt_msi_mmenable - # cfg_interrupt_msi_mask_update - # cfg_interrupt_msi_data - # cfg_interrupt_msi_select - # cfg_interrupt_msi_int - # cfg_interrupt_msi_pending_status - # cfg_interrupt_msi_pending_status_data_enable - # cfg_interrupt_msi_pending_status_function_num - # cfg_interrupt_msi_sent - # cfg_interrupt_msi_fail - cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable, - cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask, - cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable, - cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask, - cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address, - cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data, - cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int, - cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending, - cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status, - cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent, - cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail, - # cfg_interrupt_msi_attr - # cfg_interrupt_msi_tph_present - # cfg_interrupt_msi_tph_type - # cfg_interrupt_msi_tph_st_tag - cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, - - # Configuration Extend Interface - # cfg_ext_read_received - # cfg_ext_write_received - # cfg_ext_register_number - # cfg_ext_function_number - # cfg_ext_write_data - # cfg_ext_write_byte_enable - # cfg_ext_read_data - # cfg_ext_read_data_valid - ) - - # self.dev.log.setLevel(logging.DEBUG) - - self.rc.make_port().connect(self.dev) - - self.driver = mqnic.Driver() - - self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) - if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): - self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) - - cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start()) - dut.ptp_rst.setimmediatevalue(0) - cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start()) - - # Ethernet - self.qsfp_mac = [] - - for k in range(2): - cocotb.start_soon(Clock(getattr(dut, f"qsfp{k}_rx_clk"), 3.102, units="ns").start()) - cocotb.start_soon(Clock(getattr(dut, f"qsfp{k}_tx_clk"), 3.102, units="ns").start()) - - mac = EthMac( - tx_clk=getattr(dut, f"qsfp{k}_tx_clk"), - tx_rst=getattr(dut, f"qsfp{k}_tx_rst"), - tx_bus=AxiStreamBus.from_prefix(dut, f"qsfp{k}_tx_axis"), - tx_ptp_time=getattr(dut, f"qsfp{k}_tx_ptp_time"), - tx_ptp_ts=getattr(dut, f"qsfp{k}_tx_ptp_ts"), - tx_ptp_ts_tag=getattr(dut, f"qsfp{k}_tx_ptp_ts_tag"), - tx_ptp_ts_valid=getattr(dut, f"qsfp{k}_tx_ptp_ts_valid"), - rx_clk=getattr(dut, f"qsfp{k}_rx_clk"), - rx_rst=getattr(dut, f"qsfp{k}_rx_rst"), - rx_bus=AxiStreamBus.from_prefix(dut, f"qsfp{k}_rx_axis"), - rx_ptp_time=getattr(dut, f"qsfp{k}_rx_ptp_time"), - ifg=12, speed=100e9 - ) - - self.qsfp_mac.append(mac) - - getattr(dut, f"qsfp{k}_rx_status").setimmediatevalue(1) - getattr(dut, f"qsfp{k}_rx_lfc_req").setimmediatevalue(0) - getattr(dut, f"qsfp{k}_rx_pfc_req").setimmediatevalue(0) - - cocotb.start_soon(Clock(getattr(dut, f"qsfp{k}_drp_clk"), 8, units="ns").start()) - getattr(dut, f"qsfp{k}_drp_rst").setimmediatevalue(0) - getattr(dut, f"qsfp{k}_drp_do").setimmediatevalue(0) - getattr(dut, f"qsfp{k}_drp_rdy").setimmediatevalue(0) - - getattr(dut, f"qsfp{k}_modprsl").setimmediatevalue(0) - getattr(dut, f"qsfp{k}_intl").setimmediatevalue(1) - - dut.sw.setimmediatevalue(0) - - dut.i2c_scl_i.setimmediatevalue(1) - dut.i2c_sda_i.setimmediatevalue(1) - - dut.qspi_dq_i.setimmediatevalue(0) - - self.cms_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil_cms"), dut.m_axil_cms_clk, dut.m_axil_cms_rst, size=256*1024) - - self.loopback_enable = False - cocotb.start_soon(self._run_loopback()) - - async def init(self): - - self.dut.ptp_rst.setimmediatevalue(0) - for k in range(2): - getattr(self.dut, f"qsfp{k}_rx_rst").setimmediatevalue(0) - getattr(self.dut, f"qsfp{k}_tx_rst").setimmediatevalue(0) - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.ptp_rst.setimmediatevalue(1) - for k in range(2): - getattr(self.dut, f"qsfp{k}_rx_rst").setimmediatevalue(1) - getattr(self.dut, f"qsfp{k}_tx_rst").setimmediatevalue(1) - - await FallingEdge(self.dut.rst_250mhz) - await Timer(100, 'ns') - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.ptp_rst.setimmediatevalue(0) - for k in range(2): - getattr(self.dut, f"qsfp{k}_rx_rst").setimmediatevalue(0) - getattr(self.dut, f"qsfp{k}_tx_rst").setimmediatevalue(0) - - await self.rc.enumerate() - - async def _run_loopback(self): - while True: - await RisingEdge(self.dut.clk_250mhz) - - if self.loopback_enable: - for mac in self.qsfp_mac: - if not mac.tx.empty(): - await mac.rx.send(await mac.tx.recv()) - - -@cocotb.test() -async def run_test_nic(dut): - - tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index)) - - await tb.init() - - tb.log.info("Init driver") - await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id)) - await tb.driver.interfaces[0].open() - # await tb.driver.interfaces[1].open() - - # enable queues - tb.log.info("Enable queues") - await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) - for k in range(len(tb.driver.interfaces[0].txq)): - await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003) - - # wait for all writes to complete - await tb.driver.hw_regs.read_dword(0) - tb.log.info("Init complete") - - tb.log.info("Send and receive single packet") - - data = bytearray([x % 256 for x in range(1024)]) - - await tb.driver.interfaces[0].start_xmit(data, 0) - - pkt = await tb.qsfp_mac[0].tx.recv() - tb.log.info("Packet: %s", pkt) - - await tb.qsfp_mac[0].rx.send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - # await tb.driver.interfaces[1].start_xmit(data, 0) - - # pkt = await tb.qsfp_mac[1].tx.recv() - # tb.log.info("Packet: %s", pkt) - - # await tb.qsfp_mac[1].rx.send(pkt) - - # pkt = await tb.driver.interfaces[1].recv() - - # tb.log.info("Packet: %s", pkt) - # assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.log.info("RX and TX checksum tests") - - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') - ip = IP(src='192.168.1.100', dst='192.168.1.101') - udp = UDP(sport=1, dport=2) - test_pkt = eth / ip / udp / payload - - test_pkt2 = test_pkt.copy() - test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) - - await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - - pkt = await tb.qsfp_mac[0].tx.recv() - tb.log.info("Packet: %s", pkt) - - await tb.qsfp_mac[0].rx.send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - assert Ether(pkt.data).build() == test_pkt.build() - - tb.log.info("Queue mapping offset test") - - data = bytearray([x % 256 for x in range(1024)]) - - tb.loopback_enable = True - - for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) - - await tb.driver.interfaces[0].start_xmit(data, 0) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - assert pkt.queue == k - - tb.loopback_enable = False - - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) - - tb.log.info("Queue mapping RSS mask test") - - await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) - - for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) - - tb.loopback_enable = True - - queues = set() - - for k in range(64): - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') - ip = IP(src='192.168.1.100', dst='192.168.1.101') - udp = UDP(sport=1, dport=k+0) - test_pkt = eth / ip / udp / payload - - test_pkt2 = test_pkt.copy() - test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) - - await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - - for k in range(64): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - queues.add(pkt.queue) - - assert len(queues) == 4 - - tb.loopback_enable = False - - await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0) - - tb.log.info("Multiple small packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - tb.log.info("Multiple large packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - tb.log.info("Jumbo frames") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(9014)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - await RisingEdge(dut.clk_250mhz) - await RisingEdge(dut.clk_250mhz) - - -# cocotb-test - -tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) -app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app')) -axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl')) -axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) -eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) -pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl')) - - -def test_fpga_core(request): - dut = "fpga_core" - module = os.path.splitext(os.path.basename(__file__))[0] - toplevel = dut - - verilog_sources = [ - os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), - os.path.join(rtl_dir, "common", "mqnic_core.v"), - os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), - os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), - os.path.join(rtl_dir, "common", "mqnic_port_tx.v"), - os.path.join(rtl_dir, "common", "mqnic_port_rx.v"), - os.path.join(rtl_dir, "common", "mqnic_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), - os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), - os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"), - os.path.join(rtl_dir, "common", "cpl_write.v"), - os.path.join(rtl_dir, "common", "cpl_op_mux.v"), - os.path.join(rtl_dir, "common", "desc_fetch.v"), - os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "queue_manager.v"), - os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), - os.path.join(rtl_dir, "common", "tx_fifo.v"), - os.path.join(rtl_dir, "common", "rx_fifo.v"), - os.path.join(rtl_dir, "common", "tx_req_mux.v"), - os.path.join(rtl_dir, "common", "tx_engine.v"), - os.path.join(rtl_dir, "common", "rx_engine.v"), - os.path.join(rtl_dir, "common", "tx_checksum.v"), - os.path.join(rtl_dir, "common", "rx_hash.v"), - os.path.join(rtl_dir, "common", "rx_checksum.v"), - os.path.join(rtl_dir, "common", "rb_drp.v"), - os.path.join(rtl_dir, "common", "stats_counter.v"), - os.path.join(rtl_dir, "common", "stats_collect.v"), - os.path.join(rtl_dir, "common", "stats_pcie_if.v"), - os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"), - os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"), - os.path.join(rtl_dir, "common", "stats_dma_latency.v"), - os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), - os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), - os.path.join(eth_rtl_dir, "ptp_perout.v"), - os.path.join(axi_rtl_dir, "axil_interconnect.v"), - os.path.join(axi_rtl_dir, "axil_crossbar.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"), - os.path.join(axi_rtl_dir, "axil_reg_if.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"), - os.path.join(axi_rtl_dir, "axil_register_rd.v"), - os.path.join(axi_rtl_dir, "axil_register_wr.v"), - os.path.join(axi_rtl_dir, "arbiter.v"), - os.path.join(axi_rtl_dir, "priority_encoder.v"), - os.path.join(axis_rtl_dir, "axis_adapter.v"), - os.path.join(axis_rtl_dir, "axis_arb_mux.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_demux.v"), - os.path.join(axis_rtl_dir, "axis_fifo.v"), - os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), - os.path.join(axis_rtl_dir, "axis_register.v"), - os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), - os.path.join(pcie_rtl_dir, "pcie_msix.v"), - os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_psdpram.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), - os.path.join(pcie_rtl_dir, "pulse_merge.v"), - ] - - parameters = {} - - # Structural configuration - parameters['IF_COUNT'] = 2 - parameters['PORTS_PER_IF'] = 1 - parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] - parameters['PORT_MASK'] = 0 - - # Clock configuration - parameters['CLK_PERIOD_NS_NUM'] = 4 - parameters['CLK_PERIOD_NS_DENOM'] = 1 - - # PTP configuration - parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 - parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 - parameters['PTP_CLOCK_PIPELINE'] = 0 - parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_SEPARATE_RX_CLOCK'] = 0 - parameters['PTP_PORT_CDC_PIPELINE'] = 0 - parameters['PTP_PEROUT_ENABLE'] = 0 - parameters['PTP_PEROUT_COUNT'] = 1 - - # Queue manager configuration - parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['CQ_OP_TABLE_SIZE'] = 32 - parameters['EQN_WIDTH'] = 6 - parameters['TX_QUEUE_INDEX_WIDTH'] = 13 - parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 - parameters['EQ_PIPELINE'] = 3 - parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) - - # TX and RX engine configuration - parameters['TX_DESC_TABLE_SIZE'] = 32 - parameters['RX_DESC_TABLE_SIZE'] = 32 - parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) - - # Scheduler configuration - parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] - parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['TDMA_INDEX_WIDTH'] = 6 - - # Interface configuration - parameters['PTP_TS_ENABLE'] = 1 - parameters['TX_CPL_FIFO_DEPTH'] = 32 - parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_HASH_ENABLE'] = 1 - parameters['RX_CHECKSUM_ENABLE'] = 1 - parameters['LFC_ENABLE'] = 1 - parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] - parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 131072 - parameters['MAX_TX_SIZE'] = 9214 - parameters['MAX_RX_SIZE'] = 9214 - parameters['TX_RAM_SIZE'] = 131072 - parameters['RX_RAM_SIZE'] = 131072 - - # Application block configuration - parameters['APP_ID'] = 0x00000000 - parameters['APP_ENABLE'] = 0 - parameters['APP_CTRL_ENABLE'] = 1 - parameters['APP_DMA_ENABLE'] = 1 - parameters['APP_AXIS_DIRECT_ENABLE'] = 1 - parameters['APP_AXIS_SYNC_ENABLE'] = 1 - parameters['APP_AXIS_IF_ENABLE'] = 1 - parameters['APP_STAT_ENABLE'] = 1 - - # DMA interface configuration - parameters['DMA_IMM_ENABLE'] = 0 - parameters['DMA_IMM_WIDTH'] = 32 - parameters['DMA_LEN_WIDTH'] = 16 - parameters['DMA_TAG_WIDTH'] = 16 - parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length() - parameters['RAM_PIPELINE'] = 2 - - # PCIe interface configuration - parameters['AXIS_PCIE_DATA_WIDTH'] = 512 - parameters['PF_COUNT'] = 1 - parameters['VF_COUNT'] = 0 - - # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] - - # AXI lite interface configuration (control) - parameters['AXIL_CTRL_DATA_WIDTH'] = 32 - parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 - - # AXI lite interface configuration (application control) - parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH'] - parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24 - - # Ethernet interface configuration - parameters['AXIS_ETH_TX_PIPELINE'] = 4 - parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 4 - parameters['AXIS_ETH_TX_TS_PIPELINE'] = 4 - parameters['AXIS_ETH_RX_PIPELINE'] = 4 - parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 4 - - # Statistics counter subsystem - parameters['STAT_ENABLE'] = 1 - parameters['STAT_DMA_ENABLE'] = 1 - parameters['STAT_PCIE_ENABLE'] = 1 - parameters['STAT_INC_WIDTH'] = 24 - parameters['STAT_ID_WIDTH'] = 12 - - extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} - - sim_build = os.path.join(tests_dir, "sim_build", - request.node.name.replace('[', '-').replace(']', '')) - - cocotb_test.simulator.run( - python_search=[tests_dir], - verilog_sources=verilog_sources, - toplevel=toplevel, - module=module, - parameters=parameters, - sim_build=sim_build, - extra_env=extra_env, - ) diff --git a/fpga/mqnic/AU250/fpga_25g/Makefile b/fpga/mqnic/AU250/fpga_25g/Makefile deleted file mode 100644 index f504bd06f..000000000 --- a/fpga/mqnic/AU250/fpga_25g/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# Targets -TARGETS:= - -# Subdirectories -SUBDIRS = fpga -SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) - -# Rules -.PHONY: all -all: $(SUBDIRS) $(TARGETS) - -.PHONY: $(SUBDIRS) -$(SUBDIRS): - cd $@ && $(MAKE) - -.PHONY: $(SUBDIRS_CLEAN) -$(SUBDIRS_CLEAN): - cd $(@:.clean=) && $(MAKE) clean - -.PHONY: clean -clean: $(SUBDIRS_CLEAN) - -rm -rf $(TARGETS) - -program: - #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit diff --git a/fpga/mqnic/AU250/fpga_25g/README.md b/fpga/mqnic/AU250/fpga_25g/README.md deleted file mode 100644 index 0f5426def..000000000 --- a/fpga/mqnic/AU250/fpga_25g/README.md +++ /dev/null @@ -1,23 +0,0 @@ -# Corundum mqnic for Alveo U250 - -## Introduction - -This design targets the Xilinx Alveo U250 FPGA board. - -* FPGA: xcu250-figd2104-2-e -* PHY: 10G BASE-R PHY IP core and internal GTY transceiver -* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM) - -## Quick start - -### Build FPGA bitstream - -Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. - -### Build driver and userspace tools - -On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools. - -### Testing - -Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state. diff --git a/fpga/mqnic/AU250/fpga_25g/app b/fpga/mqnic/AU250/fpga_25g/app deleted file mode 120000 index 4d46690fb..000000000 --- a/fpga/mqnic/AU250/fpga_25g/app +++ /dev/null @@ -1 +0,0 @@ -../../../app/ \ No newline at end of file diff --git a/fpga/mqnic/AU250/fpga_25g/boot.xdc b/fpga/mqnic/AU250/fpga_25g/boot.xdc deleted file mode 100644 index 5fb323e94..000000000 --- a/fpga/mqnic/AU250/fpga_25g/boot.xdc +++ /dev/null @@ -1,4 +0,0 @@ -# Timing constraints for FPGA boot logic - -set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] -set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] diff --git a/fpga/mqnic/AU250/fpga_25g/cfgmclk.xdc b/fpga/mqnic/AU250/fpga_25g/cfgmclk.xdc deleted file mode 100644 index 51f8c2ab1..000000000 --- a/fpga/mqnic/AU250/fpga_25g/cfgmclk.xdc +++ /dev/null @@ -1,4 +0,0 @@ -# Timing constraints for cfgmclk - -# Fcfgmclk is 50 MHz +/- 15%, rounding to 15 ns period -create_clock -period 15 -name cfgmclk [get_pins startupe3_inst/CFGMCLK] diff --git a/fpga/mqnic/AU250/fpga_25g/common/vivado.mk b/fpga/mqnic/AU250/fpga_25g/common/vivado.mk deleted file mode 100644 index 1402e2382..000000000 --- a/fpga/mqnic/AU250/fpga_25g/common/vivado.mk +++ /dev/null @@ -1,137 +0,0 @@ -################################################################### -# -# Xilinx Vivado FPGA Makefile -# -# Copyright (c) 2016 Alex Forencich -# -################################################################### -# -# Parameters: -# FPGA_TOP - Top module name -# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) -# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) -# SYN_FILES - space-separated list of source files -# INC_FILES - space-separated list of include files -# XDC_FILES - space-separated list of timing constraint files -# XCI_FILES - space-separated list of IP XCI files -# -# Example: -# -# FPGA_TOP = fpga -# FPGA_FAMILY = VirtexUltrascale -# FPGA_DEVICE = xcvu095-ffva2104-2-e -# SYN_FILES = rtl/fpga.v -# XDC_FILES = fpga.xdc -# XCI_FILES = ip/pcspma.xci -# include ../common/vivado.mk -# -################################################################### - -# phony targets -.PHONY: fpga vivado tmpclean clean distclean - -# prevent make from deleting intermediate files and reports -.PRECIOUS: %.xpr %.bit %.mcs %.prm -.SECONDARY: - -CONFIG ?= config.mk --include ../$(CONFIG) - -FPGA_TOP ?= fpga -PROJECT ?= $(FPGA_TOP) - -SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) - -ifdef XDC_FILES - XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -else - XDC_FILES_REL = $(PROJECT).xdc -endif - -################################################################### -# Main Targets -# -# all: build everything -# clean: remove output files and project files -################################################################### - -all: fpga - -fpga: $(PROJECT).bit - -vivado: $(PROJECT).xpr - vivado $(PROJECT).xpr - -tmpclean:: - -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl - -clean:: tmpclean - -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl - -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt - -distclean:: clean - -rm -rf rev - -################################################################### -# Target implementations -################################################################### - -# Vivado project file -create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) - rm -rf defines.v - touch defines.v - for x in $(DEFS); do echo '`define' $$x >> defines.v; done - echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ - echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ - echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ - echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ - for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done - for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) - echo "open_project -quiet $(PROJECT).xpr" > $@ - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -$(PROJECT).xpr: create_project.tcl update_config.tcl - vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) - -# synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr - echo "open_project $(PROJECT).xpr" > run_synth.tcl - echo "reset_run synth_1" >> run_synth.tcl - echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl - echo "wait_on_run synth_1" >> run_synth.tcl - vivado -nojournal -nolog -mode batch -source run_synth.tcl - -# implementation run -$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp - echo "open_project $(PROJECT).xpr" > run_impl.tcl - echo "reset_run impl_1" >> run_impl.tcl - echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl - echo "wait_on_run impl_1" >> run_impl.tcl - echo "open_run impl_1" >> run_impl.tcl - echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl - echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl - vivado -nojournal -nolog -mode batch -source run_impl.tcl - -# bit file -$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp - echo "open_project $(PROJECT).xpr" > generate_bit.tcl - echo "open_run impl_1" >> generate_bit.tcl - echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl - echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl - vivado -nojournal -nolog -mode batch -source generate_bit.tcl - ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi - mkdir -p rev - COUNT=100; \ - while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ - do COUNT=$$((COUNT+1)); done; \ - cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/mqnic/AU250/fpga_25g/fpga.xdc b/fpga/mqnic/AU250/fpga_25g/fpga.xdc deleted file mode 100644 index 2a3ff77fc..000000000 --- a/fpga/mqnic/AU250/fpga_25g/fpga.xdc +++ /dev/null @@ -1,848 +0,0 @@ -# XDC constraints for the Xilinx Alveo U250 board -# part: xcu250-figd2104-2-e - -# General configuration -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design] -set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] -set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] -set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] -set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] - -set_operating_conditions -design_power_budget 160 - -# System clocks -# 300 MHz (DDR 0) -set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] -set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] -#create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p] - -# 300 MHz (DDR 1) -set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] -set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] -#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] - -# 300 MHz (DDR 2) -set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] -set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] -#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] - -# 300 MHz (DDR 3) -set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] -set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] -#create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p] - -# SI570 user clock -#set_property -dict {LOC AU19 IOSTANDARD LVDS} [get_ports clk_user_p] -#set_property -dict {LOC AV19 IOSTANDARD LVDS} [get_ports clk_user_n] -#create_clock -period 6.400 -name clk_user [get_ports clk_user_p] - -# LEDs -set_property -dict {LOC BC21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] -set_property -dict {LOC BB21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] -set_property -dict {LOC BA20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}] - -set_false_path -to [get_ports {led[*]}] -set_output_delay 0 [get_ports {led[*]}] - -# Reset button -#set_property -dict {LOC AL20 IOSTANDARD LVCMOS12} [get_ports reset] - -#set_false_path -from [get_ports {reset}] -#set_input_delay 0 [get_ports {reset}] - -# DIP switches -set_property -dict {LOC AN22 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] -set_property -dict {LOC AM19 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] -set_property -dict {LOC AL19 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] -set_property -dict {LOC AP20 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] - -set_false_path -from [get_ports {sw[*]}] -set_input_delay 0 [get_ports {sw[*]}] - -# UART -#set_property -dict {LOC BF18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd] -#set_property -dict {LOC BB20 IOSTANDARD LVCMOS12} [get_ports uart_rxd] - -#set_false_path -to [get_ports {uart_txd}] -#set_output_delay 0 [get_ports {uart_txd}] -#set_false_path -from [get_ports {uart_rxd}] -#set_input_delay 0 [get_ports {uart_rxd}] - -# BMC -set_property -dict {LOC AR20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[0]}] -set_property -dict {LOC AM20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[1]}] -set_property -dict {LOC AM21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[2]}] -set_property -dict {LOC AN21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[3]}] -set_property -dict {LOC BB19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_uart_txd}] -set_property -dict {LOC BA19 IOSTANDARD LVCMOS12} [get_ports {msp_uart_rxd}] - -set_false_path -to [get_ports {msp_uart_txd}] -set_output_delay 0 [get_ports {msp_uart_txd}] -set_false_path -from [get_ports {msp_gpio[*] msp_uart_rxd}] -set_input_delay 0 [get_ports {msp_gpio[*] msp_uart_rxd}] - -# QSFP28 Interfaces -set_property -dict {LOC N4 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC N3 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC N9 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC N8 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC M2 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC M1 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC M7 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC M6 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC L4 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC L3 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC L9 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC L8 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC K2 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC K1 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC K7 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC K6 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13 -#set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14 -set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18 -set_property -dict {LOC K10 } [get_ports qsfp0_mgt_refclk_1_n] ;# MGTREFCLK1N_231 from U9.17 -set_property -dict {LOC BE16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_modsell] -set_property -dict {LOC BE17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl] -set_property -dict {LOC BE20 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_modprsl] -set_property -dict {LOC BE21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_intl] -set_property -dict {LOC BD18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode] -set_property -dict {LOC AT22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_refclk_reset] -set_property -dict {LOC AT20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[0]}] -set_property -dict {LOC AU22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[1]}] - -# 156.25 MHz MGT reference clock (from SI570) -#create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports qsfp0_mgt_refclk_0_p] - -# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) -#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] - -# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) -create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] - -set_false_path -to [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] -set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] -set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}] -set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}] - -set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC U9 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC U8 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC T2 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC T1 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC R4 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC R3 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC R9 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC R8 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC P2 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC P1 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 -set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 -#set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15 -#set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16 -set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18 -set_property -dict {LOC P10 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U12.17 -set_property -dict {LOC AY20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_modsell] -set_property -dict {LOC BC18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl] -set_property -dict {LOC BC19 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_modprsl] -set_property -dict {LOC AV21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_intl] -set_property -dict {LOC AV22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode] -set_property -dict {LOC AR21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_refclk_reset] -set_property -dict {LOC AR22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[0]}] -set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[1]}] - -# 156.25 MHz MGT reference clock (from SI570) -#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p] - -# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) -#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] - -# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) -create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] - -set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] -set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] -set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] -set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] - -# I2C interface -#set_property -dict {LOC BF19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset] -set_property -dict {LOC BF20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_scl] -set_property -dict {LOC BF17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_sda] - -set_false_path -to [get_ports {i2c_sda i2c_scl}] -set_output_delay 0 [get_ports {i2c_sda i2c_scl}] -set_false_path -from [get_ports {i2c_sda i2c_scl}] -set_input_delay 0 [get_ports {i2c_sda i2c_scl}] - -# PCIe Interface -set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AG9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AG8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AJ9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AJ8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AL4 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AL3 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AL9 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AL8 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AN4 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AN3 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AN9 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AN8 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AR4 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AR3 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AR9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AR8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AU4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AU3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AU9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AU8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC AV7 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC AV6 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC AW4 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC AW3 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BB5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BB4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BD5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BD4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BF5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC BF4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4 -set_property -dict {LOC AM11 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_226 -set_property -dict {LOC AM10 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_226 -set_property -dict {LOC BD21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n] - -# 100 MHz MGT reference clock -create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p] - -set_false_path -from [get_ports {pcie_reset_n}] -set_input_delay 0 [get_ports {pcie_reset_n}] - -# DDR4 C0 -set_property -dict {LOC AT36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] -set_property -dict {LOC AV36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] -set_property -dict {LOC AV37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] -set_property -dict {LOC AW35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] -set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] -set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] -set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] -set_property -dict {LOC BA40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] -set_property -dict {LOC BA37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] -set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] -set_property -dict {LOC AR35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] -set_property -dict {LOC BA39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] -set_property -dict {LOC BB40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] -set_property -dict {LOC AN36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] -set_property -dict {LOC AP35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] -set_property -dict {LOC AP36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] -set_property -dict {LOC AR36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] -set_property -dict {LOC AT35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] -set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] -set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] -set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] -set_property -dict {LOC AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[0]}] -set_property -dict {LOC AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[0]}] -#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[1]}] -#set_property -dict {LOC AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[1]}] -set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}] -#set_property -dict {LOC BC40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}] -set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}] -#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}] -#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}] -#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}] -set_property -dict {LOC BB39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] -set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}] -#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}] -set_property -dict {LOC AU36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] -set_property -dict {LOC AU31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] - -set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] -set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] -set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] -set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] -set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] -set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] -set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] -set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] -set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] -set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] -set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] -set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] -set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] -set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] -set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] -set_property -dict {LOC BF29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] -set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] -set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] -set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] -set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] -set_property -dict {LOC BC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] -set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] -set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] -set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] -set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] -set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] -set_property -dict {LOC AV34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] -set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] -set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] -set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] -set_property -dict {LOC BA35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] -set_property -dict {LOC BA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] -set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] -set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] -set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] -set_property -dict {LOC AT32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] -set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] -set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] -set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] -set_property -dict {LOC AR31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] -set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] -set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] -set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] -set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] -set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] -set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] -set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] -set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] -set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] -set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] -set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] -set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] -set_property -dict {LOC AV29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] -set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] -set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] -set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] -set_property -dict {LOC BD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] -set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] -set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] -set_property -dict {LOC BD35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] -set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] -set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] -set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] -set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] -set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] -set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] -set_property -dict {LOC BF43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] -set_property -dict {LOC BF42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] -set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] -set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] -set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] -set_property -dict {LOC BF41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] -set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] -set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] -set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] -set_property -dict {LOC BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] -set_property -dict {LOC BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] -set_property -dict {LOC BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] -set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] -set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] -set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] -set_property -dict {LOC BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] -set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] -set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] -set_property -dict {LOC AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] -set_property -dict {LOC AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] -set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] -set_property -dict {LOC BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] -set_property -dict {LOC AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] -set_property -dict {LOC AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] -set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}] -set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}] -set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}] -set_property -dict {LOC AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}] -set_property -dict {LOC AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}] -set_property -dict {LOC AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}] -set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}] -set_property -dict {LOC AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}] -set_property -dict {LOC AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}] -set_property -dict {LOC AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}] -set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}] -set_property -dict {LOC BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}] -set_property -dict {LOC BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}] -set_property -dict {LOC BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}] -set_property -dict {LOC BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}] -set_property -dict {LOC BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}] -set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}] -set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}] - -# DDR4 C1 -set_property -dict {LOC AN24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] -set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] -set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] -set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] -set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] -set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] -set_property -dict {LOC AV24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] -set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] -set_property -dict {LOC AY25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] -set_property -dict {LOC BA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] -set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] -set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] -set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] -set_property -dict {LOC AL24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] -set_property -dict {LOC AL25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] -set_property -dict {LOC AM25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] -set_property -dict {LOC AN23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] -set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] -set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] -set_property -dict {LOC BC22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] -set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] -set_property -dict {LOC AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[0]}] -set_property -dict {LOC AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[0]}] -#set_property -dict {LOC AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[1]}] -#set_property -dict {LOC AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[1]}] -set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}] -#set_property -dict {LOC BB24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}] -set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}] -#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}] -#set_property -dict {LOC AR23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}] -#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}] -set_property -dict {LOC AW25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] -set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}] -#set_property -dict {LOC AP24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}] -set_property -dict {LOC AT23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] -set_property -dict {LOC AR17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] - -set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] -set_property -dict {LOC BD7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] -set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] -set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] -set_property -dict {LOC BD10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] -set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] -set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] -set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] -set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] -set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] -set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] -set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] -set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] -set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] -set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] -set_property -dict {LOC BA11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] -set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] -set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] -set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] -set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] -set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] -set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] -set_property -dict {LOC BA7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] -set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] -set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] -set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] -set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] -set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] -set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] -set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] -set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] -set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] -set_property -dict {LOC BE13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] -set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] -set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] -set_property -dict {LOC BD13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] -set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] -set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] -set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] -set_property -dict {LOC BF13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] -set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] -set_property -dict {LOC BA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] -set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] -set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] -set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] -set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] -set_property -dict {LOC BC11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] -set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] -set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] -set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] -set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] -set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] -set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] -set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] -set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] -set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] -set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] -set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] -set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] -set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] -set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] -set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] -set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] -set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] -set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] -set_property -dict {LOC BF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] -set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] -set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] -set_property -dict {LOC BD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] -set_property -dict {LOC BC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] -set_property -dict {LOC BF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] -set_property -dict {LOC BE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] -set_property -dict {LOC BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] -set_property -dict {LOC BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] -set_property -dict {LOC BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] -set_property -dict {LOC BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] -set_property -dict {LOC AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] -set_property -dict {LOC AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] -set_property -dict {LOC AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] -set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] -set_property -dict {LOC BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] -set_property -dict {LOC BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] -set_property -dict {LOC BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] -set_property -dict {LOC BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] -set_property -dict {LOC AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] -set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] -set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] -set_property -dict {LOC AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] -set_property -dict {LOC BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] -set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] -set_property -dict {LOC BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] -set_property -dict {LOC BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] -set_property -dict {LOC BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}] -set_property -dict {LOC BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}] -set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}] -set_property -dict {LOC BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}] -set_property -dict {LOC AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}] -set_property -dict {LOC AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}] -set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}] -set_property -dict {LOC AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}] -set_property -dict {LOC AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}] -set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}] -set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}] -set_property -dict {LOC AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}] -set_property -dict {LOC BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}] -set_property -dict {LOC BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}] -set_property -dict {LOC BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}] -set_property -dict {LOC BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}] - -# DDR4 C2 -set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] -set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] -set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] -set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] -set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] -set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] -set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] -set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] -set_property -dict {LOC A32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] -set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] -set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] -set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] -set_property -dict {LOC M30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] -set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] -set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] -set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] -set_property -dict {LOC K30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] -set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] -set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] -set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] -set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}] -set_property -dict {LOC C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[0]}] -set_property -dict {LOC B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[0]}] -#set_property -dict {LOC D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[1]}] -#set_property -dict {LOC D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[1]}] -set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}] -#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}] -set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}] -#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}] -#set_property -dict {LOC L30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}] -#set_property -dict {LOC K31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}] -set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] -set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}] -#set_property -dict {LOC F34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}] -set_property -dict {LOC M29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] -set_property -dict {LOC D36 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] - -set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] -set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] -set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] -set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] -set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] -set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] -set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] -set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] -set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] -set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] -set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] -set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] -set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] -set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] -set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] -set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] -set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] -set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] -set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] -set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] -set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] -set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] -set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] -set_property -dict {LOC F29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] -set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] -set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] -set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] -set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] -set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] -set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] -set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] -set_property -dict {LOC C28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] -set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] -set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] -set_property -dict {LOC D38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] -set_property -dict {LOC E35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] -set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] -set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] -set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] -set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] -set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] -set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] -set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] -set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] -set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] -set_property -dict {LOC M32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] -set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] -set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] -set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] -set_property -dict {LOC K35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] -set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] -set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] -set_property -dict {LOC J34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] -set_property -dict {LOC J33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] -set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] -set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] -set_property -dict {LOC H36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] -set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] -set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] -set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] -set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] -set_property -dict {LOC K38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] -set_property -dict {LOC G35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] -set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] -set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] -set_property -dict {LOC B37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] -set_property -dict {LOC A37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] -set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] -set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] -set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] -set_property -dict {LOC A40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] -set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] -set_property -dict {LOC N26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] -set_property -dict {LOC M26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] -set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] -set_property -dict {LOC P28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] -set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] -set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] -set_property -dict {LOC M27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] -set_property -dict {LOC L28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] -set_property -dict {LOC D29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] -set_property -dict {LOC D30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] -set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] -set_property -dict {LOC H27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] -set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] -set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] -set_property -dict {LOC C29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] -set_property -dict {LOC B29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] -set_property -dict {LOC E39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] -set_property -dict {LOC E40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] -set_property -dict {LOC G37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] -set_property -dict {LOC F37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] -set_property -dict {LOC N31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}] -set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}] -set_property -dict {LOC T30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}] -set_property -dict {LOC R31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}] -set_property -dict {LOC L35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}] -set_property -dict {LOC L36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}] -set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}] -set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}] -set_property -dict {LOC J38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}] -set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}] -set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}] -set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}] -set_property -dict {LOC B39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}] -set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}] -set_property -dict {LOC C37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}] -set_property -dict {LOC C38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}] - -# DDR4 C3 -set_property -dict {LOC K15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}] -set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}] -set_property -dict {LOC F14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}] -set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}] -set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}] -set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}] -set_property -dict {LOC B14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}] -set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}] -set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}] -set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}] -set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}] -set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}] -set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}] -set_property -dict {LOC K16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}] -set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}] -set_property -dict {LOC E15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}] -set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}] -set_property -dict {LOC J15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}] -set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}] -set_property -dict {LOC D13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}] -set_property -dict {LOC J13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}] -set_property -dict {LOC L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[0]}] -set_property -dict {LOC L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[0]}] -#set_property -dict {LOC G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[1]}] -#set_property -dict {LOC G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[1]}] -set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}] -#set_property -dict {LOC L15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}] -set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}] -#set_property -dict {LOC D16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}] -#set_property -dict {LOC M14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}] -#set_property -dict {LOC M13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}] -set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}] -set_property -dict {LOC C16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}] -#set_property -dict {LOC E16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}] -set_property -dict {LOC J14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}] -set_property -dict {LOC D21 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}] - -set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}] -set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}] -set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}] -set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}] -set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}] -set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}] -set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}] -set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}] -set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}] -set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}] -set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}] -set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}] -set_property -dict {LOC L24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}] -set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}] -set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}] -set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}] -set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}] -set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}] -set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}] -set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}] -set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}] -set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}] -set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}] -set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}] -set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}] -set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}] -set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}] -set_property -dict {LOC R17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}] -set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}] -set_property -dict {LOC T20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}] -set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}] -set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}] -set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}] -set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}] -set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}] -set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}] -set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}] -set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}] -set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}] -set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}] -set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}] -set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}] -set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}] -set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}] -set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}] -set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}] -set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}] -set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}] -set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}] -set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}] -set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}] -set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}] -set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}] -set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}] -set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}] -set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}] -set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}] -set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}] -set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}] -set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}] -set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}] -set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}] -set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}] -set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}] -set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}] -set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}] -set_property -dict {LOC N13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}] -set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}] -set_property -dict {LOC T15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}] -set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}] -set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}] -set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}] -set_property -dict {LOC T22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}] -set_property -dict {LOC R22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}] -set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}] -set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}] -set_property -dict {LOC J21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}] -set_property -dict {LOC H21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}] -set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}] -set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}] -set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}] -set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}] -set_property -dict {LOC K18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}] -set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}] -set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}] -set_property -dict {LOC P18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}] -set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}] -set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}] -set_property -dict {LOC A25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}] -set_property -dict {LOC A24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}] -set_property -dict {LOC D24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}] -set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}] -set_property -dict {LOC C17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}] -set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}] -set_property -dict {LOC B19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}] -set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}] -set_property -dict {LOC F18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}] -set_property -dict {LOC F17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}] -set_property -dict {LOC H19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}] -set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}] -set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}] -set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}] -set_property -dict {LOC H23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}] -set_property -dict {LOC H22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}] -set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}] -set_property -dict {LOC P15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}] -set_property -dict {LOC T13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}] -set_property -dict {LOC R13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}] diff --git a/fpga/mqnic/AU250/fpga_25g/ip/cms.tcl b/fpga/mqnic/AU250/fpga_25g/ip/cms.tcl deleted file mode 100644 index 22126d4d6..000000000 --- a/fpga/mqnic/AU250/fpga_25g/ip/cms.tcl +++ /dev/null @@ -1,16 +0,0 @@ - -# create block design -create_bd_design "cms" - -# create CMS IP -set cms_block [create_bd_cell -type ip -vlnv xilinx.com:ip:cms_subsystem cms_subsystem_0] -make_bd_pins_external $cms_block -make_bd_intf_pins_external $cms_block - -# assign addresses -assign_bd_address -target_address_space /s_axi_ctrl_0 [get_bd_addr_segs $cms_block/s_axi_ctrl/Mem0] -force - -# save block design and create HDL wrapper -save_bd_design [current_bd_design] -add_files -norecurse [make_wrapper -files [get_files [get_property FILE_NAME [current_bd_design]]] -top] -close_bd_design [current_bd_design] diff --git a/fpga/mqnic/AU250/fpga_25g/ip/ddr4_0.tcl b/fpga/mqnic/AU250/fpga_25g/ip/ddr4_0.tcl deleted file mode 100644 index 27252f502..000000000 --- a/fpga/mqnic/AU250/fpga_25g/ip/ddr4_0.tcl +++ /dev/null @@ -1,17 +0,0 @@ - -create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 - -set_property -dict [list \ - CONFIG.C0.DDR4_AxiSelection {true} \ - CONFIG.C0.DDR4_AxiDataWidth {512} \ - CONFIG.C0.DDR4_AxiIDWidth {8} \ - CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ - CONFIG.C0.DDR4_TimePeriod {833} \ - CONFIG.C0.DDR4_InputClockPeriod {3332} \ - CONFIG.C0.DDR4_MemoryType {RDIMMs} \ - CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ - CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ - CONFIG.C0.DDR4_CasLatency {17} \ - CONFIG.C0.DDR4_CasWriteLatency {12} \ - CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} -] [get_ips ddr4_0] diff --git a/fpga/mqnic/AU250/fpga_25g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/AU250/fpga_25g/ip/eth_xcvr_gty.tcl deleted file mode 100644 index e1dda063f..000000000 --- a/fpga/mqnic/AU250/fpga_25g/ip/eth_xcvr_gty.tcl +++ /dev/null @@ -1,103 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2022-2023 The Regents of the University of California - -set base_name {eth_xcvr_gty} - -set preset {GTY-10GBASE-R} - -set freerun_freq {125} -set line_rate {25.78125} -set sec_line_rate {10.3125} -set refclk_freq {161.1328125} -set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set user_data_width {64} -set int_data_width $user_data_width -set rx_eq_mode {DFE} -set extra_ports [list] -set extra_pll_ports [list] -# DRP connections -lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out -lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out -# PLL reset and power down -lappend extra_pll_ports qpll0reset_in qpll1reset_in -lappend extra_pll_ports qpll0pd_in qpll1pd_in -# PLL clocking -lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out -lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out -# channel reset -lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out -lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out -# channel power down -lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in -# channel clock selection -lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in -# channel polarity -lappend extra_ports txpolarity_in rxpolarity_in -# channel TX driver -lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in -# channel CDR -lappend extra_ports rxcdrlock_out rxcdrhold_in -# channel EQ -lappend extra_ports rxlpmen_in -# channel digital monitor -lappend extra_ports dmonitorout_out -# channel PRBS -lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out -# channel eye scan -lappend extra_ports eyescandataerror_out -# channel loopback -lappend extra_ports loopback_in - -set config [dict create] - -dict set config TX_LINE_RATE $line_rate -dict set config TX_REFCLK_FREQUENCY $refclk_freq -dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config TX_USER_DATA_WIDTH $user_data_width -dict set config TX_INT_DATA_WIDTH $int_data_width -dict set config RX_LINE_RATE $line_rate -dict set config RX_REFCLK_FREQUENCY $refclk_freq -dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config RX_USER_DATA_WIDTH $user_data_width -dict set config RX_INT_DATA_WIDTH $int_data_width -dict set config RX_EQ_MODE $rx_eq_mode -if {$sec_line_rate != 0} { - dict set config SECONDARY_QPLL_ENABLE true - dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn - dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq -} else { - dict set config SECONDARY_QPLL_ENABLE false -} -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} -dict set config LOCATE_TX_USER_CLOCKING {CORE} -dict set config LOCATE_RX_USER_CLOCKING {CORE} -dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} -dict set config FREERUN_FREQUENCY $freerun_freq -dict set config DISABLE_LOC_XDC {1} - -proc create_gtwizard_ip {name preset config} { - create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name - set ip [get_ips $name] - set_property CONFIG.preset $preset $ip - set config_list {} - dict for {name value} $config { - lappend config_list "CONFIG.${name}" $value - } - set_property -dict $config_list $ip -} - -# variant with channel and common -dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports] -dict set config LOCATE_COMMON {CORE} - -create_gtwizard_ip "${base_name}_full" $preset $config - -# variant with channel only -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {EXAMPLE_DESIGN} - -create_gtwizard_ip "${base_name}_channel" $preset $config diff --git a/fpga/mqnic/AU250/fpga_25g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/AU250/fpga_25g/ip/pcie4_uscale_plus_0.tcl deleted file mode 100644 index 8d998b95c..000000000 --- a/fpga/mqnic/AU250/fpga_25g/ip/pcie4_uscale_plus_0.tcl +++ /dev/null @@ -1,34 +0,0 @@ - -create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 - -set_property -dict [list \ - CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ - CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ - CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \ - CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \ - CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \ - CONFIG.axisten_if_enable_client_tag {true} \ - CONFIG.axisten_if_width {512_bit} \ - CONFIG.extended_tag_field {true} \ - CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ - CONFIG.axisten_freq {250} \ - CONFIG.PF0_Use_Class_Code_Lookup_Assistant {false} \ - CONFIG.PF0_CLASS_CODE {020000} \ - CONFIG.PF0_DEVICE_ID {1001} \ - CONFIG.PF0_SUBSYSTEM_ID {90fa} \ - CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ - CONFIG.pf0_bar0_64bit {true} \ - CONFIG.pf0_bar0_prefetchable {true} \ - CONFIG.pf0_bar0_scale {Megabytes} \ - CONFIG.pf0_bar0_size {16} \ - CONFIG.pf0_msi_enabled {false} \ - CONFIG.pf0_msix_enabled {true} \ - CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ - CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \ - CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \ - CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \ - CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \ - CONFIG.MSI_X_OPTIONS {MSI-X_External} \ - CONFIG.vendor_id {1234} \ - CONFIG.mode_selection {Advanced} \ -] [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/AU250/fpga_25g/lib b/fpga/mqnic/AU250/fpga_25g/lib deleted file mode 120000 index 9512b3d5e..000000000 --- a/fpga/mqnic/AU250/fpga_25g/lib +++ /dev/null @@ -1 +0,0 @@ -../../../lib/ \ No newline at end of file diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/common b/fpga/mqnic/AU250/fpga_25g/rtl/common deleted file mode 120000 index 449c9409c..000000000 --- a/fpga/mqnic/AU250/fpga_25g/rtl/common +++ /dev/null @@ -1 +0,0 @@ -../../../../common/rtl/ \ No newline at end of file diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/debounce_switch.v b/fpga/mqnic/AU250/fpga_25g/rtl/debounce_switch.v deleted file mode 100644 index 8e93a50c4..000000000 --- a/fpga/mqnic/AU250/fpga_25g/rtl/debounce_switch.v +++ /dev/null @@ -1,93 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog-2001 - -`resetall -`timescale 1 ns / 1 ps -`default_nettype none - -/* - * Synchronizes switch and button inputs with a slow sampled shift register - */ -module debounce_switch #( - parameter WIDTH=1, // width of the input and output signals - parameter N=3, // length of shift register - parameter RATE=125000 // clock division factor -)( - input wire clk, - input wire rst, - input wire [WIDTH-1:0] in, - output wire [WIDTH-1:0] out -); - -reg [23:0] cnt_reg = 24'd0; - -reg [N-1:0] debounce_reg[WIDTH-1:0]; - -reg [WIDTH-1:0] state; - -/* - * The synchronized output is the state register - */ -assign out = state; - -integer k; - -always @(posedge clk or posedge rst) begin - if (rst) begin - cnt_reg <= 0; - state <= 0; - - for (k = 0; k < WIDTH; k = k + 1) begin - debounce_reg[k] <= 0; - end - end else begin - if (cnt_reg < RATE) begin - cnt_reg <= cnt_reg + 24'd1; - end else begin - cnt_reg <= 24'd0; - end - - if (cnt_reg == 24'd0) begin - for (k = 0; k < WIDTH; k = k + 1) begin - debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]}; - end - end - - for (k = 0; k < WIDTH; k = k + 1) begin - if (|debounce_reg[k] == 0) begin - state[k] <= 0; - end else if (&debounce_reg[k] == 1) begin - state[k] <= 1; - end else begin - state[k] <= state[k]; - end - end - end -end - -endmodule - -`resetall diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v deleted file mode 100644 index 7271c2d0c..000000000 --- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v +++ /dev/null @@ -1,2550 +0,0 @@ -// SPDX-License-Identifier: BSD-2-Clause-Views -/* - * Copyright (c) 2019-2023 The Regents of the University of California - */ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA top-level module - */ -module fpga # -( - // FW and board IDs - parameter FPGA_ID = 32'h4B57093, - parameter FW_ID = 32'h00000000, - parameter FW_VER = 32'h00_00_01_00, - parameter BOARD_ID = 32'h10ee_90fa, - parameter BOARD_VER = 32'h01_00_00_00, - parameter BUILD_DATE = 32'd602976000, - parameter GIT_HASH = 32'hdce357bf, - parameter RELEASE_INFO = 32'h00000000, - - // Board configuration - parameter TDMA_BER_ENABLE = 0, - - // Structural configuration - parameter IF_COUNT = 2, - parameter PORTS_PER_IF = 1, - parameter SCHED_PER_IF = PORTS_PER_IF, - parameter PORT_MASK = 0, - - // Clock configuration - parameter CLK_PERIOD_NS_NUM = 4, - parameter CLK_PERIOD_NS_DENOM = 1, - - // PTP configuration - parameter PTP_CLOCK_PIPELINE = 0, - parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_PORT_CDC_PIPELINE = 0, - parameter PTP_PEROUT_ENABLE = 0, - parameter PTP_PEROUT_COUNT = 1, - - // Queue manager configuration - parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_QUEUE_OP_TABLE_SIZE = 32, - parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter CQ_OP_TABLE_SIZE = 32, - parameter EQN_WIDTH = 5, - parameter TX_QUEUE_INDEX_WIDTH = 13, - parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, - parameter EQ_PIPELINE = 3, - parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), - parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), - - // TX and RX engine configuration - parameter TX_DESC_TABLE_SIZE = 32, - parameter RX_DESC_TABLE_SIZE = 32, - parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, - - // Scheduler configuration - parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, - parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, - parameter TDMA_INDEX_WIDTH = 6, - - // Interface configuration - parameter PTP_TS_ENABLE = 1, - parameter TX_CPL_FIFO_DEPTH = 32, - parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_HASH_ENABLE = 1, - parameter RX_CHECKSUM_ENABLE = 1, - parameter PFC_ENABLE = 1, - parameter LFC_ENABLE = PFC_ENABLE, - parameter ENABLE_PADDING = 1, - parameter ENABLE_DIC = 1, - parameter MIN_FRAME_LENGTH = 64, - parameter TX_FIFO_DEPTH = 32768, - parameter RX_FIFO_DEPTH = 32768, - parameter MAX_TX_SIZE = 9214, - parameter MAX_RX_SIZE = 9214, - parameter TX_RAM_SIZE = 32768, - parameter RX_RAM_SIZE = 32768, - - // RAM configuration - parameter DDR_CH = 4, - parameter DDR_ENABLE = 0, - parameter AXI_DDR_DATA_WIDTH = 512, - parameter AXI_DDR_ADDR_WIDTH = 34, - parameter AXI_DDR_ID_WIDTH = 8, - parameter AXI_DDR_MAX_BURST_LEN = 256, - parameter AXI_DDR_NARROW_BURST = 0, - - // Application block configuration - parameter APP_ID = 32'h00000000, - parameter APP_ENABLE = 0, - parameter APP_CTRL_ENABLE = 1, - parameter APP_DMA_ENABLE = 1, - parameter APP_AXIS_DIRECT_ENABLE = 1, - parameter APP_AXIS_SYNC_ENABLE = 1, - parameter APP_AXIS_IF_ENABLE = 1, - parameter APP_STAT_ENABLE = 1, - - // DMA interface configuration - parameter DMA_IMM_ENABLE = 0, - parameter DMA_IMM_WIDTH = 32, - parameter DMA_LEN_WIDTH = 16, - parameter DMA_TAG_WIDTH = 16, - parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), - parameter RAM_PIPELINE = 2, - - // PCIe interface configuration - parameter AXIS_PCIE_DATA_WIDTH = 512, - parameter PF_COUNT = 1, - parameter VF_COUNT = 0, - - // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EQN_WIDTH, - - // AXI lite interface configuration (control) - parameter AXIL_CTRL_DATA_WIDTH = 32, - parameter AXIL_CTRL_ADDR_WIDTH = 24, - - // AXI lite interface configuration (application control) - parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, - parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, - - // Ethernet interface configuration - parameter AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE = 1, - parameter AXIS_ETH_TX_PIPELINE = 4, - parameter AXIS_ETH_TX_FIFO_PIPELINE = 4, - parameter AXIS_ETH_TX_TS_PIPELINE = 4, - parameter AXIS_ETH_RX_PIPELINE = 4, - parameter AXIS_ETH_RX_FIFO_PIPELINE = 4, - - // Statistics counter subsystem - parameter STAT_ENABLE = 1, - parameter STAT_DMA_ENABLE = 1, - parameter STAT_PCIE_ENABLE = 1, - parameter STAT_INC_WIDTH = 24, - parameter STAT_ID_WIDTH = 12 -) -( - /* - * Clock and reset - */ - input wire clk_300mhz_0_p, - input wire clk_300mhz_0_n, - input wire clk_300mhz_1_p, - input wire clk_300mhz_1_n, - input wire clk_300mhz_2_p, - input wire clk_300mhz_2_n, - input wire clk_300mhz_3_p, - input wire clk_300mhz_3_n, - - /* - * GPIO - */ - input wire [3:0] sw, - output wire [2:0] led, - input wire [3:0] msp_gpio, - output wire msp_uart_txd, - input wire msp_uart_rxd, - - /* - * I2C for board management - */ - inout wire i2c_scl, - inout wire i2c_sda, - - /* - * PCI express - */ - input wire [15:0] pcie_rx_p, - input wire [15:0] pcie_rx_n, - output wire [15:0] pcie_tx_p, - output wire [15:0] pcie_tx_n, - input wire pcie_refclk_p, - input wire pcie_refclk_n, - input wire pcie_reset_n, - - /* - * Ethernet: QSFP28 - */ - output wire [3:0] qsfp0_tx_p, - output wire [3:0] qsfp0_tx_n, - input wire [3:0] qsfp0_rx_p, - input wire [3:0] qsfp0_rx_n, - // input wire qsfp0_mgt_refclk_0_p, - // input wire qsfp0_mgt_refclk_0_n, - input wire qsfp0_mgt_refclk_1_p, - input wire qsfp0_mgt_refclk_1_n, - output wire qsfp0_modsell, - output wire qsfp0_resetl, - input wire qsfp0_modprsl, - input wire qsfp0_intl, - output wire qsfp0_lpmode, - output wire qsfp0_refclk_reset, - output wire [1:0] qsfp0_fs, - - output wire [3:0] qsfp1_tx_p, - output wire [3:0] qsfp1_tx_n, - input wire [3:0] qsfp1_rx_p, - input wire [3:0] qsfp1_rx_n, - // input wire qsfp1_mgt_refclk_0_p, - // input wire qsfp1_mgt_refclk_0_n, - input wire qsfp1_mgt_refclk_1_p, - input wire qsfp1_mgt_refclk_1_n, - output wire qsfp1_modsell, - output wire qsfp1_resetl, - input wire qsfp1_modprsl, - input wire qsfp1_intl, - output wire qsfp1_lpmode, - output wire qsfp1_refclk_reset, - output wire [1:0] qsfp1_fs, - - /* - * DDR4 - */ - output wire [16:0] ddr4_c0_adr, - output wire [1:0] ddr4_c0_ba, - output wire [1:0] ddr4_c0_bg, - output wire [0:0] ddr4_c0_ck_t, - output wire [0:0] ddr4_c0_ck_c, - output wire [0:0] ddr4_c0_cke, - output wire [0:0] ddr4_c0_cs_n, - output wire ddr4_c0_act_n, - output wire [0:0] ddr4_c0_odt, - output wire ddr4_c0_par, - output wire ddr4_c0_reset_n, - inout wire [71:0] ddr4_c0_dq, - inout wire [17:0] ddr4_c0_dqs_t, - inout wire [17:0] ddr4_c0_dqs_c, - - output wire [16:0] ddr4_c1_adr, - output wire [1:0] ddr4_c1_ba, - output wire [1:0] ddr4_c1_bg, - output wire [0:0] ddr4_c1_ck_t, - output wire [0:0] ddr4_c1_ck_c, - output wire [0:0] ddr4_c1_cke, - output wire [0:0] ddr4_c1_cs_n, - output wire ddr4_c1_act_n, - output wire [0:0] ddr4_c1_odt, - output wire ddr4_c1_par, - output wire ddr4_c1_reset_n, - inout wire [71:0] ddr4_c1_dq, - inout wire [17:0] ddr4_c1_dqs_t, - inout wire [17:0] ddr4_c1_dqs_c, - - output wire [16:0] ddr4_c2_adr, - output wire [1:0] ddr4_c2_ba, - output wire [1:0] ddr4_c2_bg, - output wire [0:0] ddr4_c2_ck_t, - output wire [0:0] ddr4_c2_ck_c, - output wire [0:0] ddr4_c2_cke, - output wire [0:0] ddr4_c2_cs_n, - output wire ddr4_c2_act_n, - output wire [0:0] ddr4_c2_odt, - output wire ddr4_c2_par, - output wire ddr4_c2_reset_n, - inout wire [71:0] ddr4_c2_dq, - inout wire [17:0] ddr4_c2_dqs_t, - inout wire [17:0] ddr4_c2_dqs_c, - - output wire [16:0] ddr4_c3_adr, - output wire [1:0] ddr4_c3_ba, - output wire [1:0] ddr4_c3_bg, - output wire [0:0] ddr4_c3_ck_t, - output wire [0:0] ddr4_c3_ck_c, - output wire [0:0] ddr4_c3_cke, - output wire [0:0] ddr4_c3_cs_n, - output wire ddr4_c3_act_n, - output wire [0:0] ddr4_c3_odt, - output wire ddr4_c3_par, - output wire ddr4_c3_reset_n, - inout wire [71:0] ddr4_c3_dq, - inout wire [17:0] ddr4_c3_dqs_t, - inout wire [17:0] ddr4_c3_dqs_c -); - -// PTP configuration -parameter PTP_CLK_PERIOD_NS_NUM = 1024; -parameter PTP_CLK_PERIOD_NS_DENOM = 165; -parameter PTP_TS_WIDTH = 96; -parameter IF_PTP_PERIOD_NS = 6'h6; -parameter IF_PTP_PERIOD_FNS = 16'h6666; - -// Interface configuration -parameter TX_TAG_WIDTH = 16; - -// RAM configuration -parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); - -// PCIe interface configuration -parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); -parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161; -parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137; -parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183; -parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81; -parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256; -parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; -parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; -parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; -parameter RQ_SEQ_NUM_WIDTH = 6; -parameter PCIE_TAG_COUNT = 256; - -// Ethernet interface configuration -parameter XGMII_DATA_WIDTH = 64; -parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; -parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH; -parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; -parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE ? 2 : 1); -parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1; -parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; - -// Clock and reset -wire pcie_user_clk; -wire pcie_user_reset; - -wire cfgmclk_int; - -wire clk_161mhz_ref_int; - -wire clk_50mhz_mmcm_out; -wire clk_125mhz_mmcm_out; - -// Internal 50 MHz clock -wire clk_50mhz_int; -wire rst_50mhz_int; - -// Internal 125 MHz clock -wire clk_125mhz_int; -wire rst_125mhz_int; - -wire mmcm_rst; -wire mmcm_locked; -wire mmcm_clkfb; - -// MMCM instance -// 161.13 MHz in, 50 MHz + 125 MHz out -// PFD range: 10 MHz to 500 MHz -// VCO range: 800 MHz to 1600 MHz -// M = 128, D = 15 sets Fvco = 1375 MHz (in range) -// Divide by 27.5 to get output frequency of 50 MHz -// Divide by 11 to get output frequency of 125 MHz -MMCME4_BASE #( - .BANDWIDTH("OPTIMIZED"), - .CLKOUT0_DIVIDE_F(27.5), - .CLKOUT0_DUTY_CYCLE(0.5), - .CLKOUT0_PHASE(0), - .CLKOUT1_DIVIDE(11), - .CLKOUT1_DUTY_CYCLE(0.5), - .CLKOUT1_PHASE(0), - .CLKOUT2_DIVIDE(1), - .CLKOUT2_DUTY_CYCLE(0.5), - .CLKOUT2_PHASE(0), - .CLKOUT3_DIVIDE(1), - .CLKOUT3_DUTY_CYCLE(0.5), - .CLKOUT3_PHASE(0), - .CLKOUT4_DIVIDE(1), - .CLKOUT4_DUTY_CYCLE(0.5), - .CLKOUT4_PHASE(0), - .CLKOUT5_DIVIDE(1), - .CLKOUT5_DUTY_CYCLE(0.5), - .CLKOUT5_PHASE(0), - .CLKOUT6_DIVIDE(1), - .CLKOUT6_DUTY_CYCLE(0.5), - .CLKOUT6_PHASE(0), - .CLKFBOUT_MULT_F(128), - .CLKFBOUT_PHASE(0), - .DIVCLK_DIVIDE(15), - .REF_JITTER1(0.010), - .CLKIN1_PERIOD(6.206), - .STARTUP_WAIT("FALSE"), - .CLKOUT4_CASCADE("FALSE") -) -clk_mmcm_inst ( - .CLKIN1(clk_161mhz_ref_int), - .CLKFBIN(mmcm_clkfb), - .RST(mmcm_rst), - .PWRDWN(1'b0), - .CLKOUT0(clk_50mhz_mmcm_out), - .CLKOUT0B(), - .CLKOUT1(clk_125mhz_mmcm_out), - .CLKOUT1B(), - .CLKOUT2(), - .CLKOUT2B(), - .CLKOUT3(), - .CLKOUT3B(), - .CLKOUT4(), - .CLKOUT5(), - .CLKOUT6(), - .CLKFBOUT(mmcm_clkfb), - .CLKFBOUTB(), - .LOCKED(mmcm_locked) -); - -BUFG -clk_50mhz_bufg_inst ( - .I(clk_50mhz_mmcm_out), - .O(clk_50mhz_int) -); - -BUFG -clk_125mhz_bufg_inst ( - .I(clk_125mhz_mmcm_out), - .O(clk_125mhz_int) -); - -sync_reset #( - .N(4) -) -sync_reset_50mhz_inst ( - .clk(clk_50mhz_int), - .rst(~mmcm_locked), - .out(rst_50mhz_int) -); - -sync_reset #( - .N(4) -) -sync_reset_125mhz_inst ( - .clk(clk_125mhz_int), - .rst(~mmcm_locked), - .out(rst_125mhz_int) -); - -// GPIO -wire btnu_int; -wire btnl_int; -wire btnd_int; -wire btnr_int; -wire btnc_int; -wire [3:0] sw_int; -wire qsfp0_modprsl_int; -wire qsfp1_modprsl_int; -wire qsfp0_intl_int; -wire qsfp1_intl_int; -wire i2c_scl_i; -wire i2c_scl_o; -wire i2c_scl_t; -wire i2c_sda_i; -wire i2c_sda_o; -wire i2c_sda_t; - -reg i2c_scl_o_reg; -reg i2c_scl_t_reg; -reg i2c_sda_o_reg; -reg i2c_sda_t_reg; - -always @(posedge pcie_user_clk) begin - i2c_scl_o_reg <= i2c_scl_o; - i2c_scl_t_reg <= i2c_scl_t; - i2c_sda_o_reg <= i2c_sda_o; - i2c_sda_t_reg <= i2c_sda_t; -end - -debounce_switch #( - .WIDTH(4), - .N(4), - .RATE(250000) -) -debounce_switch_inst ( - .clk(pcie_user_clk), - .rst(pcie_user_reset), - .in({sw}), - .out({sw_int}) -); - -sync_signal #( - .WIDTH(6), - .N(2) -) -sync_signal_inst ( - .clk(pcie_user_clk), - .in({qsfp0_modprsl, qsfp1_modprsl, qsfp0_intl, qsfp1_intl, - i2c_scl, i2c_sda}), - .out({qsfp0_modprsl_int, qsfp1_modprsl_int, qsfp0_intl_int, qsfp1_intl_int, - i2c_scl_i, i2c_sda_i}) -); - -assign i2c_scl = i2c_scl_t_reg ? 1'bz : i2c_scl_o_reg; -assign i2c_sda = i2c_sda_t_reg ? 1'bz : i2c_sda_o_reg; - -// Flash -wire qspi_clk_int; -wire [3:0] qspi_dq_int; -wire [3:0] qspi_dq_i_int; -wire [3:0] qspi_dq_o_int; -wire [3:0] qspi_dq_oe_int; -wire qspi_cs_int; - -reg qspi_clk_reg; -reg [3:0] qspi_dq_o_reg; -reg [3:0] qspi_dq_oe_reg; -reg qspi_cs_reg; - -always @(posedge pcie_user_clk) begin - qspi_clk_reg <= qspi_clk_int; - qspi_dq_o_reg <= qspi_dq_o_int; - qspi_dq_oe_reg <= qspi_dq_oe_int; - qspi_cs_reg <= qspi_cs_int; -end - -sync_signal #( - .WIDTH(4), - .N(2) -) -flash_sync_signal_inst ( - .clk(pcie_user_clk), - .in({qspi_dq_int}), - .out({qspi_dq_i_int}) -); - -// startupe3 instance -wire cfgmclk; - -STARTUPE3 -startupe3_inst ( - .CFGCLK(), - .CFGMCLK(cfgmclk), - .DI(qspi_dq_int), - .DO(qspi_dq_o_reg), - .DTS(~qspi_dq_oe_reg), - .EOS(), - .FCSBO(qspi_cs_reg), - .FCSBTS(1'b0), - .GSR(1'b0), - .GTS(1'b0), - .KEYCLEARB(1'b1), - .PACK(1'b0), - .PREQ(), - .USRCCLKO(qspi_clk_reg), - .USRCCLKTS(1'b0), - .USRDONEO(1'b0), - .USRDONETS(1'b1) -); - -BUFG -cfgmclk_bufg_inst ( - .I(cfgmclk), - .O(cfgmclk_int) -); - -// FPGA boot -wire fpga_boot; - -reg fpga_boot_sync_reg_0 = 1'b0; -reg fpga_boot_sync_reg_1 = 1'b0; -reg fpga_boot_sync_reg_2 = 1'b0; - -wire icap_avail; -reg [2:0] icap_state = 0; -reg icap_csib_reg = 1'b1; -reg icap_rdwrb_reg = 1'b0; -reg [31:0] icap_di_reg = 32'hffffffff; - -wire [31:0] icap_di_rev; - -assign icap_di_rev[ 7] = icap_di_reg[ 0]; -assign icap_di_rev[ 6] = icap_di_reg[ 1]; -assign icap_di_rev[ 5] = icap_di_reg[ 2]; -assign icap_di_rev[ 4] = icap_di_reg[ 3]; -assign icap_di_rev[ 3] = icap_di_reg[ 4]; -assign icap_di_rev[ 2] = icap_di_reg[ 5]; -assign icap_di_rev[ 1] = icap_di_reg[ 6]; -assign icap_di_rev[ 0] = icap_di_reg[ 7]; - -assign icap_di_rev[15] = icap_di_reg[ 8]; -assign icap_di_rev[14] = icap_di_reg[ 9]; -assign icap_di_rev[13] = icap_di_reg[10]; -assign icap_di_rev[12] = icap_di_reg[11]; -assign icap_di_rev[11] = icap_di_reg[12]; -assign icap_di_rev[10] = icap_di_reg[13]; -assign icap_di_rev[ 9] = icap_di_reg[14]; -assign icap_di_rev[ 8] = icap_di_reg[15]; - -assign icap_di_rev[23] = icap_di_reg[16]; -assign icap_di_rev[22] = icap_di_reg[17]; -assign icap_di_rev[21] = icap_di_reg[18]; -assign icap_di_rev[20] = icap_di_reg[19]; -assign icap_di_rev[19] = icap_di_reg[20]; -assign icap_di_rev[18] = icap_di_reg[21]; -assign icap_di_rev[17] = icap_di_reg[22]; -assign icap_di_rev[16] = icap_di_reg[23]; - -assign icap_di_rev[31] = icap_di_reg[24]; -assign icap_di_rev[30] = icap_di_reg[25]; -assign icap_di_rev[29] = icap_di_reg[26]; -assign icap_di_rev[28] = icap_di_reg[27]; -assign icap_di_rev[27] = icap_di_reg[28]; -assign icap_di_rev[26] = icap_di_reg[29]; -assign icap_di_rev[25] = icap_di_reg[30]; -assign icap_di_rev[24] = icap_di_reg[31]; - -always @(posedge clk_125mhz_int) begin - case (icap_state) - 0: begin - icap_state <= 0; - icap_csib_reg <= 1'b1; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hffffffff; // dummy word - - if (fpga_boot_sync_reg_2 && icap_avail) begin - icap_state <= 1; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hffffffff; // dummy word - end - end - 1: begin - icap_state <= 2; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hAA995566; // sync word - end - 2: begin - icap_state <= 3; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h20000000; // type 1 noop - end - 3: begin - icap_state <= 4; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h30008001; // write 1 word to CMD - end - 4: begin - icap_state <= 5; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h0000000F; // IPROG - end - 5: begin - icap_state <= 0; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h20000000; // type 1 noop - end - endcase - - fpga_boot_sync_reg_0 <= fpga_boot; - fpga_boot_sync_reg_1 <= fpga_boot_sync_reg_0; - fpga_boot_sync_reg_2 <= fpga_boot_sync_reg_1; -end - -ICAPE3 -icape3_inst ( - .AVAIL(icap_avail), - .CLK(clk_125mhz_int), - .CSIB(icap_csib_reg), - .I(icap_di_rev), - .O(), - .PRDONE(), - .PRERROR(), - .RDWRB(icap_rdwrb_reg) -); - -// BMC -wire axil_cms_clk; -wire axil_cms_rst; -wire [17:0] axil_cms_awaddr; -wire [2:0] axil_cms_awprot; -wire axil_cms_awvalid; -wire axil_cms_awready; -wire [31:0] axil_cms_wdata; -wire [3:0] axil_cms_wstrb; -wire axil_cms_wvalid; -wire axil_cms_wready; -wire [1:0] axil_cms_bresp; -wire axil_cms_bvalid; -wire axil_cms_bready; -wire [17:0] axil_cms_araddr; -wire [2:0] axil_cms_arprot; -wire axil_cms_arvalid; -wire axil_cms_arready; -wire [31:0] axil_cms_rdata; -wire [1:0] axil_cms_rresp; -wire axil_cms_rvalid; -wire axil_cms_rready; - -wire [17:0] axil_cms_awaddr_int; -wire [2:0] axil_cms_awprot_int; -wire axil_cms_awvalid_int; -wire axil_cms_awready_int; -wire [31:0] axil_cms_wdata_int; -wire [3:0] axil_cms_wstrb_int; -wire axil_cms_wvalid_int; -wire axil_cms_wready_int; -wire [1:0] axil_cms_bresp_int; -wire axil_cms_bvalid_int; -wire axil_cms_bready_int; -wire [17:0] axil_cms_araddr_int; -wire [2:0] axil_cms_arprot_int; -wire axil_cms_arvalid_int; -wire axil_cms_arready_int; -wire [31:0] axil_cms_rdata_int; -wire [1:0] axil_cms_rresp_int; -wire axil_cms_rvalid_int; -wire axil_cms_rready_int; - -axil_cdc #( - .DATA_WIDTH(32), - .ADDR_WIDTH(18) -) -cms_axil_cdc_inst ( - .s_clk(axil_cms_clk), - .s_rst(axil_cms_rst), - .s_axil_awaddr(axil_cms_awaddr), - .s_axil_awprot(axil_cms_awprot), - .s_axil_awvalid(axil_cms_awvalid), - .s_axil_awready(axil_cms_awready), - .s_axil_wdata(axil_cms_wdata), - .s_axil_wstrb(axil_cms_wstrb), - .s_axil_wvalid(axil_cms_wvalid), - .s_axil_wready(axil_cms_wready), - .s_axil_bresp(axil_cms_bresp), - .s_axil_bvalid(axil_cms_bvalid), - .s_axil_bready(axil_cms_bready), - .s_axil_araddr(axil_cms_araddr), - .s_axil_arprot(axil_cms_arprot), - .s_axil_arvalid(axil_cms_arvalid), - .s_axil_arready(axil_cms_arready), - .s_axil_rdata(axil_cms_rdata), - .s_axil_rresp(axil_cms_rresp), - .s_axil_rvalid(axil_cms_rvalid), - .s_axil_rready(axil_cms_rready), - .m_clk(clk_50mhz_int), - .m_rst(rst_50mhz_int), - .m_axil_awaddr(axil_cms_awaddr_int), - .m_axil_awprot(axil_cms_awprot_int), - .m_axil_awvalid(axil_cms_awvalid_int), - .m_axil_awready(axil_cms_awready_int), - .m_axil_wdata(axil_cms_wdata_int), - .m_axil_wstrb(axil_cms_wstrb_int), - .m_axil_wvalid(axil_cms_wvalid_int), - .m_axil_wready(axil_cms_wready_int), - .m_axil_bresp(axil_cms_bresp_int), - .m_axil_bvalid(axil_cms_bvalid_int), - .m_axil_bready(axil_cms_bready_int), - .m_axil_araddr(axil_cms_araddr_int), - .m_axil_arprot(axil_cms_arprot_int), - .m_axil_arvalid(axil_cms_arvalid_int), - .m_axil_arready(axil_cms_arready_int), - .m_axil_rdata(axil_cms_rdata_int), - .m_axil_rresp(axil_cms_rresp_int), - .m_axil_rvalid(axil_cms_rvalid_int), - .m_axil_rready(axil_cms_rready_int) -); - -cms_wrapper -cms_inst ( - .aclk_ctrl_0(clk_50mhz_int), - .aresetn_ctrl_0(~rst_50mhz_int), - .interrupt_host_0(), - .qsfp0_int_l_0(qsfp0_intl), - .qsfp0_lpmode_0(), - .qsfp0_modprs_l_0(qsfp0_modprsl), - .qsfp0_modsel_l_0(), - .qsfp0_reset_l_0(), - .qsfp1_int_l_0(qsfp1_intl), - .qsfp1_lpmode_0(), - .qsfp1_modprs_l_0(qsfp1_modprsl), - .qsfp1_modsel_l_0(), - .qsfp1_reset_l_0(), - .s_axi_ctrl_0_araddr(axil_cms_araddr_int), - .s_axi_ctrl_0_arprot(axil_cms_arprot_int), - .s_axi_ctrl_0_arready(axil_cms_arready_int), - .s_axi_ctrl_0_arvalid(axil_cms_arvalid_int), - .s_axi_ctrl_0_awaddr(axil_cms_awaddr_int), - .s_axi_ctrl_0_awprot(axil_cms_awprot_int), - .s_axi_ctrl_0_awready(axil_cms_awready_int), - .s_axi_ctrl_0_awvalid(axil_cms_awvalid_int), - .s_axi_ctrl_0_bready(axil_cms_bready_int), - .s_axi_ctrl_0_bresp(axil_cms_bresp_int), - .s_axi_ctrl_0_bvalid(axil_cms_bvalid_int), - .s_axi_ctrl_0_rdata(axil_cms_rdata_int), - .s_axi_ctrl_0_rready(axil_cms_rready_int), - .s_axi_ctrl_0_rresp(axil_cms_rresp_int), - .s_axi_ctrl_0_rvalid(axil_cms_rvalid_int), - .s_axi_ctrl_0_wdata(axil_cms_wdata_int), - .s_axi_ctrl_0_wready(axil_cms_wready_int), - .s_axi_ctrl_0_wstrb(axil_cms_wstrb_int), - .s_axi_ctrl_0_wvalid(axil_cms_wvalid_int), - .satellite_gpio_0(msp_gpio), - .satellite_uart_0_rxd(msp_uart_rxd), - .satellite_uart_0_txd(msp_uart_txd) -); - -// configure SI5335 clock generators -reg qsfp_refclk_reset_reg = 1'b1; -reg sys_reset_reg = 1'b1; - -reg [9:0] reset_timer_reg = 0; - -assign mmcm_rst = sys_reset_reg | pcie_user_reset; - -always @(posedge cfgmclk_int) begin - if (&reset_timer_reg) begin - if (qsfp_refclk_reset_reg) begin - qsfp_refclk_reset_reg <= 1'b0; - reset_timer_reg <= 0; - end else begin - qsfp_refclk_reset_reg <= 1'b0; - sys_reset_reg <= 1'b0; - end - end else begin - reset_timer_reg <= reset_timer_reg + 1; - end -end - -// PCIe -wire pcie_sys_clk; -wire pcie_sys_clk_gt; - -IBUFDS_GTE4 #( - .REFCLK_HROW_CK_SEL(2'b00) -) -ibufds_gte4_pcie_mgt_refclk_inst ( - .I (pcie_refclk_p), - .IB (pcie_refclk_n), - .CEB (1'b0), - .O (pcie_sys_clk_gt), - .ODIV2 (pcie_sys_clk) -); - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep; -wire axis_rq_tlast; -wire axis_rq_tready; -wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser; -wire axis_rq_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep; -wire axis_rc_tlast; -wire axis_rc_tready; -wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser; -wire axis_rc_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep; -wire axis_cq_tlast; -wire axis_cq_tready; -wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser; -wire axis_cq_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep; -wire axis_cc_tlast; -wire axis_cc_tready; -wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser; -wire axis_cc_tvalid; - -wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num0; -wire pcie_rq_seq_num_vld0; -wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num1; -wire pcie_rq_seq_num_vld1; - -wire [3:0] pcie_tfc_nph_av; -wire [3:0] pcie_tfc_npd_av; - -wire [2:0] cfg_max_payload; -wire [2:0] cfg_max_read_req; -wire [3:0] cfg_rcb_status; - -wire [9:0] cfg_mgmt_addr; -wire [7:0] cfg_mgmt_function_number; -wire cfg_mgmt_write; -wire [31:0] cfg_mgmt_write_data; -wire [3:0] cfg_mgmt_byte_enable; -wire cfg_mgmt_read; -wire [31:0] cfg_mgmt_read_data; -wire cfg_mgmt_read_write_done; - -wire [7:0] cfg_fc_ph; -wire [11:0] cfg_fc_pd; -wire [7:0] cfg_fc_nph; -wire [11:0] cfg_fc_npd; -wire [7:0] cfg_fc_cplh; -wire [11:0] cfg_fc_cpld; -wire [2:0] cfg_fc_sel; - -wire [3:0] cfg_interrupt_msix_enable; -wire [3:0] cfg_interrupt_msix_mask; -wire [251:0] cfg_interrupt_msix_vf_enable; -wire [251:0] cfg_interrupt_msix_vf_mask; -wire [63:0] cfg_interrupt_msix_address; -wire [31:0] cfg_interrupt_msix_data; -wire cfg_interrupt_msix_int; -wire [1:0] cfg_interrupt_msix_vec_pending; -wire cfg_interrupt_msix_vec_pending_status; -wire cfg_interrupt_msix_sent; -wire cfg_interrupt_msix_fail; -wire [7:0] cfg_interrupt_msi_function_number; - -wire status_error_cor; -wire status_error_uncor; - -// extra register for pcie_user_reset signal -wire pcie_user_reset_int; -(* shreg_extract = "no" *) -reg pcie_user_reset_reg_1 = 1'b1; -(* shreg_extract = "no" *) -reg pcie_user_reset_reg_2 = 1'b1; - -always @(posedge pcie_user_clk) begin - pcie_user_reset_reg_1 <= pcie_user_reset_int; - pcie_user_reset_reg_2 <= pcie_user_reset_reg_1; -end - -BUFG -pcie_user_reset_bufg_inst ( - .I(pcie_user_reset_reg_2), - .O(pcie_user_reset) -); - -pcie4_uscale_plus_0 -pcie4_uscale_plus_inst ( - .pci_exp_txn(pcie_tx_n), - .pci_exp_txp(pcie_tx_p), - .pci_exp_rxn(pcie_rx_n), - .pci_exp_rxp(pcie_rx_p), - .user_clk(pcie_user_clk), - .user_reset(pcie_user_reset_int), - .user_lnk_up(), - - .s_axis_rq_tdata(axis_rq_tdata), - .s_axis_rq_tkeep(axis_rq_tkeep), - .s_axis_rq_tlast(axis_rq_tlast), - .s_axis_rq_tready(axis_rq_tready), - .s_axis_rq_tuser(axis_rq_tuser), - .s_axis_rq_tvalid(axis_rq_tvalid), - - .m_axis_rc_tdata(axis_rc_tdata), - .m_axis_rc_tkeep(axis_rc_tkeep), - .m_axis_rc_tlast(axis_rc_tlast), - .m_axis_rc_tready(axis_rc_tready), - .m_axis_rc_tuser(axis_rc_tuser), - .m_axis_rc_tvalid(axis_rc_tvalid), - - .m_axis_cq_tdata(axis_cq_tdata), - .m_axis_cq_tkeep(axis_cq_tkeep), - .m_axis_cq_tlast(axis_cq_tlast), - .m_axis_cq_tready(axis_cq_tready), - .m_axis_cq_tuser(axis_cq_tuser), - .m_axis_cq_tvalid(axis_cq_tvalid), - - .s_axis_cc_tdata(axis_cc_tdata), - .s_axis_cc_tkeep(axis_cc_tkeep), - .s_axis_cc_tlast(axis_cc_tlast), - .s_axis_cc_tready(axis_cc_tready), - .s_axis_cc_tuser(axis_cc_tuser), - .s_axis_cc_tvalid(axis_cc_tvalid), - - .pcie_rq_seq_num0(pcie_rq_seq_num0), - .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0), - .pcie_rq_seq_num1(pcie_rq_seq_num1), - .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1), - .pcie_rq_tag0(), - .pcie_rq_tag1(), - .pcie_rq_tag_av(), - .pcie_rq_tag_vld0(), - .pcie_rq_tag_vld1(), - - .pcie_tfc_nph_av(pcie_tfc_nph_av), - .pcie_tfc_npd_av(pcie_tfc_npd_av), - - .pcie_cq_np_req(1'b1), - .pcie_cq_np_req_count(), - - .cfg_phy_link_down(), - .cfg_phy_link_status(), - .cfg_negotiated_width(), - .cfg_current_speed(), - .cfg_max_payload(cfg_max_payload), - .cfg_max_read_req(cfg_max_read_req), - .cfg_function_status(), - .cfg_function_power_state(), - .cfg_vf_status(), - .cfg_vf_power_state(), - .cfg_link_power_state(), - - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - .cfg_mgmt_debug_access(1'b0), - - .cfg_err_cor_out(), - .cfg_err_nonfatal_out(), - .cfg_err_fatal_out(), - .cfg_local_error_valid(), - .cfg_local_error_out(), - .cfg_ltssm_state(), - .cfg_rx_pm_state(), - .cfg_tx_pm_state(), - .cfg_rcb_status(cfg_rcb_status), - .cfg_obff_enable(), - .cfg_pl_status_change(), - .cfg_tph_requester_enable(), - .cfg_tph_st_mode(), - .cfg_vf_tph_requester_enable(), - .cfg_vf_tph_st_mode(), - - .cfg_msg_received(), - .cfg_msg_received_data(), - .cfg_msg_received_type(), - .cfg_msg_transmit(1'b0), - .cfg_msg_transmit_type(3'd0), - .cfg_msg_transmit_data(32'd0), - .cfg_msg_transmit_done(), - - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - .cfg_dsn(64'd0), - - .cfg_power_state_change_ack(1'b1), - .cfg_power_state_change_interrupt(), - - .cfg_err_cor_in(status_error_cor), - .cfg_err_uncor_in(status_error_uncor), - .cfg_flr_in_process(), - .cfg_flr_done(4'd0), - .cfg_vf_flr_in_process(), - .cfg_vf_flr_func_num(8'd0), - .cfg_vf_flr_done(8'd0), - - .cfg_link_training_enable(1'b1), - - .cfg_interrupt_int(4'd0), - .cfg_interrupt_pending(4'd0), - .cfg_interrupt_sent(), - .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), - .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), - .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), - .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), - .cfg_interrupt_msix_address(cfg_interrupt_msix_address), - .cfg_interrupt_msix_data(cfg_interrupt_msix_data), - .cfg_interrupt_msix_int(cfg_interrupt_msix_int), - .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), - .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), - .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent), - .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - .cfg_pm_aspm_l1_entry_reject(1'b0), - .cfg_pm_aspm_tx_l0s_entry_disable(1'b0), - - .cfg_hot_reset_out(), - - .cfg_config_space_enable(1'b1), - .cfg_req_pm_transition_l23_ready(1'b0), - .cfg_hot_reset_in(1'b0), - - .cfg_ds_port_number(8'd0), - .cfg_ds_bus_number(8'd0), - .cfg_ds_device_number(5'd0), - - .sys_clk(pcie_sys_clk), - .sys_clk_gt(pcie_sys_clk_gt), - .sys_reset(pcie_reset_n), - - .phy_rdy_out() -); - -// XGMII 10G PHY - -// QSFP0 -assign qsfp0_refclk_reset = qsfp_refclk_reset_reg; -assign qsfp0_fs = 2'b10; - -wire qsfp0_tx_clk_1_int; -wire qsfp0_tx_rst_1_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1_int; -wire qsfp0_cfg_tx_prbs31_enable_1_int; -wire qsfp0_rx_clk_1_int; -wire qsfp0_rx_rst_1_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1_int; -wire qsfp0_cfg_rx_prbs31_enable_1_int; -wire [6:0] qsfp0_rx_error_count_1_int; -wire qsfp0_tx_clk_2_int; -wire qsfp0_tx_rst_2_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2_int; -wire qsfp0_cfg_tx_prbs31_enable_2_int; -wire qsfp0_rx_clk_2_int; -wire qsfp0_rx_rst_2_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2_int; -wire qsfp0_cfg_rx_prbs31_enable_2_int; -wire [6:0] qsfp0_rx_error_count_2_int; -wire qsfp0_tx_clk_3_int; -wire qsfp0_tx_rst_3_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3_int; -wire qsfp0_cfg_tx_prbs31_enable_3_int; -wire qsfp0_rx_clk_3_int; -wire qsfp0_rx_rst_3_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3_int; -wire qsfp0_cfg_rx_prbs31_enable_3_int; -wire [6:0] qsfp0_rx_error_count_3_int; -wire qsfp0_tx_clk_4_int; -wire qsfp0_tx_rst_4_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4_int; -wire qsfp0_cfg_tx_prbs31_enable_4_int; -wire qsfp0_rx_clk_4_int; -wire qsfp0_rx_rst_4_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4_int; -wire qsfp0_cfg_rx_prbs31_enable_4_int; -wire [6:0] qsfp0_rx_error_count_4_int; - -wire qsfp0_drp_clk = clk_125mhz_int; -wire qsfp0_drp_rst = rst_125mhz_int; -wire [23:0] qsfp0_drp_addr; -wire [15:0] qsfp0_drp_di; -wire qsfp0_drp_en; -wire qsfp0_drp_we; -wire [15:0] qsfp0_drp_do; -wire qsfp0_drp_rdy; - -wire qsfp0_rx_block_lock_1; -wire qsfp0_rx_status_1; -wire qsfp0_rx_block_lock_2; -wire qsfp0_rx_status_2; -wire qsfp0_rx_block_lock_3; -wire qsfp0_rx_status_3; -wire qsfp0_rx_block_lock_4; -wire qsfp0_rx_status_4; - -wire qsfp0_gtpowergood; - -wire qsfp0_mgt_refclk_1; -wire qsfp0_mgt_refclk_1_int; -wire qsfp0_mgt_refclk_1_bufg; - -assign clk_161mhz_ref_int = qsfp0_mgt_refclk_1_bufg; - -IBUFDS_GTE4 ibufds_gte4_qsfp0_mgt_refclk_1_inst ( - .I (qsfp0_mgt_refclk_1_p), - .IB (qsfp0_mgt_refclk_1_n), - .CEB (1'b0), - .O (qsfp0_mgt_refclk_1), - .ODIV2 (qsfp0_mgt_refclk_1_int) -); - -BUFG_GT bufg_gt_qsfp0_mgt_refclk_1_inst ( - .CE (qsfp0_gtpowergood), - .CEMASK (1'b1), - .CLR (1'b0), - .CLRMASK (1'b1), - .DIV (3'd0), - .I (qsfp0_mgt_refclk_1_int), - .O (qsfp0_mgt_refclk_1_bufg) -); - -wire qsfp0_rst; - -sync_reset #( - .N(4) -) -qsfp0_sync_reset_inst ( - .clk(qsfp0_mgt_refclk_1_bufg), - .rst(rst_125mhz_int), - .out(qsfp0_rst) -); - -eth_xcvr_phy_10g_gty_quad_wrapper #( - .PRBS31_ENABLE(1), - .TX_SERDES_PIPELINE(1), - .RX_SERDES_PIPELINE(1), - .COUNT_125US(125000/2.56) -) -qsfp0_phy_quad_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp0_rst), - - /* - * Common - */ - .xcvr_gtpowergood_out(qsfp0_gtpowergood), - .xcvr_ref_clk(qsfp0_mgt_refclk_1), - - /* - * DRP - */ - .drp_clk(qsfp0_drp_clk), - .drp_rst(qsfp0_drp_rst), - .drp_addr(qsfp0_drp_addr), - .drp_di(qsfp0_drp_di), - .drp_en(qsfp0_drp_en), - .drp_we(qsfp0_drp_we), - .drp_do(qsfp0_drp_do), - .drp_rdy(qsfp0_drp_rdy), - - /* - * Serial data - */ - .xcvr_txp(qsfp0_tx_p), - .xcvr_txn(qsfp0_tx_n), - .xcvr_rxp(qsfp0_rx_p), - .xcvr_rxn(qsfp0_rx_n), - - /* - * PHY connections - */ - .phy_1_tx_clk(qsfp0_tx_clk_1_int), - .phy_1_tx_rst(qsfp0_tx_rst_1_int), - .phy_1_xgmii_txd(qsfp0_txd_1_int), - .phy_1_xgmii_txc(qsfp0_txc_1_int), - .phy_1_rx_clk(qsfp0_rx_clk_1_int), - .phy_1_rx_rst(qsfp0_rx_rst_1_int), - .phy_1_xgmii_rxd(qsfp0_rxd_1_int), - .phy_1_xgmii_rxc(qsfp0_rxc_1_int), - .phy_1_tx_bad_block(), - .phy_1_rx_error_count(qsfp0_rx_error_count_1_int), - .phy_1_rx_bad_block(), - .phy_1_rx_sequence_error(), - .phy_1_rx_block_lock(qsfp0_rx_block_lock_1), - .phy_1_rx_high_ber(), - .phy_1_rx_status(qsfp0_rx_status_1), - .phy_1_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_1_int), - .phy_1_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_1_int), - - .phy_2_tx_clk(qsfp0_tx_clk_2_int), - .phy_2_tx_rst(qsfp0_tx_rst_2_int), - .phy_2_xgmii_txd(qsfp0_txd_2_int), - .phy_2_xgmii_txc(qsfp0_txc_2_int), - .phy_2_rx_clk(qsfp0_rx_clk_2_int), - .phy_2_rx_rst(qsfp0_rx_rst_2_int), - .phy_2_xgmii_rxd(qsfp0_rxd_2_int), - .phy_2_xgmii_rxc(qsfp0_rxc_2_int), - .phy_2_tx_bad_block(), - .phy_2_rx_error_count(qsfp0_rx_error_count_2_int), - .phy_2_rx_bad_block(), - .phy_2_rx_sequence_error(), - .phy_2_rx_block_lock(qsfp0_rx_block_lock_2), - .phy_2_rx_high_ber(), - .phy_2_rx_status(qsfp0_rx_status_2), - .phy_2_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_2_int), - .phy_2_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_2_int), - - .phy_3_tx_clk(qsfp0_tx_clk_3_int), - .phy_3_tx_rst(qsfp0_tx_rst_3_int), - .phy_3_xgmii_txd(qsfp0_txd_3_int), - .phy_3_xgmii_txc(qsfp0_txc_3_int), - .phy_3_rx_clk(qsfp0_rx_clk_3_int), - .phy_3_rx_rst(qsfp0_rx_rst_3_int), - .phy_3_xgmii_rxd(qsfp0_rxd_3_int), - .phy_3_xgmii_rxc(qsfp0_rxc_3_int), - .phy_3_tx_bad_block(), - .phy_3_rx_error_count(qsfp0_rx_error_count_3_int), - .phy_3_rx_bad_block(), - .phy_3_rx_sequence_error(), - .phy_3_rx_block_lock(qsfp0_rx_block_lock_3), - .phy_3_rx_high_ber(), - .phy_3_rx_status(qsfp0_rx_status_3), - .phy_3_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_3_int), - .phy_3_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_3_int), - - .phy_4_tx_clk(qsfp0_tx_clk_4_int), - .phy_4_tx_rst(qsfp0_tx_rst_4_int), - .phy_4_xgmii_txd(qsfp0_txd_4_int), - .phy_4_xgmii_txc(qsfp0_txc_4_int), - .phy_4_rx_clk(qsfp0_rx_clk_4_int), - .phy_4_rx_rst(qsfp0_rx_rst_4_int), - .phy_4_xgmii_rxd(qsfp0_rxd_4_int), - .phy_4_xgmii_rxc(qsfp0_rxc_4_int), - .phy_4_tx_bad_block(), - .phy_4_rx_error_count(qsfp0_rx_error_count_4_int), - .phy_4_rx_bad_block(), - .phy_4_rx_sequence_error(), - .phy_4_rx_block_lock(qsfp0_rx_block_lock_4), - .phy_4_rx_high_ber(), - .phy_4_rx_status(qsfp0_rx_status_4), - .phy_4_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_4_int), - .phy_4_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_4_int) -); - -// QSFP1 -assign qsfp1_refclk_reset = qsfp_refclk_reset_reg; -assign qsfp1_fs = 2'b10; - -wire qsfp1_tx_clk_1_int; -wire qsfp1_tx_rst_1_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1_int; -wire qsfp1_cfg_tx_prbs31_enable_1_int; -wire qsfp1_rx_clk_1_int; -wire qsfp1_rx_rst_1_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1_int; -wire qsfp1_cfg_rx_prbs31_enable_1_int; -wire [6:0] qsfp1_rx_error_count_1_int; -wire qsfp1_tx_clk_2_int; -wire qsfp1_tx_rst_2_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2_int; -wire qsfp1_cfg_tx_prbs31_enable_2_int; -wire qsfp1_rx_clk_2_int; -wire qsfp1_rx_rst_2_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2_int; -wire qsfp1_cfg_rx_prbs31_enable_2_int; -wire [6:0] qsfp1_rx_error_count_2_int; -wire qsfp1_tx_clk_3_int; -wire qsfp1_tx_rst_3_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3_int; -wire qsfp1_cfg_tx_prbs31_enable_3_int; -wire qsfp1_rx_clk_3_int; -wire qsfp1_rx_rst_3_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3_int; -wire qsfp1_cfg_rx_prbs31_enable_3_int; -wire [6:0] qsfp1_rx_error_count_3_int; -wire qsfp1_tx_clk_4_int; -wire qsfp1_tx_rst_4_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4_int; -wire qsfp1_cfg_tx_prbs31_enable_4_int; -wire qsfp1_rx_clk_4_int; -wire qsfp1_rx_rst_4_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4_int; -wire qsfp1_cfg_rx_prbs31_enable_4_int; -wire [6:0] qsfp1_rx_error_count_4_int; - -wire qsfp1_drp_clk = clk_125mhz_int; -wire qsfp1_drp_rst = rst_125mhz_int; -wire [23:0] qsfp1_drp_addr; -wire [15:0] qsfp1_drp_di; -wire qsfp1_drp_en; -wire qsfp1_drp_we; -wire [15:0] qsfp1_drp_do; -wire qsfp1_drp_rdy; - -wire qsfp1_rx_block_lock_1; -wire qsfp1_rx_status_1; -wire qsfp1_rx_block_lock_2; -wire qsfp1_rx_status_2; -wire qsfp1_rx_block_lock_3; -wire qsfp1_rx_status_3; -wire qsfp1_rx_block_lock_4; -wire qsfp1_rx_status_4; - -wire qsfp1_gtpowergood; - -wire qsfp1_mgt_refclk_1; -wire qsfp1_mgt_refclk_1_int; -wire qsfp1_mgt_refclk_1_bufg; - -IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_1_inst ( - .I (qsfp1_mgt_refclk_1_p), - .IB (qsfp1_mgt_refclk_1_n), - .CEB (1'b0), - .O (qsfp1_mgt_refclk_1), - .ODIV2 (qsfp1_mgt_refclk_1_int) -); - -BUFG_GT bufg_gt_qsfp1_mgt_refclk_1_inst ( - .CE (qsfp1_gtpowergood), - .CEMASK (1'b1), - .CLR (1'b0), - .CLRMASK (1'b1), - .DIV (3'd0), - .I (qsfp1_mgt_refclk_1_int), - .O (qsfp1_mgt_refclk_1_bufg) -); - -wire qsfp1_rst; - -sync_reset #( - .N(4) -) -qsfp1_sync_reset_inst ( - .clk(qsfp1_mgt_refclk_1_bufg), - .rst(rst_125mhz_int), - .out(qsfp1_rst) -); - -eth_xcvr_phy_10g_gty_quad_wrapper #( - .PRBS31_ENABLE(1), - .TX_SERDES_PIPELINE(1), - .RX_SERDES_PIPELINE(1), - .COUNT_125US(125000/2.56) -) -qsfp1_phy_quad_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp1_rst), - - /* - * Common - */ - .xcvr_gtpowergood_out(qsfp1_gtpowergood), - .xcvr_ref_clk(qsfp1_mgt_refclk_1), - - /* - * DRP - */ - .drp_clk(qsfp1_drp_clk), - .drp_rst(qsfp1_drp_rst), - .drp_addr(qsfp1_drp_addr), - .drp_di(qsfp1_drp_di), - .drp_en(qsfp1_drp_en), - .drp_we(qsfp1_drp_we), - .drp_do(qsfp1_drp_do), - .drp_rdy(qsfp1_drp_rdy), - - /* - * Serial data - */ - .xcvr_txp(qsfp1_tx_p), - .xcvr_txn(qsfp1_tx_n), - .xcvr_rxp(qsfp1_rx_p), - .xcvr_rxn(qsfp1_rx_n), - - /* - * PHY connections - */ - .phy_1_tx_clk(qsfp1_tx_clk_1_int), - .phy_1_tx_rst(qsfp1_tx_rst_1_int), - .phy_1_xgmii_txd(qsfp1_txd_1_int), - .phy_1_xgmii_txc(qsfp1_txc_1_int), - .phy_1_rx_clk(qsfp1_rx_clk_1_int), - .phy_1_rx_rst(qsfp1_rx_rst_1_int), - .phy_1_xgmii_rxd(qsfp1_rxd_1_int), - .phy_1_xgmii_rxc(qsfp1_rxc_1_int), - .phy_1_tx_bad_block(), - .phy_1_rx_error_count(qsfp1_rx_error_count_1_int), - .phy_1_rx_bad_block(), - .phy_1_rx_sequence_error(), - .phy_1_rx_block_lock(qsfp1_rx_block_lock_1), - .phy_1_rx_high_ber(), - .phy_1_rx_status(qsfp1_rx_status_1), - .phy_1_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_1_int), - .phy_1_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_1_int), - - .phy_2_tx_clk(qsfp1_tx_clk_2_int), - .phy_2_tx_rst(qsfp1_tx_rst_2_int), - .phy_2_xgmii_txd(qsfp1_txd_2_int), - .phy_2_xgmii_txc(qsfp1_txc_2_int), - .phy_2_rx_clk(qsfp1_rx_clk_2_int), - .phy_2_rx_rst(qsfp1_rx_rst_2_int), - .phy_2_xgmii_rxd(qsfp1_rxd_2_int), - .phy_2_xgmii_rxc(qsfp1_rxc_2_int), - .phy_2_tx_bad_block(), - .phy_2_rx_error_count(qsfp1_rx_error_count_2_int), - .phy_2_rx_bad_block(), - .phy_2_rx_sequence_error(), - .phy_2_rx_block_lock(qsfp1_rx_block_lock_2), - .phy_2_rx_high_ber(), - .phy_2_rx_status(qsfp1_rx_status_2), - .phy_2_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_2_int), - .phy_2_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_2_int), - - .phy_3_tx_clk(qsfp1_tx_clk_3_int), - .phy_3_tx_rst(qsfp1_tx_rst_3_int), - .phy_3_xgmii_txd(qsfp1_txd_3_int), - .phy_3_xgmii_txc(qsfp1_txc_3_int), - .phy_3_rx_clk(qsfp1_rx_clk_3_int), - .phy_3_rx_rst(qsfp1_rx_rst_3_int), - .phy_3_xgmii_rxd(qsfp1_rxd_3_int), - .phy_3_xgmii_rxc(qsfp1_rxc_3_int), - .phy_3_tx_bad_block(), - .phy_3_rx_error_count(qsfp1_rx_error_count_3_int), - .phy_3_rx_bad_block(), - .phy_3_rx_sequence_error(), - .phy_3_rx_block_lock(qsfp1_rx_block_lock_3), - .phy_3_rx_high_ber(), - .phy_3_rx_status(qsfp1_rx_status_3), - .phy_3_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_3_int), - .phy_3_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_3_int), - - .phy_4_tx_clk(qsfp1_tx_clk_4_int), - .phy_4_tx_rst(qsfp1_tx_rst_4_int), - .phy_4_xgmii_txd(qsfp1_txd_4_int), - .phy_4_xgmii_txc(qsfp1_txc_4_int), - .phy_4_rx_clk(qsfp1_rx_clk_4_int), - .phy_4_rx_rst(qsfp1_rx_rst_4_int), - .phy_4_xgmii_rxd(qsfp1_rxd_4_int), - .phy_4_xgmii_rxc(qsfp1_rxc_4_int), - .phy_4_tx_bad_block(), - .phy_4_rx_error_count(qsfp1_rx_error_count_4_int), - .phy_4_rx_bad_block(), - .phy_4_rx_sequence_error(), - .phy_4_rx_block_lock(qsfp1_rx_block_lock_4), - .phy_4_rx_high_ber(), - .phy_4_rx_status(qsfp1_rx_status_4), - .phy_4_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_4_int), - .phy_4_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_4_int) -); - -wire ptp_clk; -wire ptp_rst; -wire ptp_sample_clk; - -assign ptp_clk = qsfp0_mgt_refclk_1_bufg; -assign ptp_rst = qsfp0_rst; -assign ptp_sample_clk = clk_125mhz_int; - -// DDR4 -wire [DDR_CH-1:0] ddr_clk; -wire [DDR_CH-1:0] ddr_rst; - -wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; -wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; -wire [DDR_CH*8-1:0] m_axi_ddr_awlen; -wire [DDR_CH*3-1:0] m_axi_ddr_awsize; -wire [DDR_CH*2-1:0] m_axi_ddr_awburst; -wire [DDR_CH-1:0] m_axi_ddr_awlock; -wire [DDR_CH*4-1:0] m_axi_ddr_awcache; -wire [DDR_CH*3-1:0] m_axi_ddr_awprot; -wire [DDR_CH*4-1:0] m_axi_ddr_awqos; -wire [DDR_CH-1:0] m_axi_ddr_awvalid; -wire [DDR_CH-1:0] m_axi_ddr_awready; -wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; -wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; -wire [DDR_CH-1:0] m_axi_ddr_wlast; -wire [DDR_CH-1:0] m_axi_ddr_wvalid; -wire [DDR_CH-1:0] m_axi_ddr_wready; -wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; -wire [DDR_CH*2-1:0] m_axi_ddr_bresp; -wire [DDR_CH-1:0] m_axi_ddr_bvalid; -wire [DDR_CH-1:0] m_axi_ddr_bready; -wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; -wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; -wire [DDR_CH*8-1:0] m_axi_ddr_arlen; -wire [DDR_CH*3-1:0] m_axi_ddr_arsize; -wire [DDR_CH*2-1:0] m_axi_ddr_arburst; -wire [DDR_CH-1:0] m_axi_ddr_arlock; -wire [DDR_CH*4-1:0] m_axi_ddr_arcache; -wire [DDR_CH*3-1:0] m_axi_ddr_arprot; -wire [DDR_CH*4-1:0] m_axi_ddr_arqos; -wire [DDR_CH-1:0] m_axi_ddr_arvalid; -wire [DDR_CH-1:0] m_axi_ddr_arready; -wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; -wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; -wire [DDR_CH*2-1:0] m_axi_ddr_rresp; -wire [DDR_CH-1:0] m_axi_ddr_rlast; -wire [DDR_CH-1:0] m_axi_ddr_rvalid; -wire [DDR_CH-1:0] m_axi_ddr_rready; - -wire [DDR_CH-1:0] ddr_status; - -generate - -if (DDR_ENABLE && DDR_CH > 0) begin - -reg ddr4_rst_reg = 1'b1; - -always @(posedge pcie_user_clk or posedge pcie_user_reset) begin - if (pcie_user_reset) begin - ddr4_rst_reg <= 1'b1; - end else begin - ddr4_rst_reg <= 1'b0; - end -end - -ddr4_0 ddr4_c0_inst ( - .c0_sys_clk_p(clk_300mhz_0_p), - .c0_sys_clk_n(clk_300mhz_0_n), - .sys_rst(ddr4_rst_reg), - - .c0_init_calib_complete(ddr_status[0 +: 1]), - .c0_ddr4_interrupt(), - .dbg_clk(), - .dbg_bus(), - - .c0_ddr4_adr(ddr4_c0_adr), - .c0_ddr4_ba(ddr4_c0_ba), - .c0_ddr4_cke(ddr4_c0_cke), - .c0_ddr4_cs_n(ddr4_c0_cs_n), - .c0_ddr4_dq(ddr4_c0_dq), - .c0_ddr4_dqs_t(ddr4_c0_dqs_t), - .c0_ddr4_dqs_c(ddr4_c0_dqs_c), - .c0_ddr4_odt(ddr4_c0_odt), - .c0_ddr4_parity(ddr4_c0_par), - .c0_ddr4_bg(ddr4_c0_bg), - .c0_ddr4_reset_n(ddr4_c0_reset_n), - .c0_ddr4_act_n(ddr4_c0_act_n), - .c0_ddr4_ck_t(ddr4_c0_ck_t), - .c0_ddr4_ck_c(ddr4_c0_ck_c), - - .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), - .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), - - .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), - - .c0_ddr4_s_axi_ctrl_awvalid(1'b0), - .c0_ddr4_s_axi_ctrl_awready(), - .c0_ddr4_s_axi_ctrl_awaddr(32'd0), - .c0_ddr4_s_axi_ctrl_wvalid(1'b0), - .c0_ddr4_s_axi_ctrl_wready(), - .c0_ddr4_s_axi_ctrl_wdata(32'd0), - .c0_ddr4_s_axi_ctrl_bvalid(), - .c0_ddr4_s_axi_ctrl_bready(1'b1), - .c0_ddr4_s_axi_ctrl_bresp(), - .c0_ddr4_s_axi_ctrl_arvalid(1'b0), - .c0_ddr4_s_axi_ctrl_arready(), - .c0_ddr4_s_axi_ctrl_araddr(31'd0), - .c0_ddr4_s_axi_ctrl_rvalid(), - .c0_ddr4_s_axi_ctrl_rready(1'b1), - .c0_ddr4_s_axi_ctrl_rdata(), - .c0_ddr4_s_axi_ctrl_rresp(), - - .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), - .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), - .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), - .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), - .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), - .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), - .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), - .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), - .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), - .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), - .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), - .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), - .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), - .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), - .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), - .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), - .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), - .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), - .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), - .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), - .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), - .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), - .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), - .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), - .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), - .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), - .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), - .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), - .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), - .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), - .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) -); - -end else begin - -assign ddr4_c0_adr = {17{1'bz}}; -assign ddr4_c0_ba = {2{1'bz}}; -assign ddr4_c0_bg = {2{1'bz}}; -assign ddr4_c0_cke = 1'bz; -assign ddr4_c0_cs_n = 1'bz; -assign ddr4_c0_act_n = 1'bz; -assign ddr4_c0_odt = 1'bz; -assign ddr4_c0_par = 1'bz; -assign ddr4_c0_reset_n = 1'b0; -assign ddr4_c0_dq = {72{1'bz}}; -assign ddr4_c0_dqs_t = {18{1'bz}}; -assign ddr4_c0_dqs_c = {18{1'bz}}; - -OBUFTDS ddr4_c0_ck_obuftds_inst ( - .I(1'b0), - .T(1'b1), - .O(ddr4_c0_ck_t), - .OB(ddr4_c0_ck_c) -); - -assign ddr_clk = 0; -assign ddr_rst = 0; - -assign m_axi_ddr_awready = 0; -assign m_axi_ddr_wready = 0; -assign m_axi_ddr_bid = 0; -assign m_axi_ddr_bresp = 0; -assign m_axi_ddr_bvalid = 0; -assign m_axi_ddr_arready = 0; -assign m_axi_ddr_rid = 0; -assign m_axi_ddr_rdata = 0; -assign m_axi_ddr_rresp = 0; -assign m_axi_ddr_rlast = 0; -assign m_axi_ddr_rvalid = 0; - -assign ddr_status = 0; - -end - -if (DDR_ENABLE && DDR_CH > 1) begin - -reg ddr4_rst_reg = 1'b1; - -always @(posedge pcie_user_clk or posedge pcie_user_reset) begin - if (pcie_user_reset) begin - ddr4_rst_reg <= 1'b1; - end else begin - ddr4_rst_reg <= 1'b0; - end -end - -ddr4_0 ddr4_c1_inst ( - .c0_sys_clk_p(clk_300mhz_1_p), - .c0_sys_clk_n(clk_300mhz_1_n), - .sys_rst(ddr4_rst_reg), - - .c0_init_calib_complete(ddr_status[1 +: 1]), - .c0_ddr4_interrupt(), - .dbg_clk(), - .dbg_bus(), - - .c0_ddr4_adr(ddr4_c1_adr), - .c0_ddr4_ba(ddr4_c1_ba), - .c0_ddr4_cke(ddr4_c1_cke), - .c0_ddr4_cs_n(ddr4_c1_cs_n), - .c0_ddr4_dq(ddr4_c1_dq), - .c0_ddr4_dqs_t(ddr4_c1_dqs_t), - .c0_ddr4_dqs_c(ddr4_c1_dqs_c), - .c0_ddr4_odt(ddr4_c1_odt), - .c0_ddr4_parity(ddr4_c1_par), - .c0_ddr4_bg(ddr4_c1_bg), - .c0_ddr4_reset_n(ddr4_c1_reset_n), - .c0_ddr4_act_n(ddr4_c1_act_n), - .c0_ddr4_ck_t(ddr4_c1_ck_t), - .c0_ddr4_ck_c(ddr4_c1_ck_c), - - .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), - .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), - - .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), - - .c0_ddr4_s_axi_ctrl_awvalid(1'b0), - .c0_ddr4_s_axi_ctrl_awready(), - .c0_ddr4_s_axi_ctrl_awaddr(32'd0), - .c0_ddr4_s_axi_ctrl_wvalid(1'b0), - .c0_ddr4_s_axi_ctrl_wready(), - .c0_ddr4_s_axi_ctrl_wdata(32'd0), - .c0_ddr4_s_axi_ctrl_bvalid(), - .c0_ddr4_s_axi_ctrl_bready(1'b1), - .c0_ddr4_s_axi_ctrl_bresp(), - .c0_ddr4_s_axi_ctrl_arvalid(1'b0), - .c0_ddr4_s_axi_ctrl_arready(), - .c0_ddr4_s_axi_ctrl_araddr(31'd0), - .c0_ddr4_s_axi_ctrl_rvalid(), - .c0_ddr4_s_axi_ctrl_rready(1'b1), - .c0_ddr4_s_axi_ctrl_rdata(), - .c0_ddr4_s_axi_ctrl_rresp(), - - .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), - .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), - .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), - .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), - .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), - .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), - .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), - .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), - .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), - .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), - .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), - .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), - .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), - .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), - .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), - .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), - .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), - .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), - .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), - .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), - .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), - .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), - .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), - .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), - .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), - .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), - .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), - .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), - .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), - .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), - .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) -); - -end else begin - -assign ddr4_c1_adr = {17{1'bz}}; -assign ddr4_c1_ba = {2{1'bz}}; -assign ddr4_c1_bg = {2{1'bz}}; -assign ddr4_c1_cke = 1'bz; -assign ddr4_c1_cs_n = 1'bz; -assign ddr4_c1_act_n = 1'bz; -assign ddr4_c1_odt = 1'bz; -assign ddr4_c1_par = 1'bz; -assign ddr4_c1_reset_n = 1'b0; -assign ddr4_c1_dq = {72{1'bz}}; -assign ddr4_c1_dqs_t = {18{1'bz}}; -assign ddr4_c1_dqs_c = {18{1'bz}}; - -OBUFTDS ddr4_c1_ck_obuftds_inst ( - .I(1'b0), - .T(1'b1), - .O(ddr4_c1_ck_t), - .OB(ddr4_c1_ck_c) -); - -end - -if (DDR_ENABLE && DDR_CH > 2) begin - -reg ddr4_rst_reg = 1'b1; - -always @(posedge pcie_user_clk or posedge pcie_user_reset) begin - if (pcie_user_reset) begin - ddr4_rst_reg <= 1'b1; - end else begin - ddr4_rst_reg <= 1'b0; - end -end - -ddr4_0 ddr4_c2_inst ( - .c0_sys_clk_p(clk_300mhz_2_p), - .c0_sys_clk_n(clk_300mhz_2_n), - .sys_rst(ddr4_rst_reg), - - .c0_init_calib_complete(ddr_status[2 +: 1]), - .c0_ddr4_interrupt(), - .dbg_clk(), - .dbg_bus(), - - .c0_ddr4_adr(ddr4_c2_adr), - .c0_ddr4_ba(ddr4_c2_ba), - .c0_ddr4_cke(ddr4_c2_cke), - .c0_ddr4_cs_n(ddr4_c2_cs_n), - .c0_ddr4_dq(ddr4_c2_dq), - .c0_ddr4_dqs_t(ddr4_c2_dqs_t), - .c0_ddr4_dqs_c(ddr4_c2_dqs_c), - .c0_ddr4_odt(ddr4_c2_odt), - .c0_ddr4_parity(ddr4_c2_par), - .c0_ddr4_bg(ddr4_c2_bg), - .c0_ddr4_reset_n(ddr4_c2_reset_n), - .c0_ddr4_act_n(ddr4_c2_act_n), - .c0_ddr4_ck_t(ddr4_c2_ck_t), - .c0_ddr4_ck_c(ddr4_c2_ck_c), - - .c0_ddr4_ui_clk(ddr_clk[2 +: 1]), - .c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]), - - .c0_ddr4_aresetn(!ddr_rst[2 +: 1]), - - .c0_ddr4_s_axi_ctrl_awvalid(1'b0), - .c0_ddr4_s_axi_ctrl_awready(), - .c0_ddr4_s_axi_ctrl_awaddr(32'd0), - .c0_ddr4_s_axi_ctrl_wvalid(1'b0), - .c0_ddr4_s_axi_ctrl_wready(), - .c0_ddr4_s_axi_ctrl_wdata(32'd0), - .c0_ddr4_s_axi_ctrl_bvalid(), - .c0_ddr4_s_axi_ctrl_bready(1'b1), - .c0_ddr4_s_axi_ctrl_bresp(), - .c0_ddr4_s_axi_ctrl_arvalid(1'b0), - .c0_ddr4_s_axi_ctrl_arready(), - .c0_ddr4_s_axi_ctrl_araddr(31'd0), - .c0_ddr4_s_axi_ctrl_rvalid(), - .c0_ddr4_s_axi_ctrl_rready(1'b1), - .c0_ddr4_s_axi_ctrl_rdata(), - .c0_ddr4_s_axi_ctrl_rresp(), - - .c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]), - .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]), - .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]), - .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]), - .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]), - .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]), - .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]), - .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]), - .c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]), - .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), - .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), - .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]), - .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]), - .c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]), - .c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]), - .c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]), - .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]), - .c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]), - .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]), - .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]), - .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]), - .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]), - .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]), - .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]), - .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]), - .c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]), - .c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]), - .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]), - .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]), - .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]), - .c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) -); - -end else begin - -assign ddr4_c2_adr = {17{1'bz}}; -assign ddr4_c2_ba = {2{1'bz}}; -assign ddr4_c2_bg = {2{1'bz}}; -assign ddr4_c2_cke = 1'bz; -assign ddr4_c2_cs_n = 1'bz; -assign ddr4_c2_act_n = 1'bz; -assign ddr4_c2_odt = 1'bz; -assign ddr4_c2_par = 1'bz; -assign ddr4_c2_reset_n = 1'b0; -assign ddr4_c2_dq = {72{1'bz}}; -assign ddr4_c2_dqs_t = {18{1'bz}}; -assign ddr4_c2_dqs_c = {18{1'bz}}; - -OBUFTDS ddr4_c2_ck_obuftds_inst ( - .I(1'b0), - .T(1'b1), - .O(ddr4_c2_ck_t), - .OB(ddr4_c2_ck_c) -); - -end - -if (DDR_ENABLE && DDR_CH > 3) begin - -reg ddr4_rst_reg = 1'b1; - -always @(posedge pcie_user_clk or posedge pcie_user_reset) begin - if (pcie_user_reset) begin - ddr4_rst_reg <= 1'b1; - end else begin - ddr4_rst_reg <= 1'b0; - end -end - -ddr4_0 ddr4_c3_inst ( - .c0_sys_clk_p(clk_300mhz_3_p), - .c0_sys_clk_n(clk_300mhz_3_n), - .sys_rst(ddr4_rst_reg), - - .c0_init_calib_complete(ddr_status[3 +: 1]), - .c0_ddr4_interrupt(), - .dbg_clk(), - .dbg_bus(), - - .c0_ddr4_adr(ddr4_c3_adr), - .c0_ddr4_ba(ddr4_c3_ba), - .c0_ddr4_cke(ddr4_c3_cke), - .c0_ddr4_cs_n(ddr4_c3_cs_n), - .c0_ddr4_dq(ddr4_c3_dq), - .c0_ddr4_dqs_t(ddr4_c3_dqs_t), - .c0_ddr4_dqs_c(ddr4_c3_dqs_c), - .c0_ddr4_odt(ddr4_c3_odt), - .c0_ddr4_parity(ddr4_c3_par), - .c0_ddr4_bg(ddr4_c3_bg), - .c0_ddr4_reset_n(ddr4_c3_reset_n), - .c0_ddr4_act_n(ddr4_c3_act_n), - .c0_ddr4_ck_t(ddr4_c3_ck_t), - .c0_ddr4_ck_c(ddr4_c3_ck_c), - - .c0_ddr4_ui_clk(ddr_clk[3 +: 1]), - .c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]), - - .c0_ddr4_aresetn(!ddr_rst[3 +: 1]), - - .c0_ddr4_s_axi_ctrl_awvalid(1'b0), - .c0_ddr4_s_axi_ctrl_awready(), - .c0_ddr4_s_axi_ctrl_awaddr(32'd0), - .c0_ddr4_s_axi_ctrl_wvalid(1'b0), - .c0_ddr4_s_axi_ctrl_wready(), - .c0_ddr4_s_axi_ctrl_wdata(32'd0), - .c0_ddr4_s_axi_ctrl_bvalid(), - .c0_ddr4_s_axi_ctrl_bready(1'b1), - .c0_ddr4_s_axi_ctrl_bresp(), - .c0_ddr4_s_axi_ctrl_arvalid(1'b0), - .c0_ddr4_s_axi_ctrl_arready(), - .c0_ddr4_s_axi_ctrl_araddr(31'd0), - .c0_ddr4_s_axi_ctrl_rvalid(), - .c0_ddr4_s_axi_ctrl_rready(1'b1), - .c0_ddr4_s_axi_ctrl_rdata(), - .c0_ddr4_s_axi_ctrl_rresp(), - - .c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]), - .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]), - .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]), - .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]), - .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]), - .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]), - .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]), - .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]), - .c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]), - .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), - .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), - .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]), - .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]), - .c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]), - .c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]), - .c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]), - .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]), - .c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]), - .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]), - .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]), - .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]), - .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]), - .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]), - .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]), - .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]), - .c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]), - .c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]), - .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]), - .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]), - .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]), - .c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) -); - -end else begin - -assign ddr4_c3_adr = {17{1'bz}}; -assign ddr4_c3_ba = {2{1'bz}}; -assign ddr4_c3_bg = {2{1'bz}}; -assign ddr4_c3_cke = 1'bz; -assign ddr4_c3_cs_n = 1'bz; -assign ddr4_c3_act_n = 1'bz; -assign ddr4_c3_odt = 1'bz; -assign ddr4_c3_par = 1'bz; -assign ddr4_c3_reset_n = 1'b0; -assign ddr4_c3_dq = {72{1'bz}}; -assign ddr4_c3_dqs_t = {18{1'bz}}; -assign ddr4_c3_dqs_c = {18{1'bz}}; - -OBUFTDS ddr4_c3_ck_obuftds_inst ( - .I(1'b0), - .T(1'b1), - .O(ddr4_c3_ck_t), - .OB(ddr4_c3_ck_c) -); - -end - -endgenerate - -fpga_core #( - // FW and board IDs - .FPGA_ID(FPGA_ID), - .FW_ID(FW_ID), - .FW_VER(FW_VER), - .BOARD_ID(BOARD_ID), - .BOARD_VER(BOARD_VER), - .BUILD_DATE(BUILD_DATE), - .GIT_HASH(GIT_HASH), - .RELEASE_INFO(RELEASE_INFO), - - // Board configuration - .TDMA_BER_ENABLE(TDMA_BER_ENABLE), - - // Structural configuration - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - .SCHED_PER_IF(SCHED_PER_IF), - .PORT_MASK(PORT_MASK), - - // Clock configuration - .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), - .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), - - // PTP configuration - .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), - .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), - .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), - - // Queue manager configuration - .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), - .EQN_WIDTH(EQN_WIDTH), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .CQN_WIDTH(CQN_WIDTH), - .EQ_PIPELINE(EQ_PIPELINE), - .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), - .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .CQ_PIPELINE(CQ_PIPELINE), - - // TX and RX engine configuration - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), - - // Scheduler configuration - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - - // Interface configuration - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), - .TX_TAG_WIDTH(TX_TAG_WIDTH), - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .PFC_ENABLE(PFC_ENABLE), - .LFC_ENABLE(LFC_ENABLE), - .ENABLE_PADDING(ENABLE_PADDING), - .ENABLE_DIC(ENABLE_DIC), - .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), - .TX_FIFO_DEPTH(TX_FIFO_DEPTH), - .RX_FIFO_DEPTH(RX_FIFO_DEPTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - - // RAM configuration - .DDR_CH(DDR_CH), - .DDR_ENABLE(DDR_ENABLE), - .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), - .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), - .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), - .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), - .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), - .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), - - // Application block configuration - .APP_ID(APP_ID), - .APP_ENABLE(APP_ENABLE), - .APP_CTRL_ENABLE(APP_CTRL_ENABLE), - .APP_DMA_ENABLE(APP_DMA_ENABLE), - .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), - .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), - .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), - .APP_STAT_ENABLE(APP_STAT_ENABLE), - - // DMA interface configuration - .DMA_IMM_ENABLE(DMA_IMM_ENABLE), - .DMA_IMM_WIDTH(DMA_IMM_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - - // PCIe interface configuration - .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), - .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), - .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), - .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), - .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), - .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), - .RC_STRADDLE(RC_STRADDLE), - .RQ_STRADDLE(RQ_STRADDLE), - .CQ_STRADDLE(CQ_STRADDLE), - .CC_STRADDLE(CC_STRADDLE), - .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), - .PF_COUNT(PF_COUNT), - .VF_COUNT(VF_COUNT), - .PCIE_TAG_COUNT(PCIE_TAG_COUNT), - - // Interrupt configuration - .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), - - // AXI lite interface configuration (control) - .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - - // AXI lite interface configuration (application control) - .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), - .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), - - // Ethernet interface configuration - .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), - .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH), - .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), - .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), - .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), - .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), - .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), - .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), - - // Statistics counter subsystem - .STAT_ENABLE(STAT_ENABLE), - .STAT_DMA_ENABLE(STAT_DMA_ENABLE), - .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), - .STAT_INC_WIDTH(STAT_INC_WIDTH), - .STAT_ID_WIDTH(STAT_ID_WIDTH) -) -core_inst ( - /* - * Clock: 250 MHz - * Synchronous reset - */ - .clk_250mhz(pcie_user_clk), - .rst_250mhz(pcie_user_reset), - - /* - * PTP clock - */ - .ptp_clk(ptp_clk), - .ptp_rst(ptp_rst), - .ptp_sample_clk(ptp_sample_clk), - - /* - * GPIO - */ - .sw(sw_int), - .led(led), - - /* - * I2C - */ - .i2c_scl_i(i2c_scl_i), - .i2c_scl_o(i2c_scl_o), - .i2c_scl_t(i2c_scl_t), - .i2c_sda_i(i2c_sda_i), - .i2c_sda_o(i2c_sda_o), - .i2c_sda_t(i2c_sda_t), - - /* - * PCIe - */ - .m_axis_rq_tdata(axis_rq_tdata), - .m_axis_rq_tkeep(axis_rq_tkeep), - .m_axis_rq_tlast(axis_rq_tlast), - .m_axis_rq_tready(axis_rq_tready), - .m_axis_rq_tuser(axis_rq_tuser), - .m_axis_rq_tvalid(axis_rq_tvalid), - - .s_axis_rc_tdata(axis_rc_tdata), - .s_axis_rc_tkeep(axis_rc_tkeep), - .s_axis_rc_tlast(axis_rc_tlast), - .s_axis_rc_tready(axis_rc_tready), - .s_axis_rc_tuser(axis_rc_tuser), - .s_axis_rc_tvalid(axis_rc_tvalid), - - .s_axis_cq_tdata(axis_cq_tdata), - .s_axis_cq_tkeep(axis_cq_tkeep), - .s_axis_cq_tlast(axis_cq_tlast), - .s_axis_cq_tready(axis_cq_tready), - .s_axis_cq_tuser(axis_cq_tuser), - .s_axis_cq_tvalid(axis_cq_tvalid), - - .m_axis_cc_tdata(axis_cc_tdata), - .m_axis_cc_tkeep(axis_cc_tkeep), - .m_axis_cc_tlast(axis_cc_tlast), - .m_axis_cc_tready(axis_cc_tready), - .m_axis_cc_tuser(axis_cc_tuser), - .m_axis_cc_tvalid(axis_cc_tvalid), - - .s_axis_rq_seq_num_0(pcie_rq_seq_num0), - .s_axis_rq_seq_num_valid_0(pcie_rq_seq_num_vld0), - .s_axis_rq_seq_num_1(pcie_rq_seq_num1), - .s_axis_rq_seq_num_valid_1(pcie_rq_seq_num_vld1), - - .pcie_tfc_nph_av(pcie_tfc_nph_av), - .pcie_tfc_npd_av(pcie_tfc_npd_av), - - .cfg_max_payload(cfg_max_payload), - .cfg_max_read_req(cfg_max_read_req), - .cfg_rcb_status(cfg_rcb_status), - - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), - .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), - .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), - .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), - .cfg_interrupt_msix_address(cfg_interrupt_msix_address), - .cfg_interrupt_msix_data(cfg_interrupt_msix_data), - .cfg_interrupt_msix_int(cfg_interrupt_msix_int), - .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), - .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), - .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), - .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - .status_error_cor(status_error_cor), - .status_error_uncor(status_error_uncor), - - /* - * Ethernet: QSFP28 - */ - .qsfp0_tx_clk_1(qsfp0_tx_clk_1_int), - .qsfp0_tx_rst_1(qsfp0_tx_rst_1_int), - .qsfp0_txd_1(qsfp0_txd_1_int), - .qsfp0_txc_1(qsfp0_txc_1_int), - .qsfp0_cfg_tx_prbs31_enable_1(qsfp0_cfg_tx_prbs31_enable_1_int), - .qsfp0_rx_clk_1(qsfp0_rx_clk_1_int), - .qsfp0_rx_rst_1(qsfp0_rx_rst_1_int), - .qsfp0_rxd_1(qsfp0_rxd_1_int), - .qsfp0_rxc_1(qsfp0_rxc_1_int), - .qsfp0_cfg_rx_prbs31_enable_1(qsfp0_cfg_rx_prbs31_enable_1_int), - .qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int), - .qsfp0_rx_status_1(qsfp0_rx_status_1), - .qsfp0_tx_clk_2(qsfp0_tx_clk_2_int), - .qsfp0_tx_rst_2(qsfp0_tx_rst_2_int), - .qsfp0_txd_2(qsfp0_txd_2_int), - .qsfp0_txc_2(qsfp0_txc_2_int), - .qsfp0_cfg_tx_prbs31_enable_2(qsfp0_cfg_tx_prbs31_enable_2_int), - .qsfp0_rx_clk_2(qsfp0_rx_clk_2_int), - .qsfp0_rx_rst_2(qsfp0_rx_rst_2_int), - .qsfp0_rxd_2(qsfp0_rxd_2_int), - .qsfp0_rxc_2(qsfp0_rxc_2_int), - .qsfp0_cfg_rx_prbs31_enable_2(qsfp0_cfg_rx_prbs31_enable_2_int), - .qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int), - .qsfp0_rx_status_2(qsfp0_rx_status_2), - .qsfp0_tx_clk_3(qsfp0_tx_clk_3_int), - .qsfp0_tx_rst_3(qsfp0_tx_rst_3_int), - .qsfp0_txd_3(qsfp0_txd_3_int), - .qsfp0_txc_3(qsfp0_txc_3_int), - .qsfp0_cfg_tx_prbs31_enable_3(qsfp0_cfg_tx_prbs31_enable_3_int), - .qsfp0_rx_clk_3(qsfp0_rx_clk_3_int), - .qsfp0_rx_rst_3(qsfp0_rx_rst_3_int), - .qsfp0_rxd_3(qsfp0_rxd_3_int), - .qsfp0_rxc_3(qsfp0_rxc_3_int), - .qsfp0_cfg_rx_prbs31_enable_3(qsfp0_cfg_rx_prbs31_enable_3_int), - .qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int), - .qsfp0_rx_status_3(qsfp0_rx_status_3), - .qsfp0_tx_clk_4(qsfp0_tx_clk_4_int), - .qsfp0_tx_rst_4(qsfp0_tx_rst_4_int), - .qsfp0_txd_4(qsfp0_txd_4_int), - .qsfp0_txc_4(qsfp0_txc_4_int), - .qsfp0_cfg_tx_prbs31_enable_4(qsfp0_cfg_tx_prbs31_enable_4_int), - .qsfp0_rx_clk_4(qsfp0_rx_clk_4_int), - .qsfp0_rx_rst_4(qsfp0_rx_rst_4_int), - .qsfp0_rxd_4(qsfp0_rxd_4_int), - .qsfp0_rxc_4(qsfp0_rxc_4_int), - .qsfp0_cfg_rx_prbs31_enable_4(qsfp0_cfg_rx_prbs31_enable_4_int), - .qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int), - .qsfp0_rx_status_4(qsfp0_rx_status_4), - - .qsfp0_drp_clk(qsfp0_drp_clk), - .qsfp0_drp_rst(qsfp0_drp_rst), - .qsfp0_drp_addr(qsfp0_drp_addr), - .qsfp0_drp_di(qsfp0_drp_di), - .qsfp0_drp_en(qsfp0_drp_en), - .qsfp0_drp_we(qsfp0_drp_we), - .qsfp0_drp_do(qsfp0_drp_do), - .qsfp0_drp_rdy(qsfp0_drp_rdy), - - .qsfp0_modprsl(qsfp0_modprsl_int), - .qsfp0_modsell(qsfp0_modsell), - .qsfp0_resetl(qsfp0_resetl), - .qsfp0_intl(qsfp0_intl_int), - .qsfp0_lpmode(qsfp0_lpmode), - - .qsfp1_tx_clk_1(qsfp1_tx_clk_1_int), - .qsfp1_tx_rst_1(qsfp1_tx_rst_1_int), - .qsfp1_txd_1(qsfp1_txd_1_int), - .qsfp1_txc_1(qsfp1_txc_1_int), - .qsfp1_cfg_tx_prbs31_enable_1(qsfp1_cfg_tx_prbs31_enable_1_int), - .qsfp1_rx_clk_1(qsfp1_rx_clk_1_int), - .qsfp1_rx_rst_1(qsfp1_rx_rst_1_int), - .qsfp1_rxd_1(qsfp1_rxd_1_int), - .qsfp1_rxc_1(qsfp1_rxc_1_int), - .qsfp1_cfg_rx_prbs31_enable_1(qsfp1_cfg_rx_prbs31_enable_1_int), - .qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int), - .qsfp1_rx_status_1(qsfp1_rx_status_1), - .qsfp1_tx_clk_2(qsfp1_tx_clk_2_int), - .qsfp1_tx_rst_2(qsfp1_tx_rst_2_int), - .qsfp1_txd_2(qsfp1_txd_2_int), - .qsfp1_txc_2(qsfp1_txc_2_int), - .qsfp1_cfg_tx_prbs31_enable_2(qsfp1_cfg_tx_prbs31_enable_2_int), - .qsfp1_rx_clk_2(qsfp1_rx_clk_2_int), - .qsfp1_rx_rst_2(qsfp1_rx_rst_2_int), - .qsfp1_rxd_2(qsfp1_rxd_2_int), - .qsfp1_rxc_2(qsfp1_rxc_2_int), - .qsfp1_cfg_rx_prbs31_enable_2(qsfp1_cfg_rx_prbs31_enable_2_int), - .qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int), - .qsfp1_rx_status_2(qsfp1_rx_status_2), - .qsfp1_tx_clk_3(qsfp1_tx_clk_3_int), - .qsfp1_tx_rst_3(qsfp1_tx_rst_3_int), - .qsfp1_txd_3(qsfp1_txd_3_int), - .qsfp1_txc_3(qsfp1_txc_3_int), - .qsfp1_cfg_tx_prbs31_enable_3(qsfp1_cfg_tx_prbs31_enable_3_int), - .qsfp1_rx_clk_3(qsfp1_rx_clk_3_int), - .qsfp1_rx_rst_3(qsfp1_rx_rst_3_int), - .qsfp1_rxd_3(qsfp1_rxd_3_int), - .qsfp1_rxc_3(qsfp1_rxc_3_int), - .qsfp1_cfg_rx_prbs31_enable_3(qsfp1_cfg_rx_prbs31_enable_3_int), - .qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int), - .qsfp1_rx_status_3(qsfp1_rx_status_3), - .qsfp1_tx_clk_4(qsfp1_tx_clk_4_int), - .qsfp1_tx_rst_4(qsfp1_tx_rst_4_int), - .qsfp1_txd_4(qsfp1_txd_4_int), - .qsfp1_txc_4(qsfp1_txc_4_int), - .qsfp1_cfg_tx_prbs31_enable_4(qsfp1_cfg_tx_prbs31_enable_4_int), - .qsfp1_rx_clk_4(qsfp1_rx_clk_4_int), - .qsfp1_rx_rst_4(qsfp1_rx_rst_4_int), - .qsfp1_rxd_4(qsfp1_rxd_4_int), - .qsfp1_rxc_4(qsfp1_rxc_4_int), - .qsfp1_cfg_rx_prbs31_enable_4(qsfp1_cfg_rx_prbs31_enable_4_int), - .qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int), - .qsfp1_rx_status_4(qsfp1_rx_status_4), - - .qsfp1_drp_clk(qsfp1_drp_clk), - .qsfp1_drp_rst(qsfp1_drp_rst), - .qsfp1_drp_addr(qsfp1_drp_addr), - .qsfp1_drp_di(qsfp1_drp_di), - .qsfp1_drp_en(qsfp1_drp_en), - .qsfp1_drp_we(qsfp1_drp_we), - .qsfp1_drp_do(qsfp1_drp_do), - .qsfp1_drp_rdy(qsfp1_drp_rdy), - - .qsfp1_modprsl(qsfp1_modprsl_int), - .qsfp1_modsell(qsfp1_modsell), - .qsfp1_resetl(qsfp1_resetl), - .qsfp1_intl(qsfp1_intl_int), - .qsfp1_lpmode(qsfp1_lpmode), - - /* - * DDR - */ - .ddr_clk(ddr_clk), - .ddr_rst(ddr_rst), - - .m_axi_ddr_awid(m_axi_ddr_awid), - .m_axi_ddr_awaddr(m_axi_ddr_awaddr), - .m_axi_ddr_awlen(m_axi_ddr_awlen), - .m_axi_ddr_awsize(m_axi_ddr_awsize), - .m_axi_ddr_awburst(m_axi_ddr_awburst), - .m_axi_ddr_awlock(m_axi_ddr_awlock), - .m_axi_ddr_awcache(m_axi_ddr_awcache), - .m_axi_ddr_awprot(m_axi_ddr_awprot), - .m_axi_ddr_awqos(m_axi_ddr_awqos), - .m_axi_ddr_awvalid(m_axi_ddr_awvalid), - .m_axi_ddr_awready(m_axi_ddr_awready), - .m_axi_ddr_wdata(m_axi_ddr_wdata), - .m_axi_ddr_wstrb(m_axi_ddr_wstrb), - .m_axi_ddr_wlast(m_axi_ddr_wlast), - .m_axi_ddr_wvalid(m_axi_ddr_wvalid), - .m_axi_ddr_wready(m_axi_ddr_wready), - .m_axi_ddr_bid(m_axi_ddr_bid), - .m_axi_ddr_bresp(m_axi_ddr_bresp), - .m_axi_ddr_bvalid(m_axi_ddr_bvalid), - .m_axi_ddr_bready(m_axi_ddr_bready), - .m_axi_ddr_arid(m_axi_ddr_arid), - .m_axi_ddr_araddr(m_axi_ddr_araddr), - .m_axi_ddr_arlen(m_axi_ddr_arlen), - .m_axi_ddr_arsize(m_axi_ddr_arsize), - .m_axi_ddr_arburst(m_axi_ddr_arburst), - .m_axi_ddr_arlock(m_axi_ddr_arlock), - .m_axi_ddr_arcache(m_axi_ddr_arcache), - .m_axi_ddr_arprot(m_axi_ddr_arprot), - .m_axi_ddr_arqos(m_axi_ddr_arqos), - .m_axi_ddr_arvalid(m_axi_ddr_arvalid), - .m_axi_ddr_arready(m_axi_ddr_arready), - .m_axi_ddr_rid(m_axi_ddr_rid), - .m_axi_ddr_rdata(m_axi_ddr_rdata), - .m_axi_ddr_rresp(m_axi_ddr_rresp), - .m_axi_ddr_rlast(m_axi_ddr_rlast), - .m_axi_ddr_rvalid(m_axi_ddr_rvalid), - .m_axi_ddr_rready(m_axi_ddr_rready), - - .ddr_status(ddr_status), - - /* - * QSPI flash - */ - .fpga_boot(fpga_boot), - .qspi_clk(qspi_clk_int), - .qspi_dq_i(qspi_dq_i_int), - .qspi_dq_o(qspi_dq_o_int), - .qspi_dq_oe(qspi_dq_oe_int), - .qspi_cs(qspi_cs_int), - - /* - * AXI-Lite interface to CMS - */ - .m_axil_cms_clk(axil_cms_clk), - .m_axil_cms_rst(axil_cms_rst), - .m_axil_cms_awaddr(axil_cms_awaddr), - .m_axil_cms_awprot(axil_cms_awprot), - .m_axil_cms_awvalid(axil_cms_awvalid), - .m_axil_cms_awready(axil_cms_awready), - .m_axil_cms_wdata(axil_cms_wdata), - .m_axil_cms_wstrb(axil_cms_wstrb), - .m_axil_cms_wvalid(axil_cms_wvalid), - .m_axil_cms_wready(axil_cms_wready), - .m_axil_cms_bresp(axil_cms_bresp), - .m_axil_cms_bvalid(axil_cms_bvalid), - .m_axil_cms_bready(axil_cms_bready), - .m_axil_cms_araddr(axil_cms_araddr), - .m_axil_cms_arprot(axil_cms_arprot), - .m_axil_cms_arvalid(axil_cms_arvalid), - .m_axil_cms_arready(axil_cms_arready), - .m_axil_cms_rdata(axil_cms_rdata), - .m_axil_cms_rresp(axil_cms_rresp), - .m_axil_cms_rvalid(axil_cms_rvalid), - .m_axil_cms_rready(axil_cms_rready) -); - -endmodule - -`resetall diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v deleted file mode 100644 index 3a51ec6d5..000000000 --- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v +++ /dev/null @@ -1,1740 +0,0 @@ -// SPDX-License-Identifier: BSD-2-Clause-Views -/* - * Copyright (c) 2019-2023 The Regents of the University of California - */ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA core logic - */ -module fpga_core # -( - // FW and board IDs - parameter FPGA_ID = 32'h4B57093, - parameter FW_ID = 32'h00000000, - parameter FW_VER = 32'h00_00_01_00, - parameter BOARD_ID = 32'h10ee_90fa, - parameter BOARD_VER = 32'h01_00_00_00, - parameter BUILD_DATE = 32'd602976000, - parameter GIT_HASH = 32'hdce357bf, - parameter RELEASE_INFO = 32'h00000000, - - // Board configuration - parameter TDMA_BER_ENABLE = 0, - - // Structural configuration - parameter IF_COUNT = 2, - parameter PORTS_PER_IF = 1, - parameter SCHED_PER_IF = PORTS_PER_IF, - parameter PORT_MASK = 0, - - // Clock configuration - parameter CLK_PERIOD_NS_NUM = 4, - parameter CLK_PERIOD_NS_DENOM = 1, - - // PTP configuration - parameter PTP_CLK_PERIOD_NS_NUM = 1024, - parameter PTP_CLK_PERIOD_NS_DENOM = 165, - parameter PTP_TS_WIDTH = 96, - parameter PTP_CLOCK_PIPELINE = 0, - parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_PORT_CDC_PIPELINE = 0, - parameter PTP_PEROUT_ENABLE = 0, - parameter PTP_PEROUT_COUNT = 1, - parameter IF_PTP_PERIOD_NS = 6'h6, - parameter IF_PTP_PERIOD_FNS = 16'h6666, - - // Queue manager configuration - parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_QUEUE_OP_TABLE_SIZE = 32, - parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter CQ_OP_TABLE_SIZE = 32, - parameter EQN_WIDTH = 5, - parameter TX_QUEUE_INDEX_WIDTH = 13, - parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, - parameter EQ_PIPELINE = 3, - parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), - parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), - - // TX and RX engine configuration - parameter TX_DESC_TABLE_SIZE = 32, - parameter RX_DESC_TABLE_SIZE = 32, - parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, - - // Scheduler configuration - parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, - parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, - parameter TDMA_INDEX_WIDTH = 6, - - // Interface configuration - parameter PTP_TS_ENABLE = 1, - parameter TX_CPL_FIFO_DEPTH = 32, - parameter TX_TAG_WIDTH = 16, - parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_HASH_ENABLE = 1, - parameter RX_CHECKSUM_ENABLE = 1, - parameter PFC_ENABLE = 1, - parameter LFC_ENABLE = PFC_ENABLE, - parameter ENABLE_PADDING = 1, - parameter ENABLE_DIC = 1, - parameter MIN_FRAME_LENGTH = 64, - parameter TX_FIFO_DEPTH = 32768, - parameter RX_FIFO_DEPTH = 32768, - parameter MAX_TX_SIZE = 9214, - parameter MAX_RX_SIZE = 9214, - parameter TX_RAM_SIZE = 32768, - parameter RX_RAM_SIZE = 32768, - - // RAM configuration - parameter DDR_CH = 4, - parameter DDR_ENABLE = 0, - parameter AXI_DDR_DATA_WIDTH = 512, - parameter AXI_DDR_ADDR_WIDTH = 34, - parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), - parameter AXI_DDR_ID_WIDTH = 8, - parameter AXI_DDR_MAX_BURST_LEN = 256, - parameter AXI_DDR_NARROW_BURST = 0, - - // Application block configuration - parameter APP_ID = 32'h00000000, - parameter APP_ENABLE = 0, - parameter APP_CTRL_ENABLE = 1, - parameter APP_DMA_ENABLE = 1, - parameter APP_AXIS_DIRECT_ENABLE = 1, - parameter APP_AXIS_SYNC_ENABLE = 1, - parameter APP_AXIS_IF_ENABLE = 1, - parameter APP_STAT_ENABLE = 1, - - // DMA interface configuration - parameter DMA_IMM_ENABLE = 0, - parameter DMA_IMM_WIDTH = 32, - parameter DMA_LEN_WIDTH = 16, - parameter DMA_TAG_WIDTH = 16, - parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), - parameter RAM_PIPELINE = 2, - - // PCIe interface configuration - parameter AXIS_PCIE_DATA_WIDTH = 512, - parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), - parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161, - parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137, - parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183, - parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81, - parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256, - parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6, - parameter PF_COUNT = 1, - parameter VF_COUNT = 0, - parameter PCIE_TAG_COUNT = 256, - - // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EQN_WIDTH, - - // AXI lite interface configuration (control) - parameter AXIL_CTRL_DATA_WIDTH = 32, - parameter AXIL_CTRL_ADDR_WIDTH = 24, - - // AXI lite interface configuration (application control) - parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, - parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, - - // Ethernet interface configuration - parameter XGMII_DATA_WIDTH = 64, - parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8, - parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH, - parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, - parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*2, - parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1, - parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, - parameter AXIS_ETH_TX_PIPELINE = 4, - parameter AXIS_ETH_TX_FIFO_PIPELINE = 4, - parameter AXIS_ETH_TX_TS_PIPELINE = 4, - parameter AXIS_ETH_RX_PIPELINE = 4, - parameter AXIS_ETH_RX_FIFO_PIPELINE = 4, - - // Statistics counter subsystem - parameter STAT_ENABLE = 1, - parameter STAT_DMA_ENABLE = 1, - parameter STAT_PCIE_ENABLE = 1, - parameter STAT_INC_WIDTH = 24, - parameter STAT_ID_WIDTH = 12 -) -( - /* - * Clock: 250 MHz - * Synchronous reset - */ - input wire clk_250mhz, - input wire rst_250mhz, - - /* - * PTP clock - */ - input wire ptp_clk, - input wire ptp_rst, - input wire ptp_sample_clk, - - /* - * GPIO - */ - input wire [3:0] sw, - output wire [2:0] led, - - /* - * I2C - */ - input wire i2c_scl_i, - output wire i2c_scl_o, - output wire i2c_scl_t, - input wire i2c_sda_i, - output wire i2c_sda_o, - output wire i2c_sda_t, - - /* - * PCIe - */ - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, - output wire m_axis_rq_tlast, - input wire m_axis_rq_tready, - output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser, - output wire m_axis_rq_tvalid, - - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, - input wire s_axis_rc_tlast, - output wire s_axis_rc_tready, - input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser, - input wire s_axis_rc_tvalid, - - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, - input wire s_axis_cq_tlast, - output wire s_axis_cq_tready, - input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser, - input wire s_axis_cq_tvalid, - - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, - output wire m_axis_cc_tlast, - input wire m_axis_cc_tready, - output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser, - output wire m_axis_cc_tvalid, - - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0, - input wire s_axis_rq_seq_num_valid_0, - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1, - input wire s_axis_rq_seq_num_valid_1, - - input wire [1:0] pcie_tfc_nph_av, - input wire [1:0] pcie_tfc_npd_av, - - input wire [2:0] cfg_max_payload, - input wire [2:0] cfg_max_read_req, - input wire [3:0] cfg_rcb_status, - - output wire [9:0] cfg_mgmt_addr, - output wire [7:0] cfg_mgmt_function_number, - output wire cfg_mgmt_write, - output wire [31:0] cfg_mgmt_write_data, - output wire [3:0] cfg_mgmt_byte_enable, - output wire cfg_mgmt_read, - input wire [31:0] cfg_mgmt_read_data, - input wire cfg_mgmt_read_write_done, - - input wire [7:0] cfg_fc_ph, - input wire [11:0] cfg_fc_pd, - input wire [7:0] cfg_fc_nph, - input wire [11:0] cfg_fc_npd, - input wire [7:0] cfg_fc_cplh, - input wire [11:0] cfg_fc_cpld, - output wire [2:0] cfg_fc_sel, - - input wire [3:0] cfg_interrupt_msix_enable, - input wire [3:0] cfg_interrupt_msix_mask, - input wire [251:0] cfg_interrupt_msix_vf_enable, - input wire [251:0] cfg_interrupt_msix_vf_mask, - output wire [63:0] cfg_interrupt_msix_address, - output wire [31:0] cfg_interrupt_msix_data, - output wire cfg_interrupt_msix_int, - output wire [1:0] cfg_interrupt_msix_vec_pending, - input wire cfg_interrupt_msix_vec_pending_status, - input wire cfg_interrupt_msix_sent, - input wire cfg_interrupt_msix_fail, - output wire [7:0] cfg_interrupt_msi_function_number, - - output wire status_error_cor, - output wire status_error_uncor, - - /* - * Ethernet: QSFP28 - */ - input wire qsfp0_tx_clk_1, - input wire qsfp0_tx_rst_1, - output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1, - output wire qsfp0_cfg_tx_prbs31_enable_1, - input wire qsfp0_rx_clk_1, - input wire qsfp0_rx_rst_1, - input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1, - output wire qsfp0_cfg_rx_prbs31_enable_1, - input wire [6:0] qsfp0_rx_error_count_1, - input wire qsfp0_rx_status_1, - input wire qsfp0_tx_clk_2, - input wire qsfp0_tx_rst_2, - output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2, - output wire qsfp0_cfg_tx_prbs31_enable_2, - input wire qsfp0_rx_clk_2, - input wire qsfp0_rx_rst_2, - input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2, - output wire qsfp0_cfg_rx_prbs31_enable_2, - input wire [6:0] qsfp0_rx_error_count_2, - input wire qsfp0_rx_status_2, - input wire qsfp0_tx_clk_3, - input wire qsfp0_tx_rst_3, - output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3, - output wire qsfp0_cfg_tx_prbs31_enable_3, - input wire qsfp0_rx_clk_3, - input wire qsfp0_rx_rst_3, - input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3, - output wire qsfp0_cfg_rx_prbs31_enable_3, - input wire [6:0] qsfp0_rx_error_count_3, - input wire qsfp0_rx_status_3, - input wire qsfp0_tx_clk_4, - input wire qsfp0_tx_rst_4, - output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4, - output wire qsfp0_cfg_tx_prbs31_enable_4, - input wire qsfp0_rx_clk_4, - input wire qsfp0_rx_rst_4, - input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4, - output wire qsfp0_cfg_rx_prbs31_enable_4, - input wire [6:0] qsfp0_rx_error_count_4, - input wire qsfp0_rx_status_4, - - input wire qsfp0_drp_clk, - input wire qsfp0_drp_rst, - output wire [23:0] qsfp0_drp_addr, - output wire [15:0] qsfp0_drp_di, - output wire qsfp0_drp_en, - output wire qsfp0_drp_we, - input wire [15:0] qsfp0_drp_do, - input wire qsfp0_drp_rdy, - - output wire qsfp0_modsell, - output wire qsfp0_resetl, - input wire qsfp0_modprsl, - input wire qsfp0_intl, - output wire qsfp0_lpmode, - - input wire qsfp1_tx_clk_1, - input wire qsfp1_tx_rst_1, - output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1, - output wire qsfp1_cfg_tx_prbs31_enable_1, - input wire qsfp1_rx_clk_1, - input wire qsfp1_rx_rst_1, - input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1, - output wire qsfp1_cfg_rx_prbs31_enable_1, - input wire [6:0] qsfp1_rx_error_count_1, - input wire qsfp1_rx_status_1, - input wire qsfp1_tx_clk_2, - input wire qsfp1_tx_rst_2, - output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2, - output wire qsfp1_cfg_tx_prbs31_enable_2, - input wire qsfp1_rx_clk_2, - input wire qsfp1_rx_rst_2, - input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2, - output wire qsfp1_cfg_rx_prbs31_enable_2, - input wire [6:0] qsfp1_rx_error_count_2, - input wire qsfp1_rx_status_2, - input wire qsfp1_tx_clk_3, - input wire qsfp1_tx_rst_3, - output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3, - output wire qsfp1_cfg_tx_prbs31_enable_3, - input wire qsfp1_rx_clk_3, - input wire qsfp1_rx_rst_3, - input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3, - output wire qsfp1_cfg_rx_prbs31_enable_3, - input wire [6:0] qsfp1_rx_error_count_3, - input wire qsfp1_rx_status_3, - input wire qsfp1_tx_clk_4, - input wire qsfp1_tx_rst_4, - output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4, - output wire qsfp1_cfg_tx_prbs31_enable_4, - input wire qsfp1_rx_clk_4, - input wire qsfp1_rx_rst_4, - input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4, - output wire qsfp1_cfg_rx_prbs31_enable_4, - input wire [6:0] qsfp1_rx_error_count_4, - input wire qsfp1_rx_status_4, - - input wire qsfp1_drp_clk, - input wire qsfp1_drp_rst, - output wire [23:0] qsfp1_drp_addr, - output wire [15:0] qsfp1_drp_di, - output wire qsfp1_drp_en, - output wire qsfp1_drp_we, - input wire [15:0] qsfp1_drp_do, - input wire qsfp1_drp_rdy, - - output wire qsfp1_modsell, - output wire qsfp1_resetl, - input wire qsfp1_modprsl, - input wire qsfp1_intl, - output wire qsfp1_lpmode, - - /* - * DDR - */ - input wire [DDR_CH-1:0] ddr_clk, - input wire [DDR_CH-1:0] ddr_rst, - - output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, - output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, - output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, - output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, - output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, - output wire [DDR_CH-1:0] m_axi_ddr_awlock, - output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, - output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, - output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, - output wire [DDR_CH-1:0] m_axi_ddr_awvalid, - input wire [DDR_CH-1:0] m_axi_ddr_awready, - output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, - output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, - output wire [DDR_CH-1:0] m_axi_ddr_wlast, - output wire [DDR_CH-1:0] m_axi_ddr_wvalid, - input wire [DDR_CH-1:0] m_axi_ddr_wready, - input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, - input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, - input wire [DDR_CH-1:0] m_axi_ddr_bvalid, - output wire [DDR_CH-1:0] m_axi_ddr_bready, - output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, - output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, - output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, - output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, - output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, - output wire [DDR_CH-1:0] m_axi_ddr_arlock, - output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, - output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, - output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, - output wire [DDR_CH-1:0] m_axi_ddr_arvalid, - input wire [DDR_CH-1:0] m_axi_ddr_arready, - input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, - input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, - input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, - input wire [DDR_CH-1:0] m_axi_ddr_rlast, - input wire [DDR_CH-1:0] m_axi_ddr_rvalid, - output wire [DDR_CH-1:0] m_axi_ddr_rready, - - input wire [DDR_CH-1:0] ddr_status, - - /* - * QSPI flash - */ - output wire fpga_boot, - output wire qspi_clk, - input wire [3:0] qspi_dq_i, - output wire [3:0] qspi_dq_o, - output wire [3:0] qspi_dq_oe, - output wire qspi_cs, - - /* - * AXI-Lite interface to CMS - */ - output wire m_axil_cms_clk, - output wire m_axil_cms_rst, - output wire [17:0] m_axil_cms_awaddr, - output wire [2:0] m_axil_cms_awprot, - output wire m_axil_cms_awvalid, - input wire m_axil_cms_awready, - output wire [31:0] m_axil_cms_wdata, - output wire [3:0] m_axil_cms_wstrb, - output wire m_axil_cms_wvalid, - input wire m_axil_cms_wready, - input wire [1:0] m_axil_cms_bresp, - input wire m_axil_cms_bvalid, - output wire m_axil_cms_bready, - output wire [17:0] m_axil_cms_araddr, - output wire [2:0] m_axil_cms_arprot, - output wire m_axil_cms_arvalid, - input wire m_axil_cms_arready, - input wire [31:0] m_axil_cms_rdata, - input wire [1:0] m_axil_cms_rresp, - input wire m_axil_cms_rvalid, - output wire m_axil_cms_rready -); - -parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; - -parameter F_COUNT = PF_COUNT+VF_COUNT; - -parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8); -parameter AXIL_IF_CTRL_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT); -parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8); - -localparam RB_BASE_ADDR = 16'h1000; -localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; - -localparam RB_DRP_QSFP0_BASE = RB_BASE_ADDR + 16'h60; -localparam RB_DRP_QSFP1_BASE = RB_DRP_QSFP0_BASE + 16'h20; - -initial begin - if (PORT_COUNT > 8) begin - $error("Error: Max port count exceeded (instance %m)"); - $finish; - end -end - -// AXI lite connections -wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_awaddr; -wire [2:0] axil_csr_awprot; -wire axil_csr_awvalid; -wire axil_csr_awready; -wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_wdata; -wire [AXIL_CTRL_STRB_WIDTH-1:0] axil_csr_wstrb; -wire axil_csr_wvalid; -wire axil_csr_wready; -wire [1:0] axil_csr_bresp; -wire axil_csr_bvalid; -wire axil_csr_bready; -wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_araddr; -wire [2:0] axil_csr_arprot; -wire axil_csr_arvalid; -wire axil_csr_arready; -wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_rdata; -wire [1:0] axil_csr_rresp; -wire axil_csr_rvalid; -wire axil_csr_rready; - -// PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; - -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse; - -// control registers -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_wr_addr; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_wr_data; -wire [AXIL_CTRL_STRB_WIDTH-1:0] ctrl_reg_wr_strb; -wire ctrl_reg_wr_en; -wire ctrl_reg_wr_wait; -wire ctrl_reg_wr_ack; -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_rd_addr; -wire ctrl_reg_rd_en; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data; -wire ctrl_reg_rd_wait; -wire ctrl_reg_rd_ack; - -wire qsfp0_drp_reg_wr_wait; -wire qsfp0_drp_reg_wr_ack; -wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp0_drp_reg_rd_data; -wire qsfp0_drp_reg_rd_wait; -wire qsfp0_drp_reg_rd_ack; - -wire qsfp1_drp_reg_wr_wait; -wire qsfp1_drp_reg_wr_ack; -wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp1_drp_reg_rd_data; -wire qsfp1_drp_reg_rd_wait; -wire qsfp1_drp_reg_rd_ack; - -reg ctrl_reg_wr_ack_reg = 1'b0; -reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; -reg ctrl_reg_rd_ack_reg = 1'b0; - -reg qsfp0_reset_reg = 1'b0; -reg qsfp1_reset_reg = 1'b0; - -reg qsfp0_lpmode_reg = 1'b0; -reg qsfp1_lpmode_reg = 1'b0; - -reg i2c_scl_o_reg = 1'b1; -reg i2c_sda_o_reg = 1'b1; - -reg fpga_boot_reg = 1'b0; - -reg qspi_clk_reg = 1'b0; -reg qspi_cs_reg = 1'b1; -reg [3:0] qspi_dq_o_reg = 4'd0; -reg [3:0] qspi_dq_oe_reg = 4'd0; - -reg [17:0] m_axil_cms_addr_reg = 18'd0; -reg m_axil_cms_awvalid_reg = 1'b0; -reg [31:0] m_axil_cms_wdata_reg = 32'd0; -reg [3:0] m_axil_cms_wstrb_reg = 4'b0000; -reg m_axil_cms_wvalid_reg = 1'b0; -reg m_axil_cms_arvalid_reg = 1'b0; - -assign ctrl_reg_wr_wait = qsfp0_drp_reg_wr_wait | qsfp1_drp_reg_wr_wait; -assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp0_drp_reg_wr_ack | qsfp1_drp_reg_wr_ack; -assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp0_drp_reg_rd_data | qsfp1_drp_reg_rd_data; -assign ctrl_reg_rd_wait = qsfp0_drp_reg_rd_wait | qsfp1_drp_reg_rd_wait; -assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp0_drp_reg_rd_ack | qsfp1_drp_reg_rd_ack; - -assign qsfp0_modsell = 1'b0; -assign qsfp1_modsell = 1'b0; - -assign qsfp0_resetl = !qsfp0_reset_reg; -assign qsfp1_resetl = !qsfp1_reset_reg; - -assign qsfp0_lpmode = qsfp0_lpmode_reg; -assign qsfp1_lpmode = qsfp1_lpmode_reg; - -assign i2c_scl_o = i2c_scl_o_reg; -assign i2c_scl_t = i2c_scl_o_reg; -assign i2c_sda_o = i2c_sda_o_reg; -assign i2c_sda_t = i2c_sda_o_reg; - -assign fpga_boot = fpga_boot_reg; - -assign qspi_clk = qspi_clk_reg; -assign qspi_cs = qspi_cs_reg; -assign qspi_dq_o = qspi_dq_o_reg; -assign qspi_dq_oe = qspi_dq_oe_reg; - -assign m_axil_cms_clk = clk_250mhz; -assign m_axil_cms_rst = rst_250mhz; -assign m_axil_cms_awaddr = m_axil_cms_addr_reg; -assign m_axil_cms_awprot = 3'b000; -assign m_axil_cms_awvalid = m_axil_cms_awvalid_reg; -assign m_axil_cms_wdata = m_axil_cms_wdata_reg; -assign m_axil_cms_wstrb = m_axil_cms_wstrb_reg; -assign m_axil_cms_wvalid = m_axil_cms_wvalid_reg; -assign m_axil_cms_bready = 1'b1; -assign m_axil_cms_araddr = m_axil_cms_addr_reg; -assign m_axil_cms_arprot = 3'b000; -assign m_axil_cms_arvalid = m_axil_cms_arvalid_reg; -assign m_axil_cms_rready = 1'b1; - -always @(posedge clk_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; - ctrl_reg_rd_ack_reg <= 1'b0; - - m_axil_cms_awvalid_reg <= m_axil_cms_awvalid_reg && !m_axil_cms_awready; - m_axil_cms_wvalid_reg <= m_axil_cms_wvalid_reg && !m_axil_cms_wready; - m_axil_cms_arvalid_reg <= m_axil_cms_arvalid_reg && !m_axil_cms_arready; - - if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin - // write operation - ctrl_reg_wr_ack_reg <= 1'b0; - case ({ctrl_reg_wr_addr >> 2, 2'b00}) - // FW ID - 8'h0C: begin - // FW ID: FPGA JTAG ID - fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD; - end - // I2C 0 - RBB+8'h0C: begin - // I2C ctrl: control - if (ctrl_reg_wr_strb[0]) begin - i2c_scl_o_reg <= ctrl_reg_wr_data[1]; - end - if (ctrl_reg_wr_strb[1]) begin - i2c_sda_o_reg <= ctrl_reg_wr_data[9]; - end - end - // XCVR GPIO - RBB+8'h1C: begin - // XCVR GPIO: control 0123 - if (ctrl_reg_wr_strb[0]) begin - qsfp0_reset_reg <= ctrl_reg_wr_data[4]; - qsfp0_lpmode_reg <= ctrl_reg_wr_data[5]; - end - if (ctrl_reg_wr_strb[1]) begin - qsfp1_reset_reg <= ctrl_reg_wr_data[12]; - qsfp1_lpmode_reg <= ctrl_reg_wr_data[13]; - end - end - // QSPI flash - RBB+8'h2C: begin - // SPI flash ctrl: format - fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD; - end - RBB+8'h30: begin - // SPI flash ctrl: control 0 - if (ctrl_reg_wr_strb[0]) begin - qspi_dq_o_reg <= ctrl_reg_wr_data[3:0]; - end - if (ctrl_reg_wr_strb[1]) begin - qspi_dq_oe_reg <= ctrl_reg_wr_data[11:8]; - end - if (ctrl_reg_wr_strb[2]) begin - qspi_clk_reg <= ctrl_reg_wr_data[16]; - qspi_cs_reg <= ctrl_reg_wr_data[17]; - end - end - // Alveo BMC - RBB+8'h4C: begin - // BMC ctrl: Addr - if (!m_axil_cms_arvalid && !m_axil_cms_awvalid) begin - m_axil_cms_addr_reg <= ctrl_reg_wr_data; - m_axil_cms_arvalid_reg <= 1'b1; - end - end - RBB+8'h50: begin - // BMC ctrl: Data - if (!m_axil_cms_wvalid) begin - m_axil_cms_awvalid_reg <= 1'b1; - m_axil_cms_wdata_reg <= ctrl_reg_wr_data; - m_axil_cms_wstrb_reg <= ctrl_reg_wr_strb; - m_axil_cms_wvalid_reg <= 1'b1; - end - end - default: ctrl_reg_wr_ack_reg <= 1'b0; - endcase - end - - if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin - // read operation - ctrl_reg_rd_ack_reg <= 1'b1; - case ({ctrl_reg_rd_addr >> 2, 2'b00}) - // I2C 0 - RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type - RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version - RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // I2C ctrl: Next header - RBB+8'h0C: begin - // I2C ctrl: control - ctrl_reg_rd_data_reg[0] <= i2c_scl_i; - ctrl_reg_rd_data_reg[1] <= i2c_scl_o_reg; - ctrl_reg_rd_data_reg[8] <= i2c_sda_i; - ctrl_reg_rd_data_reg[9] <= i2c_sda_o_reg; - end - // XCVR GPIO - RBB+8'h10: ctrl_reg_rd_data_reg <= 32'h0000C101; // XCVR GPIO: Type - RBB+8'h14: ctrl_reg_rd_data_reg <= 32'h00000100; // XCVR GPIO: Version - RBB+8'h18: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // XCVR GPIO: Next header - RBB+8'h1C: begin - // XCVR GPIO: control 0123 - ctrl_reg_rd_data_reg[0] <= !qsfp0_modprsl; - ctrl_reg_rd_data_reg[1] <= !qsfp0_intl; - ctrl_reg_rd_data_reg[4] <= qsfp0_reset_reg; - ctrl_reg_rd_data_reg[5] <= qsfp0_lpmode_reg; - ctrl_reg_rd_data_reg[8] <= !qsfp1_modprsl; - ctrl_reg_rd_data_reg[9] <= !qsfp1_intl; - ctrl_reg_rd_data_reg[12] <= qsfp1_reset_reg; - ctrl_reg_rd_data_reg[13] <= qsfp1_lpmode_reg; - end - // QSPI flash - RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type - RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version - RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // SPI flash ctrl: Next header - RBB+8'h2C: begin - // SPI flash ctrl: format - ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments) - ctrl_reg_rd_data_reg[7:4] <= 1; // default segment - ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment - ctrl_reg_rd_data_reg[31:12] <= 32'h01002000 >> 12; // first segment size (Alveo default) - end - RBB+8'h30: begin - // SPI flash ctrl: control 0 - ctrl_reg_rd_data_reg[3:0] <= qspi_dq_i; - ctrl_reg_rd_data_reg[11:8] <= qspi_dq_oe; - ctrl_reg_rd_data_reg[16] <= qspi_clk; - ctrl_reg_rd_data_reg[17] <= qspi_cs; - end - // Alveo BMC - RBB+8'h40: ctrl_reg_rd_data_reg <= 32'h0000C140; // BMC ctrl: Type - RBB+8'h44: ctrl_reg_rd_data_reg <= 32'h00000100; // BMC ctrl: Version - RBB+8'h48: ctrl_reg_rd_data_reg <= RB_DRP_QSFP0_BASE; // BMC ctrl: Next header - RBB+8'h4C: ctrl_reg_rd_data_reg <= m_axil_cms_addr_reg; // BMC ctrl: Addr - RBB+8'h50: ctrl_reg_rd_data_reg <= m_axil_cms_rdata; // BMC ctrl: Data - default: ctrl_reg_rd_ack_reg <= 1'b0; - endcase - end - - if (rst_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_ack_reg <= 1'b0; - - qsfp0_reset_reg <= 1'b0; - qsfp1_reset_reg <= 1'b0; - - qsfp0_lpmode_reg <= 1'b0; - qsfp1_lpmode_reg <= 1'b0; - - i2c_scl_o_reg <= 1'b1; - i2c_sda_o_reg <= 1'b1; - - fpga_boot_reg <= 1'b0; - - qspi_clk_reg <= 1'b0; - qspi_cs_reg <= 1'b1; - qspi_dq_o_reg <= 4'd0; - qspi_dq_oe_reg <= 4'd0; - - m_axil_cms_awvalid_reg <= 1'b0; - m_axil_cms_wvalid_reg <= 1'b0; - m_axil_cms_arvalid_reg <= 1'b0; - end -end - -rb_drp #( - .DRP_ADDR_WIDTH(24), - .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}), - .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .RB_BASE_ADDR(RB_DRP_QSFP0_BASE), - .RB_NEXT_PTR(RB_DRP_QSFP1_BASE) -) -qsfp0_rb_drp_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * Register interface - */ - .reg_wr_addr(ctrl_reg_wr_addr), - .reg_wr_data(ctrl_reg_wr_data), - .reg_wr_strb(ctrl_reg_wr_strb), - .reg_wr_en(ctrl_reg_wr_en), - .reg_wr_wait(qsfp0_drp_reg_wr_wait), - .reg_wr_ack(qsfp0_drp_reg_wr_ack), - .reg_rd_addr(ctrl_reg_rd_addr), - .reg_rd_en(ctrl_reg_rd_en), - .reg_rd_data(qsfp0_drp_reg_rd_data), - .reg_rd_wait(qsfp0_drp_reg_rd_wait), - .reg_rd_ack(qsfp0_drp_reg_rd_ack), - - /* - * DRP - */ - .drp_clk(qsfp0_drp_clk), - .drp_rst(qsfp0_drp_rst), - .drp_addr(qsfp0_drp_addr), - .drp_di(qsfp0_drp_di), - .drp_en(qsfp0_drp_en), - .drp_we(qsfp0_drp_we), - .drp_do(qsfp0_drp_do), - .drp_rdy(qsfp0_drp_rdy) -); - -rb_drp #( - .DRP_ADDR_WIDTH(24), - .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}), - .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .RB_BASE_ADDR(RB_DRP_QSFP1_BASE), - .RB_NEXT_PTR(0) -) -qsfp1_rb_drp_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * Register interface - */ - .reg_wr_addr(ctrl_reg_wr_addr), - .reg_wr_data(ctrl_reg_wr_data), - .reg_wr_strb(ctrl_reg_wr_strb), - .reg_wr_en(ctrl_reg_wr_en), - .reg_wr_wait(qsfp1_drp_reg_wr_wait), - .reg_wr_ack(qsfp1_drp_reg_wr_ack), - .reg_rd_addr(ctrl_reg_rd_addr), - .reg_rd_en(ctrl_reg_rd_en), - .reg_rd_data(qsfp1_drp_reg_rd_data), - .reg_rd_wait(qsfp1_drp_reg_rd_wait), - .reg_rd_ack(qsfp1_drp_reg_rd_ack), - - /* - * DRP - */ - .drp_clk(qsfp1_drp_clk), - .drp_rst(qsfp1_drp_rst), - .drp_addr(qsfp1_drp_addr), - .drp_di(qsfp1_drp_di), - .drp_en(qsfp1_drp_en), - .drp_we(qsfp1_drp_we), - .drp_do(qsfp1_drp_do), - .drp_rdy(qsfp1_drp_rdy) -); - -generate - -if (TDMA_BER_ENABLE) begin - - // BER tester - tdma_ber #( - .COUNT(8), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(8)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000), - .PHY_PIPELINE(2) - ) - tdma_ber_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - .phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), - .phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), - .phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}), - .phy_cfg_tx_prbs31_enable({qsfp1_cfg_tx_prbs31_enable_4, qsfp1_cfg_tx_prbs31_enable_3, qsfp1_cfg_tx_prbs31_enable_2, qsfp1_cfg_tx_prbs31_enable_1, qsfp0_cfg_tx_prbs31_enable_4, qsfp0_cfg_tx_prbs31_enable_3, qsfp0_cfg_tx_prbs31_enable_2, qsfp0_cfg_tx_prbs31_enable_1}), - .phy_cfg_rx_prbs31_enable({qsfp1_cfg_rx_prbs31_enable_4, qsfp1_cfg_rx_prbs31_enable_3, qsfp1_cfg_rx_prbs31_enable_2, qsfp1_cfg_rx_prbs31_enable_1, qsfp0_cfg_rx_prbs31_enable_4, qsfp0_cfg_rx_prbs31_enable_3, qsfp0_cfg_rx_prbs31_enable_2, qsfp0_cfg_rx_prbs31_enable_1}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) - ); - -end else begin - - assign qsfp0_cfg_tx_prbs31_enable_1 = 1'b0; - assign qsfp0_cfg_rx_prbs31_enable_1 = 1'b0; - assign qsfp0_cfg_tx_prbs31_enable_2 = 1'b0; - assign qsfp0_cfg_rx_prbs31_enable_2 = 1'b0; - assign qsfp0_cfg_tx_prbs31_enable_3 = 1'b0; - assign qsfp0_cfg_rx_prbs31_enable_3 = 1'b0; - assign qsfp0_cfg_tx_prbs31_enable_4 = 1'b0; - assign qsfp0_cfg_rx_prbs31_enable_4 = 1'b0; - assign qsfp1_cfg_tx_prbs31_enable_1 = 1'b0; - assign qsfp1_cfg_rx_prbs31_enable_1 = 1'b0; - assign qsfp1_cfg_tx_prbs31_enable_2 = 1'b0; - assign qsfp1_cfg_rx_prbs31_enable_2 = 1'b0; - assign qsfp1_cfg_tx_prbs31_enable_3 = 1'b0; - assign qsfp1_cfg_rx_prbs31_enable_3 = 1'b0; - assign qsfp1_cfg_tx_prbs31_enable_4 = 1'b0; - assign qsfp1_cfg_rx_prbs31_enable_4 = 1'b0; - -end - -endgenerate - -assign led[0] = ptp_pps_str; -assign led[2:1] = 0; - -wire [PORT_COUNT-1:0] eth_tx_clk; -wire [PORT_COUNT-1:0] eth_tx_rst; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_tx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_tx_tready; -wire [PORT_COUNT-1:0] axis_eth_tx_tlast; -wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts; -wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; - -wire [PORT_COUNT-1:0] eth_tx_enable; -wire [PORT_COUNT-1:0] eth_tx_status; -wire [PORT_COUNT-1:0] eth_tx_lfc_en; -wire [PORT_COUNT-1:0] eth_tx_lfc_req; -wire [PORT_COUNT*8-1:0] eth_tx_pfc_en; -wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; - -wire [PORT_COUNT-1:0] eth_rx_clk; -wire [PORT_COUNT-1:0] eth_rx_rst; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_rx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_rx_tready; -wire [PORT_COUNT-1:0] axis_eth_rx_tlast; -wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; - -wire [PORT_COUNT-1:0] eth_rx_enable; -wire [PORT_COUNT-1:0] eth_rx_status; -wire [PORT_COUNT-1:0] eth_rx_lfc_en; -wire [PORT_COUNT-1:0] eth_rx_lfc_req; -wire [PORT_COUNT-1:0] eth_rx_lfc_ack; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_en; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_req; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack; - -wire [PORT_COUNT-1:0] port_xgmii_tx_clk; -wire [PORT_COUNT-1:0] port_xgmii_tx_rst; -wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_txd; -wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_txc; - -wire [PORT_COUNT-1:0] port_xgmii_rx_clk; -wire [PORT_COUNT-1:0] port_xgmii_rx_rst; -wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_rxd; -wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_rxc; - -mqnic_port_map_phy_xgmii #( - .PHY_COUNT(8), - .PORT_MASK(PORT_MASK), - .PORT_GROUP_SIZE(4), - - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - - .PORT_COUNT(PORT_COUNT), - - .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), - .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH) -) -mqnic_port_map_phy_xgmii_inst ( - // towards PHY - .phy_xgmii_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), - .phy_xgmii_tx_rst({qsfp1_tx_rst_4, qsfp1_tx_rst_3, qsfp1_tx_rst_2, qsfp1_tx_rst_1, qsfp0_tx_rst_4, qsfp0_tx_rst_3, qsfp0_tx_rst_2, qsfp0_tx_rst_1}), - .phy_xgmii_txd({qsfp1_txd_4, qsfp1_txd_3, qsfp1_txd_2, qsfp1_txd_1, qsfp0_txd_4, qsfp0_txd_3, qsfp0_txd_2, qsfp0_txd_1}), - .phy_xgmii_txc({qsfp1_txc_4, qsfp1_txc_3, qsfp1_txc_2, qsfp1_txc_1, qsfp0_txc_4, qsfp0_txc_3, qsfp0_txc_2, qsfp0_txc_1}), - .phy_tx_status(8'hff), - - .phy_xgmii_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), - .phy_xgmii_rx_rst({qsfp1_rx_rst_4, qsfp1_rx_rst_3, qsfp1_rx_rst_2, qsfp1_rx_rst_1, qsfp0_rx_rst_4, qsfp0_rx_rst_3, qsfp0_rx_rst_2, qsfp0_rx_rst_1}), - .phy_xgmii_rxd({qsfp1_rxd_4, qsfp1_rxd_3, qsfp1_rxd_2, qsfp1_rxd_1, qsfp0_rxd_4, qsfp0_rxd_3, qsfp0_rxd_2, qsfp0_rxd_1}), - .phy_xgmii_rxc({qsfp1_rxc_4, qsfp1_rxc_3, qsfp1_rxc_2, qsfp1_rxc_1, qsfp0_rxc_4, qsfp0_rxc_3, qsfp0_rxc_2, qsfp0_rxc_1}), - .phy_rx_status({qsfp1_rx_status_4, qsfp1_rx_status_3, qsfp1_rx_status_2, qsfp1_rx_status_1, qsfp0_rx_status_4, qsfp0_rx_status_3, qsfp0_rx_status_2, qsfp0_rx_status_1}), - - // towards MAC - .port_xgmii_tx_clk(port_xgmii_tx_clk), - .port_xgmii_tx_rst(port_xgmii_tx_rst), - .port_xgmii_txd(port_xgmii_txd), - .port_xgmii_txc(port_xgmii_txc), - .port_tx_status(eth_tx_status), - - .port_xgmii_rx_clk(port_xgmii_rx_clk), - .port_xgmii_rx_rst(port_xgmii_rx_rst), - .port_xgmii_rxd(port_xgmii_rxd), - .port_xgmii_rxc(port_xgmii_rxc), - .port_rx_status(eth_rx_status) -); - -generate - genvar n; - - for (n = 0; n < PORT_COUNT; n = n + 1) begin : mac - - assign eth_tx_clk[n] = port_xgmii_tx_clk[n]; - assign eth_tx_rst[n] = port_xgmii_tx_rst[n]; - assign eth_rx_clk[n] = port_xgmii_rx_clk[n]; - assign eth_rx_rst[n] = port_xgmii_rx_rst[n]; - - eth_mac_10g #( - .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .ENABLE_PADDING(ENABLE_PADDING), - .ENABLE_DIC(ENABLE_DIC), - .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), - .PTP_PERIOD_NS(IF_PTP_PERIOD_NS), - .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS), - .TX_PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_PTP_TS_WIDTH(PTP_TS_WIDTH), - .TX_PTP_TS_CTRL_IN_TUSER(0), - .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE), - .TX_PTP_TAG_WIDTH(TX_TAG_WIDTH), - .RX_PTP_TS_ENABLE(PTP_TS_ENABLE), - .RX_PTP_TS_WIDTH(PTP_TS_WIDTH), - .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .PFC_ENABLE(PFC_ENABLE), - .PAUSE_ENABLE(LFC_ENABLE) - ) - eth_mac_inst ( - .tx_clk(port_xgmii_tx_clk[n]), - .tx_rst(port_xgmii_tx_rst[n]), - .rx_clk(port_xgmii_rx_clk[n]), - .rx_rst(port_xgmii_rx_rst[n]), - - /* - * AXI input - */ - .tx_axis_tdata(axis_eth_tx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), - .tx_axis_tkeep(axis_eth_tx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), - .tx_axis_tvalid(axis_eth_tx_tvalid[n +: 1]), - .tx_axis_tready(axis_eth_tx_tready[n +: 1]), - .tx_axis_tlast(axis_eth_tx_tlast[n +: 1]), - .tx_axis_tuser(axis_eth_tx_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]), - - /* - * AXI output - */ - .rx_axis_tdata(axis_eth_rx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), - .rx_axis_tkeep(axis_eth_rx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), - .rx_axis_tvalid(axis_eth_rx_tvalid[n +: 1]), - .rx_axis_tlast(axis_eth_rx_tlast[n +: 1]), - .rx_axis_tuser(axis_eth_rx_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]), - - /* - * XGMII interface - */ - .xgmii_rxd(port_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), - .xgmii_rxc(port_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), - .xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), - .xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), - - /* - * PTP - */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), - .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), - - /* - * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) - */ - .tx_lfc_req(eth_tx_lfc_req[n +: 1]), - .tx_lfc_resend(1'b0), - .rx_lfc_en(eth_rx_lfc_en[n +: 1]), - .rx_lfc_req(eth_rx_lfc_req[n +: 1]), - .rx_lfc_ack(eth_rx_lfc_ack[n +: 1]), - - /* - * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC) - */ - .tx_pfc_req(eth_tx_pfc_req[n*8 +: 8]), - .tx_pfc_resend(1'b0), - .rx_pfc_en(eth_rx_pfc_en[n*8 +: 8]), - .rx_pfc_req(eth_rx_pfc_req[n*8 +: 8]), - .rx_pfc_ack(eth_rx_pfc_ack[n*8 +: 8]), - - /* - * Pause interface - */ - .tx_lfc_pause_en(1'b1), - .tx_pause_req(1'b0), - .tx_pause_ack(), - - /* - * Status - */ - .tx_start_packet(), - .tx_error_underflow(), - .rx_start_packet(), - .rx_error_bad_frame(), - .rx_error_bad_fcs(), - .stat_tx_mcf(), - .stat_rx_mcf(), - .stat_tx_lfc_pkt(), - .stat_tx_lfc_xon(), - .stat_tx_lfc_xoff(), - .stat_tx_lfc_paused(), - .stat_tx_pfc_pkt(), - .stat_tx_pfc_xon(), - .stat_tx_pfc_xoff(), - .stat_tx_pfc_paused(), - .stat_rx_lfc_pkt(), - .stat_rx_lfc_xon(), - .stat_rx_lfc_xoff(), - .stat_rx_lfc_paused(), - .stat_rx_pfc_pkt(), - .stat_rx_pfc_xon(), - .stat_rx_pfc_xoff(), - .stat_rx_pfc_paused(), - - /* - * Configuration - */ - .cfg_ifg(8'd12), - .cfg_tx_enable(eth_tx_enable[n +: 1]), - .cfg_rx_enable(eth_rx_enable[n +: 1]), - .cfg_mcf_rx_eth_dst_mcast(48'h01_80_C2_00_00_01), - .cfg_mcf_rx_check_eth_dst_mcast(1'b1), - .cfg_mcf_rx_eth_dst_ucast(48'd0), - .cfg_mcf_rx_check_eth_dst_ucast(1'b0), - .cfg_mcf_rx_eth_src(48'd0), - .cfg_mcf_rx_check_eth_src(1'b0), - .cfg_mcf_rx_eth_type(16'h8808), - .cfg_mcf_rx_opcode_lfc(16'h0001), - .cfg_mcf_rx_check_opcode_lfc(eth_rx_lfc_en[n +: 1]), - .cfg_mcf_rx_opcode_pfc(16'h0101), - .cfg_mcf_rx_check_opcode_pfc(eth_rx_pfc_en[n*8 +: 8] != 0), - .cfg_mcf_rx_forward(1'b0), - .cfg_mcf_rx_enable(eth_rx_lfc_en[n +: 1] || eth_rx_pfc_en[n*8 +: 8]), - .cfg_tx_lfc_eth_dst(48'h01_80_C2_00_00_01), - .cfg_tx_lfc_eth_src(48'h80_23_31_43_54_4C), - .cfg_tx_lfc_eth_type(16'h8808), - .cfg_tx_lfc_opcode(16'h0001), - .cfg_tx_lfc_en(eth_tx_lfc_en[n +: 1]), - .cfg_tx_lfc_quanta(16'hffff), - .cfg_tx_lfc_refresh(16'h7fff), - .cfg_tx_pfc_eth_dst(48'h01_80_C2_00_00_01), - .cfg_tx_pfc_eth_src(48'h80_23_31_43_54_4C), - .cfg_tx_pfc_eth_type(16'h8808), - .cfg_tx_pfc_opcode(16'h0101), - .cfg_tx_pfc_en(eth_tx_pfc_en[n*8 +: 8] != 0), - .cfg_tx_pfc_quanta({8{16'hffff}}), - .cfg_tx_pfc_refresh({8{16'h7fff}}), - .cfg_rx_lfc_opcode(16'h0001), - .cfg_rx_lfc_en(eth_rx_lfc_en[n +: 1]), - .cfg_rx_pfc_opcode(16'h0101), - .cfg_rx_pfc_en(eth_rx_pfc_en[n*8 +: 8] != 0) - ); - - end - -endgenerate - -mqnic_core_pcie_us #( - // FW and board IDs - .FPGA_ID(FPGA_ID), - .FW_ID(FW_ID), - .FW_VER(FW_VER), - .BOARD_ID(BOARD_ID), - .BOARD_VER(BOARD_VER), - .BUILD_DATE(BUILD_DATE), - .GIT_HASH(GIT_HASH), - .RELEASE_INFO(RELEASE_INFO), - - // Structural configuration - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - .SCHED_PER_IF(SCHED_PER_IF), - - .PORT_COUNT(PORT_COUNT), - - // Clock configuration - .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), - .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), - - // PTP configuration - .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), - .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), - .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_TX_CLOCK(0), - .PTP_SEPARATE_RX_CLOCK(0), - .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), - - // Queue manager configuration - .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), - .EQN_WIDTH(EQN_WIDTH), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .CQN_WIDTH(CQN_WIDTH), - .EQ_PIPELINE(EQ_PIPELINE), - .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), - .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .CQ_PIPELINE(CQ_PIPELINE), - - // TX and RX engine configuration - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), - - // Scheduler configuration - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - - // Interface configuration - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_CPL_ENABLE(PTP_TS_ENABLE), - .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), - .TX_TAG_WIDTH(TX_TAG_WIDTH), - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .PFC_ENABLE(PFC_ENABLE), - .LFC_ENABLE(LFC_ENABLE), - .MAC_CTRL_ENABLE(0), - .TX_FIFO_DEPTH(TX_FIFO_DEPTH), - .RX_FIFO_DEPTH(RX_FIFO_DEPTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - - // RAM configuration - .DDR_CH(DDR_CH), - .DDR_ENABLE(DDR_ENABLE), - .DDR_GROUP_SIZE(1), - .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), - .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), - .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), - .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), - .AXI_DDR_AWUSER_ENABLE(0), - .AXI_DDR_WUSER_ENABLE(0), - .AXI_DDR_BUSER_ENABLE(0), - .AXI_DDR_ARUSER_ENABLE(0), - .AXI_DDR_RUSER_ENABLE(0), - .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), - .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), - .AXI_DDR_FIXED_BURST(0), - .AXI_DDR_WRAP_BURST(1), - .HBM_ENABLE(0), - - // Application block configuration - .APP_ID(APP_ID), - .APP_ENABLE(APP_ENABLE), - .APP_CTRL_ENABLE(APP_CTRL_ENABLE), - .APP_DMA_ENABLE(APP_DMA_ENABLE), - .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), - .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), - .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), - .APP_STAT_ENABLE(APP_STAT_ENABLE), - .APP_GPIO_IN_WIDTH(32), - .APP_GPIO_OUT_WIDTH(32), - - // DMA interface configuration - .DMA_IMM_ENABLE(DMA_IMM_ENABLE), - .DMA_IMM_WIDTH(DMA_IMM_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - - // PCIe interface configuration - .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), - .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), - .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), - .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), - .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), - .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), - .RC_STRADDLE(RC_STRADDLE), - .RQ_STRADDLE(RQ_STRADDLE), - .CQ_STRADDLE(CQ_STRADDLE), - .CC_STRADDLE(CC_STRADDLE), - .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), - .PF_COUNT(PF_COUNT), - .VF_COUNT(VF_COUNT), - .F_COUNT(F_COUNT), - .PCIE_TAG_COUNT(PCIE_TAG_COUNT), - - // Interrupt configuration - .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), - - // AXI lite interface configuration (control) - .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), - .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), - .RB_NEXT_PTR(RB_BASE_ADDR), - - // AXI lite interface configuration (application control) - .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), - .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), - - // Ethernet interface configuration - .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), - .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .AXIS_ETH_RX_USE_READY(0), - .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), - .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), - .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), - .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), - .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), - - // Statistics counter subsystem - .STAT_ENABLE(STAT_ENABLE), - .STAT_DMA_ENABLE(STAT_DMA_ENABLE), - .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), - .STAT_INC_WIDTH(STAT_INC_WIDTH), - .STAT_ID_WIDTH(STAT_ID_WIDTH) -) -core_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * AXI input (RC) - */ - .s_axis_rc_tdata(s_axis_rc_tdata), - .s_axis_rc_tkeep(s_axis_rc_tkeep), - .s_axis_rc_tvalid(s_axis_rc_tvalid), - .s_axis_rc_tready(s_axis_rc_tready), - .s_axis_rc_tlast(s_axis_rc_tlast), - .s_axis_rc_tuser(s_axis_rc_tuser), - - /* - * AXI output (RQ) - */ - .m_axis_rq_tdata(m_axis_rq_tdata), - .m_axis_rq_tkeep(m_axis_rq_tkeep), - .m_axis_rq_tvalid(m_axis_rq_tvalid), - .m_axis_rq_tready(m_axis_rq_tready), - .m_axis_rq_tlast(m_axis_rq_tlast), - .m_axis_rq_tuser(m_axis_rq_tuser), - - /* - * AXI input (CQ) - */ - .s_axis_cq_tdata(s_axis_cq_tdata), - .s_axis_cq_tkeep(s_axis_cq_tkeep), - .s_axis_cq_tvalid(s_axis_cq_tvalid), - .s_axis_cq_tready(s_axis_cq_tready), - .s_axis_cq_tlast(s_axis_cq_tlast), - .s_axis_cq_tuser(s_axis_cq_tuser), - - /* - * AXI output (CC) - */ - .m_axis_cc_tdata(m_axis_cc_tdata), - .m_axis_cc_tkeep(m_axis_cc_tkeep), - .m_axis_cc_tvalid(m_axis_cc_tvalid), - .m_axis_cc_tready(m_axis_cc_tready), - .m_axis_cc_tlast(m_axis_cc_tlast), - .m_axis_cc_tuser(m_axis_cc_tuser), - - /* - * Transmit sequence number input - */ - .s_axis_rq_seq_num_0(s_axis_rq_seq_num_0), - .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), - .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), - .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), - - /* - * Flow control - */ - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - /* - * Configuration inputs - */ - .cfg_max_read_req(cfg_max_read_req), - .cfg_max_payload(cfg_max_payload), - .cfg_rcb_status(cfg_rcb_status), - - /* - * Configuration interface - */ - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - - /* - * Interrupt interface - */ - .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), - .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), - .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), - .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), - .cfg_interrupt_msix_address(cfg_interrupt_msix_address), - .cfg_interrupt_msix_data(cfg_interrupt_msix_data), - .cfg_interrupt_msix_int(cfg_interrupt_msix_int), - .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), - .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), - .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), - .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - /* - * PCIe error outputs - */ - .status_error_cor(status_error_cor), - .status_error_uncor(status_error_uncor), - - /* - * AXI-Lite master interface (passthrough for NIC control and status) - */ - .m_axil_csr_awaddr(axil_csr_awaddr), - .m_axil_csr_awprot(axil_csr_awprot), - .m_axil_csr_awvalid(axil_csr_awvalid), - .m_axil_csr_awready(axil_csr_awready), - .m_axil_csr_wdata(axil_csr_wdata), - .m_axil_csr_wstrb(axil_csr_wstrb), - .m_axil_csr_wvalid(axil_csr_wvalid), - .m_axil_csr_wready(axil_csr_wready), - .m_axil_csr_bresp(axil_csr_bresp), - .m_axil_csr_bvalid(axil_csr_bvalid), - .m_axil_csr_bready(axil_csr_bready), - .m_axil_csr_araddr(axil_csr_araddr), - .m_axil_csr_arprot(axil_csr_arprot), - .m_axil_csr_arvalid(axil_csr_arvalid), - .m_axil_csr_arready(axil_csr_arready), - .m_axil_csr_rdata(axil_csr_rdata), - .m_axil_csr_rresp(axil_csr_rresp), - .m_axil_csr_rvalid(axil_csr_rvalid), - .m_axil_csr_rready(axil_csr_rready), - - /* - * Control register interface - */ - .ctrl_reg_wr_addr(ctrl_reg_wr_addr), - .ctrl_reg_wr_data(ctrl_reg_wr_data), - .ctrl_reg_wr_strb(ctrl_reg_wr_strb), - .ctrl_reg_wr_en(ctrl_reg_wr_en), - .ctrl_reg_wr_wait(ctrl_reg_wr_wait), - .ctrl_reg_wr_ack(ctrl_reg_wr_ack), - .ctrl_reg_rd_addr(ctrl_reg_rd_addr), - .ctrl_reg_rd_en(ctrl_reg_rd_en), - .ctrl_reg_rd_data(ctrl_reg_rd_data), - .ctrl_reg_rd_wait(ctrl_reg_rd_wait), - .ctrl_reg_rd_ack(ctrl_reg_rd_ack), - - /* - * PTP clock - */ - .ptp_clk(ptp_clk), - .ptp_rst(ptp_rst), - .ptp_sample_clk(ptp_sample_clk), - .ptp_pps(ptp_pps), - .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), - .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), - .ptp_perout_locked(ptp_perout_locked), - .ptp_perout_error(ptp_perout_error), - .ptp_perout_pulse(ptp_perout_pulse), - - /* - * Ethernet - */ - .eth_tx_clk(eth_tx_clk), - .eth_tx_rst(eth_tx_rst), - - .eth_tx_ptp_clk(0), - .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), - - .m_axis_eth_tx_tdata(axis_eth_tx_tdata), - .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), - .m_axis_eth_tx_tvalid(axis_eth_tx_tvalid), - .m_axis_eth_tx_tready(axis_eth_tx_tready), - .m_axis_eth_tx_tlast(axis_eth_tx_tlast), - .m_axis_eth_tx_tuser(axis_eth_tx_tuser), - - .s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts), - .s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag), - .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), - .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), - - .eth_tx_enable(eth_tx_enable), - .eth_tx_status(eth_tx_status), - .eth_tx_lfc_en(eth_tx_lfc_en), - .eth_tx_lfc_req(eth_tx_lfc_req), - .eth_tx_pfc_en(eth_tx_pfc_en), - .eth_tx_pfc_req(eth_tx_pfc_req), - .eth_tx_fc_quanta_clk_en(0), - - .eth_rx_clk(eth_rx_clk), - .eth_rx_rst(eth_rx_rst), - - .eth_rx_ptp_clk(0), - .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), - - .s_axis_eth_rx_tdata(axis_eth_rx_tdata), - .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), - .s_axis_eth_rx_tvalid(axis_eth_rx_tvalid), - .s_axis_eth_rx_tready(axis_eth_rx_tready), - .s_axis_eth_rx_tlast(axis_eth_rx_tlast), - .s_axis_eth_rx_tuser(axis_eth_rx_tuser), - - .eth_rx_enable(eth_rx_enable), - .eth_rx_status(eth_rx_status), - .eth_rx_lfc_en(eth_rx_lfc_en), - .eth_rx_lfc_req(eth_rx_lfc_req), - .eth_rx_lfc_ack(eth_rx_lfc_ack), - .eth_rx_pfc_en(eth_rx_pfc_en), - .eth_rx_pfc_req(eth_rx_pfc_req), - .eth_rx_pfc_ack(eth_rx_pfc_ack), - .eth_rx_fc_quanta_clk_en(0), - - /* - * DDR - */ - .ddr_clk(ddr_clk), - .ddr_rst(ddr_rst), - - .m_axi_ddr_awid(m_axi_ddr_awid), - .m_axi_ddr_awaddr(m_axi_ddr_awaddr), - .m_axi_ddr_awlen(m_axi_ddr_awlen), - .m_axi_ddr_awsize(m_axi_ddr_awsize), - .m_axi_ddr_awburst(m_axi_ddr_awburst), - .m_axi_ddr_awlock(m_axi_ddr_awlock), - .m_axi_ddr_awcache(m_axi_ddr_awcache), - .m_axi_ddr_awprot(m_axi_ddr_awprot), - .m_axi_ddr_awqos(m_axi_ddr_awqos), - .m_axi_ddr_awuser(), - .m_axi_ddr_awvalid(m_axi_ddr_awvalid), - .m_axi_ddr_awready(m_axi_ddr_awready), - .m_axi_ddr_wdata(m_axi_ddr_wdata), - .m_axi_ddr_wstrb(m_axi_ddr_wstrb), - .m_axi_ddr_wlast(m_axi_ddr_wlast), - .m_axi_ddr_wuser(), - .m_axi_ddr_wvalid(m_axi_ddr_wvalid), - .m_axi_ddr_wready(m_axi_ddr_wready), - .m_axi_ddr_bid(m_axi_ddr_bid), - .m_axi_ddr_bresp(m_axi_ddr_bresp), - .m_axi_ddr_buser(0), - .m_axi_ddr_bvalid(m_axi_ddr_bvalid), - .m_axi_ddr_bready(m_axi_ddr_bready), - .m_axi_ddr_arid(m_axi_ddr_arid), - .m_axi_ddr_araddr(m_axi_ddr_araddr), - .m_axi_ddr_arlen(m_axi_ddr_arlen), - .m_axi_ddr_arsize(m_axi_ddr_arsize), - .m_axi_ddr_arburst(m_axi_ddr_arburst), - .m_axi_ddr_arlock(m_axi_ddr_arlock), - .m_axi_ddr_arcache(m_axi_ddr_arcache), - .m_axi_ddr_arprot(m_axi_ddr_arprot), - .m_axi_ddr_arqos(m_axi_ddr_arqos), - .m_axi_ddr_aruser(), - .m_axi_ddr_arvalid(m_axi_ddr_arvalid), - .m_axi_ddr_arready(m_axi_ddr_arready), - .m_axi_ddr_rid(m_axi_ddr_rid), - .m_axi_ddr_rdata(m_axi_ddr_rdata), - .m_axi_ddr_rresp(m_axi_ddr_rresp), - .m_axi_ddr_rlast(m_axi_ddr_rlast), - .m_axi_ddr_ruser(0), - .m_axi_ddr_rvalid(m_axi_ddr_rvalid), - .m_axi_ddr_rready(m_axi_ddr_rready), - - .ddr_status(ddr_status), - - /* - * HBM - */ - .hbm_clk(0), - .hbm_rst(0), - - .m_axi_hbm_awid(), - .m_axi_hbm_awaddr(), - .m_axi_hbm_awlen(), - .m_axi_hbm_awsize(), - .m_axi_hbm_awburst(), - .m_axi_hbm_awlock(), - .m_axi_hbm_awcache(), - .m_axi_hbm_awprot(), - .m_axi_hbm_awqos(), - .m_axi_hbm_awuser(), - .m_axi_hbm_awvalid(), - .m_axi_hbm_awready(0), - .m_axi_hbm_wdata(), - .m_axi_hbm_wstrb(), - .m_axi_hbm_wlast(), - .m_axi_hbm_wuser(), - .m_axi_hbm_wvalid(), - .m_axi_hbm_wready(0), - .m_axi_hbm_bid(0), - .m_axi_hbm_bresp(0), - .m_axi_hbm_buser(0), - .m_axi_hbm_bvalid(0), - .m_axi_hbm_bready(), - .m_axi_hbm_arid(), - .m_axi_hbm_araddr(), - .m_axi_hbm_arlen(), - .m_axi_hbm_arsize(), - .m_axi_hbm_arburst(), - .m_axi_hbm_arlock(), - .m_axi_hbm_arcache(), - .m_axi_hbm_arprot(), - .m_axi_hbm_arqos(), - .m_axi_hbm_aruser(), - .m_axi_hbm_arvalid(), - .m_axi_hbm_arready(0), - .m_axi_hbm_rid(0), - .m_axi_hbm_rdata(0), - .m_axi_hbm_rresp(0), - .m_axi_hbm_rlast(0), - .m_axi_hbm_ruser(0), - .m_axi_hbm_rvalid(0), - .m_axi_hbm_rready(), - - .hbm_status(0), - - /* - * Statistics input - */ - .s_axis_stat_tdata(0), - .s_axis_stat_tid(0), - .s_axis_stat_tvalid(1'b0), - .s_axis_stat_tready(), - - /* - * GPIO - */ - .app_gpio_in(0), - .app_gpio_out(), - - /* - * JTAG - */ - .app_jtag_tdi(1'b0), - .app_jtag_tdo(), - .app_jtag_tms(1'b0), - .app_jtag_tck(1'b0) -); - -endmodule - -`resetall diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/sync_signal.v b/fpga/mqnic/AU250/fpga_25g/rtl/sync_signal.v deleted file mode 100644 index 74b855fa1..000000000 --- a/fpga/mqnic/AU250/fpga_25g/rtl/sync_signal.v +++ /dev/null @@ -1,62 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog-2001 - -`resetall -`timescale 1 ns / 1 ps -`default_nettype none - -/* - * Synchronizes an asyncronous signal to a given clock by using a pipeline of - * two registers. - */ -module sync_signal #( - parameter WIDTH=1, // width of the input and output signals - parameter N=2 // depth of synchronizer -)( - input wire clk, - input wire [WIDTH-1:0] in, - output wire [WIDTH-1:0] out -); - -reg [WIDTH-1:0] sync_reg[N-1:0]; - -/* - * The synchronized output is the last register in the pipeline. - */ -assign out = sync_reg[N-1]; - -integer k; - -always @(posedge clk) begin - sync_reg[0] <= in; - for (k = 1; k < N; k = k + 1) begin - sync_reg[k] <= sync_reg[k-1]; - end -end - -endmodule - -`resetall diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile deleted file mode 100644 index a480035a9..000000000 --- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile +++ /dev/null @@ -1,261 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2020-2023 The Regents of the University of California - -TOPLEVEL_LANG = verilog - -SIM ?= icarus -WAVES ?= 0 - -COCOTB_HDL_TIMEUNIT = 1ns -COCOTB_HDL_TIMEPRECISION = 1ps - -DUT = fpga_core -TOPLEVEL = $(DUT) -MODULE = test_$(DUT) -VERILOG_SOURCES += ../../rtl/$(DUT).v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core.v -VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v -VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v -VERILOG_SOURCES += ../../rtl/common/cpl_write.v -VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v -VERILOG_SOURCES += ../../rtl/common/desc_fetch.v -VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/queue_manager.v -VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v -VERILOG_SOURCES += ../../rtl/common/tx_fifo.v -VERILOG_SOURCES += ../../rtl/common/rx_fifo.v -VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v -VERILOG_SOURCES += ../../rtl/common/tx_engine.v -VERILOG_SOURCES += ../../rtl/common/rx_engine.v -VERILOG_SOURCES += ../../rtl/common/tx_checksum.v -VERILOG_SOURCES += ../../rtl/common/rx_hash.v -VERILOG_SOURCES += ../../rtl/common/rx_checksum.v -VERILOG_SOURCES += ../../rtl/common/rb_drp.v -VERILOG_SOURCES += ../../rtl/common/stats_counter.v -VERILOG_SOURCES += ../../rtl/common/stats_collect.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v -VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v -VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v -VERILOG_SOURCES += ../../rtl/common/tdma_ber.v -VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v -VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v -VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v -VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v -VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v -VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v -VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v - -# module parameters - -# Structural configuration -export PARAM_IF_COUNT := 2 -export PARAM_PORTS_PER_IF := 1 -export PARAM_SCHED_PER_IF := $(PARAM_PORTS_PER_IF) -export PARAM_PORT_MASK := 0 - -# Clock configuration -export PARAM_CLK_PERIOD_NS_NUM := 4 -export PARAM_CLK_PERIOD_NS_DENOM := 1 - -# PTP configuration -export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 -export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 -export PARAM_PTP_CLOCK_PIPELINE := 0 -export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_PORT_CDC_PIPELINE := 0 -export PARAM_PTP_PEROUT_ENABLE := 0 -export PARAM_PTP_PEROUT_COUNT := 1 - -# Queue manager configuration -export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_CQ_OP_TABLE_SIZE := 32 -export PARAM_EQN_WIDTH := 6 -export PARAM_TX_QUEUE_INDEX_WIDTH := 13 -export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") -export PARAM_EQ_PIPELINE := 3 -export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") - -# TX and RX engine configuration -export PARAM_TX_DESC_TABLE_SIZE := 32 -export PARAM_RX_DESC_TABLE_SIZE := 32 -export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") - -# Scheduler configuration -export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) -export PARAM_TX_SCHEDULER_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_TDMA_INDEX_WIDTH := 6 - -# Interface configuration -export PARAM_PTP_TS_ENABLE := 1 -export PARAM_TX_CPL_FIFO_DEPTH := 32 -export PARAM_TX_CHECKSUM_ENABLE := 1 -export PARAM_RX_HASH_ENABLE := 1 -export PARAM_RX_CHECKSUM_ENABLE := 1 -export PARAM_LFC_ENABLE := 1 -export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) -export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 -export PARAM_MAX_TX_SIZE := 9214 -export PARAM_MAX_RX_SIZE := 9214 -export PARAM_TX_RAM_SIZE := 32768 -export PARAM_RX_RAM_SIZE := 131072 - -# Application block configuration -export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) -export PARAM_APP_ENABLE := 0 -export PARAM_APP_CTRL_ENABLE := 1 -export PARAM_APP_DMA_ENABLE := 1 -export PARAM_APP_AXIS_DIRECT_ENABLE := 1 -export PARAM_APP_AXIS_SYNC_ENABLE := 1 -export PARAM_APP_AXIS_IF_ENABLE := 1 -export PARAM_APP_STAT_ENABLE := 1 - -# DMA interface configuration -export PARAM_DMA_IMM_ENABLE := 0 -export PARAM_DMA_IMM_WIDTH := 32 -export PARAM_DMA_LEN_WIDTH := 16 -export PARAM_DMA_TAG_WIDTH := 16 -export PARAM_RAM_ADDR_WIDTH := $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())") -export PARAM_RAM_PIPELINE := 2 - -# PCIe interface configuration -export PARAM_AXIS_PCIE_DATA_WIDTH := 512 -export PARAM_PF_COUNT := 1 -export PARAM_VF_COUNT := 0 - -# Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) - -# AXI lite interface configuration (control) -export PARAM_AXIL_CTRL_DATA_WIDTH := 32 -export PARAM_AXIL_CTRL_ADDR_WIDTH := 24 - -# AXI lite interface configuration (application control) -export PARAM_AXIL_APP_CTRL_DATA_WIDTH := $(PARAM_AXIL_CTRL_DATA_WIDTH) -export PARAM_AXIL_APP_CTRL_ADDR_WIDTH := 24 - -# Ethernet interface configuration -export PARAM_AXIS_ETH_TX_PIPELINE := 4 -export PARAM_AXIS_ETH_TX_FIFO_PIPELINE := 4 -export PARAM_AXIS_ETH_TX_TS_PIPELINE := 4 -export PARAM_AXIS_ETH_RX_PIPELINE := 4 -export PARAM_AXIS_ETH_RX_FIFO_PIPELINE := 4 - -# Statistics counter subsystem -export PARAM_STAT_ENABLE := 1 -export PARAM_STAT_DMA_ENABLE := 1 -export PARAM_STAT_PCIE_ENABLE := 1 -export PARAM_STAT_INC_WIDTH := 24 -export PARAM_STAT_ID_WIDTH := 12 - -ifeq ($(SIM), icarus) - PLUSARGS += -fst - - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif -else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - COMPILE_ARGS += --trace-fst - endif -endif - -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/mqnic.py b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/mqnic.py deleted file mode 120000 index dfa8522e7..000000000 --- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/mqnic.py +++ /dev/null @@ -1 +0,0 @@ -../../../../../common/tb/mqnic.py \ No newline at end of file diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py deleted file mode 100644 index 51914360e..000000000 --- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py +++ /dev/null @@ -1,812 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2020-2023 The Regents of the University of California - -import logging -import os -import struct -import sys - -import scapy.utils -from scapy.layers.l2 import Ether -from scapy.layers.inet import IP, UDP - -import cocotb_test.simulator - -import cocotb -from cocotb.log import SimLog -from cocotb.clock import Clock -from cocotb.triggers import RisingEdge, FallingEdge, Timer - -from cocotbext.axi import AxiStreamBus, AxiLiteBus, AxiLiteRam -from cocotbext.eth import XgmiiSource, XgmiiSink, XgmiiFrame -from cocotbext.pcie.core import RootComplex -from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice - -try: - import mqnic -except ImportError: - # attempt import from current directory - sys.path.insert(0, os.path.join(os.path.dirname(__file__))) - try: - import mqnic - finally: - del sys.path[0] - - -class TB(object): - def __init__(self, dut, msix_count=32): - self.dut = dut - - self.log = SimLog("cocotb.tb") - self.log.setLevel(logging.DEBUG) - - # PCIe - self.rc = RootComplex() - - self.rc.max_payload_size = 0x1 # 256 bytes - self.rc.max_read_request_size = 0x2 # 512 bytes - - self.dev = UltraScalePlusPcieDevice( - # configuration options - pcie_generation=3, - pcie_link_width=16, - user_clk_frequency=250e6, - alignment="dword", - cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1, - cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1, - rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1, - rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1, - rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2, - pf_count=1, - max_payload_size=1024, - enable_client_tag=True, - enable_extended_tag=True, - enable_parity=False, - enable_rx_msg_interface=False, - enable_sriov=False, - enable_extended_configuration=False, - - pf0_msi_enable=False, - pf0_msi_count=32, - pf1_msi_enable=False, - pf1_msi_count=1, - pf2_msi_enable=False, - pf2_msi_count=1, - pf3_msi_enable=False, - pf3_msi_count=1, - pf0_msix_enable=True, - pf0_msix_table_size=msix_count-1, - pf0_msix_table_bir=0, - pf0_msix_table_offset=0x00010000, - pf0_msix_pba_bir=0, - pf0_msix_pba_offset=0x00018000, - pf1_msix_enable=False, - pf1_msix_table_size=0, - pf1_msix_table_bir=0, - pf1_msix_table_offset=0x00000000, - pf1_msix_pba_bir=0, - pf1_msix_pba_offset=0x00000000, - pf2_msix_enable=False, - pf2_msix_table_size=0, - pf2_msix_table_bir=0, - pf2_msix_table_offset=0x00000000, - pf2_msix_pba_bir=0, - pf2_msix_pba_offset=0x00000000, - pf3_msix_enable=False, - pf3_msix_table_size=0, - pf3_msix_table_bir=0, - pf3_msix_table_offset=0x00000000, - pf3_msix_pba_bir=0, - pf3_msix_pba_offset=0x00000000, - - # signals - # Clock and Reset Interface - user_clk=dut.clk_250mhz, - user_reset=dut.rst_250mhz, - # user_lnk_up - # sys_clk - # sys_clk_gt - # sys_reset - # phy_rdy_out - - # Requester reQuest Interface - rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), - pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, - pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, - pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, - pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, - # pcie_rq_tag0 - # pcie_rq_tag1 - # pcie_rq_tag_av - # pcie_rq_tag_vld0 - # pcie_rq_tag_vld1 - - # Requester Completion Interface - rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), - - # Completer reQuest Interface - cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), - # pcie_cq_np_req - # pcie_cq_np_req_count - - # Completer Completion Interface - cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), - - # Transmit Flow Control Interface - # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, - # pcie_tfc_npd_av=dut.pcie_tfc_npd_av, - - # Configuration Management Interface - cfg_mgmt_addr=dut.cfg_mgmt_addr, - cfg_mgmt_function_number=dut.cfg_mgmt_function_number, - cfg_mgmt_write=dut.cfg_mgmt_write, - cfg_mgmt_write_data=dut.cfg_mgmt_write_data, - cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable, - cfg_mgmt_read=dut.cfg_mgmt_read, - cfg_mgmt_read_data=dut.cfg_mgmt_read_data, - cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done, - # cfg_mgmt_debug_access - - # Configuration Status Interface - # cfg_phy_link_down - # cfg_phy_link_status - # cfg_negotiated_width - # cfg_current_speed - cfg_max_payload=dut.cfg_max_payload, - cfg_max_read_req=dut.cfg_max_read_req, - # cfg_function_status - # cfg_vf_status - # cfg_function_power_state - # cfg_vf_power_state - # cfg_link_power_state - # cfg_err_cor_out - # cfg_err_nonfatal_out - # cfg_err_fatal_out - # cfg_local_error_out - # cfg_local_error_valid - # cfg_rx_pm_state - # cfg_tx_pm_state - # cfg_ltssm_state - cfg_rcb_status=dut.cfg_rcb_status, - # cfg_obff_enable - # cfg_pl_status_change - # cfg_tph_requester_enable - # cfg_tph_st_mode - # cfg_vf_tph_requester_enable - # cfg_vf_tph_st_mode - - # Configuration Received Message Interface - # cfg_msg_received - # cfg_msg_received_data - # cfg_msg_received_type - - # Configuration Transmit Message Interface - # cfg_msg_transmit - # cfg_msg_transmit_type - # cfg_msg_transmit_data - # cfg_msg_transmit_done - - # Configuration Flow Control Interface - cfg_fc_ph=dut.cfg_fc_ph, - cfg_fc_pd=dut.cfg_fc_pd, - cfg_fc_nph=dut.cfg_fc_nph, - cfg_fc_npd=dut.cfg_fc_npd, - cfg_fc_cplh=dut.cfg_fc_cplh, - cfg_fc_cpld=dut.cfg_fc_cpld, - cfg_fc_sel=dut.cfg_fc_sel, - - # Configuration Control Interface - # cfg_hot_reset_in - # cfg_hot_reset_out - # cfg_config_space_enable - # cfg_dsn - # cfg_bus_number - # cfg_ds_port_number - # cfg_ds_bus_number - # cfg_ds_device_number - # cfg_ds_function_number - # cfg_power_state_change_ack - # cfg_power_state_change_interrupt - cfg_err_cor_in=dut.status_error_cor, - cfg_err_uncor_in=dut.status_error_uncor, - # cfg_flr_in_process - # cfg_flr_done - # cfg_vf_flr_in_process - # cfg_vf_flr_func_num - # cfg_vf_flr_done - # cfg_pm_aspm_l1_entry_reject - # cfg_pm_aspm_tx_l0s_entry_disable - # cfg_req_pm_transition_l23_ready - # cfg_link_training_enable - - # Configuration Interrupt Controller Interface - # cfg_interrupt_int - # cfg_interrupt_sent - # cfg_interrupt_pending - # cfg_interrupt_msi_enable - # cfg_interrupt_msi_mmenable - # cfg_interrupt_msi_mask_update - # cfg_interrupt_msi_data - # cfg_interrupt_msi_select - # cfg_interrupt_msi_int - # cfg_interrupt_msi_pending_status - # cfg_interrupt_msi_pending_status_data_enable - # cfg_interrupt_msi_pending_status_function_num - # cfg_interrupt_msi_sent - # cfg_interrupt_msi_fail - cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable, - cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask, - cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable, - cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask, - cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address, - cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data, - cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int, - cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending, - cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status, - cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent, - cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail, - # cfg_interrupt_msi_attr - # cfg_interrupt_msi_tph_present - # cfg_interrupt_msi_tph_type - # cfg_interrupt_msi_tph_st_tag - cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, - - # Configuration Extend Interface - # cfg_ext_read_received - # cfg_ext_write_received - # cfg_ext_register_number - # cfg_ext_function_number - # cfg_ext_write_data - # cfg_ext_write_byte_enable - # cfg_ext_read_data - # cfg_ext_read_data_valid - ) - - # self.dev.log.setLevel(logging.DEBUG) - - self.rc.make_port().connect(self.dev) - - self.driver = mqnic.Driver() - - self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) - if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): - self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) - - cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start()) - dut.ptp_rst.setimmediatevalue(0) - cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start()) - - # Ethernet - self.qsfp_source = [] - self.qsfp_sink = [] - - for x in range(2): - sources = [] - sinks = [] - for y in range(1, 5): - cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_rx_clk_{y}"), 2.56, units="ns").start()) - source = XgmiiSource(getattr(dut, f"qsfp{x}_rxd_{y}"), getattr(dut, f"qsfp{x}_rxc_{y}"), getattr(dut, f"qsfp{x}_rx_clk_{y}"), getattr(dut, f"qsfp{x}_rx_rst_{y}")) - sources.append(source) - cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_tx_clk_{y}"), 2.56, units="ns").start()) - sink = XgmiiSink(getattr(dut, f"qsfp{x}_txd_{y}"), getattr(dut, f"qsfp{x}_txc_{y}"), getattr(dut, f"qsfp{x}_tx_clk_{y}"), getattr(dut, f"qsfp{x}_tx_rst_{y}")) - sinks.append(sink) - getattr(dut, f"qsfp{x}_rx_status_{y}").setimmediatevalue(1) - getattr(dut, f"qsfp{x}_rx_error_count_{y}").setimmediatevalue(0) - self.qsfp_source.append(sources) - self.qsfp_sink.append(sinks) - - cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_drp_clk"), 8, units="ns").start()) - getattr(dut, f"qsfp{x}_drp_rst").setimmediatevalue(0) - getattr(dut, f"qsfp{x}_drp_do").setimmediatevalue(0) - getattr(dut, f"qsfp{x}_drp_rdy").setimmediatevalue(0) - - getattr(dut, f"qsfp{x}_modprsl").setimmediatevalue(0) - getattr(dut, f"qsfp{x}_intl").setimmediatevalue(1) - - dut.sw.setimmediatevalue(0) - - dut.i2c_scl_i.setimmediatevalue(1) - dut.i2c_sda_i.setimmediatevalue(1) - - dut.qspi_dq_i.setimmediatevalue(0) - - self.cms_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil_cms"), dut.m_axil_cms_clk, dut.m_axil_cms_rst, size=256*1024) - - self.loopback_enable = False - cocotb.start_soon(self._run_loopback()) - - async def init(self): - - self.dut.ptp_rst.setimmediatevalue(0) - for x in range(2): - for y in range(1, 5): - getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(0) - getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(0) - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.ptp_rst.setimmediatevalue(1) - for x in range(2): - for y in range(1, 5): - getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(1) - getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(1) - - await FallingEdge(self.dut.rst_250mhz) - await Timer(100, 'ns') - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.ptp_rst.setimmediatevalue(0) - for x in range(2): - for y in range(1, 5): - getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(0) - getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(0) - - await self.rc.enumerate() - - async def _run_loopback(self): - while True: - await RisingEdge(self.dut.clk_250mhz) - - if self.loopback_enable: - for x in range(len(self.qsfp_sink)): - for y in range(len(self.qsfp_sink[x])): - if not self.qsfp_sink[x][y].empty(): - await self.qsfp_source[x][y].send(await self.qsfp_sink[x][y].recv()) - - -@cocotb.test() -async def run_test_nic(dut): - - tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index)) - - await tb.init() - - tb.log.info("Init driver") - await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id)) - await tb.driver.interfaces[0].open() - # await tb.driver.interfaces[1].open() - - # enable queues - tb.log.info("Enable queues") - await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) - for k in range(len(tb.driver.interfaces[0].txq)): - await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003) - - # wait for all writes to complete - await tb.driver.hw_regs.read_dword(0) - tb.log.info("Init complete") - - tb.log.info("Send and receive single packet") - - data = bytearray([x % 256 for x in range(1024)]) - - await tb.driver.interfaces[0].start_xmit(data, 0) - - pkt = await tb.qsfp_sink[0][0].recv() - tb.log.info("Packet: %s", pkt) - - await tb.qsfp_source[0][0].send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - # await tb.driver.interfaces[1].start_xmit(data, 0) - - # pkt = await tb.qsfp_sink[1][0].recv() - # tb.log.info("Packet: %s", pkt) - - # await tb.qsfp_source[1][0].send(pkt) - - # pkt = await tb.driver.interfaces[1].recv() - - # tb.log.info("Packet: %s", pkt) - # assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.log.info("RX and TX checksum tests") - - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') - ip = IP(src='192.168.1.100', dst='192.168.1.101') - udp = UDP(sport=1, dport=2) - test_pkt = eth / ip / udp / payload - - test_pkt2 = test_pkt.copy() - test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) - - await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - - pkt = await tb.qsfp_sink[0][0].recv() - tb.log.info("Packet: %s", pkt) - - await tb.qsfp_source[0][0].send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - assert Ether(pkt.data).build() == test_pkt.build() - - tb.log.info("Queue mapping offset test") - - data = bytearray([x % 256 for x in range(1024)]) - - tb.loopback_enable = True - - for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) - - await tb.driver.interfaces[0].start_xmit(data, 0) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - assert pkt.queue == k - - tb.loopback_enable = False - - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) - - tb.log.info("Queue mapping RSS mask test") - - await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) - - for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) - - tb.loopback_enable = True - - queues = set() - - for k in range(64): - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') - ip = IP(src='192.168.1.100', dst='192.168.1.101') - udp = UDP(sport=1, dport=k+0) - test_pkt = eth / ip / udp / payload - - test_pkt2 = test_pkt.copy() - test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) - - await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - - for k in range(64): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - queues.add(pkt.queue) - - assert len(queues) == 4 - - tb.loopback_enable = False - - await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0) - - tb.log.info("Multiple small packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - tb.log.info("Multiple large packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - if tb.driver.interfaces[0].if_feature_lfc: - tb.log.info("Test LFC pause frame RX") - - await tb.driver.interfaces[0].ports[0].set_lfc_ctrl(mqnic.MQNIC_PORT_LFC_CTRL_TX_LFC_EN | mqnic.MQNIC_PORT_LFC_CTRL_RX_LFC_EN) - await tb.driver.hw_regs.read_dword(0) - - lfc_xoff = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) / struct.pack('!HH', 0x0001, 2000) - - await tb.qsfp_source[0][0].send(XgmiiFrame.from_payload(bytes(lfc_xoff))) - - count = 16 - - pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - if tb.driver.interfaces[0].if_feature_rx_csum: - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - await RisingEdge(dut.clk_250mhz) - await RisingEdge(dut.clk_250mhz) - - -# cocotb-test - -tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) -app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app')) -axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl')) -axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) -eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) -pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl')) - - -def test_fpga_core(request): - dut = "fpga_core" - module = os.path.splitext(os.path.basename(__file__))[0] - toplevel = dut - - verilog_sources = [ - os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), - os.path.join(rtl_dir, "common", "mqnic_core.v"), - os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), - os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), - os.path.join(rtl_dir, "common", "mqnic_port_tx.v"), - os.path.join(rtl_dir, "common", "mqnic_port_rx.v"), - os.path.join(rtl_dir, "common", "mqnic_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), - os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), - os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), - os.path.join(rtl_dir, "common", "cpl_write.v"), - os.path.join(rtl_dir, "common", "cpl_op_mux.v"), - os.path.join(rtl_dir, "common", "desc_fetch.v"), - os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "queue_manager.v"), - os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), - os.path.join(rtl_dir, "common", "tx_fifo.v"), - os.path.join(rtl_dir, "common", "rx_fifo.v"), - os.path.join(rtl_dir, "common", "tx_req_mux.v"), - os.path.join(rtl_dir, "common", "tx_engine.v"), - os.path.join(rtl_dir, "common", "rx_engine.v"), - os.path.join(rtl_dir, "common", "tx_checksum.v"), - os.path.join(rtl_dir, "common", "rx_hash.v"), - os.path.join(rtl_dir, "common", "rx_checksum.v"), - os.path.join(rtl_dir, "common", "rb_drp.v"), - os.path.join(rtl_dir, "common", "stats_counter.v"), - os.path.join(rtl_dir, "common", "stats_collect.v"), - os.path.join(rtl_dir, "common", "stats_pcie_if.v"), - os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"), - os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"), - os.path.join(rtl_dir, "common", "stats_dma_latency.v"), - os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), - os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(rtl_dir, "common", "tdma_scheduler.v"), - os.path.join(rtl_dir, "common", "tdma_ber.v"), - os.path.join(rtl_dir, "common", "tdma_ber_ch.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), - os.path.join(eth_rtl_dir, "mac_ctrl_rx.v"), - os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"), - os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), - os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), - os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), - os.path.join(eth_rtl_dir, "ptp_perout.v"), - os.path.join(axi_rtl_dir, "axil_interconnect.v"), - os.path.join(axi_rtl_dir, "axil_crossbar.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"), - os.path.join(axi_rtl_dir, "axil_reg_if.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"), - os.path.join(axi_rtl_dir, "axil_register_rd.v"), - os.path.join(axi_rtl_dir, "axil_register_wr.v"), - os.path.join(axi_rtl_dir, "arbiter.v"), - os.path.join(axi_rtl_dir, "priority_encoder.v"), - os.path.join(axis_rtl_dir, "axis_adapter.v"), - os.path.join(axis_rtl_dir, "axis_arb_mux.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_demux.v"), - os.path.join(axis_rtl_dir, "axis_fifo.v"), - os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), - os.path.join(axis_rtl_dir, "axis_register.v"), - os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), - os.path.join(pcie_rtl_dir, "pcie_msix.v"), - os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_psdpram.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), - os.path.join(pcie_rtl_dir, "pulse_merge.v"), - ] - - parameters = {} - - # Structural configuration - parameters['IF_COUNT'] = 2 - parameters['PORTS_PER_IF'] = 1 - parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] - parameters['PORT_MASK'] = 0 - - # Clock configuration - parameters['CLK_PERIOD_NS_NUM'] = 4 - parameters['CLK_PERIOD_NS_DENOM'] = 1 - - # PTP configuration - parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 - parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 - parameters['PTP_CLOCK_PIPELINE'] = 0 - parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_PORT_CDC_PIPELINE'] = 0 - parameters['PTP_PEROUT_ENABLE'] = 0 - parameters['PTP_PEROUT_COUNT'] = 1 - - # Queue manager configuration - parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['CQ_OP_TABLE_SIZE'] = 32 - parameters['EQN_WIDTH'] = 6 - parameters['TX_QUEUE_INDEX_WIDTH'] = 13 - parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 - parameters['EQ_PIPELINE'] = 3 - parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) - - # TX and RX engine configuration - parameters['TX_DESC_TABLE_SIZE'] = 32 - parameters['RX_DESC_TABLE_SIZE'] = 32 - parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) - - # Scheduler configuration - parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] - parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['TDMA_INDEX_WIDTH'] = 6 - - # Interface configuration - parameters['PTP_TS_ENABLE'] = 1 - parameters['TX_CPL_FIFO_DEPTH'] = 32 - parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_HASH_ENABLE'] = 1 - parameters['RX_CHECKSUM_ENABLE'] = 1 - parameters['LFC_ENABLE'] = 1 - parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] - parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 - parameters['MAX_TX_SIZE'] = 9214 - parameters['MAX_RX_SIZE'] = 9214 - parameters['TX_RAM_SIZE'] = 32768 - parameters['RX_RAM_SIZE'] = 131072 - - # Application block configuration - parameters['APP_ID'] = 0x00000000 - parameters['APP_ENABLE'] = 0 - parameters['APP_CTRL_ENABLE'] = 1 - parameters['APP_DMA_ENABLE'] = 1 - parameters['APP_AXIS_DIRECT_ENABLE'] = 1 - parameters['APP_AXIS_SYNC_ENABLE'] = 1 - parameters['APP_AXIS_IF_ENABLE'] = 1 - parameters['APP_STAT_ENABLE'] = 1 - - # DMA interface configuration - parameters['DMA_IMM_ENABLE'] = 0 - parameters['DMA_IMM_WIDTH'] = 32 - parameters['DMA_LEN_WIDTH'] = 16 - parameters['DMA_TAG_WIDTH'] = 16 - parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length() - parameters['RAM_PIPELINE'] = 2 - - # PCIe interface configuration - parameters['AXIS_PCIE_DATA_WIDTH'] = 512 - parameters['PF_COUNT'] = 1 - parameters['VF_COUNT'] = 0 - - # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] - - # AXI lite interface configuration (control) - parameters['AXIL_CTRL_DATA_WIDTH'] = 32 - parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 - - # AXI lite interface configuration (application control) - parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH'] - parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24 - - # Ethernet interface configuration - parameters['AXIS_ETH_TX_PIPELINE'] = 4 - parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 4 - parameters['AXIS_ETH_TX_TS_PIPELINE'] = 4 - parameters['AXIS_ETH_RX_PIPELINE'] = 4 - parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 4 - - # Statistics counter subsystem - parameters['STAT_ENABLE'] = 1 - parameters['STAT_DMA_ENABLE'] = 1 - parameters['STAT_PCIE_ENABLE'] = 1 - parameters['STAT_INC_WIDTH'] = 24 - parameters['STAT_ID_WIDTH'] = 12 - - extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} - - sim_build = os.path.join(tests_dir, "sim_build", - request.node.name.replace('[', '-').replace(']', '')) - - cocotb_test.simulator.run( - python_search=[tests_dir], - verilog_sources=verilog_sources, - toplevel=toplevel, - module=module, - parameters=parameters, - sim_build=sim_build, - extra_env=extra_env, - ) diff --git a/fpga/mqnic/VCU1525/fpga_100g/Makefile b/fpga/mqnic/VCU1525/fpga_100g/Makefile deleted file mode 100644 index f504bd06f..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# Targets -TARGETS:= - -# Subdirectories -SUBDIRS = fpga -SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) - -# Rules -.PHONY: all -all: $(SUBDIRS) $(TARGETS) - -.PHONY: $(SUBDIRS) -$(SUBDIRS): - cd $@ && $(MAKE) - -.PHONY: $(SUBDIRS_CLEAN) -$(SUBDIRS_CLEAN): - cd $(@:.clean=) && $(MAKE) clean - -.PHONY: clean -clean: $(SUBDIRS_CLEAN) - -rm -rf $(TARGETS) - -program: - #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit diff --git a/fpga/mqnic/VCU1525/fpga_100g/README.md b/fpga/mqnic/VCU1525/fpga_100g/README.md deleted file mode 100644 index 43e4fec0e..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/README.md +++ /dev/null @@ -1,24 +0,0 @@ -# Corundum mqnic for VCU1525 - -## Introduction - -This design targets the Xilinx VCU1525 FPGA board. - -* FPGA: xcvu9p-fsgd2104-2L-e -* MAC: Xilinx 100G CMAC -* PHY: 100G CAUI-4 CMAC and internal GTY transceivers -* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM) - -## Quick start - -### Build FPGA bitstream - -Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. - -### Build driver and userspace tools - -On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools. - -### Testing - -Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state. diff --git a/fpga/mqnic/VCU1525/fpga_100g/app b/fpga/mqnic/VCU1525/fpga_100g/app deleted file mode 120000 index 4d46690fb..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/app +++ /dev/null @@ -1 +0,0 @@ -../../../app/ \ No newline at end of file diff --git a/fpga/mqnic/VCU1525/fpga_100g/boot.xdc b/fpga/mqnic/VCU1525/fpga_100g/boot.xdc deleted file mode 100644 index 5fb323e94..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/boot.xdc +++ /dev/null @@ -1,4 +0,0 @@ -# Timing constraints for FPGA boot logic - -set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] -set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] diff --git a/fpga/mqnic/VCU1525/fpga_100g/cfgmclk.xdc b/fpga/mqnic/VCU1525/fpga_100g/cfgmclk.xdc deleted file mode 100644 index 51f8c2ab1..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/cfgmclk.xdc +++ /dev/null @@ -1,4 +0,0 @@ -# Timing constraints for cfgmclk - -# Fcfgmclk is 50 MHz +/- 15%, rounding to 15 ns period -create_clock -period 15 -name cfgmclk [get_pins startupe3_inst/CFGMCLK] diff --git a/fpga/mqnic/VCU1525/fpga_100g/common/vivado.mk b/fpga/mqnic/VCU1525/fpga_100g/common/vivado.mk deleted file mode 100644 index 1402e2382..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/common/vivado.mk +++ /dev/null @@ -1,137 +0,0 @@ -################################################################### -# -# Xilinx Vivado FPGA Makefile -# -# Copyright (c) 2016 Alex Forencich -# -################################################################### -# -# Parameters: -# FPGA_TOP - Top module name -# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) -# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) -# SYN_FILES - space-separated list of source files -# INC_FILES - space-separated list of include files -# XDC_FILES - space-separated list of timing constraint files -# XCI_FILES - space-separated list of IP XCI files -# -# Example: -# -# FPGA_TOP = fpga -# FPGA_FAMILY = VirtexUltrascale -# FPGA_DEVICE = xcvu095-ffva2104-2-e -# SYN_FILES = rtl/fpga.v -# XDC_FILES = fpga.xdc -# XCI_FILES = ip/pcspma.xci -# include ../common/vivado.mk -# -################################################################### - -# phony targets -.PHONY: fpga vivado tmpclean clean distclean - -# prevent make from deleting intermediate files and reports -.PRECIOUS: %.xpr %.bit %.mcs %.prm -.SECONDARY: - -CONFIG ?= config.mk --include ../$(CONFIG) - -FPGA_TOP ?= fpga -PROJECT ?= $(FPGA_TOP) - -SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) - -ifdef XDC_FILES - XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -else - XDC_FILES_REL = $(PROJECT).xdc -endif - -################################################################### -# Main Targets -# -# all: build everything -# clean: remove output files and project files -################################################################### - -all: fpga - -fpga: $(PROJECT).bit - -vivado: $(PROJECT).xpr - vivado $(PROJECT).xpr - -tmpclean:: - -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl - -clean:: tmpclean - -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl - -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt - -distclean:: clean - -rm -rf rev - -################################################################### -# Target implementations -################################################################### - -# Vivado project file -create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) - rm -rf defines.v - touch defines.v - for x in $(DEFS); do echo '`define' $$x >> defines.v; done - echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ - echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ - echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ - echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ - for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done - for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) - echo "open_project -quiet $(PROJECT).xpr" > $@ - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -$(PROJECT).xpr: create_project.tcl update_config.tcl - vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) - -# synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr - echo "open_project $(PROJECT).xpr" > run_synth.tcl - echo "reset_run synth_1" >> run_synth.tcl - echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl - echo "wait_on_run synth_1" >> run_synth.tcl - vivado -nojournal -nolog -mode batch -source run_synth.tcl - -# implementation run -$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp - echo "open_project $(PROJECT).xpr" > run_impl.tcl - echo "reset_run impl_1" >> run_impl.tcl - echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl - echo "wait_on_run impl_1" >> run_impl.tcl - echo "open_run impl_1" >> run_impl.tcl - echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl - echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl - vivado -nojournal -nolog -mode batch -source run_impl.tcl - -# bit file -$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp - echo "open_project $(PROJECT).xpr" > generate_bit.tcl - echo "open_run impl_1" >> generate_bit.tcl - echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl - echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl - vivado -nojournal -nolog -mode batch -source generate_bit.tcl - ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi - mkdir -p rev - COUNT=100; \ - while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ - do COUNT=$$((COUNT+1)); done; \ - cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga.xdc b/fpga/mqnic/VCU1525/fpga_100g/fpga.xdc deleted file mode 100644 index d53a1f3e6..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga.xdc +++ /dev/null @@ -1,833 +0,0 @@ -# XDC constraints for the Xilinx VCU1525 board -# part: xcvu9p-fsgd2104-2L-e - -# General configuration -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design] -set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] -set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] -set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] -set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] - -# System clocks -# 300 MHz (DDR 0) -set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] -set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] -#create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p] - -# 300 MHz (DDR 1) -set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] -set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] -#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] - -# 300 MHz (DDR 2) -set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] -set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] -#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] - -# 300 MHz (DDR 3) -set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] -set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] -#create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p] - -# SI570 user clock -#set_property -dict {LOC AU19 IOSTANDARD LVDS} [get_ports clk_user_p] -#set_property -dict {LOC AV19 IOSTANDARD LVDS} [get_ports clk_user_n] -#create_clock -period 6.400 -name clk_user [get_ports clk_user_p] - -# LEDs -set_property -dict {LOC BC21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] -set_property -dict {LOC BB21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] -set_property -dict {LOC BA20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}] - -set_false_path -to [get_ports {led[*]}] -set_output_delay 0 [get_ports {led[*]}] - -# Reset button -#set_property -dict {LOC AL20 IOSTANDARD LVCMOS12} [get_ports reset] - -#set_false_path -from [get_ports {reset}] -#set_input_delay 0 [get_ports {reset}] - -# DIP switches -set_property -dict {LOC AN22 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] -set_property -dict {LOC AM19 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] -set_property -dict {LOC AL19 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] -set_property -dict {LOC AP20 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] - -set_false_path -from [get_ports {sw[*]}] -set_input_delay 0 [get_ports {sw[*]}] - -# UART -#set_property -dict {LOC BF18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd] -#set_property -dict {LOC BB20 IOSTANDARD LVCMOS12} [get_ports uart_rxd] - -#set_false_path -to [get_ports {uart_txd}] -#set_output_delay 0 [get_ports {uart_txd}] -#set_false_path -from [get_ports {uart_rxd}] -#set_input_delay 0 [get_ports {uart_rxd}] - -# QSFP28 Interfaces -set_property -dict {LOC N4 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC N3 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC N9 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC N8 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M2 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M1 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M7 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M6 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L4 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L3 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L9 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L8 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K2 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K1 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K7 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K6 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13 -#set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14 -set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18 -set_property -dict {LOC K10 } [get_ports qsfp0_mgt_refclk_1_n] ;# MGTREFCLK1N_231 from U9.17 -set_property -dict {LOC BE16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_modsell] -set_property -dict {LOC BE17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl] -set_property -dict {LOC BE20 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_modprsl] -set_property -dict {LOC BE21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_intl] -set_property -dict {LOC BD18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode] -set_property -dict {LOC AT22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_refclk_reset] -set_property -dict {LOC AT20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[0]}] -set_property -dict {LOC AU22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[1]}] - -# 156.25 MHz MGT reference clock (from SI570) -#create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports qsfp0_mgt_refclk_0_p] - -# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) -#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] - -# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) -create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] - -set_false_path -to [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] -set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] -set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}] -set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}] - -set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC U9 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC U8 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T2 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T1 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R4 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R3 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R9 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R8 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P2 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P1 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15 -#set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16 -set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18 -set_property -dict {LOC P10 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U12.17 -set_property -dict {LOC AY20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_modsell] -set_property -dict {LOC BC18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl] -set_property -dict {LOC BC19 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_modprsl] -set_property -dict {LOC AV21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_intl] -set_property -dict {LOC AV22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode] -set_property -dict {LOC AR21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_refclk_reset] -set_property -dict {LOC AR22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[0]}] -set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[1]}] - -# 156.25 MHz MGT reference clock (from SI570) -#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p] - -# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) -#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] - -# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) -create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] - -set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] -set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] -set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] -set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] - -# I2C interface -#set_property -dict {LOC BF19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset] -set_property -dict {LOC BF20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_scl] -set_property -dict {LOC BF17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_sda] - -set_false_path -to [get_ports {i2c_sda i2c_scl}] -set_output_delay 0 [get_ports {i2c_sda i2c_scl}] -set_false_path -from [get_ports {i2c_sda i2c_scl}] -set_input_delay 0 [get_ports {i2c_sda i2c_scl}] - -# PCIe Interface -set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AG9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AG8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AJ9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AJ8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AL4 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AL3 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AL9 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AL8 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AN4 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AN3 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AN9 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AN8 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AR4 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AR3 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AR9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AR8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AU4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AU3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AU9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AU8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AV7 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AV6 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AW4 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AW3 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BB5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BB4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BD5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BD4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BF5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BF4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AM11 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_226 -set_property -dict {LOC AM10 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_226 -set_property -dict {LOC BD21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n] - -# 100 MHz MGT reference clock -create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p] - -set_false_path -from [get_ports {pcie_reset_n}] -set_input_delay 0 [get_ports {pcie_reset_n}] - -# DDR4 C0 -set_property -dict {LOC AT36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] -set_property -dict {LOC AV36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] -set_property -dict {LOC AV37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] -set_property -dict {LOC AW35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] -set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] -set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] -set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] -set_property -dict {LOC BA40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] -set_property -dict {LOC BA37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] -set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] -set_property -dict {LOC AR35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] -set_property -dict {LOC BA39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] -set_property -dict {LOC BB40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] -set_property -dict {LOC AN36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] -set_property -dict {LOC AP35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] -set_property -dict {LOC AP36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] -set_property -dict {LOC AR36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] -set_property -dict {LOC AT35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] -set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] -set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] -set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] -set_property -dict {LOC AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[0]}] -set_property -dict {LOC AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[0]}] -#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[1]}] -#set_property -dict {LOC AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[1]}] -set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}] -#set_property -dict {LOC BC40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}] -set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}] -#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}] -#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}] -#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}] -set_property -dict {LOC BB39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] -set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}] -#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}] -set_property -dict {LOC AU36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] -set_property -dict {LOC AU31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] - -set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] -set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] -set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] -set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] -set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] -set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] -set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] -set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] -set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] -set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] -set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] -set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] -set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] -set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] -set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] -set_property -dict {LOC BF29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] -set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] -set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] -set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] -set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] -set_property -dict {LOC BC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] -set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] -set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] -set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] -set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] -set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] -set_property -dict {LOC AV34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] -set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] -set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] -set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] -set_property -dict {LOC BA35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] -set_property -dict {LOC BA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] -set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] -set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] -set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] -set_property -dict {LOC AT32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] -set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] -set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] -set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] -set_property -dict {LOC AR31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] -set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] -set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] -set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] -set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] -set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] -set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] -set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] -set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] -set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] -set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] -set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] -set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] -set_property -dict {LOC AV29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] -set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] -set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] -set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] -set_property -dict {LOC BD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] -set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] -set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] -set_property -dict {LOC BD35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] -set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] -set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] -set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] -set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] -set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] -set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] -set_property -dict {LOC BF43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] -set_property -dict {LOC BF42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] -set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] -set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] -set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] -set_property -dict {LOC BF41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] -set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] -set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] -set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] -set_property -dict {LOC BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] -set_property -dict {LOC BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] -set_property -dict {LOC BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] -set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] -set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] -set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] -set_property -dict {LOC BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] -set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] -set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] -set_property -dict {LOC AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] -set_property -dict {LOC AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] -set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] -set_property -dict {LOC BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] -set_property -dict {LOC AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] -set_property -dict {LOC AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] -set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}] -set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}] -set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}] -set_property -dict {LOC AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}] -set_property -dict {LOC AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}] -set_property -dict {LOC AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}] -set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}] -set_property -dict {LOC AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}] -set_property -dict {LOC AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}] -set_property -dict {LOC AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}] -set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}] -set_property -dict {LOC BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}] -set_property -dict {LOC BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}] -set_property -dict {LOC BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}] -set_property -dict {LOC BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}] -set_property -dict {LOC BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}] -set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}] -set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}] - -# DDR4 C1 -set_property -dict {LOC AN24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] -set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] -set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] -set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] -set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] -set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] -set_property -dict {LOC AV24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] -set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] -set_property -dict {LOC AY25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] -set_property -dict {LOC BA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] -set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] -set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] -set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] -set_property -dict {LOC AL24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] -set_property -dict {LOC AL25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] -set_property -dict {LOC AM25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] -set_property -dict {LOC AN23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] -set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] -set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] -set_property -dict {LOC BC22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] -set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] -set_property -dict {LOC AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[0]}] -set_property -dict {LOC AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[0]}] -#set_property -dict {LOC AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[1]}] -#set_property -dict {LOC AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[1]}] -set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}] -#set_property -dict {LOC BB24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}] -set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}] -#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}] -#set_property -dict {LOC AR23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}] -#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}] -set_property -dict {LOC AW25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] -set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}] -#set_property -dict {LOC AP24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}] -set_property -dict {LOC AT23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] -set_property -dict {LOC AR17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] - -set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] -set_property -dict {LOC BD7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] -set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] -set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] -set_property -dict {LOC BD10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] -set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] -set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] -set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] -set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] -set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] -set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] -set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] -set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] -set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] -set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] -set_property -dict {LOC BA11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] -set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] -set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] -set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] -set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] -set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] -set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] -set_property -dict {LOC BA7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] -set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] -set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] -set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] -set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] -set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] -set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] -set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] -set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] -set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] -set_property -dict {LOC BE13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] -set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] -set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] -set_property -dict {LOC BD13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] -set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] -set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] -set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] -set_property -dict {LOC BF13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] -set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] -set_property -dict {LOC BA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] -set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] -set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] -set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] -set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] -set_property -dict {LOC BC11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] -set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] -set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] -set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] -set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] -set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] -set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] -set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] -set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] -set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] -set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] -set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] -set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] -set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] -set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] -set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] -set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] -set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] -set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] -set_property -dict {LOC BF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] -set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] -set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] -set_property -dict {LOC BD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] -set_property -dict {LOC BC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] -set_property -dict {LOC BF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] -set_property -dict {LOC BE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] -set_property -dict {LOC BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] -set_property -dict {LOC BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] -set_property -dict {LOC BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] -set_property -dict {LOC BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] -set_property -dict {LOC AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] -set_property -dict {LOC AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] -set_property -dict {LOC AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] -set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] -set_property -dict {LOC BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] -set_property -dict {LOC BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] -set_property -dict {LOC BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] -set_property -dict {LOC BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] -set_property -dict {LOC AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] -set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] -set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] -set_property -dict {LOC AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] -set_property -dict {LOC BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] -set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] -set_property -dict {LOC BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] -set_property -dict {LOC BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] -set_property -dict {LOC BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}] -set_property -dict {LOC BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}] -set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}] -set_property -dict {LOC BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}] -set_property -dict {LOC AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}] -set_property -dict {LOC AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}] -set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}] -set_property -dict {LOC AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}] -set_property -dict {LOC AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}] -set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}] -set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}] -set_property -dict {LOC AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}] -set_property -dict {LOC BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}] -set_property -dict {LOC BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}] -set_property -dict {LOC BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}] -set_property -dict {LOC BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}] - -# DDR4 C2 -set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] -set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] -set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] -set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] -set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] -set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] -set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] -set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] -set_property -dict {LOC A32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] -set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] -set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] -set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] -set_property -dict {LOC M30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] -set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] -set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] -set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] -set_property -dict {LOC K30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] -set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] -set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] -set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] -set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}] -set_property -dict {LOC C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[0]}] -set_property -dict {LOC B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[0]}] -#set_property -dict {LOC D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[1]}] -#set_property -dict {LOC D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[1]}] -set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}] -#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}] -set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}] -#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}] -#set_property -dict {LOC L30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}] -#set_property -dict {LOC K31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}] -set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] -set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}] -#set_property -dict {LOC F34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}] -set_property -dict {LOC M29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] -set_property -dict {LOC D36 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] - -set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] -set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] -set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] -set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] -set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] -set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] -set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] -set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] -set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] -set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] -set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] -set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] -set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] -set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] -set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] -set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] -set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] -set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] -set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] -set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] -set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] -set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] -set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] -set_property -dict {LOC F29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] -set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] -set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] -set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] -set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] -set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] -set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] -set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] -set_property -dict {LOC C28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] -set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] -set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] -set_property -dict {LOC D38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] -set_property -dict {LOC E35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] -set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] -set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] -set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] -set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] -set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] -set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] -set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] -set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] -set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] -set_property -dict {LOC M32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] -set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] -set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] -set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] -set_property -dict {LOC K35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] -set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] -set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] -set_property -dict {LOC J34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] -set_property -dict {LOC J33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] -set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] -set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] -set_property -dict {LOC H36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] -set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] -set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] -set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] -set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] -set_property -dict {LOC K38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] -set_property -dict {LOC G35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] -set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] -set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] -set_property -dict {LOC B37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] -set_property -dict {LOC A37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] -set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] -set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] -set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] -set_property -dict {LOC A40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] -set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] -set_property -dict {LOC N26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] -set_property -dict {LOC M26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] -set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] -set_property -dict {LOC P28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] -set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] -set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] -set_property -dict {LOC M27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] -set_property -dict {LOC L28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] -set_property -dict {LOC D29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] -set_property -dict {LOC D30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] -set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] -set_property -dict {LOC H27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] -set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] -set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] -set_property -dict {LOC C29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] -set_property -dict {LOC B29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] -set_property -dict {LOC E39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] -set_property -dict {LOC E40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] -set_property -dict {LOC G37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] -set_property -dict {LOC F37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] -set_property -dict {LOC N31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}] -set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}] -set_property -dict {LOC T30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}] -set_property -dict {LOC R31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}] -set_property -dict {LOC L35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}] -set_property -dict {LOC L36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}] -set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}] -set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}] -set_property -dict {LOC J38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}] -set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}] -set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}] -set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}] -set_property -dict {LOC B39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}] -set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}] -set_property -dict {LOC C37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}] -set_property -dict {LOC C38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}] - -# DDR4 C3 -set_property -dict {LOC K15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}] -set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}] -set_property -dict {LOC F14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}] -set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}] -set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}] -set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}] -set_property -dict {LOC B14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}] -set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}] -set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}] -set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}] -set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}] -set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}] -set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}] -set_property -dict {LOC K16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}] -set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}] -set_property -dict {LOC E15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}] -set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}] -set_property -dict {LOC J15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}] -set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}] -set_property -dict {LOC D13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}] -set_property -dict {LOC J13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}] -set_property -dict {LOC L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[0]}] -set_property -dict {LOC L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[0]}] -#set_property -dict {LOC G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[1]}] -#set_property -dict {LOC G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[1]}] -set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}] -#set_property -dict {LOC L15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}] -set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}] -#set_property -dict {LOC D16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}] -#set_property -dict {LOC M14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}] -#set_property -dict {LOC M13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}] -set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}] -set_property -dict {LOC C16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}] -#set_property -dict {LOC E16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}] -set_property -dict {LOC J14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}] -set_property -dict {LOC D21 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}] - -set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}] -set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}] -set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}] -set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}] -set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}] -set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}] -set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}] -set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}] -set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}] -set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}] -set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}] -set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}] -set_property -dict {LOC L24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}] -set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}] -set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}] -set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}] -set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}] -set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}] -set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}] -set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}] -set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}] -set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}] -set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}] -set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}] -set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}] -set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}] -set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}] -set_property -dict {LOC R17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}] -set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}] -set_property -dict {LOC T20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}] -set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}] -set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}] -set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}] -set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}] -set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}] -set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}] -set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}] -set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}] -set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}] -set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}] -set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}] -set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}] -set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}] -set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}] -set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}] -set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}] -set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}] -set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}] -set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}] -set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}] -set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}] -set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}] -set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}] -set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}] -set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}] -set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}] -set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}] -set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}] -set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}] -set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}] -set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}] -set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}] -set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}] -set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}] -set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}] -set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}] -set_property -dict {LOC N13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}] -set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}] -set_property -dict {LOC T15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}] -set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}] -set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}] -set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}] -set_property -dict {LOC T22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}] -set_property -dict {LOC R22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}] -set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}] -set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}] -set_property -dict {LOC J21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}] -set_property -dict {LOC H21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}] -set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}] -set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}] -set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}] -set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}] -set_property -dict {LOC K18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}] -set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}] -set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}] -set_property -dict {LOC P18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}] -set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}] -set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}] -set_property -dict {LOC A25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}] -set_property -dict {LOC A24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}] -set_property -dict {LOC D24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}] -set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}] -set_property -dict {LOC C17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}] -set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}] -set_property -dict {LOC B19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}] -set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}] -set_property -dict {LOC F18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}] -set_property -dict {LOC F17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}] -set_property -dict {LOC H19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}] -set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}] -set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}] -set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}] -set_property -dict {LOC H23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}] -set_property -dict {LOC H22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}] -set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}] -set_property -dict {LOC P15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}] -set_property -dict {LOC T13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}] -set_property -dict {LOC R13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}] diff --git a/fpga/mqnic/VCU1525/fpga_100g/ip/cmac_gty.tcl b/fpga/mqnic/VCU1525/fpga_100g/ip/cmac_gty.tcl deleted file mode 100644 index 6a14c1f28..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/ip/cmac_gty.tcl +++ /dev/null @@ -1,106 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2022-2023 The Regents of the University of California - -set base_name {cmac_gty} - -set preset {GTY-CAUI_4} - -set freerun_freq {125} -set line_rate {25.78125} -set sec_line_rate {0} -set refclk_freq {161.1328125} -set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set user_data_width {80} -set int_data_width $user_data_width -set rx_eq_mode {LPM} -set extra_ports [list] -set extra_pll_ports [list] -# DRP connections -lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out -lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out -# PLL reset and power down -lappend extra_pll_ports qpll0reset_in qpll1reset_in -lappend extra_pll_ports qpll0pd_in qpll1pd_in -# PLL clocking -lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out -lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out -# channel reset -lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out -lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out -# channel power down -lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in -# channel clock selection -lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in -# channel polarity -lappend extra_ports txpolarity_in rxpolarity_in -# channel TX driver -lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in -# channel CDR -lappend extra_ports rxcdrlock_out rxcdrhold_in -# channel EQ -lappend extra_ports rxlpmen_in -# channel digital monitor -lappend extra_ports dmonitorout_out -# channel PRBS -lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out -# channel eye scan -lappend extra_ports eyescandataerror_out -# channel loopback -lappend extra_ports loopback_in - -set config [dict create] - -dict set config TX_LINE_RATE $line_rate -dict set config TX_REFCLK_FREQUENCY $refclk_freq -dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config TX_USER_DATA_WIDTH $user_data_width -dict set config TX_INT_DATA_WIDTH $int_data_width -dict set config RX_LINE_RATE $line_rate -dict set config RX_REFCLK_FREQUENCY $refclk_freq -dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config RX_USER_DATA_WIDTH $user_data_width -dict set config RX_INT_DATA_WIDTH $int_data_width -dict set config RX_EQ_MODE $rx_eq_mode -if {$sec_line_rate != 0} { - dict set config SECONDARY_QPLL_ENABLE true - dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn - dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq -} else { - dict set config SECONDARY_QPLL_ENABLE false -} -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} -dict set config LOCATE_TX_USER_CLOCKING {EXAMPLE_DESIGN} -dict set config LOCATE_RX_USER_CLOCKING {EXAMPLE_DESIGN} -dict set config LOCATE_USER_DATA_WIDTH_SIZING {EXAMPLE_DESIGN} -dict set config FREERUN_FREQUENCY $freerun_freq -dict set config DISABLE_LOC_XDC {1} - -proc create_gtwizard_ip {name preset config} { - create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name - set ip [get_ips $name] - set_property CONFIG.preset $preset $ip - set config_list {} - dict for {name value} $config { - lappend config_list "CONFIG.${name}" $value - } - set_property -dict $config_list $ip - - # enable only one site - set_property CONFIG.CHANNEL_ENABLE [lindex [get_property CONFIG.CHANNEL_ENABLE $ip] 0] $ip -} - -# variant with channel and common -dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports] -dict set config LOCATE_COMMON {CORE} - -create_gtwizard_ip "${base_name}_full" $preset $config - -# variant with channel only -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {EXAMPLE_DESIGN} - -create_gtwizard_ip "${base_name}_channel" $preset $config diff --git a/fpga/mqnic/VCU1525/fpga_100g/ip/cmac_usplus.tcl b/fpga/mqnic/VCU1525/fpga_100g/ip/cmac_usplus.tcl deleted file mode 100644 index af9cc8265..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/ip/cmac_usplus.tcl +++ /dev/null @@ -1,21 +0,0 @@ - -create_ip -name cmac_usplus -vendor xilinx.com -library ip -module_name cmac_usplus - -set_property -dict [list \ - CONFIG.CMAC_CAUI4_MODE {1} \ - CONFIG.NUM_LANES {4x25} \ - CONFIG.USER_INTERFACE {AXIS} \ - CONFIG.GT_DRP_CLK {125} \ - CONFIG.GT_LOCATION {0} \ - CONFIG.TX_FLOW_CONTROL {1} \ - CONFIG.RX_FLOW_CONTROL {1} \ - CONFIG.RX_FORWARD_CONTROL_FRAMES {0} \ - CONFIG.RX_CHECK_ACK {1} \ - CONFIG.INCLUDE_RS_FEC {1} \ - CONFIG.ENABLE_TIME_STAMPING {1} -] [get_ips cmac_usplus] - -# disable LOC constraint -set_property generate_synth_checkpoint false [get_files [get_property IP_FILE [get_ips cmac_usplus]]] -generate_target synthesis [get_files [get_property IP_FILE [get_ips cmac_usplus]]] -set_property is_enabled false [get_files -of_objects [get_files [get_property IP_FILE [get_ips cmac_usplus]]] cmac_usplus.xdc] diff --git a/fpga/mqnic/VCU1525/fpga_100g/ip/ddr4_0.tcl b/fpga/mqnic/VCU1525/fpga_100g/ip/ddr4_0.tcl deleted file mode 100644 index 27252f502..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/ip/ddr4_0.tcl +++ /dev/null @@ -1,17 +0,0 @@ - -create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 - -set_property -dict [list \ - CONFIG.C0.DDR4_AxiSelection {true} \ - CONFIG.C0.DDR4_AxiDataWidth {512} \ - CONFIG.C0.DDR4_AxiIDWidth {8} \ - CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ - CONFIG.C0.DDR4_TimePeriod {833} \ - CONFIG.C0.DDR4_InputClockPeriod {3332} \ - CONFIG.C0.DDR4_MemoryType {RDIMMs} \ - CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ - CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ - CONFIG.C0.DDR4_CasLatency {17} \ - CONFIG.C0.DDR4_CasWriteLatency {12} \ - CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} -] [get_ips ddr4_0] diff --git a/fpga/mqnic/VCU1525/fpga_100g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/VCU1525/fpga_100g/ip/pcie4_uscale_plus_0.tcl deleted file mode 100644 index 12f4ce18d..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/ip/pcie4_uscale_plus_0.tcl +++ /dev/null @@ -1,34 +0,0 @@ - -create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 - -set_property -dict [list \ - CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ - CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ - CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \ - CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \ - CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \ - CONFIG.axisten_if_enable_client_tag {true} \ - CONFIG.axisten_if_width {512_bit} \ - CONFIG.extended_tag_field {true} \ - CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ - CONFIG.axisten_freq {250} \ - CONFIG.PF0_Use_Class_Code_Lookup_Assistant {false} \ - CONFIG.PF0_CLASS_CODE {020000} \ - CONFIG.PF0_DEVICE_ID {1001} \ - CONFIG.PF0_SUBSYSTEM_ID {95f5} \ - CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ - CONFIG.pf0_bar0_64bit {true} \ - CONFIG.pf0_bar0_prefetchable {true} \ - CONFIG.pf0_bar0_scale {Megabytes} \ - CONFIG.pf0_bar0_size {16} \ - CONFIG.pf0_msi_enabled {false} \ - CONFIG.pf0_msix_enabled {true} \ - CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ - CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \ - CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \ - CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \ - CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \ - CONFIG.MSI_X_OPTIONS {MSI-X_External} \ - CONFIG.vendor_id {1234} \ - CONFIG.mode_selection {Advanced} \ -] [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/VCU1525/fpga_100g/lib b/fpga/mqnic/VCU1525/fpga_100g/lib deleted file mode 120000 index 9512b3d5e..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/lib +++ /dev/null @@ -1 +0,0 @@ -../../../lib/ \ No newline at end of file diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/common b/fpga/mqnic/VCU1525/fpga_100g/rtl/common deleted file mode 120000 index 449c9409c..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/common +++ /dev/null @@ -1 +0,0 @@ -../../../../common/rtl/ \ No newline at end of file diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/debounce_switch.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/debounce_switch.v deleted file mode 100644 index 8e93a50c4..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/debounce_switch.v +++ /dev/null @@ -1,93 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog-2001 - -`resetall -`timescale 1 ns / 1 ps -`default_nettype none - -/* - * Synchronizes switch and button inputs with a slow sampled shift register - */ -module debounce_switch #( - parameter WIDTH=1, // width of the input and output signals - parameter N=3, // length of shift register - parameter RATE=125000 // clock division factor -)( - input wire clk, - input wire rst, - input wire [WIDTH-1:0] in, - output wire [WIDTH-1:0] out -); - -reg [23:0] cnt_reg = 24'd0; - -reg [N-1:0] debounce_reg[WIDTH-1:0]; - -reg [WIDTH-1:0] state; - -/* - * The synchronized output is the state register - */ -assign out = state; - -integer k; - -always @(posedge clk or posedge rst) begin - if (rst) begin - cnt_reg <= 0; - state <= 0; - - for (k = 0; k < WIDTH; k = k + 1) begin - debounce_reg[k] <= 0; - end - end else begin - if (cnt_reg < RATE) begin - cnt_reg <= cnt_reg + 24'd1; - end else begin - cnt_reg <= 24'd0; - end - - if (cnt_reg == 24'd0) begin - for (k = 0; k < WIDTH; k = k + 1) begin - debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]}; - end - end - - for (k = 0; k < WIDTH; k = k + 1) begin - if (|debounce_reg[k] == 0) begin - state[k] <= 0; - end else if (&debounce_reg[k] == 1) begin - state[k] <= 1; - end else begin - state[k] <= state[k]; - end - end - end -end - -endmodule - -`resetall diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v deleted file mode 100644 index 05db2dd82..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v +++ /dev/null @@ -1,2261 +0,0 @@ -// SPDX-License-Identifier: BSD-2-Clause-Views -/* - * Copyright (c) 2019-2023 The Regents of the University of California - */ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA top-level module - */ -module fpga # -( - // FW and board IDs - parameter FPGA_ID = 32'h4B31093, - parameter FW_ID = 32'h00000000, - parameter FW_VER = 32'h00_00_01_00, - parameter BOARD_ID = 32'h10ee_95f5, - parameter BOARD_VER = 32'h01_00_00_00, - parameter BUILD_DATE = 32'd602976000, - parameter GIT_HASH = 32'hdce357bf, - parameter RELEASE_INFO = 32'h00000000, - - // Structural configuration - parameter IF_COUNT = 2, - parameter PORTS_PER_IF = 1, - parameter SCHED_PER_IF = PORTS_PER_IF, - parameter PORT_MASK = 0, - - // Clock configuration - parameter CLK_PERIOD_NS_NUM = 4, - parameter CLK_PERIOD_NS_DENOM = 1, - - // PTP configuration - parameter PTP_CLOCK_PIPELINE = 0, - parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_PORT_CDC_PIPELINE = 0, - parameter PTP_PEROUT_ENABLE = 0, - parameter PTP_PEROUT_COUNT = 1, - - // Queue manager configuration - parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_QUEUE_OP_TABLE_SIZE = 32, - parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter CQ_OP_TABLE_SIZE = 32, - parameter EQN_WIDTH = 5, - parameter TX_QUEUE_INDEX_WIDTH = 13, - parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, - parameter EQ_PIPELINE = 3, - parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), - parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), - - // TX and RX engine configuration - parameter TX_DESC_TABLE_SIZE = 32, - parameter RX_DESC_TABLE_SIZE = 32, - parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, - - // Scheduler configuration - parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, - parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, - parameter TDMA_INDEX_WIDTH = 6, - - // Interface configuration - parameter PTP_TS_ENABLE = 1, - parameter TX_CPL_FIFO_DEPTH = 32, - parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_HASH_ENABLE = 1, - parameter RX_CHECKSUM_ENABLE = 1, - parameter PFC_ENABLE = 1, - parameter LFC_ENABLE = PFC_ENABLE, - parameter TX_FIFO_DEPTH = 32768, - parameter RX_FIFO_DEPTH = 131072, - parameter MAX_TX_SIZE = 9214, - parameter MAX_RX_SIZE = 9214, - parameter TX_RAM_SIZE = 131072, - parameter RX_RAM_SIZE = 131072, - - // RAM configuration - parameter DDR_CH = 4, - parameter DDR_ENABLE = 0, - parameter AXI_DDR_DATA_WIDTH = 512, - parameter AXI_DDR_ADDR_WIDTH = 34, - parameter AXI_DDR_ID_WIDTH = 8, - parameter AXI_DDR_MAX_BURST_LEN = 256, - parameter AXI_DDR_NARROW_BURST = 0, - - // Application block configuration - parameter APP_ID = 32'h00000000, - parameter APP_ENABLE = 0, - parameter APP_CTRL_ENABLE = 1, - parameter APP_DMA_ENABLE = 1, - parameter APP_AXIS_DIRECT_ENABLE = 1, - parameter APP_AXIS_SYNC_ENABLE = 1, - parameter APP_AXIS_IF_ENABLE = 1, - parameter APP_STAT_ENABLE = 1, - - // DMA interface configuration - parameter DMA_IMM_ENABLE = 0, - parameter DMA_IMM_WIDTH = 32, - parameter DMA_LEN_WIDTH = 16, - parameter DMA_TAG_WIDTH = 16, - parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), - parameter RAM_PIPELINE = 2, - - // PCIe interface configuration - parameter AXIS_PCIE_DATA_WIDTH = 512, - parameter PF_COUNT = 1, - parameter VF_COUNT = 0, - - // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EQN_WIDTH, - - // AXI lite interface configuration (control) - parameter AXIL_CTRL_DATA_WIDTH = 32, - parameter AXIL_CTRL_ADDR_WIDTH = 24, - - // AXI lite interface configuration (application control) - parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, - parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, - - // Ethernet interface configuration - parameter AXIS_ETH_TX_PIPELINE = 4, - parameter AXIS_ETH_TX_FIFO_PIPELINE = 4, - parameter AXIS_ETH_TX_TS_PIPELINE = 4, - parameter AXIS_ETH_RX_PIPELINE = 4, - parameter AXIS_ETH_RX_FIFO_PIPELINE = 4, - - // Statistics counter subsystem - parameter STAT_ENABLE = 1, - parameter STAT_DMA_ENABLE = 1, - parameter STAT_PCIE_ENABLE = 1, - parameter STAT_INC_WIDTH = 24, - parameter STAT_ID_WIDTH = 12 -) -( - /* - * Clock and reset - */ - input wire clk_300mhz_0_p, - input wire clk_300mhz_0_n, - input wire clk_300mhz_1_p, - input wire clk_300mhz_1_n, - input wire clk_300mhz_2_p, - input wire clk_300mhz_2_n, - input wire clk_300mhz_3_p, - input wire clk_300mhz_3_n, - - /* - * GPIO - */ - input wire [3:0] sw, - output wire [2:0] led, - - /* - * I2C for board management - */ - inout wire i2c_scl, - inout wire i2c_sda, - - /* - * PCI express - */ - input wire [15:0] pcie_rx_p, - input wire [15:0] pcie_rx_n, - output wire [15:0] pcie_tx_p, - output wire [15:0] pcie_tx_n, - input wire pcie_refclk_p, - input wire pcie_refclk_n, - input wire pcie_reset_n, - - /* - * Ethernet: QSFP28 - */ - output wire [3:0] qsfp0_tx_p, - output wire [3:0] qsfp0_tx_n, - input wire [3:0] qsfp0_rx_p, - input wire [3:0] qsfp0_rx_n, - // input wire qsfp0_mgt_refclk_0_p, - // input wire qsfp0_mgt_refclk_0_n, - input wire qsfp0_mgt_refclk_1_p, - input wire qsfp0_mgt_refclk_1_n, - output wire qsfp0_modsell, - output wire qsfp0_resetl, - input wire qsfp0_modprsl, - input wire qsfp0_intl, - output wire qsfp0_lpmode, - output wire qsfp0_refclk_reset, - output wire [1:0] qsfp0_fs, - - output wire [3:0] qsfp1_tx_p, - output wire [3:0] qsfp1_tx_n, - input wire [3:0] qsfp1_rx_p, - input wire [3:0] qsfp1_rx_n, - // input wire qsfp1_mgt_refclk_0_p, - // input wire qsfp1_mgt_refclk_0_n, - input wire qsfp1_mgt_refclk_1_p, - input wire qsfp1_mgt_refclk_1_n, - output wire qsfp1_modsell, - output wire qsfp1_resetl, - input wire qsfp1_modprsl, - input wire qsfp1_intl, - output wire qsfp1_lpmode, - output wire qsfp1_refclk_reset, - output wire [1:0] qsfp1_fs, - - /* - * DDR4 - */ - output wire [16:0] ddr4_c0_adr, - output wire [1:0] ddr4_c0_ba, - output wire [1:0] ddr4_c0_bg, - output wire [0:0] ddr4_c0_ck_t, - output wire [0:0] ddr4_c0_ck_c, - output wire [0:0] ddr4_c0_cke, - output wire [0:0] ddr4_c0_cs_n, - output wire ddr4_c0_act_n, - output wire [0:0] ddr4_c0_odt, - output wire ddr4_c0_par, - output wire ddr4_c0_reset_n, - inout wire [71:0] ddr4_c0_dq, - inout wire [17:0] ddr4_c0_dqs_t, - inout wire [17:0] ddr4_c0_dqs_c, - - output wire [16:0] ddr4_c1_adr, - output wire [1:0] ddr4_c1_ba, - output wire [1:0] ddr4_c1_bg, - output wire [0:0] ddr4_c1_ck_t, - output wire [0:0] ddr4_c1_ck_c, - output wire [0:0] ddr4_c1_cke, - output wire [0:0] ddr4_c1_cs_n, - output wire ddr4_c1_act_n, - output wire [0:0] ddr4_c1_odt, - output wire ddr4_c1_par, - output wire ddr4_c1_reset_n, - inout wire [71:0] ddr4_c1_dq, - inout wire [17:0] ddr4_c1_dqs_t, - inout wire [17:0] ddr4_c1_dqs_c, - - output wire [16:0] ddr4_c2_adr, - output wire [1:0] ddr4_c2_ba, - output wire [1:0] ddr4_c2_bg, - output wire [0:0] ddr4_c2_ck_t, - output wire [0:0] ddr4_c2_ck_c, - output wire [0:0] ddr4_c2_cke, - output wire [0:0] ddr4_c2_cs_n, - output wire ddr4_c2_act_n, - output wire [0:0] ddr4_c2_odt, - output wire ddr4_c2_par, - output wire ddr4_c2_reset_n, - inout wire [71:0] ddr4_c2_dq, - inout wire [17:0] ddr4_c2_dqs_t, - inout wire [17:0] ddr4_c2_dqs_c, - - output wire [16:0] ddr4_c3_adr, - output wire [1:0] ddr4_c3_ba, - output wire [1:0] ddr4_c3_bg, - output wire [0:0] ddr4_c3_ck_t, - output wire [0:0] ddr4_c3_ck_c, - output wire [0:0] ddr4_c3_cke, - output wire [0:0] ddr4_c3_cs_n, - output wire ddr4_c3_act_n, - output wire [0:0] ddr4_c3_odt, - output wire ddr4_c3_par, - output wire ddr4_c3_reset_n, - inout wire [71:0] ddr4_c3_dq, - inout wire [17:0] ddr4_c3_dqs_t, - inout wire [17:0] ddr4_c3_dqs_c -); - -// PTP configuration -parameter PTP_CLK_PERIOD_NS_NUM = 1024; -parameter PTP_CLK_PERIOD_NS_DENOM = 165; -parameter PTP_TS_WIDTH = 96; -parameter PTP_SEPARATE_RX_CLOCK = 1; - -// Interface configuration -parameter TX_TAG_WIDTH = 16; - -// RAM configuration -parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); - -// PCIe interface configuration -parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); -parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161; -parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137; -parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183; -parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81; -parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256; -parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; -parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; -parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; -parameter RQ_SEQ_NUM_WIDTH = 6; -parameter PCIE_TAG_COUNT = 256; - -// Ethernet interface configuration -parameter AXIS_ETH_DATA_WIDTH = 512; -parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; -parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH; -parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1; -parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; - -// Clock and reset -wire pcie_user_clk; -wire pcie_user_reset; - -wire cfgmclk_int; - -wire clk_161mhz_ref_int; - -wire clk_125mhz_mmcm_out; - -// Internal 125 MHz clock -wire clk_125mhz_int; -wire rst_125mhz_int; - -wire mmcm_rst; -wire mmcm_locked; -wire mmcm_clkfb; - -// MMCM instance -// 161.13 MHz in, 125 MHz out -// PFD range: 10 MHz to 500 MHz -// VCO range: 800 MHz to 1600 MHz -// M = 64, D = 11 sets Fvco = 937.5 MHz (in range) -// Divide by 7.5 to get output frequency of 125 MHz -MMCME4_BASE #( - .BANDWIDTH("OPTIMIZED"), - .CLKOUT0_DIVIDE_F(7.5), - .CLKOUT0_DUTY_CYCLE(0.5), - .CLKOUT0_PHASE(0), - .CLKOUT1_DIVIDE(1), - .CLKOUT1_DUTY_CYCLE(0.5), - .CLKOUT1_PHASE(0), - .CLKOUT2_DIVIDE(1), - .CLKOUT2_DUTY_CYCLE(0.5), - .CLKOUT2_PHASE(0), - .CLKOUT3_DIVIDE(1), - .CLKOUT3_DUTY_CYCLE(0.5), - .CLKOUT3_PHASE(0), - .CLKOUT4_DIVIDE(1), - .CLKOUT4_DUTY_CYCLE(0.5), - .CLKOUT4_PHASE(0), - .CLKOUT5_DIVIDE(1), - .CLKOUT5_DUTY_CYCLE(0.5), - .CLKOUT5_PHASE(0), - .CLKOUT6_DIVIDE(1), - .CLKOUT6_DUTY_CYCLE(0.5), - .CLKOUT6_PHASE(0), - .CLKFBOUT_MULT_F(64), - .CLKFBOUT_PHASE(0), - .DIVCLK_DIVIDE(11), - .REF_JITTER1(0.010), - .CLKIN1_PERIOD(6.206), - .STARTUP_WAIT("FALSE"), - .CLKOUT4_CASCADE("FALSE") -) -clk_mmcm_inst ( - .CLKIN1(clk_161mhz_ref_int), - .CLKFBIN(mmcm_clkfb), - .RST(mmcm_rst), - .PWRDWN(1'b0), - .CLKOUT0(clk_125mhz_mmcm_out), - .CLKOUT0B(), - .CLKOUT1(), - .CLKOUT1B(), - .CLKOUT2(), - .CLKOUT2B(), - .CLKOUT3(), - .CLKOUT3B(), - .CLKOUT4(), - .CLKOUT5(), - .CLKOUT6(), - .CLKFBOUT(mmcm_clkfb), - .CLKFBOUTB(), - .LOCKED(mmcm_locked) -); - -BUFG -clk_125mhz_bufg_inst ( - .I(clk_125mhz_mmcm_out), - .O(clk_125mhz_int) -); - -sync_reset #( - .N(4) -) -sync_reset_125mhz_inst ( - .clk(clk_125mhz_int), - .rst(~mmcm_locked), - .out(rst_125mhz_int) -); - -// GPIO -wire btnu_int; -wire btnl_int; -wire btnd_int; -wire btnr_int; -wire btnc_int; -wire [3:0] sw_int; -wire qsfp0_modprsl_int; -wire qsfp1_modprsl_int; -wire qsfp0_intl_int; -wire qsfp1_intl_int; -wire i2c_scl_i; -wire i2c_scl_o; -wire i2c_scl_t; -wire i2c_sda_i; -wire i2c_sda_o; -wire i2c_sda_t; - -reg i2c_scl_o_reg; -reg i2c_scl_t_reg; -reg i2c_sda_o_reg; -reg i2c_sda_t_reg; - -always @(posedge pcie_user_clk) begin - i2c_scl_o_reg <= i2c_scl_o; - i2c_scl_t_reg <= i2c_scl_t; - i2c_sda_o_reg <= i2c_sda_o; - i2c_sda_t_reg <= i2c_sda_t; -end - -debounce_switch #( - .WIDTH(4), - .N(4), - .RATE(250000) -) -debounce_switch_inst ( - .clk(pcie_user_clk), - .rst(pcie_user_reset), - .in({sw}), - .out({sw_int}) -); - -sync_signal #( - .WIDTH(6), - .N(2) -) -sync_signal_inst ( - .clk(pcie_user_clk), - .in({qsfp0_modprsl, qsfp1_modprsl, qsfp0_intl, qsfp1_intl, - i2c_scl, i2c_sda}), - .out({qsfp0_modprsl_int, qsfp1_modprsl_int, qsfp0_intl_int, qsfp1_intl_int, - i2c_scl_i, i2c_sda_i}) -); - -assign i2c_scl = i2c_scl_t_reg ? 1'bz : i2c_scl_o_reg; -assign i2c_sda = i2c_sda_t_reg ? 1'bz : i2c_sda_o_reg; - -// Flash -wire qspi_clk_int; -wire [3:0] qspi_dq_int; -wire [3:0] qspi_dq_i_int; -wire [3:0] qspi_dq_o_int; -wire [3:0] qspi_dq_oe_int; -wire qspi_cs_int; - -reg qspi_clk_reg; -reg [3:0] qspi_dq_o_reg; -reg [3:0] qspi_dq_oe_reg; -reg qspi_cs_reg; - -always @(posedge pcie_user_clk) begin - qspi_clk_reg <= qspi_clk_int; - qspi_dq_o_reg <= qspi_dq_o_int; - qspi_dq_oe_reg <= qspi_dq_oe_int; - qspi_cs_reg <= qspi_cs_int; -end - -sync_signal #( - .WIDTH(4), - .N(2) -) -flash_sync_signal_inst ( - .clk(pcie_user_clk), - .in({qspi_dq_int}), - .out({qspi_dq_i_int}) -); - -// startupe3 instance -wire cfgmclk; - -STARTUPE3 -startupe3_inst ( - .CFGCLK(), - .CFGMCLK(cfgmclk), - .DI(qspi_dq_int), - .DO(qspi_dq_o_reg), - .DTS(~qspi_dq_oe_reg), - .EOS(), - .FCSBO(qspi_cs_reg), - .FCSBTS(1'b0), - .GSR(1'b0), - .GTS(1'b0), - .KEYCLEARB(1'b1), - .PACK(1'b0), - .PREQ(), - .USRCCLKO(qspi_clk_reg), - .USRCCLKTS(1'b0), - .USRDONEO(1'b0), - .USRDONETS(1'b1) -); - -BUFG -cfgmclk_bufg_inst ( - .I(cfgmclk), - .O(cfgmclk_int) -); - -// FPGA boot -wire fpga_boot; - -reg fpga_boot_sync_reg_0 = 1'b0; -reg fpga_boot_sync_reg_1 = 1'b0; -reg fpga_boot_sync_reg_2 = 1'b0; - -wire icap_avail; -reg [2:0] icap_state = 0; -reg icap_csib_reg = 1'b1; -reg icap_rdwrb_reg = 1'b0; -reg [31:0] icap_di_reg = 32'hffffffff; - -wire [31:0] icap_di_rev; - -assign icap_di_rev[ 7] = icap_di_reg[ 0]; -assign icap_di_rev[ 6] = icap_di_reg[ 1]; -assign icap_di_rev[ 5] = icap_di_reg[ 2]; -assign icap_di_rev[ 4] = icap_di_reg[ 3]; -assign icap_di_rev[ 3] = icap_di_reg[ 4]; -assign icap_di_rev[ 2] = icap_di_reg[ 5]; -assign icap_di_rev[ 1] = icap_di_reg[ 6]; -assign icap_di_rev[ 0] = icap_di_reg[ 7]; - -assign icap_di_rev[15] = icap_di_reg[ 8]; -assign icap_di_rev[14] = icap_di_reg[ 9]; -assign icap_di_rev[13] = icap_di_reg[10]; -assign icap_di_rev[12] = icap_di_reg[11]; -assign icap_di_rev[11] = icap_di_reg[12]; -assign icap_di_rev[10] = icap_di_reg[13]; -assign icap_di_rev[ 9] = icap_di_reg[14]; -assign icap_di_rev[ 8] = icap_di_reg[15]; - -assign icap_di_rev[23] = icap_di_reg[16]; -assign icap_di_rev[22] = icap_di_reg[17]; -assign icap_di_rev[21] = icap_di_reg[18]; -assign icap_di_rev[20] = icap_di_reg[19]; -assign icap_di_rev[19] = icap_di_reg[20]; -assign icap_di_rev[18] = icap_di_reg[21]; -assign icap_di_rev[17] = icap_di_reg[22]; -assign icap_di_rev[16] = icap_di_reg[23]; - -assign icap_di_rev[31] = icap_di_reg[24]; -assign icap_di_rev[30] = icap_di_reg[25]; -assign icap_di_rev[29] = icap_di_reg[26]; -assign icap_di_rev[28] = icap_di_reg[27]; -assign icap_di_rev[27] = icap_di_reg[28]; -assign icap_di_rev[26] = icap_di_reg[29]; -assign icap_di_rev[25] = icap_di_reg[30]; -assign icap_di_rev[24] = icap_di_reg[31]; - -always @(posedge clk_125mhz_int) begin - case (icap_state) - 0: begin - icap_state <= 0; - icap_csib_reg <= 1'b1; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hffffffff; // dummy word - - if (fpga_boot_sync_reg_2 && icap_avail) begin - icap_state <= 1; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hffffffff; // dummy word - end - end - 1: begin - icap_state <= 2; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hAA995566; // sync word - end - 2: begin - icap_state <= 3; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h20000000; // type 1 noop - end - 3: begin - icap_state <= 4; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h30008001; // write 1 word to CMD - end - 4: begin - icap_state <= 5; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h0000000F; // IPROG - end - 5: begin - icap_state <= 0; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h20000000; // type 1 noop - end - endcase - - fpga_boot_sync_reg_0 <= fpga_boot; - fpga_boot_sync_reg_1 <= fpga_boot_sync_reg_0; - fpga_boot_sync_reg_2 <= fpga_boot_sync_reg_1; -end - -ICAPE3 -icape3_inst ( - .AVAIL(icap_avail), - .CLK(clk_125mhz_int), - .CSIB(icap_csib_reg), - .I(icap_di_rev), - .O(), - .PRDONE(), - .PRERROR(), - .RDWRB(icap_rdwrb_reg) -); - -// configure SI5335 clock generators -reg qsfp_refclk_reset_reg = 1'b1; -reg sys_reset_reg = 1'b1; - -reg [9:0] reset_timer_reg = 0; - -assign mmcm_rst = sys_reset_reg | pcie_user_reset; - -always @(posedge cfgmclk_int) begin - if (&reset_timer_reg) begin - if (qsfp_refclk_reset_reg) begin - qsfp_refclk_reset_reg <= 1'b0; - reset_timer_reg <= 0; - end else begin - qsfp_refclk_reset_reg <= 1'b0; - sys_reset_reg <= 1'b0; - end - end else begin - reset_timer_reg <= reset_timer_reg + 1; - end -end - -// PCIe -wire pcie_sys_clk; -wire pcie_sys_clk_gt; - -IBUFDS_GTE4 #( - .REFCLK_HROW_CK_SEL(2'b00) -) -ibufds_gte4_pcie_mgt_refclk_inst ( - .I (pcie_refclk_p), - .IB (pcie_refclk_n), - .CEB (1'b0), - .O (pcie_sys_clk_gt), - .ODIV2 (pcie_sys_clk) -); - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep; -wire axis_rq_tlast; -wire axis_rq_tready; -wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser; -wire axis_rq_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep; -wire axis_rc_tlast; -wire axis_rc_tready; -wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser; -wire axis_rc_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep; -wire axis_cq_tlast; -wire axis_cq_tready; -wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser; -wire axis_cq_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep; -wire axis_cc_tlast; -wire axis_cc_tready; -wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser; -wire axis_cc_tvalid; - -wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num0; -wire pcie_rq_seq_num_vld0; -wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num1; -wire pcie_rq_seq_num_vld1; - -wire [3:0] pcie_tfc_nph_av; -wire [3:0] pcie_tfc_npd_av; - -wire [2:0] cfg_max_payload; -wire [2:0] cfg_max_read_req; -wire [3:0] cfg_rcb_status; - -wire [9:0] cfg_mgmt_addr; -wire [7:0] cfg_mgmt_function_number; -wire cfg_mgmt_write; -wire [31:0] cfg_mgmt_write_data; -wire [3:0] cfg_mgmt_byte_enable; -wire cfg_mgmt_read; -wire [31:0] cfg_mgmt_read_data; -wire cfg_mgmt_read_write_done; - -wire [7:0] cfg_fc_ph; -wire [11:0] cfg_fc_pd; -wire [7:0] cfg_fc_nph; -wire [11:0] cfg_fc_npd; -wire [7:0] cfg_fc_cplh; -wire [11:0] cfg_fc_cpld; -wire [2:0] cfg_fc_sel; - -wire [3:0] cfg_interrupt_msix_enable; -wire [3:0] cfg_interrupt_msix_mask; -wire [251:0] cfg_interrupt_msix_vf_enable; -wire [251:0] cfg_interrupt_msix_vf_mask; -wire [63:0] cfg_interrupt_msix_address; -wire [31:0] cfg_interrupt_msix_data; -wire cfg_interrupt_msix_int; -wire [1:0] cfg_interrupt_msix_vec_pending; -wire cfg_interrupt_msix_vec_pending_status; -wire cfg_interrupt_msix_sent; -wire cfg_interrupt_msix_fail; -wire [7:0] cfg_interrupt_msi_function_number; - -wire status_error_cor; -wire status_error_uncor; - -// extra register for pcie_user_reset signal -wire pcie_user_reset_int; -(* shreg_extract = "no" *) -reg pcie_user_reset_reg_1 = 1'b1; -(* shreg_extract = "no" *) -reg pcie_user_reset_reg_2 = 1'b1; - -always @(posedge pcie_user_clk) begin - pcie_user_reset_reg_1 <= pcie_user_reset_int; - pcie_user_reset_reg_2 <= pcie_user_reset_reg_1; -end - -BUFG -pcie_user_reset_bufg_inst ( - .I(pcie_user_reset_reg_2), - .O(pcie_user_reset) -); - -pcie4_uscale_plus_0 -pcie4_uscale_plus_inst ( - .pci_exp_txn(pcie_tx_n), - .pci_exp_txp(pcie_tx_p), - .pci_exp_rxn(pcie_rx_n), - .pci_exp_rxp(pcie_rx_p), - .user_clk(pcie_user_clk), - .user_reset(pcie_user_reset_int), - .user_lnk_up(), - - .s_axis_rq_tdata(axis_rq_tdata), - .s_axis_rq_tkeep(axis_rq_tkeep), - .s_axis_rq_tlast(axis_rq_tlast), - .s_axis_rq_tready(axis_rq_tready), - .s_axis_rq_tuser(axis_rq_tuser), - .s_axis_rq_tvalid(axis_rq_tvalid), - - .m_axis_rc_tdata(axis_rc_tdata), - .m_axis_rc_tkeep(axis_rc_tkeep), - .m_axis_rc_tlast(axis_rc_tlast), - .m_axis_rc_tready(axis_rc_tready), - .m_axis_rc_tuser(axis_rc_tuser), - .m_axis_rc_tvalid(axis_rc_tvalid), - - .m_axis_cq_tdata(axis_cq_tdata), - .m_axis_cq_tkeep(axis_cq_tkeep), - .m_axis_cq_tlast(axis_cq_tlast), - .m_axis_cq_tready(axis_cq_tready), - .m_axis_cq_tuser(axis_cq_tuser), - .m_axis_cq_tvalid(axis_cq_tvalid), - - .s_axis_cc_tdata(axis_cc_tdata), - .s_axis_cc_tkeep(axis_cc_tkeep), - .s_axis_cc_tlast(axis_cc_tlast), - .s_axis_cc_tready(axis_cc_tready), - .s_axis_cc_tuser(axis_cc_tuser), - .s_axis_cc_tvalid(axis_cc_tvalid), - - .pcie_rq_seq_num0(pcie_rq_seq_num0), - .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0), - .pcie_rq_seq_num1(pcie_rq_seq_num1), - .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1), - .pcie_rq_tag0(), - .pcie_rq_tag1(), - .pcie_rq_tag_av(), - .pcie_rq_tag_vld0(), - .pcie_rq_tag_vld1(), - - .pcie_tfc_nph_av(pcie_tfc_nph_av), - .pcie_tfc_npd_av(pcie_tfc_npd_av), - - .pcie_cq_np_req(1'b1), - .pcie_cq_np_req_count(), - - .cfg_phy_link_down(), - .cfg_phy_link_status(), - .cfg_negotiated_width(), - .cfg_current_speed(), - .cfg_max_payload(cfg_max_payload), - .cfg_max_read_req(cfg_max_read_req), - .cfg_function_status(), - .cfg_function_power_state(), - .cfg_vf_status(), - .cfg_vf_power_state(), - .cfg_link_power_state(), - - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - .cfg_mgmt_debug_access(1'b0), - - .cfg_err_cor_out(), - .cfg_err_nonfatal_out(), - .cfg_err_fatal_out(), - .cfg_local_error_valid(), - .cfg_local_error_out(), - .cfg_ltssm_state(), - .cfg_rx_pm_state(), - .cfg_tx_pm_state(), - .cfg_rcb_status(cfg_rcb_status), - .cfg_obff_enable(), - .cfg_pl_status_change(), - .cfg_tph_requester_enable(), - .cfg_tph_st_mode(), - .cfg_vf_tph_requester_enable(), - .cfg_vf_tph_st_mode(), - - .cfg_msg_received(), - .cfg_msg_received_data(), - .cfg_msg_received_type(), - .cfg_msg_transmit(1'b0), - .cfg_msg_transmit_type(3'd0), - .cfg_msg_transmit_data(32'd0), - .cfg_msg_transmit_done(), - - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - .cfg_dsn(64'd0), - - .cfg_power_state_change_ack(1'b1), - .cfg_power_state_change_interrupt(), - - .cfg_err_cor_in(status_error_cor), - .cfg_err_uncor_in(status_error_uncor), - .cfg_flr_in_process(), - .cfg_flr_done(4'd0), - .cfg_vf_flr_in_process(), - .cfg_vf_flr_func_num(8'd0), - .cfg_vf_flr_done(8'd0), - - .cfg_link_training_enable(1'b1), - - .cfg_interrupt_int(4'd0), - .cfg_interrupt_pending(4'd0), - .cfg_interrupt_sent(), - .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), - .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), - .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), - .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), - .cfg_interrupt_msix_address(cfg_interrupt_msix_address), - .cfg_interrupt_msix_data(cfg_interrupt_msix_data), - .cfg_interrupt_msix_int(cfg_interrupt_msix_int), - .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), - .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), - .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent), - .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - .cfg_pm_aspm_l1_entry_reject(1'b0), - .cfg_pm_aspm_tx_l0s_entry_disable(1'b0), - - .cfg_hot_reset_out(), - - .cfg_config_space_enable(1'b1), - .cfg_req_pm_transition_l23_ready(1'b0), - .cfg_hot_reset_in(1'b0), - - .cfg_ds_port_number(8'd0), - .cfg_ds_bus_number(8'd0), - .cfg_ds_device_number(5'd0), - - .sys_clk(pcie_sys_clk), - .sys_clk_gt(pcie_sys_clk_gt), - .sys_reset(pcie_reset_n), - - .phy_rdy_out() -); - -// QSFP0 CMAC -assign qsfp0_refclk_reset = qsfp_refclk_reset_reg; -assign qsfp0_fs = 2'b10; - -wire qsfp0_tx_clk_int; -wire qsfp0_tx_rst_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_tx_axis_tkeep_int; -wire qsfp0_tx_axis_tvalid_int; -wire qsfp0_tx_axis_tready_int; -wire qsfp0_tx_axis_tlast_int; -wire [16+1-1:0] qsfp0_tx_axis_tuser_int; - -wire [79:0] qsfp0_tx_ptp_time_int; -wire [79:0] qsfp0_tx_ptp_ts_int; -wire [15:0] qsfp0_tx_ptp_ts_tag_int; -wire qsfp0_tx_ptp_ts_valid_int; - -wire qsfp0_rx_clk_int; -wire qsfp0_rx_rst_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_rx_axis_tkeep_int; -wire qsfp0_rx_axis_tvalid_int; -wire qsfp0_rx_axis_tlast_int; -wire [80+1-1:0] qsfp0_rx_axis_tuser_int; - -wire qsfp0_rx_ptp_clk_int; -wire qsfp0_rx_ptp_rst_int; -wire [79:0] qsfp0_rx_ptp_time_int; - -wire qsfp0_drp_clk = clk_125mhz_int; -wire qsfp0_drp_rst = rst_125mhz_int; -wire [23:0] qsfp0_drp_addr; -wire [15:0] qsfp0_drp_di; -wire qsfp0_drp_en; -wire qsfp0_drp_we; -wire [15:0] qsfp0_drp_do; -wire qsfp0_drp_rdy; - -wire qsfp0_tx_enable; -wire qsfp0_tx_lfc_en; -wire qsfp0_tx_lfc_req; -wire [7:0] qsfp0_tx_pfc_en; -wire [7:0] qsfp0_tx_pfc_req; - -wire qsfp0_rx_enable; -wire qsfp0_rx_status; -wire qsfp0_rx_lfc_en; -wire qsfp0_rx_lfc_req; -wire qsfp0_rx_lfc_ack; -wire [7:0] qsfp0_rx_pfc_en; -wire [7:0] qsfp0_rx_pfc_req; -wire [7:0] qsfp0_rx_pfc_ack; - -wire qsfp0_gtpowergood; - -wire qsfp0_mgt_refclk_1; -wire qsfp0_mgt_refclk_1_int; -wire qsfp0_mgt_refclk_1_bufg; - -assign clk_161mhz_ref_int = qsfp0_mgt_refclk_1_bufg; - -IBUFDS_GTE4 ibufds_gte4_qsfp0_mgt_refclk_1_inst ( - .I (qsfp0_mgt_refclk_1_p), - .IB (qsfp0_mgt_refclk_1_n), - .CEB (1'b0), - .O (qsfp0_mgt_refclk_1), - .ODIV2 (qsfp0_mgt_refclk_1_int) -); - -BUFG_GT bufg_gt_qsfp0_mgt_refclk_1_inst ( - .CE (qsfp0_gtpowergood), - .CEMASK (1'b1), - .CLR (1'b0), - .CLRMASK (1'b1), - .DIV (3'd0), - .I (qsfp0_mgt_refclk_1_int), - .O (qsfp0_mgt_refclk_1_bufg) -); - -wire qsfp0_rst; - -sync_reset #( - .N(4) -) -qsfp0_sync_reset_inst ( - .clk(qsfp0_mgt_refclk_1_bufg), - .rst(rst_125mhz_int), - .out(qsfp0_rst) -); - -cmac_gty_wrapper #( - .DRP_CLK_FREQ_HZ(125000000), - .AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .TX_SERDES_PIPELINE(0), - .RX_SERDES_PIPELINE(0), - .RS_FEC_ENABLE(1) -) -qsfp0_cmac_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp0_rst), - - /* - * Common - */ - .xcvr_gtpowergood_out(qsfp0_gtpowergood), - .xcvr_ref_clk(qsfp0_mgt_refclk_1), - - /* - * DRP - */ - .drp_clk(qsfp0_drp_clk), - .drp_rst(qsfp0_drp_rst), - .drp_addr(qsfp0_drp_addr), - .drp_di(qsfp0_drp_di), - .drp_en(qsfp0_drp_en), - .drp_we(qsfp0_drp_we), - .drp_do(qsfp0_drp_do), - .drp_rdy(qsfp0_drp_rdy), - - /* - * Serial data - */ - .xcvr_txp(qsfp0_tx_p), - .xcvr_txn(qsfp0_tx_n), - .xcvr_rxp(qsfp0_rx_p), - .xcvr_rxn(qsfp0_rx_n), - - /* - * CMAC connections - */ - .tx_clk(qsfp0_tx_clk_int), - .tx_rst(qsfp0_tx_rst_int), - - .tx_axis_tdata(qsfp0_tx_axis_tdata_int), - .tx_axis_tkeep(qsfp0_tx_axis_tkeep_int), - .tx_axis_tvalid(qsfp0_tx_axis_tvalid_int), - .tx_axis_tready(qsfp0_tx_axis_tready_int), - .tx_axis_tlast(qsfp0_tx_axis_tlast_int), - .tx_axis_tuser(qsfp0_tx_axis_tuser_int), - - .tx_ptp_time(qsfp0_tx_ptp_time_int), - .tx_ptp_ts(qsfp0_tx_ptp_ts_int), - .tx_ptp_ts_tag(qsfp0_tx_ptp_ts_tag_int), - .tx_ptp_ts_valid(qsfp0_tx_ptp_ts_valid_int), - - .tx_enable(qsfp0_tx_enable), - .tx_lfc_en(qsfp0_tx_lfc_en), - .tx_lfc_req(qsfp0_tx_lfc_req), - .tx_pfc_en(qsfp0_tx_pfc_en), - .tx_pfc_req(qsfp0_tx_pfc_req), - - .rx_clk(qsfp0_rx_clk_int), - .rx_rst(qsfp0_rx_rst_int), - - .rx_axis_tdata(qsfp0_rx_axis_tdata_int), - .rx_axis_tkeep(qsfp0_rx_axis_tkeep_int), - .rx_axis_tvalid(qsfp0_rx_axis_tvalid_int), - .rx_axis_tlast(qsfp0_rx_axis_tlast_int), - .rx_axis_tuser(qsfp0_rx_axis_tuser_int), - - .rx_ptp_clk(qsfp0_rx_ptp_clk_int), - .rx_ptp_rst(qsfp0_rx_ptp_rst_int), - .rx_ptp_time(qsfp0_rx_ptp_time_int), - - .rx_enable(qsfp0_rx_enable), - .rx_status(qsfp0_rx_status), - .rx_lfc_en(qsfp0_rx_lfc_en), - .rx_lfc_req(qsfp0_rx_lfc_req), - .rx_lfc_ack(qsfp0_rx_lfc_ack), - .rx_pfc_en(qsfp0_rx_pfc_en), - .rx_pfc_req(qsfp0_rx_pfc_req), - .rx_pfc_ack(qsfp0_rx_pfc_ack) -); - -// QSFP1 CMAC -assign qsfp1_refclk_reset = qsfp_refclk_reset_reg; -assign qsfp1_fs = 2'b10; - -wire qsfp1_tx_clk_int; -wire qsfp1_tx_rst_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_tx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_tx_axis_tkeep_int; -wire qsfp1_tx_axis_tvalid_int; -wire qsfp1_tx_axis_tready_int; -wire qsfp1_tx_axis_tlast_int; -wire [16+1-1:0] qsfp1_tx_axis_tuser_int; - -wire [79:0] qsfp1_tx_ptp_time_int; -wire [79:0] qsfp1_tx_ptp_ts_int; -wire [15:0] qsfp1_tx_ptp_ts_tag_int; -wire qsfp1_tx_ptp_ts_valid_int; - -wire qsfp1_rx_clk_int; -wire qsfp1_rx_rst_int; - -wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_rx_axis_tdata_int; -wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_rx_axis_tkeep_int; -wire qsfp1_rx_axis_tvalid_int; -wire qsfp1_rx_axis_tlast_int; -wire [80+1-1:0] qsfp1_rx_axis_tuser_int; - -wire qsfp1_rx_ptp_clk_int; -wire qsfp1_rx_ptp_rst_int; -wire [79:0] qsfp1_rx_ptp_time_int; - -wire qsfp1_drp_clk = clk_125mhz_int; -wire qsfp1_drp_rst = rst_125mhz_int; -wire [23:0] qsfp1_drp_addr; -wire [15:0] qsfp1_drp_di; -wire qsfp1_drp_en; -wire qsfp1_drp_we; -wire [15:0] qsfp1_drp_do; -wire qsfp1_drp_rdy; - -wire qsfp1_tx_enable; -wire qsfp1_tx_lfc_en; -wire qsfp1_tx_lfc_req; -wire [7:0] qsfp1_tx_pfc_en; -wire [7:0] qsfp1_tx_pfc_req; - -wire qsfp1_rx_enable; -wire qsfp1_rx_status; -wire qsfp1_rx_lfc_en; -wire qsfp1_rx_lfc_req; -wire qsfp1_rx_lfc_ack; -wire [7:0] qsfp1_rx_pfc_en; -wire [7:0] qsfp1_rx_pfc_req; -wire [7:0] qsfp1_rx_pfc_ack; - -wire qsfp1_gtpowergood; - -wire qsfp1_mgt_refclk_1; -wire qsfp1_mgt_refclk_1_int; -wire qsfp1_mgt_refclk_1_bufg; - -IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_1_inst ( - .I (qsfp1_mgt_refclk_1_p), - .IB (qsfp1_mgt_refclk_1_n), - .CEB (1'b0), - .O (qsfp1_mgt_refclk_1), - .ODIV2 (qsfp1_mgt_refclk_1_int) -); - -BUFG_GT bufg_gt_qsfp1_mgt_refclk_1_inst ( - .CE (qsfp1_gtpowergood), - .CEMASK (1'b1), - .CLR (1'b0), - .CLRMASK (1'b1), - .DIV (3'd0), - .I (qsfp1_mgt_refclk_1_int), - .O (qsfp1_mgt_refclk_1_bufg) -); - -wire qsfp1_rst; - -sync_reset #( - .N(4) -) -qsfp1_sync_reset_inst ( - .clk(qsfp1_mgt_refclk_1_bufg), - .rst(rst_125mhz_int), - .out(qsfp1_rst) -); - -cmac_gty_wrapper #( - .DRP_CLK_FREQ_HZ(125000000), - .AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .TX_SERDES_PIPELINE(0), - .RX_SERDES_PIPELINE(0), - .RS_FEC_ENABLE(1) -) -qsfp1_cmac_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp1_rst), - - /* - * Common - */ - .xcvr_gtpowergood_out(qsfp1_gtpowergood), - .xcvr_ref_clk(qsfp1_mgt_refclk_1), - - /* - * DRP - */ - .drp_clk(qsfp1_drp_clk), - .drp_rst(qsfp1_drp_rst), - .drp_addr(qsfp1_drp_addr), - .drp_di(qsfp1_drp_di), - .drp_en(qsfp1_drp_en), - .drp_we(qsfp1_drp_we), - .drp_do(qsfp1_drp_do), - .drp_rdy(qsfp1_drp_rdy), - - /* - * Serial data - */ - .xcvr_txp(qsfp1_tx_p), - .xcvr_txn(qsfp1_tx_n), - .xcvr_rxp(qsfp1_rx_p), - .xcvr_rxn(qsfp1_rx_n), - - /* - * CMAC connections - */ - .tx_clk(qsfp1_tx_clk_int), - .tx_rst(qsfp1_tx_rst_int), - - .tx_axis_tdata(qsfp1_tx_axis_tdata_int), - .tx_axis_tkeep(qsfp1_tx_axis_tkeep_int), - .tx_axis_tvalid(qsfp1_tx_axis_tvalid_int), - .tx_axis_tready(qsfp1_tx_axis_tready_int), - .tx_axis_tlast(qsfp1_tx_axis_tlast_int), - .tx_axis_tuser(qsfp1_tx_axis_tuser_int), - - .tx_ptp_time(qsfp1_tx_ptp_time_int), - .tx_ptp_ts(qsfp1_tx_ptp_ts_int), - .tx_ptp_ts_tag(qsfp1_tx_ptp_ts_tag_int), - .tx_ptp_ts_valid(qsfp1_tx_ptp_ts_valid_int), - - .tx_enable(qsfp1_tx_enable), - .tx_lfc_en(qsfp1_tx_lfc_en), - .tx_lfc_req(qsfp1_tx_lfc_req), - .tx_pfc_en(qsfp1_tx_pfc_en), - .tx_pfc_req(qsfp1_tx_pfc_req), - - .rx_clk(qsfp1_rx_clk_int), - .rx_rst(qsfp1_rx_rst_int), - - .rx_axis_tdata(qsfp1_rx_axis_tdata_int), - .rx_axis_tkeep(qsfp1_rx_axis_tkeep_int), - .rx_axis_tvalid(qsfp1_rx_axis_tvalid_int), - .rx_axis_tlast(qsfp1_rx_axis_tlast_int), - .rx_axis_tuser(qsfp1_rx_axis_tuser_int), - - .rx_ptp_clk(qsfp1_rx_ptp_clk_int), - .rx_ptp_rst(qsfp1_rx_ptp_rst_int), - .rx_ptp_time(qsfp1_rx_ptp_time_int), - - .rx_enable(qsfp1_rx_enable), - .rx_status(qsfp1_rx_status), - .rx_lfc_en(qsfp1_rx_lfc_en), - .rx_lfc_req(qsfp1_rx_lfc_req), - .rx_lfc_ack(qsfp1_rx_lfc_ack), - .rx_pfc_en(qsfp1_rx_pfc_en), - .rx_pfc_req(qsfp1_rx_pfc_req), - .rx_pfc_ack(qsfp1_rx_pfc_ack) -); - -wire ptp_clk; -wire ptp_rst; -wire ptp_sample_clk; - -assign ptp_clk = qsfp0_mgt_refclk_1_bufg; -assign ptp_rst = qsfp0_rst; -assign ptp_sample_clk = clk_125mhz_int; - -wire [2:0] led_int; - -assign led[0] = led_int[0]; // red -assign led[1] = qsfp1_rx_status; // yellow -assign led[2] = qsfp0_rx_status; // green - -// DDR4 -wire [DDR_CH-1:0] ddr_clk; -wire [DDR_CH-1:0] ddr_rst; - -wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; -wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; -wire [DDR_CH*8-1:0] m_axi_ddr_awlen; -wire [DDR_CH*3-1:0] m_axi_ddr_awsize; -wire [DDR_CH*2-1:0] m_axi_ddr_awburst; -wire [DDR_CH-1:0] m_axi_ddr_awlock; -wire [DDR_CH*4-1:0] m_axi_ddr_awcache; -wire [DDR_CH*3-1:0] m_axi_ddr_awprot; -wire [DDR_CH*4-1:0] m_axi_ddr_awqos; -wire [DDR_CH-1:0] m_axi_ddr_awvalid; -wire [DDR_CH-1:0] m_axi_ddr_awready; -wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; -wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; -wire [DDR_CH-1:0] m_axi_ddr_wlast; -wire [DDR_CH-1:0] m_axi_ddr_wvalid; -wire [DDR_CH-1:0] m_axi_ddr_wready; -wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; -wire [DDR_CH*2-1:0] m_axi_ddr_bresp; -wire [DDR_CH-1:0] m_axi_ddr_bvalid; -wire [DDR_CH-1:0] m_axi_ddr_bready; -wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; -wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; -wire [DDR_CH*8-1:0] m_axi_ddr_arlen; -wire [DDR_CH*3-1:0] m_axi_ddr_arsize; -wire [DDR_CH*2-1:0] m_axi_ddr_arburst; -wire [DDR_CH-1:0] m_axi_ddr_arlock; -wire [DDR_CH*4-1:0] m_axi_ddr_arcache; -wire [DDR_CH*3-1:0] m_axi_ddr_arprot; -wire [DDR_CH*4-1:0] m_axi_ddr_arqos; -wire [DDR_CH-1:0] m_axi_ddr_arvalid; -wire [DDR_CH-1:0] m_axi_ddr_arready; -wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; -wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; -wire [DDR_CH*2-1:0] m_axi_ddr_rresp; -wire [DDR_CH-1:0] m_axi_ddr_rlast; -wire [DDR_CH-1:0] m_axi_ddr_rvalid; -wire [DDR_CH-1:0] m_axi_ddr_rready; - -wire [DDR_CH-1:0] ddr_status; - -generate - -if (DDR_ENABLE && DDR_CH > 0) begin - -reg ddr4_rst_reg = 1'b1; - -always @(posedge pcie_user_clk or posedge pcie_user_reset) begin - if (pcie_user_reset) begin - ddr4_rst_reg <= 1'b1; - end else begin - ddr4_rst_reg <= 1'b0; - end -end - -ddr4_0 ddr4_c0_inst ( - .c0_sys_clk_p(clk_300mhz_0_p), - .c0_sys_clk_n(clk_300mhz_0_n), - .sys_rst(ddr4_rst_reg), - - .c0_init_calib_complete(ddr_status[0 +: 1]), - .c0_ddr4_interrupt(), - .dbg_clk(), - .dbg_bus(), - - .c0_ddr4_adr(ddr4_c0_adr), - .c0_ddr4_ba(ddr4_c0_ba), - .c0_ddr4_cke(ddr4_c0_cke), - .c0_ddr4_cs_n(ddr4_c0_cs_n), - .c0_ddr4_dq(ddr4_c0_dq), - .c0_ddr4_dqs_t(ddr4_c0_dqs_t), - .c0_ddr4_dqs_c(ddr4_c0_dqs_c), - .c0_ddr4_odt(ddr4_c0_odt), - .c0_ddr4_parity(ddr4_c0_par), - .c0_ddr4_bg(ddr4_c0_bg), - .c0_ddr4_reset_n(ddr4_c0_reset_n), - .c0_ddr4_act_n(ddr4_c0_act_n), - .c0_ddr4_ck_t(ddr4_c0_ck_t), - .c0_ddr4_ck_c(ddr4_c0_ck_c), - - .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), - .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), - - .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), - - .c0_ddr4_s_axi_ctrl_awvalid(1'b0), - .c0_ddr4_s_axi_ctrl_awready(), - .c0_ddr4_s_axi_ctrl_awaddr(32'd0), - .c0_ddr4_s_axi_ctrl_wvalid(1'b0), - .c0_ddr4_s_axi_ctrl_wready(), - .c0_ddr4_s_axi_ctrl_wdata(32'd0), - .c0_ddr4_s_axi_ctrl_bvalid(), - .c0_ddr4_s_axi_ctrl_bready(1'b1), - .c0_ddr4_s_axi_ctrl_bresp(), - .c0_ddr4_s_axi_ctrl_arvalid(1'b0), - .c0_ddr4_s_axi_ctrl_arready(), - .c0_ddr4_s_axi_ctrl_araddr(31'd0), - .c0_ddr4_s_axi_ctrl_rvalid(), - .c0_ddr4_s_axi_ctrl_rready(1'b1), - .c0_ddr4_s_axi_ctrl_rdata(), - .c0_ddr4_s_axi_ctrl_rresp(), - - .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), - .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), - .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), - .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), - .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), - .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), - .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), - .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), - .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), - .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), - .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), - .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), - .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), - .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), - .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), - .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), - .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), - .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), - .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), - .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), - .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), - .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), - .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), - .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), - .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), - .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), - .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), - .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), - .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), - .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), - .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) -); - -end else begin - -assign ddr4_c0_adr = {17{1'bz}}; -assign ddr4_c0_ba = {2{1'bz}}; -assign ddr4_c0_bg = {2{1'bz}}; -assign ddr4_c0_cke = 1'bz; -assign ddr4_c0_cs_n = 1'bz; -assign ddr4_c0_act_n = 1'bz; -assign ddr4_c0_odt = 1'bz; -assign ddr4_c0_par = 1'bz; -assign ddr4_c0_reset_n = 1'b0; -assign ddr4_c0_dq = {72{1'bz}}; -assign ddr4_c0_dqs_t = {18{1'bz}}; -assign ddr4_c0_dqs_c = {18{1'bz}}; - -OBUFTDS ddr4_c0_ck_obuftds_inst ( - .I(1'b0), - .T(1'b1), - .O(ddr4_c0_ck_t), - .OB(ddr4_c0_ck_c) -); - -assign ddr_clk = 0; -assign ddr_rst = 0; - -assign m_axi_ddr_awready = 0; -assign m_axi_ddr_wready = 0; -assign m_axi_ddr_bid = 0; -assign m_axi_ddr_bresp = 0; -assign m_axi_ddr_bvalid = 0; -assign m_axi_ddr_arready = 0; -assign m_axi_ddr_rid = 0; -assign m_axi_ddr_rdata = 0; -assign m_axi_ddr_rresp = 0; -assign m_axi_ddr_rlast = 0; -assign m_axi_ddr_rvalid = 0; - -assign ddr_status = 0; - -end - -if (DDR_ENABLE && DDR_CH > 1) begin - -reg ddr4_rst_reg = 1'b1; - -always @(posedge pcie_user_clk or posedge pcie_user_reset) begin - if (pcie_user_reset) begin - ddr4_rst_reg <= 1'b1; - end else begin - ddr4_rst_reg <= 1'b0; - end -end - -ddr4_0 ddr4_c1_inst ( - .c0_sys_clk_p(clk_300mhz_1_p), - .c0_sys_clk_n(clk_300mhz_1_n), - .sys_rst(ddr4_rst_reg), - - .c0_init_calib_complete(ddr_status[1 +: 1]), - .c0_ddr4_interrupt(), - .dbg_clk(), - .dbg_bus(), - - .c0_ddr4_adr(ddr4_c1_adr), - .c0_ddr4_ba(ddr4_c1_ba), - .c0_ddr4_cke(ddr4_c1_cke), - .c0_ddr4_cs_n(ddr4_c1_cs_n), - .c0_ddr4_dq(ddr4_c1_dq), - .c0_ddr4_dqs_t(ddr4_c1_dqs_t), - .c0_ddr4_dqs_c(ddr4_c1_dqs_c), - .c0_ddr4_odt(ddr4_c1_odt), - .c0_ddr4_parity(ddr4_c1_par), - .c0_ddr4_bg(ddr4_c1_bg), - .c0_ddr4_reset_n(ddr4_c1_reset_n), - .c0_ddr4_act_n(ddr4_c1_act_n), - .c0_ddr4_ck_t(ddr4_c1_ck_t), - .c0_ddr4_ck_c(ddr4_c1_ck_c), - - .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), - .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), - - .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), - - .c0_ddr4_s_axi_ctrl_awvalid(1'b0), - .c0_ddr4_s_axi_ctrl_awready(), - .c0_ddr4_s_axi_ctrl_awaddr(32'd0), - .c0_ddr4_s_axi_ctrl_wvalid(1'b0), - .c0_ddr4_s_axi_ctrl_wready(), - .c0_ddr4_s_axi_ctrl_wdata(32'd0), - .c0_ddr4_s_axi_ctrl_bvalid(), - .c0_ddr4_s_axi_ctrl_bready(1'b1), - .c0_ddr4_s_axi_ctrl_bresp(), - .c0_ddr4_s_axi_ctrl_arvalid(1'b0), - .c0_ddr4_s_axi_ctrl_arready(), - .c0_ddr4_s_axi_ctrl_araddr(31'd0), - .c0_ddr4_s_axi_ctrl_rvalid(), - .c0_ddr4_s_axi_ctrl_rready(1'b1), - .c0_ddr4_s_axi_ctrl_rdata(), - .c0_ddr4_s_axi_ctrl_rresp(), - - .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), - .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), - .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), - .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), - .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), - .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), - .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), - .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), - .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), - .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), - .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), - .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), - .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), - .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), - .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), - .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), - .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), - .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), - .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), - .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), - .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), - .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), - .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), - .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), - .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), - .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), - .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), - .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), - .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), - .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), - .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) -); - -end else begin - -assign ddr4_c1_adr = {17{1'bz}}; -assign ddr4_c1_ba = {2{1'bz}}; -assign ddr4_c1_bg = {2{1'bz}}; -assign ddr4_c1_cke = 1'bz; -assign ddr4_c1_cs_n = 1'bz; -assign ddr4_c1_act_n = 1'bz; -assign ddr4_c1_odt = 1'bz; -assign ddr4_c1_par = 1'bz; -assign ddr4_c1_reset_n = 1'b0; -assign ddr4_c1_dq = {72{1'bz}}; -assign ddr4_c1_dqs_t = {18{1'bz}}; -assign ddr4_c1_dqs_c = {18{1'bz}}; - -OBUFTDS ddr4_c1_ck_obuftds_inst ( - .I(1'b0), - .T(1'b1), - .O(ddr4_c1_ck_t), - .OB(ddr4_c1_ck_c) -); - -end - -if (DDR_ENABLE && DDR_CH > 2) begin - -reg ddr4_rst_reg = 1'b1; - -always @(posedge pcie_user_clk or posedge pcie_user_reset) begin - if (pcie_user_reset) begin - ddr4_rst_reg <= 1'b1; - end else begin - ddr4_rst_reg <= 1'b0; - end -end - -ddr4_0 ddr4_c2_inst ( - .c0_sys_clk_p(clk_300mhz_2_p), - .c0_sys_clk_n(clk_300mhz_2_n), - .sys_rst(ddr4_rst_reg), - - .c0_init_calib_complete(ddr_status[2 +: 1]), - .c0_ddr4_interrupt(), - .dbg_clk(), - .dbg_bus(), - - .c0_ddr4_adr(ddr4_c2_adr), - .c0_ddr4_ba(ddr4_c2_ba), - .c0_ddr4_cke(ddr4_c2_cke), - .c0_ddr4_cs_n(ddr4_c2_cs_n), - .c0_ddr4_dq(ddr4_c2_dq), - .c0_ddr4_dqs_t(ddr4_c2_dqs_t), - .c0_ddr4_dqs_c(ddr4_c2_dqs_c), - .c0_ddr4_odt(ddr4_c2_odt), - .c0_ddr4_parity(ddr4_c2_par), - .c0_ddr4_bg(ddr4_c2_bg), - .c0_ddr4_reset_n(ddr4_c2_reset_n), - .c0_ddr4_act_n(ddr4_c2_act_n), - .c0_ddr4_ck_t(ddr4_c2_ck_t), - .c0_ddr4_ck_c(ddr4_c2_ck_c), - - .c0_ddr4_ui_clk(ddr_clk[2 +: 1]), - .c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]), - - .c0_ddr4_aresetn(!ddr_rst[2 +: 1]), - - .c0_ddr4_s_axi_ctrl_awvalid(1'b0), - .c0_ddr4_s_axi_ctrl_awready(), - .c0_ddr4_s_axi_ctrl_awaddr(32'd0), - .c0_ddr4_s_axi_ctrl_wvalid(1'b0), - .c0_ddr4_s_axi_ctrl_wready(), - .c0_ddr4_s_axi_ctrl_wdata(32'd0), - .c0_ddr4_s_axi_ctrl_bvalid(), - .c0_ddr4_s_axi_ctrl_bready(1'b1), - .c0_ddr4_s_axi_ctrl_bresp(), - .c0_ddr4_s_axi_ctrl_arvalid(1'b0), - .c0_ddr4_s_axi_ctrl_arready(), - .c0_ddr4_s_axi_ctrl_araddr(31'd0), - .c0_ddr4_s_axi_ctrl_rvalid(), - .c0_ddr4_s_axi_ctrl_rready(1'b1), - .c0_ddr4_s_axi_ctrl_rdata(), - .c0_ddr4_s_axi_ctrl_rresp(), - - .c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]), - .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]), - .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]), - .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]), - .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]), - .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]), - .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]), - .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]), - .c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]), - .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), - .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), - .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]), - .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]), - .c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]), - .c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]), - .c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]), - .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]), - .c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]), - .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]), - .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]), - .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]), - .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]), - .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]), - .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]), - .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]), - .c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]), - .c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]), - .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]), - .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]), - .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]), - .c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) -); - -end else begin - -assign ddr4_c2_adr = {17{1'bz}}; -assign ddr4_c2_ba = {2{1'bz}}; -assign ddr4_c2_bg = {2{1'bz}}; -assign ddr4_c2_cke = 1'bz; -assign ddr4_c2_cs_n = 1'bz; -assign ddr4_c2_act_n = 1'bz; -assign ddr4_c2_odt = 1'bz; -assign ddr4_c2_par = 1'bz; -assign ddr4_c2_reset_n = 1'b0; -assign ddr4_c2_dq = {72{1'bz}}; -assign ddr4_c2_dqs_t = {18{1'bz}}; -assign ddr4_c2_dqs_c = {18{1'bz}}; - -OBUFTDS ddr4_c2_ck_obuftds_inst ( - .I(1'b0), - .T(1'b1), - .O(ddr4_c2_ck_t), - .OB(ddr4_c2_ck_c) -); - -end - -if (DDR_ENABLE && DDR_CH > 3) begin - -reg ddr4_rst_reg = 1'b1; - -always @(posedge pcie_user_clk or posedge pcie_user_reset) begin - if (pcie_user_reset) begin - ddr4_rst_reg <= 1'b1; - end else begin - ddr4_rst_reg <= 1'b0; - end -end - -ddr4_0 ddr4_c3_inst ( - .c0_sys_clk_p(clk_300mhz_3_p), - .c0_sys_clk_n(clk_300mhz_3_n), - .sys_rst(ddr4_rst_reg), - - .c0_init_calib_complete(ddr_status[3 +: 1]), - .c0_ddr4_interrupt(), - .dbg_clk(), - .dbg_bus(), - - .c0_ddr4_adr(ddr4_c3_adr), - .c0_ddr4_ba(ddr4_c3_ba), - .c0_ddr4_cke(ddr4_c3_cke), - .c0_ddr4_cs_n(ddr4_c3_cs_n), - .c0_ddr4_dq(ddr4_c3_dq), - .c0_ddr4_dqs_t(ddr4_c3_dqs_t), - .c0_ddr4_dqs_c(ddr4_c3_dqs_c), - .c0_ddr4_odt(ddr4_c3_odt), - .c0_ddr4_parity(ddr4_c3_par), - .c0_ddr4_bg(ddr4_c3_bg), - .c0_ddr4_reset_n(ddr4_c3_reset_n), - .c0_ddr4_act_n(ddr4_c3_act_n), - .c0_ddr4_ck_t(ddr4_c3_ck_t), - .c0_ddr4_ck_c(ddr4_c3_ck_c), - - .c0_ddr4_ui_clk(ddr_clk[3 +: 1]), - .c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]), - - .c0_ddr4_aresetn(!ddr_rst[3 +: 1]), - - .c0_ddr4_s_axi_ctrl_awvalid(1'b0), - .c0_ddr4_s_axi_ctrl_awready(), - .c0_ddr4_s_axi_ctrl_awaddr(32'd0), - .c0_ddr4_s_axi_ctrl_wvalid(1'b0), - .c0_ddr4_s_axi_ctrl_wready(), - .c0_ddr4_s_axi_ctrl_wdata(32'd0), - .c0_ddr4_s_axi_ctrl_bvalid(), - .c0_ddr4_s_axi_ctrl_bready(1'b1), - .c0_ddr4_s_axi_ctrl_bresp(), - .c0_ddr4_s_axi_ctrl_arvalid(1'b0), - .c0_ddr4_s_axi_ctrl_arready(), - .c0_ddr4_s_axi_ctrl_araddr(31'd0), - .c0_ddr4_s_axi_ctrl_rvalid(), - .c0_ddr4_s_axi_ctrl_rready(1'b1), - .c0_ddr4_s_axi_ctrl_rdata(), - .c0_ddr4_s_axi_ctrl_rresp(), - - .c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]), - .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]), - .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]), - .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]), - .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]), - .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]), - .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]), - .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]), - .c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]), - .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), - .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), - .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]), - .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]), - .c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]), - .c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]), - .c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]), - .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]), - .c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]), - .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]), - .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]), - .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]), - .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]), - .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]), - .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]), - .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]), - .c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]), - .c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]), - .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]), - .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]), - .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]), - .c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) -); - -end else begin - -assign ddr4_c3_adr = {17{1'bz}}; -assign ddr4_c3_ba = {2{1'bz}}; -assign ddr4_c3_bg = {2{1'bz}}; -assign ddr4_c3_cke = 1'bz; -assign ddr4_c3_cs_n = 1'bz; -assign ddr4_c3_act_n = 1'bz; -assign ddr4_c3_odt = 1'bz; -assign ddr4_c3_par = 1'bz; -assign ddr4_c3_reset_n = 1'b0; -assign ddr4_c3_dq = {72{1'bz}}; -assign ddr4_c3_dqs_t = {18{1'bz}}; -assign ddr4_c3_dqs_c = {18{1'bz}}; - -OBUFTDS ddr4_c3_ck_obuftds_inst ( - .I(1'b0), - .T(1'b1), - .O(ddr4_c3_ck_t), - .OB(ddr4_c3_ck_c) -); - -end - -endgenerate - -fpga_core #( - // FW and board IDs - .FPGA_ID(FPGA_ID), - .FW_ID(FW_ID), - .FW_VER(FW_VER), - .BOARD_ID(BOARD_ID), - .BOARD_VER(BOARD_VER), - .BUILD_DATE(BUILD_DATE), - .GIT_HASH(GIT_HASH), - .RELEASE_INFO(RELEASE_INFO), - - // Structural configuration - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - .SCHED_PER_IF(SCHED_PER_IF), - .PORT_MASK(PORT_MASK), - - // Clock configuration - .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), - .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), - - // PTP configuration - .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), - .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), - .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), - .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), - - // Queue manager configuration - .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), - .EQN_WIDTH(EQN_WIDTH), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .CQN_WIDTH(CQN_WIDTH), - .EQ_PIPELINE(EQ_PIPELINE), - .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), - .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .CQ_PIPELINE(CQ_PIPELINE), - - // TX and RX engine configuration - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), - - // Scheduler configuration - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - - // Interface configuration - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), - .TX_TAG_WIDTH(TX_TAG_WIDTH), - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .PFC_ENABLE(PFC_ENABLE), - .LFC_ENABLE(LFC_ENABLE), - .TX_FIFO_DEPTH(TX_FIFO_DEPTH), - .RX_FIFO_DEPTH(RX_FIFO_DEPTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - - // RAM configuration - .DDR_CH(DDR_CH), - .DDR_ENABLE(DDR_ENABLE), - .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), - .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), - .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), - .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), - .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), - .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), - - // Application block configuration - .APP_ID(APP_ID), - .APP_ENABLE(APP_ENABLE), - .APP_CTRL_ENABLE(APP_CTRL_ENABLE), - .APP_DMA_ENABLE(APP_DMA_ENABLE), - .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), - .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), - .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), - .APP_STAT_ENABLE(APP_STAT_ENABLE), - - // DMA interface configuration - .DMA_IMM_ENABLE(DMA_IMM_ENABLE), - .DMA_IMM_WIDTH(DMA_IMM_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - - // PCIe interface configuration - .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), - .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), - .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), - .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), - .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), - .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), - .RC_STRADDLE(RC_STRADDLE), - .RQ_STRADDLE(RQ_STRADDLE), - .CQ_STRADDLE(CQ_STRADDLE), - .CC_STRADDLE(CC_STRADDLE), - .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), - .PF_COUNT(PF_COUNT), - .VF_COUNT(VF_COUNT), - .PCIE_TAG_COUNT(PCIE_TAG_COUNT), - - // Interrupt configuration - .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), - - // AXI lite interface configuration (control) - .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - - // AXI lite interface configuration (application control) - .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), - .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), - - // Ethernet interface configuration - .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), - .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), - .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), - .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), - .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), - .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), - - // Statistics counter subsystem - .STAT_ENABLE(STAT_ENABLE), - .STAT_DMA_ENABLE(STAT_DMA_ENABLE), - .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), - .STAT_INC_WIDTH(STAT_INC_WIDTH), - .STAT_ID_WIDTH(STAT_ID_WIDTH) -) -core_inst ( - /* - * Clock: 250 MHz - * Synchronous reset - */ - .clk_250mhz(pcie_user_clk), - .rst_250mhz(pcie_user_reset), - - /* - * PTP clock - */ - .ptp_clk(ptp_clk), - .ptp_rst(ptp_rst), - .ptp_sample_clk(ptp_sample_clk), - - /* - * GPIO - */ - .sw(sw_int), - .led(led_int), - - /* - * I2C - */ - .i2c_scl_i(i2c_scl_i), - .i2c_scl_o(i2c_scl_o), - .i2c_scl_t(i2c_scl_t), - .i2c_sda_i(i2c_sda_i), - .i2c_sda_o(i2c_sda_o), - .i2c_sda_t(i2c_sda_t), - - /* - * PCIe - */ - .m_axis_rq_tdata(axis_rq_tdata), - .m_axis_rq_tkeep(axis_rq_tkeep), - .m_axis_rq_tlast(axis_rq_tlast), - .m_axis_rq_tready(axis_rq_tready), - .m_axis_rq_tuser(axis_rq_tuser), - .m_axis_rq_tvalid(axis_rq_tvalid), - - .s_axis_rc_tdata(axis_rc_tdata), - .s_axis_rc_tkeep(axis_rc_tkeep), - .s_axis_rc_tlast(axis_rc_tlast), - .s_axis_rc_tready(axis_rc_tready), - .s_axis_rc_tuser(axis_rc_tuser), - .s_axis_rc_tvalid(axis_rc_tvalid), - - .s_axis_cq_tdata(axis_cq_tdata), - .s_axis_cq_tkeep(axis_cq_tkeep), - .s_axis_cq_tlast(axis_cq_tlast), - .s_axis_cq_tready(axis_cq_tready), - .s_axis_cq_tuser(axis_cq_tuser), - .s_axis_cq_tvalid(axis_cq_tvalid), - - .m_axis_cc_tdata(axis_cc_tdata), - .m_axis_cc_tkeep(axis_cc_tkeep), - .m_axis_cc_tlast(axis_cc_tlast), - .m_axis_cc_tready(axis_cc_tready), - .m_axis_cc_tuser(axis_cc_tuser), - .m_axis_cc_tvalid(axis_cc_tvalid), - - .s_axis_rq_seq_num_0(pcie_rq_seq_num0), - .s_axis_rq_seq_num_valid_0(pcie_rq_seq_num_vld0), - .s_axis_rq_seq_num_1(pcie_rq_seq_num1), - .s_axis_rq_seq_num_valid_1(pcie_rq_seq_num_vld1), - - .pcie_tfc_nph_av(pcie_tfc_nph_av), - .pcie_tfc_npd_av(pcie_tfc_npd_av), - - .cfg_max_payload(cfg_max_payload), - .cfg_max_read_req(cfg_max_read_req), - .cfg_rcb_status(cfg_rcb_status), - - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), - .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), - .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), - .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), - .cfg_interrupt_msix_address(cfg_interrupt_msix_address), - .cfg_interrupt_msix_data(cfg_interrupt_msix_data), - .cfg_interrupt_msix_int(cfg_interrupt_msix_int), - .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), - .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), - .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), - .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - .status_error_cor(status_error_cor), - .status_error_uncor(status_error_uncor), - - /* - * Ethernet: QSFP28 - */ - .qsfp0_tx_clk(qsfp0_tx_clk_int), - .qsfp0_tx_rst(qsfp0_tx_rst_int), - .qsfp0_tx_axis_tdata(qsfp0_tx_axis_tdata_int), - .qsfp0_tx_axis_tkeep(qsfp0_tx_axis_tkeep_int), - .qsfp0_tx_axis_tvalid(qsfp0_tx_axis_tvalid_int), - .qsfp0_tx_axis_tready(qsfp0_tx_axis_tready_int), - .qsfp0_tx_axis_tlast(qsfp0_tx_axis_tlast_int), - .qsfp0_tx_axis_tuser(qsfp0_tx_axis_tuser_int), - .qsfp0_tx_ptp_time(qsfp0_tx_ptp_time_int), - .qsfp0_tx_ptp_ts(qsfp0_tx_ptp_ts_int), - .qsfp0_tx_ptp_ts_tag(qsfp0_tx_ptp_ts_tag_int), - .qsfp0_tx_ptp_ts_valid(qsfp0_tx_ptp_ts_valid_int), - - .qsfp0_tx_enable(qsfp0_tx_enable), - .qsfp0_tx_lfc_en(qsfp0_tx_lfc_en), - .qsfp0_tx_lfc_req(qsfp0_tx_lfc_req), - .qsfp0_tx_pfc_en(qsfp0_tx_pfc_en), - .qsfp0_tx_pfc_req(qsfp0_tx_pfc_req), - - .qsfp0_rx_clk(qsfp0_rx_clk_int), - .qsfp0_rx_rst(qsfp0_rx_rst_int), - .qsfp0_rx_axis_tdata(qsfp0_rx_axis_tdata_int), - .qsfp0_rx_axis_tkeep(qsfp0_rx_axis_tkeep_int), - .qsfp0_rx_axis_tvalid(qsfp0_rx_axis_tvalid_int), - .qsfp0_rx_axis_tlast(qsfp0_rx_axis_tlast_int), - .qsfp0_rx_axis_tuser(qsfp0_rx_axis_tuser_int), - .qsfp0_rx_ptp_clk(qsfp0_rx_ptp_clk_int), - .qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int), - .qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int), - - .qsfp0_rx_enable(qsfp0_rx_enable), - .qsfp0_rx_status(qsfp0_rx_status), - .qsfp0_rx_lfc_en(qsfp0_rx_lfc_en), - .qsfp0_rx_lfc_req(qsfp0_rx_lfc_req), - .qsfp0_rx_lfc_ack(qsfp0_rx_lfc_ack), - .qsfp0_rx_pfc_en(qsfp0_rx_pfc_en), - .qsfp0_rx_pfc_req(qsfp0_rx_pfc_req), - .qsfp0_rx_pfc_ack(qsfp0_rx_pfc_ack), - - .qsfp0_drp_clk(qsfp0_drp_clk), - .qsfp0_drp_rst(qsfp0_drp_rst), - .qsfp0_drp_addr(qsfp0_drp_addr), - .qsfp0_drp_di(qsfp0_drp_di), - .qsfp0_drp_en(qsfp0_drp_en), - .qsfp0_drp_we(qsfp0_drp_we), - .qsfp0_drp_do(qsfp0_drp_do), - .qsfp0_drp_rdy(qsfp0_drp_rdy), - - .qsfp0_modprsl(qsfp0_modprsl_int), - .qsfp0_modsell(qsfp0_modsell), - .qsfp0_resetl(qsfp0_resetl), - .qsfp0_intl(qsfp0_intl_int), - .qsfp0_lpmode(qsfp0_lpmode), - - .qsfp1_tx_clk(qsfp1_tx_clk_int), - .qsfp1_tx_rst(qsfp1_tx_rst_int), - .qsfp1_tx_axis_tdata(qsfp1_tx_axis_tdata_int), - .qsfp1_tx_axis_tkeep(qsfp1_tx_axis_tkeep_int), - .qsfp1_tx_axis_tvalid(qsfp1_tx_axis_tvalid_int), - .qsfp1_tx_axis_tready(qsfp1_tx_axis_tready_int), - .qsfp1_tx_axis_tlast(qsfp1_tx_axis_tlast_int), - .qsfp1_tx_axis_tuser(qsfp1_tx_axis_tuser_int), - .qsfp1_tx_ptp_time(qsfp1_tx_ptp_time_int), - .qsfp1_tx_ptp_ts(qsfp1_tx_ptp_ts_int), - .qsfp1_tx_ptp_ts_tag(qsfp1_tx_ptp_ts_tag_int), - .qsfp1_tx_ptp_ts_valid(qsfp1_tx_ptp_ts_valid_int), - - .qsfp1_tx_enable(qsfp1_tx_enable), - .qsfp1_tx_lfc_en(qsfp1_tx_lfc_en), - .qsfp1_tx_lfc_req(qsfp1_tx_lfc_req), - .qsfp1_tx_pfc_en(qsfp1_tx_pfc_en), - .qsfp1_tx_pfc_req(qsfp1_tx_pfc_req), - - .qsfp1_rx_clk(qsfp1_rx_clk_int), - .qsfp1_rx_rst(qsfp1_rx_rst_int), - .qsfp1_rx_axis_tdata(qsfp1_rx_axis_tdata_int), - .qsfp1_rx_axis_tkeep(qsfp1_rx_axis_tkeep_int), - .qsfp1_rx_axis_tvalid(qsfp1_rx_axis_tvalid_int), - .qsfp1_rx_axis_tlast(qsfp1_rx_axis_tlast_int), - .qsfp1_rx_axis_tuser(qsfp1_rx_axis_tuser_int), - .qsfp1_rx_ptp_clk(qsfp1_rx_ptp_clk_int), - .qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int), - .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int), - - .qsfp1_rx_enable(qsfp1_rx_enable), - .qsfp1_rx_status(qsfp1_rx_status), - .qsfp1_rx_lfc_en(qsfp1_rx_lfc_en), - .qsfp1_rx_lfc_req(qsfp1_rx_lfc_req), - .qsfp1_rx_lfc_ack(qsfp1_rx_lfc_ack), - .qsfp1_rx_pfc_en(qsfp1_rx_pfc_en), - .qsfp1_rx_pfc_req(qsfp1_rx_pfc_req), - .qsfp1_rx_pfc_ack(qsfp1_rx_pfc_ack), - - .qsfp1_drp_clk(qsfp1_drp_clk), - .qsfp1_drp_rst(qsfp1_drp_rst), - .qsfp1_drp_addr(qsfp1_drp_addr), - .qsfp1_drp_di(qsfp1_drp_di), - .qsfp1_drp_en(qsfp1_drp_en), - .qsfp1_drp_we(qsfp1_drp_we), - .qsfp1_drp_do(qsfp1_drp_do), - .qsfp1_drp_rdy(qsfp1_drp_rdy), - - .qsfp1_modprsl(qsfp1_modprsl_int), - .qsfp1_modsell(qsfp1_modsell), - .qsfp1_resetl(qsfp1_resetl), - .qsfp1_intl(qsfp1_intl_int), - .qsfp1_lpmode(qsfp1_lpmode), - - /* - * DDR - */ - .ddr_clk(ddr_clk), - .ddr_rst(ddr_rst), - - .m_axi_ddr_awid(m_axi_ddr_awid), - .m_axi_ddr_awaddr(m_axi_ddr_awaddr), - .m_axi_ddr_awlen(m_axi_ddr_awlen), - .m_axi_ddr_awsize(m_axi_ddr_awsize), - .m_axi_ddr_awburst(m_axi_ddr_awburst), - .m_axi_ddr_awlock(m_axi_ddr_awlock), - .m_axi_ddr_awcache(m_axi_ddr_awcache), - .m_axi_ddr_awprot(m_axi_ddr_awprot), - .m_axi_ddr_awqos(m_axi_ddr_awqos), - .m_axi_ddr_awvalid(m_axi_ddr_awvalid), - .m_axi_ddr_awready(m_axi_ddr_awready), - .m_axi_ddr_wdata(m_axi_ddr_wdata), - .m_axi_ddr_wstrb(m_axi_ddr_wstrb), - .m_axi_ddr_wlast(m_axi_ddr_wlast), - .m_axi_ddr_wvalid(m_axi_ddr_wvalid), - .m_axi_ddr_wready(m_axi_ddr_wready), - .m_axi_ddr_bid(m_axi_ddr_bid), - .m_axi_ddr_bresp(m_axi_ddr_bresp), - .m_axi_ddr_bvalid(m_axi_ddr_bvalid), - .m_axi_ddr_bready(m_axi_ddr_bready), - .m_axi_ddr_arid(m_axi_ddr_arid), - .m_axi_ddr_araddr(m_axi_ddr_araddr), - .m_axi_ddr_arlen(m_axi_ddr_arlen), - .m_axi_ddr_arsize(m_axi_ddr_arsize), - .m_axi_ddr_arburst(m_axi_ddr_arburst), - .m_axi_ddr_arlock(m_axi_ddr_arlock), - .m_axi_ddr_arcache(m_axi_ddr_arcache), - .m_axi_ddr_arprot(m_axi_ddr_arprot), - .m_axi_ddr_arqos(m_axi_ddr_arqos), - .m_axi_ddr_arvalid(m_axi_ddr_arvalid), - .m_axi_ddr_arready(m_axi_ddr_arready), - .m_axi_ddr_rid(m_axi_ddr_rid), - .m_axi_ddr_rdata(m_axi_ddr_rdata), - .m_axi_ddr_rresp(m_axi_ddr_rresp), - .m_axi_ddr_rlast(m_axi_ddr_rlast), - .m_axi_ddr_rvalid(m_axi_ddr_rvalid), - .m_axi_ddr_rready(m_axi_ddr_rready), - - .ddr_status(ddr_status), - - /* - * QSPI flash - */ - .fpga_boot(fpga_boot), - .qspi_clk(qspi_clk_int), - .qspi_dq_i(qspi_dq_i_int), - .qspi_dq_o(qspi_dq_o_int), - .qspi_dq_oe(qspi_dq_oe_int), - .qspi_cs(qspi_cs_int) -); - -endmodule - -`resetall diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v deleted file mode 100644 index d0b52a2ae..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v +++ /dev/null @@ -1,1464 +0,0 @@ -// SPDX-License-Identifier: BSD-2-Clause-Views -/* - * Copyright (c) 2019-2023 The Regents of the University of California - */ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA core logic - */ -module fpga_core # -( - // FW and board IDs - parameter FPGA_ID = 32'h4B31093, - parameter FW_ID = 32'h00000000, - parameter FW_VER = 32'h00_00_01_00, - parameter BOARD_ID = 32'h10ee_95f5, - parameter BOARD_VER = 32'h01_00_00_00, - parameter BUILD_DATE = 32'd602976000, - parameter GIT_HASH = 32'hdce357bf, - parameter RELEASE_INFO = 32'h00000000, - - // Structural configuration - parameter IF_COUNT = 2, - parameter PORTS_PER_IF = 1, - parameter SCHED_PER_IF = PORTS_PER_IF, - parameter PORT_MASK = 0, - - // Clock configuration - parameter CLK_PERIOD_NS_NUM = 4, - parameter CLK_PERIOD_NS_DENOM = 1, - - // PTP configuration - parameter PTP_CLK_PERIOD_NS_NUM = 1024, - parameter PTP_CLK_PERIOD_NS_DENOM = 165, - parameter PTP_TS_WIDTH = 96, - parameter PTP_CLOCK_PIPELINE = 0, - parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_SEPARATE_RX_CLOCK = 0, - parameter PTP_PORT_CDC_PIPELINE = 0, - parameter PTP_PEROUT_ENABLE = 0, - parameter PTP_PEROUT_COUNT = 1, - - // Queue manager configuration - parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_QUEUE_OP_TABLE_SIZE = 32, - parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter CQ_OP_TABLE_SIZE = 32, - parameter EQN_WIDTH = 5, - parameter TX_QUEUE_INDEX_WIDTH = 13, - parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, - parameter EQ_PIPELINE = 3, - parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), - parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), - - // TX and RX engine configuration - parameter TX_DESC_TABLE_SIZE = 32, - parameter RX_DESC_TABLE_SIZE = 32, - parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, - - // Scheduler configuration - parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, - parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, - parameter TDMA_INDEX_WIDTH = 6, - - // Interface configuration - parameter PTP_TS_ENABLE = 1, - parameter TX_CPL_FIFO_DEPTH = 32, - parameter TX_TAG_WIDTH = 16, - parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_HASH_ENABLE = 1, - parameter RX_CHECKSUM_ENABLE = 1, - parameter PFC_ENABLE = 1, - parameter LFC_ENABLE = PFC_ENABLE, - parameter TX_FIFO_DEPTH = 32768, - parameter RX_FIFO_DEPTH = 131072, - parameter MAX_TX_SIZE = 9214, - parameter MAX_RX_SIZE = 9214, - parameter TX_RAM_SIZE = 131072, - parameter RX_RAM_SIZE = 131072, - - // RAM configuration - parameter DDR_CH = 4, - parameter DDR_ENABLE = 0, - parameter AXI_DDR_DATA_WIDTH = 512, - parameter AXI_DDR_ADDR_WIDTH = 34, - parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), - parameter AXI_DDR_ID_WIDTH = 8, - parameter AXI_DDR_MAX_BURST_LEN = 256, - parameter AXI_DDR_NARROW_BURST = 0, - - // Application block configuration - parameter APP_ID = 32'h00000000, - parameter APP_ENABLE = 0, - parameter APP_CTRL_ENABLE = 1, - parameter APP_DMA_ENABLE = 1, - parameter APP_AXIS_DIRECT_ENABLE = 1, - parameter APP_AXIS_SYNC_ENABLE = 1, - parameter APP_AXIS_IF_ENABLE = 1, - parameter APP_STAT_ENABLE = 1, - - // DMA interface configuration - parameter DMA_IMM_ENABLE = 0, - parameter DMA_IMM_WIDTH = 32, - parameter DMA_LEN_WIDTH = 16, - parameter DMA_TAG_WIDTH = 16, - parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), - parameter RAM_PIPELINE = 2, - - // PCIe interface configuration - parameter AXIS_PCIE_DATA_WIDTH = 512, - parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), - parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161, - parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137, - parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183, - parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81, - parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256, - parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6, - parameter PF_COUNT = 1, - parameter VF_COUNT = 0, - parameter PCIE_TAG_COUNT = 256, - - // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EQN_WIDTH, - - // AXI lite interface configuration (control) - parameter AXIL_CTRL_DATA_WIDTH = 32, - parameter AXIL_CTRL_ADDR_WIDTH = 24, - - // AXI lite interface configuration (application control) - parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, - parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, - - // Ethernet interface configuration - parameter AXIS_ETH_DATA_WIDTH = 512, - parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, - parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH, - parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1, - parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, - parameter AXIS_ETH_TX_PIPELINE = 4, - parameter AXIS_ETH_TX_FIFO_PIPELINE = 4, - parameter AXIS_ETH_TX_TS_PIPELINE = 4, - parameter AXIS_ETH_RX_PIPELINE = 4, - parameter AXIS_ETH_RX_FIFO_PIPELINE = 4, - - // Statistics counter subsystem - parameter STAT_ENABLE = 1, - parameter STAT_DMA_ENABLE = 1, - parameter STAT_PCIE_ENABLE = 1, - parameter STAT_INC_WIDTH = 24, - parameter STAT_ID_WIDTH = 12 -) -( - /* - * Clock: 250 MHz - * Synchronous reset - */ - input wire clk_250mhz, - input wire rst_250mhz, - - /* - * PTP clock - */ - input wire ptp_clk, - input wire ptp_rst, - input wire ptp_sample_clk, - - /* - * GPIO - */ - input wire [3:0] sw, - output wire [2:0] led, - - /* - * I2C - */ - input wire i2c_scl_i, - output wire i2c_scl_o, - output wire i2c_scl_t, - input wire i2c_sda_i, - output wire i2c_sda_o, - output wire i2c_sda_t, - - /* - * PCIe - */ - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, - output wire m_axis_rq_tlast, - input wire m_axis_rq_tready, - output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser, - output wire m_axis_rq_tvalid, - - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, - input wire s_axis_rc_tlast, - output wire s_axis_rc_tready, - input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser, - input wire s_axis_rc_tvalid, - - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, - input wire s_axis_cq_tlast, - output wire s_axis_cq_tready, - input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser, - input wire s_axis_cq_tvalid, - - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, - output wire m_axis_cc_tlast, - input wire m_axis_cc_tready, - output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser, - output wire m_axis_cc_tvalid, - - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0, - input wire s_axis_rq_seq_num_valid_0, - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1, - input wire s_axis_rq_seq_num_valid_1, - - input wire [1:0] pcie_tfc_nph_av, - input wire [1:0] pcie_tfc_npd_av, - - input wire [2:0] cfg_max_payload, - input wire [2:0] cfg_max_read_req, - input wire [3:0] cfg_rcb_status, - - output wire [9:0] cfg_mgmt_addr, - output wire [7:0] cfg_mgmt_function_number, - output wire cfg_mgmt_write, - output wire [31:0] cfg_mgmt_write_data, - output wire [3:0] cfg_mgmt_byte_enable, - output wire cfg_mgmt_read, - input wire [31:0] cfg_mgmt_read_data, - input wire cfg_mgmt_read_write_done, - - input wire [7:0] cfg_fc_ph, - input wire [11:0] cfg_fc_pd, - input wire [7:0] cfg_fc_nph, - input wire [11:0] cfg_fc_npd, - input wire [7:0] cfg_fc_cplh, - input wire [11:0] cfg_fc_cpld, - output wire [2:0] cfg_fc_sel, - - input wire [3:0] cfg_interrupt_msix_enable, - input wire [3:0] cfg_interrupt_msix_mask, - input wire [251:0] cfg_interrupt_msix_vf_enable, - input wire [251:0] cfg_interrupt_msix_vf_mask, - output wire [63:0] cfg_interrupt_msix_address, - output wire [31:0] cfg_interrupt_msix_data, - output wire cfg_interrupt_msix_int, - output wire [1:0] cfg_interrupt_msix_vec_pending, - input wire cfg_interrupt_msix_vec_pending_status, - input wire cfg_interrupt_msix_sent, - input wire cfg_interrupt_msix_fail, - output wire [7:0] cfg_interrupt_msi_function_number, - - output wire status_error_cor, - output wire status_error_uncor, - - /* - * Ethernet: QSFP28 - */ - input wire qsfp0_tx_clk, - input wire qsfp0_tx_rst, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_tx_axis_tkeep, - output wire qsfp0_tx_axis_tvalid, - input wire qsfp0_tx_axis_tready, - output wire qsfp0_tx_axis_tlast, - output wire [16+1-1:0] qsfp0_tx_axis_tuser, - - output wire [79:0] qsfp0_tx_ptp_time, - input wire [79:0] qsfp0_tx_ptp_ts, - input wire [15:0] qsfp0_tx_ptp_ts_tag, - input wire qsfp0_tx_ptp_ts_valid, - - output wire qsfp0_tx_enable, - output wire qsfp0_tx_lfc_en, - output wire qsfp0_tx_lfc_req, - output wire [7:0] qsfp0_tx_pfc_en, - output wire [7:0] qsfp0_tx_pfc_req, - - input wire qsfp0_rx_clk, - input wire qsfp0_rx_rst, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp0_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp0_rx_axis_tkeep, - input wire qsfp0_rx_axis_tvalid, - input wire qsfp0_rx_axis_tlast, - input wire [80+1-1:0] qsfp0_rx_axis_tuser, - - input wire qsfp0_rx_ptp_clk, - input wire qsfp0_rx_ptp_rst, - output wire [79:0] qsfp0_rx_ptp_time, - - output wire qsfp0_rx_enable, - input wire qsfp0_rx_status, - output wire qsfp0_rx_lfc_en, - input wire qsfp0_rx_lfc_req, - output wire qsfp0_rx_lfc_ack, - output wire [7:0] qsfp0_rx_pfc_en, - input wire [7:0] qsfp0_rx_pfc_req, - output wire [7:0] qsfp0_rx_pfc_ack, - - input wire qsfp0_drp_clk, - input wire qsfp0_drp_rst, - output wire [23:0] qsfp0_drp_addr, - output wire [15:0] qsfp0_drp_di, - output wire qsfp0_drp_en, - output wire qsfp0_drp_we, - input wire [15:0] qsfp0_drp_do, - input wire qsfp0_drp_rdy, - - output wire qsfp0_modsell, - output wire qsfp0_resetl, - input wire qsfp0_modprsl, - input wire qsfp0_intl, - output wire qsfp0_lpmode, - - input wire qsfp1_tx_clk, - input wire qsfp1_tx_rst, - - output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_tx_axis_tdata, - output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_tx_axis_tkeep, - output wire qsfp1_tx_axis_tvalid, - input wire qsfp1_tx_axis_tready, - output wire qsfp1_tx_axis_tlast, - output wire [16+1-1:0] qsfp1_tx_axis_tuser, - - output wire [79:0] qsfp1_tx_ptp_time, - input wire [79:0] qsfp1_tx_ptp_ts, - input wire [15:0] qsfp1_tx_ptp_ts_tag, - input wire qsfp1_tx_ptp_ts_valid, - - output wire qsfp1_tx_enable, - output wire qsfp1_tx_lfc_en, - output wire qsfp1_tx_lfc_req, - output wire [7:0] qsfp1_tx_pfc_en, - output wire [7:0] qsfp1_tx_pfc_req, - - input wire qsfp1_rx_clk, - input wire qsfp1_rx_rst, - - input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_rx_axis_tdata, - input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_rx_axis_tkeep, - input wire qsfp1_rx_axis_tvalid, - input wire qsfp1_rx_axis_tlast, - input wire [80+1-1:0] qsfp1_rx_axis_tuser, - - input wire qsfp1_rx_ptp_clk, - input wire qsfp1_rx_ptp_rst, - output wire [79:0] qsfp1_rx_ptp_time, - - output wire qsfp1_rx_enable, - input wire qsfp1_rx_status, - output wire qsfp1_rx_lfc_en, - input wire qsfp1_rx_lfc_req, - output wire qsfp1_rx_lfc_ack, - output wire [7:0] qsfp1_rx_pfc_en, - input wire [7:0] qsfp1_rx_pfc_req, - output wire [7:0] qsfp1_rx_pfc_ack, - - input wire qsfp1_drp_clk, - input wire qsfp1_drp_rst, - output wire [23:0] qsfp1_drp_addr, - output wire [15:0] qsfp1_drp_di, - output wire qsfp1_drp_en, - output wire qsfp1_drp_we, - input wire [15:0] qsfp1_drp_do, - input wire qsfp1_drp_rdy, - - output wire qsfp1_modsell, - output wire qsfp1_resetl, - input wire qsfp1_modprsl, - input wire qsfp1_intl, - output wire qsfp1_lpmode, - - /* - * DDR - */ - input wire [DDR_CH-1:0] ddr_clk, - input wire [DDR_CH-1:0] ddr_rst, - - output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, - output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, - output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, - output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, - output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, - output wire [DDR_CH-1:0] m_axi_ddr_awlock, - output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, - output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, - output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, - output wire [DDR_CH-1:0] m_axi_ddr_awvalid, - input wire [DDR_CH-1:0] m_axi_ddr_awready, - output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, - output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, - output wire [DDR_CH-1:0] m_axi_ddr_wlast, - output wire [DDR_CH-1:0] m_axi_ddr_wvalid, - input wire [DDR_CH-1:0] m_axi_ddr_wready, - input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, - input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, - input wire [DDR_CH-1:0] m_axi_ddr_bvalid, - output wire [DDR_CH-1:0] m_axi_ddr_bready, - output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, - output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, - output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, - output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, - output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, - output wire [DDR_CH-1:0] m_axi_ddr_arlock, - output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, - output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, - output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, - output wire [DDR_CH-1:0] m_axi_ddr_arvalid, - input wire [DDR_CH-1:0] m_axi_ddr_arready, - input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, - input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, - input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, - input wire [DDR_CH-1:0] m_axi_ddr_rlast, - input wire [DDR_CH-1:0] m_axi_ddr_rvalid, - output wire [DDR_CH-1:0] m_axi_ddr_rready, - - input wire [DDR_CH-1:0] ddr_status, - - /* - * QSPI flash - */ - output wire fpga_boot, - output wire qspi_clk, - input wire [3:0] qspi_dq_i, - output wire [3:0] qspi_dq_o, - output wire [3:0] qspi_dq_oe, - output wire qspi_cs -); - -parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; - -parameter F_COUNT = PF_COUNT+VF_COUNT; - -parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8); -parameter AXIL_IF_CTRL_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT); -parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8); - -localparam RB_BASE_ADDR = 16'h1000; -localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; - -localparam RB_DRP_QSFP0_BASE = RB_BASE_ADDR + 16'h40; -localparam RB_DRP_QSFP1_BASE = RB_DRP_QSFP0_BASE + 16'h20; - -initial begin - if (PORT_COUNT > 2) begin - $error("Error: Max port count exceeded (instance %m)"); - $finish; - end -end - -// PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; - -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse; - -// control registers -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_wr_addr; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_wr_data; -wire [AXIL_CTRL_STRB_WIDTH-1:0] ctrl_reg_wr_strb; -wire ctrl_reg_wr_en; -wire ctrl_reg_wr_wait; -wire ctrl_reg_wr_ack; -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_rd_addr; -wire ctrl_reg_rd_en; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data; -wire ctrl_reg_rd_wait; -wire ctrl_reg_rd_ack; - -wire qsfp0_drp_reg_wr_wait; -wire qsfp0_drp_reg_wr_ack; -wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp0_drp_reg_rd_data; -wire qsfp0_drp_reg_rd_wait; -wire qsfp0_drp_reg_rd_ack; - -wire qsfp1_drp_reg_wr_wait; -wire qsfp1_drp_reg_wr_ack; -wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp1_drp_reg_rd_data; -wire qsfp1_drp_reg_rd_wait; -wire qsfp1_drp_reg_rd_ack; - -reg ctrl_reg_wr_ack_reg = 1'b0; -reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; -reg ctrl_reg_rd_ack_reg = 1'b0; - -reg qsfp0_reset_reg = 1'b0; -reg qsfp1_reset_reg = 1'b0; - -reg qsfp0_lpmode_reg = 1'b0; -reg qsfp1_lpmode_reg = 1'b0; - -reg i2c_scl_o_reg = 1'b1; -reg i2c_sda_o_reg = 1'b1; - -reg fpga_boot_reg = 1'b0; - -reg qspi_clk_reg = 1'b0; -reg qspi_cs_reg = 1'b1; -reg [3:0] qspi_dq_o_reg = 4'd0; -reg [3:0] qspi_dq_oe_reg = 4'd0; - -assign ctrl_reg_wr_wait = qsfp0_drp_reg_wr_wait | qsfp1_drp_reg_wr_wait; -assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp0_drp_reg_wr_ack | qsfp1_drp_reg_wr_ack; -assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp0_drp_reg_rd_data | qsfp1_drp_reg_rd_data; -assign ctrl_reg_rd_wait = qsfp0_drp_reg_rd_wait | qsfp1_drp_reg_rd_wait; -assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp0_drp_reg_rd_ack | qsfp1_drp_reg_rd_ack; - -assign qsfp0_modsell = 1'b0; -assign qsfp1_modsell = 1'b0; - -assign qsfp0_resetl = !qsfp0_reset_reg; -assign qsfp1_resetl = !qsfp1_reset_reg; - -assign qsfp0_lpmode = qsfp0_lpmode_reg; -assign qsfp1_lpmode = qsfp1_lpmode_reg; - -assign i2c_scl_o = i2c_scl_o_reg; -assign i2c_scl_t = i2c_scl_o_reg; -assign i2c_sda_o = i2c_sda_o_reg; -assign i2c_sda_t = i2c_sda_o_reg; - -assign fpga_boot = fpga_boot_reg; - -assign qspi_clk = qspi_clk_reg; -assign qspi_cs = qspi_cs_reg; -assign qspi_dq_o = qspi_dq_o_reg; -assign qspi_dq_oe = qspi_dq_oe_reg; - -always @(posedge clk_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; - ctrl_reg_rd_ack_reg <= 1'b0; - - if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin - // write operation - ctrl_reg_wr_ack_reg <= 1'b0; - case ({ctrl_reg_wr_addr >> 2, 2'b00}) - // FW ID - 8'h0C: begin - // FW ID: FPGA JTAG ID - fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD; - end - // I2C 0 - RBB+8'h0C: begin - // I2C ctrl: control - if (ctrl_reg_wr_strb[0]) begin - i2c_scl_o_reg <= ctrl_reg_wr_data[1]; - end - if (ctrl_reg_wr_strb[1]) begin - i2c_sda_o_reg <= ctrl_reg_wr_data[9]; - end - end - // XCVR GPIO - RBB+8'h1C: begin - // XCVR GPIO: control 0123 - if (ctrl_reg_wr_strb[0]) begin - qsfp0_reset_reg <= ctrl_reg_wr_data[4]; - qsfp0_lpmode_reg <= ctrl_reg_wr_data[5]; - end - if (ctrl_reg_wr_strb[1]) begin - qsfp1_reset_reg <= ctrl_reg_wr_data[12]; - qsfp1_lpmode_reg <= ctrl_reg_wr_data[13]; - end - end - // QSPI flash - RBB+8'h2C: begin - // SPI flash ctrl: format - fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD; - end - RBB+8'h30: begin - // SPI flash ctrl: control 0 - if (ctrl_reg_wr_strb[0]) begin - qspi_dq_o_reg <= ctrl_reg_wr_data[3:0]; - end - if (ctrl_reg_wr_strb[1]) begin - qspi_dq_oe_reg <= ctrl_reg_wr_data[11:8]; - end - if (ctrl_reg_wr_strb[2]) begin - qspi_clk_reg <= ctrl_reg_wr_data[16]; - qspi_cs_reg <= ctrl_reg_wr_data[17]; - end - end - default: ctrl_reg_wr_ack_reg <= 1'b0; - endcase - end - - if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin - // read operation - ctrl_reg_rd_ack_reg <= 1'b1; - case ({ctrl_reg_rd_addr >> 2, 2'b00}) - // I2C 0 - RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type - RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version - RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // I2C ctrl: Next header - RBB+8'h0C: begin - // I2C ctrl: control - ctrl_reg_rd_data_reg[0] <= i2c_scl_i; - ctrl_reg_rd_data_reg[1] <= i2c_scl_o_reg; - ctrl_reg_rd_data_reg[8] <= i2c_sda_i; - ctrl_reg_rd_data_reg[9] <= i2c_sda_o_reg; - end - // XCVR GPIO - RBB+8'h10: ctrl_reg_rd_data_reg <= 32'h0000C101; // XCVR GPIO: Type - RBB+8'h14: ctrl_reg_rd_data_reg <= 32'h00000100; // XCVR GPIO: Version - RBB+8'h18: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // XCVR GPIO: Next header - RBB+8'h1C: begin - // XCVR GPIO: control 0123 - ctrl_reg_rd_data_reg[0] <= !qsfp0_modprsl; - ctrl_reg_rd_data_reg[1] <= !qsfp0_intl; - ctrl_reg_rd_data_reg[4] <= qsfp0_reset_reg; - ctrl_reg_rd_data_reg[5] <= qsfp0_lpmode_reg; - ctrl_reg_rd_data_reg[8] <= !qsfp1_modprsl; - ctrl_reg_rd_data_reg[9] <= !qsfp1_intl; - ctrl_reg_rd_data_reg[12] <= qsfp1_reset_reg; - ctrl_reg_rd_data_reg[13] <= qsfp1_lpmode_reg; - end - // QSPI flash - RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type - RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version - RBB+8'h28: ctrl_reg_rd_data_reg <= RB_DRP_QSFP0_BASE; // SPI flash ctrl: Next header - RBB+8'h2C: begin - // SPI flash ctrl: format - ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments) - ctrl_reg_rd_data_reg[7:4] <= 1; // default segment - ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment - ctrl_reg_rd_data_reg[31:12] <= 32'h00000000 >> 12; // first segment size (even split) - end - RBB+8'h30: begin - // SPI flash ctrl: control 0 - ctrl_reg_rd_data_reg[3:0] <= qspi_dq_i; - ctrl_reg_rd_data_reg[11:8] <= qspi_dq_oe; - ctrl_reg_rd_data_reg[16] <= qspi_clk; - ctrl_reg_rd_data_reg[17] <= qspi_cs; - end - default: ctrl_reg_rd_ack_reg <= 1'b0; - endcase - end - - if (rst_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_ack_reg <= 1'b0; - - qsfp0_reset_reg <= 1'b0; - qsfp1_reset_reg <= 1'b0; - - qsfp0_lpmode_reg <= 1'b0; - qsfp1_lpmode_reg <= 1'b0; - - i2c_scl_o_reg <= 1'b1; - i2c_sda_o_reg <= 1'b1; - - fpga_boot_reg <= 1'b0; - - qspi_clk_reg <= 1'b0; - qspi_cs_reg <= 1'b1; - qspi_dq_o_reg <= 4'd0; - qspi_dq_oe_reg <= 4'd0; - end -end - -rb_drp #( - .DRP_ADDR_WIDTH(24), - .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h09, 8'h03, 8'd2, 8'd4}), - .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .RB_BASE_ADDR(RB_DRP_QSFP0_BASE), - .RB_NEXT_PTR(RB_DRP_QSFP1_BASE) -) -qsfp0_rb_drp_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * Register interface - */ - .reg_wr_addr(ctrl_reg_wr_addr), - .reg_wr_data(ctrl_reg_wr_data), - .reg_wr_strb(ctrl_reg_wr_strb), - .reg_wr_en(ctrl_reg_wr_en), - .reg_wr_wait(qsfp0_drp_reg_wr_wait), - .reg_wr_ack(qsfp0_drp_reg_wr_ack), - .reg_rd_addr(ctrl_reg_rd_addr), - .reg_rd_en(ctrl_reg_rd_en), - .reg_rd_data(qsfp0_drp_reg_rd_data), - .reg_rd_wait(qsfp0_drp_reg_rd_wait), - .reg_rd_ack(qsfp0_drp_reg_rd_ack), - - /* - * DRP - */ - .drp_clk(qsfp0_drp_clk), - .drp_rst(qsfp0_drp_rst), - .drp_addr(qsfp0_drp_addr), - .drp_di(qsfp0_drp_di), - .drp_en(qsfp0_drp_en), - .drp_we(qsfp0_drp_we), - .drp_do(qsfp0_drp_do), - .drp_rdy(qsfp0_drp_rdy) -); - -rb_drp #( - .DRP_ADDR_WIDTH(24), - .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h09, 8'h03, 8'd2, 8'd4}), - .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .RB_BASE_ADDR(RB_DRP_QSFP1_BASE), - .RB_NEXT_PTR(0) -) -qsfp1_rb_drp_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * Register interface - */ - .reg_wr_addr(ctrl_reg_wr_addr), - .reg_wr_data(ctrl_reg_wr_data), - .reg_wr_strb(ctrl_reg_wr_strb), - .reg_wr_en(ctrl_reg_wr_en), - .reg_wr_wait(qsfp1_drp_reg_wr_wait), - .reg_wr_ack(qsfp1_drp_reg_wr_ack), - .reg_rd_addr(ctrl_reg_rd_addr), - .reg_rd_en(ctrl_reg_rd_en), - .reg_rd_data(qsfp1_drp_reg_rd_data), - .reg_rd_wait(qsfp1_drp_reg_rd_wait), - .reg_rd_ack(qsfp1_drp_reg_rd_ack), - - /* - * DRP - */ - .drp_clk(qsfp1_drp_clk), - .drp_rst(qsfp1_drp_rst), - .drp_addr(qsfp1_drp_addr), - .drp_di(qsfp1_drp_di), - .drp_en(qsfp1_drp_en), - .drp_we(qsfp1_drp_we), - .drp_do(qsfp1_drp_do), - .drp_rdy(qsfp1_drp_rdy) -); - -assign led[0] = ptp_pps_str; -assign led[2:1] = 0; - -wire [PORT_COUNT-1:0] eth_tx_clk; -wire [PORT_COUNT-1:0] eth_tx_rst; - -wire [PORT_COUNT-1:0] eth_tx_ptp_clk; -wire [PORT_COUNT-1:0] eth_tx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_tx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_tx_tready; -wire [PORT_COUNT-1:0] axis_eth_tx_tlast; -wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts; -wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; - -wire [PORT_COUNT-1:0] eth_tx_enable; -wire [PORT_COUNT-1:0] eth_tx_status; -wire [PORT_COUNT-1:0] eth_tx_lfc_en; -wire [PORT_COUNT-1:0] eth_tx_lfc_req; -wire [PORT_COUNT*8-1:0] eth_tx_pfc_en; -wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; - -wire [PORT_COUNT-1:0] eth_rx_clk; -wire [PORT_COUNT-1:0] eth_rx_rst; - -wire [PORT_COUNT-1:0] eth_rx_ptp_clk; -wire [PORT_COUNT-1:0] eth_rx_ptp_rst; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_rx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_rx_tready; -wire [PORT_COUNT-1:0] axis_eth_rx_tlast; -wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; - -wire [PORT_COUNT-1:0] eth_rx_enable; -wire [PORT_COUNT-1:0] eth_rx_status; -wire [PORT_COUNT-1:0] eth_rx_lfc_en; -wire [PORT_COUNT-1:0] eth_rx_lfc_req; -wire [PORT_COUNT-1:0] eth_rx_lfc_ack; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_en; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_req; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack; - -wire [PTP_TS_WIDTH-1:0] qsfp0_tx_ptp_time_int; -wire [PTP_TS_WIDTH-1:0] qsfp1_tx_ptp_time_int; -wire [PTP_TS_WIDTH-1:0] qsfp0_rx_ptp_time_int; -wire [PTP_TS_WIDTH-1:0] qsfp1_rx_ptp_time_int; - -assign qsfp0_tx_ptp_time = qsfp0_tx_ptp_time_int >> 16; -assign qsfp1_tx_ptp_time = qsfp1_tx_ptp_time_int >> 16; -assign qsfp0_rx_ptp_time = qsfp0_rx_ptp_time_int >> 16; -assign qsfp1_rx_ptp_time = qsfp1_rx_ptp_time_int >> 16; - -mqnic_port_map_mac_axis #( - .MAC_COUNT(2), - .PORT_MASK(PORT_MASK), - .PORT_GROUP_SIZE(1), - - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - - .PORT_COUNT(PORT_COUNT), - - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_TAG_WIDTH(TX_TAG_WIDTH), - .AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) -) -mqnic_port_map_mac_axis_inst ( - // towards MAC - .mac_tx_clk({qsfp1_tx_clk, qsfp0_tx_clk}), - .mac_tx_rst({qsfp1_tx_rst, qsfp0_tx_rst}), - - .mac_tx_ptp_clk(2'b00), - .mac_tx_ptp_rst(2'b00), - .mac_tx_ptp_ts_96({qsfp1_tx_ptp_time_int, qsfp0_tx_ptp_time_int}), - .mac_tx_ptp_ts_step(), - - .m_axis_mac_tx_tdata({qsfp1_tx_axis_tdata, qsfp0_tx_axis_tdata}), - .m_axis_mac_tx_tkeep({qsfp1_tx_axis_tkeep, qsfp0_tx_axis_tkeep}), - .m_axis_mac_tx_tvalid({qsfp1_tx_axis_tvalid, qsfp0_tx_axis_tvalid}), - .m_axis_mac_tx_tready({qsfp1_tx_axis_tready, qsfp0_tx_axis_tready}), - .m_axis_mac_tx_tlast({qsfp1_tx_axis_tlast, qsfp0_tx_axis_tlast}), - .m_axis_mac_tx_tuser({qsfp1_tx_axis_tuser, qsfp0_tx_axis_tuser}), - - .s_axis_mac_tx_ptp_ts({{qsfp1_tx_ptp_ts, 16'd0}, {qsfp0_tx_ptp_ts, 16'd0}}), - .s_axis_mac_tx_ptp_ts_tag({qsfp1_tx_ptp_ts_tag, qsfp0_tx_ptp_ts_tag}), - .s_axis_mac_tx_ptp_ts_valid({qsfp1_tx_ptp_ts_valid, qsfp0_tx_ptp_ts_valid}), - .s_axis_mac_tx_ptp_ts_ready(), - - .mac_tx_enable({qsfp1_tx_enable, qsfp0_tx_enable}), - .mac_tx_status(2'b11), - .mac_tx_lfc_en({qsfp1_tx_lfc_en, qsfp0_tx_lfc_en}), - .mac_tx_lfc_req({qsfp1_tx_lfc_req, qsfp0_tx_lfc_req}), - .mac_tx_pfc_en({qsfp1_tx_pfc_en, qsfp0_tx_pfc_en}), - .mac_tx_pfc_req({qsfp1_tx_pfc_req, qsfp0_tx_pfc_req}), - - .mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}), - .mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}), - - .mac_rx_ptp_clk({qsfp1_rx_ptp_clk, qsfp0_rx_ptp_clk}), - .mac_rx_ptp_rst({qsfp1_rx_ptp_rst, qsfp0_rx_ptp_rst}), - .mac_rx_ptp_ts_96({qsfp1_rx_ptp_time_int, qsfp0_rx_ptp_time_int}), - .mac_rx_ptp_ts_step(), - - .s_axis_mac_rx_tdata({qsfp1_rx_axis_tdata, qsfp0_rx_axis_tdata}), - .s_axis_mac_rx_tkeep({qsfp1_rx_axis_tkeep, qsfp0_rx_axis_tkeep}), - .s_axis_mac_rx_tvalid({qsfp1_rx_axis_tvalid, qsfp0_rx_axis_tvalid}), - .s_axis_mac_rx_tready(), - .s_axis_mac_rx_tlast({qsfp1_rx_axis_tlast, qsfp0_rx_axis_tlast}), - .s_axis_mac_rx_tuser({{qsfp1_rx_axis_tuser[80:1], 16'd0, qsfp1_rx_axis_tuser[0]}, {qsfp0_rx_axis_tuser[80:1], 16'd0, qsfp0_rx_axis_tuser[0]}}), - - .mac_rx_enable({qsfp1_rx_enable, qsfp0_rx_enable}), - .mac_rx_status({qsfp1_rx_status, qsfp0_rx_status}), - .mac_rx_lfc_en({qsfp1_rx_lfc_en, qsfp0_rx_lfc_en}), - .mac_rx_lfc_req({qsfp1_rx_lfc_req, qsfp0_rx_lfc_req}), - .mac_rx_lfc_ack({qsfp1_rx_lfc_ack, qsfp0_rx_lfc_ack}), - .mac_rx_pfc_en({qsfp1_rx_pfc_en, qsfp0_rx_pfc_en}), - .mac_rx_pfc_req({qsfp1_rx_pfc_req, qsfp0_rx_pfc_req}), - .mac_rx_pfc_ack({qsfp1_rx_pfc_ack, qsfp0_rx_pfc_ack}), - - // towards datapath - .tx_clk(eth_tx_clk), - .tx_rst(eth_tx_rst), - - .tx_ptp_clk(eth_tx_ptp_clk), - .tx_ptp_rst(eth_tx_ptp_rst), - .tx_ptp_ts_96(eth_tx_ptp_ts_96), - .tx_ptp_ts_step(eth_tx_ptp_ts_step), - - .s_axis_tx_tdata(axis_eth_tx_tdata), - .s_axis_tx_tkeep(axis_eth_tx_tkeep), - .s_axis_tx_tvalid(axis_eth_tx_tvalid), - .s_axis_tx_tready(axis_eth_tx_tready), - .s_axis_tx_tlast(axis_eth_tx_tlast), - .s_axis_tx_tuser(axis_eth_tx_tuser), - - .m_axis_tx_ptp_ts(axis_eth_tx_ptp_ts), - .m_axis_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag), - .m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid), - .m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready), - - .tx_enable(eth_tx_enable), - .tx_status(eth_tx_status), - .tx_lfc_en(eth_tx_lfc_en), - .tx_lfc_req(eth_tx_lfc_req), - .tx_pfc_en(eth_tx_pfc_en), - .tx_pfc_req(eth_tx_pfc_req), - - .rx_clk(eth_rx_clk), - .rx_rst(eth_rx_rst), - - .rx_ptp_clk(eth_rx_ptp_clk), - .rx_ptp_rst(eth_rx_ptp_rst), - .rx_ptp_ts_96(eth_rx_ptp_ts_96), - .rx_ptp_ts_step(eth_rx_ptp_ts_step), - - .m_axis_rx_tdata(axis_eth_rx_tdata), - .m_axis_rx_tkeep(axis_eth_rx_tkeep), - .m_axis_rx_tvalid(axis_eth_rx_tvalid), - .m_axis_rx_tready(axis_eth_rx_tready), - .m_axis_rx_tlast(axis_eth_rx_tlast), - .m_axis_rx_tuser(axis_eth_rx_tuser), - - .rx_enable(eth_rx_enable), - .rx_status(eth_rx_status), - .rx_lfc_en(eth_rx_lfc_en), - .rx_lfc_req(eth_rx_lfc_req), - .rx_lfc_ack(eth_rx_lfc_ack), - .rx_pfc_en(eth_rx_pfc_en), - .rx_pfc_req(eth_rx_pfc_req), - .rx_pfc_ack(eth_rx_pfc_ack) -); - -mqnic_core_pcie_us #( - // FW and board IDs - .FPGA_ID(FPGA_ID), - .FW_ID(FW_ID), - .FW_VER(FW_VER), - .BOARD_ID(BOARD_ID), - .BOARD_VER(BOARD_VER), - .BUILD_DATE(BUILD_DATE), - .GIT_HASH(GIT_HASH), - .RELEASE_INFO(RELEASE_INFO), - - // Structural configuration - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - .SCHED_PER_IF(SCHED_PER_IF), - - .PORT_COUNT(PORT_COUNT), - - // Clock configuration - .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), - .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), - - // PTP configuration - .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), - .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), - .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_TX_CLOCK(0), - .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK), - .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), - - // Queue manager configuration - .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), - .EQN_WIDTH(EQN_WIDTH), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .CQN_WIDTH(CQN_WIDTH), - .EQ_PIPELINE(EQ_PIPELINE), - .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), - .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .CQ_PIPELINE(CQ_PIPELINE), - - // TX and RX engine configuration - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), - - // Scheduler configuration - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - - // Interface configuration - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_CPL_ENABLE(PTP_TS_ENABLE), - .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), - .TX_TAG_WIDTH(TX_TAG_WIDTH), - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .PFC_ENABLE(PFC_ENABLE), - .LFC_ENABLE(LFC_ENABLE), - .MAC_CTRL_ENABLE(0), - .TX_FIFO_DEPTH(TX_FIFO_DEPTH), - .RX_FIFO_DEPTH(RX_FIFO_DEPTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - - // RAM configuration - .DDR_CH(DDR_CH), - .DDR_ENABLE(DDR_ENABLE), - .DDR_GROUP_SIZE(1), - .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), - .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), - .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), - .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), - .AXI_DDR_AWUSER_ENABLE(0), - .AXI_DDR_WUSER_ENABLE(0), - .AXI_DDR_BUSER_ENABLE(0), - .AXI_DDR_ARUSER_ENABLE(0), - .AXI_DDR_RUSER_ENABLE(0), - .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), - .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), - .AXI_DDR_FIXED_BURST(0), - .AXI_DDR_WRAP_BURST(1), - .HBM_ENABLE(0), - - // Application block configuration - .APP_ID(APP_ID), - .APP_ENABLE(APP_ENABLE), - .APP_CTRL_ENABLE(APP_CTRL_ENABLE), - .APP_DMA_ENABLE(APP_DMA_ENABLE), - .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), - .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), - .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), - .APP_STAT_ENABLE(APP_STAT_ENABLE), - .APP_GPIO_IN_WIDTH(32), - .APP_GPIO_OUT_WIDTH(32), - - // DMA interface configuration - .DMA_IMM_ENABLE(DMA_IMM_ENABLE), - .DMA_IMM_WIDTH(DMA_IMM_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - - // PCIe interface configuration - .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), - .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), - .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), - .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), - .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), - .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), - .RC_STRADDLE(RC_STRADDLE), - .RQ_STRADDLE(RQ_STRADDLE), - .CQ_STRADDLE(CQ_STRADDLE), - .CC_STRADDLE(CC_STRADDLE), - .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), - .PF_COUNT(PF_COUNT), - .VF_COUNT(VF_COUNT), - .F_COUNT(F_COUNT), - .PCIE_TAG_COUNT(PCIE_TAG_COUNT), - - // Interrupt configuration - .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), - - // AXI lite interface configuration (control) - .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), - .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(0), - .RB_NEXT_PTR(RB_BASE_ADDR), - - // AXI lite interface configuration (application control) - .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), - .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), - - // Ethernet interface configuration - .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), - .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .AXIS_ETH_RX_USE_READY(0), - .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), - .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), - .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), - .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), - .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), - - // Statistics counter subsystem - .STAT_ENABLE(STAT_ENABLE), - .STAT_DMA_ENABLE(STAT_DMA_ENABLE), - .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), - .STAT_INC_WIDTH(STAT_INC_WIDTH), - .STAT_ID_WIDTH(STAT_ID_WIDTH) -) -core_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * AXI input (RC) - */ - .s_axis_rc_tdata(s_axis_rc_tdata), - .s_axis_rc_tkeep(s_axis_rc_tkeep), - .s_axis_rc_tvalid(s_axis_rc_tvalid), - .s_axis_rc_tready(s_axis_rc_tready), - .s_axis_rc_tlast(s_axis_rc_tlast), - .s_axis_rc_tuser(s_axis_rc_tuser), - - /* - * AXI output (RQ) - */ - .m_axis_rq_tdata(m_axis_rq_tdata), - .m_axis_rq_tkeep(m_axis_rq_tkeep), - .m_axis_rq_tvalid(m_axis_rq_tvalid), - .m_axis_rq_tready(m_axis_rq_tready), - .m_axis_rq_tlast(m_axis_rq_tlast), - .m_axis_rq_tuser(m_axis_rq_tuser), - - /* - * AXI input (CQ) - */ - .s_axis_cq_tdata(s_axis_cq_tdata), - .s_axis_cq_tkeep(s_axis_cq_tkeep), - .s_axis_cq_tvalid(s_axis_cq_tvalid), - .s_axis_cq_tready(s_axis_cq_tready), - .s_axis_cq_tlast(s_axis_cq_tlast), - .s_axis_cq_tuser(s_axis_cq_tuser), - - /* - * AXI output (CC) - */ - .m_axis_cc_tdata(m_axis_cc_tdata), - .m_axis_cc_tkeep(m_axis_cc_tkeep), - .m_axis_cc_tvalid(m_axis_cc_tvalid), - .m_axis_cc_tready(m_axis_cc_tready), - .m_axis_cc_tlast(m_axis_cc_tlast), - .m_axis_cc_tuser(m_axis_cc_tuser), - - /* - * Transmit sequence number input - */ - .s_axis_rq_seq_num_0(s_axis_rq_seq_num_0), - .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), - .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), - .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), - - /* - * Flow control - */ - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - /* - * Configuration inputs - */ - .cfg_max_read_req(cfg_max_read_req), - .cfg_max_payload(cfg_max_payload), - .cfg_rcb_status(cfg_rcb_status), - - /* - * Configuration interface - */ - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - - /* - * Interrupt interface - */ - .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), - .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), - .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), - .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), - .cfg_interrupt_msix_address(cfg_interrupt_msix_address), - .cfg_interrupt_msix_data(cfg_interrupt_msix_data), - .cfg_interrupt_msix_int(cfg_interrupt_msix_int), - .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), - .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), - .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), - .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - /* - * PCIe error outputs - */ - .status_error_cor(status_error_cor), - .status_error_uncor(status_error_uncor), - - /* - * AXI-Lite master interface (passthrough for NIC control and status) - */ - .m_axil_csr_awaddr(), - .m_axil_csr_awprot(), - .m_axil_csr_awvalid(), - .m_axil_csr_awready(1), - .m_axil_csr_wdata(), - .m_axil_csr_wstrb(), - .m_axil_csr_wvalid(), - .m_axil_csr_wready(1), - .m_axil_csr_bresp(0), - .m_axil_csr_bvalid(0), - .m_axil_csr_bready(), - .m_axil_csr_araddr(), - .m_axil_csr_arprot(), - .m_axil_csr_arvalid(), - .m_axil_csr_arready(1), - .m_axil_csr_rdata(0), - .m_axil_csr_rresp(0), - .m_axil_csr_rvalid(0), - .m_axil_csr_rready(), - - /* - * Control register interface - */ - .ctrl_reg_wr_addr(ctrl_reg_wr_addr), - .ctrl_reg_wr_data(ctrl_reg_wr_data), - .ctrl_reg_wr_strb(ctrl_reg_wr_strb), - .ctrl_reg_wr_en(ctrl_reg_wr_en), - .ctrl_reg_wr_wait(ctrl_reg_wr_wait), - .ctrl_reg_wr_ack(ctrl_reg_wr_ack), - .ctrl_reg_rd_addr(ctrl_reg_rd_addr), - .ctrl_reg_rd_en(ctrl_reg_rd_en), - .ctrl_reg_rd_data(ctrl_reg_rd_data), - .ctrl_reg_rd_wait(ctrl_reg_rd_wait), - .ctrl_reg_rd_ack(ctrl_reg_rd_ack), - - /* - * PTP clock - */ - .ptp_clk(ptp_clk), - .ptp_rst(ptp_rst), - .ptp_sample_clk(ptp_sample_clk), - .ptp_pps(ptp_pps), - .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), - .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), - .ptp_perout_locked(ptp_perout_locked), - .ptp_perout_error(ptp_perout_error), - .ptp_perout_pulse(ptp_perout_pulse), - - /* - * Ethernet - */ - .eth_tx_clk(eth_tx_clk), - .eth_tx_rst(eth_tx_rst), - - .eth_tx_ptp_clk(eth_tx_ptp_clk), - .eth_tx_ptp_rst(eth_tx_ptp_rst), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), - - .m_axis_eth_tx_tdata(axis_eth_tx_tdata), - .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), - .m_axis_eth_tx_tvalid(axis_eth_tx_tvalid), - .m_axis_eth_tx_tready(axis_eth_tx_tready), - .m_axis_eth_tx_tlast(axis_eth_tx_tlast), - .m_axis_eth_tx_tuser(axis_eth_tx_tuser), - - .s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts), - .s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag), - .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), - .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), - - .eth_tx_enable(eth_tx_enable), - .eth_tx_status(eth_tx_status), - .eth_tx_lfc_en(eth_tx_lfc_en), - .eth_tx_lfc_req(eth_tx_lfc_req), - .eth_tx_pfc_en(eth_tx_pfc_en), - .eth_tx_pfc_req(eth_tx_pfc_req), - .eth_tx_fc_quanta_clk_en(0), - - .eth_rx_clk(eth_rx_clk), - .eth_rx_rst(eth_rx_rst), - - .eth_rx_ptp_clk(eth_rx_ptp_clk), - .eth_rx_ptp_rst(eth_rx_ptp_rst), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), - - .s_axis_eth_rx_tdata(axis_eth_rx_tdata), - .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), - .s_axis_eth_rx_tvalid(axis_eth_rx_tvalid), - .s_axis_eth_rx_tready(axis_eth_rx_tready), - .s_axis_eth_rx_tlast(axis_eth_rx_tlast), - .s_axis_eth_rx_tuser(axis_eth_rx_tuser), - - .eth_rx_enable(eth_rx_enable), - .eth_rx_status(eth_rx_status), - .eth_rx_lfc_en(eth_rx_lfc_en), - .eth_rx_lfc_req(eth_rx_lfc_req), - .eth_rx_lfc_ack(eth_rx_lfc_ack), - .eth_rx_pfc_en(eth_rx_pfc_en), - .eth_rx_pfc_req(eth_rx_pfc_req), - .eth_rx_pfc_ack(eth_rx_pfc_ack), - .eth_rx_fc_quanta_clk_en(0), - - /* - * DDR - */ - .ddr_clk(ddr_clk), - .ddr_rst(ddr_rst), - - .m_axi_ddr_awid(m_axi_ddr_awid), - .m_axi_ddr_awaddr(m_axi_ddr_awaddr), - .m_axi_ddr_awlen(m_axi_ddr_awlen), - .m_axi_ddr_awsize(m_axi_ddr_awsize), - .m_axi_ddr_awburst(m_axi_ddr_awburst), - .m_axi_ddr_awlock(m_axi_ddr_awlock), - .m_axi_ddr_awcache(m_axi_ddr_awcache), - .m_axi_ddr_awprot(m_axi_ddr_awprot), - .m_axi_ddr_awqos(m_axi_ddr_awqos), - .m_axi_ddr_awuser(), - .m_axi_ddr_awvalid(m_axi_ddr_awvalid), - .m_axi_ddr_awready(m_axi_ddr_awready), - .m_axi_ddr_wdata(m_axi_ddr_wdata), - .m_axi_ddr_wstrb(m_axi_ddr_wstrb), - .m_axi_ddr_wlast(m_axi_ddr_wlast), - .m_axi_ddr_wuser(), - .m_axi_ddr_wvalid(m_axi_ddr_wvalid), - .m_axi_ddr_wready(m_axi_ddr_wready), - .m_axi_ddr_bid(m_axi_ddr_bid), - .m_axi_ddr_bresp(m_axi_ddr_bresp), - .m_axi_ddr_buser(0), - .m_axi_ddr_bvalid(m_axi_ddr_bvalid), - .m_axi_ddr_bready(m_axi_ddr_bready), - .m_axi_ddr_arid(m_axi_ddr_arid), - .m_axi_ddr_araddr(m_axi_ddr_araddr), - .m_axi_ddr_arlen(m_axi_ddr_arlen), - .m_axi_ddr_arsize(m_axi_ddr_arsize), - .m_axi_ddr_arburst(m_axi_ddr_arburst), - .m_axi_ddr_arlock(m_axi_ddr_arlock), - .m_axi_ddr_arcache(m_axi_ddr_arcache), - .m_axi_ddr_arprot(m_axi_ddr_arprot), - .m_axi_ddr_arqos(m_axi_ddr_arqos), - .m_axi_ddr_aruser(), - .m_axi_ddr_arvalid(m_axi_ddr_arvalid), - .m_axi_ddr_arready(m_axi_ddr_arready), - .m_axi_ddr_rid(m_axi_ddr_rid), - .m_axi_ddr_rdata(m_axi_ddr_rdata), - .m_axi_ddr_rresp(m_axi_ddr_rresp), - .m_axi_ddr_rlast(m_axi_ddr_rlast), - .m_axi_ddr_ruser(0), - .m_axi_ddr_rvalid(m_axi_ddr_rvalid), - .m_axi_ddr_rready(m_axi_ddr_rready), - - .ddr_status(ddr_status), - - /* - * HBM - */ - .hbm_clk(0), - .hbm_rst(0), - - .m_axi_hbm_awid(), - .m_axi_hbm_awaddr(), - .m_axi_hbm_awlen(), - .m_axi_hbm_awsize(), - .m_axi_hbm_awburst(), - .m_axi_hbm_awlock(), - .m_axi_hbm_awcache(), - .m_axi_hbm_awprot(), - .m_axi_hbm_awqos(), - .m_axi_hbm_awuser(), - .m_axi_hbm_awvalid(), - .m_axi_hbm_awready(0), - .m_axi_hbm_wdata(), - .m_axi_hbm_wstrb(), - .m_axi_hbm_wlast(), - .m_axi_hbm_wuser(), - .m_axi_hbm_wvalid(), - .m_axi_hbm_wready(0), - .m_axi_hbm_bid(0), - .m_axi_hbm_bresp(0), - .m_axi_hbm_buser(0), - .m_axi_hbm_bvalid(0), - .m_axi_hbm_bready(), - .m_axi_hbm_arid(), - .m_axi_hbm_araddr(), - .m_axi_hbm_arlen(), - .m_axi_hbm_arsize(), - .m_axi_hbm_arburst(), - .m_axi_hbm_arlock(), - .m_axi_hbm_arcache(), - .m_axi_hbm_arprot(), - .m_axi_hbm_arqos(), - .m_axi_hbm_aruser(), - .m_axi_hbm_arvalid(), - .m_axi_hbm_arready(0), - .m_axi_hbm_rid(0), - .m_axi_hbm_rdata(0), - .m_axi_hbm_rresp(0), - .m_axi_hbm_rlast(0), - .m_axi_hbm_ruser(0), - .m_axi_hbm_rvalid(0), - .m_axi_hbm_rready(), - - .hbm_status(0), - - /* - * Statistics input - */ - .s_axis_stat_tdata(0), - .s_axis_stat_tid(0), - .s_axis_stat_tvalid(1'b0), - .s_axis_stat_tready(), - - /* - * GPIO - */ - .app_gpio_in(0), - .app_gpio_out(), - - /* - * JTAG - */ - .app_jtag_tdi(1'b0), - .app_jtag_tdo(), - .app_jtag_tms(1'b0), - .app_jtag_tck(1'b0) -); - -endmodule - -`resetall diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/sync_signal.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/sync_signal.v deleted file mode 100644 index 74b855fa1..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/sync_signal.v +++ /dev/null @@ -1,62 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog-2001 - -`resetall -`timescale 1 ns / 1 ps -`default_nettype none - -/* - * Synchronizes an asyncronous signal to a given clock by using a pipeline of - * two registers. - */ -module sync_signal #( - parameter WIDTH=1, // width of the input and output signals - parameter N=2 // depth of synchronizer -)( - input wire clk, - input wire [WIDTH-1:0] in, - output wire [WIDTH-1:0] out -); - -reg [WIDTH-1:0] sync_reg[N-1:0]; - -/* - * The synchronized output is the last register in the pipeline. - */ -assign out = sync_reg[N-1]; - -integer k; - -always @(posedge clk) begin - sync_reg[0] <= in; - for (k = 1; k < N; k = k + 1) begin - sync_reg[k] <= sync_reg[k-1]; - end -end - -endmodule - -`resetall diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile deleted file mode 100644 index 6b3457a52..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile +++ /dev/null @@ -1,251 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2020-2023 The Regents of the University of California - -TOPLEVEL_LANG = verilog - -SIM ?= icarus -WAVES ?= 0 - -COCOTB_HDL_TIMEUNIT = 1ns -COCOTB_HDL_TIMEPRECISION = 1ps - -DUT = fpga_core -TOPLEVEL = $(DUT) -MODULE = test_$(DUT) -VERILOG_SOURCES += ../../rtl/$(DUT).v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core.v -VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v -VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v -VERILOG_SOURCES += ../../rtl/common/cpl_write.v -VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v -VERILOG_SOURCES += ../../rtl/common/desc_fetch.v -VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/queue_manager.v -VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v -VERILOG_SOURCES += ../../rtl/common/tx_fifo.v -VERILOG_SOURCES += ../../rtl/common/rx_fifo.v -VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v -VERILOG_SOURCES += ../../rtl/common/tx_engine.v -VERILOG_SOURCES += ../../rtl/common/rx_engine.v -VERILOG_SOURCES += ../../rtl/common/tx_checksum.v -VERILOG_SOURCES += ../../rtl/common/rx_hash.v -VERILOG_SOURCES += ../../rtl/common/rx_checksum.v -VERILOG_SOURCES += ../../rtl/common/rb_drp.v -VERILOG_SOURCES += ../../rtl/common/stats_counter.v -VERILOG_SOURCES += ../../rtl/common/stats_collect.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v -VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v -VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v -VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v -VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v - -# module parameters - -# Structural configuration -export PARAM_IF_COUNT := 2 -export PARAM_PORTS_PER_IF := 1 -export PARAM_SCHED_PER_IF := $(PARAM_PORTS_PER_IF) -export PARAM_PORT_MASK := 0 - -# Clock configuration -export PARAM_CLK_PERIOD_NS_NUM := 4 -export PARAM_CLK_PERIOD_NS_DENOM := 1 - -# PTP configuration -export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 -export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 -export PARAM_PTP_CLOCK_PIPELINE := 0 -export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_SEPARATE_RX_CLOCK := 0 -export PARAM_PTP_PORT_CDC_PIPELINE := 0 -export PARAM_PTP_PEROUT_ENABLE := 0 -export PARAM_PTP_PEROUT_COUNT := 1 - -# Queue manager configuration -export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_CQ_OP_TABLE_SIZE := 32 -export PARAM_EQN_WIDTH := 6 -export PARAM_TX_QUEUE_INDEX_WIDTH := 13 -export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") -export PARAM_EQ_PIPELINE := 3 -export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") - -# TX and RX engine configuration -export PARAM_TX_DESC_TABLE_SIZE := 32 -export PARAM_RX_DESC_TABLE_SIZE := 32 -export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") - -# Scheduler configuration -export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) -export PARAM_TX_SCHEDULER_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_TDMA_INDEX_WIDTH := 6 - -# Interface configuration -export PARAM_PTP_TS_ENABLE := 1 -export PARAM_TX_CPL_FIFO_DEPTH := 32 -export PARAM_TX_CHECKSUM_ENABLE := 1 -export PARAM_RX_HASH_ENABLE := 1 -export PARAM_RX_CHECKSUM_ENABLE := 1 -export PARAM_LFC_ENABLE := 1 -export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) -export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 131072 -export PARAM_MAX_TX_SIZE := 9214 -export PARAM_MAX_RX_SIZE := 9214 -export PARAM_TX_RAM_SIZE := 131072 -export PARAM_RX_RAM_SIZE := 131072 - -# Application block configuration -export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) -export PARAM_APP_ENABLE := 0 -export PARAM_APP_CTRL_ENABLE := 1 -export PARAM_APP_DMA_ENABLE := 1 -export PARAM_APP_AXIS_DIRECT_ENABLE := 1 -export PARAM_APP_AXIS_SYNC_ENABLE := 1 -export PARAM_APP_AXIS_IF_ENABLE := 1 -export PARAM_APP_STAT_ENABLE := 1 - -# DMA interface configuration -export PARAM_DMA_IMM_ENABLE := 0 -export PARAM_DMA_IMM_WIDTH := 32 -export PARAM_DMA_LEN_WIDTH := 16 -export PARAM_DMA_TAG_WIDTH := 16 -export PARAM_RAM_ADDR_WIDTH := $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())") -export PARAM_RAM_PIPELINE := 2 - -# PCIe interface configuration -export PARAM_AXIS_PCIE_DATA_WIDTH := 512 -export PARAM_PF_COUNT := 1 -export PARAM_VF_COUNT := 0 - -# Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) - -# AXI lite interface configuration (control) -export PARAM_AXIL_CTRL_DATA_WIDTH := 32 -export PARAM_AXIL_CTRL_ADDR_WIDTH := 24 - -# AXI lite interface configuration (application control) -export PARAM_AXIL_APP_CTRL_DATA_WIDTH := $(PARAM_AXIL_CTRL_DATA_WIDTH) -export PARAM_AXIL_APP_CTRL_ADDR_WIDTH := 24 - -# Ethernet interface configuration -export PARAM_AXIS_ETH_TX_PIPELINE := 4 -export PARAM_AXIS_ETH_TX_FIFO_PIPELINE := 4 -export PARAM_AXIS_ETH_TX_TS_PIPELINE := 4 -export PARAM_AXIS_ETH_RX_PIPELINE := 4 -export PARAM_AXIS_ETH_RX_FIFO_PIPELINE := 4 - -# Statistics counter subsystem -export PARAM_STAT_ENABLE := 1 -export PARAM_STAT_DMA_ENABLE := 1 -export PARAM_STAT_PCIE_ENABLE := 1 -export PARAM_STAT_INC_WIDTH := 24 -export PARAM_STAT_ID_WIDTH := 12 - -ifeq ($(SIM), icarus) - PLUSARGS += -fst - - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif -else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - COMPILE_ARGS += --trace-fst - endif -endif - -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/mqnic.py b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/mqnic.py deleted file mode 120000 index dfa8522e7..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/mqnic.py +++ /dev/null @@ -1 +0,0 @@ -../../../../../common/tb/mqnic.py \ No newline at end of file diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py deleted file mode 100644 index 5940a33d8..000000000 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py +++ /dev/null @@ -1,795 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2020-2023 The Regents of the University of California - -import logging -import os -import sys - -import scapy.utils -from scapy.layers.l2 import Ether -from scapy.layers.inet import IP, UDP - -import cocotb_test.simulator - -import cocotb -from cocotb.log import SimLog -from cocotb.clock import Clock -from cocotb.triggers import RisingEdge, FallingEdge, Timer - -from cocotbext.axi import AxiStreamBus -from cocotbext.eth import EthMac -from cocotbext.pcie.core import RootComplex -from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice - -try: - import mqnic -except ImportError: - # attempt import from current directory - sys.path.insert(0, os.path.join(os.path.dirname(__file__))) - try: - import mqnic - finally: - del sys.path[0] - - -class TB(object): - def __init__(self, dut, msix_count=32): - self.dut = dut - - self.log = SimLog("cocotb.tb") - self.log.setLevel(logging.DEBUG) - - # PCIe - self.rc = RootComplex() - - self.rc.max_payload_size = 0x1 # 256 bytes - self.rc.max_read_request_size = 0x2 # 512 bytes - - self.dev = UltraScalePlusPcieDevice( - # configuration options - pcie_generation=3, - pcie_link_width=16, - user_clk_frequency=250e6, - alignment="dword", - cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1, - cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1, - rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1, - rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1, - rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2, - pf_count=1, - max_payload_size=1024, - enable_client_tag=True, - enable_extended_tag=True, - enable_parity=False, - enable_rx_msg_interface=False, - enable_sriov=False, - enable_extended_configuration=False, - - pf0_msi_enable=False, - pf0_msi_count=32, - pf1_msi_enable=False, - pf1_msi_count=1, - pf2_msi_enable=False, - pf2_msi_count=1, - pf3_msi_enable=False, - pf3_msi_count=1, - pf0_msix_enable=True, - pf0_msix_table_size=msix_count-1, - pf0_msix_table_bir=0, - pf0_msix_table_offset=0x00010000, - pf0_msix_pba_bir=0, - pf0_msix_pba_offset=0x00018000, - pf1_msix_enable=False, - pf1_msix_table_size=0, - pf1_msix_table_bir=0, - pf1_msix_table_offset=0x00000000, - pf1_msix_pba_bir=0, - pf1_msix_pba_offset=0x00000000, - pf2_msix_enable=False, - pf2_msix_table_size=0, - pf2_msix_table_bir=0, - pf2_msix_table_offset=0x00000000, - pf2_msix_pba_bir=0, - pf2_msix_pba_offset=0x00000000, - pf3_msix_enable=False, - pf3_msix_table_size=0, - pf3_msix_table_bir=0, - pf3_msix_table_offset=0x00000000, - pf3_msix_pba_bir=0, - pf3_msix_pba_offset=0x00000000, - - # signals - # Clock and Reset Interface - user_clk=dut.clk_250mhz, - user_reset=dut.rst_250mhz, - # user_lnk_up - # sys_clk - # sys_clk_gt - # sys_reset - # phy_rdy_out - - # Requester reQuest Interface - rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), - pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, - pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, - pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, - pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, - # pcie_rq_tag0 - # pcie_rq_tag1 - # pcie_rq_tag_av - # pcie_rq_tag_vld0 - # pcie_rq_tag_vld1 - - # Requester Completion Interface - rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), - - # Completer reQuest Interface - cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), - # pcie_cq_np_req - # pcie_cq_np_req_count - - # Completer Completion Interface - cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), - - # Transmit Flow Control Interface - # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, - # pcie_tfc_npd_av=dut.pcie_tfc_npd_av, - - # Configuration Management Interface - cfg_mgmt_addr=dut.cfg_mgmt_addr, - cfg_mgmt_function_number=dut.cfg_mgmt_function_number, - cfg_mgmt_write=dut.cfg_mgmt_write, - cfg_mgmt_write_data=dut.cfg_mgmt_write_data, - cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable, - cfg_mgmt_read=dut.cfg_mgmt_read, - cfg_mgmt_read_data=dut.cfg_mgmt_read_data, - cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done, - # cfg_mgmt_debug_access - - # Configuration Status Interface - # cfg_phy_link_down - # cfg_phy_link_status - # cfg_negotiated_width - # cfg_current_speed - cfg_max_payload=dut.cfg_max_payload, - cfg_max_read_req=dut.cfg_max_read_req, - # cfg_function_status - # cfg_vf_status - # cfg_function_power_state - # cfg_vf_power_state - # cfg_link_power_state - # cfg_err_cor_out - # cfg_err_nonfatal_out - # cfg_err_fatal_out - # cfg_local_error_out - # cfg_local_error_valid - # cfg_rx_pm_state - # cfg_tx_pm_state - # cfg_ltssm_state - cfg_rcb_status=dut.cfg_rcb_status, - # cfg_obff_enable - # cfg_pl_status_change - # cfg_tph_requester_enable - # cfg_tph_st_mode - # cfg_vf_tph_requester_enable - # cfg_vf_tph_st_mode - - # Configuration Received Message Interface - # cfg_msg_received - # cfg_msg_received_data - # cfg_msg_received_type - - # Configuration Transmit Message Interface - # cfg_msg_transmit - # cfg_msg_transmit_type - # cfg_msg_transmit_data - # cfg_msg_transmit_done - - # Configuration Flow Control Interface - cfg_fc_ph=dut.cfg_fc_ph, - cfg_fc_pd=dut.cfg_fc_pd, - cfg_fc_nph=dut.cfg_fc_nph, - cfg_fc_npd=dut.cfg_fc_npd, - cfg_fc_cplh=dut.cfg_fc_cplh, - cfg_fc_cpld=dut.cfg_fc_cpld, - cfg_fc_sel=dut.cfg_fc_sel, - - # Configuration Control Interface - # cfg_hot_reset_in - # cfg_hot_reset_out - # cfg_config_space_enable - # cfg_dsn - # cfg_bus_number - # cfg_ds_port_number - # cfg_ds_bus_number - # cfg_ds_device_number - # cfg_ds_function_number - # cfg_power_state_change_ack - # cfg_power_state_change_interrupt - cfg_err_cor_in=dut.status_error_cor, - cfg_err_uncor_in=dut.status_error_uncor, - # cfg_flr_in_process - # cfg_flr_done - # cfg_vf_flr_in_process - # cfg_vf_flr_func_num - # cfg_vf_flr_done - # cfg_pm_aspm_l1_entry_reject - # cfg_pm_aspm_tx_l0s_entry_disable - # cfg_req_pm_transition_l23_ready - # cfg_link_training_enable - - # Configuration Interrupt Controller Interface - # cfg_interrupt_int - # cfg_interrupt_sent - # cfg_interrupt_pending - # cfg_interrupt_msi_enable - # cfg_interrupt_msi_mmenable - # cfg_interrupt_msi_mask_update - # cfg_interrupt_msi_data - # cfg_interrupt_msi_select - # cfg_interrupt_msi_int - # cfg_interrupt_msi_pending_status - # cfg_interrupt_msi_pending_status_data_enable - # cfg_interrupt_msi_pending_status_function_num - # cfg_interrupt_msi_sent - # cfg_interrupt_msi_fail - cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable, - cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask, - cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable, - cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask, - cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address, - cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data, - cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int, - cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending, - cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status, - cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent, - cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail, - # cfg_interrupt_msi_attr - # cfg_interrupt_msi_tph_present - # cfg_interrupt_msi_tph_type - # cfg_interrupt_msi_tph_st_tag - cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, - - # Configuration Extend Interface - # cfg_ext_read_received - # cfg_ext_write_received - # cfg_ext_register_number - # cfg_ext_function_number - # cfg_ext_write_data - # cfg_ext_write_byte_enable - # cfg_ext_read_data - # cfg_ext_read_data_valid - ) - - # self.dev.log.setLevel(logging.DEBUG) - - self.rc.make_port().connect(self.dev) - - self.driver = mqnic.Driver() - - self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) - if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): - self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) - - cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start()) - dut.ptp_rst.setimmediatevalue(0) - cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start()) - - # Ethernet - self.qsfp_mac = [] - - for k in range(2): - cocotb.start_soon(Clock(getattr(dut, f"qsfp{k}_rx_clk"), 3.102, units="ns").start()) - cocotb.start_soon(Clock(getattr(dut, f"qsfp{k}_tx_clk"), 3.102, units="ns").start()) - - mac = EthMac( - tx_clk=getattr(dut, f"qsfp{k}_tx_clk"), - tx_rst=getattr(dut, f"qsfp{k}_tx_rst"), - tx_bus=AxiStreamBus.from_prefix(dut, f"qsfp{k}_tx_axis"), - tx_ptp_time=getattr(dut, f"qsfp{k}_tx_ptp_time"), - tx_ptp_ts=getattr(dut, f"qsfp{k}_tx_ptp_ts"), - tx_ptp_ts_tag=getattr(dut, f"qsfp{k}_tx_ptp_ts_tag"), - tx_ptp_ts_valid=getattr(dut, f"qsfp{k}_tx_ptp_ts_valid"), - rx_clk=getattr(dut, f"qsfp{k}_rx_clk"), - rx_rst=getattr(dut, f"qsfp{k}_rx_rst"), - rx_bus=AxiStreamBus.from_prefix(dut, f"qsfp{k}_rx_axis"), - rx_ptp_time=getattr(dut, f"qsfp{k}_rx_ptp_time"), - ifg=12, speed=100e9 - ) - - self.qsfp_mac.append(mac) - - getattr(dut, f"qsfp{k}_rx_status").setimmediatevalue(1) - getattr(dut, f"qsfp{k}_rx_lfc_req").setimmediatevalue(0) - getattr(dut, f"qsfp{k}_rx_pfc_req").setimmediatevalue(0) - - cocotb.start_soon(Clock(getattr(dut, f"qsfp{k}_drp_clk"), 8, units="ns").start()) - getattr(dut, f"qsfp{k}_drp_rst").setimmediatevalue(0) - getattr(dut, f"qsfp{k}_drp_do").setimmediatevalue(0) - getattr(dut, f"qsfp{k}_drp_rdy").setimmediatevalue(0) - - getattr(dut, f"qsfp{k}_modprsl").setimmediatevalue(0) - getattr(dut, f"qsfp{k}_intl").setimmediatevalue(1) - - dut.sw.setimmediatevalue(0) - - dut.i2c_scl_i.setimmediatevalue(1) - dut.i2c_sda_i.setimmediatevalue(1) - - dut.qspi_dq_i.setimmediatevalue(0) - - self.loopback_enable = False - cocotb.start_soon(self._run_loopback()) - - async def init(self): - - self.dut.ptp_rst.setimmediatevalue(0) - for k in range(2): - getattr(self.dut, f"qsfp{k}_rx_rst").setimmediatevalue(0) - getattr(self.dut, f"qsfp{k}_tx_rst").setimmediatevalue(0) - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.ptp_rst.setimmediatevalue(1) - for k in range(2): - getattr(self.dut, f"qsfp{k}_rx_rst").setimmediatevalue(1) - getattr(self.dut, f"qsfp{k}_tx_rst").setimmediatevalue(1) - - await FallingEdge(self.dut.rst_250mhz) - await Timer(100, 'ns') - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.ptp_rst.setimmediatevalue(0) - for k in range(2): - getattr(self.dut, f"qsfp{k}_rx_rst").setimmediatevalue(0) - getattr(self.dut, f"qsfp{k}_tx_rst").setimmediatevalue(0) - - await self.rc.enumerate() - - async def _run_loopback(self): - while True: - await RisingEdge(self.dut.clk_250mhz) - - if self.loopback_enable: - for mac in self.qsfp_mac: - if not mac.tx.empty(): - await mac.rx.send(await mac.tx.recv()) - - -@cocotb.test() -async def run_test_nic(dut): - - tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index)) - - await tb.init() - - tb.log.info("Init driver") - await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id)) - await tb.driver.interfaces[0].open() - # await tb.driver.interfaces[1].open() - - # enable queues - tb.log.info("Enable queues") - await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) - for k in range(len(tb.driver.interfaces[0].txq)): - await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003) - - # wait for all writes to complete - await tb.driver.hw_regs.read_dword(0) - tb.log.info("Init complete") - - tb.log.info("Send and receive single packet") - - data = bytearray([x % 256 for x in range(1024)]) - - await tb.driver.interfaces[0].start_xmit(data, 0) - - pkt = await tb.qsfp_mac[0].tx.recv() - tb.log.info("Packet: %s", pkt) - - await tb.qsfp_mac[0].rx.send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - # await tb.driver.interfaces[1].start_xmit(data, 0) - - # pkt = await tb.qsfp_mac[1].tx.recv() - # tb.log.info("Packet: %s", pkt) - - # await tb.qsfp_mac[1].rx.send(pkt) - - # pkt = await tb.driver.interfaces[1].recv() - - # tb.log.info("Packet: %s", pkt) - # assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.log.info("RX and TX checksum tests") - - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') - ip = IP(src='192.168.1.100', dst='192.168.1.101') - udp = UDP(sport=1, dport=2) - test_pkt = eth / ip / udp / payload - - test_pkt2 = test_pkt.copy() - test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) - - await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - - pkt = await tb.qsfp_mac[0].tx.recv() - tb.log.info("Packet: %s", pkt) - - await tb.qsfp_mac[0].rx.send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - assert Ether(pkt.data).build() == test_pkt.build() - - tb.log.info("Queue mapping offset test") - - data = bytearray([x % 256 for x in range(1024)]) - - tb.loopback_enable = True - - for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) - - await tb.driver.interfaces[0].start_xmit(data, 0) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - assert pkt.queue == k - - tb.loopback_enable = False - - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) - - tb.log.info("Queue mapping RSS mask test") - - await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) - - for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) - - tb.loopback_enable = True - - queues = set() - - for k in range(64): - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') - ip = IP(src='192.168.1.100', dst='192.168.1.101') - udp = UDP(sport=1, dport=k+0) - test_pkt = eth / ip / udp / payload - - test_pkt2 = test_pkt.copy() - test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) - - await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - - for k in range(64): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - queues.add(pkt.queue) - - assert len(queues) == 4 - - tb.loopback_enable = False - - await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0) - - tb.log.info("Multiple small packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - tb.log.info("Multiple large packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - tb.log.info("Jumbo frames") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(9014)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - await RisingEdge(dut.clk_250mhz) - await RisingEdge(dut.clk_250mhz) - - -# cocotb-test - -tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) -app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app')) -axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl')) -axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) -eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) -pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl')) - - -def test_fpga_core(request): - dut = "fpga_core" - module = os.path.splitext(os.path.basename(__file__))[0] - toplevel = dut - - verilog_sources = [ - os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), - os.path.join(rtl_dir, "common", "mqnic_core.v"), - os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), - os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), - os.path.join(rtl_dir, "common", "mqnic_port_tx.v"), - os.path.join(rtl_dir, "common", "mqnic_port_rx.v"), - os.path.join(rtl_dir, "common", "mqnic_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), - os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), - os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"), - os.path.join(rtl_dir, "common", "cpl_write.v"), - os.path.join(rtl_dir, "common", "cpl_op_mux.v"), - os.path.join(rtl_dir, "common", "desc_fetch.v"), - os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "queue_manager.v"), - os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), - os.path.join(rtl_dir, "common", "tx_fifo.v"), - os.path.join(rtl_dir, "common", "rx_fifo.v"), - os.path.join(rtl_dir, "common", "tx_req_mux.v"), - os.path.join(rtl_dir, "common", "tx_engine.v"), - os.path.join(rtl_dir, "common", "rx_engine.v"), - os.path.join(rtl_dir, "common", "tx_checksum.v"), - os.path.join(rtl_dir, "common", "rx_hash.v"), - os.path.join(rtl_dir, "common", "rx_checksum.v"), - os.path.join(rtl_dir, "common", "rb_drp.v"), - os.path.join(rtl_dir, "common", "stats_counter.v"), - os.path.join(rtl_dir, "common", "stats_collect.v"), - os.path.join(rtl_dir, "common", "stats_pcie_if.v"), - os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"), - os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"), - os.path.join(rtl_dir, "common", "stats_dma_latency.v"), - os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), - os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), - os.path.join(eth_rtl_dir, "ptp_perout.v"), - os.path.join(axi_rtl_dir, "axil_interconnect.v"), - os.path.join(axi_rtl_dir, "axil_crossbar.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"), - os.path.join(axi_rtl_dir, "axil_reg_if.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"), - os.path.join(axi_rtl_dir, "axil_register_rd.v"), - os.path.join(axi_rtl_dir, "axil_register_wr.v"), - os.path.join(axi_rtl_dir, "arbiter.v"), - os.path.join(axi_rtl_dir, "priority_encoder.v"), - os.path.join(axis_rtl_dir, "axis_adapter.v"), - os.path.join(axis_rtl_dir, "axis_arb_mux.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_demux.v"), - os.path.join(axis_rtl_dir, "axis_fifo.v"), - os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), - os.path.join(axis_rtl_dir, "axis_register.v"), - os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), - os.path.join(pcie_rtl_dir, "pcie_msix.v"), - os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_psdpram.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), - os.path.join(pcie_rtl_dir, "pulse_merge.v"), - ] - - parameters = {} - - # Structural configuration - parameters['IF_COUNT'] = 2 - parameters['PORTS_PER_IF'] = 1 - parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] - parameters['PORT_MASK'] = 0 - - # Clock configuration - parameters['CLK_PERIOD_NS_NUM'] = 4 - parameters['CLK_PERIOD_NS_DENOM'] = 1 - - # PTP configuration - parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 - parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 - parameters['PTP_CLOCK_PIPELINE'] = 0 - parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_SEPARATE_RX_CLOCK'] = 0 - parameters['PTP_PORT_CDC_PIPELINE'] = 0 - parameters['PTP_PEROUT_ENABLE'] = 0 - parameters['PTP_PEROUT_COUNT'] = 1 - - # Queue manager configuration - parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['CQ_OP_TABLE_SIZE'] = 32 - parameters['EQN_WIDTH'] = 6 - parameters['TX_QUEUE_INDEX_WIDTH'] = 13 - parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 - parameters['EQ_PIPELINE'] = 3 - parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) - - # TX and RX engine configuration - parameters['TX_DESC_TABLE_SIZE'] = 32 - parameters['RX_DESC_TABLE_SIZE'] = 32 - parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) - - # Scheduler configuration - parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] - parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['TDMA_INDEX_WIDTH'] = 6 - - # Interface configuration - parameters['PTP_TS_ENABLE'] = 1 - parameters['TX_CPL_FIFO_DEPTH'] = 32 - parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_HASH_ENABLE'] = 1 - parameters['RX_CHECKSUM_ENABLE'] = 1 - parameters['LFC_ENABLE'] = 1 - parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] - parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 131072 - parameters['MAX_TX_SIZE'] = 9214 - parameters['MAX_RX_SIZE'] = 9214 - parameters['TX_RAM_SIZE'] = 131072 - parameters['RX_RAM_SIZE'] = 131072 - - # Application block configuration - parameters['APP_ID'] = 0x00000000 - parameters['APP_ENABLE'] = 0 - parameters['APP_CTRL_ENABLE'] = 1 - parameters['APP_DMA_ENABLE'] = 1 - parameters['APP_AXIS_DIRECT_ENABLE'] = 1 - parameters['APP_AXIS_SYNC_ENABLE'] = 1 - parameters['APP_AXIS_IF_ENABLE'] = 1 - parameters['APP_STAT_ENABLE'] = 1 - - # DMA interface configuration - parameters['DMA_IMM_ENABLE'] = 0 - parameters['DMA_IMM_WIDTH'] = 32 - parameters['DMA_LEN_WIDTH'] = 16 - parameters['DMA_TAG_WIDTH'] = 16 - parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length() - parameters['RAM_PIPELINE'] = 2 - - # PCIe interface configuration - parameters['AXIS_PCIE_DATA_WIDTH'] = 512 - parameters['PF_COUNT'] = 1 - parameters['VF_COUNT'] = 0 - - # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] - - # AXI lite interface configuration (control) - parameters['AXIL_CTRL_DATA_WIDTH'] = 32 - parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 - - # AXI lite interface configuration (application control) - parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH'] - parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24 - - # Ethernet interface configuration - parameters['AXIS_ETH_TX_PIPELINE'] = 4 - parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 4 - parameters['AXIS_ETH_TX_TS_PIPELINE'] = 4 - parameters['AXIS_ETH_RX_PIPELINE'] = 4 - parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 4 - - # Statistics counter subsystem - parameters['STAT_ENABLE'] = 1 - parameters['STAT_DMA_ENABLE'] = 1 - parameters['STAT_PCIE_ENABLE'] = 1 - parameters['STAT_INC_WIDTH'] = 24 - parameters['STAT_ID_WIDTH'] = 12 - - extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} - - sim_build = os.path.join(tests_dir, "sim_build", - request.node.name.replace('[', '-').replace(']', '')) - - cocotb_test.simulator.run( - python_search=[tests_dir], - verilog_sources=verilog_sources, - toplevel=toplevel, - module=module, - parameters=parameters, - sim_build=sim_build, - extra_env=extra_env, - ) diff --git a/fpga/mqnic/VCU1525/fpga_25g/Makefile b/fpga/mqnic/VCU1525/fpga_25g/Makefile deleted file mode 100644 index f504bd06f..000000000 --- a/fpga/mqnic/VCU1525/fpga_25g/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# Targets -TARGETS:= - -# Subdirectories -SUBDIRS = fpga -SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) - -# Rules -.PHONY: all -all: $(SUBDIRS) $(TARGETS) - -.PHONY: $(SUBDIRS) -$(SUBDIRS): - cd $@ && $(MAKE) - -.PHONY: $(SUBDIRS_CLEAN) -$(SUBDIRS_CLEAN): - cd $(@:.clean=) && $(MAKE) clean - -.PHONY: clean -clean: $(SUBDIRS_CLEAN) - -rm -rf $(TARGETS) - -program: - #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit diff --git a/fpga/mqnic/VCU1525/fpga_25g/README.md b/fpga/mqnic/VCU1525/fpga_25g/README.md deleted file mode 100644 index c32b84259..000000000 --- a/fpga/mqnic/VCU1525/fpga_25g/README.md +++ /dev/null @@ -1,23 +0,0 @@ -# Corundum mqnic for VCU1525 - -## Introduction - -This design targets the Xilinx VCU1525 FPGA board. - -* FPGA: xcvu9p-fsgd2104-2L-e -* PHY: 10G BASE-R PHY IP core and internal GTY transceiver -* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM) - -## Quick start - -### Build FPGA bitstream - -Run `make` in the `fpga` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. - -### Build driver and userspace tools - -On the host system, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run `make` in `utils` to build the userspace tools. - -### Testing - -Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization, and run `mqnic-dump -d /dev/mqnic0` to dump the internal state. diff --git a/fpga/mqnic/VCU1525/fpga_25g/app b/fpga/mqnic/VCU1525/fpga_25g/app deleted file mode 120000 index 4d46690fb..000000000 --- a/fpga/mqnic/VCU1525/fpga_25g/app +++ /dev/null @@ -1 +0,0 @@ -../../../app/ \ No newline at end of file diff --git a/fpga/mqnic/VCU1525/fpga_25g/boot.xdc b/fpga/mqnic/VCU1525/fpga_25g/boot.xdc deleted file mode 100644 index 5fb323e94..000000000 --- a/fpga/mqnic/VCU1525/fpga_25g/boot.xdc +++ /dev/null @@ -1,4 +0,0 @@ -# Timing constraints for FPGA boot logic - -set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"] -set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"] diff --git a/fpga/mqnic/VCU1525/fpga_25g/cfgmclk.xdc b/fpga/mqnic/VCU1525/fpga_25g/cfgmclk.xdc deleted file mode 100644 index 51f8c2ab1..000000000 --- a/fpga/mqnic/VCU1525/fpga_25g/cfgmclk.xdc +++ /dev/null @@ -1,4 +0,0 @@ -# Timing constraints for cfgmclk - -# Fcfgmclk is 50 MHz +/- 15%, rounding to 15 ns period -create_clock -period 15 -name cfgmclk [get_pins startupe3_inst/CFGMCLK] diff --git a/fpga/mqnic/VCU1525/fpga_25g/common/vivado.mk b/fpga/mqnic/VCU1525/fpga_25g/common/vivado.mk deleted file mode 100644 index 1402e2382..000000000 --- a/fpga/mqnic/VCU1525/fpga_25g/common/vivado.mk +++ /dev/null @@ -1,137 +0,0 @@ -################################################################### -# -# Xilinx Vivado FPGA Makefile -# -# Copyright (c) 2016 Alex Forencich -# -################################################################### -# -# Parameters: -# FPGA_TOP - Top module name -# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) -# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) -# SYN_FILES - space-separated list of source files -# INC_FILES - space-separated list of include files -# XDC_FILES - space-separated list of timing constraint files -# XCI_FILES - space-separated list of IP XCI files -# -# Example: -# -# FPGA_TOP = fpga -# FPGA_FAMILY = VirtexUltrascale -# FPGA_DEVICE = xcvu095-ffva2104-2-e -# SYN_FILES = rtl/fpga.v -# XDC_FILES = fpga.xdc -# XCI_FILES = ip/pcspma.xci -# include ../common/vivado.mk -# -################################################################### - -# phony targets -.PHONY: fpga vivado tmpclean clean distclean - -# prevent make from deleting intermediate files and reports -.PRECIOUS: %.xpr %.bit %.mcs %.prm -.SECONDARY: - -CONFIG ?= config.mk --include ../$(CONFIG) - -FPGA_TOP ?= fpga -PROJECT ?= $(FPGA_TOP) - -SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) - -ifdef XDC_FILES - XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -else - XDC_FILES_REL = $(PROJECT).xdc -endif - -################################################################### -# Main Targets -# -# all: build everything -# clean: remove output files and project files -################################################################### - -all: fpga - -fpga: $(PROJECT).bit - -vivado: $(PROJECT).xpr - vivado $(PROJECT).xpr - -tmpclean:: - -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl - -clean:: tmpclean - -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl - -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt - -distclean:: clean - -rm -rf rev - -################################################################### -# Target implementations -################################################################### - -# Vivado project file -create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) - rm -rf defines.v - touch defines.v - for x in $(DEFS); do echo '`define' $$x >> defines.v; done - echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ - echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ - echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ - echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ - for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done - for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) - echo "open_project -quiet $(PROJECT).xpr" > $@ - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -$(PROJECT).xpr: create_project.tcl update_config.tcl - vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) - -# synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr - echo "open_project $(PROJECT).xpr" > run_synth.tcl - echo "reset_run synth_1" >> run_synth.tcl - echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl - echo "wait_on_run synth_1" >> run_synth.tcl - vivado -nojournal -nolog -mode batch -source run_synth.tcl - -# implementation run -$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp - echo "open_project $(PROJECT).xpr" > run_impl.tcl - echo "reset_run impl_1" >> run_impl.tcl - echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl - echo "wait_on_run impl_1" >> run_impl.tcl - echo "open_run impl_1" >> run_impl.tcl - echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl - echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl - vivado -nojournal -nolog -mode batch -source run_impl.tcl - -# bit file -$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp - echo "open_project $(PROJECT).xpr" > generate_bit.tcl - echo "open_run impl_1" >> generate_bit.tcl - echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl - echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl - vivado -nojournal -nolog -mode batch -source generate_bit.tcl - ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi - mkdir -p rev - COUNT=100; \ - while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ - do COUNT=$$((COUNT+1)); done; \ - cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga.xdc b/fpga/mqnic/VCU1525/fpga_25g/fpga.xdc deleted file mode 100644 index d53a1f3e6..000000000 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga.xdc +++ /dev/null @@ -1,833 +0,0 @@ -# XDC constraints for the Xilinx VCU1525 board -# part: xcvu9p-fsgd2104-2L-e - -# General configuration -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design] -set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] -set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] -set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] -set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] - -# System clocks -# 300 MHz (DDR 0) -set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] -set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] -#create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p] - -# 300 MHz (DDR 1) -set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] -set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] -#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] - -# 300 MHz (DDR 2) -set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] -set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] -#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] - -# 300 MHz (DDR 3) -set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] -set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] -#create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p] - -# SI570 user clock -#set_property -dict {LOC AU19 IOSTANDARD LVDS} [get_ports clk_user_p] -#set_property -dict {LOC AV19 IOSTANDARD LVDS} [get_ports clk_user_n] -#create_clock -period 6.400 -name clk_user [get_ports clk_user_p] - -# LEDs -set_property -dict {LOC BC21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] -set_property -dict {LOC BB21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] -set_property -dict {LOC BA20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}] - -set_false_path -to [get_ports {led[*]}] -set_output_delay 0 [get_ports {led[*]}] - -# Reset button -#set_property -dict {LOC AL20 IOSTANDARD LVCMOS12} [get_ports reset] - -#set_false_path -from [get_ports {reset}] -#set_input_delay 0 [get_ports {reset}] - -# DIP switches -set_property -dict {LOC AN22 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] -set_property -dict {LOC AM19 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] -set_property -dict {LOC AL19 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] -set_property -dict {LOC AP20 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] - -set_false_path -from [get_ports {sw[*]}] -set_input_delay 0 [get_ports {sw[*]}] - -# UART -#set_property -dict {LOC BF18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd] -#set_property -dict {LOC BB20 IOSTANDARD LVCMOS12} [get_ports uart_rxd] - -#set_false_path -to [get_ports {uart_txd}] -#set_output_delay 0 [get_ports {uart_txd}] -#set_false_path -from [get_ports {uart_rxd}] -#set_input_delay 0 [get_ports {uart_rxd}] - -# QSFP28 Interfaces -set_property -dict {LOC N4 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC N3 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC N9 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC N8 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M2 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M1 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M7 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M6 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L4 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L3 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L9 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC L8 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K2 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K1 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K7 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC K6 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13 -#set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14 -set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18 -set_property -dict {LOC K10 } [get_ports qsfp0_mgt_refclk_1_n] ;# MGTREFCLK1N_231 from U9.17 -set_property -dict {LOC BE16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_modsell] -set_property -dict {LOC BE17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl] -set_property -dict {LOC BE20 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_modprsl] -set_property -dict {LOC BE21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_intl] -set_property -dict {LOC BD18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode] -set_property -dict {LOC AT22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_refclk_reset] -set_property -dict {LOC AT20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[0]}] -set_property -dict {LOC AU22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[1]}] - -# 156.25 MHz MGT reference clock (from SI570) -#create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports qsfp0_mgt_refclk_0_p] - -# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) -#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] - -# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) -create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p] - -set_false_path -to [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] -set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}] -set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}] -set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}] - -set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC U9 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC U8 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T2 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T1 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R4 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R3 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R9 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC R8 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P2 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P1 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 -#set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15 -#set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16 -set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18 -set_property -dict {LOC P10 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U12.17 -set_property -dict {LOC AY20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_modsell] -set_property -dict {LOC BC18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl] -set_property -dict {LOC BC19 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_modprsl] -set_property -dict {LOC AV21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_intl] -set_property -dict {LOC AV22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode] -set_property -dict {LOC AR21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_refclk_reset] -set_property -dict {LOC AR22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[0]}] -set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[1]}] - -# 156.25 MHz MGT reference clock (from SI570) -#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p] - -# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) -#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] - -# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) -create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] - -set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] -set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] -set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] -set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] - -# I2C interface -#set_property -dict {LOC BF19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset] -set_property -dict {LOC BF20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_scl] -set_property -dict {LOC BF17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_sda] - -set_false_path -to [get_ports {i2c_sda i2c_scl}] -set_output_delay 0 [get_ports {i2c_sda i2c_scl}] -set_false_path -from [get_ports {i2c_sda i2c_scl}] -set_input_delay 0 [get_ports {i2c_sda i2c_scl}] - -# PCIe Interface -set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AG9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AG8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AJ9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AJ8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AL4 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AL3 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AL9 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AL8 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AN4 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AN3 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AN9 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AN8 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AR4 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AR3 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AR9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AR8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AU4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AU3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AU9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AU8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AV7 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AV6 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AW4 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AW3 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BB5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BB4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BD5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BD4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BF5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC BF4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -set_property -dict {LOC AM11 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_226 -set_property -dict {LOC AM10 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_226 -set_property -dict {LOC BD21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n] - -# 100 MHz MGT reference clock -create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p] - -set_false_path -from [get_ports {pcie_reset_n}] -set_input_delay 0 [get_ports {pcie_reset_n}] - -# DDR4 C0 -set_property -dict {LOC AT36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] -set_property -dict {LOC AV36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] -set_property -dict {LOC AV37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] -set_property -dict {LOC AW35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] -set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] -set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] -set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] -set_property -dict {LOC BA40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] -set_property -dict {LOC BA37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] -set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] -set_property -dict {LOC AR35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] -set_property -dict {LOC BA39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] -set_property -dict {LOC BB40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] -set_property -dict {LOC AN36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] -set_property -dict {LOC AP35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] -set_property -dict {LOC AP36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] -set_property -dict {LOC AR36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] -set_property -dict {LOC AT35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] -set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] -set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] -set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] -set_property -dict {LOC AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[0]}] -set_property -dict {LOC AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[0]}] -#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[1]}] -#set_property -dict {LOC AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[1]}] -set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}] -#set_property -dict {LOC BC40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}] -set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}] -#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}] -#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}] -#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}] -set_property -dict {LOC BB39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] -set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}] -#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}] -set_property -dict {LOC AU36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] -set_property -dict {LOC AU31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] - -set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] -set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] -set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] -set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] -set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] -set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] -set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] -set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] -set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] -set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] -set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] -set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] -set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] -set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] -set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] -set_property -dict {LOC BF29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] -set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] -set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] -set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] -set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] -set_property -dict {LOC BC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] -set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] -set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] -set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] -set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] -set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] -set_property -dict {LOC AV34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] -set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] -set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] -set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] -set_property -dict {LOC BA35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] -set_property -dict {LOC BA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] -set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] -set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] -set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] -set_property -dict {LOC AT32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] -set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] -set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] -set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] -set_property -dict {LOC AR31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] -set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] -set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] -set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] -set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] -set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] -set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] -set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] -set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] -set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] -set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] -set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] -set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] -set_property -dict {LOC AV29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] -set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] -set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] -set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] -set_property -dict {LOC BD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] -set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] -set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] -set_property -dict {LOC BD35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] -set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] -set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] -set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] -set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] -set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] -set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] -set_property -dict {LOC BF43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] -set_property -dict {LOC BF42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] -set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] -set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] -set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] -set_property -dict {LOC BF41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] -set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] -set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] -set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] -set_property -dict {LOC BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] -set_property -dict {LOC BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] -set_property -dict {LOC BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] -set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] -set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] -set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] -set_property -dict {LOC BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] -set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] -set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] -set_property -dict {LOC AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] -set_property -dict {LOC AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] -set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] -set_property -dict {LOC BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] -set_property -dict {LOC AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] -set_property -dict {LOC AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] -set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}] -set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}] -set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}] -set_property -dict {LOC AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}] -set_property -dict {LOC AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}] -set_property -dict {LOC AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}] -set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}] -set_property -dict {LOC AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}] -set_property -dict {LOC AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}] -set_property -dict {LOC AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}] -set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}] -set_property -dict {LOC BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}] -set_property -dict {LOC BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}] -set_property -dict {LOC BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}] -set_property -dict {LOC BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}] -set_property -dict {LOC BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}] -set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}] -set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}] - -# DDR4 C1 -set_property -dict {LOC AN24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] -set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] -set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] -set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] -set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] -set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] -set_property -dict {LOC AV24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] -set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] -set_property -dict {LOC AY25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] -set_property -dict {LOC BA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] -set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] -set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] -set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] -set_property -dict {LOC AL24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] -set_property -dict {LOC AL25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] -set_property -dict {LOC AM25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] -set_property -dict {LOC AN23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] -set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] -set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] -set_property -dict {LOC BC22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] -set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] -set_property -dict {LOC AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[0]}] -set_property -dict {LOC AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[0]}] -#set_property -dict {LOC AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[1]}] -#set_property -dict {LOC AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[1]}] -set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}] -#set_property -dict {LOC BB24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}] -set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}] -#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}] -#set_property -dict {LOC AR23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}] -#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}] -set_property -dict {LOC AW25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] -set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}] -#set_property -dict {LOC AP24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}] -set_property -dict {LOC AT23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] -set_property -dict {LOC AR17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] - -set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] -set_property -dict {LOC BD7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] -set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] -set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] -set_property -dict {LOC BD10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] -set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] -set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] -set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] -set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] -set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] -set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] -set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] -set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] -set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] -set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] -set_property -dict {LOC BA11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] -set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] -set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] -set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] -set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] -set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] -set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] -set_property -dict {LOC BA7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] -set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] -set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] -set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] -set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] -set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] -set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] -set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] -set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] -set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] -set_property -dict {LOC BE13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] -set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] -set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] -set_property -dict {LOC BD13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] -set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] -set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] -set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] -set_property -dict {LOC BF13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] -set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] -set_property -dict {LOC BA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] -set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] -set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] -set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] -set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] -set_property -dict {LOC BC11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] -set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] -set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] -set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] -set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] -set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] -set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] -set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] -set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] -set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] -set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] -set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] -set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] -set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] -set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] -set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] -set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] -set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] -set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] -set_property -dict {LOC BF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] -set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] -set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] -set_property -dict {LOC BD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] -set_property -dict {LOC BC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] -set_property -dict {LOC BF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] -set_property -dict {LOC BE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] -set_property -dict {LOC BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] -set_property -dict {LOC BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] -set_property -dict {LOC BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] -set_property -dict {LOC BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] -set_property -dict {LOC AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] -set_property -dict {LOC AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] -set_property -dict {LOC AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] -set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] -set_property -dict {LOC BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] -set_property -dict {LOC BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] -set_property -dict {LOC BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] -set_property -dict {LOC BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] -set_property -dict {LOC AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] -set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] -set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] -set_property -dict {LOC AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] -set_property -dict {LOC BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] -set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] -set_property -dict {LOC BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] -set_property -dict {LOC BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] -set_property -dict {LOC BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}] -set_property -dict {LOC BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}] -set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}] -set_property -dict {LOC BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}] -set_property -dict {LOC AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}] -set_property -dict {LOC AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}] -set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}] -set_property -dict {LOC AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}] -set_property -dict {LOC AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}] -set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}] -set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}] -set_property -dict {LOC AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}] -set_property -dict {LOC BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}] -set_property -dict {LOC BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}] -set_property -dict {LOC BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}] -set_property -dict {LOC BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}] - -# DDR4 C2 -set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] -set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] -set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] -set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] -set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] -set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] -set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] -set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] -set_property -dict {LOC A32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] -set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] -set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] -set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] -set_property -dict {LOC M30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] -set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] -set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] -set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] -set_property -dict {LOC K30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] -set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] -set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] -set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] -set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}] -set_property -dict {LOC C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[0]}] -set_property -dict {LOC B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[0]}] -#set_property -dict {LOC D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[1]}] -#set_property -dict {LOC D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[1]}] -set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}] -#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}] -set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}] -#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}] -#set_property -dict {LOC L30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}] -#set_property -dict {LOC K31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}] -set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] -set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}] -#set_property -dict {LOC F34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}] -set_property -dict {LOC M29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] -set_property -dict {LOC D36 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] - -set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] -set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] -set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] -set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] -set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] -set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] -set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] -set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] -set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] -set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] -set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] -set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] -set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] -set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] -set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] -set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] -set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] -set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] -set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] -set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] -set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] -set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] -set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] -set_property -dict {LOC F29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] -set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] -set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] -set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] -set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] -set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] -set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] -set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] -set_property -dict {LOC C28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] -set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] -set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] -set_property -dict {LOC D38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] -set_property -dict {LOC E35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] -set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] -set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] -set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] -set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] -set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] -set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] -set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] -set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] -set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] -set_property -dict {LOC M32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] -set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] -set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] -set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] -set_property -dict {LOC K35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] -set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] -set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] -set_property -dict {LOC J34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] -set_property -dict {LOC J33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] -set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] -set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] -set_property -dict {LOC H36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] -set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] -set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] -set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] -set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] -set_property -dict {LOC K38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] -set_property -dict {LOC G35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] -set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] -set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] -set_property -dict {LOC B37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] -set_property -dict {LOC A37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] -set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] -set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] -set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] -set_property -dict {LOC A40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] -set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] -set_property -dict {LOC N26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] -set_property -dict {LOC M26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] -set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] -set_property -dict {LOC P28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] -set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] -set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] -set_property -dict {LOC M27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] -set_property -dict {LOC L28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] -set_property -dict {LOC D29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] -set_property -dict {LOC D30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] -set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] -set_property -dict {LOC H27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] -set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] -set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] -set_property -dict {LOC C29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] -set_property -dict {LOC B29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] -set_property -dict {LOC E39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] -set_property -dict {LOC E40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] -set_property -dict {LOC G37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] -set_property -dict {LOC F37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] -set_property -dict {LOC N31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}] -set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}] -set_property -dict {LOC T30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}] -set_property -dict {LOC R31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}] -set_property -dict {LOC L35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}] -set_property -dict {LOC L36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}] -set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}] -set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}] -set_property -dict {LOC J38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}] -set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}] -set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}] -set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}] -set_property -dict {LOC B39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}] -set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}] -set_property -dict {LOC C37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}] -set_property -dict {LOC C38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}] - -# DDR4 C3 -set_property -dict {LOC K15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}] -set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}] -set_property -dict {LOC F14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}] -set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}] -set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}] -set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}] -set_property -dict {LOC B14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}] -set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}] -set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}] -set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}] -set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}] -set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}] -set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}] -set_property -dict {LOC K16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}] -set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}] -set_property -dict {LOC E15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}] -set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}] -set_property -dict {LOC J15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}] -set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}] -set_property -dict {LOC D13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}] -set_property -dict {LOC J13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}] -set_property -dict {LOC L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[0]}] -set_property -dict {LOC L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[0]}] -#set_property -dict {LOC G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[1]}] -#set_property -dict {LOC G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[1]}] -set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}] -#set_property -dict {LOC L15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}] -set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}] -#set_property -dict {LOC D16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}] -#set_property -dict {LOC M14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}] -#set_property -dict {LOC M13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}] -set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}] -set_property -dict {LOC C16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}] -#set_property -dict {LOC E16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}] -set_property -dict {LOC J14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}] -set_property -dict {LOC D21 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}] - -set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}] -set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}] -set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}] -set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}] -set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}] -set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}] -set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}] -set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}] -set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}] -set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}] -set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}] -set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}] -set_property -dict {LOC L24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}] -set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}] -set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}] -set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}] -set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}] -set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}] -set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}] -set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}] -set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}] -set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}] -set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}] -set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}] -set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}] -set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}] -set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}] -set_property -dict {LOC R17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}] -set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}] -set_property -dict {LOC T20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}] -set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}] -set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}] -set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}] -set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}] -set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}] -set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}] -set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}] -set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}] -set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}] -set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}] -set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}] -set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}] -set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}] -set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}] -set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}] -set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}] -set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}] -set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}] -set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}] -set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}] -set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}] -set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}] -set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}] -set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}] -set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}] -set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}] -set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}] -set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}] -set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}] -set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}] -set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}] -set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}] -set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}] -set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}] -set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}] -set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}] -set_property -dict {LOC N13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}] -set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}] -set_property -dict {LOC T15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}] -set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}] -set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}] -set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}] -set_property -dict {LOC T22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}] -set_property -dict {LOC R22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}] -set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}] -set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}] -set_property -dict {LOC J21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}] -set_property -dict {LOC H21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}] -set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}] -set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}] -set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}] -set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}] -set_property -dict {LOC K18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}] -set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}] -set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}] -set_property -dict {LOC P18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}] -set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}] -set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}] -set_property -dict {LOC A25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}] -set_property -dict {LOC A24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}] -set_property -dict {LOC D24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}] -set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}] -set_property -dict {LOC C17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}] -set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}] -set_property -dict {LOC B19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}] -set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}] -set_property -dict {LOC F18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}] -set_property -dict {LOC F17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}] -set_property -dict {LOC H19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}] -set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}] -set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}] -set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}] -set_property -dict {LOC H23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}] -set_property -dict {LOC H22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}] -set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}] -set_property -dict {LOC P15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}] -set_property -dict {LOC T13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}] -set_property -dict {LOC R13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}] diff --git a/fpga/mqnic/VCU1525/fpga_25g/ip/ddr4_0.tcl b/fpga/mqnic/VCU1525/fpga_25g/ip/ddr4_0.tcl deleted file mode 100644 index 27252f502..000000000 --- a/fpga/mqnic/VCU1525/fpga_25g/ip/ddr4_0.tcl +++ /dev/null @@ -1,17 +0,0 @@ - -create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 - -set_property -dict [list \ - CONFIG.C0.DDR4_AxiSelection {true} \ - CONFIG.C0.DDR4_AxiDataWidth {512} \ - CONFIG.C0.DDR4_AxiIDWidth {8} \ - CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ - CONFIG.C0.DDR4_TimePeriod {833} \ - CONFIG.C0.DDR4_InputClockPeriod {3332} \ - CONFIG.C0.DDR4_MemoryType {RDIMMs} \ - CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ - CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ - CONFIG.C0.DDR4_CasLatency {17} \ - CONFIG.C0.DDR4_CasWriteLatency {12} \ - CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} -] [get_ips ddr4_0] diff --git a/fpga/mqnic/VCU1525/fpga_25g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/VCU1525/fpga_25g/ip/eth_xcvr_gty.tcl deleted file mode 100644 index e1dda063f..000000000 --- a/fpga/mqnic/VCU1525/fpga_25g/ip/eth_xcvr_gty.tcl +++ /dev/null @@ -1,103 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2022-2023 The Regents of the University of California - -set base_name {eth_xcvr_gty} - -set preset {GTY-10GBASE-R} - -set freerun_freq {125} -set line_rate {25.78125} -set sec_line_rate {10.3125} -set refclk_freq {161.1328125} -set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set user_data_width {64} -set int_data_width $user_data_width -set rx_eq_mode {DFE} -set extra_ports [list] -set extra_pll_ports [list] -# DRP connections -lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out -lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out -# PLL reset and power down -lappend extra_pll_ports qpll0reset_in qpll1reset_in -lappend extra_pll_ports qpll0pd_in qpll1pd_in -# PLL clocking -lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out -lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out -# channel reset -lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out -lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out -# channel power down -lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in -# channel clock selection -lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in -# channel polarity -lappend extra_ports txpolarity_in rxpolarity_in -# channel TX driver -lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in -# channel CDR -lappend extra_ports rxcdrlock_out rxcdrhold_in -# channel EQ -lappend extra_ports rxlpmen_in -# channel digital monitor -lappend extra_ports dmonitorout_out -# channel PRBS -lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out -# channel eye scan -lappend extra_ports eyescandataerror_out -# channel loopback -lappend extra_ports loopback_in - -set config [dict create] - -dict set config TX_LINE_RATE $line_rate -dict set config TX_REFCLK_FREQUENCY $refclk_freq -dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config TX_USER_DATA_WIDTH $user_data_width -dict set config TX_INT_DATA_WIDTH $int_data_width -dict set config RX_LINE_RATE $line_rate -dict set config RX_REFCLK_FREQUENCY $refclk_freq -dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config RX_USER_DATA_WIDTH $user_data_width -dict set config RX_INT_DATA_WIDTH $int_data_width -dict set config RX_EQ_MODE $rx_eq_mode -if {$sec_line_rate != 0} { - dict set config SECONDARY_QPLL_ENABLE true - dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn - dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate - dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq -} else { - dict set config SECONDARY_QPLL_ENABLE false -} -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} -dict set config LOCATE_TX_USER_CLOCKING {CORE} -dict set config LOCATE_RX_USER_CLOCKING {CORE} -dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} -dict set config FREERUN_FREQUENCY $freerun_freq -dict set config DISABLE_LOC_XDC {1} - -proc create_gtwizard_ip {name preset config} { - create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name - set ip [get_ips $name] - set_property CONFIG.preset $preset $ip - set config_list {} - dict for {name value} $config { - lappend config_list "CONFIG.${name}" $value - } - set_property -dict $config_list $ip -} - -# variant with channel and common -dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports] -dict set config LOCATE_COMMON {CORE} - -create_gtwizard_ip "${base_name}_full" $preset $config - -# variant with channel only -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {EXAMPLE_DESIGN} - -create_gtwizard_ip "${base_name}_channel" $preset $config diff --git a/fpga/mqnic/VCU1525/fpga_25g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/VCU1525/fpga_25g/ip/pcie4_uscale_plus_0.tcl deleted file mode 100644 index 12f4ce18d..000000000 --- a/fpga/mqnic/VCU1525/fpga_25g/ip/pcie4_uscale_plus_0.tcl +++ /dev/null @@ -1,34 +0,0 @@ - -create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 - -set_property -dict [list \ - CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ - CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ - CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \ - CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \ - CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \ - CONFIG.axisten_if_enable_client_tag {true} \ - CONFIG.axisten_if_width {512_bit} \ - CONFIG.extended_tag_field {true} \ - CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ - CONFIG.axisten_freq {250} \ - CONFIG.PF0_Use_Class_Code_Lookup_Assistant {false} \ - CONFIG.PF0_CLASS_CODE {020000} \ - CONFIG.PF0_DEVICE_ID {1001} \ - CONFIG.PF0_SUBSYSTEM_ID {95f5} \ - CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ - CONFIG.pf0_bar0_64bit {true} \ - CONFIG.pf0_bar0_prefetchable {true} \ - CONFIG.pf0_bar0_scale {Megabytes} \ - CONFIG.pf0_bar0_size {16} \ - CONFIG.pf0_msi_enabled {false} \ - CONFIG.pf0_msix_enabled {true} \ - CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ - CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \ - CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \ - CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \ - CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \ - CONFIG.MSI_X_OPTIONS {MSI-X_External} \ - CONFIG.vendor_id {1234} \ - CONFIG.mode_selection {Advanced} \ -] [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/VCU1525/fpga_25g/lib b/fpga/mqnic/VCU1525/fpga_25g/lib deleted file mode 120000 index 9512b3d5e..000000000 --- a/fpga/mqnic/VCU1525/fpga_25g/lib +++ /dev/null @@ -1 +0,0 @@ -../../../lib/ \ No newline at end of file diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/common b/fpga/mqnic/VCU1525/fpga_25g/rtl/common deleted file mode 120000 index 449c9409c..000000000 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/common +++ /dev/null @@ -1 +0,0 @@ -../../../../common/rtl/ \ No newline at end of file diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/debounce_switch.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/debounce_switch.v deleted file mode 100644 index 8e93a50c4..000000000 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/debounce_switch.v +++ /dev/null @@ -1,93 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog-2001 - -`resetall -`timescale 1 ns / 1 ps -`default_nettype none - -/* - * Synchronizes switch and button inputs with a slow sampled shift register - */ -module debounce_switch #( - parameter WIDTH=1, // width of the input and output signals - parameter N=3, // length of shift register - parameter RATE=125000 // clock division factor -)( - input wire clk, - input wire rst, - input wire [WIDTH-1:0] in, - output wire [WIDTH-1:0] out -); - -reg [23:0] cnt_reg = 24'd0; - -reg [N-1:0] debounce_reg[WIDTH-1:0]; - -reg [WIDTH-1:0] state; - -/* - * The synchronized output is the state register - */ -assign out = state; - -integer k; - -always @(posedge clk or posedge rst) begin - if (rst) begin - cnt_reg <= 0; - state <= 0; - - for (k = 0; k < WIDTH; k = k + 1) begin - debounce_reg[k] <= 0; - end - end else begin - if (cnt_reg < RATE) begin - cnt_reg <= cnt_reg + 24'd1; - end else begin - cnt_reg <= 24'd0; - end - - if (cnt_reg == 24'd0) begin - for (k = 0; k < WIDTH; k = k + 1) begin - debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]}; - end - end - - for (k = 0; k < WIDTH; k = k + 1) begin - if (|debounce_reg[k] == 0) begin - state[k] <= 0; - end else if (&debounce_reg[k] == 1) begin - state[k] <= 1; - end else begin - state[k] <= state[k]; - end - end - end -end - -endmodule - -`resetall diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v deleted file mode 100644 index e79630106..000000000 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v +++ /dev/null @@ -1,2370 +0,0 @@ -// SPDX-License-Identifier: BSD-2-Clause-Views -/* - * Copyright (c) 2019-2023 The Regents of the University of California - */ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA top-level module - */ -module fpga # -( - // FW and board IDs - parameter FPGA_ID = 32'h4B31093, - parameter FW_ID = 32'h00000000, - parameter FW_VER = 32'h00_00_01_00, - parameter BOARD_ID = 32'h10ee_95f5, - parameter BOARD_VER = 32'h01_00_00_00, - parameter BUILD_DATE = 32'd602976000, - parameter GIT_HASH = 32'hdce357bf, - parameter RELEASE_INFO = 32'h00000000, - - // Board configuration - parameter TDMA_BER_ENABLE = 0, - - // Structural configuration - parameter IF_COUNT = 2, - parameter PORTS_PER_IF = 1, - parameter SCHED_PER_IF = PORTS_PER_IF, - parameter PORT_MASK = 0, - - // Clock configuration - parameter CLK_PERIOD_NS_NUM = 4, - parameter CLK_PERIOD_NS_DENOM = 1, - - // PTP configuration - parameter PTP_CLOCK_PIPELINE = 0, - parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_PORT_CDC_PIPELINE = 0, - parameter PTP_PEROUT_ENABLE = 0, - parameter PTP_PEROUT_COUNT = 1, - - // Queue manager configuration - parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_QUEUE_OP_TABLE_SIZE = 32, - parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter CQ_OP_TABLE_SIZE = 32, - parameter EQN_WIDTH = 5, - parameter TX_QUEUE_INDEX_WIDTH = 13, - parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, - parameter EQ_PIPELINE = 3, - parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), - parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), - - // TX and RX engine configuration - parameter TX_DESC_TABLE_SIZE = 32, - parameter RX_DESC_TABLE_SIZE = 32, - parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, - - // Scheduler configuration - parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, - parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, - parameter TDMA_INDEX_WIDTH = 6, - - // Interface configuration - parameter PTP_TS_ENABLE = 1, - parameter TX_CPL_FIFO_DEPTH = 32, - parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_HASH_ENABLE = 1, - parameter RX_CHECKSUM_ENABLE = 1, - parameter PFC_ENABLE = 1, - parameter LFC_ENABLE = PFC_ENABLE, - parameter ENABLE_PADDING = 1, - parameter ENABLE_DIC = 1, - parameter MIN_FRAME_LENGTH = 64, - parameter TX_FIFO_DEPTH = 32768, - parameter RX_FIFO_DEPTH = 32768, - parameter MAX_TX_SIZE = 9214, - parameter MAX_RX_SIZE = 9214, - parameter TX_RAM_SIZE = 32768, - parameter RX_RAM_SIZE = 32768, - - // RAM configuration - parameter DDR_CH = 4, - parameter DDR_ENABLE = 0, - parameter AXI_DDR_DATA_WIDTH = 512, - parameter AXI_DDR_ADDR_WIDTH = 34, - parameter AXI_DDR_ID_WIDTH = 8, - parameter AXI_DDR_MAX_BURST_LEN = 256, - parameter AXI_DDR_NARROW_BURST = 0, - - // Application block configuration - parameter APP_ID = 32'h00000000, - parameter APP_ENABLE = 0, - parameter APP_CTRL_ENABLE = 1, - parameter APP_DMA_ENABLE = 1, - parameter APP_AXIS_DIRECT_ENABLE = 1, - parameter APP_AXIS_SYNC_ENABLE = 1, - parameter APP_AXIS_IF_ENABLE = 1, - parameter APP_STAT_ENABLE = 1, - - // DMA interface configuration - parameter DMA_IMM_ENABLE = 0, - parameter DMA_IMM_WIDTH = 32, - parameter DMA_LEN_WIDTH = 16, - parameter DMA_TAG_WIDTH = 16, - parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), - parameter RAM_PIPELINE = 2, - - // PCIe interface configuration - parameter AXIS_PCIE_DATA_WIDTH = 512, - parameter PF_COUNT = 1, - parameter VF_COUNT = 0, - - // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EQN_WIDTH, - - // AXI lite interface configuration (control) - parameter AXIL_CTRL_DATA_WIDTH = 32, - parameter AXIL_CTRL_ADDR_WIDTH = 24, - - // AXI lite interface configuration (application control) - parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, - parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, - - // Ethernet interface configuration - parameter AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE = 1, - parameter AXIS_ETH_TX_PIPELINE = 4, - parameter AXIS_ETH_TX_FIFO_PIPELINE = 4, - parameter AXIS_ETH_TX_TS_PIPELINE = 4, - parameter AXIS_ETH_RX_PIPELINE = 4, - parameter AXIS_ETH_RX_FIFO_PIPELINE = 4, - - // Statistics counter subsystem - parameter STAT_ENABLE = 1, - parameter STAT_DMA_ENABLE = 1, - parameter STAT_PCIE_ENABLE = 1, - parameter STAT_INC_WIDTH = 24, - parameter STAT_ID_WIDTH = 12 -) -( - /* - * Clock and reset - */ - input wire clk_300mhz_0_p, - input wire clk_300mhz_0_n, - input wire clk_300mhz_1_p, - input wire clk_300mhz_1_n, - input wire clk_300mhz_2_p, - input wire clk_300mhz_2_n, - input wire clk_300mhz_3_p, - input wire clk_300mhz_3_n, - - /* - * GPIO - */ - input wire [3:0] sw, - output wire [2:0] led, - - /* - * I2C for board management - */ - inout wire i2c_scl, - inout wire i2c_sda, - - /* - * PCI express - */ - input wire [15:0] pcie_rx_p, - input wire [15:0] pcie_rx_n, - output wire [15:0] pcie_tx_p, - output wire [15:0] pcie_tx_n, - input wire pcie_refclk_p, - input wire pcie_refclk_n, - input wire pcie_reset_n, - - /* - * Ethernet: QSFP28 - */ - output wire [3:0] qsfp0_tx_p, - output wire [3:0] qsfp0_tx_n, - input wire [3:0] qsfp0_rx_p, - input wire [3:0] qsfp0_rx_n, - // input wire qsfp0_mgt_refclk_0_p, - // input wire qsfp0_mgt_refclk_0_n, - input wire qsfp0_mgt_refclk_1_p, - input wire qsfp0_mgt_refclk_1_n, - output wire qsfp0_modsell, - output wire qsfp0_resetl, - input wire qsfp0_modprsl, - input wire qsfp0_intl, - output wire qsfp0_lpmode, - output wire qsfp0_refclk_reset, - output wire [1:0] qsfp0_fs, - - output wire [3:0] qsfp1_tx_p, - output wire [3:0] qsfp1_tx_n, - input wire [3:0] qsfp1_rx_p, - input wire [3:0] qsfp1_rx_n, - // input wire qsfp1_mgt_refclk_0_p, - // input wire qsfp1_mgt_refclk_0_n, - input wire qsfp1_mgt_refclk_1_p, - input wire qsfp1_mgt_refclk_1_n, - output wire qsfp1_modsell, - output wire qsfp1_resetl, - input wire qsfp1_modprsl, - input wire qsfp1_intl, - output wire qsfp1_lpmode, - output wire qsfp1_refclk_reset, - output wire [1:0] qsfp1_fs, - - /* - * DDR4 - */ - output wire [16:0] ddr4_c0_adr, - output wire [1:0] ddr4_c0_ba, - output wire [1:0] ddr4_c0_bg, - output wire [0:0] ddr4_c0_ck_t, - output wire [0:0] ddr4_c0_ck_c, - output wire [0:0] ddr4_c0_cke, - output wire [0:0] ddr4_c0_cs_n, - output wire ddr4_c0_act_n, - output wire [0:0] ddr4_c0_odt, - output wire ddr4_c0_par, - output wire ddr4_c0_reset_n, - inout wire [71:0] ddr4_c0_dq, - inout wire [17:0] ddr4_c0_dqs_t, - inout wire [17:0] ddr4_c0_dqs_c, - - output wire [16:0] ddr4_c1_adr, - output wire [1:0] ddr4_c1_ba, - output wire [1:0] ddr4_c1_bg, - output wire [0:0] ddr4_c1_ck_t, - output wire [0:0] ddr4_c1_ck_c, - output wire [0:0] ddr4_c1_cke, - output wire [0:0] ddr4_c1_cs_n, - output wire ddr4_c1_act_n, - output wire [0:0] ddr4_c1_odt, - output wire ddr4_c1_par, - output wire ddr4_c1_reset_n, - inout wire [71:0] ddr4_c1_dq, - inout wire [17:0] ddr4_c1_dqs_t, - inout wire [17:0] ddr4_c1_dqs_c, - - output wire [16:0] ddr4_c2_adr, - output wire [1:0] ddr4_c2_ba, - output wire [1:0] ddr4_c2_bg, - output wire [0:0] ddr4_c2_ck_t, - output wire [0:0] ddr4_c2_ck_c, - output wire [0:0] ddr4_c2_cke, - output wire [0:0] ddr4_c2_cs_n, - output wire ddr4_c2_act_n, - output wire [0:0] ddr4_c2_odt, - output wire ddr4_c2_par, - output wire ddr4_c2_reset_n, - inout wire [71:0] ddr4_c2_dq, - inout wire [17:0] ddr4_c2_dqs_t, - inout wire [17:0] ddr4_c2_dqs_c, - - output wire [16:0] ddr4_c3_adr, - output wire [1:0] ddr4_c3_ba, - output wire [1:0] ddr4_c3_bg, - output wire [0:0] ddr4_c3_ck_t, - output wire [0:0] ddr4_c3_ck_c, - output wire [0:0] ddr4_c3_cke, - output wire [0:0] ddr4_c3_cs_n, - output wire ddr4_c3_act_n, - output wire [0:0] ddr4_c3_odt, - output wire ddr4_c3_par, - output wire ddr4_c3_reset_n, - inout wire [71:0] ddr4_c3_dq, - inout wire [17:0] ddr4_c3_dqs_t, - inout wire [17:0] ddr4_c3_dqs_c -); - -// PTP configuration -parameter PTP_CLK_PERIOD_NS_NUM = 1024; -parameter PTP_CLK_PERIOD_NS_DENOM = 165; -parameter PTP_TS_WIDTH = 96; -parameter IF_PTP_PERIOD_NS = 6'h6; -parameter IF_PTP_PERIOD_FNS = 16'h6666; - -// Interface configuration -parameter TX_TAG_WIDTH = 16; - -// RAM configuration -parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); - -// PCIe interface configuration -parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); -parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161; -parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137; -parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183; -parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81; -parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256; -parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; -parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; -parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; -parameter RQ_SEQ_NUM_WIDTH = 6; -parameter PCIE_TAG_COUNT = 256; - -// Ethernet interface configuration -parameter XGMII_DATA_WIDTH = 64; -parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; -parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH; -parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; -parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE ? 2 : 1); -parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1; -parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; - -// Clock and reset -wire pcie_user_clk; -wire pcie_user_reset; - -wire cfgmclk_int; - -wire clk_161mhz_ref_int; - -wire clk_125mhz_mmcm_out; - -// Internal 125 MHz clock -wire clk_125mhz_int; -wire rst_125mhz_int; - -wire mmcm_rst; -wire mmcm_locked; -wire mmcm_clkfb; - -// MMCM instance -// 161.13 MHz in, 125 MHz out -// PFD range: 10 MHz to 500 MHz -// VCO range: 800 MHz to 1600 MHz -// M = 64, D = 11 sets Fvco = 937.5 MHz (in range) -// Divide by 7.5 to get output frequency of 125 MHz -MMCME4_BASE #( - .BANDWIDTH("OPTIMIZED"), - .CLKOUT0_DIVIDE_F(7.5), - .CLKOUT0_DUTY_CYCLE(0.5), - .CLKOUT0_PHASE(0), - .CLKOUT1_DIVIDE(1), - .CLKOUT1_DUTY_CYCLE(0.5), - .CLKOUT1_PHASE(0), - .CLKOUT2_DIVIDE(1), - .CLKOUT2_DUTY_CYCLE(0.5), - .CLKOUT2_PHASE(0), - .CLKOUT3_DIVIDE(1), - .CLKOUT3_DUTY_CYCLE(0.5), - .CLKOUT3_PHASE(0), - .CLKOUT4_DIVIDE(1), - .CLKOUT4_DUTY_CYCLE(0.5), - .CLKOUT4_PHASE(0), - .CLKOUT5_DIVIDE(1), - .CLKOUT5_DUTY_CYCLE(0.5), - .CLKOUT5_PHASE(0), - .CLKOUT6_DIVIDE(1), - .CLKOUT6_DUTY_CYCLE(0.5), - .CLKOUT6_PHASE(0), - .CLKFBOUT_MULT_F(64), - .CLKFBOUT_PHASE(0), - .DIVCLK_DIVIDE(11), - .REF_JITTER1(0.010), - .CLKIN1_PERIOD(6.206), - .STARTUP_WAIT("FALSE"), - .CLKOUT4_CASCADE("FALSE") -) -clk_mmcm_inst ( - .CLKIN1(clk_161mhz_ref_int), - .CLKFBIN(mmcm_clkfb), - .RST(mmcm_rst), - .PWRDWN(1'b0), - .CLKOUT0(clk_125mhz_mmcm_out), - .CLKOUT0B(), - .CLKOUT1(), - .CLKOUT1B(), - .CLKOUT2(), - .CLKOUT2B(), - .CLKOUT3(), - .CLKOUT3B(), - .CLKOUT4(), - .CLKOUT5(), - .CLKOUT6(), - .CLKFBOUT(mmcm_clkfb), - .CLKFBOUTB(), - .LOCKED(mmcm_locked) -); - -BUFG -clk_125mhz_bufg_inst ( - .I(clk_125mhz_mmcm_out), - .O(clk_125mhz_int) -); - -sync_reset #( - .N(4) -) -sync_reset_125mhz_inst ( - .clk(clk_125mhz_int), - .rst(~mmcm_locked), - .out(rst_125mhz_int) -); - -// GPIO -wire btnu_int; -wire btnl_int; -wire btnd_int; -wire btnr_int; -wire btnc_int; -wire [3:0] sw_int; -wire qsfp0_modprsl_int; -wire qsfp1_modprsl_int; -wire qsfp0_intl_int; -wire qsfp1_intl_int; -wire i2c_scl_i; -wire i2c_scl_o; -wire i2c_scl_t; -wire i2c_sda_i; -wire i2c_sda_o; -wire i2c_sda_t; - -reg i2c_scl_o_reg; -reg i2c_scl_t_reg; -reg i2c_sda_o_reg; -reg i2c_sda_t_reg; - -always @(posedge pcie_user_clk) begin - i2c_scl_o_reg <= i2c_scl_o; - i2c_scl_t_reg <= i2c_scl_t; - i2c_sda_o_reg <= i2c_sda_o; - i2c_sda_t_reg <= i2c_sda_t; -end - -debounce_switch #( - .WIDTH(4), - .N(4), - .RATE(250000) -) -debounce_switch_inst ( - .clk(pcie_user_clk), - .rst(pcie_user_reset), - .in({sw}), - .out({sw_int}) -); - -sync_signal #( - .WIDTH(6), - .N(2) -) -sync_signal_inst ( - .clk(pcie_user_clk), - .in({qsfp0_modprsl, qsfp1_modprsl, qsfp0_intl, qsfp1_intl, - i2c_scl, i2c_sda}), - .out({qsfp0_modprsl_int, qsfp1_modprsl_int, qsfp0_intl_int, qsfp1_intl_int, - i2c_scl_i, i2c_sda_i}) -); - -assign i2c_scl = i2c_scl_t_reg ? 1'bz : i2c_scl_o_reg; -assign i2c_sda = i2c_sda_t_reg ? 1'bz : i2c_sda_o_reg; - -// Flash -wire qspi_clk_int; -wire [3:0] qspi_dq_int; -wire [3:0] qspi_dq_i_int; -wire [3:0] qspi_dq_o_int; -wire [3:0] qspi_dq_oe_int; -wire qspi_cs_int; - -reg qspi_clk_reg; -reg [3:0] qspi_dq_o_reg; -reg [3:0] qspi_dq_oe_reg; -reg qspi_cs_reg; - -always @(posedge pcie_user_clk) begin - qspi_clk_reg <= qspi_clk_int; - qspi_dq_o_reg <= qspi_dq_o_int; - qspi_dq_oe_reg <= qspi_dq_oe_int; - qspi_cs_reg <= qspi_cs_int; -end - -sync_signal #( - .WIDTH(4), - .N(2) -) -flash_sync_signal_inst ( - .clk(pcie_user_clk), - .in({qspi_dq_int}), - .out({qspi_dq_i_int}) -); - -// startupe3 instance -wire cfgmclk; - -STARTUPE3 -startupe3_inst ( - .CFGCLK(), - .CFGMCLK(cfgmclk), - .DI(qspi_dq_int), - .DO(qspi_dq_o_reg), - .DTS(~qspi_dq_oe_reg), - .EOS(), - .FCSBO(qspi_cs_reg), - .FCSBTS(1'b0), - .GSR(1'b0), - .GTS(1'b0), - .KEYCLEARB(1'b1), - .PACK(1'b0), - .PREQ(), - .USRCCLKO(qspi_clk_reg), - .USRCCLKTS(1'b0), - .USRDONEO(1'b0), - .USRDONETS(1'b1) -); - -BUFG -cfgmclk_bufg_inst ( - .I(cfgmclk), - .O(cfgmclk_int) -); - -// FPGA boot -wire fpga_boot; - -reg fpga_boot_sync_reg_0 = 1'b0; -reg fpga_boot_sync_reg_1 = 1'b0; -reg fpga_boot_sync_reg_2 = 1'b0; - -wire icap_avail; -reg [2:0] icap_state = 0; -reg icap_csib_reg = 1'b1; -reg icap_rdwrb_reg = 1'b0; -reg [31:0] icap_di_reg = 32'hffffffff; - -wire [31:0] icap_di_rev; - -assign icap_di_rev[ 7] = icap_di_reg[ 0]; -assign icap_di_rev[ 6] = icap_di_reg[ 1]; -assign icap_di_rev[ 5] = icap_di_reg[ 2]; -assign icap_di_rev[ 4] = icap_di_reg[ 3]; -assign icap_di_rev[ 3] = icap_di_reg[ 4]; -assign icap_di_rev[ 2] = icap_di_reg[ 5]; -assign icap_di_rev[ 1] = icap_di_reg[ 6]; -assign icap_di_rev[ 0] = icap_di_reg[ 7]; - -assign icap_di_rev[15] = icap_di_reg[ 8]; -assign icap_di_rev[14] = icap_di_reg[ 9]; -assign icap_di_rev[13] = icap_di_reg[10]; -assign icap_di_rev[12] = icap_di_reg[11]; -assign icap_di_rev[11] = icap_di_reg[12]; -assign icap_di_rev[10] = icap_di_reg[13]; -assign icap_di_rev[ 9] = icap_di_reg[14]; -assign icap_di_rev[ 8] = icap_di_reg[15]; - -assign icap_di_rev[23] = icap_di_reg[16]; -assign icap_di_rev[22] = icap_di_reg[17]; -assign icap_di_rev[21] = icap_di_reg[18]; -assign icap_di_rev[20] = icap_di_reg[19]; -assign icap_di_rev[19] = icap_di_reg[20]; -assign icap_di_rev[18] = icap_di_reg[21]; -assign icap_di_rev[17] = icap_di_reg[22]; -assign icap_di_rev[16] = icap_di_reg[23]; - -assign icap_di_rev[31] = icap_di_reg[24]; -assign icap_di_rev[30] = icap_di_reg[25]; -assign icap_di_rev[29] = icap_di_reg[26]; -assign icap_di_rev[28] = icap_di_reg[27]; -assign icap_di_rev[27] = icap_di_reg[28]; -assign icap_di_rev[26] = icap_di_reg[29]; -assign icap_di_rev[25] = icap_di_reg[30]; -assign icap_di_rev[24] = icap_di_reg[31]; - -always @(posedge clk_125mhz_int) begin - case (icap_state) - 0: begin - icap_state <= 0; - icap_csib_reg <= 1'b1; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hffffffff; // dummy word - - if (fpga_boot_sync_reg_2 && icap_avail) begin - icap_state <= 1; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hffffffff; // dummy word - end - end - 1: begin - icap_state <= 2; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'hAA995566; // sync word - end - 2: begin - icap_state <= 3; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h20000000; // type 1 noop - end - 3: begin - icap_state <= 4; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h30008001; // write 1 word to CMD - end - 4: begin - icap_state <= 5; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h0000000F; // IPROG - end - 5: begin - icap_state <= 0; - icap_csib_reg <= 1'b0; - icap_rdwrb_reg <= 1'b0; - icap_di_reg <= 32'h20000000; // type 1 noop - end - endcase - - fpga_boot_sync_reg_0 <= fpga_boot; - fpga_boot_sync_reg_1 <= fpga_boot_sync_reg_0; - fpga_boot_sync_reg_2 <= fpga_boot_sync_reg_1; -end - -ICAPE3 -icape3_inst ( - .AVAIL(icap_avail), - .CLK(clk_125mhz_int), - .CSIB(icap_csib_reg), - .I(icap_di_rev), - .O(), - .PRDONE(), - .PRERROR(), - .RDWRB(icap_rdwrb_reg) -); - -// configure SI5335 clock generators -reg qsfp_refclk_reset_reg = 1'b1; -reg sys_reset_reg = 1'b1; - -reg [9:0] reset_timer_reg = 0; - -assign mmcm_rst = sys_reset_reg | pcie_user_reset; - -always @(posedge cfgmclk_int) begin - if (&reset_timer_reg) begin - if (qsfp_refclk_reset_reg) begin - qsfp_refclk_reset_reg <= 1'b0; - reset_timer_reg <= 0; - end else begin - qsfp_refclk_reset_reg <= 1'b0; - sys_reset_reg <= 1'b0; - end - end else begin - reset_timer_reg <= reset_timer_reg + 1; - end -end - -// PCIe -wire pcie_sys_clk; -wire pcie_sys_clk_gt; - -IBUFDS_GTE4 #( - .REFCLK_HROW_CK_SEL(2'b00) -) -ibufds_gte4_pcie_mgt_refclk_inst ( - .I (pcie_refclk_p), - .IB (pcie_refclk_n), - .CEB (1'b0), - .O (pcie_sys_clk_gt), - .ODIV2 (pcie_sys_clk) -); - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep; -wire axis_rq_tlast; -wire axis_rq_tready; -wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser; -wire axis_rq_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep; -wire axis_rc_tlast; -wire axis_rc_tready; -wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser; -wire axis_rc_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep; -wire axis_cq_tlast; -wire axis_cq_tready; -wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser; -wire axis_cq_tvalid; - -wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata; -wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep; -wire axis_cc_tlast; -wire axis_cc_tready; -wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser; -wire axis_cc_tvalid; - -wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num0; -wire pcie_rq_seq_num_vld0; -wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num1; -wire pcie_rq_seq_num_vld1; - -wire [3:0] pcie_tfc_nph_av; -wire [3:0] pcie_tfc_npd_av; - -wire [2:0] cfg_max_payload; -wire [2:0] cfg_max_read_req; -wire [3:0] cfg_rcb_status; - -wire [9:0] cfg_mgmt_addr; -wire [7:0] cfg_mgmt_function_number; -wire cfg_mgmt_write; -wire [31:0] cfg_mgmt_write_data; -wire [3:0] cfg_mgmt_byte_enable; -wire cfg_mgmt_read; -wire [31:0] cfg_mgmt_read_data; -wire cfg_mgmt_read_write_done; - -wire [7:0] cfg_fc_ph; -wire [11:0] cfg_fc_pd; -wire [7:0] cfg_fc_nph; -wire [11:0] cfg_fc_npd; -wire [7:0] cfg_fc_cplh; -wire [11:0] cfg_fc_cpld; -wire [2:0] cfg_fc_sel; - -wire [3:0] cfg_interrupt_msix_enable; -wire [3:0] cfg_interrupt_msix_mask; -wire [251:0] cfg_interrupt_msix_vf_enable; -wire [251:0] cfg_interrupt_msix_vf_mask; -wire [63:0] cfg_interrupt_msix_address; -wire [31:0] cfg_interrupt_msix_data; -wire cfg_interrupt_msix_int; -wire [1:0] cfg_interrupt_msix_vec_pending; -wire cfg_interrupt_msix_vec_pending_status; -wire cfg_interrupt_msix_sent; -wire cfg_interrupt_msix_fail; -wire [7:0] cfg_interrupt_msi_function_number; - -wire status_error_cor; -wire status_error_uncor; - -// extra register for pcie_user_reset signal -wire pcie_user_reset_int; -(* shreg_extract = "no" *) -reg pcie_user_reset_reg_1 = 1'b1; -(* shreg_extract = "no" *) -reg pcie_user_reset_reg_2 = 1'b1; - -always @(posedge pcie_user_clk) begin - pcie_user_reset_reg_1 <= pcie_user_reset_int; - pcie_user_reset_reg_2 <= pcie_user_reset_reg_1; -end - -BUFG -pcie_user_reset_bufg_inst ( - .I(pcie_user_reset_reg_2), - .O(pcie_user_reset) -); - -pcie4_uscale_plus_0 -pcie4_uscale_plus_inst ( - .pci_exp_txn(pcie_tx_n), - .pci_exp_txp(pcie_tx_p), - .pci_exp_rxn(pcie_rx_n), - .pci_exp_rxp(pcie_rx_p), - .user_clk(pcie_user_clk), - .user_reset(pcie_user_reset_int), - .user_lnk_up(), - - .s_axis_rq_tdata(axis_rq_tdata), - .s_axis_rq_tkeep(axis_rq_tkeep), - .s_axis_rq_tlast(axis_rq_tlast), - .s_axis_rq_tready(axis_rq_tready), - .s_axis_rq_tuser(axis_rq_tuser), - .s_axis_rq_tvalid(axis_rq_tvalid), - - .m_axis_rc_tdata(axis_rc_tdata), - .m_axis_rc_tkeep(axis_rc_tkeep), - .m_axis_rc_tlast(axis_rc_tlast), - .m_axis_rc_tready(axis_rc_tready), - .m_axis_rc_tuser(axis_rc_tuser), - .m_axis_rc_tvalid(axis_rc_tvalid), - - .m_axis_cq_tdata(axis_cq_tdata), - .m_axis_cq_tkeep(axis_cq_tkeep), - .m_axis_cq_tlast(axis_cq_tlast), - .m_axis_cq_tready(axis_cq_tready), - .m_axis_cq_tuser(axis_cq_tuser), - .m_axis_cq_tvalid(axis_cq_tvalid), - - .s_axis_cc_tdata(axis_cc_tdata), - .s_axis_cc_tkeep(axis_cc_tkeep), - .s_axis_cc_tlast(axis_cc_tlast), - .s_axis_cc_tready(axis_cc_tready), - .s_axis_cc_tuser(axis_cc_tuser), - .s_axis_cc_tvalid(axis_cc_tvalid), - - .pcie_rq_seq_num0(pcie_rq_seq_num0), - .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0), - .pcie_rq_seq_num1(pcie_rq_seq_num1), - .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1), - .pcie_rq_tag0(), - .pcie_rq_tag1(), - .pcie_rq_tag_av(), - .pcie_rq_tag_vld0(), - .pcie_rq_tag_vld1(), - - .pcie_tfc_nph_av(pcie_tfc_nph_av), - .pcie_tfc_npd_av(pcie_tfc_npd_av), - - .pcie_cq_np_req(1'b1), - .pcie_cq_np_req_count(), - - .cfg_phy_link_down(), - .cfg_phy_link_status(), - .cfg_negotiated_width(), - .cfg_current_speed(), - .cfg_max_payload(cfg_max_payload), - .cfg_max_read_req(cfg_max_read_req), - .cfg_function_status(), - .cfg_function_power_state(), - .cfg_vf_status(), - .cfg_vf_power_state(), - .cfg_link_power_state(), - - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - .cfg_mgmt_debug_access(1'b0), - - .cfg_err_cor_out(), - .cfg_err_nonfatal_out(), - .cfg_err_fatal_out(), - .cfg_local_error_valid(), - .cfg_local_error_out(), - .cfg_ltssm_state(), - .cfg_rx_pm_state(), - .cfg_tx_pm_state(), - .cfg_rcb_status(cfg_rcb_status), - .cfg_obff_enable(), - .cfg_pl_status_change(), - .cfg_tph_requester_enable(), - .cfg_tph_st_mode(), - .cfg_vf_tph_requester_enable(), - .cfg_vf_tph_st_mode(), - - .cfg_msg_received(), - .cfg_msg_received_data(), - .cfg_msg_received_type(), - .cfg_msg_transmit(1'b0), - .cfg_msg_transmit_type(3'd0), - .cfg_msg_transmit_data(32'd0), - .cfg_msg_transmit_done(), - - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - .cfg_dsn(64'd0), - - .cfg_power_state_change_ack(1'b1), - .cfg_power_state_change_interrupt(), - - .cfg_err_cor_in(status_error_cor), - .cfg_err_uncor_in(status_error_uncor), - .cfg_flr_in_process(), - .cfg_flr_done(4'd0), - .cfg_vf_flr_in_process(), - .cfg_vf_flr_func_num(8'd0), - .cfg_vf_flr_done(8'd0), - - .cfg_link_training_enable(1'b1), - - .cfg_interrupt_int(4'd0), - .cfg_interrupt_pending(4'd0), - .cfg_interrupt_sent(), - .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), - .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), - .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), - .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), - .cfg_interrupt_msix_address(cfg_interrupt_msix_address), - .cfg_interrupt_msix_data(cfg_interrupt_msix_data), - .cfg_interrupt_msix_int(cfg_interrupt_msix_int), - .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), - .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), - .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent), - .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - .cfg_pm_aspm_l1_entry_reject(1'b0), - .cfg_pm_aspm_tx_l0s_entry_disable(1'b0), - - .cfg_hot_reset_out(), - - .cfg_config_space_enable(1'b1), - .cfg_req_pm_transition_l23_ready(1'b0), - .cfg_hot_reset_in(1'b0), - - .cfg_ds_port_number(8'd0), - .cfg_ds_bus_number(8'd0), - .cfg_ds_device_number(5'd0), - - .sys_clk(pcie_sys_clk), - .sys_clk_gt(pcie_sys_clk_gt), - .sys_reset(pcie_reset_n), - - .phy_rdy_out() -); - -// XGMII 10G PHY - -// QSFP0 -assign qsfp0_refclk_reset = qsfp_refclk_reset_reg; -assign qsfp0_fs = 2'b10; - -wire qsfp0_tx_clk_1_int; -wire qsfp0_tx_rst_1_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1_int; -wire qsfp0_cfg_tx_prbs31_enable_1_int; -wire qsfp0_rx_clk_1_int; -wire qsfp0_rx_rst_1_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1_int; -wire qsfp0_cfg_rx_prbs31_enable_1_int; -wire [6:0] qsfp0_rx_error_count_1_int; -wire qsfp0_tx_clk_2_int; -wire qsfp0_tx_rst_2_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2_int; -wire qsfp0_cfg_tx_prbs31_enable_2_int; -wire qsfp0_rx_clk_2_int; -wire qsfp0_rx_rst_2_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2_int; -wire qsfp0_cfg_rx_prbs31_enable_2_int; -wire [6:0] qsfp0_rx_error_count_2_int; -wire qsfp0_tx_clk_3_int; -wire qsfp0_tx_rst_3_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3_int; -wire qsfp0_cfg_tx_prbs31_enable_3_int; -wire qsfp0_rx_clk_3_int; -wire qsfp0_rx_rst_3_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3_int; -wire qsfp0_cfg_rx_prbs31_enable_3_int; -wire [6:0] qsfp0_rx_error_count_3_int; -wire qsfp0_tx_clk_4_int; -wire qsfp0_tx_rst_4_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4_int; -wire qsfp0_cfg_tx_prbs31_enable_4_int; -wire qsfp0_rx_clk_4_int; -wire qsfp0_rx_rst_4_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4_int; -wire qsfp0_cfg_rx_prbs31_enable_4_int; -wire [6:0] qsfp0_rx_error_count_4_int; - -wire qsfp0_drp_clk = clk_125mhz_int; -wire qsfp0_drp_rst = rst_125mhz_int; -wire [23:0] qsfp0_drp_addr; -wire [15:0] qsfp0_drp_di; -wire qsfp0_drp_en; -wire qsfp0_drp_we; -wire [15:0] qsfp0_drp_do; -wire qsfp0_drp_rdy; - -wire qsfp0_rx_block_lock_1; -wire qsfp0_rx_status_1; -wire qsfp0_rx_block_lock_2; -wire qsfp0_rx_status_2; -wire qsfp0_rx_block_lock_3; -wire qsfp0_rx_status_3; -wire qsfp0_rx_block_lock_4; -wire qsfp0_rx_status_4; - -wire qsfp0_gtpowergood; - -wire qsfp0_mgt_refclk_1; -wire qsfp0_mgt_refclk_1_int; -wire qsfp0_mgt_refclk_1_bufg; - -assign clk_161mhz_ref_int = qsfp0_mgt_refclk_1_bufg; - -IBUFDS_GTE4 ibufds_gte4_qsfp0_mgt_refclk_1_inst ( - .I (qsfp0_mgt_refclk_1_p), - .IB (qsfp0_mgt_refclk_1_n), - .CEB (1'b0), - .O (qsfp0_mgt_refclk_1), - .ODIV2 (qsfp0_mgt_refclk_1_int) -); - -BUFG_GT bufg_gt_qsfp0_mgt_refclk_1_inst ( - .CE (qsfp0_gtpowergood), - .CEMASK (1'b1), - .CLR (1'b0), - .CLRMASK (1'b1), - .DIV (3'd0), - .I (qsfp0_mgt_refclk_1_int), - .O (qsfp0_mgt_refclk_1_bufg) -); - -wire qsfp0_rst; - -sync_reset #( - .N(4) -) -qsfp0_sync_reset_inst ( - .clk(qsfp0_mgt_refclk_1_bufg), - .rst(rst_125mhz_int), - .out(qsfp0_rst) -); - -eth_xcvr_phy_10g_gty_quad_wrapper #( - .PRBS31_ENABLE(1), - .TX_SERDES_PIPELINE(1), - .RX_SERDES_PIPELINE(1), - .COUNT_125US(125000/2.56) -) -qsfp0_phy_quad_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp0_rst), - - /* - * Common - */ - .xcvr_gtpowergood_out(qsfp0_gtpowergood), - .xcvr_ref_clk(qsfp0_mgt_refclk_1), - - /* - * DRP - */ - .drp_clk(qsfp0_drp_clk), - .drp_rst(qsfp0_drp_rst), - .drp_addr(qsfp0_drp_addr), - .drp_di(qsfp0_drp_di), - .drp_en(qsfp0_drp_en), - .drp_we(qsfp0_drp_we), - .drp_do(qsfp0_drp_do), - .drp_rdy(qsfp0_drp_rdy), - - /* - * Serial data - */ - .xcvr_txp(qsfp0_tx_p), - .xcvr_txn(qsfp0_tx_n), - .xcvr_rxp(qsfp0_rx_p), - .xcvr_rxn(qsfp0_rx_n), - - /* - * PHY connections - */ - .phy_1_tx_clk(qsfp0_tx_clk_1_int), - .phy_1_tx_rst(qsfp0_tx_rst_1_int), - .phy_1_xgmii_txd(qsfp0_txd_1_int), - .phy_1_xgmii_txc(qsfp0_txc_1_int), - .phy_1_rx_clk(qsfp0_rx_clk_1_int), - .phy_1_rx_rst(qsfp0_rx_rst_1_int), - .phy_1_xgmii_rxd(qsfp0_rxd_1_int), - .phy_1_xgmii_rxc(qsfp0_rxc_1_int), - .phy_1_tx_bad_block(), - .phy_1_rx_error_count(qsfp0_rx_error_count_1_int), - .phy_1_rx_bad_block(), - .phy_1_rx_sequence_error(), - .phy_1_rx_block_lock(qsfp0_rx_block_lock_1), - .phy_1_rx_high_ber(), - .phy_1_rx_status(qsfp0_rx_status_1), - .phy_1_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_1_int), - .phy_1_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_1_int), - - .phy_2_tx_clk(qsfp0_tx_clk_2_int), - .phy_2_tx_rst(qsfp0_tx_rst_2_int), - .phy_2_xgmii_txd(qsfp0_txd_2_int), - .phy_2_xgmii_txc(qsfp0_txc_2_int), - .phy_2_rx_clk(qsfp0_rx_clk_2_int), - .phy_2_rx_rst(qsfp0_rx_rst_2_int), - .phy_2_xgmii_rxd(qsfp0_rxd_2_int), - .phy_2_xgmii_rxc(qsfp0_rxc_2_int), - .phy_2_tx_bad_block(), - .phy_2_rx_error_count(qsfp0_rx_error_count_2_int), - .phy_2_rx_bad_block(), - .phy_2_rx_sequence_error(), - .phy_2_rx_block_lock(qsfp0_rx_block_lock_2), - .phy_2_rx_high_ber(), - .phy_2_rx_status(qsfp0_rx_status_2), - .phy_2_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_2_int), - .phy_2_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_2_int), - - .phy_3_tx_clk(qsfp0_tx_clk_3_int), - .phy_3_tx_rst(qsfp0_tx_rst_3_int), - .phy_3_xgmii_txd(qsfp0_txd_3_int), - .phy_3_xgmii_txc(qsfp0_txc_3_int), - .phy_3_rx_clk(qsfp0_rx_clk_3_int), - .phy_3_rx_rst(qsfp0_rx_rst_3_int), - .phy_3_xgmii_rxd(qsfp0_rxd_3_int), - .phy_3_xgmii_rxc(qsfp0_rxc_3_int), - .phy_3_tx_bad_block(), - .phy_3_rx_error_count(qsfp0_rx_error_count_3_int), - .phy_3_rx_bad_block(), - .phy_3_rx_sequence_error(), - .phy_3_rx_block_lock(qsfp0_rx_block_lock_3), - .phy_3_rx_high_ber(), - .phy_3_rx_status(qsfp0_rx_status_3), - .phy_3_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_3_int), - .phy_3_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_3_int), - - .phy_4_tx_clk(qsfp0_tx_clk_4_int), - .phy_4_tx_rst(qsfp0_tx_rst_4_int), - .phy_4_xgmii_txd(qsfp0_txd_4_int), - .phy_4_xgmii_txc(qsfp0_txc_4_int), - .phy_4_rx_clk(qsfp0_rx_clk_4_int), - .phy_4_rx_rst(qsfp0_rx_rst_4_int), - .phy_4_xgmii_rxd(qsfp0_rxd_4_int), - .phy_4_xgmii_rxc(qsfp0_rxc_4_int), - .phy_4_tx_bad_block(), - .phy_4_rx_error_count(qsfp0_rx_error_count_4_int), - .phy_4_rx_bad_block(), - .phy_4_rx_sequence_error(), - .phy_4_rx_block_lock(qsfp0_rx_block_lock_4), - .phy_4_rx_high_ber(), - .phy_4_rx_status(qsfp0_rx_status_4), - .phy_4_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_4_int), - .phy_4_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_4_int) -); - -// QSFP1 -assign qsfp1_refclk_reset = qsfp_refclk_reset_reg; -assign qsfp1_fs = 2'b10; - -wire qsfp1_tx_clk_1_int; -wire qsfp1_tx_rst_1_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1_int; -wire qsfp1_cfg_tx_prbs31_enable_1_int; -wire qsfp1_rx_clk_1_int; -wire qsfp1_rx_rst_1_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1_int; -wire qsfp1_cfg_rx_prbs31_enable_1_int; -wire [6:0] qsfp1_rx_error_count_1_int; -wire qsfp1_tx_clk_2_int; -wire qsfp1_tx_rst_2_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2_int; -wire qsfp1_cfg_tx_prbs31_enable_2_int; -wire qsfp1_rx_clk_2_int; -wire qsfp1_rx_rst_2_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2_int; -wire qsfp1_cfg_rx_prbs31_enable_2_int; -wire [6:0] qsfp1_rx_error_count_2_int; -wire qsfp1_tx_clk_3_int; -wire qsfp1_tx_rst_3_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3_int; -wire qsfp1_cfg_tx_prbs31_enable_3_int; -wire qsfp1_rx_clk_3_int; -wire qsfp1_rx_rst_3_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3_int; -wire qsfp1_cfg_rx_prbs31_enable_3_int; -wire [6:0] qsfp1_rx_error_count_3_int; -wire qsfp1_tx_clk_4_int; -wire qsfp1_tx_rst_4_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4_int; -wire qsfp1_cfg_tx_prbs31_enable_4_int; -wire qsfp1_rx_clk_4_int; -wire qsfp1_rx_rst_4_int; -wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4_int; -wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4_int; -wire qsfp1_cfg_rx_prbs31_enable_4_int; -wire [6:0] qsfp1_rx_error_count_4_int; - -wire qsfp1_drp_clk = clk_125mhz_int; -wire qsfp1_drp_rst = rst_125mhz_int; -wire [23:0] qsfp1_drp_addr; -wire [15:0] qsfp1_drp_di; -wire qsfp1_drp_en; -wire qsfp1_drp_we; -wire [15:0] qsfp1_drp_do; -wire qsfp1_drp_rdy; - -wire qsfp1_rx_block_lock_1; -wire qsfp1_rx_status_1; -wire qsfp1_rx_block_lock_2; -wire qsfp1_rx_status_2; -wire qsfp1_rx_block_lock_3; -wire qsfp1_rx_status_3; -wire qsfp1_rx_block_lock_4; -wire qsfp1_rx_status_4; - -wire qsfp1_gtpowergood; - -wire qsfp1_mgt_refclk_1; -wire qsfp1_mgt_refclk_1_int; -wire qsfp1_mgt_refclk_1_bufg; - -IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_1_inst ( - .I (qsfp1_mgt_refclk_1_p), - .IB (qsfp1_mgt_refclk_1_n), - .CEB (1'b0), - .O (qsfp1_mgt_refclk_1), - .ODIV2 (qsfp1_mgt_refclk_1_int) -); - -BUFG_GT bufg_gt_qsfp1_mgt_refclk_1_inst ( - .CE (qsfp1_gtpowergood), - .CEMASK (1'b1), - .CLR (1'b0), - .CLRMASK (1'b1), - .DIV (3'd0), - .I (qsfp1_mgt_refclk_1_int), - .O (qsfp1_mgt_refclk_1_bufg) -); - -wire qsfp1_rst; - -sync_reset #( - .N(4) -) -qsfp1_sync_reset_inst ( - .clk(qsfp1_mgt_refclk_1_bufg), - .rst(rst_125mhz_int), - .out(qsfp1_rst) -); - -eth_xcvr_phy_10g_gty_quad_wrapper #( - .PRBS31_ENABLE(1), - .TX_SERDES_PIPELINE(1), - .RX_SERDES_PIPELINE(1), - .COUNT_125US(125000/2.56) -) -qsfp1_phy_quad_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(qsfp1_rst), - - /* - * Common - */ - .xcvr_gtpowergood_out(qsfp1_gtpowergood), - .xcvr_ref_clk(qsfp1_mgt_refclk_1), - - /* - * DRP - */ - .drp_clk(qsfp1_drp_clk), - .drp_rst(qsfp1_drp_rst), - .drp_addr(qsfp1_drp_addr), - .drp_di(qsfp1_drp_di), - .drp_en(qsfp1_drp_en), - .drp_we(qsfp1_drp_we), - .drp_do(qsfp1_drp_do), - .drp_rdy(qsfp1_drp_rdy), - - /* - * Serial data - */ - .xcvr_txp(qsfp1_tx_p), - .xcvr_txn(qsfp1_tx_n), - .xcvr_rxp(qsfp1_rx_p), - .xcvr_rxn(qsfp1_rx_n), - - /* - * PHY connections - */ - .phy_1_tx_clk(qsfp1_tx_clk_1_int), - .phy_1_tx_rst(qsfp1_tx_rst_1_int), - .phy_1_xgmii_txd(qsfp1_txd_1_int), - .phy_1_xgmii_txc(qsfp1_txc_1_int), - .phy_1_rx_clk(qsfp1_rx_clk_1_int), - .phy_1_rx_rst(qsfp1_rx_rst_1_int), - .phy_1_xgmii_rxd(qsfp1_rxd_1_int), - .phy_1_xgmii_rxc(qsfp1_rxc_1_int), - .phy_1_tx_bad_block(), - .phy_1_rx_error_count(qsfp1_rx_error_count_1_int), - .phy_1_rx_bad_block(), - .phy_1_rx_sequence_error(), - .phy_1_rx_block_lock(qsfp1_rx_block_lock_1), - .phy_1_rx_high_ber(), - .phy_1_rx_status(qsfp1_rx_status_1), - .phy_1_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_1_int), - .phy_1_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_1_int), - - .phy_2_tx_clk(qsfp1_tx_clk_2_int), - .phy_2_tx_rst(qsfp1_tx_rst_2_int), - .phy_2_xgmii_txd(qsfp1_txd_2_int), - .phy_2_xgmii_txc(qsfp1_txc_2_int), - .phy_2_rx_clk(qsfp1_rx_clk_2_int), - .phy_2_rx_rst(qsfp1_rx_rst_2_int), - .phy_2_xgmii_rxd(qsfp1_rxd_2_int), - .phy_2_xgmii_rxc(qsfp1_rxc_2_int), - .phy_2_tx_bad_block(), - .phy_2_rx_error_count(qsfp1_rx_error_count_2_int), - .phy_2_rx_bad_block(), - .phy_2_rx_sequence_error(), - .phy_2_rx_block_lock(qsfp1_rx_block_lock_2), - .phy_2_rx_high_ber(), - .phy_2_rx_status(qsfp1_rx_status_2), - .phy_2_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_2_int), - .phy_2_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_2_int), - - .phy_3_tx_clk(qsfp1_tx_clk_3_int), - .phy_3_tx_rst(qsfp1_tx_rst_3_int), - .phy_3_xgmii_txd(qsfp1_txd_3_int), - .phy_3_xgmii_txc(qsfp1_txc_3_int), - .phy_3_rx_clk(qsfp1_rx_clk_3_int), - .phy_3_rx_rst(qsfp1_rx_rst_3_int), - .phy_3_xgmii_rxd(qsfp1_rxd_3_int), - .phy_3_xgmii_rxc(qsfp1_rxc_3_int), - .phy_3_tx_bad_block(), - .phy_3_rx_error_count(qsfp1_rx_error_count_3_int), - .phy_3_rx_bad_block(), - .phy_3_rx_sequence_error(), - .phy_3_rx_block_lock(qsfp1_rx_block_lock_3), - .phy_3_rx_high_ber(), - .phy_3_rx_status(qsfp1_rx_status_3), - .phy_3_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_3_int), - .phy_3_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_3_int), - - .phy_4_tx_clk(qsfp1_tx_clk_4_int), - .phy_4_tx_rst(qsfp1_tx_rst_4_int), - .phy_4_xgmii_txd(qsfp1_txd_4_int), - .phy_4_xgmii_txc(qsfp1_txc_4_int), - .phy_4_rx_clk(qsfp1_rx_clk_4_int), - .phy_4_rx_rst(qsfp1_rx_rst_4_int), - .phy_4_xgmii_rxd(qsfp1_rxd_4_int), - .phy_4_xgmii_rxc(qsfp1_rxc_4_int), - .phy_4_tx_bad_block(), - .phy_4_rx_error_count(qsfp1_rx_error_count_4_int), - .phy_4_rx_bad_block(), - .phy_4_rx_sequence_error(), - .phy_4_rx_block_lock(qsfp1_rx_block_lock_4), - .phy_4_rx_high_ber(), - .phy_4_rx_status(qsfp1_rx_status_4), - .phy_4_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_4_int), - .phy_4_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_4_int) -); - -wire ptp_clk; -wire ptp_rst; -wire ptp_sample_clk; - -assign ptp_clk = qsfp0_mgt_refclk_1_bufg; -assign ptp_rst = qsfp0_rst; -assign ptp_sample_clk = clk_125mhz_int; - -// DDR4 -wire [DDR_CH-1:0] ddr_clk; -wire [DDR_CH-1:0] ddr_rst; - -wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; -wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; -wire [DDR_CH*8-1:0] m_axi_ddr_awlen; -wire [DDR_CH*3-1:0] m_axi_ddr_awsize; -wire [DDR_CH*2-1:0] m_axi_ddr_awburst; -wire [DDR_CH-1:0] m_axi_ddr_awlock; -wire [DDR_CH*4-1:0] m_axi_ddr_awcache; -wire [DDR_CH*3-1:0] m_axi_ddr_awprot; -wire [DDR_CH*4-1:0] m_axi_ddr_awqos; -wire [DDR_CH-1:0] m_axi_ddr_awvalid; -wire [DDR_CH-1:0] m_axi_ddr_awready; -wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; -wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; -wire [DDR_CH-1:0] m_axi_ddr_wlast; -wire [DDR_CH-1:0] m_axi_ddr_wvalid; -wire [DDR_CH-1:0] m_axi_ddr_wready; -wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; -wire [DDR_CH*2-1:0] m_axi_ddr_bresp; -wire [DDR_CH-1:0] m_axi_ddr_bvalid; -wire [DDR_CH-1:0] m_axi_ddr_bready; -wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; -wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; -wire [DDR_CH*8-1:0] m_axi_ddr_arlen; -wire [DDR_CH*3-1:0] m_axi_ddr_arsize; -wire [DDR_CH*2-1:0] m_axi_ddr_arburst; -wire [DDR_CH-1:0] m_axi_ddr_arlock; -wire [DDR_CH*4-1:0] m_axi_ddr_arcache; -wire [DDR_CH*3-1:0] m_axi_ddr_arprot; -wire [DDR_CH*4-1:0] m_axi_ddr_arqos; -wire [DDR_CH-1:0] m_axi_ddr_arvalid; -wire [DDR_CH-1:0] m_axi_ddr_arready; -wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; -wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; -wire [DDR_CH*2-1:0] m_axi_ddr_rresp; -wire [DDR_CH-1:0] m_axi_ddr_rlast; -wire [DDR_CH-1:0] m_axi_ddr_rvalid; -wire [DDR_CH-1:0] m_axi_ddr_rready; - -wire [DDR_CH-1:0] ddr_status; - -generate - -if (DDR_ENABLE && DDR_CH > 0) begin - -reg ddr4_rst_reg = 1'b1; - -always @(posedge pcie_user_clk or posedge pcie_user_reset) begin - if (pcie_user_reset) begin - ddr4_rst_reg <= 1'b1; - end else begin - ddr4_rst_reg <= 1'b0; - end -end - -ddr4_0 ddr4_c0_inst ( - .c0_sys_clk_p(clk_300mhz_0_p), - .c0_sys_clk_n(clk_300mhz_0_n), - .sys_rst(ddr4_rst_reg), - - .c0_init_calib_complete(ddr_status[0 +: 1]), - .c0_ddr4_interrupt(), - .dbg_clk(), - .dbg_bus(), - - .c0_ddr4_adr(ddr4_c0_adr), - .c0_ddr4_ba(ddr4_c0_ba), - .c0_ddr4_cke(ddr4_c0_cke), - .c0_ddr4_cs_n(ddr4_c0_cs_n), - .c0_ddr4_dq(ddr4_c0_dq), - .c0_ddr4_dqs_t(ddr4_c0_dqs_t), - .c0_ddr4_dqs_c(ddr4_c0_dqs_c), - .c0_ddr4_odt(ddr4_c0_odt), - .c0_ddr4_parity(ddr4_c0_par), - .c0_ddr4_bg(ddr4_c0_bg), - .c0_ddr4_reset_n(ddr4_c0_reset_n), - .c0_ddr4_act_n(ddr4_c0_act_n), - .c0_ddr4_ck_t(ddr4_c0_ck_t), - .c0_ddr4_ck_c(ddr4_c0_ck_c), - - .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), - .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), - - .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), - - .c0_ddr4_s_axi_ctrl_awvalid(1'b0), - .c0_ddr4_s_axi_ctrl_awready(), - .c0_ddr4_s_axi_ctrl_awaddr(32'd0), - .c0_ddr4_s_axi_ctrl_wvalid(1'b0), - .c0_ddr4_s_axi_ctrl_wready(), - .c0_ddr4_s_axi_ctrl_wdata(32'd0), - .c0_ddr4_s_axi_ctrl_bvalid(), - .c0_ddr4_s_axi_ctrl_bready(1'b1), - .c0_ddr4_s_axi_ctrl_bresp(), - .c0_ddr4_s_axi_ctrl_arvalid(1'b0), - .c0_ddr4_s_axi_ctrl_arready(), - .c0_ddr4_s_axi_ctrl_araddr(31'd0), - .c0_ddr4_s_axi_ctrl_rvalid(), - .c0_ddr4_s_axi_ctrl_rready(1'b1), - .c0_ddr4_s_axi_ctrl_rdata(), - .c0_ddr4_s_axi_ctrl_rresp(), - - .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), - .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), - .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), - .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), - .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), - .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), - .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), - .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), - .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), - .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), - .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), - .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), - .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), - .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), - .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), - .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), - .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), - .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), - .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), - .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), - .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), - .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), - .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), - .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), - .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), - .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), - .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), - .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), - .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), - .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), - .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) -); - -end else begin - -assign ddr4_c0_adr = {17{1'bz}}; -assign ddr4_c0_ba = {2{1'bz}}; -assign ddr4_c0_bg = {2{1'bz}}; -assign ddr4_c0_cke = 1'bz; -assign ddr4_c0_cs_n = 1'bz; -assign ddr4_c0_act_n = 1'bz; -assign ddr4_c0_odt = 1'bz; -assign ddr4_c0_par = 1'bz; -assign ddr4_c0_reset_n = 1'b0; -assign ddr4_c0_dq = {72{1'bz}}; -assign ddr4_c0_dqs_t = {18{1'bz}}; -assign ddr4_c0_dqs_c = {18{1'bz}}; - -OBUFTDS ddr4_c0_ck_obuftds_inst ( - .I(1'b0), - .T(1'b1), - .O(ddr4_c0_ck_t), - .OB(ddr4_c0_ck_c) -); - -assign ddr_clk = 0; -assign ddr_rst = 0; - -assign m_axi_ddr_awready = 0; -assign m_axi_ddr_wready = 0; -assign m_axi_ddr_bid = 0; -assign m_axi_ddr_bresp = 0; -assign m_axi_ddr_bvalid = 0; -assign m_axi_ddr_arready = 0; -assign m_axi_ddr_rid = 0; -assign m_axi_ddr_rdata = 0; -assign m_axi_ddr_rresp = 0; -assign m_axi_ddr_rlast = 0; -assign m_axi_ddr_rvalid = 0; - -assign ddr_status = 0; - -end - -if (DDR_ENABLE && DDR_CH > 1) begin - -reg ddr4_rst_reg = 1'b1; - -always @(posedge pcie_user_clk or posedge pcie_user_reset) begin - if (pcie_user_reset) begin - ddr4_rst_reg <= 1'b1; - end else begin - ddr4_rst_reg <= 1'b0; - end -end - -ddr4_0 ddr4_c1_inst ( - .c0_sys_clk_p(clk_300mhz_1_p), - .c0_sys_clk_n(clk_300mhz_1_n), - .sys_rst(ddr4_rst_reg), - - .c0_init_calib_complete(ddr_status[1 +: 1]), - .c0_ddr4_interrupt(), - .dbg_clk(), - .dbg_bus(), - - .c0_ddr4_adr(ddr4_c1_adr), - .c0_ddr4_ba(ddr4_c1_ba), - .c0_ddr4_cke(ddr4_c1_cke), - .c0_ddr4_cs_n(ddr4_c1_cs_n), - .c0_ddr4_dq(ddr4_c1_dq), - .c0_ddr4_dqs_t(ddr4_c1_dqs_t), - .c0_ddr4_dqs_c(ddr4_c1_dqs_c), - .c0_ddr4_odt(ddr4_c1_odt), - .c0_ddr4_parity(ddr4_c1_par), - .c0_ddr4_bg(ddr4_c1_bg), - .c0_ddr4_reset_n(ddr4_c1_reset_n), - .c0_ddr4_act_n(ddr4_c1_act_n), - .c0_ddr4_ck_t(ddr4_c1_ck_t), - .c0_ddr4_ck_c(ddr4_c1_ck_c), - - .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), - .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), - - .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), - - .c0_ddr4_s_axi_ctrl_awvalid(1'b0), - .c0_ddr4_s_axi_ctrl_awready(), - .c0_ddr4_s_axi_ctrl_awaddr(32'd0), - .c0_ddr4_s_axi_ctrl_wvalid(1'b0), - .c0_ddr4_s_axi_ctrl_wready(), - .c0_ddr4_s_axi_ctrl_wdata(32'd0), - .c0_ddr4_s_axi_ctrl_bvalid(), - .c0_ddr4_s_axi_ctrl_bready(1'b1), - .c0_ddr4_s_axi_ctrl_bresp(), - .c0_ddr4_s_axi_ctrl_arvalid(1'b0), - .c0_ddr4_s_axi_ctrl_arready(), - .c0_ddr4_s_axi_ctrl_araddr(31'd0), - .c0_ddr4_s_axi_ctrl_rvalid(), - .c0_ddr4_s_axi_ctrl_rready(1'b1), - .c0_ddr4_s_axi_ctrl_rdata(), - .c0_ddr4_s_axi_ctrl_rresp(), - - .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), - .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), - .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), - .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), - .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), - .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), - .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), - .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), - .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), - .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), - .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), - .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), - .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), - .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), - .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), - .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), - .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), - .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), - .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), - .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), - .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), - .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), - .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), - .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), - .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), - .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), - .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), - .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), - .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), - .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), - .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) -); - -end else begin - -assign ddr4_c1_adr = {17{1'bz}}; -assign ddr4_c1_ba = {2{1'bz}}; -assign ddr4_c1_bg = {2{1'bz}}; -assign ddr4_c1_cke = 1'bz; -assign ddr4_c1_cs_n = 1'bz; -assign ddr4_c1_act_n = 1'bz; -assign ddr4_c1_odt = 1'bz; -assign ddr4_c1_par = 1'bz; -assign ddr4_c1_reset_n = 1'b0; -assign ddr4_c1_dq = {72{1'bz}}; -assign ddr4_c1_dqs_t = {18{1'bz}}; -assign ddr4_c1_dqs_c = {18{1'bz}}; - -OBUFTDS ddr4_c1_ck_obuftds_inst ( - .I(1'b0), - .T(1'b1), - .O(ddr4_c1_ck_t), - .OB(ddr4_c1_ck_c) -); - -end - -if (DDR_ENABLE && DDR_CH > 2) begin - -reg ddr4_rst_reg = 1'b1; - -always @(posedge pcie_user_clk or posedge pcie_user_reset) begin - if (pcie_user_reset) begin - ddr4_rst_reg <= 1'b1; - end else begin - ddr4_rst_reg <= 1'b0; - end -end - -ddr4_0 ddr4_c2_inst ( - .c0_sys_clk_p(clk_300mhz_2_p), - .c0_sys_clk_n(clk_300mhz_2_n), - .sys_rst(ddr4_rst_reg), - - .c0_init_calib_complete(ddr_status[2 +: 1]), - .c0_ddr4_interrupt(), - .dbg_clk(), - .dbg_bus(), - - .c0_ddr4_adr(ddr4_c2_adr), - .c0_ddr4_ba(ddr4_c2_ba), - .c0_ddr4_cke(ddr4_c2_cke), - .c0_ddr4_cs_n(ddr4_c2_cs_n), - .c0_ddr4_dq(ddr4_c2_dq), - .c0_ddr4_dqs_t(ddr4_c2_dqs_t), - .c0_ddr4_dqs_c(ddr4_c2_dqs_c), - .c0_ddr4_odt(ddr4_c2_odt), - .c0_ddr4_parity(ddr4_c2_par), - .c0_ddr4_bg(ddr4_c2_bg), - .c0_ddr4_reset_n(ddr4_c2_reset_n), - .c0_ddr4_act_n(ddr4_c2_act_n), - .c0_ddr4_ck_t(ddr4_c2_ck_t), - .c0_ddr4_ck_c(ddr4_c2_ck_c), - - .c0_ddr4_ui_clk(ddr_clk[2 +: 1]), - .c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]), - - .c0_ddr4_aresetn(!ddr_rst[2 +: 1]), - - .c0_ddr4_s_axi_ctrl_awvalid(1'b0), - .c0_ddr4_s_axi_ctrl_awready(), - .c0_ddr4_s_axi_ctrl_awaddr(32'd0), - .c0_ddr4_s_axi_ctrl_wvalid(1'b0), - .c0_ddr4_s_axi_ctrl_wready(), - .c0_ddr4_s_axi_ctrl_wdata(32'd0), - .c0_ddr4_s_axi_ctrl_bvalid(), - .c0_ddr4_s_axi_ctrl_bready(1'b1), - .c0_ddr4_s_axi_ctrl_bresp(), - .c0_ddr4_s_axi_ctrl_arvalid(1'b0), - .c0_ddr4_s_axi_ctrl_arready(), - .c0_ddr4_s_axi_ctrl_araddr(31'd0), - .c0_ddr4_s_axi_ctrl_rvalid(), - .c0_ddr4_s_axi_ctrl_rready(1'b1), - .c0_ddr4_s_axi_ctrl_rdata(), - .c0_ddr4_s_axi_ctrl_rresp(), - - .c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]), - .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]), - .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]), - .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]), - .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]), - .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]), - .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]), - .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]), - .c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]), - .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), - .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), - .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]), - .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]), - .c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]), - .c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]), - .c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]), - .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]), - .c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]), - .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]), - .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]), - .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]), - .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]), - .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]), - .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]), - .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]), - .c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]), - .c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]), - .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]), - .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]), - .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]), - .c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) -); - -end else begin - -assign ddr4_c2_adr = {17{1'bz}}; -assign ddr4_c2_ba = {2{1'bz}}; -assign ddr4_c2_bg = {2{1'bz}}; -assign ddr4_c2_cke = 1'bz; -assign ddr4_c2_cs_n = 1'bz; -assign ddr4_c2_act_n = 1'bz; -assign ddr4_c2_odt = 1'bz; -assign ddr4_c2_par = 1'bz; -assign ddr4_c2_reset_n = 1'b0; -assign ddr4_c2_dq = {72{1'bz}}; -assign ddr4_c2_dqs_t = {18{1'bz}}; -assign ddr4_c2_dqs_c = {18{1'bz}}; - -OBUFTDS ddr4_c2_ck_obuftds_inst ( - .I(1'b0), - .T(1'b1), - .O(ddr4_c2_ck_t), - .OB(ddr4_c2_ck_c) -); - -end - -if (DDR_ENABLE && DDR_CH > 3) begin - -reg ddr4_rst_reg = 1'b1; - -always @(posedge pcie_user_clk or posedge pcie_user_reset) begin - if (pcie_user_reset) begin - ddr4_rst_reg <= 1'b1; - end else begin - ddr4_rst_reg <= 1'b0; - end -end - -ddr4_0 ddr4_c3_inst ( - .c0_sys_clk_p(clk_300mhz_3_p), - .c0_sys_clk_n(clk_300mhz_3_n), - .sys_rst(ddr4_rst_reg), - - .c0_init_calib_complete(ddr_status[3 +: 1]), - .c0_ddr4_interrupt(), - .dbg_clk(), - .dbg_bus(), - - .c0_ddr4_adr(ddr4_c3_adr), - .c0_ddr4_ba(ddr4_c3_ba), - .c0_ddr4_cke(ddr4_c3_cke), - .c0_ddr4_cs_n(ddr4_c3_cs_n), - .c0_ddr4_dq(ddr4_c3_dq), - .c0_ddr4_dqs_t(ddr4_c3_dqs_t), - .c0_ddr4_dqs_c(ddr4_c3_dqs_c), - .c0_ddr4_odt(ddr4_c3_odt), - .c0_ddr4_parity(ddr4_c3_par), - .c0_ddr4_bg(ddr4_c3_bg), - .c0_ddr4_reset_n(ddr4_c3_reset_n), - .c0_ddr4_act_n(ddr4_c3_act_n), - .c0_ddr4_ck_t(ddr4_c3_ck_t), - .c0_ddr4_ck_c(ddr4_c3_ck_c), - - .c0_ddr4_ui_clk(ddr_clk[3 +: 1]), - .c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]), - - .c0_ddr4_aresetn(!ddr_rst[3 +: 1]), - - .c0_ddr4_s_axi_ctrl_awvalid(1'b0), - .c0_ddr4_s_axi_ctrl_awready(), - .c0_ddr4_s_axi_ctrl_awaddr(32'd0), - .c0_ddr4_s_axi_ctrl_wvalid(1'b0), - .c0_ddr4_s_axi_ctrl_wready(), - .c0_ddr4_s_axi_ctrl_wdata(32'd0), - .c0_ddr4_s_axi_ctrl_bvalid(), - .c0_ddr4_s_axi_ctrl_bready(1'b1), - .c0_ddr4_s_axi_ctrl_bresp(), - .c0_ddr4_s_axi_ctrl_arvalid(1'b0), - .c0_ddr4_s_axi_ctrl_arready(), - .c0_ddr4_s_axi_ctrl_araddr(31'd0), - .c0_ddr4_s_axi_ctrl_rvalid(), - .c0_ddr4_s_axi_ctrl_rready(1'b1), - .c0_ddr4_s_axi_ctrl_rdata(), - .c0_ddr4_s_axi_ctrl_rresp(), - - .c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]), - .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]), - .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]), - .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]), - .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]), - .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]), - .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]), - .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]), - .c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]), - .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), - .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), - .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]), - .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]), - .c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]), - .c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]), - .c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]), - .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]), - .c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), - .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]), - .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]), - .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]), - .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]), - .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]), - .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]), - .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]), - .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]), - .c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]), - .c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]), - .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]), - .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]), - .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]), - .c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), - .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) -); - -end else begin - -assign ddr4_c3_adr = {17{1'bz}}; -assign ddr4_c3_ba = {2{1'bz}}; -assign ddr4_c3_bg = {2{1'bz}}; -assign ddr4_c3_cke = 1'bz; -assign ddr4_c3_cs_n = 1'bz; -assign ddr4_c3_act_n = 1'bz; -assign ddr4_c3_odt = 1'bz; -assign ddr4_c3_par = 1'bz; -assign ddr4_c3_reset_n = 1'b0; -assign ddr4_c3_dq = {72{1'bz}}; -assign ddr4_c3_dqs_t = {18{1'bz}}; -assign ddr4_c3_dqs_c = {18{1'bz}}; - -OBUFTDS ddr4_c3_ck_obuftds_inst ( - .I(1'b0), - .T(1'b1), - .O(ddr4_c3_ck_t), - .OB(ddr4_c3_ck_c) -); - -end - -endgenerate - -fpga_core #( - // FW and board IDs - .FPGA_ID(FPGA_ID), - .FW_ID(FW_ID), - .FW_VER(FW_VER), - .BOARD_ID(BOARD_ID), - .BOARD_VER(BOARD_VER), - .BUILD_DATE(BUILD_DATE), - .GIT_HASH(GIT_HASH), - .RELEASE_INFO(RELEASE_INFO), - - // Board configuration - .TDMA_BER_ENABLE(TDMA_BER_ENABLE), - - // Structural configuration - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - .SCHED_PER_IF(SCHED_PER_IF), - .PORT_MASK(PORT_MASK), - - // Clock configuration - .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), - .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), - - // PTP configuration - .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), - .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), - .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), - - // Queue manager configuration - .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), - .EQN_WIDTH(EQN_WIDTH), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .CQN_WIDTH(CQN_WIDTH), - .EQ_PIPELINE(EQ_PIPELINE), - .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), - .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .CQ_PIPELINE(CQ_PIPELINE), - - // TX and RX engine configuration - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), - - // Scheduler configuration - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - - // Interface configuration - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), - .TX_TAG_WIDTH(TX_TAG_WIDTH), - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .PFC_ENABLE(PFC_ENABLE), - .LFC_ENABLE(LFC_ENABLE), - .ENABLE_PADDING(ENABLE_PADDING), - .ENABLE_DIC(ENABLE_DIC), - .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), - .TX_FIFO_DEPTH(TX_FIFO_DEPTH), - .RX_FIFO_DEPTH(RX_FIFO_DEPTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - - // RAM configuration - .DDR_CH(DDR_CH), - .DDR_ENABLE(DDR_ENABLE), - .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), - .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), - .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), - .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), - .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), - .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), - - // Application block configuration - .APP_ID(APP_ID), - .APP_ENABLE(APP_ENABLE), - .APP_CTRL_ENABLE(APP_CTRL_ENABLE), - .APP_DMA_ENABLE(APP_DMA_ENABLE), - .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), - .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), - .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), - .APP_STAT_ENABLE(APP_STAT_ENABLE), - - // DMA interface configuration - .DMA_IMM_ENABLE(DMA_IMM_ENABLE), - .DMA_IMM_WIDTH(DMA_IMM_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - - // PCIe interface configuration - .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), - .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), - .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), - .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), - .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), - .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), - .RC_STRADDLE(RC_STRADDLE), - .RQ_STRADDLE(RQ_STRADDLE), - .CQ_STRADDLE(CQ_STRADDLE), - .CC_STRADDLE(CC_STRADDLE), - .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), - .PF_COUNT(PF_COUNT), - .VF_COUNT(VF_COUNT), - .PCIE_TAG_COUNT(PCIE_TAG_COUNT), - - // Interrupt configuration - .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), - - // AXI lite interface configuration (control) - .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - - // AXI lite interface configuration (application control) - .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), - .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), - - // Ethernet interface configuration - .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), - .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH), - .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), - .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), - .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), - .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), - .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), - .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), - - // Statistics counter subsystem - .STAT_ENABLE(STAT_ENABLE), - .STAT_DMA_ENABLE(STAT_DMA_ENABLE), - .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), - .STAT_INC_WIDTH(STAT_INC_WIDTH), - .STAT_ID_WIDTH(STAT_ID_WIDTH) -) -core_inst ( - /* - * Clock: 250 MHz - * Synchronous reset - */ - .clk_250mhz(pcie_user_clk), - .rst_250mhz(pcie_user_reset), - - /* - * PTP clock - */ - .ptp_clk(ptp_clk), - .ptp_rst(ptp_rst), - .ptp_sample_clk(ptp_sample_clk), - - /* - * GPIO - */ - .sw(sw_int), - .led(led), - - /* - * I2C - */ - .i2c_scl_i(i2c_scl_i), - .i2c_scl_o(i2c_scl_o), - .i2c_scl_t(i2c_scl_t), - .i2c_sda_i(i2c_sda_i), - .i2c_sda_o(i2c_sda_o), - .i2c_sda_t(i2c_sda_t), - - /* - * PCIe - */ - .m_axis_rq_tdata(axis_rq_tdata), - .m_axis_rq_tkeep(axis_rq_tkeep), - .m_axis_rq_tlast(axis_rq_tlast), - .m_axis_rq_tready(axis_rq_tready), - .m_axis_rq_tuser(axis_rq_tuser), - .m_axis_rq_tvalid(axis_rq_tvalid), - - .s_axis_rc_tdata(axis_rc_tdata), - .s_axis_rc_tkeep(axis_rc_tkeep), - .s_axis_rc_tlast(axis_rc_tlast), - .s_axis_rc_tready(axis_rc_tready), - .s_axis_rc_tuser(axis_rc_tuser), - .s_axis_rc_tvalid(axis_rc_tvalid), - - .s_axis_cq_tdata(axis_cq_tdata), - .s_axis_cq_tkeep(axis_cq_tkeep), - .s_axis_cq_tlast(axis_cq_tlast), - .s_axis_cq_tready(axis_cq_tready), - .s_axis_cq_tuser(axis_cq_tuser), - .s_axis_cq_tvalid(axis_cq_tvalid), - - .m_axis_cc_tdata(axis_cc_tdata), - .m_axis_cc_tkeep(axis_cc_tkeep), - .m_axis_cc_tlast(axis_cc_tlast), - .m_axis_cc_tready(axis_cc_tready), - .m_axis_cc_tuser(axis_cc_tuser), - .m_axis_cc_tvalid(axis_cc_tvalid), - - .s_axis_rq_seq_num_0(pcie_rq_seq_num0), - .s_axis_rq_seq_num_valid_0(pcie_rq_seq_num_vld0), - .s_axis_rq_seq_num_1(pcie_rq_seq_num1), - .s_axis_rq_seq_num_valid_1(pcie_rq_seq_num_vld1), - - .pcie_tfc_nph_av(pcie_tfc_nph_av), - .pcie_tfc_npd_av(pcie_tfc_npd_av), - - .cfg_max_payload(cfg_max_payload), - .cfg_max_read_req(cfg_max_read_req), - .cfg_rcb_status(cfg_rcb_status), - - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), - .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), - .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), - .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), - .cfg_interrupt_msix_address(cfg_interrupt_msix_address), - .cfg_interrupt_msix_data(cfg_interrupt_msix_data), - .cfg_interrupt_msix_int(cfg_interrupt_msix_int), - .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), - .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), - .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), - .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - .status_error_cor(status_error_cor), - .status_error_uncor(status_error_uncor), - - /* - * Ethernet: QSFP28 - */ - .qsfp0_tx_clk_1(qsfp0_tx_clk_1_int), - .qsfp0_tx_rst_1(qsfp0_tx_rst_1_int), - .qsfp0_txd_1(qsfp0_txd_1_int), - .qsfp0_txc_1(qsfp0_txc_1_int), - .qsfp0_cfg_tx_prbs31_enable_1(qsfp0_cfg_tx_prbs31_enable_1_int), - .qsfp0_rx_clk_1(qsfp0_rx_clk_1_int), - .qsfp0_rx_rst_1(qsfp0_rx_rst_1_int), - .qsfp0_rxd_1(qsfp0_rxd_1_int), - .qsfp0_rxc_1(qsfp0_rxc_1_int), - .qsfp0_cfg_rx_prbs31_enable_1(qsfp0_cfg_rx_prbs31_enable_1_int), - .qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int), - .qsfp0_rx_status_1(qsfp0_rx_status_1), - .qsfp0_tx_clk_2(qsfp0_tx_clk_2_int), - .qsfp0_tx_rst_2(qsfp0_tx_rst_2_int), - .qsfp0_txd_2(qsfp0_txd_2_int), - .qsfp0_txc_2(qsfp0_txc_2_int), - .qsfp0_cfg_tx_prbs31_enable_2(qsfp0_cfg_tx_prbs31_enable_2_int), - .qsfp0_rx_clk_2(qsfp0_rx_clk_2_int), - .qsfp0_rx_rst_2(qsfp0_rx_rst_2_int), - .qsfp0_rxd_2(qsfp0_rxd_2_int), - .qsfp0_rxc_2(qsfp0_rxc_2_int), - .qsfp0_cfg_rx_prbs31_enable_2(qsfp0_cfg_rx_prbs31_enable_2_int), - .qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int), - .qsfp0_rx_status_2(qsfp0_rx_status_2), - .qsfp0_tx_clk_3(qsfp0_tx_clk_3_int), - .qsfp0_tx_rst_3(qsfp0_tx_rst_3_int), - .qsfp0_txd_3(qsfp0_txd_3_int), - .qsfp0_txc_3(qsfp0_txc_3_int), - .qsfp0_cfg_tx_prbs31_enable_3(qsfp0_cfg_tx_prbs31_enable_3_int), - .qsfp0_rx_clk_3(qsfp0_rx_clk_3_int), - .qsfp0_rx_rst_3(qsfp0_rx_rst_3_int), - .qsfp0_rxd_3(qsfp0_rxd_3_int), - .qsfp0_rxc_3(qsfp0_rxc_3_int), - .qsfp0_cfg_rx_prbs31_enable_3(qsfp0_cfg_rx_prbs31_enable_3_int), - .qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int), - .qsfp0_rx_status_3(qsfp0_rx_status_3), - .qsfp0_tx_clk_4(qsfp0_tx_clk_4_int), - .qsfp0_tx_rst_4(qsfp0_tx_rst_4_int), - .qsfp0_txd_4(qsfp0_txd_4_int), - .qsfp0_txc_4(qsfp0_txc_4_int), - .qsfp0_cfg_tx_prbs31_enable_4(qsfp0_cfg_tx_prbs31_enable_4_int), - .qsfp0_rx_clk_4(qsfp0_rx_clk_4_int), - .qsfp0_rx_rst_4(qsfp0_rx_rst_4_int), - .qsfp0_rxd_4(qsfp0_rxd_4_int), - .qsfp0_rxc_4(qsfp0_rxc_4_int), - .qsfp0_cfg_rx_prbs31_enable_4(qsfp0_cfg_rx_prbs31_enable_4_int), - .qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int), - .qsfp0_rx_status_4(qsfp0_rx_status_4), - - .qsfp0_drp_clk(qsfp0_drp_clk), - .qsfp0_drp_rst(qsfp0_drp_rst), - .qsfp0_drp_addr(qsfp0_drp_addr), - .qsfp0_drp_di(qsfp0_drp_di), - .qsfp0_drp_en(qsfp0_drp_en), - .qsfp0_drp_we(qsfp0_drp_we), - .qsfp0_drp_do(qsfp0_drp_do), - .qsfp0_drp_rdy(qsfp0_drp_rdy), - - .qsfp0_modprsl(qsfp0_modprsl_int), - .qsfp0_modsell(qsfp0_modsell), - .qsfp0_resetl(qsfp0_resetl), - .qsfp0_intl(qsfp0_intl_int), - .qsfp0_lpmode(qsfp0_lpmode), - - .qsfp1_tx_clk_1(qsfp1_tx_clk_1_int), - .qsfp1_tx_rst_1(qsfp1_tx_rst_1_int), - .qsfp1_txd_1(qsfp1_txd_1_int), - .qsfp1_txc_1(qsfp1_txc_1_int), - .qsfp1_cfg_tx_prbs31_enable_1(qsfp1_cfg_tx_prbs31_enable_1_int), - .qsfp1_rx_clk_1(qsfp1_rx_clk_1_int), - .qsfp1_rx_rst_1(qsfp1_rx_rst_1_int), - .qsfp1_rxd_1(qsfp1_rxd_1_int), - .qsfp1_rxc_1(qsfp1_rxc_1_int), - .qsfp1_cfg_rx_prbs31_enable_1(qsfp1_cfg_rx_prbs31_enable_1_int), - .qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int), - .qsfp1_rx_status_1(qsfp1_rx_status_1), - .qsfp1_tx_clk_2(qsfp1_tx_clk_2_int), - .qsfp1_tx_rst_2(qsfp1_tx_rst_2_int), - .qsfp1_txd_2(qsfp1_txd_2_int), - .qsfp1_txc_2(qsfp1_txc_2_int), - .qsfp1_cfg_tx_prbs31_enable_2(qsfp1_cfg_tx_prbs31_enable_2_int), - .qsfp1_rx_clk_2(qsfp1_rx_clk_2_int), - .qsfp1_rx_rst_2(qsfp1_rx_rst_2_int), - .qsfp1_rxd_2(qsfp1_rxd_2_int), - .qsfp1_rxc_2(qsfp1_rxc_2_int), - .qsfp1_cfg_rx_prbs31_enable_2(qsfp1_cfg_rx_prbs31_enable_2_int), - .qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int), - .qsfp1_rx_status_2(qsfp1_rx_status_2), - .qsfp1_tx_clk_3(qsfp1_tx_clk_3_int), - .qsfp1_tx_rst_3(qsfp1_tx_rst_3_int), - .qsfp1_txd_3(qsfp1_txd_3_int), - .qsfp1_txc_3(qsfp1_txc_3_int), - .qsfp1_cfg_tx_prbs31_enable_3(qsfp1_cfg_tx_prbs31_enable_3_int), - .qsfp1_rx_clk_3(qsfp1_rx_clk_3_int), - .qsfp1_rx_rst_3(qsfp1_rx_rst_3_int), - .qsfp1_rxd_3(qsfp1_rxd_3_int), - .qsfp1_rxc_3(qsfp1_rxc_3_int), - .qsfp1_cfg_rx_prbs31_enable_3(qsfp1_cfg_rx_prbs31_enable_3_int), - .qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int), - .qsfp1_rx_status_3(qsfp1_rx_status_3), - .qsfp1_tx_clk_4(qsfp1_tx_clk_4_int), - .qsfp1_tx_rst_4(qsfp1_tx_rst_4_int), - .qsfp1_txd_4(qsfp1_txd_4_int), - .qsfp1_txc_4(qsfp1_txc_4_int), - .qsfp1_cfg_tx_prbs31_enable_4(qsfp1_cfg_tx_prbs31_enable_4_int), - .qsfp1_rx_clk_4(qsfp1_rx_clk_4_int), - .qsfp1_rx_rst_4(qsfp1_rx_rst_4_int), - .qsfp1_rxd_4(qsfp1_rxd_4_int), - .qsfp1_rxc_4(qsfp1_rxc_4_int), - .qsfp1_cfg_rx_prbs31_enable_4(qsfp1_cfg_rx_prbs31_enable_4_int), - .qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int), - .qsfp1_rx_status_4(qsfp1_rx_status_4), - - .qsfp1_drp_clk(qsfp1_drp_clk), - .qsfp1_drp_rst(qsfp1_drp_rst), - .qsfp1_drp_addr(qsfp1_drp_addr), - .qsfp1_drp_di(qsfp1_drp_di), - .qsfp1_drp_en(qsfp1_drp_en), - .qsfp1_drp_we(qsfp1_drp_we), - .qsfp1_drp_do(qsfp1_drp_do), - .qsfp1_drp_rdy(qsfp1_drp_rdy), - - .qsfp1_modprsl(qsfp1_modprsl_int), - .qsfp1_modsell(qsfp1_modsell), - .qsfp1_resetl(qsfp1_resetl), - .qsfp1_intl(qsfp1_intl_int), - .qsfp1_lpmode(qsfp1_lpmode), - - /* - * DDR - */ - .ddr_clk(ddr_clk), - .ddr_rst(ddr_rst), - - .m_axi_ddr_awid(m_axi_ddr_awid), - .m_axi_ddr_awaddr(m_axi_ddr_awaddr), - .m_axi_ddr_awlen(m_axi_ddr_awlen), - .m_axi_ddr_awsize(m_axi_ddr_awsize), - .m_axi_ddr_awburst(m_axi_ddr_awburst), - .m_axi_ddr_awlock(m_axi_ddr_awlock), - .m_axi_ddr_awcache(m_axi_ddr_awcache), - .m_axi_ddr_awprot(m_axi_ddr_awprot), - .m_axi_ddr_awqos(m_axi_ddr_awqos), - .m_axi_ddr_awvalid(m_axi_ddr_awvalid), - .m_axi_ddr_awready(m_axi_ddr_awready), - .m_axi_ddr_wdata(m_axi_ddr_wdata), - .m_axi_ddr_wstrb(m_axi_ddr_wstrb), - .m_axi_ddr_wlast(m_axi_ddr_wlast), - .m_axi_ddr_wvalid(m_axi_ddr_wvalid), - .m_axi_ddr_wready(m_axi_ddr_wready), - .m_axi_ddr_bid(m_axi_ddr_bid), - .m_axi_ddr_bresp(m_axi_ddr_bresp), - .m_axi_ddr_bvalid(m_axi_ddr_bvalid), - .m_axi_ddr_bready(m_axi_ddr_bready), - .m_axi_ddr_arid(m_axi_ddr_arid), - .m_axi_ddr_araddr(m_axi_ddr_araddr), - .m_axi_ddr_arlen(m_axi_ddr_arlen), - .m_axi_ddr_arsize(m_axi_ddr_arsize), - .m_axi_ddr_arburst(m_axi_ddr_arburst), - .m_axi_ddr_arlock(m_axi_ddr_arlock), - .m_axi_ddr_arcache(m_axi_ddr_arcache), - .m_axi_ddr_arprot(m_axi_ddr_arprot), - .m_axi_ddr_arqos(m_axi_ddr_arqos), - .m_axi_ddr_arvalid(m_axi_ddr_arvalid), - .m_axi_ddr_arready(m_axi_ddr_arready), - .m_axi_ddr_rid(m_axi_ddr_rid), - .m_axi_ddr_rdata(m_axi_ddr_rdata), - .m_axi_ddr_rresp(m_axi_ddr_rresp), - .m_axi_ddr_rlast(m_axi_ddr_rlast), - .m_axi_ddr_rvalid(m_axi_ddr_rvalid), - .m_axi_ddr_rready(m_axi_ddr_rready), - - .ddr_status(ddr_status), - - /* - * QSPI flash - */ - .fpga_boot(fpga_boot), - .qspi_clk(qspi_clk_int), - .qspi_dq_i(qspi_dq_i_int), - .qspi_dq_o(qspi_dq_o_int), - .qspi_dq_oe(qspi_dq_oe_int), - .qspi_cs(qspi_cs_int) -); - -endmodule - -`resetall diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v deleted file mode 100644 index 0822327b3..000000000 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v +++ /dev/null @@ -1,1663 +0,0 @@ -// SPDX-License-Identifier: BSD-2-Clause-Views -/* - * Copyright (c) 2019-2023 The Regents of the University of California - */ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA core logic - */ -module fpga_core # -( - // FW and board IDs - parameter FPGA_ID = 32'h4B31093, - parameter FW_ID = 32'h00000000, - parameter FW_VER = 32'h00_00_01_00, - parameter BOARD_ID = 32'h10ee_95f5, - parameter BOARD_VER = 32'h01_00_00_00, - parameter BUILD_DATE = 32'd602976000, - parameter GIT_HASH = 32'hdce357bf, - parameter RELEASE_INFO = 32'h00000000, - - // Board configuration - parameter TDMA_BER_ENABLE = 0, - - // Structural configuration - parameter IF_COUNT = 2, - parameter PORTS_PER_IF = 1, - parameter SCHED_PER_IF = PORTS_PER_IF, - parameter PORT_MASK = 0, - - // Clock configuration - parameter CLK_PERIOD_NS_NUM = 4, - parameter CLK_PERIOD_NS_DENOM = 1, - - // PTP configuration - parameter PTP_CLK_PERIOD_NS_NUM = 1024, - parameter PTP_CLK_PERIOD_NS_DENOM = 165, - parameter PTP_TS_WIDTH = 96, - parameter PTP_CLOCK_PIPELINE = 0, - parameter PTP_CLOCK_CDC_PIPELINE = 0, - parameter PTP_PORT_CDC_PIPELINE = 0, - parameter PTP_PEROUT_ENABLE = 0, - parameter PTP_PEROUT_COUNT = 1, - parameter IF_PTP_PERIOD_NS = 6'h6, - parameter IF_PTP_PERIOD_FNS = 16'h6666, - - // Queue manager configuration - parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, - parameter TX_QUEUE_OP_TABLE_SIZE = 32, - parameter RX_QUEUE_OP_TABLE_SIZE = 32, - parameter CQ_OP_TABLE_SIZE = 32, - parameter EQN_WIDTH = 5, - parameter TX_QUEUE_INDEX_WIDTH = 13, - parameter RX_QUEUE_INDEX_WIDTH = 8, - parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1, - parameter EQ_PIPELINE = 3, - parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), - parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), - parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0), - - // TX and RX engine configuration - parameter TX_DESC_TABLE_SIZE = 32, - parameter RX_DESC_TABLE_SIZE = 32, - parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, - - // Scheduler configuration - parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, - parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, - parameter TDMA_INDEX_WIDTH = 6, - - // Interface configuration - parameter PTP_TS_ENABLE = 1, - parameter TX_CPL_FIFO_DEPTH = 32, - parameter TX_TAG_WIDTH = 16, - parameter TX_CHECKSUM_ENABLE = 1, - parameter RX_HASH_ENABLE = 1, - parameter RX_CHECKSUM_ENABLE = 1, - parameter PFC_ENABLE = 1, - parameter LFC_ENABLE = PFC_ENABLE, - parameter ENABLE_PADDING = 1, - parameter ENABLE_DIC = 1, - parameter MIN_FRAME_LENGTH = 64, - parameter TX_FIFO_DEPTH = 32768, - parameter RX_FIFO_DEPTH = 32768, - parameter MAX_TX_SIZE = 9214, - parameter MAX_RX_SIZE = 9214, - parameter TX_RAM_SIZE = 32768, - parameter RX_RAM_SIZE = 32768, - - // RAM configuration - parameter DDR_CH = 4, - parameter DDR_ENABLE = 0, - parameter AXI_DDR_DATA_WIDTH = 512, - parameter AXI_DDR_ADDR_WIDTH = 34, - parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), - parameter AXI_DDR_ID_WIDTH = 8, - parameter AXI_DDR_MAX_BURST_LEN = 256, - parameter AXI_DDR_NARROW_BURST = 0, - - // Application block configuration - parameter APP_ID = 32'h00000000, - parameter APP_ENABLE = 0, - parameter APP_CTRL_ENABLE = 1, - parameter APP_DMA_ENABLE = 1, - parameter APP_AXIS_DIRECT_ENABLE = 1, - parameter APP_AXIS_SYNC_ENABLE = 1, - parameter APP_AXIS_IF_ENABLE = 1, - parameter APP_STAT_ENABLE = 1, - - // DMA interface configuration - parameter DMA_IMM_ENABLE = 0, - parameter DMA_IMM_WIDTH = 32, - parameter DMA_LEN_WIDTH = 16, - parameter DMA_TAG_WIDTH = 16, - parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), - parameter RAM_PIPELINE = 2, - - // PCIe interface configuration - parameter AXIS_PCIE_DATA_WIDTH = 512, - parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), - parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161, - parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137, - parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183, - parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81, - parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256, - parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, - parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6, - parameter PF_COUNT = 1, - parameter VF_COUNT = 0, - parameter PCIE_TAG_COUNT = 256, - - // Interrupt configuration - parameter IRQ_INDEX_WIDTH = EQN_WIDTH, - - // AXI lite interface configuration (control) - parameter AXIL_CTRL_DATA_WIDTH = 32, - parameter AXIL_CTRL_ADDR_WIDTH = 24, - - // AXI lite interface configuration (application control) - parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, - parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, - - // Ethernet interface configuration - parameter XGMII_DATA_WIDTH = 64, - parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8, - parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH, - parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, - parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*2, - parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1, - parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, - parameter AXIS_ETH_TX_PIPELINE = 4, - parameter AXIS_ETH_TX_FIFO_PIPELINE = 4, - parameter AXIS_ETH_TX_TS_PIPELINE = 4, - parameter AXIS_ETH_RX_PIPELINE = 4, - parameter AXIS_ETH_RX_FIFO_PIPELINE = 4, - - // Statistics counter subsystem - parameter STAT_ENABLE = 1, - parameter STAT_DMA_ENABLE = 1, - parameter STAT_PCIE_ENABLE = 1, - parameter STAT_INC_WIDTH = 24, - parameter STAT_ID_WIDTH = 12 -) -( - /* - * Clock: 250 MHz - * Synchronous reset - */ - input wire clk_250mhz, - input wire rst_250mhz, - - /* - * PTP clock - */ - input wire ptp_clk, - input wire ptp_rst, - input wire ptp_sample_clk, - - /* - * GPIO - */ - input wire [3:0] sw, - output wire [2:0] led, - - /* - * I2C - */ - input wire i2c_scl_i, - output wire i2c_scl_o, - output wire i2c_scl_t, - input wire i2c_sda_i, - output wire i2c_sda_o, - output wire i2c_sda_t, - - /* - * PCIe - */ - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, - output wire m_axis_rq_tlast, - input wire m_axis_rq_tready, - output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser, - output wire m_axis_rq_tvalid, - - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, - input wire s_axis_rc_tlast, - output wire s_axis_rc_tready, - input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser, - input wire s_axis_rc_tvalid, - - input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, - input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, - input wire s_axis_cq_tlast, - output wire s_axis_cq_tready, - input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser, - input wire s_axis_cq_tvalid, - - output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, - output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, - output wire m_axis_cc_tlast, - input wire m_axis_cc_tready, - output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser, - output wire m_axis_cc_tvalid, - - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0, - input wire s_axis_rq_seq_num_valid_0, - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1, - input wire s_axis_rq_seq_num_valid_1, - - input wire [1:0] pcie_tfc_nph_av, - input wire [1:0] pcie_tfc_npd_av, - - input wire [2:0] cfg_max_payload, - input wire [2:0] cfg_max_read_req, - input wire [3:0] cfg_rcb_status, - - output wire [9:0] cfg_mgmt_addr, - output wire [7:0] cfg_mgmt_function_number, - output wire cfg_mgmt_write, - output wire [31:0] cfg_mgmt_write_data, - output wire [3:0] cfg_mgmt_byte_enable, - output wire cfg_mgmt_read, - input wire [31:0] cfg_mgmt_read_data, - input wire cfg_mgmt_read_write_done, - - input wire [7:0] cfg_fc_ph, - input wire [11:0] cfg_fc_pd, - input wire [7:0] cfg_fc_nph, - input wire [11:0] cfg_fc_npd, - input wire [7:0] cfg_fc_cplh, - input wire [11:0] cfg_fc_cpld, - output wire [2:0] cfg_fc_sel, - - input wire [3:0] cfg_interrupt_msix_enable, - input wire [3:0] cfg_interrupt_msix_mask, - input wire [251:0] cfg_interrupt_msix_vf_enable, - input wire [251:0] cfg_interrupt_msix_vf_mask, - output wire [63:0] cfg_interrupt_msix_address, - output wire [31:0] cfg_interrupt_msix_data, - output wire cfg_interrupt_msix_int, - output wire [1:0] cfg_interrupt_msix_vec_pending, - input wire cfg_interrupt_msix_vec_pending_status, - input wire cfg_interrupt_msix_sent, - input wire cfg_interrupt_msix_fail, - output wire [7:0] cfg_interrupt_msi_function_number, - - output wire status_error_cor, - output wire status_error_uncor, - - /* - * Ethernet: QSFP28 - */ - input wire qsfp0_tx_clk_1, - input wire qsfp0_tx_rst_1, - output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1, - output wire qsfp0_cfg_tx_prbs31_enable_1, - input wire qsfp0_rx_clk_1, - input wire qsfp0_rx_rst_1, - input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1, - output wire qsfp0_cfg_rx_prbs31_enable_1, - input wire [6:0] qsfp0_rx_error_count_1, - input wire qsfp0_rx_status_1, - input wire qsfp0_tx_clk_2, - input wire qsfp0_tx_rst_2, - output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2, - output wire qsfp0_cfg_tx_prbs31_enable_2, - input wire qsfp0_rx_clk_2, - input wire qsfp0_rx_rst_2, - input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2, - output wire qsfp0_cfg_rx_prbs31_enable_2, - input wire [6:0] qsfp0_rx_error_count_2, - input wire qsfp0_rx_status_2, - input wire qsfp0_tx_clk_3, - input wire qsfp0_tx_rst_3, - output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3, - output wire qsfp0_cfg_tx_prbs31_enable_3, - input wire qsfp0_rx_clk_3, - input wire qsfp0_rx_rst_3, - input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3, - output wire qsfp0_cfg_rx_prbs31_enable_3, - input wire [6:0] qsfp0_rx_error_count_3, - input wire qsfp0_rx_status_3, - input wire qsfp0_tx_clk_4, - input wire qsfp0_tx_rst_4, - output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4, - output wire qsfp0_cfg_tx_prbs31_enable_4, - input wire qsfp0_rx_clk_4, - input wire qsfp0_rx_rst_4, - input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4, - output wire qsfp0_cfg_rx_prbs31_enable_4, - input wire [6:0] qsfp0_rx_error_count_4, - input wire qsfp0_rx_status_4, - - input wire qsfp0_drp_clk, - input wire qsfp0_drp_rst, - output wire [23:0] qsfp0_drp_addr, - output wire [15:0] qsfp0_drp_di, - output wire qsfp0_drp_en, - output wire qsfp0_drp_we, - input wire [15:0] qsfp0_drp_do, - input wire qsfp0_drp_rdy, - - output wire qsfp0_modsell, - output wire qsfp0_resetl, - input wire qsfp0_modprsl, - input wire qsfp0_intl, - output wire qsfp0_lpmode, - - input wire qsfp1_tx_clk_1, - input wire qsfp1_tx_rst_1, - output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1, - output wire qsfp1_cfg_tx_prbs31_enable_1, - input wire qsfp1_rx_clk_1, - input wire qsfp1_rx_rst_1, - input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1, - output wire qsfp1_cfg_rx_prbs31_enable_1, - input wire [6:0] qsfp1_rx_error_count_1, - input wire qsfp1_rx_status_1, - input wire qsfp1_tx_clk_2, - input wire qsfp1_tx_rst_2, - output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2, - output wire qsfp1_cfg_tx_prbs31_enable_2, - input wire qsfp1_rx_clk_2, - input wire qsfp1_rx_rst_2, - input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2, - output wire qsfp1_cfg_rx_prbs31_enable_2, - input wire [6:0] qsfp1_rx_error_count_2, - input wire qsfp1_rx_status_2, - input wire qsfp1_tx_clk_3, - input wire qsfp1_tx_rst_3, - output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3, - output wire qsfp1_cfg_tx_prbs31_enable_3, - input wire qsfp1_rx_clk_3, - input wire qsfp1_rx_rst_3, - input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3, - output wire qsfp1_cfg_rx_prbs31_enable_3, - input wire [6:0] qsfp1_rx_error_count_3, - input wire qsfp1_rx_status_3, - input wire qsfp1_tx_clk_4, - input wire qsfp1_tx_rst_4, - output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4, - output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4, - output wire qsfp1_cfg_tx_prbs31_enable_4, - input wire qsfp1_rx_clk_4, - input wire qsfp1_rx_rst_4, - input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4, - input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4, - output wire qsfp1_cfg_rx_prbs31_enable_4, - input wire [6:0] qsfp1_rx_error_count_4, - input wire qsfp1_rx_status_4, - - input wire qsfp1_drp_clk, - input wire qsfp1_drp_rst, - output wire [23:0] qsfp1_drp_addr, - output wire [15:0] qsfp1_drp_di, - output wire qsfp1_drp_en, - output wire qsfp1_drp_we, - input wire [15:0] qsfp1_drp_do, - input wire qsfp1_drp_rdy, - - output wire qsfp1_modsell, - output wire qsfp1_resetl, - input wire qsfp1_modprsl, - input wire qsfp1_intl, - output wire qsfp1_lpmode, - - /* - * DDR - */ - input wire [DDR_CH-1:0] ddr_clk, - input wire [DDR_CH-1:0] ddr_rst, - - output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, - output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, - output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, - output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, - output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, - output wire [DDR_CH-1:0] m_axi_ddr_awlock, - output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, - output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, - output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, - output wire [DDR_CH-1:0] m_axi_ddr_awvalid, - input wire [DDR_CH-1:0] m_axi_ddr_awready, - output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, - output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, - output wire [DDR_CH-1:0] m_axi_ddr_wlast, - output wire [DDR_CH-1:0] m_axi_ddr_wvalid, - input wire [DDR_CH-1:0] m_axi_ddr_wready, - input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, - input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, - input wire [DDR_CH-1:0] m_axi_ddr_bvalid, - output wire [DDR_CH-1:0] m_axi_ddr_bready, - output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, - output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, - output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, - output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, - output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, - output wire [DDR_CH-1:0] m_axi_ddr_arlock, - output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, - output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, - output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, - output wire [DDR_CH-1:0] m_axi_ddr_arvalid, - input wire [DDR_CH-1:0] m_axi_ddr_arready, - input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, - input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, - input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, - input wire [DDR_CH-1:0] m_axi_ddr_rlast, - input wire [DDR_CH-1:0] m_axi_ddr_rvalid, - output wire [DDR_CH-1:0] m_axi_ddr_rready, - - input wire [DDR_CH-1:0] ddr_status, - - /* - * QSPI flash - */ - output wire fpga_boot, - output wire qspi_clk, - input wire [3:0] qspi_dq_i, - output wire [3:0] qspi_dq_o, - output wire [3:0] qspi_dq_oe, - output wire qspi_cs -); - -parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; - -parameter F_COUNT = PF_COUNT+VF_COUNT; - -parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8); -parameter AXIL_IF_CTRL_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT); -parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8); - -localparam RB_BASE_ADDR = 16'h1000; -localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; - -localparam RB_DRP_QSFP0_BASE = RB_BASE_ADDR + 16'h40; -localparam RB_DRP_QSFP1_BASE = RB_DRP_QSFP0_BASE + 16'h20; - -initial begin - if (PORT_COUNT > 8) begin - $error("Error: Max port count exceeded (instance %m)"); - $finish; - end -end - -// AXI lite connections -wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_awaddr; -wire [2:0] axil_csr_awprot; -wire axil_csr_awvalid; -wire axil_csr_awready; -wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_wdata; -wire [AXIL_CTRL_STRB_WIDTH-1:0] axil_csr_wstrb; -wire axil_csr_wvalid; -wire axil_csr_wready; -wire [1:0] axil_csr_bresp; -wire axil_csr_bvalid; -wire axil_csr_bready; -wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_araddr; -wire [2:0] axil_csr_arprot; -wire axil_csr_arvalid; -wire axil_csr_arready; -wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_rdata; -wire [1:0] axil_csr_rresp; -wire axil_csr_rvalid; -wire axil_csr_rready; - -// PTP -wire [PTP_TS_WIDTH-1:0] ptp_ts_96; -wire ptp_ts_step; -wire ptp_pps; -wire ptp_pps_str; -wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; -wire ptp_sync_ts_step; -wire ptp_sync_pps; - -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; -wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse; - -// control registers -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_wr_addr; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_wr_data; -wire [AXIL_CTRL_STRB_WIDTH-1:0] ctrl_reg_wr_strb; -wire ctrl_reg_wr_en; -wire ctrl_reg_wr_wait; -wire ctrl_reg_wr_ack; -wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_rd_addr; -wire ctrl_reg_rd_en; -wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data; -wire ctrl_reg_rd_wait; -wire ctrl_reg_rd_ack; - -wire qsfp0_drp_reg_wr_wait; -wire qsfp0_drp_reg_wr_ack; -wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp0_drp_reg_rd_data; -wire qsfp0_drp_reg_rd_wait; -wire qsfp0_drp_reg_rd_ack; - -wire qsfp1_drp_reg_wr_wait; -wire qsfp1_drp_reg_wr_ack; -wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp1_drp_reg_rd_data; -wire qsfp1_drp_reg_rd_wait; -wire qsfp1_drp_reg_rd_ack; - -reg ctrl_reg_wr_ack_reg = 1'b0; -reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; -reg ctrl_reg_rd_ack_reg = 1'b0; - -reg qsfp0_reset_reg = 1'b0; -reg qsfp1_reset_reg = 1'b0; - -reg qsfp0_lpmode_reg = 1'b0; -reg qsfp1_lpmode_reg = 1'b0; - -reg i2c_scl_o_reg = 1'b1; -reg i2c_sda_o_reg = 1'b1; - -reg fpga_boot_reg = 1'b0; - -reg qspi_clk_reg = 1'b0; -reg qspi_cs_reg = 1'b1; -reg [3:0] qspi_dq_o_reg = 4'd0; -reg [3:0] qspi_dq_oe_reg = 4'd0; - -assign ctrl_reg_wr_wait = qsfp0_drp_reg_wr_wait | qsfp1_drp_reg_wr_wait; -assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp0_drp_reg_wr_ack | qsfp1_drp_reg_wr_ack; -assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp0_drp_reg_rd_data | qsfp1_drp_reg_rd_data; -assign ctrl_reg_rd_wait = qsfp0_drp_reg_rd_wait | qsfp1_drp_reg_rd_wait; -assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp0_drp_reg_rd_ack | qsfp1_drp_reg_rd_ack; - -assign qsfp0_modsell = 1'b0; -assign qsfp1_modsell = 1'b0; - -assign qsfp0_resetl = !qsfp0_reset_reg; -assign qsfp1_resetl = !qsfp1_reset_reg; - -assign qsfp0_lpmode = qsfp0_lpmode_reg; -assign qsfp1_lpmode = qsfp1_lpmode_reg; - -assign i2c_scl_o = i2c_scl_o_reg; -assign i2c_scl_t = i2c_scl_o_reg; -assign i2c_sda_o = i2c_sda_o_reg; -assign i2c_sda_t = i2c_sda_o_reg; - -assign fpga_boot = fpga_boot_reg; - -assign qspi_clk = qspi_clk_reg; -assign qspi_cs = qspi_cs_reg; -assign qspi_dq_o = qspi_dq_o_reg; -assign qspi_dq_oe = qspi_dq_oe_reg; - -always @(posedge clk_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; - ctrl_reg_rd_ack_reg <= 1'b0; - - if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin - // write operation - ctrl_reg_wr_ack_reg <= 1'b0; - case ({ctrl_reg_wr_addr >> 2, 2'b00}) - // FW ID - 8'h0C: begin - // FW ID: FPGA JTAG ID - fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD; - end - // I2C 0 - RBB+8'h0C: begin - // I2C ctrl: control - if (ctrl_reg_wr_strb[0]) begin - i2c_scl_o_reg <= ctrl_reg_wr_data[1]; - end - if (ctrl_reg_wr_strb[1]) begin - i2c_sda_o_reg <= ctrl_reg_wr_data[9]; - end - end - // XCVR GPIO - RBB+8'h1C: begin - // XCVR GPIO: control 0123 - if (ctrl_reg_wr_strb[0]) begin - qsfp0_reset_reg <= ctrl_reg_wr_data[4]; - qsfp0_lpmode_reg <= ctrl_reg_wr_data[5]; - end - if (ctrl_reg_wr_strb[1]) begin - qsfp1_reset_reg <= ctrl_reg_wr_data[12]; - qsfp1_lpmode_reg <= ctrl_reg_wr_data[13]; - end - end - // QSPI flash - RBB+8'h2C: begin - // SPI flash ctrl: format - fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD; - end - RBB+8'h30: begin - // SPI flash ctrl: control 0 - if (ctrl_reg_wr_strb[0]) begin - qspi_dq_o_reg <= ctrl_reg_wr_data[3:0]; - end - if (ctrl_reg_wr_strb[1]) begin - qspi_dq_oe_reg <= ctrl_reg_wr_data[11:8]; - end - if (ctrl_reg_wr_strb[2]) begin - qspi_clk_reg <= ctrl_reg_wr_data[16]; - qspi_cs_reg <= ctrl_reg_wr_data[17]; - end - end - default: ctrl_reg_wr_ack_reg <= 1'b0; - endcase - end - - if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin - // read operation - ctrl_reg_rd_ack_reg <= 1'b1; - case ({ctrl_reg_rd_addr >> 2, 2'b00}) - // I2C 0 - RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type - RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version - RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // I2C ctrl: Next header - RBB+8'h0C: begin - // I2C ctrl: control - ctrl_reg_rd_data_reg[0] <= i2c_scl_i; - ctrl_reg_rd_data_reg[1] <= i2c_scl_o_reg; - ctrl_reg_rd_data_reg[8] <= i2c_sda_i; - ctrl_reg_rd_data_reg[9] <= i2c_sda_o_reg; - end - // XCVR GPIO - RBB+8'h10: ctrl_reg_rd_data_reg <= 32'h0000C101; // XCVR GPIO: Type - RBB+8'h14: ctrl_reg_rd_data_reg <= 32'h00000100; // XCVR GPIO: Version - RBB+8'h18: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // XCVR GPIO: Next header - RBB+8'h1C: begin - // XCVR GPIO: control 0123 - ctrl_reg_rd_data_reg[0] <= !qsfp0_modprsl; - ctrl_reg_rd_data_reg[1] <= !qsfp0_intl; - ctrl_reg_rd_data_reg[4] <= qsfp0_reset_reg; - ctrl_reg_rd_data_reg[5] <= qsfp0_lpmode_reg; - ctrl_reg_rd_data_reg[8] <= !qsfp1_modprsl; - ctrl_reg_rd_data_reg[9] <= !qsfp1_intl; - ctrl_reg_rd_data_reg[12] <= qsfp1_reset_reg; - ctrl_reg_rd_data_reg[13] <= qsfp1_lpmode_reg; - end - // QSPI flash - RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type - RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version - RBB+8'h28: ctrl_reg_rd_data_reg <= RB_DRP_QSFP0_BASE; // SPI flash ctrl: Next header - RBB+8'h2C: begin - // SPI flash ctrl: format - ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments) - ctrl_reg_rd_data_reg[7:4] <= 1; // default segment - ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment - ctrl_reg_rd_data_reg[31:12] <= 32'h00000000 >> 12; // first segment size (even split) - end - RBB+8'h30: begin - // SPI flash ctrl: control 0 - ctrl_reg_rd_data_reg[3:0] <= qspi_dq_i; - ctrl_reg_rd_data_reg[11:8] <= qspi_dq_oe; - ctrl_reg_rd_data_reg[16] <= qspi_clk; - ctrl_reg_rd_data_reg[17] <= qspi_cs; - end - default: ctrl_reg_rd_ack_reg <= 1'b0; - endcase - end - - if (rst_250mhz) begin - ctrl_reg_wr_ack_reg <= 1'b0; - ctrl_reg_rd_ack_reg <= 1'b0; - - qsfp0_reset_reg <= 1'b0; - qsfp1_reset_reg <= 1'b0; - - qsfp0_lpmode_reg <= 1'b0; - qsfp1_lpmode_reg <= 1'b0; - - i2c_scl_o_reg <= 1'b1; - i2c_sda_o_reg <= 1'b1; - - fpga_boot_reg <= 1'b0; - - qspi_clk_reg <= 1'b0; - qspi_cs_reg <= 1'b1; - qspi_dq_o_reg <= 4'd0; - qspi_dq_oe_reg <= 4'd0; - end -end - -rb_drp #( - .DRP_ADDR_WIDTH(24), - .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}), - .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .RB_BASE_ADDR(RB_DRP_QSFP0_BASE), - .RB_NEXT_PTR(RB_DRP_QSFP1_BASE) -) -qsfp0_rb_drp_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * Register interface - */ - .reg_wr_addr(ctrl_reg_wr_addr), - .reg_wr_data(ctrl_reg_wr_data), - .reg_wr_strb(ctrl_reg_wr_strb), - .reg_wr_en(ctrl_reg_wr_en), - .reg_wr_wait(qsfp0_drp_reg_wr_wait), - .reg_wr_ack(qsfp0_drp_reg_wr_ack), - .reg_rd_addr(ctrl_reg_rd_addr), - .reg_rd_en(ctrl_reg_rd_en), - .reg_rd_data(qsfp0_drp_reg_rd_data), - .reg_rd_wait(qsfp0_drp_reg_rd_wait), - .reg_rd_ack(qsfp0_drp_reg_rd_ack), - - /* - * DRP - */ - .drp_clk(qsfp0_drp_clk), - .drp_rst(qsfp0_drp_rst), - .drp_addr(qsfp0_drp_addr), - .drp_di(qsfp0_drp_di), - .drp_en(qsfp0_drp_en), - .drp_we(qsfp0_drp_we), - .drp_do(qsfp0_drp_do), - .drp_rdy(qsfp0_drp_rdy) -); - -rb_drp #( - .DRP_ADDR_WIDTH(24), - .DRP_DATA_WIDTH(16), - .DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}), - .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .RB_BASE_ADDR(RB_DRP_QSFP1_BASE), - .RB_NEXT_PTR(0) -) -qsfp1_rb_drp_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * Register interface - */ - .reg_wr_addr(ctrl_reg_wr_addr), - .reg_wr_data(ctrl_reg_wr_data), - .reg_wr_strb(ctrl_reg_wr_strb), - .reg_wr_en(ctrl_reg_wr_en), - .reg_wr_wait(qsfp1_drp_reg_wr_wait), - .reg_wr_ack(qsfp1_drp_reg_wr_ack), - .reg_rd_addr(ctrl_reg_rd_addr), - .reg_rd_en(ctrl_reg_rd_en), - .reg_rd_data(qsfp1_drp_reg_rd_data), - .reg_rd_wait(qsfp1_drp_reg_rd_wait), - .reg_rd_ack(qsfp1_drp_reg_rd_ack), - - /* - * DRP - */ - .drp_clk(qsfp1_drp_clk), - .drp_rst(qsfp1_drp_rst), - .drp_addr(qsfp1_drp_addr), - .drp_di(qsfp1_drp_di), - .drp_en(qsfp1_drp_en), - .drp_we(qsfp1_drp_we), - .drp_do(qsfp1_drp_do), - .drp_rdy(qsfp1_drp_rdy) -); - -generate - -if (TDMA_BER_ENABLE) begin - - // BER tester - tdma_ber #( - .COUNT(8), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(8)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000), - .PHY_PIPELINE(2) - ) - tdma_ber_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - .phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), - .phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), - .phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}), - .phy_cfg_tx_prbs31_enable({qsfp1_cfg_tx_prbs31_enable_4, qsfp1_cfg_tx_prbs31_enable_3, qsfp1_cfg_tx_prbs31_enable_2, qsfp1_cfg_tx_prbs31_enable_1, qsfp0_cfg_tx_prbs31_enable_4, qsfp0_cfg_tx_prbs31_enable_3, qsfp0_cfg_tx_prbs31_enable_2, qsfp0_cfg_tx_prbs31_enable_1}), - .phy_cfg_rx_prbs31_enable({qsfp1_cfg_rx_prbs31_enable_4, qsfp1_cfg_rx_prbs31_enable_3, qsfp1_cfg_rx_prbs31_enable_2, qsfp1_cfg_rx_prbs31_enable_1, qsfp0_cfg_rx_prbs31_enable_4, qsfp0_cfg_rx_prbs31_enable_3, qsfp0_cfg_rx_prbs31_enable_2, qsfp0_cfg_rx_prbs31_enable_1}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) - ); - -end else begin - - assign qsfp0_cfg_tx_prbs31_enable_1 = 1'b0; - assign qsfp0_cfg_rx_prbs31_enable_1 = 1'b0; - assign qsfp0_cfg_tx_prbs31_enable_2 = 1'b0; - assign qsfp0_cfg_rx_prbs31_enable_2 = 1'b0; - assign qsfp0_cfg_tx_prbs31_enable_3 = 1'b0; - assign qsfp0_cfg_rx_prbs31_enable_3 = 1'b0; - assign qsfp0_cfg_tx_prbs31_enable_4 = 1'b0; - assign qsfp0_cfg_rx_prbs31_enable_4 = 1'b0; - assign qsfp1_cfg_tx_prbs31_enable_1 = 1'b0; - assign qsfp1_cfg_rx_prbs31_enable_1 = 1'b0; - assign qsfp1_cfg_tx_prbs31_enable_2 = 1'b0; - assign qsfp1_cfg_rx_prbs31_enable_2 = 1'b0; - assign qsfp1_cfg_tx_prbs31_enable_3 = 1'b0; - assign qsfp1_cfg_rx_prbs31_enable_3 = 1'b0; - assign qsfp1_cfg_tx_prbs31_enable_4 = 1'b0; - assign qsfp1_cfg_rx_prbs31_enable_4 = 1'b0; - -end - -endgenerate - -assign led[0] = ptp_pps_str; -assign led[2:1] = 0; - -wire [PORT_COUNT-1:0] eth_tx_clk; -wire [PORT_COUNT-1:0] eth_tx_rst; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_tx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_tx_tready; -wire [PORT_COUNT-1:0] axis_eth_tx_tlast; -wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts; -wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; -wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; - -wire [PORT_COUNT-1:0] eth_tx_enable; -wire [PORT_COUNT-1:0] eth_tx_status; -wire [PORT_COUNT-1:0] eth_tx_lfc_en; -wire [PORT_COUNT-1:0] eth_tx_lfc_req; -wire [PORT_COUNT*8-1:0] eth_tx_pfc_en; -wire [PORT_COUNT*8-1:0] eth_tx_pfc_req; - -wire [PORT_COUNT-1:0] eth_rx_clk; -wire [PORT_COUNT-1:0] eth_rx_rst; - -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; -wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; - -wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; -wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; -wire [PORT_COUNT-1:0] axis_eth_rx_tvalid; -wire [PORT_COUNT-1:0] axis_eth_rx_tready; -wire [PORT_COUNT-1:0] axis_eth_rx_tlast; -wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; - -wire [PORT_COUNT-1:0] eth_rx_enable; -wire [PORT_COUNT-1:0] eth_rx_status; -wire [PORT_COUNT-1:0] eth_rx_lfc_en; -wire [PORT_COUNT-1:0] eth_rx_lfc_req; -wire [PORT_COUNT-1:0] eth_rx_lfc_ack; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_en; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_req; -wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack; - -wire [PORT_COUNT-1:0] port_xgmii_tx_clk; -wire [PORT_COUNT-1:0] port_xgmii_tx_rst; -wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_txd; -wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_txc; - -wire [PORT_COUNT-1:0] port_xgmii_rx_clk; -wire [PORT_COUNT-1:0] port_xgmii_rx_rst; -wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_rxd; -wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_rxc; - -mqnic_port_map_phy_xgmii #( - .PHY_COUNT(8), - .PORT_MASK(PORT_MASK), - .PORT_GROUP_SIZE(4), - - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - - .PORT_COUNT(PORT_COUNT), - - .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), - .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH) -) -mqnic_port_map_phy_xgmii_inst ( - // towards PHY - .phy_xgmii_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), - .phy_xgmii_tx_rst({qsfp1_tx_rst_4, qsfp1_tx_rst_3, qsfp1_tx_rst_2, qsfp1_tx_rst_1, qsfp0_tx_rst_4, qsfp0_tx_rst_3, qsfp0_tx_rst_2, qsfp0_tx_rst_1}), - .phy_xgmii_txd({qsfp1_txd_4, qsfp1_txd_3, qsfp1_txd_2, qsfp1_txd_1, qsfp0_txd_4, qsfp0_txd_3, qsfp0_txd_2, qsfp0_txd_1}), - .phy_xgmii_txc({qsfp1_txc_4, qsfp1_txc_3, qsfp1_txc_2, qsfp1_txc_1, qsfp0_txc_4, qsfp0_txc_3, qsfp0_txc_2, qsfp0_txc_1}), - .phy_tx_status(8'hff), - - .phy_xgmii_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), - .phy_xgmii_rx_rst({qsfp1_rx_rst_4, qsfp1_rx_rst_3, qsfp1_rx_rst_2, qsfp1_rx_rst_1, qsfp0_rx_rst_4, qsfp0_rx_rst_3, qsfp0_rx_rst_2, qsfp0_rx_rst_1}), - .phy_xgmii_rxd({qsfp1_rxd_4, qsfp1_rxd_3, qsfp1_rxd_2, qsfp1_rxd_1, qsfp0_rxd_4, qsfp0_rxd_3, qsfp0_rxd_2, qsfp0_rxd_1}), - .phy_xgmii_rxc({qsfp1_rxc_4, qsfp1_rxc_3, qsfp1_rxc_2, qsfp1_rxc_1, qsfp0_rxc_4, qsfp0_rxc_3, qsfp0_rxc_2, qsfp0_rxc_1}), - .phy_rx_status({qsfp1_rx_status_4, qsfp1_rx_status_3, qsfp1_rx_status_2, qsfp1_rx_status_1, qsfp0_rx_status_4, qsfp0_rx_status_3, qsfp0_rx_status_2, qsfp0_rx_status_1}), - - // towards MAC - .port_xgmii_tx_clk(port_xgmii_tx_clk), - .port_xgmii_tx_rst(port_xgmii_tx_rst), - .port_xgmii_txd(port_xgmii_txd), - .port_xgmii_txc(port_xgmii_txc), - .port_tx_status(eth_tx_status), - - .port_xgmii_rx_clk(port_xgmii_rx_clk), - .port_xgmii_rx_rst(port_xgmii_rx_rst), - .port_xgmii_rxd(port_xgmii_rxd), - .port_xgmii_rxc(port_xgmii_rxc), - .port_rx_status(eth_rx_status) -); - -generate - genvar n; - - for (n = 0; n < PORT_COUNT; n = n + 1) begin : mac - - assign eth_tx_clk[n] = port_xgmii_tx_clk[n]; - assign eth_tx_rst[n] = port_xgmii_tx_rst[n]; - assign eth_rx_clk[n] = port_xgmii_rx_clk[n]; - assign eth_rx_rst[n] = port_xgmii_rx_rst[n]; - - eth_mac_10g #( - .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .ENABLE_PADDING(ENABLE_PADDING), - .ENABLE_DIC(ENABLE_DIC), - .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), - .PTP_PERIOD_NS(IF_PTP_PERIOD_NS), - .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS), - .TX_PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_PTP_TS_WIDTH(PTP_TS_WIDTH), - .TX_PTP_TS_CTRL_IN_TUSER(0), - .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE), - .TX_PTP_TAG_WIDTH(TX_TAG_WIDTH), - .RX_PTP_TS_ENABLE(PTP_TS_ENABLE), - .RX_PTP_TS_WIDTH(PTP_TS_WIDTH), - .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .PFC_ENABLE(PFC_ENABLE), - .PAUSE_ENABLE(LFC_ENABLE) - ) - eth_mac_inst ( - .tx_clk(port_xgmii_tx_clk[n]), - .tx_rst(port_xgmii_tx_rst[n]), - .rx_clk(port_xgmii_rx_clk[n]), - .rx_rst(port_xgmii_rx_rst[n]), - - /* - * AXI input - */ - .tx_axis_tdata(axis_eth_tx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), - .tx_axis_tkeep(axis_eth_tx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), - .tx_axis_tvalid(axis_eth_tx_tvalid[n +: 1]), - .tx_axis_tready(axis_eth_tx_tready[n +: 1]), - .tx_axis_tlast(axis_eth_tx_tlast[n +: 1]), - .tx_axis_tuser(axis_eth_tx_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]), - - /* - * AXI output - */ - .rx_axis_tdata(axis_eth_rx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), - .rx_axis_tkeep(axis_eth_rx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), - .rx_axis_tvalid(axis_eth_rx_tvalid[n +: 1]), - .rx_axis_tlast(axis_eth_rx_tlast[n +: 1]), - .rx_axis_tuser(axis_eth_rx_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]), - - /* - * XGMII interface - */ - .xgmii_rxd(port_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), - .xgmii_rxc(port_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), - .xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), - .xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), - - /* - * PTP - */ - .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), - .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), - - /* - * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) - */ - .tx_lfc_req(eth_tx_lfc_req[n +: 1]), - .tx_lfc_resend(1'b0), - .rx_lfc_en(eth_rx_lfc_en[n +: 1]), - .rx_lfc_req(eth_rx_lfc_req[n +: 1]), - .rx_lfc_ack(eth_rx_lfc_ack[n +: 1]), - - /* - * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC) - */ - .tx_pfc_req(eth_tx_pfc_req[n*8 +: 8]), - .tx_pfc_resend(1'b0), - .rx_pfc_en(eth_rx_pfc_en[n*8 +: 8]), - .rx_pfc_req(eth_rx_pfc_req[n*8 +: 8]), - .rx_pfc_ack(eth_rx_pfc_ack[n*8 +: 8]), - - /* - * Pause interface - */ - .tx_lfc_pause_en(1'b1), - .tx_pause_req(1'b0), - .tx_pause_ack(), - - /* - * Status - */ - .tx_start_packet(), - .tx_error_underflow(), - .rx_start_packet(), - .rx_error_bad_frame(), - .rx_error_bad_fcs(), - .stat_tx_mcf(), - .stat_rx_mcf(), - .stat_tx_lfc_pkt(), - .stat_tx_lfc_xon(), - .stat_tx_lfc_xoff(), - .stat_tx_lfc_paused(), - .stat_tx_pfc_pkt(), - .stat_tx_pfc_xon(), - .stat_tx_pfc_xoff(), - .stat_tx_pfc_paused(), - .stat_rx_lfc_pkt(), - .stat_rx_lfc_xon(), - .stat_rx_lfc_xoff(), - .stat_rx_lfc_paused(), - .stat_rx_pfc_pkt(), - .stat_rx_pfc_xon(), - .stat_rx_pfc_xoff(), - .stat_rx_pfc_paused(), - - /* - * Configuration - */ - .cfg_ifg(8'd12), - .cfg_tx_enable(eth_tx_enable[n +: 1]), - .cfg_rx_enable(eth_rx_enable[n +: 1]), - .cfg_mcf_rx_eth_dst_mcast(48'h01_80_C2_00_00_01), - .cfg_mcf_rx_check_eth_dst_mcast(1'b1), - .cfg_mcf_rx_eth_dst_ucast(48'd0), - .cfg_mcf_rx_check_eth_dst_ucast(1'b0), - .cfg_mcf_rx_eth_src(48'd0), - .cfg_mcf_rx_check_eth_src(1'b0), - .cfg_mcf_rx_eth_type(16'h8808), - .cfg_mcf_rx_opcode_lfc(16'h0001), - .cfg_mcf_rx_check_opcode_lfc(eth_rx_lfc_en[n +: 1]), - .cfg_mcf_rx_opcode_pfc(16'h0101), - .cfg_mcf_rx_check_opcode_pfc(eth_rx_pfc_en[n*8 +: 8] != 0), - .cfg_mcf_rx_forward(1'b0), - .cfg_mcf_rx_enable(eth_rx_lfc_en[n +: 1] || eth_rx_pfc_en[n*8 +: 8]), - .cfg_tx_lfc_eth_dst(48'h01_80_C2_00_00_01), - .cfg_tx_lfc_eth_src(48'h80_23_31_43_54_4C), - .cfg_tx_lfc_eth_type(16'h8808), - .cfg_tx_lfc_opcode(16'h0001), - .cfg_tx_lfc_en(eth_tx_lfc_en[n +: 1]), - .cfg_tx_lfc_quanta(16'hffff), - .cfg_tx_lfc_refresh(16'h7fff), - .cfg_tx_pfc_eth_dst(48'h01_80_C2_00_00_01), - .cfg_tx_pfc_eth_src(48'h80_23_31_43_54_4C), - .cfg_tx_pfc_eth_type(16'h8808), - .cfg_tx_pfc_opcode(16'h0101), - .cfg_tx_pfc_en(eth_tx_pfc_en[n*8 +: 8] != 0), - .cfg_tx_pfc_quanta({8{16'hffff}}), - .cfg_tx_pfc_refresh({8{16'h7fff}}), - .cfg_rx_lfc_opcode(16'h0001), - .cfg_rx_lfc_en(eth_rx_lfc_en[n +: 1]), - .cfg_rx_pfc_opcode(16'h0101), - .cfg_rx_pfc_en(eth_rx_pfc_en[n*8 +: 8] != 0) - ); - - end - -endgenerate - -mqnic_core_pcie_us #( - // FW and board IDs - .FPGA_ID(FPGA_ID), - .FW_ID(FW_ID), - .FW_VER(FW_VER), - .BOARD_ID(BOARD_ID), - .BOARD_VER(BOARD_VER), - .BUILD_DATE(BUILD_DATE), - .GIT_HASH(GIT_HASH), - .RELEASE_INFO(RELEASE_INFO), - - // Structural configuration - .IF_COUNT(IF_COUNT), - .PORTS_PER_IF(PORTS_PER_IF), - .SCHED_PER_IF(SCHED_PER_IF), - - .PORT_COUNT(PORT_COUNT), - - // Clock configuration - .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), - .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), - - // PTP configuration - .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), - .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), - .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), - .PTP_SEPARATE_TX_CLOCK(0), - .PTP_SEPARATE_RX_CLOCK(0), - .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), - .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), - .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), - - // Queue manager configuration - .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), - .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), - .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), - .CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE), - .EQN_WIDTH(EQN_WIDTH), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .CQN_WIDTH(CQN_WIDTH), - .EQ_PIPELINE(EQ_PIPELINE), - .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), - .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), - .CQ_PIPELINE(CQ_PIPELINE), - - // TX and RX engine configuration - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), - - // Scheduler configuration - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - - // Interface configuration - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_CPL_ENABLE(PTP_TS_ENABLE), - .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), - .TX_TAG_WIDTH(TX_TAG_WIDTH), - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .PFC_ENABLE(PFC_ENABLE), - .LFC_ENABLE(LFC_ENABLE), - .MAC_CTRL_ENABLE(0), - .TX_FIFO_DEPTH(TX_FIFO_DEPTH), - .RX_FIFO_DEPTH(RX_FIFO_DEPTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - - // RAM configuration - .DDR_CH(DDR_CH), - .DDR_ENABLE(DDR_ENABLE), - .DDR_GROUP_SIZE(1), - .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), - .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), - .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), - .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), - .AXI_DDR_AWUSER_ENABLE(0), - .AXI_DDR_WUSER_ENABLE(0), - .AXI_DDR_BUSER_ENABLE(0), - .AXI_DDR_ARUSER_ENABLE(0), - .AXI_DDR_RUSER_ENABLE(0), - .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), - .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), - .AXI_DDR_FIXED_BURST(0), - .AXI_DDR_WRAP_BURST(1), - .HBM_ENABLE(0), - - // Application block configuration - .APP_ID(APP_ID), - .APP_ENABLE(APP_ENABLE), - .APP_CTRL_ENABLE(APP_CTRL_ENABLE), - .APP_DMA_ENABLE(APP_DMA_ENABLE), - .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), - .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), - .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), - .APP_STAT_ENABLE(APP_STAT_ENABLE), - .APP_GPIO_IN_WIDTH(32), - .APP_GPIO_OUT_WIDTH(32), - - // DMA interface configuration - .DMA_IMM_ENABLE(DMA_IMM_ENABLE), - .DMA_IMM_WIDTH(DMA_IMM_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - - // PCIe interface configuration - .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), - .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), - .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), - .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), - .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), - .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), - .RC_STRADDLE(RC_STRADDLE), - .RQ_STRADDLE(RQ_STRADDLE), - .CQ_STRADDLE(CQ_STRADDLE), - .CC_STRADDLE(CC_STRADDLE), - .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), - .PF_COUNT(PF_COUNT), - .VF_COUNT(VF_COUNT), - .F_COUNT(F_COUNT), - .PCIE_TAG_COUNT(PCIE_TAG_COUNT), - - // Interrupt configuration - .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), - - // AXI lite interface configuration (control) - .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), - .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), - .RB_NEXT_PTR(RB_BASE_ADDR), - - // AXI lite interface configuration (application control) - .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), - .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), - - // Ethernet interface configuration - .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), - .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), - .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), - .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), - .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), - .AXIS_ETH_RX_USE_READY(0), - .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), - .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), - .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), - .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), - .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), - - // Statistics counter subsystem - .STAT_ENABLE(STAT_ENABLE), - .STAT_DMA_ENABLE(STAT_DMA_ENABLE), - .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), - .STAT_INC_WIDTH(STAT_INC_WIDTH), - .STAT_ID_WIDTH(STAT_ID_WIDTH) -) -core_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - - /* - * AXI input (RC) - */ - .s_axis_rc_tdata(s_axis_rc_tdata), - .s_axis_rc_tkeep(s_axis_rc_tkeep), - .s_axis_rc_tvalid(s_axis_rc_tvalid), - .s_axis_rc_tready(s_axis_rc_tready), - .s_axis_rc_tlast(s_axis_rc_tlast), - .s_axis_rc_tuser(s_axis_rc_tuser), - - /* - * AXI output (RQ) - */ - .m_axis_rq_tdata(m_axis_rq_tdata), - .m_axis_rq_tkeep(m_axis_rq_tkeep), - .m_axis_rq_tvalid(m_axis_rq_tvalid), - .m_axis_rq_tready(m_axis_rq_tready), - .m_axis_rq_tlast(m_axis_rq_tlast), - .m_axis_rq_tuser(m_axis_rq_tuser), - - /* - * AXI input (CQ) - */ - .s_axis_cq_tdata(s_axis_cq_tdata), - .s_axis_cq_tkeep(s_axis_cq_tkeep), - .s_axis_cq_tvalid(s_axis_cq_tvalid), - .s_axis_cq_tready(s_axis_cq_tready), - .s_axis_cq_tlast(s_axis_cq_tlast), - .s_axis_cq_tuser(s_axis_cq_tuser), - - /* - * AXI output (CC) - */ - .m_axis_cc_tdata(m_axis_cc_tdata), - .m_axis_cc_tkeep(m_axis_cc_tkeep), - .m_axis_cc_tvalid(m_axis_cc_tvalid), - .m_axis_cc_tready(m_axis_cc_tready), - .m_axis_cc_tlast(m_axis_cc_tlast), - .m_axis_cc_tuser(m_axis_cc_tuser), - - /* - * Transmit sequence number input - */ - .s_axis_rq_seq_num_0(s_axis_rq_seq_num_0), - .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), - .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), - .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), - - /* - * Flow control - */ - .cfg_fc_ph(cfg_fc_ph), - .cfg_fc_pd(cfg_fc_pd), - .cfg_fc_nph(cfg_fc_nph), - .cfg_fc_npd(cfg_fc_npd), - .cfg_fc_cplh(cfg_fc_cplh), - .cfg_fc_cpld(cfg_fc_cpld), - .cfg_fc_sel(cfg_fc_sel), - - /* - * Configuration inputs - */ - .cfg_max_read_req(cfg_max_read_req), - .cfg_max_payload(cfg_max_payload), - .cfg_rcb_status(cfg_rcb_status), - - /* - * Configuration interface - */ - .cfg_mgmt_addr(cfg_mgmt_addr), - .cfg_mgmt_function_number(cfg_mgmt_function_number), - .cfg_mgmt_write(cfg_mgmt_write), - .cfg_mgmt_write_data(cfg_mgmt_write_data), - .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), - .cfg_mgmt_read(cfg_mgmt_read), - .cfg_mgmt_read_data(cfg_mgmt_read_data), - .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), - - /* - * Interrupt interface - */ - .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), - .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), - .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), - .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), - .cfg_interrupt_msix_address(cfg_interrupt_msix_address), - .cfg_interrupt_msix_data(cfg_interrupt_msix_data), - .cfg_interrupt_msix_int(cfg_interrupt_msix_int), - .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), - .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), - .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), - .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), - .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), - - /* - * PCIe error outputs - */ - .status_error_cor(status_error_cor), - .status_error_uncor(status_error_uncor), - - /* - * AXI-Lite master interface (passthrough for NIC control and status) - */ - .m_axil_csr_awaddr(axil_csr_awaddr), - .m_axil_csr_awprot(axil_csr_awprot), - .m_axil_csr_awvalid(axil_csr_awvalid), - .m_axil_csr_awready(axil_csr_awready), - .m_axil_csr_wdata(axil_csr_wdata), - .m_axil_csr_wstrb(axil_csr_wstrb), - .m_axil_csr_wvalid(axil_csr_wvalid), - .m_axil_csr_wready(axil_csr_wready), - .m_axil_csr_bresp(axil_csr_bresp), - .m_axil_csr_bvalid(axil_csr_bvalid), - .m_axil_csr_bready(axil_csr_bready), - .m_axil_csr_araddr(axil_csr_araddr), - .m_axil_csr_arprot(axil_csr_arprot), - .m_axil_csr_arvalid(axil_csr_arvalid), - .m_axil_csr_arready(axil_csr_arready), - .m_axil_csr_rdata(axil_csr_rdata), - .m_axil_csr_rresp(axil_csr_rresp), - .m_axil_csr_rvalid(axil_csr_rvalid), - .m_axil_csr_rready(axil_csr_rready), - - /* - * Control register interface - */ - .ctrl_reg_wr_addr(ctrl_reg_wr_addr), - .ctrl_reg_wr_data(ctrl_reg_wr_data), - .ctrl_reg_wr_strb(ctrl_reg_wr_strb), - .ctrl_reg_wr_en(ctrl_reg_wr_en), - .ctrl_reg_wr_wait(ctrl_reg_wr_wait), - .ctrl_reg_wr_ack(ctrl_reg_wr_ack), - .ctrl_reg_rd_addr(ctrl_reg_rd_addr), - .ctrl_reg_rd_en(ctrl_reg_rd_en), - .ctrl_reg_rd_data(ctrl_reg_rd_data), - .ctrl_reg_rd_wait(ctrl_reg_rd_wait), - .ctrl_reg_rd_ack(ctrl_reg_rd_ack), - - /* - * PTP clock - */ - .ptp_clk(ptp_clk), - .ptp_rst(ptp_rst), - .ptp_sample_clk(ptp_sample_clk), - .ptp_pps(ptp_pps), - .ptp_pps_str(ptp_pps_str), - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), - .ptp_sync_pps(ptp_sync_pps), - .ptp_sync_ts_96(ptp_sync_ts_96), - .ptp_sync_ts_step(ptp_sync_ts_step), - .ptp_perout_locked(ptp_perout_locked), - .ptp_perout_error(ptp_perout_error), - .ptp_perout_pulse(ptp_perout_pulse), - - /* - * Ethernet - */ - .eth_tx_clk(eth_tx_clk), - .eth_tx_rst(eth_tx_rst), - - .eth_tx_ptp_clk(0), - .eth_tx_ptp_rst(0), - .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), - .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), - - .m_axis_eth_tx_tdata(axis_eth_tx_tdata), - .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), - .m_axis_eth_tx_tvalid(axis_eth_tx_tvalid), - .m_axis_eth_tx_tready(axis_eth_tx_tready), - .m_axis_eth_tx_tlast(axis_eth_tx_tlast), - .m_axis_eth_tx_tuser(axis_eth_tx_tuser), - - .s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts), - .s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag), - .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), - .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), - - .eth_tx_enable(eth_tx_enable), - .eth_tx_status(eth_tx_status), - .eth_tx_lfc_en(eth_tx_lfc_en), - .eth_tx_lfc_req(eth_tx_lfc_req), - .eth_tx_pfc_en(eth_tx_pfc_en), - .eth_tx_pfc_req(eth_tx_pfc_req), - .eth_tx_fc_quanta_clk_en(0), - - .eth_rx_clk(eth_rx_clk), - .eth_rx_rst(eth_rx_rst), - - .eth_rx_ptp_clk(0), - .eth_rx_ptp_rst(0), - .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), - .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), - - .s_axis_eth_rx_tdata(axis_eth_rx_tdata), - .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), - .s_axis_eth_rx_tvalid(axis_eth_rx_tvalid), - .s_axis_eth_rx_tready(axis_eth_rx_tready), - .s_axis_eth_rx_tlast(axis_eth_rx_tlast), - .s_axis_eth_rx_tuser(axis_eth_rx_tuser), - - .eth_rx_enable(eth_rx_enable), - .eth_rx_status(eth_rx_status), - .eth_rx_lfc_en(eth_rx_lfc_en), - .eth_rx_lfc_req(eth_rx_lfc_req), - .eth_rx_lfc_ack(eth_rx_lfc_ack), - .eth_rx_pfc_en(eth_rx_pfc_en), - .eth_rx_pfc_req(eth_rx_pfc_req), - .eth_rx_pfc_ack(eth_rx_pfc_ack), - .eth_rx_fc_quanta_clk_en(0), - - /* - * DDR - */ - .ddr_clk(ddr_clk), - .ddr_rst(ddr_rst), - - .m_axi_ddr_awid(m_axi_ddr_awid), - .m_axi_ddr_awaddr(m_axi_ddr_awaddr), - .m_axi_ddr_awlen(m_axi_ddr_awlen), - .m_axi_ddr_awsize(m_axi_ddr_awsize), - .m_axi_ddr_awburst(m_axi_ddr_awburst), - .m_axi_ddr_awlock(m_axi_ddr_awlock), - .m_axi_ddr_awcache(m_axi_ddr_awcache), - .m_axi_ddr_awprot(m_axi_ddr_awprot), - .m_axi_ddr_awqos(m_axi_ddr_awqos), - .m_axi_ddr_awuser(), - .m_axi_ddr_awvalid(m_axi_ddr_awvalid), - .m_axi_ddr_awready(m_axi_ddr_awready), - .m_axi_ddr_wdata(m_axi_ddr_wdata), - .m_axi_ddr_wstrb(m_axi_ddr_wstrb), - .m_axi_ddr_wlast(m_axi_ddr_wlast), - .m_axi_ddr_wuser(), - .m_axi_ddr_wvalid(m_axi_ddr_wvalid), - .m_axi_ddr_wready(m_axi_ddr_wready), - .m_axi_ddr_bid(m_axi_ddr_bid), - .m_axi_ddr_bresp(m_axi_ddr_bresp), - .m_axi_ddr_buser(0), - .m_axi_ddr_bvalid(m_axi_ddr_bvalid), - .m_axi_ddr_bready(m_axi_ddr_bready), - .m_axi_ddr_arid(m_axi_ddr_arid), - .m_axi_ddr_araddr(m_axi_ddr_araddr), - .m_axi_ddr_arlen(m_axi_ddr_arlen), - .m_axi_ddr_arsize(m_axi_ddr_arsize), - .m_axi_ddr_arburst(m_axi_ddr_arburst), - .m_axi_ddr_arlock(m_axi_ddr_arlock), - .m_axi_ddr_arcache(m_axi_ddr_arcache), - .m_axi_ddr_arprot(m_axi_ddr_arprot), - .m_axi_ddr_arqos(m_axi_ddr_arqos), - .m_axi_ddr_aruser(), - .m_axi_ddr_arvalid(m_axi_ddr_arvalid), - .m_axi_ddr_arready(m_axi_ddr_arready), - .m_axi_ddr_rid(m_axi_ddr_rid), - .m_axi_ddr_rdata(m_axi_ddr_rdata), - .m_axi_ddr_rresp(m_axi_ddr_rresp), - .m_axi_ddr_rlast(m_axi_ddr_rlast), - .m_axi_ddr_ruser(0), - .m_axi_ddr_rvalid(m_axi_ddr_rvalid), - .m_axi_ddr_rready(m_axi_ddr_rready), - - .ddr_status(ddr_status), - - /* - * HBM - */ - .hbm_clk(0), - .hbm_rst(0), - - .m_axi_hbm_awid(), - .m_axi_hbm_awaddr(), - .m_axi_hbm_awlen(), - .m_axi_hbm_awsize(), - .m_axi_hbm_awburst(), - .m_axi_hbm_awlock(), - .m_axi_hbm_awcache(), - .m_axi_hbm_awprot(), - .m_axi_hbm_awqos(), - .m_axi_hbm_awuser(), - .m_axi_hbm_awvalid(), - .m_axi_hbm_awready(0), - .m_axi_hbm_wdata(), - .m_axi_hbm_wstrb(), - .m_axi_hbm_wlast(), - .m_axi_hbm_wuser(), - .m_axi_hbm_wvalid(), - .m_axi_hbm_wready(0), - .m_axi_hbm_bid(0), - .m_axi_hbm_bresp(0), - .m_axi_hbm_buser(0), - .m_axi_hbm_bvalid(0), - .m_axi_hbm_bready(), - .m_axi_hbm_arid(), - .m_axi_hbm_araddr(), - .m_axi_hbm_arlen(), - .m_axi_hbm_arsize(), - .m_axi_hbm_arburst(), - .m_axi_hbm_arlock(), - .m_axi_hbm_arcache(), - .m_axi_hbm_arprot(), - .m_axi_hbm_arqos(), - .m_axi_hbm_aruser(), - .m_axi_hbm_arvalid(), - .m_axi_hbm_arready(0), - .m_axi_hbm_rid(0), - .m_axi_hbm_rdata(0), - .m_axi_hbm_rresp(0), - .m_axi_hbm_rlast(0), - .m_axi_hbm_ruser(0), - .m_axi_hbm_rvalid(0), - .m_axi_hbm_rready(), - - .hbm_status(0), - - /* - * Statistics input - */ - .s_axis_stat_tdata(0), - .s_axis_stat_tid(0), - .s_axis_stat_tvalid(1'b0), - .s_axis_stat_tready(), - - /* - * GPIO - */ - .app_gpio_in(0), - .app_gpio_out(), - - /* - * JTAG - */ - .app_jtag_tdi(1'b0), - .app_jtag_tdo(), - .app_jtag_tms(1'b0), - .app_jtag_tck(1'b0) -); - -endmodule - -`resetall diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/sync_signal.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/sync_signal.v deleted file mode 100644 index 74b855fa1..000000000 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/sync_signal.v +++ /dev/null @@ -1,62 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog-2001 - -`resetall -`timescale 1 ns / 1 ps -`default_nettype none - -/* - * Synchronizes an asyncronous signal to a given clock by using a pipeline of - * two registers. - */ -module sync_signal #( - parameter WIDTH=1, // width of the input and output signals - parameter N=2 // depth of synchronizer -)( - input wire clk, - input wire [WIDTH-1:0] in, - output wire [WIDTH-1:0] out -); - -reg [WIDTH-1:0] sync_reg[N-1:0]; - -/* - * The synchronized output is the last register in the pipeline. - */ -assign out = sync_reg[N-1]; - -integer k; - -always @(posedge clk) begin - sync_reg[0] <= in; - for (k = 1; k < N; k = k + 1) begin - sync_reg[k] <= sync_reg[k-1]; - end -end - -endmodule - -`resetall diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile deleted file mode 100644 index a480035a9..000000000 --- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile +++ /dev/null @@ -1,261 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2020-2023 The Regents of the University of California - -TOPLEVEL_LANG = verilog - -SIM ?= icarus -WAVES ?= 0 - -COCOTB_HDL_TIMEUNIT = 1ns -COCOTB_HDL_TIMEPRECISION = 1ps - -DUT = fpga_core -TOPLEVEL = $(DUT) -MODULE = test_$(DUT) -VERILOG_SOURCES += ../../rtl/$(DUT).v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v -VERILOG_SOURCES += ../../rtl/common/mqnic_core.v -VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v -VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v -VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v -VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v -VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v -VERILOG_SOURCES += ../../rtl/common/cpl_write.v -VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v -VERILOG_SOURCES += ../../rtl/common/desc_fetch.v -VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v -VERILOG_SOURCES += ../../rtl/common/queue_manager.v -VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v -VERILOG_SOURCES += ../../rtl/common/tx_fifo.v -VERILOG_SOURCES += ../../rtl/common/rx_fifo.v -VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v -VERILOG_SOURCES += ../../rtl/common/tx_engine.v -VERILOG_SOURCES += ../../rtl/common/rx_engine.v -VERILOG_SOURCES += ../../rtl/common/tx_checksum.v -VERILOG_SOURCES += ../../rtl/common/rx_hash.v -VERILOG_SOURCES += ../../rtl/common/rx_checksum.v -VERILOG_SOURCES += ../../rtl/common/rb_drp.v -VERILOG_SOURCES += ../../rtl/common/stats_counter.v -VERILOG_SOURCES += ../../rtl/common/stats_collect.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v -VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v -VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v -VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v -VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v -VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v -VERILOG_SOURCES += ../../rtl/common/tdma_ber.v -VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v -VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v -VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v -VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v -VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v -VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v -VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v -VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v -VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v -VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v -VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v -VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v -VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v - -# module parameters - -# Structural configuration -export PARAM_IF_COUNT := 2 -export PARAM_PORTS_PER_IF := 1 -export PARAM_SCHED_PER_IF := $(PARAM_PORTS_PER_IF) -export PARAM_PORT_MASK := 0 - -# Clock configuration -export PARAM_CLK_PERIOD_NS_NUM := 4 -export PARAM_CLK_PERIOD_NS_DENOM := 1 - -# PTP configuration -export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 -export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 -export PARAM_PTP_CLOCK_PIPELINE := 0 -export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 -export PARAM_PTP_PORT_CDC_PIPELINE := 0 -export PARAM_PTP_PEROUT_ENABLE := 0 -export PARAM_PTP_PEROUT_COUNT := 1 - -# Queue manager configuration -export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 -export PARAM_CQ_OP_TABLE_SIZE := 32 -export PARAM_EQN_WIDTH := 6 -export PARAM_TX_QUEUE_INDEX_WIDTH := 13 -export PARAM_RX_QUEUE_INDEX_WIDTH := 8 -export PARAM_CQN_WIDTH := $(shell python -c "print(max($(PARAM_TX_QUEUE_INDEX_WIDTH), $(PARAM_RX_QUEUE_INDEX_WIDTH)) + 1)") -export PARAM_EQ_PIPELINE := 3 -export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") -export PARAM_CQ_PIPELINE := $(shell python -c "print(3 + max($(PARAM_CQN_WIDTH)-12, 0))") - -# TX and RX engine configuration -export PARAM_TX_DESC_TABLE_SIZE := 32 -export PARAM_RX_DESC_TABLE_SIZE := 32 -export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") - -# Scheduler configuration -export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) -export PARAM_TX_SCHEDULER_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) -export PARAM_TDMA_INDEX_WIDTH := 6 - -# Interface configuration -export PARAM_PTP_TS_ENABLE := 1 -export PARAM_TX_CPL_FIFO_DEPTH := 32 -export PARAM_TX_CHECKSUM_ENABLE := 1 -export PARAM_RX_HASH_ENABLE := 1 -export PARAM_RX_CHECKSUM_ENABLE := 1 -export PARAM_LFC_ENABLE := 1 -export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) -export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 -export PARAM_MAX_TX_SIZE := 9214 -export PARAM_MAX_RX_SIZE := 9214 -export PARAM_TX_RAM_SIZE := 32768 -export PARAM_RX_RAM_SIZE := 131072 - -# Application block configuration -export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) -export PARAM_APP_ENABLE := 0 -export PARAM_APP_CTRL_ENABLE := 1 -export PARAM_APP_DMA_ENABLE := 1 -export PARAM_APP_AXIS_DIRECT_ENABLE := 1 -export PARAM_APP_AXIS_SYNC_ENABLE := 1 -export PARAM_APP_AXIS_IF_ENABLE := 1 -export PARAM_APP_STAT_ENABLE := 1 - -# DMA interface configuration -export PARAM_DMA_IMM_ENABLE := 0 -export PARAM_DMA_IMM_WIDTH := 32 -export PARAM_DMA_LEN_WIDTH := 16 -export PARAM_DMA_TAG_WIDTH := 16 -export PARAM_RAM_ADDR_WIDTH := $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())") -export PARAM_RAM_PIPELINE := 2 - -# PCIe interface configuration -export PARAM_AXIS_PCIE_DATA_WIDTH := 512 -export PARAM_PF_COUNT := 1 -export PARAM_VF_COUNT := 0 - -# Interrupt configuration -export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EQN_WIDTH) - -# AXI lite interface configuration (control) -export PARAM_AXIL_CTRL_DATA_WIDTH := 32 -export PARAM_AXIL_CTRL_ADDR_WIDTH := 24 - -# AXI lite interface configuration (application control) -export PARAM_AXIL_APP_CTRL_DATA_WIDTH := $(PARAM_AXIL_CTRL_DATA_WIDTH) -export PARAM_AXIL_APP_CTRL_ADDR_WIDTH := 24 - -# Ethernet interface configuration -export PARAM_AXIS_ETH_TX_PIPELINE := 4 -export PARAM_AXIS_ETH_TX_FIFO_PIPELINE := 4 -export PARAM_AXIS_ETH_TX_TS_PIPELINE := 4 -export PARAM_AXIS_ETH_RX_PIPELINE := 4 -export PARAM_AXIS_ETH_RX_FIFO_PIPELINE := 4 - -# Statistics counter subsystem -export PARAM_STAT_ENABLE := 1 -export PARAM_STAT_DMA_ENABLE := 1 -export PARAM_STAT_PCIE_ENABLE := 1 -export PARAM_STAT_INC_WIDTH := 24 -export PARAM_STAT_ID_WIDTH := 12 - -ifeq ($(SIM), icarus) - PLUSARGS += -fst - - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif -else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - - COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) - - ifeq ($(WAVES), 1) - COMPILE_ARGS += --trace-fst - endif -endif - -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/mqnic.py b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/mqnic.py deleted file mode 120000 index dfa8522e7..000000000 --- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/mqnic.py +++ /dev/null @@ -1 +0,0 @@ -../../../../../common/tb/mqnic.py \ No newline at end of file diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py deleted file mode 100644 index 59babf55f..000000000 --- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py +++ /dev/null @@ -1,810 +0,0 @@ -# SPDX-License-Identifier: BSD-2-Clause-Views -# Copyright (c) 2020-2023 The Regents of the University of California - -import logging -import os -import struct -import sys - -import scapy.utils -from scapy.layers.l2 import Ether -from scapy.layers.inet import IP, UDP - -import cocotb_test.simulator - -import cocotb -from cocotb.log import SimLog -from cocotb.clock import Clock -from cocotb.triggers import RisingEdge, FallingEdge, Timer - -from cocotbext.axi import AxiStreamBus -from cocotbext.eth import XgmiiSource, XgmiiSink, XgmiiFrame -from cocotbext.pcie.core import RootComplex -from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice - -try: - import mqnic -except ImportError: - # attempt import from current directory - sys.path.insert(0, os.path.join(os.path.dirname(__file__))) - try: - import mqnic - finally: - del sys.path[0] - - -class TB(object): - def __init__(self, dut, msix_count=32): - self.dut = dut - - self.log = SimLog("cocotb.tb") - self.log.setLevel(logging.DEBUG) - - # PCIe - self.rc = RootComplex() - - self.rc.max_payload_size = 0x1 # 256 bytes - self.rc.max_read_request_size = 0x2 # 512 bytes - - self.dev = UltraScalePlusPcieDevice( - # configuration options - pcie_generation=3, - pcie_link_width=16, - user_clk_frequency=250e6, - alignment="dword", - cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1, - cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1, - rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1, - rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1, - rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2, - pf_count=1, - max_payload_size=1024, - enable_client_tag=True, - enable_extended_tag=True, - enable_parity=False, - enable_rx_msg_interface=False, - enable_sriov=False, - enable_extended_configuration=False, - - pf0_msi_enable=False, - pf0_msi_count=32, - pf1_msi_enable=False, - pf1_msi_count=1, - pf2_msi_enable=False, - pf2_msi_count=1, - pf3_msi_enable=False, - pf3_msi_count=1, - pf0_msix_enable=True, - pf0_msix_table_size=msix_count-1, - pf0_msix_table_bir=0, - pf0_msix_table_offset=0x00010000, - pf0_msix_pba_bir=0, - pf0_msix_pba_offset=0x00018000, - pf1_msix_enable=False, - pf1_msix_table_size=0, - pf1_msix_table_bir=0, - pf1_msix_table_offset=0x00000000, - pf1_msix_pba_bir=0, - pf1_msix_pba_offset=0x00000000, - pf2_msix_enable=False, - pf2_msix_table_size=0, - pf2_msix_table_bir=0, - pf2_msix_table_offset=0x00000000, - pf2_msix_pba_bir=0, - pf2_msix_pba_offset=0x00000000, - pf3_msix_enable=False, - pf3_msix_table_size=0, - pf3_msix_table_bir=0, - pf3_msix_table_offset=0x00000000, - pf3_msix_pba_bir=0, - pf3_msix_pba_offset=0x00000000, - - # signals - # Clock and Reset Interface - user_clk=dut.clk_250mhz, - user_reset=dut.rst_250mhz, - # user_lnk_up - # sys_clk - # sys_clk_gt - # sys_reset - # phy_rdy_out - - # Requester reQuest Interface - rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), - pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, - pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, - pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, - pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, - # pcie_rq_tag0 - # pcie_rq_tag1 - # pcie_rq_tag_av - # pcie_rq_tag_vld0 - # pcie_rq_tag_vld1 - - # Requester Completion Interface - rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), - - # Completer reQuest Interface - cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), - # pcie_cq_np_req - # pcie_cq_np_req_count - - # Completer Completion Interface - cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), - - # Transmit Flow Control Interface - # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, - # pcie_tfc_npd_av=dut.pcie_tfc_npd_av, - - # Configuration Management Interface - cfg_mgmt_addr=dut.cfg_mgmt_addr, - cfg_mgmt_function_number=dut.cfg_mgmt_function_number, - cfg_mgmt_write=dut.cfg_mgmt_write, - cfg_mgmt_write_data=dut.cfg_mgmt_write_data, - cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable, - cfg_mgmt_read=dut.cfg_mgmt_read, - cfg_mgmt_read_data=dut.cfg_mgmt_read_data, - cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done, - # cfg_mgmt_debug_access - - # Configuration Status Interface - # cfg_phy_link_down - # cfg_phy_link_status - # cfg_negotiated_width - # cfg_current_speed - cfg_max_payload=dut.cfg_max_payload, - cfg_max_read_req=dut.cfg_max_read_req, - # cfg_function_status - # cfg_vf_status - # cfg_function_power_state - # cfg_vf_power_state - # cfg_link_power_state - # cfg_err_cor_out - # cfg_err_nonfatal_out - # cfg_err_fatal_out - # cfg_local_error_out - # cfg_local_error_valid - # cfg_rx_pm_state - # cfg_tx_pm_state - # cfg_ltssm_state - cfg_rcb_status=dut.cfg_rcb_status, - # cfg_obff_enable - # cfg_pl_status_change - # cfg_tph_requester_enable - # cfg_tph_st_mode - # cfg_vf_tph_requester_enable - # cfg_vf_tph_st_mode - - # Configuration Received Message Interface - # cfg_msg_received - # cfg_msg_received_data - # cfg_msg_received_type - - # Configuration Transmit Message Interface - # cfg_msg_transmit - # cfg_msg_transmit_type - # cfg_msg_transmit_data - # cfg_msg_transmit_done - - # Configuration Flow Control Interface - cfg_fc_ph=dut.cfg_fc_ph, - cfg_fc_pd=dut.cfg_fc_pd, - cfg_fc_nph=dut.cfg_fc_nph, - cfg_fc_npd=dut.cfg_fc_npd, - cfg_fc_cplh=dut.cfg_fc_cplh, - cfg_fc_cpld=dut.cfg_fc_cpld, - cfg_fc_sel=dut.cfg_fc_sel, - - # Configuration Control Interface - # cfg_hot_reset_in - # cfg_hot_reset_out - # cfg_config_space_enable - # cfg_dsn - # cfg_bus_number - # cfg_ds_port_number - # cfg_ds_bus_number - # cfg_ds_device_number - # cfg_ds_function_number - # cfg_power_state_change_ack - # cfg_power_state_change_interrupt - cfg_err_cor_in=dut.status_error_cor, - cfg_err_uncor_in=dut.status_error_uncor, - # cfg_flr_in_process - # cfg_flr_done - # cfg_vf_flr_in_process - # cfg_vf_flr_func_num - # cfg_vf_flr_done - # cfg_pm_aspm_l1_entry_reject - # cfg_pm_aspm_tx_l0s_entry_disable - # cfg_req_pm_transition_l23_ready - # cfg_link_training_enable - - # Configuration Interrupt Controller Interface - # cfg_interrupt_int - # cfg_interrupt_sent - # cfg_interrupt_pending - # cfg_interrupt_msi_enable - # cfg_interrupt_msi_mmenable - # cfg_interrupt_msi_mask_update - # cfg_interrupt_msi_data - # cfg_interrupt_msi_select - # cfg_interrupt_msi_int - # cfg_interrupt_msi_pending_status - # cfg_interrupt_msi_pending_status_data_enable - # cfg_interrupt_msi_pending_status_function_num - # cfg_interrupt_msi_sent - # cfg_interrupt_msi_fail - cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable, - cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask, - cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable, - cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask, - cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address, - cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data, - cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int, - cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending, - cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status, - cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent, - cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail, - # cfg_interrupt_msi_attr - # cfg_interrupt_msi_tph_present - # cfg_interrupt_msi_tph_type - # cfg_interrupt_msi_tph_st_tag - cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, - - # Configuration Extend Interface - # cfg_ext_read_received - # cfg_ext_write_received - # cfg_ext_register_number - # cfg_ext_function_number - # cfg_ext_write_data - # cfg_ext_write_byte_enable - # cfg_ext_read_data - # cfg_ext_read_data_valid - ) - - # self.dev.log.setLevel(logging.DEBUG) - - self.rc.make_port().connect(self.dev) - - self.driver = mqnic.Driver() - - self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) - if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): - self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) - - cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start()) - dut.ptp_rst.setimmediatevalue(0) - cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start()) - - # Ethernet - self.qsfp_source = [] - self.qsfp_sink = [] - - for x in range(2): - sources = [] - sinks = [] - for y in range(1, 5): - cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_rx_clk_{y}"), 2.56, units="ns").start()) - source = XgmiiSource(getattr(dut, f"qsfp{x}_rxd_{y}"), getattr(dut, f"qsfp{x}_rxc_{y}"), getattr(dut, f"qsfp{x}_rx_clk_{y}"), getattr(dut, f"qsfp{x}_rx_rst_{y}")) - sources.append(source) - cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_tx_clk_{y}"), 2.56, units="ns").start()) - sink = XgmiiSink(getattr(dut, f"qsfp{x}_txd_{y}"), getattr(dut, f"qsfp{x}_txc_{y}"), getattr(dut, f"qsfp{x}_tx_clk_{y}"), getattr(dut, f"qsfp{x}_tx_rst_{y}")) - sinks.append(sink) - getattr(dut, f"qsfp{x}_rx_status_{y}").setimmediatevalue(1) - getattr(dut, f"qsfp{x}_rx_error_count_{y}").setimmediatevalue(0) - self.qsfp_source.append(sources) - self.qsfp_sink.append(sinks) - - cocotb.start_soon(Clock(getattr(dut, f"qsfp{x}_drp_clk"), 8, units="ns").start()) - getattr(dut, f"qsfp{x}_drp_rst").setimmediatevalue(0) - getattr(dut, f"qsfp{x}_drp_do").setimmediatevalue(0) - getattr(dut, f"qsfp{x}_drp_rdy").setimmediatevalue(0) - - getattr(dut, f"qsfp{x}_modprsl").setimmediatevalue(0) - getattr(dut, f"qsfp{x}_intl").setimmediatevalue(1) - - dut.sw.setimmediatevalue(0) - - dut.i2c_scl_i.setimmediatevalue(1) - dut.i2c_sda_i.setimmediatevalue(1) - - dut.qspi_dq_i.setimmediatevalue(0) - - self.loopback_enable = False - cocotb.start_soon(self._run_loopback()) - - async def init(self): - - self.dut.ptp_rst.setimmediatevalue(0) - for x in range(2): - for y in range(1, 5): - getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(0) - getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(0) - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.ptp_rst.setimmediatevalue(1) - for x in range(2): - for y in range(1, 5): - getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(1) - getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(1) - - await FallingEdge(self.dut.rst_250mhz) - await Timer(100, 'ns') - - await RisingEdge(self.dut.clk_250mhz) - await RisingEdge(self.dut.clk_250mhz) - - self.dut.ptp_rst.setimmediatevalue(0) - for x in range(2): - for y in range(1, 5): - getattr(self.dut, f"qsfp{x}_rx_rst_{y}").setimmediatevalue(0) - getattr(self.dut, f"qsfp{x}_tx_rst_{y}").setimmediatevalue(0) - - await self.rc.enumerate() - - async def _run_loopback(self): - while True: - await RisingEdge(self.dut.clk_250mhz) - - if self.loopback_enable: - for x in range(len(self.qsfp_sink)): - for y in range(len(self.qsfp_sink[x])): - if not self.qsfp_sink[x][y].empty(): - await self.qsfp_source[x][y].send(await self.qsfp_sink[x][y].recv()) - - -@cocotb.test() -async def run_test_nic(dut): - - tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index)) - - await tb.init() - - tb.log.info("Init driver") - await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id)) - await tb.driver.interfaces[0].open() - # await tb.driver.interfaces[1].open() - - # enable queues - tb.log.info("Enable queues") - await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) - for k in range(len(tb.driver.interfaces[0].txq)): - await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003) - - # wait for all writes to complete - await tb.driver.hw_regs.read_dword(0) - tb.log.info("Init complete") - - tb.log.info("Send and receive single packet") - - data = bytearray([x % 256 for x in range(1024)]) - - await tb.driver.interfaces[0].start_xmit(data, 0) - - pkt = await tb.qsfp_sink[0][0].recv() - tb.log.info("Packet: %s", pkt) - - await tb.qsfp_source[0][0].send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - # await tb.driver.interfaces[1].start_xmit(data, 0) - - # pkt = await tb.qsfp_sink[1][0].recv() - # tb.log.info("Packet: %s", pkt) - - # await tb.qsfp_source[1][0].send(pkt) - - # pkt = await tb.driver.interfaces[1].recv() - - # tb.log.info("Packet: %s", pkt) - # assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.log.info("RX and TX checksum tests") - - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') - ip = IP(src='192.168.1.100', dst='192.168.1.101') - udp = UDP(sport=1, dport=2) - test_pkt = eth / ip / udp / payload - - test_pkt2 = test_pkt.copy() - test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) - - await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - - pkt = await tb.qsfp_sink[0][0].recv() - tb.log.info("Packet: %s", pkt) - - await tb.qsfp_source[0][0].send(pkt) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - assert Ether(pkt.data).build() == test_pkt.build() - - tb.log.info("Queue mapping offset test") - - data = bytearray([x % 256 for x in range(1024)]) - - tb.loopback_enable = True - - for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) - - await tb.driver.interfaces[0].start_xmit(data, 0) - - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - assert pkt.queue == k - - tb.loopback_enable = False - - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) - - tb.log.info("Queue mapping RSS mask test") - - await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) - - for k in range(4): - await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) - - tb.loopback_enable = True - - queues = set() - - for k in range(64): - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') - ip = IP(src='192.168.1.100', dst='192.168.1.101') - udp = UDP(sport=1, dport=k+0) - test_pkt = eth / ip / udp / payload - - test_pkt2 = test_pkt.copy() - test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) - - await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) - - for k in range(64): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - queues.add(pkt.queue) - - assert len(queues) == 4 - - tb.loopback_enable = False - - await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0) - - tb.log.info("Multiple small packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - tb.log.info("Multiple large packets") - - count = 64 - - pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - if tb.driver.interfaces[0].if_feature_lfc: - tb.log.info("Test LFC pause frame RX") - - await tb.driver.interfaces[0].ports[0].set_lfc_ctrl(mqnic.MQNIC_PORT_LFC_CTRL_TX_LFC_EN | mqnic.MQNIC_PORT_LFC_CTRL_RX_LFC_EN) - await tb.driver.hw_regs.read_dword(0) - - lfc_xoff = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) / struct.pack('!HH', 0x0001, 2000) - - await tb.qsfp_source[0][0].send(XgmiiFrame.from_payload(bytes(lfc_xoff))) - - count = 16 - - pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] - - tb.loopback_enable = True - - for p in pkts: - await tb.driver.interfaces[0].start_xmit(p, 0) - - for k in range(count): - pkt = await tb.driver.interfaces[0].recv() - - tb.log.info("Packet: %s", pkt) - assert pkt.data == pkts[k] - if tb.driver.interfaces[0].if_feature_rx_csum: - assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff - - tb.loopback_enable = False - - await RisingEdge(dut.clk_250mhz) - await RisingEdge(dut.clk_250mhz) - - -# cocotb-test - -tests_dir = os.path.dirname(__file__) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) -app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app')) -axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl')) -axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) -eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) -pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl')) - - -def test_fpga_core(request): - dut = "fpga_core" - module = os.path.splitext(os.path.basename(__file__))[0] - toplevel = dut - - verilog_sources = [ - os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), - os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), - os.path.join(rtl_dir, "common", "mqnic_core.v"), - os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), - os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), - os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), - os.path.join(rtl_dir, "common", "mqnic_port_tx.v"), - os.path.join(rtl_dir, "common", "mqnic_port_rx.v"), - os.path.join(rtl_dir, "common", "mqnic_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), - os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), - os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), - os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), - os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), - os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), - os.path.join(rtl_dir, "common", "cpl_write.v"), - os.path.join(rtl_dir, "common", "cpl_op_mux.v"), - os.path.join(rtl_dir, "common", "desc_fetch.v"), - os.path.join(rtl_dir, "common", "desc_op_mux.v"), - os.path.join(rtl_dir, "common", "queue_manager.v"), - os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), - os.path.join(rtl_dir, "common", "tx_fifo.v"), - os.path.join(rtl_dir, "common", "rx_fifo.v"), - os.path.join(rtl_dir, "common", "tx_req_mux.v"), - os.path.join(rtl_dir, "common", "tx_engine.v"), - os.path.join(rtl_dir, "common", "rx_engine.v"), - os.path.join(rtl_dir, "common", "tx_checksum.v"), - os.path.join(rtl_dir, "common", "rx_hash.v"), - os.path.join(rtl_dir, "common", "rx_checksum.v"), - os.path.join(rtl_dir, "common", "rb_drp.v"), - os.path.join(rtl_dir, "common", "stats_counter.v"), - os.path.join(rtl_dir, "common", "stats_collect.v"), - os.path.join(rtl_dir, "common", "stats_pcie_if.v"), - os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"), - os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"), - os.path.join(rtl_dir, "common", "stats_dma_latency.v"), - os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), - os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), - os.path.join(rtl_dir, "common", "tdma_scheduler.v"), - os.path.join(rtl_dir, "common", "tdma_ber.v"), - os.path.join(rtl_dir, "common", "tdma_ber_ch.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), - os.path.join(eth_rtl_dir, "mac_ctrl_rx.v"), - os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"), - os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"), - os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"), - os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "ptp_clock.v"), - os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), - os.path.join(eth_rtl_dir, "ptp_perout.v"), - os.path.join(axi_rtl_dir, "axil_interconnect.v"), - os.path.join(axi_rtl_dir, "axil_crossbar.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"), - os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"), - os.path.join(axi_rtl_dir, "axil_reg_if.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"), - os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"), - os.path.join(axi_rtl_dir, "axil_register_rd.v"), - os.path.join(axi_rtl_dir, "axil_register_wr.v"), - os.path.join(axi_rtl_dir, "arbiter.v"), - os.path.join(axi_rtl_dir, "priority_encoder.v"), - os.path.join(axis_rtl_dir, "axis_adapter.v"), - os.path.join(axis_rtl_dir, "axis_arb_mux.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_demux.v"), - os.path.join(axis_rtl_dir, "axis_fifo.v"), - os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), - os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), - os.path.join(axis_rtl_dir, "axis_register.v"), - os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), - os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), - os.path.join(pcie_rtl_dir, "pcie_msix.v"), - os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"), - os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"), - os.path.join(pcie_rtl_dir, "dma_psdpram.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"), - os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), - os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), - os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), - os.path.join(pcie_rtl_dir, "pulse_merge.v"), - ] - - parameters = {} - - # Structural configuration - parameters['IF_COUNT'] = 2 - parameters['PORTS_PER_IF'] = 1 - parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] - parameters['PORT_MASK'] = 0 - - # Clock configuration - parameters['CLK_PERIOD_NS_NUM'] = 4 - parameters['CLK_PERIOD_NS_DENOM'] = 1 - - # PTP configuration - parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 - parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 - parameters['PTP_CLOCK_PIPELINE'] = 0 - parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 - parameters['PTP_PORT_CDC_PIPELINE'] = 0 - parameters['PTP_PEROUT_ENABLE'] = 0 - parameters['PTP_PEROUT_COUNT'] = 1 - - # Queue manager configuration - parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 - parameters['CQ_OP_TABLE_SIZE'] = 32 - parameters['EQN_WIDTH'] = 6 - parameters['TX_QUEUE_INDEX_WIDTH'] = 13 - parameters['RX_QUEUE_INDEX_WIDTH'] = 8 - parameters['CQN_WIDTH'] = max(parameters['TX_QUEUE_INDEX_WIDTH'], parameters['RX_QUEUE_INDEX_WIDTH']) + 1 - parameters['EQ_PIPELINE'] = 3 - parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) - parameters['CQ_PIPELINE'] = 3 + max(parameters['CQN_WIDTH']-12, 0) - - # TX and RX engine configuration - parameters['TX_DESC_TABLE_SIZE'] = 32 - parameters['RX_DESC_TABLE_SIZE'] = 32 - parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) - - # Scheduler configuration - parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] - parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] - parameters['TDMA_INDEX_WIDTH'] = 6 - - # Interface configuration - parameters['PTP_TS_ENABLE'] = 1 - parameters['TX_CPL_FIFO_DEPTH'] = 32 - parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_HASH_ENABLE'] = 1 - parameters['RX_CHECKSUM_ENABLE'] = 1 - parameters['LFC_ENABLE'] = 1 - parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] - parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 - parameters['MAX_TX_SIZE'] = 9214 - parameters['MAX_RX_SIZE'] = 9214 - parameters['TX_RAM_SIZE'] = 32768 - parameters['RX_RAM_SIZE'] = 131072 - - # Application block configuration - parameters['APP_ID'] = 0x00000000 - parameters['APP_ENABLE'] = 0 - parameters['APP_CTRL_ENABLE'] = 1 - parameters['APP_DMA_ENABLE'] = 1 - parameters['APP_AXIS_DIRECT_ENABLE'] = 1 - parameters['APP_AXIS_SYNC_ENABLE'] = 1 - parameters['APP_AXIS_IF_ENABLE'] = 1 - parameters['APP_STAT_ENABLE'] = 1 - - # DMA interface configuration - parameters['DMA_IMM_ENABLE'] = 0 - parameters['DMA_IMM_WIDTH'] = 32 - parameters['DMA_LEN_WIDTH'] = 16 - parameters['DMA_TAG_WIDTH'] = 16 - parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length() - parameters['RAM_PIPELINE'] = 2 - - # PCIe interface configuration - parameters['AXIS_PCIE_DATA_WIDTH'] = 512 - parameters['PF_COUNT'] = 1 - parameters['VF_COUNT'] = 0 - - # Interrupt configuration - parameters['IRQ_INDEX_WIDTH'] = parameters['EQN_WIDTH'] - - # AXI lite interface configuration (control) - parameters['AXIL_CTRL_DATA_WIDTH'] = 32 - parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 - - # AXI lite interface configuration (application control) - parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH'] - parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24 - - # Ethernet interface configuration - parameters['AXIS_ETH_TX_PIPELINE'] = 4 - parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 4 - parameters['AXIS_ETH_TX_TS_PIPELINE'] = 4 - parameters['AXIS_ETH_RX_PIPELINE'] = 4 - parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 4 - - # Statistics counter subsystem - parameters['STAT_ENABLE'] = 1 - parameters['STAT_DMA_ENABLE'] = 1 - parameters['STAT_PCIE_ENABLE'] = 1 - parameters['STAT_INC_WIDTH'] = 24 - parameters['STAT_ID_WIDTH'] = 12 - - extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} - - sim_build = os.path.join(tests_dir, "sim_build", - request.node.name.replace('[', '-').replace(']', '')) - - cocotb_test.simulator.run( - python_search=[tests_dir], - verilog_sources=verilog_sources, - toplevel=toplevel, - module=module, - parameters=parameters, - sim_build=sim_build, - extra_env=extra_env, - )