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Convert generated eth_demux to verilog parametrized module

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This commit is contained in:
Alex Forencich 2018-11-02 00:23:31 -07:00
parent 470ab887d9
commit 18c4214edb
9 changed files with 919 additions and 2240 deletions
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343
rtl/eth_demux.py
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#!/usr/bin/env python
"""
Generates an Ethernet demux with the specified number of ports
"""
from __future__ import print_function
import argparse
import math
from jinja2 import Template
def main():
parser = argparse.ArgumentParser(description=__doc__.strip())
parser.add_argument('-p', '--ports', type=int, default=4, help="number of ports")
parser.add_argument('-n', '--name', type=str, help="module name")
parser.add_argument('-o', '--output', type=str, help="output file name")
args = parser.parse_args()
try:
generate(**args.__dict__)
except IOError as ex:
print(ex)
exit(1)
def generate(ports=4, name=None, output=None):
if name is None:
name = "eth_demux_{0}".format(ports)
if output is None:
output = name + ".v"
print("Opening file '{0}'...".format(output))
output_file = open(output, 'w')
print("Generating {0} port Ethernet demux {1}...".format(ports, name))
select_width = int(math.ceil(math.log(ports, 2)))
t = Template(u"""/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Ethernet {{n}} port demultiplexer
*/
module {{name}}
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire input_eth_hdr_valid,
output wire input_eth_hdr_ready,
input wire [47:0] input_eth_dest_mac,
input wire [47:0] input_eth_src_mac,
input wire [15:0] input_eth_type,
input wire [7:0] input_eth_payload_tdata,
input wire input_eth_payload_tvalid,
output wire input_eth_payload_tready,
input wire input_eth_payload_tlast,
input wire input_eth_payload_tuser,
/*
* Ethernet frame outputs
*/
{%- for p in ports %}
output wire output_{{p}}_eth_hdr_valid,
input wire output_{{p}}_eth_hdr_ready,
output wire [47:0] output_{{p}}_eth_dest_mac,
output wire [47:0] output_{{p}}_eth_src_mac,
output wire [15:0] output_{{p}}_eth_type,
output wire [7:0] output_{{p}}_eth_payload_tdata,
output wire output_{{p}}_eth_payload_tvalid,
input wire output_{{p}}_eth_payload_tready,
output wire output_{{p}}_eth_payload_tlast,
output wire output_{{p}}_eth_payload_tuser,
{% endfor %}
/*
* Control
*/
input wire enable,
input wire [{{w-1}}:0] select
);
reg [{{w-1}}:0] select_reg = {{w}}'d0, select_next;
reg frame_reg = 1'b0, frame_next;
reg input_eth_hdr_ready_reg = 1'b0, input_eth_hdr_ready_next;
reg input_eth_payload_tready_reg = 1'b0, input_eth_payload_tready_next;
{% for p in ports %}
reg output_{{p}}_eth_hdr_valid_reg = 1'b0, output_{{p}}_eth_hdr_valid_next;
{%- endfor %}
reg [47:0] output_eth_dest_mac_reg = 48'd0, output_eth_dest_mac_next;
reg [47:0] output_eth_src_mac_reg = 48'd0, output_eth_src_mac_next;
reg [15:0] output_eth_type_reg = 16'd0, output_eth_type_next;
// internal datapath
reg [7:0] output_eth_payload_tdata_int;
reg output_eth_payload_tvalid_int;
reg output_eth_payload_tready_int_reg = 1'b0;
reg output_eth_payload_tlast_int;
reg output_eth_payload_tuser_int;
wire output_eth_payload_tready_int_early;
assign input_eth_hdr_ready = input_eth_hdr_ready_reg;
assign input_eth_payload_tready = input_eth_payload_tready_reg;
{% for p in ports %}
assign output_{{p}}_eth_hdr_valid = output_{{p}}_eth_hdr_valid_reg;
assign output_{{p}}_eth_dest_mac = output_eth_dest_mac_reg;
assign output_{{p}}_eth_src_mac = output_eth_src_mac_reg;
assign output_{{p}}_eth_type = output_eth_type_reg;
{% endfor %}
// mux for output control signals
reg current_output_eth_hdr_valid;
reg current_output_eth_hdr_ready;
reg current_output_tvalid;
reg current_output_tready;
always @* begin
case (select_reg)
{%- for p in ports %}
{{w}}'d{{p}}: begin
current_output_eth_hdr_valid = output_{{p}}_eth_hdr_valid;
current_output_eth_hdr_ready = output_{{p}}_eth_hdr_ready;
current_output_tvalid = output_{{p}}_eth_payload_tvalid;
current_output_tready = output_{{p}}_eth_payload_tready;
end
{%- endfor %}
default: begin
current_output_eth_hdr_valid = 1'b0;
current_output_eth_hdr_ready = 1'b0;
current_output_tvalid = 1'b0;
current_output_tready = 1'b0;
end
endcase
end
always @* begin
select_next = select_reg;
frame_next = frame_reg;
input_eth_hdr_ready_next = input_eth_hdr_ready_reg & ~input_eth_hdr_valid;
input_eth_payload_tready_next = 1'b0;
{%- for p in ports %}
output_{{p}}_eth_hdr_valid_next = output_{{p}}_eth_hdr_valid_reg & ~output_{{p}}_eth_hdr_ready;
{%- endfor %}
output_eth_dest_mac_next = output_eth_dest_mac_reg;
output_eth_src_mac_next = output_eth_src_mac_reg;
output_eth_type_next = output_eth_type_reg;
if (input_eth_payload_tvalid & input_eth_payload_tready) begin
// end of frame detection
if (input_eth_payload_tlast) begin
frame_next = 1'b0;
end
end
if (~frame_reg & enable & input_eth_hdr_valid & ~current_output_eth_hdr_valid & ~current_output_tvalid) begin
// start of frame, grab select value
frame_next = 1'b1;
select_next = select;
input_eth_hdr_ready_next = 1'b1;
case (select)
{%- for p in ports %}
{{w}}'d{{p}}: output_{{p}}_eth_hdr_valid_next = 1'b1;
{%- endfor %}
endcase
output_eth_dest_mac_next = input_eth_dest_mac;
output_eth_src_mac_next = input_eth_src_mac;
output_eth_type_next = input_eth_type;
end
input_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
output_eth_payload_tdata_int = input_eth_payload_tdata;
output_eth_payload_tvalid_int = input_eth_payload_tvalid & input_eth_payload_tready;
output_eth_payload_tlast_int = input_eth_payload_tlast;
output_eth_payload_tuser_int = input_eth_payload_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= {{w}}'d0;
frame_reg <= 1'b0;
input_eth_hdr_ready_reg <= 1'b0;
input_eth_payload_tready_reg <= 1'b0;
{%- for p in ports %}
output_{{p}}_eth_hdr_valid_reg <= 1'b0;
{%- endfor %}
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
input_eth_hdr_ready_reg <= input_eth_hdr_ready_next;
input_eth_payload_tready_reg <= input_eth_payload_tready_next;
{%- for p in ports %}
output_{{p}}_eth_hdr_valid_reg <= output_{{p}}_eth_hdr_valid_next;
{%- endfor %}
end
output_eth_dest_mac_reg <= output_eth_dest_mac_next;
output_eth_src_mac_reg <= output_eth_src_mac_next;
output_eth_type_reg <= output_eth_type_next;
end
// output datapath logic
reg [7:0] output_eth_payload_tdata_reg = 8'd0;
{%- for p in ports %}
reg output_{{p}}_eth_payload_tvalid_reg = 1'b0, output_{{p}}_eth_payload_tvalid_next;
{%- endfor %}
reg output_eth_payload_tlast_reg = 1'b0;
reg output_eth_payload_tuser_reg = 1'b0;
reg [7:0] temp_eth_payload_tdata_reg = 8'd0;
reg temp_eth_payload_tvalid_reg = 1'b0, temp_eth_payload_tvalid_next;
reg temp_eth_payload_tlast_reg = 1'b0;
reg temp_eth_payload_tuser_reg = 1'b0;
// datapath control
reg store_eth_payload_int_to_output;
reg store_eth_payload_int_to_temp;
reg store_eth_payload_temp_to_output;
{% for p in ports %}
assign output_{{p}}_eth_payload_tdata = output_eth_payload_tdata_reg;
assign output_{{p}}_eth_payload_tvalid = output_{{p}}_eth_payload_tvalid_reg;
assign output_{{p}}_eth_payload_tlast = output_eth_payload_tlast_reg;
assign output_{{p}}_eth_payload_tuser = output_eth_payload_tuser_reg;
{% endfor %}
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_eth_payload_tready_int_early = current_output_tready | (~temp_eth_payload_tvalid_reg & (~current_output_tvalid | ~output_eth_payload_tvalid_int));
always @* begin
// transfer sink ready state to source
{%- for p in ports %}
output_{{p}}_eth_payload_tvalid_next = output_{{p}}_eth_payload_tvalid_reg;
{%- endfor %}
temp_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg;
store_eth_payload_int_to_output = 1'b0;
store_eth_payload_int_to_temp = 1'b0;
store_eth_payload_temp_to_output = 1'b0;
if (output_eth_payload_tready_int_reg) begin
// input is ready
if (current_output_tready | ~current_output_tvalid) begin
// output is ready or currently not valid, transfer data to output
{%- for p in ports %}
output_{{p}}_eth_payload_tvalid_next = output_eth_payload_tvalid_int & (select_reg == {{w}}'d{{p}});
{%- endfor %}
store_eth_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_eth_payload_tvalid_next = output_eth_payload_tvalid_int;
store_eth_payload_int_to_temp = 1'b1;
end
end else if (current_output_tready) begin
// input is not ready, but output is ready
{%- for p in ports %}
output_{{p}}_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg & (select_reg == {{w}}'d{{p}});
{%- endfor %}
temp_eth_payload_tvalid_next = 1'b0;
store_eth_payload_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
{%- for p in ports %}
output_{{p}}_eth_payload_tvalid_reg <= 1'b0;
{%- endfor %}
output_eth_payload_tready_int_reg <= 1'b0;
temp_eth_payload_tvalid_reg <= 1'b0;
end else begin
{%- for p in ports %}
output_{{p}}_eth_payload_tvalid_reg <= output_{{p}}_eth_payload_tvalid_next;
{%- endfor %}
output_eth_payload_tready_int_reg <= output_eth_payload_tready_int_early;
temp_eth_payload_tvalid_reg <= temp_eth_payload_tvalid_next;
end
// datapath
if (store_eth_payload_int_to_output) begin
output_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
output_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
output_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
end else if (store_eth_payload_temp_to_output) begin
output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg;
output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg;
output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg;
end
if (store_eth_payload_int_to_temp) begin
temp_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
temp_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
temp_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
end
end
endmodule
""")
output_file.write(t.render(
n=ports,
w=select_width,
name=name,
ports=range(ports)
))
print("Done")
if __name__ == "__main__":
main()

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rtl/eth_demux.v Normal file
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/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Ethernet demultiplexer
*/
module eth_demux #
(
parameter M_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [DATA_WIDTH-1:0] s_eth_payload_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire [ID_WIDTH-1:0] s_eth_payload_axis_tid,
input wire [DEST_WIDTH-1:0] s_eth_payload_axis_tdest,
input wire [USER_WIDTH-1:0] s_eth_payload_axis_tuser,
/*
* Ethernet frame outputs
*/
output wire [M_COUNT-1:0] m_eth_hdr_valid,
input wire [M_COUNT-1:0] m_eth_hdr_ready,
output wire [M_COUNT*48-1:0] m_eth_dest_mac,
output wire [M_COUNT*48-1:0] m_eth_src_mac,
output wire [M_COUNT*16-1:0] m_eth_type,
output wire [M_COUNT*DATA_WIDTH-1:0] m_eth_payload_axis_tdata,
output wire [M_COUNT*KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep,
output wire [M_COUNT-1:0] m_eth_payload_axis_tvalid,
input wire [M_COUNT-1:0] m_eth_payload_axis_tready,
output wire [M_COUNT-1:0] m_eth_payload_axis_tlast,
output wire [M_COUNT*ID_WIDTH-1:0] m_eth_payload_axis_tid,
output wire [M_COUNT*DEST_WIDTH-1:0] m_eth_payload_axis_tdest,
output wire [M_COUNT*USER_WIDTH-1:0] m_eth_payload_axis_tuser,
/*
* Control
*/
input wire enable,
input wire drop,
input wire [$clog2(M_COUNT)-1:0] select
);
parameter CL_M_COUNT = $clog2(M_COUNT);
reg [CL_M_COUNT-1:0] select_reg = {CL_M_COUNT{1'b0}}, select_ctl, select_next;
reg drop_reg = 1'b0, drop_ctl, drop_next;
reg frame_reg = 1'b0, frame_ctl, frame_next;
reg s_eth_hdr_ready_reg = 1'b0, s_eth_hdr_ready_next;
reg s_eth_payload_axis_tready_reg = 1'b0, s_eth_payload_axis_tready_next;
reg [M_COUNT-1:0] m_eth_hdr_valid_reg = 0, m_eth_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_int;
reg [M_COUNT-1:0] m_eth_payload_axis_tvalid_int;
reg m_eth_payload_axis_tready_int_reg = 1'b0;
reg m_eth_payload_axis_tlast_int;
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_int;
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_int;
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_int;
wire m_eth_payload_axis_tready_int_early;
assign s_eth_hdr_ready = s_eth_hdr_ready_reg && enable;
assign s_eth_payload_axis_tready = s_eth_payload_axis_tready_reg && enable;
assign m_eth_hdr_valid = m_eth_hdr_valid_reg;
assign m_eth_dest_mac = {M_COUNT{m_eth_dest_mac_reg}};
assign m_eth_src_mac = {M_COUNT{m_eth_src_mac_reg}};
assign m_eth_type = {M_COUNT{m_eth_type_reg}};
integer i;
always @* begin
select_next = select_reg;
select_ctl = select_reg;
drop_next = drop_reg;
drop_ctl = drop_reg;
frame_next = frame_reg;
frame_ctl = frame_reg;
s_eth_hdr_ready_next = 1'b0;
s_eth_payload_axis_tready_next = 1'b0;
m_eth_hdr_valid_next = m_eth_hdr_valid_reg & ~m_eth_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
if (s_eth_payload_axis_tvalid && s_eth_payload_axis_tready) begin
// end of frame detection
if (s_eth_payload_axis_tlast) begin
frame_next = 1'b0;
drop_next = 1'b0;
end
end
if (!frame_reg && s_eth_hdr_valid && s_eth_hdr_ready) begin
// start of frame, grab select value
select_ctl = select;
drop_ctl = drop;
frame_ctl = 1'b1;
select_next = select_ctl;
drop_next = drop_ctl;
frame_next = frame_ctl;
s_eth_hdr_ready_next = 1'b0;
m_eth_hdr_valid_next = (!drop_ctl) << select_ctl;
m_eth_dest_mac_next = s_eth_dest_mac;
m_eth_src_mac_next = s_eth_src_mac;
m_eth_type_next = s_eth_type;
end
s_eth_hdr_ready_next = !frame_next && !m_eth_hdr_valid_next;
s_eth_payload_axis_tready_next = (m_eth_payload_axis_tready_int_early || drop_ctl) && frame_ctl;
m_eth_payload_axis_tdata_int = s_eth_payload_axis_tdata;
m_eth_payload_axis_tkeep_int = s_eth_payload_axis_tkeep;
m_eth_payload_axis_tvalid_int = (s_eth_payload_axis_tvalid && s_eth_payload_axis_tready && !drop_ctl) << select_ctl;
m_eth_payload_axis_tlast_int = s_eth_payload_axis_tlast;
m_eth_payload_axis_tid_int = s_eth_payload_axis_tid;
m_eth_payload_axis_tdest_int = s_eth_payload_axis_tdest;
m_eth_payload_axis_tuser_int = s_eth_payload_axis_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= 2'd0;
drop_reg <= 1'b0;
frame_reg <= 1'b0;
s_eth_hdr_ready_reg <= 1'b0;
s_eth_payload_axis_tready_reg <= 1'b0;
m_eth_hdr_valid_reg <= 0;
end else begin
select_reg <= select_next;
drop_reg <= drop_next;
frame_reg <= frame_next;
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
s_eth_payload_axis_tready_reg <= s_eth_payload_axis_tready_next;
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
end
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg [M_COUNT-1:0] m_eth_payload_axis_tvalid_reg = {M_COUNT{1'b0}}, m_eth_payload_axis_tvalid_next;
reg m_eth_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg [M_COUNT-1:0] temp_m_eth_payload_axis_tvalid_reg = {M_COUNT{1'b0}}, temp_m_eth_payload_axis_tvalid_next;
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_eth_payload_axis_temp_to_output;
assign m_eth_payload_axis_tdata = {M_COUNT{m_eth_payload_axis_tdata_reg}};
assign m_eth_payload_axis_tkeep = KEEP_ENABLE ? {M_COUNT{m_eth_payload_axis_tkeep_reg}} : {M_COUNT*KEEP_WIDTH{1'b1}};
assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
assign m_eth_payload_axis_tlast = {M_COUNT{m_eth_payload_axis_tlast_reg}};
assign m_eth_payload_axis_tid = ID_ENABLE ? {M_COUNT{m_eth_payload_axis_tid_reg}} : {M_COUNT*ID_WIDTH{1'b0}};
assign m_eth_payload_axis_tdest = DEST_ENABLE ? {M_COUNT{m_eth_payload_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
assign m_eth_payload_axis_tuser = USER_ENABLE ? {M_COUNT{m_eth_payload_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_eth_payload_axis_tready_int_early = (m_eth_payload_axis_tready & m_eth_payload_axis_tvalid) || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid || !m_eth_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b0;
if (m_eth_payload_axis_tready_int_reg) begin
// input is ready
if ((m_eth_payload_axis_tready & m_eth_payload_axis_tvalid) || !m_eth_payload_axis_tvalid) begin
// output is ready or currently not valid, transfer data to output
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_eth_payload_axis_tready & m_eth_payload_axis_tvalid) begin
// input is not ready, but output is ready
m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_eth_payload_axis_tvalid_reg <= {M_COUNT{1'b0}};
m_eth_payload_axis_tready_int_reg <= 1'b0;
temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end else if (store_eth_payload_axis_temp_to_output) begin
m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg;
m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg;
m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg;
m_eth_payload_axis_tid_reg <= temp_m_eth_payload_axis_tid_reg;
m_eth_payload_axis_tdest_reg <= temp_m_eth_payload_axis_tdest_reg;
m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
temp_m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
temp_m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end
end
endmodule

377
rtl/eth_demux_4.v
View File

@ -1,377 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Ethernet 4 port demultiplexer
*/
module eth_demux_4
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire input_eth_hdr_valid,
output wire input_eth_hdr_ready,
input wire [47:0] input_eth_dest_mac,
input wire [47:0] input_eth_src_mac,
input wire [15:0] input_eth_type,
input wire [7:0] input_eth_payload_tdata,
input wire input_eth_payload_tvalid,
output wire input_eth_payload_tready,
input wire input_eth_payload_tlast,
input wire input_eth_payload_tuser,
/*
* Ethernet frame outputs
*/
output wire output_0_eth_hdr_valid,
input wire output_0_eth_hdr_ready,
output wire [47:0] output_0_eth_dest_mac,
output wire [47:0] output_0_eth_src_mac,
output wire [15:0] output_0_eth_type,
output wire [7:0] output_0_eth_payload_tdata,
output wire output_0_eth_payload_tvalid,
input wire output_0_eth_payload_tready,
output wire output_0_eth_payload_tlast,
output wire output_0_eth_payload_tuser,
output wire output_1_eth_hdr_valid,
input wire output_1_eth_hdr_ready,
output wire [47:0] output_1_eth_dest_mac,
output wire [47:0] output_1_eth_src_mac,
output wire [15:0] output_1_eth_type,
output wire [7:0] output_1_eth_payload_tdata,
output wire output_1_eth_payload_tvalid,
input wire output_1_eth_payload_tready,
output wire output_1_eth_payload_tlast,
output wire output_1_eth_payload_tuser,
output wire output_2_eth_hdr_valid,
input wire output_2_eth_hdr_ready,
output wire [47:0] output_2_eth_dest_mac,
output wire [47:0] output_2_eth_src_mac,
output wire [15:0] output_2_eth_type,
output wire [7:0] output_2_eth_payload_tdata,
output wire output_2_eth_payload_tvalid,
input wire output_2_eth_payload_tready,
output wire output_2_eth_payload_tlast,
output wire output_2_eth_payload_tuser,
output wire output_3_eth_hdr_valid,
input wire output_3_eth_hdr_ready,
output wire [47:0] output_3_eth_dest_mac,
output wire [47:0] output_3_eth_src_mac,
output wire [15:0] output_3_eth_type,
output wire [7:0] output_3_eth_payload_tdata,
output wire output_3_eth_payload_tvalid,
input wire output_3_eth_payload_tready,
output wire output_3_eth_payload_tlast,
output wire output_3_eth_payload_tuser,
/*
* Control
*/
input wire enable,
input wire [1:0] select
);
reg [1:0] select_reg = 2'd0, select_next;
reg frame_reg = 1'b0, frame_next;
reg input_eth_hdr_ready_reg = 1'b0, input_eth_hdr_ready_next;
reg input_eth_payload_tready_reg = 1'b0, input_eth_payload_tready_next;
reg output_0_eth_hdr_valid_reg = 1'b0, output_0_eth_hdr_valid_next;
reg output_1_eth_hdr_valid_reg = 1'b0, output_1_eth_hdr_valid_next;
reg output_2_eth_hdr_valid_reg = 1'b0, output_2_eth_hdr_valid_next;
reg output_3_eth_hdr_valid_reg = 1'b0, output_3_eth_hdr_valid_next;
reg [47:0] output_eth_dest_mac_reg = 48'd0, output_eth_dest_mac_next;
reg [47:0] output_eth_src_mac_reg = 48'd0, output_eth_src_mac_next;
reg [15:0] output_eth_type_reg = 16'd0, output_eth_type_next;
// internal datapath
reg [7:0] output_eth_payload_tdata_int;
reg output_eth_payload_tvalid_int;
reg output_eth_payload_tready_int_reg = 1'b0;
reg output_eth_payload_tlast_int;
reg output_eth_payload_tuser_int;
wire output_eth_payload_tready_int_early;
assign input_eth_hdr_ready = input_eth_hdr_ready_reg;
assign input_eth_payload_tready = input_eth_payload_tready_reg;
assign output_0_eth_hdr_valid = output_0_eth_hdr_valid_reg;
assign output_0_eth_dest_mac = output_eth_dest_mac_reg;
assign output_0_eth_src_mac = output_eth_src_mac_reg;
assign output_0_eth_type = output_eth_type_reg;
assign output_1_eth_hdr_valid = output_1_eth_hdr_valid_reg;
assign output_1_eth_dest_mac = output_eth_dest_mac_reg;
assign output_1_eth_src_mac = output_eth_src_mac_reg;
assign output_1_eth_type = output_eth_type_reg;
assign output_2_eth_hdr_valid = output_2_eth_hdr_valid_reg;
assign output_2_eth_dest_mac = output_eth_dest_mac_reg;
assign output_2_eth_src_mac = output_eth_src_mac_reg;
assign output_2_eth_type = output_eth_type_reg;
assign output_3_eth_hdr_valid = output_3_eth_hdr_valid_reg;
assign output_3_eth_dest_mac = output_eth_dest_mac_reg;
assign output_3_eth_src_mac = output_eth_src_mac_reg;
assign output_3_eth_type = output_eth_type_reg;
// mux for output control signals
reg current_output_eth_hdr_valid;
reg current_output_eth_hdr_ready;
reg current_output_tvalid;
reg current_output_tready;
always @* begin
case (select_reg)
2'd0: begin
current_output_eth_hdr_valid = output_0_eth_hdr_valid;
current_output_eth_hdr_ready = output_0_eth_hdr_ready;
current_output_tvalid = output_0_eth_payload_tvalid;
current_output_tready = output_0_eth_payload_tready;
end
2'd1: begin
current_output_eth_hdr_valid = output_1_eth_hdr_valid;
current_output_eth_hdr_ready = output_1_eth_hdr_ready;
current_output_tvalid = output_1_eth_payload_tvalid;
current_output_tready = output_1_eth_payload_tready;
end
2'd2: begin
current_output_eth_hdr_valid = output_2_eth_hdr_valid;
current_output_eth_hdr_ready = output_2_eth_hdr_ready;
current_output_tvalid = output_2_eth_payload_tvalid;
current_output_tready = output_2_eth_payload_tready;
end
2'd3: begin
current_output_eth_hdr_valid = output_3_eth_hdr_valid;
current_output_eth_hdr_ready = output_3_eth_hdr_ready;
current_output_tvalid = output_3_eth_payload_tvalid;
current_output_tready = output_3_eth_payload_tready;
end
default: begin
current_output_eth_hdr_valid = 1'b0;
current_output_eth_hdr_ready = 1'b0;
current_output_tvalid = 1'b0;
current_output_tready = 1'b0;
end
endcase
end
always @* begin
select_next = select_reg;
frame_next = frame_reg;
input_eth_hdr_ready_next = input_eth_hdr_ready_reg & ~input_eth_hdr_valid;
input_eth_payload_tready_next = 1'b0;
output_0_eth_hdr_valid_next = output_0_eth_hdr_valid_reg & ~output_0_eth_hdr_ready;
output_1_eth_hdr_valid_next = output_1_eth_hdr_valid_reg & ~output_1_eth_hdr_ready;
output_2_eth_hdr_valid_next = output_2_eth_hdr_valid_reg & ~output_2_eth_hdr_ready;
output_3_eth_hdr_valid_next = output_3_eth_hdr_valid_reg & ~output_3_eth_hdr_ready;
output_eth_dest_mac_next = output_eth_dest_mac_reg;
output_eth_src_mac_next = output_eth_src_mac_reg;
output_eth_type_next = output_eth_type_reg;
if (input_eth_payload_tvalid & input_eth_payload_tready) begin
// end of frame detection
if (input_eth_payload_tlast) begin
frame_next = 1'b0;
end
end
if (~frame_reg & enable & input_eth_hdr_valid & ~current_output_eth_hdr_valid & ~current_output_tvalid) begin
// start of frame, grab select value
frame_next = 1'b1;
select_next = select;
input_eth_hdr_ready_next = 1'b1;
case (select)
2'd0: output_0_eth_hdr_valid_next = 1'b1;
2'd1: output_1_eth_hdr_valid_next = 1'b1;
2'd2: output_2_eth_hdr_valid_next = 1'b1;
2'd3: output_3_eth_hdr_valid_next = 1'b1;
endcase
output_eth_dest_mac_next = input_eth_dest_mac;
output_eth_src_mac_next = input_eth_src_mac;
output_eth_type_next = input_eth_type;
end
input_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
output_eth_payload_tdata_int = input_eth_payload_tdata;
output_eth_payload_tvalid_int = input_eth_payload_tvalid & input_eth_payload_tready;
output_eth_payload_tlast_int = input_eth_payload_tlast;
output_eth_payload_tuser_int = input_eth_payload_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= 2'd0;
frame_reg <= 1'b0;
input_eth_hdr_ready_reg <= 1'b0;
input_eth_payload_tready_reg <= 1'b0;
output_0_eth_hdr_valid_reg <= 1'b0;
output_1_eth_hdr_valid_reg <= 1'b0;
output_2_eth_hdr_valid_reg <= 1'b0;
output_3_eth_hdr_valid_reg <= 1'b0;
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
input_eth_hdr_ready_reg <= input_eth_hdr_ready_next;
input_eth_payload_tready_reg <= input_eth_payload_tready_next;
output_0_eth_hdr_valid_reg <= output_0_eth_hdr_valid_next;
output_1_eth_hdr_valid_reg <= output_1_eth_hdr_valid_next;
output_2_eth_hdr_valid_reg <= output_2_eth_hdr_valid_next;
output_3_eth_hdr_valid_reg <= output_3_eth_hdr_valid_next;
end
output_eth_dest_mac_reg <= output_eth_dest_mac_next;
output_eth_src_mac_reg <= output_eth_src_mac_next;
output_eth_type_reg <= output_eth_type_next;
end
// output datapath logic
reg [7:0] output_eth_payload_tdata_reg = 8'd0;
reg output_0_eth_payload_tvalid_reg = 1'b0, output_0_eth_payload_tvalid_next;
reg output_1_eth_payload_tvalid_reg = 1'b0, output_1_eth_payload_tvalid_next;
reg output_2_eth_payload_tvalid_reg = 1'b0, output_2_eth_payload_tvalid_next;
reg output_3_eth_payload_tvalid_reg = 1'b0, output_3_eth_payload_tvalid_next;
reg output_eth_payload_tlast_reg = 1'b0;
reg output_eth_payload_tuser_reg = 1'b0;
reg [7:0] temp_eth_payload_tdata_reg = 8'd0;
reg temp_eth_payload_tvalid_reg = 1'b0, temp_eth_payload_tvalid_next;
reg temp_eth_payload_tlast_reg = 1'b0;
reg temp_eth_payload_tuser_reg = 1'b0;
// datapath control
reg store_eth_payload_int_to_output;
reg store_eth_payload_int_to_temp;
reg store_eth_payload_temp_to_output;
assign output_0_eth_payload_tdata = output_eth_payload_tdata_reg;
assign output_0_eth_payload_tvalid = output_0_eth_payload_tvalid_reg;
assign output_0_eth_payload_tlast = output_eth_payload_tlast_reg;
assign output_0_eth_payload_tuser = output_eth_payload_tuser_reg;
assign output_1_eth_payload_tdata = output_eth_payload_tdata_reg;
assign output_1_eth_payload_tvalid = output_1_eth_payload_tvalid_reg;
assign output_1_eth_payload_tlast = output_eth_payload_tlast_reg;
assign output_1_eth_payload_tuser = output_eth_payload_tuser_reg;
assign output_2_eth_payload_tdata = output_eth_payload_tdata_reg;
assign output_2_eth_payload_tvalid = output_2_eth_payload_tvalid_reg;
assign output_2_eth_payload_tlast = output_eth_payload_tlast_reg;
assign output_2_eth_payload_tuser = output_eth_payload_tuser_reg;
assign output_3_eth_payload_tdata = output_eth_payload_tdata_reg;
assign output_3_eth_payload_tvalid = output_3_eth_payload_tvalid_reg;
assign output_3_eth_payload_tlast = output_eth_payload_tlast_reg;
assign output_3_eth_payload_tuser = output_eth_payload_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_eth_payload_tready_int_early = current_output_tready | (~temp_eth_payload_tvalid_reg & (~current_output_tvalid | ~output_eth_payload_tvalid_int));
always @* begin
// transfer sink ready state to source
output_0_eth_payload_tvalid_next = output_0_eth_payload_tvalid_reg;
output_1_eth_payload_tvalid_next = output_1_eth_payload_tvalid_reg;
output_2_eth_payload_tvalid_next = output_2_eth_payload_tvalid_reg;
output_3_eth_payload_tvalid_next = output_3_eth_payload_tvalid_reg;
temp_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg;
store_eth_payload_int_to_output = 1'b0;
store_eth_payload_int_to_temp = 1'b0;
store_eth_payload_temp_to_output = 1'b0;
if (output_eth_payload_tready_int_reg) begin
// input is ready
if (current_output_tready | ~current_output_tvalid) begin
// output is ready or currently not valid, transfer data to output
output_0_eth_payload_tvalid_next = output_eth_payload_tvalid_int & (select_reg == 2'd0);
output_1_eth_payload_tvalid_next = output_eth_payload_tvalid_int & (select_reg == 2'd1);
output_2_eth_payload_tvalid_next = output_eth_payload_tvalid_int & (select_reg == 2'd2);
output_3_eth_payload_tvalid_next = output_eth_payload_tvalid_int & (select_reg == 2'd3);
store_eth_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_eth_payload_tvalid_next = output_eth_payload_tvalid_int;
store_eth_payload_int_to_temp = 1'b1;
end
end else if (current_output_tready) begin
// input is not ready, but output is ready
output_0_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg & (select_reg == 2'd0);
output_1_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg & (select_reg == 2'd1);
output_2_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg & (select_reg == 2'd2);
output_3_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg & (select_reg == 2'd3);
temp_eth_payload_tvalid_next = 1'b0;
store_eth_payload_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
output_0_eth_payload_tvalid_reg <= 1'b0;
output_1_eth_payload_tvalid_reg <= 1'b0;
output_2_eth_payload_tvalid_reg <= 1'b0;
output_3_eth_payload_tvalid_reg <= 1'b0;
output_eth_payload_tready_int_reg <= 1'b0;
temp_eth_payload_tvalid_reg <= 1'b0;
end else begin
output_0_eth_payload_tvalid_reg <= output_0_eth_payload_tvalid_next;
output_1_eth_payload_tvalid_reg <= output_1_eth_payload_tvalid_next;
output_2_eth_payload_tvalid_reg <= output_2_eth_payload_tvalid_next;
output_3_eth_payload_tvalid_reg <= output_3_eth_payload_tvalid_next;
output_eth_payload_tready_int_reg <= output_eth_payload_tready_int_early;
temp_eth_payload_tvalid_reg <= temp_eth_payload_tvalid_next;
end
// datapath
if (store_eth_payload_int_to_output) begin
output_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
output_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
output_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
end else if (store_eth_payload_temp_to_output) begin
output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg;
output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg;
output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg;
end
if (store_eth_payload_int_to_temp) begin
temp_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
temp_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
temp_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
end
end
endmodule

353
rtl/eth_demux_64.py
View File

@ -1,353 +0,0 @@
#!/usr/bin/env python
"""
Generates an Ethernet demux with the specified number of ports
"""
from __future__ import print_function
import argparse
import math
from jinja2 import Template
def main():
parser = argparse.ArgumentParser(description=__doc__.strip())
parser.add_argument('-p', '--ports', type=int, default=4, help="number of ports")
parser.add_argument('-n', '--name', type=str, help="module name")
parser.add_argument('-o', '--output', type=str, help="output file name")
args = parser.parse_args()
try:
generate(**args.__dict__)
except IOError as ex:
print(ex)
exit(1)
def generate(ports=4, name=None, output=None):
if name is None:
name = "eth_demux_64_{0}".format(ports)
if output is None:
output = name + ".v"
print("Opening file '{0}'...".format(output))
output_file = open(output, 'w')
print("Generating {0} port Ethernet demux {1}...".format(ports, name))
select_width = int(math.ceil(math.log(ports, 2)))
t = Template(u"""/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Ethernet {{n}} port demultiplexer (64 bit datapath)
*/
module {{name}}
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire input_eth_hdr_valid,
output wire input_eth_hdr_ready,
input wire [47:0] input_eth_dest_mac,
input wire [47:0] input_eth_src_mac,
input wire [15:0] input_eth_type,
input wire [63:0] input_eth_payload_tdata,
input wire [7:0] input_eth_payload_tkeep,
input wire input_eth_payload_tvalid,
output wire input_eth_payload_tready,
input wire input_eth_payload_tlast,
input wire input_eth_payload_tuser,
/*
* Ethernet frame outputs
*/
{%- for p in ports %}
output wire output_{{p}}_eth_hdr_valid,
input wire output_{{p}}_eth_hdr_ready,
output wire [47:0] output_{{p}}_eth_dest_mac,
output wire [47:0] output_{{p}}_eth_src_mac,
output wire [15:0] output_{{p}}_eth_type,
output wire [63:0] output_{{p}}_eth_payload_tdata,
output wire [7:0] output_{{p}}_eth_payload_tkeep,
output wire output_{{p}}_eth_payload_tvalid,
input wire output_{{p}}_eth_payload_tready,
output wire output_{{p}}_eth_payload_tlast,
output wire output_{{p}}_eth_payload_tuser,
{% endfor %}
/*
* Control
*/
input wire enable,
input wire [{{w-1}}:0] select
);
reg [{{w-1}}:0] select_reg = {{w}}'d0, select_next;
reg frame_reg = 1'b0, frame_next;
reg input_eth_hdr_ready_reg = 1'b0, input_eth_hdr_ready_next;
reg input_eth_payload_tready_reg = 1'b0, input_eth_payload_tready_next;
{% for p in ports %}
reg output_{{p}}_eth_hdr_valid_reg = 1'b0, output_{{p}}_eth_hdr_valid_next;
{%- endfor %}
reg [47:0] output_eth_dest_mac_reg = 48'd0, output_eth_dest_mac_next;
reg [47:0] output_eth_src_mac_reg = 48'd0, output_eth_src_mac_next;
reg [15:0] output_eth_type_reg = 16'd0, output_eth_type_next;
// internal datapath
reg [63:0] output_eth_payload_tdata_int;
reg [7:0] output_eth_payload_tkeep_int;
reg output_eth_payload_tvalid_int;
reg output_eth_payload_tready_int_reg = 1'b0;
reg output_eth_payload_tlast_int;
reg output_eth_payload_tuser_int;
wire output_eth_payload_tready_int_early;
assign input_eth_hdr_ready = input_eth_hdr_ready_reg;
assign input_eth_payload_tready = input_eth_payload_tready_reg;
{% for p in ports %}
assign output_{{p}}_eth_hdr_valid = output_{{p}}_eth_hdr_valid_reg;
assign output_{{p}}_eth_dest_mac = output_eth_dest_mac_reg;
assign output_{{p}}_eth_src_mac = output_eth_src_mac_reg;
assign output_{{p}}_eth_type = output_eth_type_reg;
{% endfor %}
// mux for output control signals
reg current_output_eth_hdr_valid;
reg current_output_eth_hdr_ready;
reg current_output_tvalid;
reg current_output_tready;
always @* begin
case (select_reg)
{%- for p in ports %}
{{w}}'d{{p}}: begin
current_output_eth_hdr_valid = output_{{p}}_eth_hdr_valid;
current_output_eth_hdr_ready = output_{{p}}_eth_hdr_ready;
current_output_tvalid = output_{{p}}_eth_payload_tvalid;
current_output_tready = output_{{p}}_eth_payload_tready;
end
{%- endfor %}
default: begin
current_output_eth_hdr_valid = 1'b0;
current_output_eth_hdr_ready = 1'b0;
current_output_tvalid = 1'b0;
current_output_tready = 1'b0;
end
endcase
end
always @* begin
select_next = select_reg;
frame_next = frame_reg;
input_eth_hdr_ready_next = input_eth_hdr_ready_reg & ~input_eth_hdr_valid;
input_eth_payload_tready_next = 1'b0;
{%- for p in ports %}
output_{{p}}_eth_hdr_valid_next = output_{{p}}_eth_hdr_valid_reg & ~output_{{p}}_eth_hdr_ready;
{%- endfor %}
output_eth_dest_mac_next = output_eth_dest_mac_reg;
output_eth_src_mac_next = output_eth_src_mac_reg;
output_eth_type_next = output_eth_type_reg;
if (input_eth_payload_tvalid & input_eth_payload_tready) begin
// end of frame detection
if (input_eth_payload_tlast) begin
frame_next = 1'b0;
end
end
if (~frame_reg & enable & input_eth_hdr_valid & ~current_output_eth_hdr_valid & ~current_output_tvalid) begin
// start of frame, grab select value
frame_next = 1'b1;
select_next = select;
input_eth_hdr_ready_next = 1'b1;
case (select)
{%- for p in ports %}
{{w}}'d{{p}}: output_{{p}}_eth_hdr_valid_next = 1'b1;
{%- endfor %}
endcase
output_eth_dest_mac_next = input_eth_dest_mac;
output_eth_src_mac_next = input_eth_src_mac;
output_eth_type_next = input_eth_type;
end
input_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
output_eth_payload_tdata_int = input_eth_payload_tdata;
output_eth_payload_tkeep_int = input_eth_payload_tkeep;
output_eth_payload_tvalid_int = input_eth_payload_tvalid & input_eth_payload_tready;
output_eth_payload_tlast_int = input_eth_payload_tlast;
output_eth_payload_tuser_int = input_eth_payload_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= {{w}}'d0;
frame_reg <= 1'b0;
input_eth_hdr_ready_reg <= 1'b0;
input_eth_payload_tready_reg <= 1'b0;
{%- for p in ports %}
output_{{p}}_eth_hdr_valid_reg <= 1'b0;
{%- endfor %}
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
input_eth_hdr_ready_reg <= input_eth_hdr_ready_next;
input_eth_payload_tready_reg <= input_eth_payload_tready_next;
{%- for p in ports %}
output_{{p}}_eth_hdr_valid_reg <= output_{{p}}_eth_hdr_valid_next;
{%- endfor %}
end
output_eth_dest_mac_reg <= output_eth_dest_mac_next;
output_eth_src_mac_reg <= output_eth_src_mac_next;
output_eth_type_reg <= output_eth_type_next;
end
// output datapath logic
reg [63:0] output_eth_payload_tdata_reg = 64'd0;
reg [7:0] output_eth_payload_tkeep_reg = 8'd0;
{%- for p in ports %}
reg output_{{p}}_eth_payload_tvalid_reg = 1'b0, output_{{p}}_eth_payload_tvalid_next;
{%- endfor %}
reg output_eth_payload_tlast_reg = 1'b0;
reg output_eth_payload_tuser_reg = 1'b0;
reg [63:0] temp_eth_payload_tdata_reg = 64'd0;
reg [7:0] temp_eth_payload_tkeep_reg = 8'd0;
reg temp_eth_payload_tvalid_reg = 1'b0, temp_eth_payload_tvalid_next;
reg temp_eth_payload_tlast_reg = 1'b0;
reg temp_eth_payload_tuser_reg = 1'b0;
// datapath control
reg store_eth_payload_int_to_output;
reg store_eth_payload_int_to_temp;
reg store_eth_payload_temp_to_output;
{% for p in ports %}
assign output_{{p}}_eth_payload_tdata = output_eth_payload_tdata_reg;
assign output_{{p}}_eth_payload_tkeep = output_eth_payload_tkeep_reg;
assign output_{{p}}_eth_payload_tvalid = output_{{p}}_eth_payload_tvalid_reg;
assign output_{{p}}_eth_payload_tlast = output_eth_payload_tlast_reg;
assign output_{{p}}_eth_payload_tuser = output_eth_payload_tuser_reg;
{% endfor %}
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_eth_payload_tready_int_early = current_output_tready | (~temp_eth_payload_tvalid_reg & (~current_output_tvalid | ~output_eth_payload_tvalid_int));
always @* begin
// transfer sink ready state to source
{%- for p in ports %}
output_{{p}}_eth_payload_tvalid_next = output_{{p}}_eth_payload_tvalid_reg;
{%- endfor %}
temp_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg;
store_eth_payload_int_to_output = 1'b0;
store_eth_payload_int_to_temp = 1'b0;
store_eth_payload_temp_to_output = 1'b0;
if (output_eth_payload_tready_int_reg) begin
// input is ready
if (current_output_tready | ~current_output_tvalid) begin
// output is ready or currently not valid, transfer data to output
{%- for p in ports %}
output_{{p}}_eth_payload_tvalid_next = output_eth_payload_tvalid_int & (select_reg == {{w}}'d{{p}});
{%- endfor %}
store_eth_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_eth_payload_tvalid_next = output_eth_payload_tvalid_int;
store_eth_payload_int_to_temp = 1'b1;
end
end else if (current_output_tready) begin
// input is not ready, but output is ready
{%- for p in ports %}
output_{{p}}_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg & (select_reg == {{w}}'d{{p}});
{%- endfor %}
temp_eth_payload_tvalid_next = 1'b0;
store_eth_payload_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
{%- for p in ports %}
output_{{p}}_eth_payload_tvalid_reg <= 1'b0;
{%- endfor %}
output_eth_payload_tready_int_reg <= 1'b0;
temp_eth_payload_tvalid_reg <= 1'b0;
end else begin
{%- for p in ports %}
output_{{p}}_eth_payload_tvalid_reg <= output_{{p}}_eth_payload_tvalid_next;
{%- endfor %}
output_eth_payload_tready_int_reg <= output_eth_payload_tready_int_early;
temp_eth_payload_tvalid_reg <= temp_eth_payload_tvalid_next;
end
// datapath
if (store_eth_payload_int_to_output) begin
output_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
output_eth_payload_tkeep_reg <= output_eth_payload_tkeep_int;
output_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
output_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
end else if (store_eth_payload_temp_to_output) begin
output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg;
output_eth_payload_tkeep_reg <= temp_eth_payload_tkeep_reg;
output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg;
output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg;
end
if (store_eth_payload_int_to_temp) begin
temp_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
temp_eth_payload_tkeep_reg <= output_eth_payload_tkeep_int;
temp_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
temp_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
end
end
endmodule
""")
output_file.write(t.render(
n=ports,
w=select_width,
name=name,
ports=range(ports)
))
print("Done")
if __name__ == "__main__":
main()

393
rtl/eth_demux_64_4.v
View File

@ -1,393 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Ethernet 4 port demultiplexer (64 bit datapath)
*/
module eth_demux_64_4
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire input_eth_hdr_valid,
output wire input_eth_hdr_ready,
input wire [47:0] input_eth_dest_mac,
input wire [47:0] input_eth_src_mac,
input wire [15:0] input_eth_type,
input wire [63:0] input_eth_payload_tdata,
input wire [7:0] input_eth_payload_tkeep,
input wire input_eth_payload_tvalid,
output wire input_eth_payload_tready,
input wire input_eth_payload_tlast,
input wire input_eth_payload_tuser,
/*
* Ethernet frame outputs
*/
output wire output_0_eth_hdr_valid,
input wire output_0_eth_hdr_ready,
output wire [47:0] output_0_eth_dest_mac,
output wire [47:0] output_0_eth_src_mac,
output wire [15:0] output_0_eth_type,
output wire [63:0] output_0_eth_payload_tdata,
output wire [7:0] output_0_eth_payload_tkeep,
output wire output_0_eth_payload_tvalid,
input wire output_0_eth_payload_tready,
output wire output_0_eth_payload_tlast,
output wire output_0_eth_payload_tuser,
output wire output_1_eth_hdr_valid,
input wire output_1_eth_hdr_ready,
output wire [47:0] output_1_eth_dest_mac,
output wire [47:0] output_1_eth_src_mac,
output wire [15:0] output_1_eth_type,
output wire [63:0] output_1_eth_payload_tdata,
output wire [7:0] output_1_eth_payload_tkeep,
output wire output_1_eth_payload_tvalid,
input wire output_1_eth_payload_tready,
output wire output_1_eth_payload_tlast,
output wire output_1_eth_payload_tuser,
output wire output_2_eth_hdr_valid,
input wire output_2_eth_hdr_ready,
output wire [47:0] output_2_eth_dest_mac,
output wire [47:0] output_2_eth_src_mac,
output wire [15:0] output_2_eth_type,
output wire [63:0] output_2_eth_payload_tdata,
output wire [7:0] output_2_eth_payload_tkeep,
output wire output_2_eth_payload_tvalid,
input wire output_2_eth_payload_tready,
output wire output_2_eth_payload_tlast,
output wire output_2_eth_payload_tuser,
output wire output_3_eth_hdr_valid,
input wire output_3_eth_hdr_ready,
output wire [47:0] output_3_eth_dest_mac,
output wire [47:0] output_3_eth_src_mac,
output wire [15:0] output_3_eth_type,
output wire [63:0] output_3_eth_payload_tdata,
output wire [7:0] output_3_eth_payload_tkeep,
output wire output_3_eth_payload_tvalid,
input wire output_3_eth_payload_tready,
output wire output_3_eth_payload_tlast,
output wire output_3_eth_payload_tuser,
/*
* Control
*/
input wire enable,
input wire [1:0] select
);
reg [1:0] select_reg = 2'd0, select_next;
reg frame_reg = 1'b0, frame_next;
reg input_eth_hdr_ready_reg = 1'b0, input_eth_hdr_ready_next;
reg input_eth_payload_tready_reg = 1'b0, input_eth_payload_tready_next;
reg output_0_eth_hdr_valid_reg = 1'b0, output_0_eth_hdr_valid_next;
reg output_1_eth_hdr_valid_reg = 1'b0, output_1_eth_hdr_valid_next;
reg output_2_eth_hdr_valid_reg = 1'b0, output_2_eth_hdr_valid_next;
reg output_3_eth_hdr_valid_reg = 1'b0, output_3_eth_hdr_valid_next;
reg [47:0] output_eth_dest_mac_reg = 48'd0, output_eth_dest_mac_next;
reg [47:0] output_eth_src_mac_reg = 48'd0, output_eth_src_mac_next;
reg [15:0] output_eth_type_reg = 16'd0, output_eth_type_next;
// internal datapath
reg [63:0] output_eth_payload_tdata_int;
reg [7:0] output_eth_payload_tkeep_int;
reg output_eth_payload_tvalid_int;
reg output_eth_payload_tready_int_reg = 1'b0;
reg output_eth_payload_tlast_int;
reg output_eth_payload_tuser_int;
wire output_eth_payload_tready_int_early;
assign input_eth_hdr_ready = input_eth_hdr_ready_reg;
assign input_eth_payload_tready = input_eth_payload_tready_reg;
assign output_0_eth_hdr_valid = output_0_eth_hdr_valid_reg;
assign output_0_eth_dest_mac = output_eth_dest_mac_reg;
assign output_0_eth_src_mac = output_eth_src_mac_reg;
assign output_0_eth_type = output_eth_type_reg;
assign output_1_eth_hdr_valid = output_1_eth_hdr_valid_reg;
assign output_1_eth_dest_mac = output_eth_dest_mac_reg;
assign output_1_eth_src_mac = output_eth_src_mac_reg;
assign output_1_eth_type = output_eth_type_reg;
assign output_2_eth_hdr_valid = output_2_eth_hdr_valid_reg;
assign output_2_eth_dest_mac = output_eth_dest_mac_reg;
assign output_2_eth_src_mac = output_eth_src_mac_reg;
assign output_2_eth_type = output_eth_type_reg;
assign output_3_eth_hdr_valid = output_3_eth_hdr_valid_reg;
assign output_3_eth_dest_mac = output_eth_dest_mac_reg;
assign output_3_eth_src_mac = output_eth_src_mac_reg;
assign output_3_eth_type = output_eth_type_reg;
// mux for output control signals
reg current_output_eth_hdr_valid;
reg current_output_eth_hdr_ready;
reg current_output_tvalid;
reg current_output_tready;
always @* begin
case (select_reg)
2'd0: begin
current_output_eth_hdr_valid = output_0_eth_hdr_valid;
current_output_eth_hdr_ready = output_0_eth_hdr_ready;
current_output_tvalid = output_0_eth_payload_tvalid;
current_output_tready = output_0_eth_payload_tready;
end
2'd1: begin
current_output_eth_hdr_valid = output_1_eth_hdr_valid;
current_output_eth_hdr_ready = output_1_eth_hdr_ready;
current_output_tvalid = output_1_eth_payload_tvalid;
current_output_tready = output_1_eth_payload_tready;
end
2'd2: begin
current_output_eth_hdr_valid = output_2_eth_hdr_valid;
current_output_eth_hdr_ready = output_2_eth_hdr_ready;
current_output_tvalid = output_2_eth_payload_tvalid;
current_output_tready = output_2_eth_payload_tready;
end
2'd3: begin
current_output_eth_hdr_valid = output_3_eth_hdr_valid;
current_output_eth_hdr_ready = output_3_eth_hdr_ready;
current_output_tvalid = output_3_eth_payload_tvalid;
current_output_tready = output_3_eth_payload_tready;
end
default: begin
current_output_eth_hdr_valid = 1'b0;
current_output_eth_hdr_ready = 1'b0;
current_output_tvalid = 1'b0;
current_output_tready = 1'b0;
end
endcase
end
always @* begin
select_next = select_reg;
frame_next = frame_reg;
input_eth_hdr_ready_next = input_eth_hdr_ready_reg & ~input_eth_hdr_valid;
input_eth_payload_tready_next = 1'b0;
output_0_eth_hdr_valid_next = output_0_eth_hdr_valid_reg & ~output_0_eth_hdr_ready;
output_1_eth_hdr_valid_next = output_1_eth_hdr_valid_reg & ~output_1_eth_hdr_ready;
output_2_eth_hdr_valid_next = output_2_eth_hdr_valid_reg & ~output_2_eth_hdr_ready;
output_3_eth_hdr_valid_next = output_3_eth_hdr_valid_reg & ~output_3_eth_hdr_ready;
output_eth_dest_mac_next = output_eth_dest_mac_reg;
output_eth_src_mac_next = output_eth_src_mac_reg;
output_eth_type_next = output_eth_type_reg;
if (input_eth_payload_tvalid & input_eth_payload_tready) begin
// end of frame detection
if (input_eth_payload_tlast) begin
frame_next = 1'b0;
end
end
if (~frame_reg & enable & input_eth_hdr_valid & ~current_output_eth_hdr_valid & ~current_output_tvalid) begin
// start of frame, grab select value
frame_next = 1'b1;
select_next = select;
input_eth_hdr_ready_next = 1'b1;
case (select)
2'd0: output_0_eth_hdr_valid_next = 1'b1;
2'd1: output_1_eth_hdr_valid_next = 1'b1;
2'd2: output_2_eth_hdr_valid_next = 1'b1;
2'd3: output_3_eth_hdr_valid_next = 1'b1;
endcase
output_eth_dest_mac_next = input_eth_dest_mac;
output_eth_src_mac_next = input_eth_src_mac;
output_eth_type_next = input_eth_type;
end
input_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
output_eth_payload_tdata_int = input_eth_payload_tdata;
output_eth_payload_tkeep_int = input_eth_payload_tkeep;
output_eth_payload_tvalid_int = input_eth_payload_tvalid & input_eth_payload_tready;
output_eth_payload_tlast_int = input_eth_payload_tlast;
output_eth_payload_tuser_int = input_eth_payload_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= 2'd0;
frame_reg <= 1'b0;
input_eth_hdr_ready_reg <= 1'b0;
input_eth_payload_tready_reg <= 1'b0;
output_0_eth_hdr_valid_reg <= 1'b0;
output_1_eth_hdr_valid_reg <= 1'b0;
output_2_eth_hdr_valid_reg <= 1'b0;
output_3_eth_hdr_valid_reg <= 1'b0;
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
input_eth_hdr_ready_reg <= input_eth_hdr_ready_next;
input_eth_payload_tready_reg <= input_eth_payload_tready_next;
output_0_eth_hdr_valid_reg <= output_0_eth_hdr_valid_next;
output_1_eth_hdr_valid_reg <= output_1_eth_hdr_valid_next;
output_2_eth_hdr_valid_reg <= output_2_eth_hdr_valid_next;
output_3_eth_hdr_valid_reg <= output_3_eth_hdr_valid_next;
end
output_eth_dest_mac_reg <= output_eth_dest_mac_next;
output_eth_src_mac_reg <= output_eth_src_mac_next;
output_eth_type_reg <= output_eth_type_next;
end
// output datapath logic
reg [63:0] output_eth_payload_tdata_reg = 64'd0;
reg [7:0] output_eth_payload_tkeep_reg = 8'd0;
reg output_0_eth_payload_tvalid_reg = 1'b0, output_0_eth_payload_tvalid_next;
reg output_1_eth_payload_tvalid_reg = 1'b0, output_1_eth_payload_tvalid_next;
reg output_2_eth_payload_tvalid_reg = 1'b0, output_2_eth_payload_tvalid_next;
reg output_3_eth_payload_tvalid_reg = 1'b0, output_3_eth_payload_tvalid_next;
reg output_eth_payload_tlast_reg = 1'b0;
reg output_eth_payload_tuser_reg = 1'b0;
reg [63:0] temp_eth_payload_tdata_reg = 64'd0;
reg [7:0] temp_eth_payload_tkeep_reg = 8'd0;
reg temp_eth_payload_tvalid_reg = 1'b0, temp_eth_payload_tvalid_next;
reg temp_eth_payload_tlast_reg = 1'b0;
reg temp_eth_payload_tuser_reg = 1'b0;
// datapath control
reg store_eth_payload_int_to_output;
reg store_eth_payload_int_to_temp;
reg store_eth_payload_temp_to_output;
assign output_0_eth_payload_tdata = output_eth_payload_tdata_reg;
assign output_0_eth_payload_tkeep = output_eth_payload_tkeep_reg;
assign output_0_eth_payload_tvalid = output_0_eth_payload_tvalid_reg;
assign output_0_eth_payload_tlast = output_eth_payload_tlast_reg;
assign output_0_eth_payload_tuser = output_eth_payload_tuser_reg;
assign output_1_eth_payload_tdata = output_eth_payload_tdata_reg;
assign output_1_eth_payload_tkeep = output_eth_payload_tkeep_reg;
assign output_1_eth_payload_tvalid = output_1_eth_payload_tvalid_reg;
assign output_1_eth_payload_tlast = output_eth_payload_tlast_reg;
assign output_1_eth_payload_tuser = output_eth_payload_tuser_reg;
assign output_2_eth_payload_tdata = output_eth_payload_tdata_reg;
assign output_2_eth_payload_tkeep = output_eth_payload_tkeep_reg;
assign output_2_eth_payload_tvalid = output_2_eth_payload_tvalid_reg;
assign output_2_eth_payload_tlast = output_eth_payload_tlast_reg;
assign output_2_eth_payload_tuser = output_eth_payload_tuser_reg;
assign output_3_eth_payload_tdata = output_eth_payload_tdata_reg;
assign output_3_eth_payload_tkeep = output_eth_payload_tkeep_reg;
assign output_3_eth_payload_tvalid = output_3_eth_payload_tvalid_reg;
assign output_3_eth_payload_tlast = output_eth_payload_tlast_reg;
assign output_3_eth_payload_tuser = output_eth_payload_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_eth_payload_tready_int_early = current_output_tready | (~temp_eth_payload_tvalid_reg & (~current_output_tvalid | ~output_eth_payload_tvalid_int));
always @* begin
// transfer sink ready state to source
output_0_eth_payload_tvalid_next = output_0_eth_payload_tvalid_reg;
output_1_eth_payload_tvalid_next = output_1_eth_payload_tvalid_reg;
output_2_eth_payload_tvalid_next = output_2_eth_payload_tvalid_reg;
output_3_eth_payload_tvalid_next = output_3_eth_payload_tvalid_reg;
temp_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg;
store_eth_payload_int_to_output = 1'b0;
store_eth_payload_int_to_temp = 1'b0;
store_eth_payload_temp_to_output = 1'b0;
if (output_eth_payload_tready_int_reg) begin
// input is ready
if (current_output_tready | ~current_output_tvalid) begin
// output is ready or currently not valid, transfer data to output
output_0_eth_payload_tvalid_next = output_eth_payload_tvalid_int & (select_reg == 2'd0);
output_1_eth_payload_tvalid_next = output_eth_payload_tvalid_int & (select_reg == 2'd1);
output_2_eth_payload_tvalid_next = output_eth_payload_tvalid_int & (select_reg == 2'd2);
output_3_eth_payload_tvalid_next = output_eth_payload_tvalid_int & (select_reg == 2'd3);
store_eth_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_eth_payload_tvalid_next = output_eth_payload_tvalid_int;
store_eth_payload_int_to_temp = 1'b1;
end
end else if (current_output_tready) begin
// input is not ready, but output is ready
output_0_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg & (select_reg == 2'd0);
output_1_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg & (select_reg == 2'd1);
output_2_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg & (select_reg == 2'd2);
output_3_eth_payload_tvalid_next = temp_eth_payload_tvalid_reg & (select_reg == 2'd3);
temp_eth_payload_tvalid_next = 1'b0;
store_eth_payload_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
output_0_eth_payload_tvalid_reg <= 1'b0;
output_1_eth_payload_tvalid_reg <= 1'b0;
output_2_eth_payload_tvalid_reg <= 1'b0;
output_3_eth_payload_tvalid_reg <= 1'b0;
output_eth_payload_tready_int_reg <= 1'b0;
temp_eth_payload_tvalid_reg <= 1'b0;
end else begin
output_0_eth_payload_tvalid_reg <= output_0_eth_payload_tvalid_next;
output_1_eth_payload_tvalid_reg <= output_1_eth_payload_tvalid_next;
output_2_eth_payload_tvalid_reg <= output_2_eth_payload_tvalid_next;
output_3_eth_payload_tvalid_reg <= output_3_eth_payload_tvalid_next;
output_eth_payload_tready_int_reg <= output_eth_payload_tready_int_early;
temp_eth_payload_tvalid_reg <= temp_eth_payload_tvalid_next;
end
// datapath
if (store_eth_payload_int_to_output) begin
output_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
output_eth_payload_tkeep_reg <= output_eth_payload_tkeep_int;
output_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
output_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
end else if (store_eth_payload_temp_to_output) begin
output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg;
output_eth_payload_tkeep_reg <= temp_eth_payload_tkeep_reg;
output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg;
output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg;
end
if (store_eth_payload_int_to_temp) begin
temp_eth_payload_tdata_reg <= output_eth_payload_tdata_int;
temp_eth_payload_tkeep_reg <= output_eth_payload_tkeep_int;
temp_eth_payload_tlast_reg <= output_eth_payload_tlast_int;
temp_eth_payload_tuser_reg <= output_eth_payload_tuser_int;
end
end
endmodule

421
tb/test_eth_demux_4.py
View File

@ -28,8 +28,8 @@ import os
import eth_ep import eth_ep
module = 'eth_demux_4' module = 'eth_demux'
testbench = 'test_%s' % module testbench = 'test_%s_4' % module
srcs = [] srcs = []
@ -42,170 +42,123 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench(): def bench():
# Parameters
M_COUNT = 4
DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))
rst = Signal(bool(0)) rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_eth_hdr_valid = Signal(bool(0)) s_eth_hdr_valid = Signal(bool(0))
input_eth_dest_mac = Signal(intbv(0)[48:]) s_eth_dest_mac = Signal(intbv(0)[48:])
input_eth_src_mac = Signal(intbv(0)[48:]) s_eth_src_mac = Signal(intbv(0)[48:])
input_eth_type = Signal(intbv(0)[16:]) s_eth_type = Signal(intbv(0)[16:])
input_eth_payload_tdata = Signal(intbv(0)[8:]) s_eth_payload_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_eth_payload_tvalid = Signal(bool(0)) s_eth_payload_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_eth_payload_tlast = Signal(bool(0)) s_eth_payload_axis_tvalid = Signal(bool(0))
input_eth_payload_tuser = Signal(bool(0)) s_eth_payload_axis_tlast = Signal(bool(0))
s_eth_payload_axis_tid = Signal(intbv(0)[ID_WIDTH:])
s_eth_payload_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
s_eth_payload_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_0_eth_hdr_ready = Signal(bool(0)) m_eth_hdr_ready_list = [Signal(bool(0)) for i in range(M_COUNT)]
output_0_eth_payload_tready = Signal(bool(0)) m_eth_payload_axis_tready_list = [Signal(bool(0)) for i in range(M_COUNT)]
output_1_eth_hdr_ready = Signal(bool(0))
output_1_eth_payload_tready = Signal(bool(0)) m_eth_hdr_ready = ConcatSignal(*reversed(m_eth_hdr_ready_list))
output_2_eth_hdr_ready = Signal(bool(0)) m_eth_payload_axis_tready = ConcatSignal(*reversed(m_eth_payload_axis_tready_list))
output_2_eth_payload_tready = Signal(bool(0))
output_3_eth_hdr_ready = Signal(bool(0))
output_3_eth_payload_tready = Signal(bool(0))
enable = Signal(bool(0)) enable = Signal(bool(0))
drop = Signal(bool(0))
select = Signal(intbv(0)[2:]) select = Signal(intbv(0)[2:])
# Outputs # Outputs
input_eth_hdr_ready = Signal(bool(0)) s_eth_hdr_ready = Signal(bool(0))
input_eth_payload_tready = Signal(bool(0)) s_eth_payload_axis_tready = Signal(bool(0))
output_0_eth_hdr_valid = Signal(bool(0)) m_eth_hdr_valid = Signal(intbv(0)[M_COUNT:])
output_0_eth_dest_mac = Signal(intbv(0)[48:]) m_eth_dest_mac = Signal(intbv(0)[M_COUNT*48:])
output_0_eth_src_mac = Signal(intbv(0)[48:]) m_eth_src_mac = Signal(intbv(0)[M_COUNT*48:])
output_0_eth_type = Signal(intbv(0)[16:]) m_eth_type = Signal(intbv(0)[M_COUNT*16:])
output_0_eth_payload_tdata = Signal(intbv(0)[8:]) m_eth_payload_axis_tdata = Signal(intbv(0)[M_COUNT*DATA_WIDTH:])
output_0_eth_payload_tvalid = Signal(bool(0)) m_eth_payload_axis_tkeep = Signal(intbv(0xf)[M_COUNT*KEEP_WIDTH:])
output_0_eth_payload_tlast = Signal(bool(0)) m_eth_payload_axis_tvalid = Signal(intbv(0)[M_COUNT:])
output_0_eth_payload_tuser = Signal(bool(0)) m_eth_payload_axis_tlast = Signal(intbv(0)[M_COUNT:])
output_1_eth_hdr_valid = Signal(bool(0)) m_eth_payload_axis_tid = Signal(intbv(0)[M_COUNT*ID_WIDTH:])
output_1_eth_dest_mac = Signal(intbv(0)[48:]) m_eth_payload_axis_tdest = Signal(intbv(0)[M_COUNT*DEST_WIDTH:])
output_1_eth_src_mac = Signal(intbv(0)[48:]) m_eth_payload_axis_tuser = Signal(intbv(0)[M_COUNT*USER_WIDTH:])
output_1_eth_type = Signal(intbv(0)[16:])
output_1_eth_payload_tdata = Signal(intbv(0)[8:]) m_eth_hdr_valid_list = [m_eth_hdr_valid(i) for i in range(M_COUNT)]
output_1_eth_payload_tvalid = Signal(bool(0)) m_eth_dest_mac_list = [m_eth_dest_mac((i+1)*48, i*48) for i in range(M_COUNT)]
output_1_eth_payload_tlast = Signal(bool(0)) m_eth_src_mac_list = [m_eth_src_mac((i+1)*48, i*48) for i in range(M_COUNT)]
output_1_eth_payload_tuser = Signal(bool(0)) m_eth_type_list = [m_eth_type((i+1)*16, i*16) for i in range(M_COUNT)]
output_2_eth_hdr_valid = Signal(bool(0)) m_eth_payload_axis_tdata_list = [m_eth_payload_axis_tdata((i+1)*DATA_WIDTH, i*DATA_WIDTH) for i in range(M_COUNT)]
output_2_eth_dest_mac = Signal(intbv(0)[48:]) m_eth_payload_axis_tkeep_list = [m_eth_payload_axis_tkeep((i+1)*KEEP_WIDTH, i*KEEP_WIDTH) for i in range(M_COUNT)]
output_2_eth_src_mac = Signal(intbv(0)[48:]) m_eth_payload_axis_tvalid_list = [m_eth_payload_axis_tvalid(i) for i in range(M_COUNT)]
output_2_eth_type = Signal(intbv(0)[16:]) m_eth_payload_axis_tlast_list = [m_eth_payload_axis_tlast(i) for i in range(M_COUNT)]
output_2_eth_payload_tdata = Signal(intbv(0)[8:]) m_eth_payload_axis_tid_list = [m_eth_payload_axis_tid((i+1)*ID_WIDTH, i*ID_WIDTH) for i in range(M_COUNT)]
output_2_eth_payload_tvalid = Signal(bool(0)) m_eth_payload_axis_tdest_list = [m_eth_payload_axis_tdest((i+1)*DEST_WIDTH, i*DEST_WIDTH) for i in range(M_COUNT)]
output_2_eth_payload_tlast = Signal(bool(0)) m_eth_payload_axis_tuser_list = [m_eth_payload_axis_tuser((i+1)*USER_WIDTH, i*USER_WIDTH) for i in range(M_COUNT)]
output_2_eth_payload_tuser = Signal(bool(0))
output_3_eth_hdr_valid = Signal(bool(0))
output_3_eth_dest_mac = Signal(intbv(0)[48:])
output_3_eth_src_mac = Signal(intbv(0)[48:])
output_3_eth_type = Signal(intbv(0)[16:])
output_3_eth_payload_tdata = Signal(intbv(0)[8:])
output_3_eth_payload_tvalid = Signal(bool(0))
output_3_eth_payload_tlast = Signal(bool(0))
output_3_eth_payload_tuser = Signal(bool(0))
# sources and sinks # sources and sinks
source_pause = Signal(bool(0)) source_pause = Signal(bool(0))
sink_0_pause = Signal(bool(0)) sink_pause_list = []
sink_1_pause = Signal(bool(0)) sink_list = []
sink_2_pause = Signal(bool(0)) sink_logic_list = []
sink_3_pause = Signal(bool(0))
source = eth_ep.EthFrameSource() source = eth_ep.EthFrameSource()
source_logic = source.create_logic( source_logic = source.create_logic(
clk, clk,
rst, rst,
eth_hdr_ready=input_eth_hdr_ready, eth_hdr_ready=s_eth_hdr_ready,
eth_hdr_valid=input_eth_hdr_valid, eth_hdr_valid=s_eth_hdr_valid,
eth_dest_mac=input_eth_dest_mac, eth_dest_mac=s_eth_dest_mac,
eth_src_mac=input_eth_src_mac, eth_src_mac=s_eth_src_mac,
eth_type=input_eth_type, eth_type=s_eth_type,
eth_payload_tdata=input_eth_payload_tdata, eth_payload_tdata=s_eth_payload_axis_tdata,
eth_payload_tvalid=input_eth_payload_tvalid, eth_payload_tkeep=s_eth_payload_axis_tkeep,
eth_payload_tready=input_eth_payload_tready, eth_payload_tvalid=s_eth_payload_axis_tvalid,
eth_payload_tlast=input_eth_payload_tlast, eth_payload_tready=s_eth_payload_axis_tready,
eth_payload_tuser=input_eth_payload_tuser, eth_payload_tlast=s_eth_payload_axis_tlast,
eth_payload_tuser=s_eth_payload_axis_tuser,
pause=source_pause, pause=source_pause,
name='source' name='source'
) )
sink_0 = eth_ep.EthFrameSink() for k in range(M_COUNT):
s = eth_ep.EthFrameSink()
p = Signal(bool(0))
sink_0_logic = sink_0.create_logic( sink_list.append(s)
clk, sink_pause_list.append(p)
rst,
eth_hdr_ready=output_0_eth_hdr_ready,
eth_hdr_valid=output_0_eth_hdr_valid,
eth_dest_mac=output_0_eth_dest_mac,
eth_src_mac=output_0_eth_src_mac,
eth_type=output_0_eth_type,
eth_payload_tdata=output_0_eth_payload_tdata,
eth_payload_tvalid=output_0_eth_payload_tvalid,
eth_payload_tready=output_0_eth_payload_tready,
eth_payload_tlast=output_0_eth_payload_tlast,
eth_payload_tuser=output_0_eth_payload_tuser,
pause=sink_0_pause,
name='sink_0'
)
sink_1 = eth_ep.EthFrameSink() sink_logic_list.append(s.create_logic(
clk,
sink_1_logic = sink_1.create_logic( rst,
clk, eth_hdr_ready=m_eth_hdr_ready_list[k],
rst, eth_hdr_valid=m_eth_hdr_valid_list[k],
eth_hdr_ready=output_1_eth_hdr_ready, eth_dest_mac=m_eth_dest_mac_list[k],
eth_hdr_valid=output_1_eth_hdr_valid, eth_src_mac=m_eth_src_mac_list[k],
eth_dest_mac=output_1_eth_dest_mac, eth_type=m_eth_type_list[k],
eth_src_mac=output_1_eth_src_mac, eth_payload_tdata=m_eth_payload_axis_tdata_list[k],
eth_type=output_1_eth_type, eth_payload_tkeep=m_eth_payload_axis_tkeep_list[k],
eth_payload_tdata=output_1_eth_payload_tdata, eth_payload_tvalid=m_eth_payload_axis_tvalid_list[k],
eth_payload_tvalid=output_1_eth_payload_tvalid, eth_payload_tready=m_eth_payload_axis_tready_list[k],
eth_payload_tready=output_1_eth_payload_tready, eth_payload_tlast=m_eth_payload_axis_tlast_list[k],
eth_payload_tlast=output_1_eth_payload_tlast, eth_payload_tuser=m_eth_payload_axis_tuser_list[k],
eth_payload_tuser=output_1_eth_payload_tuser, pause=p,
pause=sink_1_pause, name='sink_%d' % k
name='sink_1' ))
)
sink_2 = eth_ep.EthFrameSink()
sink_2_logic = sink_2.create_logic(
clk,
rst,
eth_hdr_ready=output_2_eth_hdr_ready,
eth_hdr_valid=output_2_eth_hdr_valid,
eth_dest_mac=output_2_eth_dest_mac,
eth_src_mac=output_2_eth_src_mac,
eth_type=output_2_eth_type,
eth_payload_tdata=output_2_eth_payload_tdata,
eth_payload_tvalid=output_2_eth_payload_tvalid,
eth_payload_tready=output_2_eth_payload_tready,
eth_payload_tlast=output_2_eth_payload_tlast,
eth_payload_tuser=output_2_eth_payload_tuser,
pause=sink_2_pause,
name='sink_2'
)
sink_3 = eth_ep.EthFrameSink()
sink_3_logic = sink_3.create_logic(
clk,
rst,
eth_hdr_ready=output_3_eth_hdr_ready,
eth_hdr_valid=output_3_eth_hdr_valid,
eth_dest_mac=output_3_eth_dest_mac,
eth_src_mac=output_3_eth_src_mac,
eth_type=output_3_eth_type,
eth_payload_tdata=output_3_eth_payload_tdata,
eth_payload_tvalid=output_3_eth_payload_tvalid,
eth_payload_tready=output_3_eth_payload_tready,
eth_payload_tlast=output_3_eth_payload_tlast,
eth_payload_tuser=output_3_eth_payload_tuser,
pause=sink_3_pause,
name='sink_3'
)
# DUT # DUT
if os.system(build_cmd): if os.system(build_cmd):
@ -217,59 +170,36 @@ def bench():
rst=rst, rst=rst,
current_test=current_test, current_test=current_test,
input_eth_hdr_valid=input_eth_hdr_valid, s_eth_hdr_valid=s_eth_hdr_valid,
input_eth_hdr_ready=input_eth_hdr_ready, s_eth_hdr_ready=s_eth_hdr_ready,
input_eth_dest_mac=input_eth_dest_mac, s_eth_dest_mac=s_eth_dest_mac,
input_eth_src_mac=input_eth_src_mac, s_eth_src_mac=s_eth_src_mac,
input_eth_type=input_eth_type, s_eth_type=s_eth_type,
input_eth_payload_tdata=input_eth_payload_tdata, s_eth_payload_axis_tdata=s_eth_payload_axis_tdata,
input_eth_payload_tvalid=input_eth_payload_tvalid, s_eth_payload_axis_tkeep=s_eth_payload_axis_tkeep,
input_eth_payload_tready=input_eth_payload_tready, s_eth_payload_axis_tvalid=s_eth_payload_axis_tvalid,
input_eth_payload_tlast=input_eth_payload_tlast, s_eth_payload_axis_tready=s_eth_payload_axis_tready,
input_eth_payload_tuser=input_eth_payload_tuser, s_eth_payload_axis_tlast=s_eth_payload_axis_tlast,
s_eth_payload_axis_tid=s_eth_payload_axis_tid,
s_eth_payload_axis_tdest=s_eth_payload_axis_tdest,
s_eth_payload_axis_tuser=s_eth_payload_axis_tuser,
output_0_eth_hdr_valid=output_0_eth_hdr_valid, m_eth_hdr_valid=m_eth_hdr_valid,
output_0_eth_hdr_ready=output_0_eth_hdr_ready, m_eth_hdr_ready=m_eth_hdr_ready,
output_0_eth_dest_mac=output_0_eth_dest_mac, m_eth_dest_mac=m_eth_dest_mac,
output_0_eth_src_mac=output_0_eth_src_mac, m_eth_src_mac=m_eth_src_mac,
output_0_eth_type=output_0_eth_type, m_eth_type=m_eth_type,
output_0_eth_payload_tdata=output_0_eth_payload_tdata, m_eth_payload_axis_tdata=m_eth_payload_axis_tdata,
output_0_eth_payload_tvalid=output_0_eth_payload_tvalid, m_eth_payload_axis_tkeep=m_eth_payload_axis_tkeep,
output_0_eth_payload_tready=output_0_eth_payload_tready, m_eth_payload_axis_tvalid=m_eth_payload_axis_tvalid,
output_0_eth_payload_tlast=output_0_eth_payload_tlast, m_eth_payload_axis_tready=m_eth_payload_axis_tready,
output_0_eth_payload_tuser=output_0_eth_payload_tuser, m_eth_payload_axis_tlast=m_eth_payload_axis_tlast,
output_1_eth_hdr_valid=output_1_eth_hdr_valid, m_eth_payload_axis_tid=m_eth_payload_axis_tid,
output_1_eth_hdr_ready=output_1_eth_hdr_ready, m_eth_payload_axis_tdest=m_eth_payload_axis_tdest,
output_1_eth_dest_mac=output_1_eth_dest_mac, m_eth_payload_axis_tuser=m_eth_payload_axis_tuser,
output_1_eth_src_mac=output_1_eth_src_mac,
output_1_eth_type=output_1_eth_type,
output_1_eth_payload_tdata=output_1_eth_payload_tdata,
output_1_eth_payload_tvalid=output_1_eth_payload_tvalid,
output_1_eth_payload_tready=output_1_eth_payload_tready,
output_1_eth_payload_tlast=output_1_eth_payload_tlast,
output_1_eth_payload_tuser=output_1_eth_payload_tuser,
output_2_eth_hdr_valid=output_2_eth_hdr_valid,
output_2_eth_hdr_ready=output_2_eth_hdr_ready,
output_2_eth_dest_mac=output_2_eth_dest_mac,
output_2_eth_src_mac=output_2_eth_src_mac,
output_2_eth_type=output_2_eth_type,
output_2_eth_payload_tdata=output_2_eth_payload_tdata,
output_2_eth_payload_tvalid=output_2_eth_payload_tvalid,
output_2_eth_payload_tready=output_2_eth_payload_tready,
output_2_eth_payload_tlast=output_2_eth_payload_tlast,
output_2_eth_payload_tuser=output_2_eth_payload_tuser,
output_3_eth_hdr_valid=output_3_eth_hdr_valid,
output_3_eth_hdr_ready=output_3_eth_hdr_ready,
output_3_eth_dest_mac=output_3_eth_dest_mac,
output_3_eth_src_mac=output_3_eth_src_mac,
output_3_eth_type=output_3_eth_type,
output_3_eth_payload_tdata=output_3_eth_payload_tdata,
output_3_eth_payload_tvalid=output_3_eth_payload_tvalid,
output_3_eth_payload_tready=output_3_eth_payload_tready,
output_3_eth_payload_tlast=output_3_eth_payload_tlast,
output_3_eth_payload_tuser=output_3_eth_payload_tuser,
enable=enable, enable=enable,
drop=drop,
select=select select=select
) )
@ -305,8 +235,8 @@ def bench():
source.send(test_frame) source.send(test_frame)
yield sink_0.wait() yield sink_list[0].wait()
rx_frame = sink_0.recv() rx_frame = sink_list[0].recv()
assert rx_frame == test_frame assert rx_frame == test_frame
@ -326,8 +256,8 @@ def bench():
source.send(test_frame) source.send(test_frame)
yield sink_1.wait() yield sink_list[1].wait()
rx_frame = sink_1.recv() rx_frame = sink_list[1].recv()
assert rx_frame == test_frame assert rx_frame == test_frame
@ -353,13 +283,13 @@ def bench():
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield sink_0.wait() yield sink_list[0].wait()
rx_frame = sink_0.recv() rx_frame = sink_list[0].recv()
assert rx_frame == test_frame1 assert rx_frame == test_frame1
yield sink_0.wait() yield sink_list[0].wait()
rx_frame = sink_0.recv() rx_frame = sink_list[0].recv()
assert rx_frame == test_frame2 assert rx_frame == test_frame2
@ -386,17 +316,17 @@ def bench():
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge
while input_eth_payload_tvalid or input_eth_hdr_valid: while s_eth_payload_axis_tvalid or s_eth_hdr_valid:
yield clk.posedge yield clk.posedge
select.next = 2 select.next = 2
yield sink_1.wait() yield sink_list[1].wait()
rx_frame = sink_1.recv() rx_frame = sink_list[1].recv()
assert rx_frame == test_frame1 assert rx_frame == test_frame1
yield sink_2.wait() yield sink_list[2].wait()
rx_frame = sink_2.recv() rx_frame = sink_list[2].recv()
assert rx_frame == test_frame2 assert rx_frame == test_frame2
@ -423,7 +353,7 @@ def bench():
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge
while input_eth_payload_tvalid or input_eth_hdr_valid: while s_eth_payload_axis_tvalid or s_eth_hdr_valid:
source_pause.next = True source_pause.next = True
yield clk.posedge yield clk.posedge
yield clk.posedge yield clk.posedge
@ -432,13 +362,13 @@ def bench():
yield clk.posedge yield clk.posedge
select.next = 2 select.next = 2
yield sink_1.wait() yield sink_list[1].wait()
rx_frame = sink_1.recv() rx_frame = sink_list[1].recv()
assert rx_frame == test_frame1 assert rx_frame == test_frame1
yield sink_2.wait() yield sink_list[2].wait()
rx_frame = sink_2.recv() rx_frame = sink_list[2].recv()
assert rx_frame == test_frame2 assert rx_frame == test_frame2
@ -465,33 +395,84 @@ def bench():
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge
while input_eth_payload_tvalid or input_eth_hdr_valid: while s_eth_payload_axis_tvalid or s_eth_hdr_valid:
sink_0_pause.next = True sink_pause_list[0].next = True
sink_1_pause.next = True sink_pause_list[1].next = True
sink_2_pause.next = True sink_pause_list[2].next = True
sink_3_pause.next = True sink_pause_list[3].next = True
yield clk.posedge yield clk.posedge
yield clk.posedge yield clk.posedge
yield clk.posedge yield clk.posedge
sink_0_pause.next = False sink_pause_list[0].next = False
sink_1_pause.next = False sink_pause_list[1].next = False
sink_2_pause.next = False sink_pause_list[2].next = False
sink_3_pause.next = False sink_pause_list[3].next = False
yield clk.posedge yield clk.posedge
select.next = 2 select.next = 2
yield sink_1.wait() yield sink_list[1].wait()
rx_frame = sink_1.recv() rx_frame = sink_list[1].recv()
assert rx_frame == test_frame1 assert rx_frame == test_frame1
yield sink_2.wait() yield sink_list[2].wait()
rx_frame = sink_2.recv() rx_frame = sink_list[2].recv()
assert rx_frame == test_frame2 assert rx_frame == test_frame2
yield delay(100) yield delay(100)
yield clk.posedge
print("test 7: enable")
current_test.next = 7
enable.next = False
select.next = 0
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
source.send(test_frame)
yield delay(500)
assert sink_list[0].empty()
enable.next = True
yield sink_list[0].wait()
rx_frame = sink_list[0].recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 8: drop")
current_test.next = 8
drop.next = True
select.next = 0
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
source.send(test_frame)
yield delay(500)
assert sink_list[0].empty()
drop.next = False
yield delay(100)
raise StopSimulation raise StopSimulation
return instances() return instances()

258
tb/test_eth_demux_4.v
View File

@ -27,72 +27,61 @@ THE SOFTWARE.
`timescale 1ns / 1ps `timescale 1ns / 1ps
/* /*
* Testbench for eth_demux_4 * Testbench for eth_demux
*/ */
module test_eth_demux_4; module test_eth_demux_4;
// Parameters
parameter M_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
reg rst = 0; reg rst = 0;
reg [7:0] current_test = 0; reg [7:0] current_test = 0;
reg input_eth_hdr_valid = 0; reg s_eth_hdr_valid = 0;
reg [47:0] input_eth_dest_mac = 0; reg [47:0] s_eth_dest_mac = 0;
reg [47:0] input_eth_src_mac = 0; reg [47:0] s_eth_src_mac = 0;
reg [15:0] input_eth_type = 0; reg [15:0] s_eth_type = 0;
reg [7:0] input_eth_payload_tdata = 0; reg [DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
reg input_eth_payload_tvalid = 0; reg [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
reg input_eth_payload_tlast = 0; reg s_eth_payload_axis_tvalid = 0;
reg input_eth_payload_tuser = 0; reg s_eth_payload_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_eth_payload_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_eth_payload_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_eth_payload_axis_tuser = 0;
reg output_0_eth_hdr_ready = 0; reg [M_COUNT-1:0] m_eth_hdr_ready = 0;
reg output_0_eth_payload_tready = 0; reg [M_COUNT-1:0] m_eth_payload_axis_tready = 0;
reg output_1_eth_hdr_ready = 0;
reg output_1_eth_payload_tready = 0;
reg output_2_eth_hdr_ready = 0;
reg output_2_eth_payload_tready = 0;
reg output_3_eth_hdr_ready = 0;
reg output_3_eth_payload_tready = 0;
reg enable = 0; reg enable = 0;
reg drop = 0;
reg [1:0] select = 0; reg [1:0] select = 0;
// Outputs // Outputs
wire input_eth_hdr_ready; wire s_eth_hdr_ready;
wire input_eth_payload_tready; wire s_eth_payload_axis_tready;
wire output_0_eth_hdr_valid; wire [M_COUNT-1:0] m_eth_hdr_valid;
wire [47:0] output_0_eth_dest_mac; wire [M_COUNT*48-1:0] m_eth_dest_mac;
wire [47:0] output_0_eth_src_mac; wire [M_COUNT*48-1:0] m_eth_src_mac;
wire [15:0] output_0_eth_type; wire [M_COUNT*16-1:0] m_eth_type;
wire [7:0] output_0_eth_payload_tdata; wire [M_COUNT*DATA_WIDTH-1:0] m_eth_payload_axis_tdata;
wire output_0_eth_payload_tvalid; wire [M_COUNT*KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep;
wire output_0_eth_payload_tlast; wire [M_COUNT-1:0] m_eth_payload_axis_tvalid;
wire output_0_eth_payload_tuser; wire [M_COUNT-1:0] m_eth_payload_axis_tlast;
wire output_1_eth_hdr_valid; wire [M_COUNT*ID_WIDTH-1:0] m_eth_payload_axis_tid;
wire [47:0] output_1_eth_dest_mac; wire [M_COUNT*DEST_WIDTH-1:0] m_eth_payload_axis_tdest;
wire [47:0] output_1_eth_src_mac; wire [M_COUNT*USER_WIDTH-1:0] m_eth_payload_axis_tuser;
wire [15:0] output_1_eth_type;
wire [7:0] output_1_eth_payload_tdata;
wire output_1_eth_payload_tvalid;
wire output_1_eth_payload_tlast;
wire output_1_eth_payload_tuser;
wire output_2_eth_hdr_valid;
wire [47:0] output_2_eth_dest_mac;
wire [47:0] output_2_eth_src_mac;
wire [15:0] output_2_eth_type;
wire [7:0] output_2_eth_payload_tdata;
wire output_2_eth_payload_tvalid;
wire output_2_eth_payload_tlast;
wire output_2_eth_payload_tuser;
wire output_3_eth_hdr_valid;
wire [47:0] output_3_eth_dest_mac;
wire [47:0] output_3_eth_src_mac;
wire [15:0] output_3_eth_type;
wire [7:0] output_3_eth_payload_tdata;
wire output_3_eth_payload_tvalid;
wire output_3_eth_payload_tlast;
wire output_3_eth_payload_tuser;
initial begin initial begin
// myhdl integration // myhdl integration
@ -100,60 +89,37 @@ initial begin
clk, clk,
rst, rst,
current_test, current_test,
input_eth_hdr_valid, s_eth_hdr_valid,
input_eth_dest_mac, s_eth_dest_mac,
input_eth_src_mac, s_eth_src_mac,
input_eth_type, s_eth_type,
input_eth_payload_tdata, s_eth_payload_axis_tdata,
input_eth_payload_tvalid, s_eth_payload_axis_tkeep,
input_eth_payload_tlast, s_eth_payload_axis_tvalid,
input_eth_payload_tuser, s_eth_payload_axis_tlast,
output_0_eth_hdr_ready, s_eth_payload_axis_tid,
output_0_eth_payload_tready, s_eth_payload_axis_tdest,
output_1_eth_hdr_ready, s_eth_payload_axis_tuser,
output_1_eth_payload_tready, m_eth_hdr_ready,
output_2_eth_hdr_ready, m_eth_payload_axis_tready,
output_2_eth_payload_tready,
output_3_eth_hdr_ready,
output_3_eth_payload_tready,
enable, enable,
drop,
select select
); );
$to_myhdl( $to_myhdl(
input_eth_hdr_ready, s_eth_hdr_ready,
input_eth_payload_tready, s_eth_payload_axis_tready,
output_0_eth_hdr_valid, m_eth_hdr_valid,
output_0_eth_dest_mac, m_eth_dest_mac,
output_0_eth_src_mac, m_eth_src_mac,
output_0_eth_type, m_eth_type,
output_0_eth_payload_tdata, m_eth_payload_axis_tdata,
output_0_eth_payload_tvalid, m_eth_payload_axis_tkeep,
output_0_eth_payload_tlast, m_eth_payload_axis_tvalid,
output_0_eth_payload_tuser, m_eth_payload_axis_tlast,
output_1_eth_hdr_valid, m_eth_payload_axis_tid,
output_1_eth_dest_mac, m_eth_payload_axis_tdest,
output_1_eth_src_mac, m_eth_payload_axis_tuser
output_1_eth_type,
output_1_eth_payload_tdata,
output_1_eth_payload_tvalid,
output_1_eth_payload_tlast,
output_1_eth_payload_tuser,
output_2_eth_hdr_valid,
output_2_eth_dest_mac,
output_2_eth_src_mac,
output_2_eth_type,
output_2_eth_payload_tdata,
output_2_eth_payload_tvalid,
output_2_eth_payload_tlast,
output_2_eth_payload_tuser,
output_3_eth_hdr_valid,
output_3_eth_dest_mac,
output_3_eth_src_mac,
output_3_eth_type,
output_3_eth_payload_tdata,
output_3_eth_payload_tvalid,
output_3_eth_payload_tlast,
output_3_eth_payload_tuser
); );
// dump file // dump file
@ -161,64 +127,52 @@ initial begin
$dumpvars(0, test_eth_demux_4); $dumpvars(0, test_eth_demux_4);
end end
eth_demux_4 eth_demux #(
.M_COUNT(M_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
UUT ( UUT (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
// Ethernet frame input // Ethernet frame input
.input_eth_hdr_valid(input_eth_hdr_valid), .s_eth_hdr_valid(s_eth_hdr_valid),
.input_eth_hdr_ready(input_eth_hdr_ready), .s_eth_hdr_ready(s_eth_hdr_ready),
.input_eth_dest_mac(input_eth_dest_mac), .s_eth_dest_mac(s_eth_dest_mac),
.input_eth_src_mac(input_eth_src_mac), .s_eth_src_mac(s_eth_src_mac),
.input_eth_type(input_eth_type), .s_eth_type(s_eth_type),
.input_eth_payload_tdata(input_eth_payload_tdata), .s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.input_eth_payload_tvalid(input_eth_payload_tvalid), .s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.input_eth_payload_tready(input_eth_payload_tready), .s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.input_eth_payload_tlast(input_eth_payload_tlast), .s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.input_eth_payload_tuser(input_eth_payload_tuser), .s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tid(s_eth_payload_axis_tid),
.s_eth_payload_axis_tdest(s_eth_payload_axis_tdest),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// Ethernet frame outputs // Ethernet frame outputs
.output_0_eth_hdr_valid(output_0_eth_hdr_valid), .m_eth_hdr_valid(m_eth_hdr_valid),
.output_0_eth_hdr_ready(output_0_eth_hdr_ready), .m_eth_hdr_ready(m_eth_hdr_ready),
.output_0_eth_dest_mac(output_0_eth_dest_mac), .m_eth_dest_mac(m_eth_dest_mac),
.output_0_eth_src_mac(output_0_eth_src_mac), .m_eth_src_mac(m_eth_src_mac),
.output_0_eth_type(output_0_eth_type), .m_eth_type(m_eth_type),
.output_0_eth_payload_tdata(output_0_eth_payload_tdata), .m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.output_0_eth_payload_tvalid(output_0_eth_payload_tvalid), .m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.output_0_eth_payload_tready(output_0_eth_payload_tready), .m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.output_0_eth_payload_tlast(output_0_eth_payload_tlast), .m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.output_0_eth_payload_tuser(output_0_eth_payload_tuser), .m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.output_1_eth_hdr_valid(output_1_eth_hdr_valid), .m_eth_payload_axis_tid(m_eth_payload_axis_tid),
.output_1_eth_hdr_ready(output_1_eth_hdr_ready), .m_eth_payload_axis_tdest(m_eth_payload_axis_tdest),
.output_1_eth_dest_mac(output_1_eth_dest_mac), .m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
.output_1_eth_src_mac(output_1_eth_src_mac),
.output_1_eth_type(output_1_eth_type),
.output_1_eth_payload_tdata(output_1_eth_payload_tdata),
.output_1_eth_payload_tvalid(output_1_eth_payload_tvalid),
.output_1_eth_payload_tready(output_1_eth_payload_tready),
.output_1_eth_payload_tlast(output_1_eth_payload_tlast),
.output_1_eth_payload_tuser(output_1_eth_payload_tuser),
.output_2_eth_hdr_valid(output_2_eth_hdr_valid),
.output_2_eth_hdr_ready(output_2_eth_hdr_ready),
.output_2_eth_dest_mac(output_2_eth_dest_mac),
.output_2_eth_src_mac(output_2_eth_src_mac),
.output_2_eth_type(output_2_eth_type),
.output_2_eth_payload_tdata(output_2_eth_payload_tdata),
.output_2_eth_payload_tvalid(output_2_eth_payload_tvalid),
.output_2_eth_payload_tready(output_2_eth_payload_tready),
.output_2_eth_payload_tlast(output_2_eth_payload_tlast),
.output_2_eth_payload_tuser(output_2_eth_payload_tuser),
.output_3_eth_hdr_valid(output_3_eth_hdr_valid),
.output_3_eth_hdr_ready(output_3_eth_hdr_ready),
.output_3_eth_dest_mac(output_3_eth_dest_mac),
.output_3_eth_src_mac(output_3_eth_src_mac),
.output_3_eth_type(output_3_eth_type),
.output_3_eth_payload_tdata(output_3_eth_payload_tdata),
.output_3_eth_payload_tvalid(output_3_eth_payload_tvalid),
.output_3_eth_payload_tready(output_3_eth_payload_tready),
.output_3_eth_payload_tlast(output_3_eth_payload_tlast),
.output_3_eth_payload_tuser(output_3_eth_payload_tuser),
// Control // Control
.enable(enable), .enable(enable),
.drop(drop),
.select(select) .select(select)
); );

436
tb/test_eth_demux_64_4.py
View File

@ -28,8 +28,8 @@ import os
import eth_ep import eth_ep
module = 'eth_demux_64_4' module = 'eth_demux'
testbench = 'test_%s' % module testbench = 'test_%s_64_4' % module
srcs = [] srcs = []
@ -42,180 +42,123 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench(): def bench():
# Parameters
M_COUNT = 4
DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))
rst = Signal(bool(0)) rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:]) current_test = Signal(intbv(0)[8:])
input_eth_hdr_valid = Signal(bool(0)) s_eth_hdr_valid = Signal(bool(0))
input_eth_dest_mac = Signal(intbv(0)[48:]) s_eth_dest_mac = Signal(intbv(0)[48:])
input_eth_src_mac = Signal(intbv(0)[48:]) s_eth_src_mac = Signal(intbv(0)[48:])
input_eth_type = Signal(intbv(0)[16:]) s_eth_type = Signal(intbv(0)[16:])
input_eth_payload_tdata = Signal(intbv(0)[64:]) s_eth_payload_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_eth_payload_tkeep = Signal(intbv(0)[8:]) s_eth_payload_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_eth_payload_tvalid = Signal(bool(0)) s_eth_payload_axis_tvalid = Signal(bool(0))
input_eth_payload_tlast = Signal(bool(0)) s_eth_payload_axis_tlast = Signal(bool(0))
input_eth_payload_tuser = Signal(bool(0)) s_eth_payload_axis_tid = Signal(intbv(0)[ID_WIDTH:])
s_eth_payload_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
s_eth_payload_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_0_eth_hdr_ready = Signal(bool(0)) m_eth_hdr_ready_list = [Signal(bool(0)) for i in range(M_COUNT)]
output_0_eth_payload_tready = Signal(bool(0)) m_eth_payload_axis_tready_list = [Signal(bool(0)) for i in range(M_COUNT)]
output_1_eth_hdr_ready = Signal(bool(0))
output_1_eth_payload_tready = Signal(bool(0)) m_eth_hdr_ready = ConcatSignal(*reversed(m_eth_hdr_ready_list))
output_2_eth_hdr_ready = Signal(bool(0)) m_eth_payload_axis_tready = ConcatSignal(*reversed(m_eth_payload_axis_tready_list))
output_2_eth_payload_tready = Signal(bool(0))
output_3_eth_hdr_ready = Signal(bool(0))
output_3_eth_payload_tready = Signal(bool(0))
enable = Signal(bool(0)) enable = Signal(bool(0))
drop = Signal(bool(0))
select = Signal(intbv(0)[2:]) select = Signal(intbv(0)[2:])
# Outputs # Outputs
input_eth_hdr_ready = Signal(bool(0)) s_eth_hdr_ready = Signal(bool(0))
input_eth_payload_tready = Signal(bool(0)) s_eth_payload_axis_tready = Signal(bool(0))
output_0_eth_hdr_valid = Signal(bool(0)) m_eth_hdr_valid = Signal(intbv(0)[M_COUNT:])
output_0_eth_dest_mac = Signal(intbv(0)[48:]) m_eth_dest_mac = Signal(intbv(0)[M_COUNT*48:])
output_0_eth_src_mac = Signal(intbv(0)[48:]) m_eth_src_mac = Signal(intbv(0)[M_COUNT*48:])
output_0_eth_type = Signal(intbv(0)[16:]) m_eth_type = Signal(intbv(0)[M_COUNT*16:])
output_0_eth_payload_tdata = Signal(intbv(0)[64:]) m_eth_payload_axis_tdata = Signal(intbv(0)[M_COUNT*DATA_WIDTH:])
output_0_eth_payload_tkeep = Signal(intbv(0)[8:]) m_eth_payload_axis_tkeep = Signal(intbv(0xf)[M_COUNT*KEEP_WIDTH:])
output_0_eth_payload_tvalid = Signal(bool(0)) m_eth_payload_axis_tvalid = Signal(intbv(0)[M_COUNT:])
output_0_eth_payload_tlast = Signal(bool(0)) m_eth_payload_axis_tlast = Signal(intbv(0)[M_COUNT:])
output_0_eth_payload_tuser = Signal(bool(0)) m_eth_payload_axis_tid = Signal(intbv(0)[M_COUNT*ID_WIDTH:])
output_1_eth_hdr_valid = Signal(bool(0)) m_eth_payload_axis_tdest = Signal(intbv(0)[M_COUNT*DEST_WIDTH:])
output_1_eth_dest_mac = Signal(intbv(0)[48:]) m_eth_payload_axis_tuser = Signal(intbv(0)[M_COUNT*USER_WIDTH:])
output_1_eth_src_mac = Signal(intbv(0)[48:])
output_1_eth_type = Signal(intbv(0)[16:]) m_eth_hdr_valid_list = [m_eth_hdr_valid(i) for i in range(M_COUNT)]
output_1_eth_payload_tdata = Signal(intbv(0)[64:]) m_eth_dest_mac_list = [m_eth_dest_mac((i+1)*48, i*48) for i in range(M_COUNT)]
output_1_eth_payload_tkeep = Signal(intbv(0)[8:]) m_eth_src_mac_list = [m_eth_src_mac((i+1)*48, i*48) for i in range(M_COUNT)]
output_1_eth_payload_tvalid = Signal(bool(0)) m_eth_type_list = [m_eth_type((i+1)*16, i*16) for i in range(M_COUNT)]
output_1_eth_payload_tlast = Signal(bool(0)) m_eth_payload_axis_tdata_list = [m_eth_payload_axis_tdata((i+1)*DATA_WIDTH, i*DATA_WIDTH) for i in range(M_COUNT)]
output_1_eth_payload_tuser = Signal(bool(0)) m_eth_payload_axis_tkeep_list = [m_eth_payload_axis_tkeep((i+1)*KEEP_WIDTH, i*KEEP_WIDTH) for i in range(M_COUNT)]
output_2_eth_hdr_valid = Signal(bool(0)) m_eth_payload_axis_tvalid_list = [m_eth_payload_axis_tvalid(i) for i in range(M_COUNT)]
output_2_eth_dest_mac = Signal(intbv(0)[48:]) m_eth_payload_axis_tlast_list = [m_eth_payload_axis_tlast(i) for i in range(M_COUNT)]
output_2_eth_src_mac = Signal(intbv(0)[48:]) m_eth_payload_axis_tid_list = [m_eth_payload_axis_tid((i+1)*ID_WIDTH, i*ID_WIDTH) for i in range(M_COUNT)]
output_2_eth_type = Signal(intbv(0)[16:]) m_eth_payload_axis_tdest_list = [m_eth_payload_axis_tdest((i+1)*DEST_WIDTH, i*DEST_WIDTH) for i in range(M_COUNT)]
output_2_eth_payload_tdata = Signal(intbv(0)[64:]) m_eth_payload_axis_tuser_list = [m_eth_payload_axis_tuser((i+1)*USER_WIDTH, i*USER_WIDTH) for i in range(M_COUNT)]
output_2_eth_payload_tkeep = Signal(intbv(0)[8:])
output_2_eth_payload_tvalid = Signal(bool(0))
output_2_eth_payload_tlast = Signal(bool(0))
output_2_eth_payload_tuser = Signal(bool(0))
output_3_eth_hdr_valid = Signal(bool(0))
output_3_eth_dest_mac = Signal(intbv(0)[48:])
output_3_eth_src_mac = Signal(intbv(0)[48:])
output_3_eth_type = Signal(intbv(0)[16:])
output_3_eth_payload_tdata = Signal(intbv(0)[64:])
output_3_eth_payload_tkeep = Signal(intbv(0)[8:])
output_3_eth_payload_tvalid = Signal(bool(0))
output_3_eth_payload_tlast = Signal(bool(0))
output_3_eth_payload_tuser = Signal(bool(0))
# sources and sinks # sources and sinks
source_pause = Signal(bool(0)) source_pause = Signal(bool(0))
sink_0_pause = Signal(bool(0)) sink_pause_list = []
sink_1_pause = Signal(bool(0)) sink_list = []
sink_2_pause = Signal(bool(0)) sink_logic_list = []
sink_3_pause = Signal(bool(0))
source = eth_ep.EthFrameSource() source = eth_ep.EthFrameSource()
source_logic = source.create_logic( source_logic = source.create_logic(
clk, clk,
rst, rst,
eth_hdr_ready=input_eth_hdr_ready, eth_hdr_ready=s_eth_hdr_ready,
eth_hdr_valid=input_eth_hdr_valid, eth_hdr_valid=s_eth_hdr_valid,
eth_dest_mac=input_eth_dest_mac, eth_dest_mac=s_eth_dest_mac,
eth_src_mac=input_eth_src_mac, eth_src_mac=s_eth_src_mac,
eth_type=input_eth_type, eth_type=s_eth_type,
eth_payload_tdata=input_eth_payload_tdata, eth_payload_tdata=s_eth_payload_axis_tdata,
eth_payload_tkeep=input_eth_payload_tkeep, eth_payload_tkeep=s_eth_payload_axis_tkeep,
eth_payload_tvalid=input_eth_payload_tvalid, eth_payload_tvalid=s_eth_payload_axis_tvalid,
eth_payload_tready=input_eth_payload_tready, eth_payload_tready=s_eth_payload_axis_tready,
eth_payload_tlast=input_eth_payload_tlast, eth_payload_tlast=s_eth_payload_axis_tlast,
eth_payload_tuser=input_eth_payload_tuser, eth_payload_tuser=s_eth_payload_axis_tuser,
pause=source_pause, pause=source_pause,
name='source' name='source'
) )
sink_0 = eth_ep.EthFrameSink() for k in range(M_COUNT):
s = eth_ep.EthFrameSink()
p = Signal(bool(0))
sink_0_logic = sink_0.create_logic( sink_list.append(s)
clk, sink_pause_list.append(p)
rst,
eth_hdr_ready=output_0_eth_hdr_ready,
eth_hdr_valid=output_0_eth_hdr_valid,
eth_dest_mac=output_0_eth_dest_mac,
eth_src_mac=output_0_eth_src_mac,
eth_type=output_0_eth_type,
eth_payload_tdata=output_0_eth_payload_tdata,
eth_payload_tkeep=output_0_eth_payload_tkeep,
eth_payload_tvalid=output_0_eth_payload_tvalid,
eth_payload_tready=output_0_eth_payload_tready,
eth_payload_tlast=output_0_eth_payload_tlast,
eth_payload_tuser=output_0_eth_payload_tuser,
pause=sink_0_pause,
name='sink_0'
)
sink_1 = eth_ep.EthFrameSink() sink_logic_list.append(s.create_logic(
clk,
sink_1_logic = sink_1.create_logic( rst,
clk, eth_hdr_ready=m_eth_hdr_ready_list[k],
rst, eth_hdr_valid=m_eth_hdr_valid_list[k],
eth_hdr_ready=output_1_eth_hdr_ready, eth_dest_mac=m_eth_dest_mac_list[k],
eth_hdr_valid=output_1_eth_hdr_valid, eth_src_mac=m_eth_src_mac_list[k],
eth_dest_mac=output_1_eth_dest_mac, eth_type=m_eth_type_list[k],
eth_src_mac=output_1_eth_src_mac, eth_payload_tdata=m_eth_payload_axis_tdata_list[k],
eth_type=output_1_eth_type, eth_payload_tkeep=m_eth_payload_axis_tkeep_list[k],
eth_payload_tdata=output_1_eth_payload_tdata, eth_payload_tvalid=m_eth_payload_axis_tvalid_list[k],
eth_payload_tkeep=output_1_eth_payload_tkeep, eth_payload_tready=m_eth_payload_axis_tready_list[k],
eth_payload_tvalid=output_1_eth_payload_tvalid, eth_payload_tlast=m_eth_payload_axis_tlast_list[k],
eth_payload_tready=output_1_eth_payload_tready, eth_payload_tuser=m_eth_payload_axis_tuser_list[k],
eth_payload_tlast=output_1_eth_payload_tlast, pause=p,
eth_payload_tuser=output_1_eth_payload_tuser, name='sink_%d' % k
pause=sink_1_pause, ))
name='sink_1'
)
sink_2 = eth_ep.EthFrameSink()
sink_2_logic = sink_2.create_logic(
clk,
rst,
eth_hdr_ready=output_2_eth_hdr_ready,
eth_hdr_valid=output_2_eth_hdr_valid,
eth_dest_mac=output_2_eth_dest_mac,
eth_src_mac=output_2_eth_src_mac,
eth_type=output_2_eth_type,
eth_payload_tdata=output_2_eth_payload_tdata,
eth_payload_tkeep=output_2_eth_payload_tkeep,
eth_payload_tvalid=output_2_eth_payload_tvalid,
eth_payload_tready=output_2_eth_payload_tready,
eth_payload_tlast=output_2_eth_payload_tlast,
eth_payload_tuser=output_2_eth_payload_tuser,
pause=sink_2_pause,
name='sink_2'
)
sink_3 = eth_ep.EthFrameSink()
sink_3_logic = sink_3.create_logic(
clk,
rst,
eth_hdr_ready=output_3_eth_hdr_ready,
eth_hdr_valid=output_3_eth_hdr_valid,
eth_dest_mac=output_3_eth_dest_mac,
eth_src_mac=output_3_eth_src_mac,
eth_type=output_3_eth_type,
eth_payload_tdata=output_3_eth_payload_tdata,
eth_payload_tkeep=output_3_eth_payload_tkeep,
eth_payload_tvalid=output_3_eth_payload_tvalid,
eth_payload_tready=output_3_eth_payload_tready,
eth_payload_tlast=output_3_eth_payload_tlast,
eth_payload_tuser=output_3_eth_payload_tuser,
pause=sink_3_pause,
name='sink_3'
)
# DUT # DUT
if os.system(build_cmd): if os.system(build_cmd):
@ -227,64 +170,36 @@ def bench():
rst=rst, rst=rst,
current_test=current_test, current_test=current_test,
input_eth_hdr_valid=input_eth_hdr_valid, s_eth_hdr_valid=s_eth_hdr_valid,
input_eth_hdr_ready=input_eth_hdr_ready, s_eth_hdr_ready=s_eth_hdr_ready,
input_eth_dest_mac=input_eth_dest_mac, s_eth_dest_mac=s_eth_dest_mac,
input_eth_src_mac=input_eth_src_mac, s_eth_src_mac=s_eth_src_mac,
input_eth_type=input_eth_type, s_eth_type=s_eth_type,
input_eth_payload_tdata=input_eth_payload_tdata, s_eth_payload_axis_tdata=s_eth_payload_axis_tdata,
input_eth_payload_tkeep=input_eth_payload_tkeep, s_eth_payload_axis_tkeep=s_eth_payload_axis_tkeep,
input_eth_payload_tvalid=input_eth_payload_tvalid, s_eth_payload_axis_tvalid=s_eth_payload_axis_tvalid,
input_eth_payload_tready=input_eth_payload_tready, s_eth_payload_axis_tready=s_eth_payload_axis_tready,
input_eth_payload_tlast=input_eth_payload_tlast, s_eth_payload_axis_tlast=s_eth_payload_axis_tlast,
input_eth_payload_tuser=input_eth_payload_tuser, s_eth_payload_axis_tid=s_eth_payload_axis_tid,
s_eth_payload_axis_tdest=s_eth_payload_axis_tdest,
s_eth_payload_axis_tuser=s_eth_payload_axis_tuser,
output_0_eth_hdr_valid=output_0_eth_hdr_valid, m_eth_hdr_valid=m_eth_hdr_valid,
output_0_eth_hdr_ready=output_0_eth_hdr_ready, m_eth_hdr_ready=m_eth_hdr_ready,
output_0_eth_dest_mac=output_0_eth_dest_mac, m_eth_dest_mac=m_eth_dest_mac,
output_0_eth_src_mac=output_0_eth_src_mac, m_eth_src_mac=m_eth_src_mac,
output_0_eth_type=output_0_eth_type, m_eth_type=m_eth_type,
output_0_eth_payload_tdata=output_0_eth_payload_tdata, m_eth_payload_axis_tdata=m_eth_payload_axis_tdata,
output_0_eth_payload_tkeep=output_0_eth_payload_tkeep, m_eth_payload_axis_tkeep=m_eth_payload_axis_tkeep,
output_0_eth_payload_tvalid=output_0_eth_payload_tvalid, m_eth_payload_axis_tvalid=m_eth_payload_axis_tvalid,
output_0_eth_payload_tready=output_0_eth_payload_tready, m_eth_payload_axis_tready=m_eth_payload_axis_tready,
output_0_eth_payload_tlast=output_0_eth_payload_tlast, m_eth_payload_axis_tlast=m_eth_payload_axis_tlast,
output_0_eth_payload_tuser=output_0_eth_payload_tuser, m_eth_payload_axis_tid=m_eth_payload_axis_tid,
output_1_eth_hdr_valid=output_1_eth_hdr_valid, m_eth_payload_axis_tdest=m_eth_payload_axis_tdest,
output_1_eth_hdr_ready=output_1_eth_hdr_ready, m_eth_payload_axis_tuser=m_eth_payload_axis_tuser,
output_1_eth_dest_mac=output_1_eth_dest_mac,
output_1_eth_src_mac=output_1_eth_src_mac,
output_1_eth_type=output_1_eth_type,
output_1_eth_payload_tdata=output_1_eth_payload_tdata,
output_1_eth_payload_tkeep=output_1_eth_payload_tkeep,
output_1_eth_payload_tvalid=output_1_eth_payload_tvalid,
output_1_eth_payload_tready=output_1_eth_payload_tready,
output_1_eth_payload_tlast=output_1_eth_payload_tlast,
output_1_eth_payload_tuser=output_1_eth_payload_tuser,
output_2_eth_hdr_valid=output_2_eth_hdr_valid,
output_2_eth_hdr_ready=output_2_eth_hdr_ready,
output_2_eth_dest_mac=output_2_eth_dest_mac,
output_2_eth_src_mac=output_2_eth_src_mac,
output_2_eth_type=output_2_eth_type,
output_2_eth_payload_tdata=output_2_eth_payload_tdata,
output_2_eth_payload_tkeep=output_2_eth_payload_tkeep,
output_2_eth_payload_tvalid=output_2_eth_payload_tvalid,
output_2_eth_payload_tready=output_2_eth_payload_tready,
output_2_eth_payload_tlast=output_2_eth_payload_tlast,
output_2_eth_payload_tuser=output_2_eth_payload_tuser,
output_3_eth_hdr_valid=output_3_eth_hdr_valid,
output_3_eth_hdr_ready=output_3_eth_hdr_ready,
output_3_eth_dest_mac=output_3_eth_dest_mac,
output_3_eth_src_mac=output_3_eth_src_mac,
output_3_eth_type=output_3_eth_type,
output_3_eth_payload_tdata=output_3_eth_payload_tdata,
output_3_eth_payload_tkeep=output_3_eth_payload_tkeep,
output_3_eth_payload_tvalid=output_3_eth_payload_tvalid,
output_3_eth_payload_tready=output_3_eth_payload_tready,
output_3_eth_payload_tlast=output_3_eth_payload_tlast,
output_3_eth_payload_tuser=output_3_eth_payload_tuser,
enable=enable, enable=enable,
drop=drop,
select=select select=select
) )
@ -320,8 +235,8 @@ def bench():
source.send(test_frame) source.send(test_frame)
yield sink_0.wait() yield sink_list[0].wait()
rx_frame = sink_0.recv() rx_frame = sink_list[0].recv()
assert rx_frame == test_frame assert rx_frame == test_frame
@ -341,8 +256,8 @@ def bench():
source.send(test_frame) source.send(test_frame)
yield sink_1.wait() yield sink_list[1].wait()
rx_frame = sink_1.recv() rx_frame = sink_list[1].recv()
assert rx_frame == test_frame assert rx_frame == test_frame
@ -368,13 +283,13 @@ def bench():
source.send(test_frame1) source.send(test_frame1)
source.send(test_frame2) source.send(test_frame2)
yield sink_0.wait() yield sink_list[0].wait()
rx_frame = sink_0.recv() rx_frame = sink_list[0].recv()
assert rx_frame == test_frame1 assert rx_frame == test_frame1
yield sink_0.wait() yield sink_list[0].wait()
rx_frame = sink_0.recv() rx_frame = sink_list[0].recv()
assert rx_frame == test_frame2 assert rx_frame == test_frame2
@ -401,17 +316,17 @@ def bench():
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge
while input_eth_payload_tvalid or input_eth_hdr_valid: while s_eth_payload_axis_tvalid or s_eth_hdr_valid:
yield clk.posedge yield clk.posedge
select.next = 2 select.next = 2
yield sink_1.wait() yield sink_list[1].wait()
rx_frame = sink_1.recv() rx_frame = sink_list[1].recv()
assert rx_frame == test_frame1 assert rx_frame == test_frame1
yield sink_2.wait() yield sink_list[2].wait()
rx_frame = sink_2.recv() rx_frame = sink_list[2].recv()
assert rx_frame == test_frame2 assert rx_frame == test_frame2
@ -438,7 +353,7 @@ def bench():
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge
while input_eth_payload_tvalid or input_eth_hdr_valid: while s_eth_payload_axis_tvalid or s_eth_hdr_valid:
source_pause.next = True source_pause.next = True
yield clk.posedge yield clk.posedge
yield clk.posedge yield clk.posedge
@ -447,13 +362,13 @@ def bench():
yield clk.posedge yield clk.posedge
select.next = 2 select.next = 2
yield sink_1.wait() yield sink_list[1].wait()
rx_frame = sink_1.recv() rx_frame = sink_list[1].recv()
assert rx_frame == test_frame1 assert rx_frame == test_frame1
yield sink_2.wait() yield sink_list[2].wait()
rx_frame = sink_2.recv() rx_frame = sink_list[2].recv()
assert rx_frame == test_frame2 assert rx_frame == test_frame2
@ -480,33 +395,84 @@ def bench():
source.send(test_frame2) source.send(test_frame2)
yield clk.posedge yield clk.posedge
while input_eth_payload_tvalid or input_eth_hdr_valid: while s_eth_payload_axis_tvalid or s_eth_hdr_valid:
sink_0_pause.next = True sink_pause_list[0].next = True
sink_1_pause.next = True sink_pause_list[1].next = True
sink_2_pause.next = True sink_pause_list[2].next = True
sink_3_pause.next = True sink_pause_list[3].next = True
yield clk.posedge yield clk.posedge
yield clk.posedge yield clk.posedge
yield clk.posedge yield clk.posedge
sink_0_pause.next = False sink_pause_list[0].next = False
sink_1_pause.next = False sink_pause_list[1].next = False
sink_2_pause.next = False sink_pause_list[2].next = False
sink_3_pause.next = False sink_pause_list[3].next = False
yield clk.posedge yield clk.posedge
select.next = 2 select.next = 2
yield sink_1.wait() yield sink_list[1].wait()
rx_frame = sink_1.recv() rx_frame = sink_list[1].recv()
assert rx_frame == test_frame1 assert rx_frame == test_frame1
yield sink_2.wait() yield sink_list[2].wait()
rx_frame = sink_2.recv() rx_frame = sink_list[2].recv()
assert rx_frame == test_frame2 assert rx_frame == test_frame2
yield delay(100) yield delay(100)
yield clk.posedge
print("test 7: enable")
current_test.next = 7
enable.next = False
select.next = 0
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
source.send(test_frame)
yield delay(500)
assert sink_list[0].empty()
enable.next = True
yield sink_list[0].wait()
rx_frame = sink_list[0].recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 8: drop")
current_test.next = 8
drop.next = True
select.next = 0
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
source.send(test_frame)
yield delay(500)
assert sink_list[0].empty()
drop.next = False
yield delay(100)
raise StopSimulation raise StopSimulation
return instances() return instances()

273
tb/test_eth_demux_64_4.v
View File

@ -27,77 +27,61 @@ THE SOFTWARE.
`timescale 1ns / 1ps `timescale 1ns / 1ps
/* /*
* Testbench for eth_demux_64_4 * Testbench for eth_demux
*/ */
module test_eth_demux_64_4; module test_eth_demux_64_4;
// Parameters
parameter M_COUNT = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
reg rst = 0; reg rst = 0;
reg [7:0] current_test = 0; reg [7:0] current_test = 0;
reg input_eth_hdr_valid = 0; reg s_eth_hdr_valid = 0;
reg [47:0] input_eth_dest_mac = 0; reg [47:0] s_eth_dest_mac = 0;
reg [47:0] input_eth_src_mac = 0; reg [47:0] s_eth_src_mac = 0;
reg [15:0] input_eth_type = 0; reg [15:0] s_eth_type = 0;
reg [63:0] input_eth_payload_tdata = 0; reg [DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
reg [7:0] input_eth_payload_tkeep = 0; reg [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
reg input_eth_payload_tvalid = 0; reg s_eth_payload_axis_tvalid = 0;
reg input_eth_payload_tlast = 0; reg s_eth_payload_axis_tlast = 0;
reg input_eth_payload_tuser = 0; reg [ID_WIDTH-1:0] s_eth_payload_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_eth_payload_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_eth_payload_axis_tuser = 0;
reg output_0_eth_hdr_ready = 0; reg [M_COUNT-1:0] m_eth_hdr_ready = 0;
reg output_0_eth_payload_tready = 0; reg [M_COUNT-1:0] m_eth_payload_axis_tready = 0;
reg output_1_eth_hdr_ready = 0;
reg output_1_eth_payload_tready = 0;
reg output_2_eth_hdr_ready = 0;
reg output_2_eth_payload_tready = 0;
reg output_3_eth_hdr_ready = 0;
reg output_3_eth_payload_tready = 0;
reg enable = 0; reg enable = 0;
reg drop = 0;
reg [1:0] select = 0; reg [1:0] select = 0;
// Outputs // Outputs
wire input_eth_hdr_ready; wire s_eth_hdr_ready;
wire input_eth_payload_tready; wire s_eth_payload_axis_tready;
wire output_0_eth_hdr_valid; wire [M_COUNT-1:0] m_eth_hdr_valid;
wire [47:0] output_0_eth_dest_mac; wire [M_COUNT*48-1:0] m_eth_dest_mac;
wire [47:0] output_0_eth_src_mac; wire [M_COUNT*48-1:0] m_eth_src_mac;
wire [15:0] output_0_eth_type; wire [M_COUNT*16-1:0] m_eth_type;
wire [63:0] output_0_eth_payload_tdata; wire [M_COUNT*DATA_WIDTH-1:0] m_eth_payload_axis_tdata;
wire [7:0] output_0_eth_payload_tkeep; wire [M_COUNT*KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep;
wire output_0_eth_payload_tvalid; wire [M_COUNT-1:0] m_eth_payload_axis_tvalid;
wire output_0_eth_payload_tlast; wire [M_COUNT-1:0] m_eth_payload_axis_tlast;
wire output_0_eth_payload_tuser; wire [M_COUNT*ID_WIDTH-1:0] m_eth_payload_axis_tid;
wire output_1_eth_hdr_valid; wire [M_COUNT*DEST_WIDTH-1:0] m_eth_payload_axis_tdest;
wire [47:0] output_1_eth_dest_mac; wire [M_COUNT*USER_WIDTH-1:0] m_eth_payload_axis_tuser;
wire [47:0] output_1_eth_src_mac;
wire [15:0] output_1_eth_type;
wire [63:0] output_1_eth_payload_tdata;
wire [7:0] output_1_eth_payload_tkeep;
wire output_1_eth_payload_tvalid;
wire output_1_eth_payload_tlast;
wire output_1_eth_payload_tuser;
wire output_2_eth_hdr_valid;
wire [47:0] output_2_eth_dest_mac;
wire [47:0] output_2_eth_src_mac;
wire [15:0] output_2_eth_type;
wire [63:0] output_2_eth_payload_tdata;
wire [7:0] output_2_eth_payload_tkeep;
wire output_2_eth_payload_tvalid;
wire output_2_eth_payload_tlast;
wire output_2_eth_payload_tuser;
wire output_3_eth_hdr_valid;
wire [47:0] output_3_eth_dest_mac;
wire [47:0] output_3_eth_src_mac;
wire [15:0] output_3_eth_type;
wire [63:0] output_3_eth_payload_tdata;
wire [7:0] output_3_eth_payload_tkeep;
wire output_3_eth_payload_tvalid;
wire output_3_eth_payload_tlast;
wire output_3_eth_payload_tuser;
initial begin initial begin
// myhdl integration // myhdl integration
@ -105,65 +89,37 @@ initial begin
clk, clk,
rst, rst,
current_test, current_test,
input_eth_hdr_valid, s_eth_hdr_valid,
input_eth_dest_mac, s_eth_dest_mac,
input_eth_src_mac, s_eth_src_mac,
input_eth_type, s_eth_type,
input_eth_payload_tdata, s_eth_payload_axis_tdata,
input_eth_payload_tkeep, s_eth_payload_axis_tkeep,
input_eth_payload_tvalid, s_eth_payload_axis_tvalid,
input_eth_payload_tlast, s_eth_payload_axis_tlast,
input_eth_payload_tuser, s_eth_payload_axis_tid,
output_0_eth_hdr_ready, s_eth_payload_axis_tdest,
output_0_eth_payload_tready, s_eth_payload_axis_tuser,
output_1_eth_hdr_ready, m_eth_hdr_ready,
output_1_eth_payload_tready, m_eth_payload_axis_tready,
output_2_eth_hdr_ready,
output_2_eth_payload_tready,
output_3_eth_hdr_ready,
output_3_eth_payload_tready,
enable, enable,
drop,
select select
); );
$to_myhdl( $to_myhdl(
input_eth_hdr_ready, s_eth_hdr_ready,
input_eth_payload_tready, s_eth_payload_axis_tready,
output_0_eth_hdr_valid, m_eth_hdr_valid,
output_0_eth_dest_mac, m_eth_dest_mac,
output_0_eth_src_mac, m_eth_src_mac,
output_0_eth_type, m_eth_type,
output_0_eth_payload_tdata, m_eth_payload_axis_tdata,
output_0_eth_payload_tkeep, m_eth_payload_axis_tkeep,
output_0_eth_payload_tvalid, m_eth_payload_axis_tvalid,
output_0_eth_payload_tlast, m_eth_payload_axis_tlast,
output_0_eth_payload_tuser, m_eth_payload_axis_tid,
output_1_eth_hdr_valid, m_eth_payload_axis_tdest,
output_1_eth_dest_mac, m_eth_payload_axis_tuser
output_1_eth_src_mac,
output_1_eth_type,
output_1_eth_payload_tdata,
output_1_eth_payload_tkeep,
output_1_eth_payload_tvalid,
output_1_eth_payload_tlast,
output_1_eth_payload_tuser,
output_2_eth_hdr_valid,
output_2_eth_dest_mac,
output_2_eth_src_mac,
output_2_eth_type,
output_2_eth_payload_tdata,
output_2_eth_payload_tkeep,
output_2_eth_payload_tvalid,
output_2_eth_payload_tlast,
output_2_eth_payload_tuser,
output_3_eth_hdr_valid,
output_3_eth_dest_mac,
output_3_eth_src_mac,
output_3_eth_type,
output_3_eth_payload_tdata,
output_3_eth_payload_tkeep,
output_3_eth_payload_tvalid,
output_3_eth_payload_tlast,
output_3_eth_payload_tuser
); );
// dump file // dump file
@ -171,69 +127,52 @@ initial begin
$dumpvars(0, test_eth_demux_64_4); $dumpvars(0, test_eth_demux_64_4);
end end
eth_demux_64_4 eth_demux #(
.M_COUNT(M_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
UUT ( UUT (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
// Ethernet frame input // Ethernet frame input
.input_eth_hdr_valid(input_eth_hdr_valid), .s_eth_hdr_valid(s_eth_hdr_valid),
.input_eth_hdr_ready(input_eth_hdr_ready), .s_eth_hdr_ready(s_eth_hdr_ready),
.input_eth_dest_mac(input_eth_dest_mac), .s_eth_dest_mac(s_eth_dest_mac),
.input_eth_src_mac(input_eth_src_mac), .s_eth_src_mac(s_eth_src_mac),
.input_eth_type(input_eth_type), .s_eth_type(s_eth_type),
.input_eth_payload_tdata(input_eth_payload_tdata), .s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.input_eth_payload_tkeep(input_eth_payload_tkeep), .s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.input_eth_payload_tvalid(input_eth_payload_tvalid), .s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.input_eth_payload_tready(input_eth_payload_tready), .s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.input_eth_payload_tlast(input_eth_payload_tlast), .s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.input_eth_payload_tuser(input_eth_payload_tuser), .s_eth_payload_axis_tid(s_eth_payload_axis_tid),
.s_eth_payload_axis_tdest(s_eth_payload_axis_tdest),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// Ethernet frame outputs // Ethernet frame outputs
.output_0_eth_hdr_valid(output_0_eth_hdr_valid), .m_eth_hdr_valid(m_eth_hdr_valid),
.output_0_eth_hdr_ready(output_0_eth_hdr_ready), .m_eth_hdr_ready(m_eth_hdr_ready),
.output_0_eth_dest_mac(output_0_eth_dest_mac), .m_eth_dest_mac(m_eth_dest_mac),
.output_0_eth_src_mac(output_0_eth_src_mac), .m_eth_src_mac(m_eth_src_mac),
.output_0_eth_type(output_0_eth_type), .m_eth_type(m_eth_type),
.output_0_eth_payload_tdata(output_0_eth_payload_tdata), .m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.output_0_eth_payload_tkeep(output_0_eth_payload_tkeep), .m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.output_0_eth_payload_tvalid(output_0_eth_payload_tvalid), .m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.output_0_eth_payload_tready(output_0_eth_payload_tready), .m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.output_0_eth_payload_tlast(output_0_eth_payload_tlast), .m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.output_0_eth_payload_tuser(output_0_eth_payload_tuser), .m_eth_payload_axis_tid(m_eth_payload_axis_tid),
.output_1_eth_hdr_valid(output_1_eth_hdr_valid), .m_eth_payload_axis_tdest(m_eth_payload_axis_tdest),
.output_1_eth_hdr_ready(output_1_eth_hdr_ready), .m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
.output_1_eth_dest_mac(output_1_eth_dest_mac),
.output_1_eth_src_mac(output_1_eth_src_mac),
.output_1_eth_type(output_1_eth_type),
.output_1_eth_payload_tdata(output_1_eth_payload_tdata),
.output_1_eth_payload_tkeep(output_1_eth_payload_tkeep),
.output_1_eth_payload_tvalid(output_1_eth_payload_tvalid),
.output_1_eth_payload_tready(output_1_eth_payload_tready),
.output_1_eth_payload_tlast(output_1_eth_payload_tlast),
.output_1_eth_payload_tuser(output_1_eth_payload_tuser),
.output_2_eth_hdr_valid(output_2_eth_hdr_valid),
.output_2_eth_hdr_ready(output_2_eth_hdr_ready),
.output_2_eth_dest_mac(output_2_eth_dest_mac),
.output_2_eth_src_mac(output_2_eth_src_mac),
.output_2_eth_type(output_2_eth_type),
.output_2_eth_payload_tdata(output_2_eth_payload_tdata),
.output_2_eth_payload_tkeep(output_2_eth_payload_tkeep),
.output_2_eth_payload_tvalid(output_2_eth_payload_tvalid),
.output_2_eth_payload_tready(output_2_eth_payload_tready),
.output_2_eth_payload_tlast(output_2_eth_payload_tlast),
.output_2_eth_payload_tuser(output_2_eth_payload_tuser),
.output_3_eth_hdr_valid(output_3_eth_hdr_valid),
.output_3_eth_hdr_ready(output_3_eth_hdr_ready),
.output_3_eth_dest_mac(output_3_eth_dest_mac),
.output_3_eth_src_mac(output_3_eth_src_mac),
.output_3_eth_type(output_3_eth_type),
.output_3_eth_payload_tdata(output_3_eth_payload_tdata),
.output_3_eth_payload_tkeep(output_3_eth_payload_tkeep),
.output_3_eth_payload_tvalid(output_3_eth_payload_tvalid),
.output_3_eth_payload_tready(output_3_eth_payload_tready),
.output_3_eth_payload_tlast(output_3_eth_payload_tlast),
.output_3_eth_payload_tuser(output_3_eth_payload_tuser),
// Control // Control
.enable(enable), .enable(enable),
.drop(drop),
.select(select) .select(select)
); );