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README.md
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README.md
@ -61,107 +61,107 @@ Block diagram of the Corundum NIC. PCIe HIP: PCIe hard IP core; AXIL M: AXI lite
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### Modules
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#### cmac_pad module
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#### `cmac_pad` module
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Frame pad module for 512 bit 100G CMAC TX interface. Zero pads transmit
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frames to minimum 64 bytes.
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#### cpl_op_mux module
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#### `cpl_op_mux` module
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Completion operation multiplexer module. Merges completion write operations
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from different sources to enable sharing a single cpl_write module instance.
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from different sources to enable sharing a single `cpl_write` module instance.
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#### cpl_queue_manager module
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#### `cpl_queue_manager` module
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Completion queue manager module. Stores device to host queue state in block
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RAM or ultra RAM.
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#### cpl_write module
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#### `cpl_write` module
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Completion write module. Responsible for enqueuing completion and event
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records into the completion queue managers and writing records into host
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memory via DMA.
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#### desc_fetch module
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#### `desc_fetch` module
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Descriptor fetch module. Responsible for dequeuing descriptors from the queue
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managers and reading descriptors from host memory via DMA.
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#### desc_op_mux module
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#### `desc_op_mux` module
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Descriptor operation multiplexer module. Merges descriptor fetch operations
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from different sources to enable sharing a single desc_fetch module instance.
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from different sources to enable sharing a single `desc_fetch` module instance.
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#### event_mux module
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#### `event_mux` module
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Event mux module. Enables multiple event sources to feed the same event queue.
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#### mqnic_interface module
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#### `mqnic_interface` module
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Interface module. Contains the event queues, interface queues, and ports.
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#### mqnic_port module
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#### `mqnic_port` module
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Port module. Contains the transmit and receive datapath components, including
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transmit and receive engines and checksum and hash offloading.
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#### queue_manager module
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#### `queue_manager` module
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Queue manager module. Stores host to device queue state in block RAM or ultra
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RAM.
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#### rx_checksum module
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#### `rx_checksum` module
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Receive checksum computation module. Computes 16 bit checksum of Ethernet
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frame payload to aid in IP checksum offloading.
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#### rx_engine module
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#### `rx_engine` module
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Receive engine. Manages receive datapath operations including descriptor
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dequeue and fetch via DMA, packet reception, data writeback via DMA, and
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completion enqueue and writeback via DMA. Handles PTP timestamps for
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inclusion in completion records.
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#### rx_hash module
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#### `rx_hash` module
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Receive hash computation module. Extracts IP addresses and ports from packet
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headers and computes 32 bit Toeplitz flow hash.
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#### tdma_ber_ch module
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#### `tdma_ber_ch` module
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TDMA bit error ratio (BER) test channel module. Controls PRBS logic in
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Ethernet PHY and accumulates bit errors. Can be configured to bin error
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counts by TDMA timeslot.
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#### tdma_ber module
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#### `tdma_ber` module
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TDMA bit error ratio (BER) test module. Wrapper for a tdma_scheduler and
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multiple instances of tdma_ber_ch.
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multiple instances of `tdma_ber_ch`.
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#### tdma_scheduler module
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#### `tdma_scheduler` module
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TDMA scheduler module. Generates TDMA timeslot index and timing signals from
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PTP time.
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#### tx_checksum module
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#### `tx_checksum` module
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Transmit checksum computation and insertion module. Computes 16 bit checksum
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of frame data with specified start offset, then inserts computed checksum at
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the specified position.
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#### tx_engine module
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#### `tx_engine` module
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Transmit engine. Manages transmit datapath operations including descriptor
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dequeue and fetch via DMA, packet data fetch via DMA, packet transmission, and
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completion enqueue and writeback via DMA. Handles PTP timestamps for
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inclusion in completion records.
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#### tx_scheduler_ctrl_tdma module
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#### `tx_scheduler_ctrl_tdma` module
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TDMA transmit scheduler control module. Controls queues in a transmit
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scheduler based on PTP time, via a tdma_scheduler instance.
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scheduler based on PTP time, via a `tdma_scheduler` instance.
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#### tx_scheduler_rr module
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#### `tx_scheduler_rr` module
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Round-robin transmit scheduler. Determines which queues from which to send
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packets.
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