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Dump PHC and TDMA registers
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parent
f6da532b97
commit
1a739b326d
@ -110,6 +110,28 @@ int main(int argc, char *argv[])
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printf("IF stride: 0x%08x\n", dev->if_stride);
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printf("IF CSR offset: 0x%08x\n", dev->if_csr_offset);
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for (int k = 0; k < dev->phc_count; k++)
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{
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volatile uint8_t *phc_base = dev->phc_regs + k*dev->phc_stride;
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printf("PHC%d features: 0x%08x\n", k, mqnic_reg_read32(phc_base, MQNIC_PHC_REG_FEATURES));
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printf("PHC%d time: %ld.%09d s\n", k, mqnic_reg_read32(phc_base, MQNIC_PHC_REG_PTP_CUR_SEC_L) + (((int64_t)mqnic_reg_read32(phc_base, MQNIC_PHC_REG_PTP_CUR_SEC_H)) << 32), mqnic_reg_read32(phc_base, MQNIC_PHC_REG_PTP_CUR_NS));
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printf("PHC%d period: %d ns 0x%08x fns\n", k, mqnic_reg_read32(phc_base, MQNIC_PHC_REG_PTP_PERIOD_NS), mqnic_reg_read32(phc_base, MQNIC_PHC_REG_PTP_PERIOD_FNS));
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printf("PHC%d nom period: %d ns 0x%08x fns\n", k, mqnic_reg_read32(phc_base, MQNIC_PHC_REG_PTP_NOM_PERIOD_NS), mqnic_reg_read32(phc_base, MQNIC_PHC_REG_PTP_NOM_PERIOD_FNS));
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for (int ch = 0; ch < (mqnic_reg_read32(phc_base, MQNIC_PHC_REG_FEATURES) & 0xff); ch++)
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{
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volatile uint8_t *perout_base = phc_base + MQNIC_PHC_PEROUT_OFFSET + MQNIC_PHC_PEROUT_STRIDE*ch;
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printf("PHC%d perout ch %d ctrl: 0x%08x\n", k, ch, mqnic_reg_read32(perout_base, MQNIC_PHC_REG_PEROUT_CTRL));
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printf("PHC%d perout ch %d status: 0x%08x\n", k, ch, mqnic_reg_read32(perout_base, MQNIC_PHC_REG_PEROUT_STATUS));
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printf("PHC%d perout ch %d start: %ld.%09d s\n", k, ch, mqnic_reg_read32(perout_base, MQNIC_PHC_REG_PEROUT_START_SEC_L) + (((int64_t)mqnic_reg_read32(perout_base, MQNIC_PHC_REG_PEROUT_START_SEC_H)) << 32), mqnic_reg_read32(perout_base, MQNIC_PHC_REG_PEROUT_START_NS));
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printf("PHC%d perout ch %d period: %ld.%09d s\n", k, ch, mqnic_reg_read32(perout_base, MQNIC_PHC_REG_PEROUT_PERIOD_SEC_L) + (((int64_t)mqnic_reg_read32(perout_base, MQNIC_PHC_REG_PEROUT_PERIOD_SEC_H)) << 32), mqnic_reg_read32(perout_base, MQNIC_PHC_REG_PEROUT_PERIOD_NS));
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printf("PHC%d perout ch %d width: %ld.%09d s\n", k, ch, mqnic_reg_read32(perout_base, MQNIC_PHC_REG_PEROUT_WIDTH_SEC_L) + (((int64_t)mqnic_reg_read32(perout_base, MQNIC_PHC_REG_PEROUT_WIDTH_SEC_H)) << 32), mqnic_reg_read32(perout_base, MQNIC_PHC_REG_PEROUT_WIDTH_NS));
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}
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}
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if (interface < 0 || interface >= dev->if_count)
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{
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fprintf(stderr, "Interface out of range\n");
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@ -151,7 +173,17 @@ int main(int argc, char *argv[])
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printf("Sched stride: 0x%08x\n", dev_port->sched_stride);
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printf("Sched type: 0x%08x\n", dev_port->sched_type);
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printf("Timeslot count: %d\n", dev_port->tdma_timeslot_count);
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if (dev->phc_count > 0)
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{
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printf("TDMA control: 0x%08x\n", mqnic_reg_read32(dev_port->regs, MQNIC_PORT_REG_TDMA_CTRL));
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printf("TDMA status: 0x%08x\n", mqnic_reg_read32(dev_port->regs, MQNIC_PORT_REG_TDMA_STATUS));
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printf("TDMA timeslot count: %d\n", dev_port->tdma_timeslot_count);
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printf("TDMA schedule start: %ld.%09d s\n", mqnic_reg_read32(dev_port->regs, MQNIC_PORT_REG_TDMA_SCHED_START_SEC_L) + (((int64_t)mqnic_reg_read32(dev_port->regs, MQNIC_PORT_REG_TDMA_SCHED_START_SEC_H)) << 32), mqnic_reg_read32(dev_port->regs, MQNIC_PORT_REG_TDMA_SCHED_START_NS));
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printf("TDMA schedule period: %ld.%09d s\n", mqnic_reg_read32(dev_port->regs, MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_L) + (((int64_t)mqnic_reg_read32(dev_port->regs, MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_H)) << 32), mqnic_reg_read32(dev_port->regs, MQNIC_PORT_REG_TDMA_SCHED_PERIOD_NS));
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printf("TDMA timeslot period: %ld.%09d s\n", mqnic_reg_read32(dev_port->regs, MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_L) + (((int64_t)mqnic_reg_read32(dev_port->regs, MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_H)) << 32), mqnic_reg_read32(dev_port->regs, MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_NS));
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printf("TDMA active period: %ld.%09d s\n", mqnic_reg_read32(dev_port->regs, MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_L) + (((int64_t)mqnic_reg_read32(dev_port->regs, MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_H)) << 32), mqnic_reg_read32(dev_port->regs, MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_NS));
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}
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printf("TX queue info\n");
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printf(" Queue Base Address E LS CPL Head Tail Len\n");
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