Add RX completion stall feature to example design for testing completion buffer

Signed-off-by: Alex Forencich <alex@alexforencich.com>

example/common/rtl/example_core.v

@@ -162,7 +162,8 @@ module example_core #
     input  wire                                         dma_wr_busy,
     input  wire                                         dma_rd_req,
     input  wire                                         dma_rd_cpl,
-    input  wire                                         dma_wr_req
+    input  wire                                         dma_wr_req,
+    output wire                                         rx_cpl_stall
 );
 
 localparam RAM_ADDR_IMM_WIDTH = (DMA_IMM_ENABLE && (DMA_IMM_WIDTH > RAM_ADDR_WIDTH)) ? DMA_IMM_WIDTH : RAM_ADDR_WIDTH;
@@ -243,6 +244,9 @@ reg dma_rd_int_en_reg = 0, dma_rd_int_en_next;
 reg dma_wr_int_en_reg = 0, dma_wr_int_en_next;
 reg irq_valid_reg = 1'b0, irq_valid_next;
 
+reg rx_cpl_stall_reg = 1'b0, rx_cpl_stall_next;
+reg [23:0] rx_cpl_stall_count_reg = 0, rx_cpl_stall_count_next;
+
 reg dma_read_block_run_reg = 1'b0, dma_read_block_run_next;
 reg [DMA_LEN_WIDTH-1:0] dma_read_block_len_reg = 0, dma_read_block_len_next;
 reg [31:0] dma_read_block_count_reg = 0, dma_read_block_count_next;
@@ -298,6 +302,7 @@ assign irq_index = 0;
 assign irq_valid = irq_valid_reg;
 
 assign dma_enable = dma_enable_reg;
+assign rx_cpl_stall = rx_cpl_stall_reg;
 
 always @* begin
     axil_ctrl_awready_next = 1'b0;
@@ -337,6 +342,9 @@ always @* begin
 
     irq_valid_next = irq_valid_reg && !irq_ready;
 
+    rx_cpl_stall_next = 1'b0;
+    rx_cpl_stall_count_next = rx_cpl_stall_count_reg;
+
     dma_read_block_run_next = dma_read_block_run_reg;
     dma_read_block_len_next = dma_read_block_len_reg;
     dma_read_block_count_next = dma_read_block_count_reg;
@@ -363,6 +371,11 @@ always @* begin
     dma_write_block_ram_offset_mask_next = dma_write_block_ram_offset_mask_reg;
     dma_write_block_ram_stride_next = dma_write_block_ram_stride_reg;
 
+    if (rx_cpl_stall_count_reg) begin
+        rx_cpl_stall_count_next = rx_cpl_stall_count_reg - 1;
+        rx_cpl_stall_next = 1'b1;
+    end
+
     if (s_axil_ctrl_awvalid && s_axil_ctrl_wvalid && !axil_ctrl_bvalid_reg) begin
         // write operation
         axil_ctrl_awready_next = 1'b1;
@@ -379,6 +392,7 @@ always @* begin
                 dma_rd_int_en_next = s_axil_ctrl_wdata[0];
                 dma_wr_int_en_next = s_axil_ctrl_wdata[1];
             end
+            16'h0040: rx_cpl_stall_count_next = s_axil_ctrl_wdata;
             // single read
             16'h0100: dma_read_desc_dma_addr_next[31:0] = s_axil_ctrl_wdata;
             16'h0104: dma_read_desc_dma_addr_next[63:32] = s_axil_ctrl_wdata;
@@ -466,6 +480,7 @@ always @* begin
             16'h0020: axil_ctrl_rdata_next = dma_rd_req_count_reg;
             16'h0024: axil_ctrl_rdata_next = dma_rd_cpl_count_reg;
             16'h0028: axil_ctrl_rdata_next = dma_wr_req_count_reg;
+            16'h0040: axil_ctrl_rdata_next = rx_cpl_stall_count_reg;
             // single read
             16'h0100: axil_ctrl_rdata_next = dma_read_desc_dma_addr_reg;
             16'h0104: axil_ctrl_rdata_next = dma_read_desc_dma_addr_reg >> 32;
@@ -667,6 +682,9 @@ always @(posedge clk) begin
 
     irq_valid_reg <= irq_valid_next;
 
+    rx_cpl_stall_reg <= rx_cpl_stall_next;
+    rx_cpl_stall_count_reg <= rx_cpl_stall_count_next;
+
     dma_read_block_run_reg <= dma_read_block_run_next;
     dma_read_block_len_reg <= dma_read_block_len_next;
     dma_read_block_count_reg <= dma_read_block_count_next;
@@ -715,6 +733,8 @@ always @(posedge clk) begin
         dma_rd_int_en_reg <= 1'b0;
         dma_wr_int_en_reg <= 1'b0;
         irq_valid_reg <= 1'b0;
+        rx_cpl_stall_reg <= 1'b0;
+        rx_cpl_stall_count_reg <= 0;
         dma_read_block_run_reg <= 1'b0;
         dma_write_block_run_reg <= 1'b0;
     end

example/common/rtl/example_core_pcie.v

@@ -172,7 +172,12 @@ module example_core_pcie #
      * Status
      */
     output wire                                          status_error_cor,
-    output wire                                          status_error_uncor
+    output wire                                          status_error_uncor,
+
+    /*
+     * Control and status
+     */
+    output wire                                          rx_cpl_stall
 );
 
 parameter AXIL_CTRL_DATA_WIDTH = 32;
@@ -1124,7 +1129,8 @@ core_inst (
     .dma_wr_busy(dma_wr_busy),
     .dma_rd_req(tx_rd_req_tlp_valid && tx_rd_req_tlp_sop && tx_rd_req_tlp_ready),
     .dma_rd_cpl(rx_cpl_tlp_valid && rx_cpl_tlp_sop && rx_cpl_tlp_ready),
-    .dma_wr_req(tx_wr_req_tlp_valid && tx_wr_req_tlp_sop && tx_wr_req_tlp_ready)
+    .dma_wr_req(tx_wr_req_tlp_valid && tx_wr_req_tlp_sop && tx_wr_req_tlp_ready),
+    .rx_cpl_stall(rx_cpl_stall)
 );
 
 endmodule

example/common/rtl/example_core_pcie_ptile.v

@@ -200,6 +200,12 @@ wire [2:0] max_payload_size;
 wire msix_enable;
 wire msix_mask;
 
+wire rx_cpl_stall;
+
+wire rx_st_ready_int;
+
+assign rx_st_ready = rx_st_ready_int & !rx_cpl_stall;
+
 pcie_ptile_if #(
     .SEG_COUNT(SEG_COUNT),
     .SEG_DATA_WIDTH(SEG_DATA_WIDTH),
@@ -226,7 +232,7 @@ pcie_ptile_if_inst (
     .rx_st_sop(rx_st_sop),
     .rx_st_eop(rx_st_eop),
     .rx_st_valid(rx_st_valid),
-    .rx_st_ready(rx_st_ready),
+    .rx_st_ready(rx_st_ready_int),
     .rx_st_hdr(rx_st_hdr),
     .rx_st_tlp_prfx(rx_st_tlp_prfx),
     .rx_st_vf_active(rx_st_vf_active),
@@ -488,7 +494,12 @@ core_pcie_inst (
      * Status
      */
     .status_error_cor(),
-    .status_error_uncor()
+    .status_error_uncor(),
+
+    /*
+     * Control and status
+     */
+    .rx_cpl_stall(rx_cpl_stall)
 );
 
 endmodule

example/common/rtl/example_core_pcie_s10.v

@@ -194,6 +194,12 @@ wire [2:0] max_payload_size;
 wire msix_enable;
 wire msix_mask;
 
+wire rx_cpl_stall;
+
+wire rx_st_ready_int;
+
+assign rx_st_ready = rx_st_ready_int & !rx_cpl_stall;
+
 pcie_s10_if #(
     .SEG_COUNT(SEG_COUNT),
     .SEG_DATA_WIDTH(SEG_DATA_WIDTH),
@@ -222,7 +228,7 @@ pcie_s10_if_inst (
     .rx_st_sop(rx_st_sop),
     .rx_st_eop(rx_st_eop),
     .rx_st_valid(rx_st_valid),
-    .rx_st_ready(rx_st_ready),
+    .rx_st_ready(rx_st_ready_int),
     .rx_st_vf_active(rx_st_vf_active),
     .rx_st_func_num(rx_st_func_num),
     .rx_st_vf_num(rx_st_vf_num),
@@ -495,7 +501,12 @@ core_pcie_inst (
      * Status
      */
     .status_error_cor(),
-    .status_error_uncor()
+    .status_error_uncor(),
+
+    /*
+     * Control and status
+     */
+    .rx_cpl_stall(rx_cpl_stall)
 );
 
 endmodule

example/common/rtl/example_core_pcie_us.v

@@ -259,6 +259,14 @@ wire ext_tag_enable;
 wire msix_enable;
 wire msix_mask;
 
+wire rx_cpl_stall;
+
+wire s_axis_rc_tvalid_int;
+wire s_axis_rc_tready_int;
+
+assign s_axis_rc_tvalid_int = s_axis_rc_tvalid & ~rx_cpl_stall;
+assign s_axis_rc_tready = s_axis_rc_tready_int & ~rx_cpl_stall;
+
 pcie_us_if #(
     .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
     .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
@@ -295,8 +303,8 @@ pcie_us_if_inst (
      */
     .s_axis_rc_tdata(s_axis_rc_tdata),
     .s_axis_rc_tkeep(s_axis_rc_tkeep),
-    .s_axis_rc_tvalid(s_axis_rc_tvalid),
+    .s_axis_rc_tvalid(s_axis_rc_tvalid_int),
-    .s_axis_rc_tready(s_axis_rc_tready),
+    .s_axis_rc_tready(s_axis_rc_tready_int),
     .s_axis_rc_tlast(s_axis_rc_tlast),
     .s_axis_rc_tuser(s_axis_rc_tuser),
 
@@ -624,7 +632,12 @@ core_pcie_inst (
      * Status
      */
     .status_error_cor(status_error_cor),
-    .status_error_uncor(status_error_uncor)
+    .status_error_uncor(status_error_uncor),
+
+    /*
+     * Control and status
+     */
+    .rx_cpl_stall(rx_cpl_stall)
 );
 
 endmodule