Rename AU200 to Alveo

Signed-off-by: Alex Forencich <alex@alexforencich.com>

example/Alveo/fpga_25g/README.md

@@ -1,8 +1,8 @@
-# Verilog Ethernet Alveo U200/Alveo U250/VCU1525 Example Design
+# Verilog Ethernet Alveo Example Design
 
 ## Introduction
 
-This example design targets the Xilinx Alveo U200/Alveo U250/VCU1525 FPGA board.
+This design targets multiple FPGA boards, including most of the Xilinx Alveo line.
 
 The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received.  The design will also respond correctly to ARP requests.
 

example/Alveo/fpga_25g/fpga_AU200/Makefile

@@ -5,7 +5,7 @@ FPGA_TOP = fpga
 FPGA_ARCH = virtexuplus
 
 # Files for synthesis
-SYN_FILES = rtl/fpga.v
+SYN_FILES = rtl/fpga_au200.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
 SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
@@ -52,7 +52,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
 SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
 
 # XDC files
-XDC_FILES = fpga.xdc
+XDC_FILES = fpga_au200.xdc
 XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
 XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl

example/Alveo/fpga_25g/fpga_AU200_10g/Makefile

@@ -5,7 +5,7 @@ FPGA_TOP = fpga
 FPGA_ARCH = virtexuplus
 
 # Files for synthesis
-SYN_FILES = rtl/fpga.v
+SYN_FILES = rtl/fpga_au200.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
 SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
@@ -52,7 +52,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
 SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
 
 # XDC files
-XDC_FILES = fpga.xdc
+XDC_FILES = fpga_au200.xdc
 XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
 XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl

example/Alveo/fpga_25g/fpga_AU250/Makefile

@@ -5,7 +5,7 @@ FPGA_TOP = fpga
 FPGA_ARCH = virtexuplus
 
 # Files for synthesis
-SYN_FILES = rtl/fpga.v
+SYN_FILES = rtl/fpga_au200.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
 SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
@@ -52,7 +52,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
 SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
 
 # XDC files
-XDC_FILES = fpga.xdc
+XDC_FILES = fpga_au200.xdc
 XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
 XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl

example/Alveo/fpga_25g/fpga_AU250_10g/Makefile

@@ -5,7 +5,7 @@ FPGA_TOP = fpga
 FPGA_ARCH = virtexuplus
 
 # Files for synthesis
-SYN_FILES = rtl/fpga.v
+SYN_FILES = rtl/fpga_au200.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
 SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
@@ -52,7 +52,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
 SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
 
 # XDC files
-XDC_FILES = fpga.xdc
+XDC_FILES = fpga_au200.xdc
 XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
 XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl

example/Alveo/fpga_25g/fpga_VCU1525/Makefile

@@ -5,7 +5,7 @@ FPGA_TOP = fpga
 FPGA_ARCH = virtexuplus
 
 # Files for synthesis
-SYN_FILES = rtl/fpga.v
+SYN_FILES = rtl/fpga_au200.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
 SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
@@ -52,7 +52,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
 SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
 
 # XDC files
-XDC_FILES = fpga.xdc
+XDC_FILES = fpga_au200.xdc
 XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
 XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl

example/Alveo/fpga_25g/fpga_VCU1525_10g/Makefile

@@ -5,7 +5,7 @@ FPGA_TOP = fpga
 FPGA_ARCH = virtexuplus
 
 # Files for synthesis
-SYN_FILES = rtl/fpga.v
+SYN_FILES = rtl/fpga_au200.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
 SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
@@ -52,7 +52,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
 SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
 
 # XDC files
-XDC_FILES = fpga.xdc
+XDC_FILES = fpga_au200.xdc
 XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
 XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
 XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl