From 1b29a88b18fc57d9c4fe753d2f22177760f47ed0 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 8 Nov 2023 11:50:50 -0800 Subject: [PATCH] Rename AU200 to Alveo Signed-off-by: Alex Forencich --- example/{AU200 => Alveo}/fpga_25g/Makefile | 0 example/{AU200 => Alveo}/fpga_25g/README.md | 4 ++-- example/{AU200 => Alveo}/fpga_25g/common/vivado.mk | 0 example/{AU200 => Alveo}/fpga_25g/fpga_AU200/Makefile | 4 ++-- example/{AU200 => Alveo}/fpga_25g/fpga_AU200/config.tcl | 0 example/{AU200 => Alveo}/fpga_25g/fpga_AU200_10g/Makefile | 4 ++-- example/{AU200 => Alveo}/fpga_25g/fpga_AU200_10g/config.tcl | 0 example/{AU200 => Alveo}/fpga_25g/fpga_AU250/Makefile | 4 ++-- example/{AU200 => Alveo}/fpga_25g/fpga_AU250/config.tcl | 0 example/{AU200 => Alveo}/fpga_25g/fpga_AU250_10g/Makefile | 4 ++-- example/{AU200 => Alveo}/fpga_25g/fpga_AU250_10g/config.tcl | 0 example/{AU200 => Alveo}/fpga_25g/fpga_VCU1525/Makefile | 4 ++-- example/{AU200 => Alveo}/fpga_25g/fpga_VCU1525/config.tcl | 0 example/{AU200 => Alveo}/fpga_25g/fpga_VCU1525_10g/Makefile | 4 ++-- example/{AU200 => Alveo}/fpga_25g/fpga_VCU1525_10g/config.tcl | 0 .../fpga_25g/fpga.xdc => Alveo/fpga_25g/fpga_au200.xdc} | 0 example/{AU200 => Alveo}/fpga_25g/ip/eth_xcvr_gt.tcl | 0 example/{AU200 => Alveo}/fpga_25g/lib/eth | 0 example/{AU200 => Alveo}/fpga_25g/rtl/debounce_switch.v | 0 .../{AU200 => Alveo}/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v | 0 example/{AU200 => Alveo}/fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 0 .../fpga_25g/rtl/fpga.v => Alveo/fpga_25g/rtl/fpga_au200.v} | 0 example/{AU200 => Alveo}/fpga_25g/rtl/fpga_core.v | 0 example/{AU200 => Alveo}/fpga_25g/rtl/sync_signal.v | 0 example/{AU200 => Alveo}/fpga_25g/tb/fpga_core/Makefile | 0 .../{AU200 => Alveo}/fpga_25g/tb/fpga_core/test_fpga_core.py | 0 26 files changed, 14 insertions(+), 14 deletions(-) rename example/{AU200 => Alveo}/fpga_25g/Makefile (100%) rename example/{AU200 => Alveo}/fpga_25g/README.md (84%) rename example/{AU200 => Alveo}/fpga_25g/common/vivado.mk (100%) rename example/{AU200 => Alveo}/fpga_25g/fpga_AU200/Makefile (98%) rename example/{AU200 => Alveo}/fpga_25g/fpga_AU200/config.tcl (100%) rename example/{AU200 => Alveo}/fpga_25g/fpga_AU200_10g/Makefile (98%) rename example/{AU200 => Alveo}/fpga_25g/fpga_AU200_10g/config.tcl (100%) rename example/{AU200 => Alveo}/fpga_25g/fpga_AU250/Makefile (98%) rename example/{AU200 => Alveo}/fpga_25g/fpga_AU250/config.tcl (100%) rename example/{AU200 => Alveo}/fpga_25g/fpga_AU250_10g/Makefile (98%) rename example/{AU200 => Alveo}/fpga_25g/fpga_AU250_10g/config.tcl (100%) rename example/{AU200 => Alveo}/fpga_25g/fpga_VCU1525/Makefile (99%) rename example/{AU200 => Alveo}/fpga_25g/fpga_VCU1525/config.tcl (100%) rename example/{AU200 => Alveo}/fpga_25g/fpga_VCU1525_10g/Makefile (99%) rename example/{AU200 => Alveo}/fpga_25g/fpga_VCU1525_10g/config.tcl (100%) rename example/{AU200/fpga_25g/fpga.xdc => Alveo/fpga_25g/fpga_au200.xdc} (100%) rename example/{AU200 => Alveo}/fpga_25g/ip/eth_xcvr_gt.tcl (100%) rename example/{AU200 => Alveo}/fpga_25g/lib/eth (100%) rename example/{AU200 => Alveo}/fpga_25g/rtl/debounce_switch.v (100%) rename example/{AU200 => Alveo}/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v (100%) rename example/{AU200 => Alveo}/fpga_25g/rtl/eth_xcvr_phy_wrapper.v (100%) rename example/{AU200/fpga_25g/rtl/fpga.v => Alveo/fpga_25g/rtl/fpga_au200.v} (100%) rename example/{AU200 => Alveo}/fpga_25g/rtl/fpga_core.v (100%) rename example/{AU200 => Alveo}/fpga_25g/rtl/sync_signal.v (100%) rename example/{AU200 => Alveo}/fpga_25g/tb/fpga_core/Makefile (100%) rename example/{AU200 => Alveo}/fpga_25g/tb/fpga_core/test_fpga_core.py (100%) diff --git a/example/AU200/fpga_25g/Makefile b/example/Alveo/fpga_25g/Makefile similarity index 100% rename from example/AU200/fpga_25g/Makefile rename to example/Alveo/fpga_25g/Makefile diff --git a/example/AU200/fpga_25g/README.md b/example/Alveo/fpga_25g/README.md similarity index 84% rename from example/AU200/fpga_25g/README.md rename to example/Alveo/fpga_25g/README.md index 060e326a4..a02a6418e 100644 --- a/example/AU200/fpga_25g/README.md +++ b/example/Alveo/fpga_25g/README.md @@ -1,8 +1,8 @@ -# Verilog Ethernet Alveo U200/Alveo U250/VCU1525 Example Design +# Verilog Ethernet Alveo Example Design ## Introduction -This example design targets the Xilinx Alveo U200/Alveo U250/VCU1525 FPGA board. +This design targets multiple FPGA boards, including most of the Xilinx Alveo line. The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. diff --git a/example/AU200/fpga_25g/common/vivado.mk b/example/Alveo/fpga_25g/common/vivado.mk similarity index 100% rename from example/AU200/fpga_25g/common/vivado.mk rename to example/Alveo/fpga_25g/common/vivado.mk diff --git a/example/AU200/fpga_25g/fpga_AU200/Makefile b/example/Alveo/fpga_25g/fpga_AU200/Makefile similarity index 98% rename from example/AU200/fpga_25g/fpga_AU200/Makefile rename to example/Alveo/fpga_25g/fpga_AU200/Makefile index 9f2647361..8ca8e89ed 100644 --- a/example/AU200/fpga_25g/fpga_AU200/Makefile +++ b/example/Alveo/fpga_25g/fpga_AU200/Makefile @@ -5,7 +5,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au200.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v @@ -52,7 +52,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au200.xdc XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl diff --git a/example/AU200/fpga_25g/fpga_AU200/config.tcl b/example/Alveo/fpga_25g/fpga_AU200/config.tcl similarity index 100% rename from example/AU200/fpga_25g/fpga_AU200/config.tcl rename to example/Alveo/fpga_25g/fpga_AU200/config.tcl diff --git a/example/AU200/fpga_25g/fpga_AU200_10g/Makefile b/example/Alveo/fpga_25g/fpga_AU200_10g/Makefile similarity index 98% rename from example/AU200/fpga_25g/fpga_AU200_10g/Makefile rename to example/Alveo/fpga_25g/fpga_AU200_10g/Makefile index 9f2647361..8ca8e89ed 100644 --- a/example/AU200/fpga_25g/fpga_AU200_10g/Makefile +++ b/example/Alveo/fpga_25g/fpga_AU200_10g/Makefile @@ -5,7 +5,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au200.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v @@ -52,7 +52,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au200.xdc XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl diff --git a/example/AU200/fpga_25g/fpga_AU200_10g/config.tcl b/example/Alveo/fpga_25g/fpga_AU200_10g/config.tcl similarity index 100% rename from example/AU200/fpga_25g/fpga_AU200_10g/config.tcl rename to example/Alveo/fpga_25g/fpga_AU200_10g/config.tcl diff --git a/example/AU200/fpga_25g/fpga_AU250/Makefile b/example/Alveo/fpga_25g/fpga_AU250/Makefile similarity index 98% rename from example/AU200/fpga_25g/fpga_AU250/Makefile rename to example/Alveo/fpga_25g/fpga_AU250/Makefile index 63c549ec3..af5765609 100644 --- a/example/AU200/fpga_25g/fpga_AU250/Makefile +++ b/example/Alveo/fpga_25g/fpga_AU250/Makefile @@ -5,7 +5,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au200.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v @@ -52,7 +52,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au200.xdc XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl diff --git a/example/AU200/fpga_25g/fpga_AU250/config.tcl b/example/Alveo/fpga_25g/fpga_AU250/config.tcl similarity index 100% rename from example/AU200/fpga_25g/fpga_AU250/config.tcl rename to example/Alveo/fpga_25g/fpga_AU250/config.tcl diff --git a/example/AU200/fpga_25g/fpga_AU250_10g/Makefile b/example/Alveo/fpga_25g/fpga_AU250_10g/Makefile similarity index 98% rename from example/AU200/fpga_25g/fpga_AU250_10g/Makefile rename to example/Alveo/fpga_25g/fpga_AU250_10g/Makefile index 63c549ec3..af5765609 100644 --- a/example/AU200/fpga_25g/fpga_AU250_10g/Makefile +++ b/example/Alveo/fpga_25g/fpga_AU250_10g/Makefile @@ -5,7 +5,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au200.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v @@ -52,7 +52,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au200.xdc XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl diff --git a/example/AU200/fpga_25g/fpga_AU250_10g/config.tcl b/example/Alveo/fpga_25g/fpga_AU250_10g/config.tcl similarity index 100% rename from example/AU200/fpga_25g/fpga_AU250_10g/config.tcl rename to example/Alveo/fpga_25g/fpga_AU250_10g/config.tcl diff --git a/example/AU200/fpga_25g/fpga_VCU1525/Makefile b/example/Alveo/fpga_25g/fpga_VCU1525/Makefile similarity index 99% rename from example/AU200/fpga_25g/fpga_VCU1525/Makefile rename to example/Alveo/fpga_25g/fpga_VCU1525/Makefile index c189feaac..f60daad3c 100644 --- a/example/AU200/fpga_25g/fpga_VCU1525/Makefile +++ b/example/Alveo/fpga_25g/fpga_VCU1525/Makefile @@ -5,7 +5,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au200.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v @@ -52,7 +52,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au200.xdc XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl diff --git a/example/AU200/fpga_25g/fpga_VCU1525/config.tcl b/example/Alveo/fpga_25g/fpga_VCU1525/config.tcl similarity index 100% rename from example/AU200/fpga_25g/fpga_VCU1525/config.tcl rename to example/Alveo/fpga_25g/fpga_VCU1525/config.tcl diff --git a/example/AU200/fpga_25g/fpga_VCU1525_10g/Makefile b/example/Alveo/fpga_25g/fpga_VCU1525_10g/Makefile similarity index 99% rename from example/AU200/fpga_25g/fpga_VCU1525_10g/Makefile rename to example/Alveo/fpga_25g/fpga_VCU1525_10g/Makefile index c189feaac..f60daad3c 100644 --- a/example/AU200/fpga_25g/fpga_VCU1525_10g/Makefile +++ b/example/Alveo/fpga_25g/fpga_VCU1525_10g/Makefile @@ -5,7 +5,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au200.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v @@ -52,7 +52,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au200.xdc XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl diff --git a/example/AU200/fpga_25g/fpga_VCU1525_10g/config.tcl b/example/Alveo/fpga_25g/fpga_VCU1525_10g/config.tcl similarity index 100% rename from example/AU200/fpga_25g/fpga_VCU1525_10g/config.tcl rename to example/Alveo/fpga_25g/fpga_VCU1525_10g/config.tcl diff --git a/example/AU200/fpga_25g/fpga.xdc b/example/Alveo/fpga_25g/fpga_au200.xdc similarity index 100% rename from example/AU200/fpga_25g/fpga.xdc rename to example/Alveo/fpga_25g/fpga_au200.xdc diff --git a/example/AU200/fpga_25g/ip/eth_xcvr_gt.tcl b/example/Alveo/fpga_25g/ip/eth_xcvr_gt.tcl similarity index 100% rename from example/AU200/fpga_25g/ip/eth_xcvr_gt.tcl rename to example/Alveo/fpga_25g/ip/eth_xcvr_gt.tcl diff --git a/example/AU200/fpga_25g/lib/eth b/example/Alveo/fpga_25g/lib/eth similarity index 100% rename from example/AU200/fpga_25g/lib/eth rename to example/Alveo/fpga_25g/lib/eth diff --git a/example/AU200/fpga_25g/rtl/debounce_switch.v b/example/Alveo/fpga_25g/rtl/debounce_switch.v similarity index 100% rename from example/AU200/fpga_25g/rtl/debounce_switch.v rename to example/Alveo/fpga_25g/rtl/debounce_switch.v diff --git a/example/AU200/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/Alveo/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v similarity index 100% rename from example/AU200/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v rename to example/Alveo/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v diff --git a/example/AU200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/Alveo/fpga_25g/rtl/eth_xcvr_phy_wrapper.v similarity index 100% rename from example/AU200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v rename to example/Alveo/fpga_25g/rtl/eth_xcvr_phy_wrapper.v diff --git a/example/AU200/fpga_25g/rtl/fpga.v b/example/Alveo/fpga_25g/rtl/fpga_au200.v similarity index 100% rename from example/AU200/fpga_25g/rtl/fpga.v rename to example/Alveo/fpga_25g/rtl/fpga_au200.v diff --git a/example/AU200/fpga_25g/rtl/fpga_core.v b/example/Alveo/fpga_25g/rtl/fpga_core.v similarity index 100% rename from example/AU200/fpga_25g/rtl/fpga_core.v rename to example/Alveo/fpga_25g/rtl/fpga_core.v diff --git a/example/AU200/fpga_25g/rtl/sync_signal.v b/example/Alveo/fpga_25g/rtl/sync_signal.v similarity index 100% rename from example/AU200/fpga_25g/rtl/sync_signal.v rename to example/Alveo/fpga_25g/rtl/sync_signal.v diff --git a/example/AU200/fpga_25g/tb/fpga_core/Makefile b/example/Alveo/fpga_25g/tb/fpga_core/Makefile similarity index 100% rename from example/AU200/fpga_25g/tb/fpga_core/Makefile rename to example/Alveo/fpga_25g/tb/fpga_core/Makefile diff --git a/example/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py b/example/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.py similarity index 100% rename from example/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py rename to example/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.py