mirror of
https://github.com/corundum/corundum.git
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fpga/mqnic/ZCU102: Add 10G mqnic design for ZCU102
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
171c2a9a69
commit
1b9f5d1032
@ -41,6 +41,7 @@ Corundum currently supports devices from both Xilinx and Intel, on boards from s
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* Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095)
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* Xilinx VCU118 (Xilinx Virtex UltraScale+ XCVU9P)
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* Xilinx VCU1525 (Xilinx Virtex UltraScale+ XCVU9P)
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* Xilinx ZCU102 (Xilinx Zynq UltraScale+ XCZU9EG)
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* Xilinx ZCU106 (Xilinx Zynq UltraScale+ XCZU7EV)
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For operation at 10G and 25G, Corundum uses the open source 10G/25G MAC and PHY modules from the verilog-ethernet repository, no extra licenses are required. However, it is possible to use other MAC and/or PHY modules.
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@ -177,6 +177,7 @@ This section details SoC targets, which interface with CPU cores on the same dev
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============ ================= ==================== ==========
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Manufacturer Board FPGA Board ID
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============ ================= ==================== ==========
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Xilinx ZCU102 XCZU9EG-2FFVB1156E 0x10ee9066
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Xilinx ZCU106 XCZU7EV-2FFVC1156E 0x10ee906a
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============ ================= ==================== ==========
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@ -185,6 +186,7 @@ This section details SoC targets, which interface with CPU cores on the same dev
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================= ========= ========== =============================== =====
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Board PCIe IF Network IF DDR HBM
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================= ========= ========== =============================== =====
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ZCU102 \- 4x SFP+ 2 GB DDR4 2400 (256M x64) \-
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ZCU106 Gen 3 x4 2x SFP+ 2 GB DDR4 2400 (256M x64) \-
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================= ========= ========== =============================== =====
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@ -193,6 +195,7 @@ This section details SoC targets, which interface with CPU cores on the same dev
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================= ============ ============ ==========
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Board I2C :sup:`1` MAC :sup:`2` FW update
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================= ============ ============ ==========
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ZCU102 Y Y :sup:`3` N
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ZCU106 Y Y :sup:`3` N
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================= ============ ============ ==========
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@ -205,5 +208,6 @@ This section details SoC targets, which interface with CPU cores on the same dev
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================= ========================= ==== ======= ==== =====
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Board Design IFxP RXQ/TXQ MAC Sched
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================= ========================= ==== ======= ==== =====
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ZCU102 mqnic/fpga/fpga 2x1 32/32 10G RR
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ZCU106 mqnic/fpga_zynqmp/fpga 2x1 32/32 10G RR
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================= ========================= ==== ======= ==== =====
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@ -33,6 +33,7 @@ Corundum currently supports devices from both Xilinx and Intel, on boards from s
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* Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095)
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* Xilinx VCU118 (Xilinx Virtex UltraScale+ XCVU9P)
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* Xilinx VCU1525 (Xilinx Virtex UltraScale+ XCVU9P)
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* Xilinx ZCU102 (Xilinx Zynq UltraScale+ XCZU9EG)
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* Xilinx ZCU106 (Xilinx Zynq UltraScale+ XCZU7EV)
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Publications
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25
fpga/mqnic/ZCU102/fpga/Makefile
Normal file
25
fpga/mqnic/ZCU102/fpga/Makefile
Normal file
@ -0,0 +1,25 @@
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# Targets
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TARGETS:=
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# Subdirectories
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SUBDIRS = fpga
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SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
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# Rules
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.PHONY: all
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all: $(SUBDIRS) $(TARGETS)
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.PHONY: $(SUBDIRS)
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$(SUBDIRS):
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cd $@ && $(MAKE)
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.PHONY: $(SUBDIRS_CLEAN)
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$(SUBDIRS_CLEAN):
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cd $(@:.clean=) && $(MAKE) clean
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.PHONY: clean
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clean: $(SUBDIRS_CLEAN)
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-rm -rf $(TARGETS)
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program:
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#djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit
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31
fpga/mqnic/ZCU102/fpga/README.md
Normal file
31
fpga/mqnic/ZCU102/fpga/README.md
Normal file
@ -0,0 +1,31 @@
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# Corundum mqnic for ZCU102 using ZynqMP PS as host system
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## Introduction
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This design targets the Xilinx ZCU102 FPGA board. The host system of the NIC is
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the Zynq US+ MPSoC.
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FPGA: xczu9eg-ffvb1156-2-e
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PHY: 10G BASE-R PHY IP core and internal GTH transceiver
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## How to build
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Run make in this directory to build the bitstream and the .xsa
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file. Ensure that the Xilinx Vivado toolchain components are in PATH.
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Then change into sub-directory ps/petalinux/ and build the PetaLinux project.
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Ensure that the Xilinx PetaLinux toolchain components are in PATH.
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make -C ps/petalinux/ build-boot
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## How to test
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Copy the following, resulting files of building the PetaLinux project onto an
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SDcard suitable for then booting the ZCU102 in SDcard boot mode.
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ps/petalinux/images/linux/:
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BOOT.BIN
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boot.scr
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Image
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system.dtb
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rootfs.cpio.gz.u-boot
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1
fpga/mqnic/ZCU102/fpga/app
Symbolic link
1
fpga/mqnic/ZCU102/fpga/app
Symbolic link
@ -0,0 +1 @@
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../../../app/
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129
fpga/mqnic/ZCU102/fpga/common/vivado.mk
Normal file
129
fpga/mqnic/ZCU102/fpga/common/vivado.mk
Normal file
@ -0,0 +1,129 @@
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###################################################################
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#
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# Xilinx Vivado FPGA Makefile
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#
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# Copyright (c) 2016 Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
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# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
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# SYN_FILES - space-separated list of source files
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# INC_FILES - space-separated list of include files
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# XDC_FILES - space-separated list of timing constraint files
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# XCI_FILES - space-separated list of IP XCI files
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = VirtexUltrascale
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# FPGA_DEVICE = xcvu095-ffva2104-2-e
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# SYN_FILES = rtl/fpga.v
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# XDC_FILES = fpga.xdc
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# XCI_FILES = ip/pcspma.xci
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# include ../common/vivado.mk
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#
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###################################################################
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# phony targets
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.PHONY: fpga vivado tmpclean clean distclean
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit %.mcs %.prm
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.SECONDARY:
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CONFIG ?= config.mk
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-include ../$(CONFIG)
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SYN_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(SYN_FILES))) $(filter /% ./%,$(SYN_FILES))
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INC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(INC_FILES))) $(filter /% ./%,$(INC_FILES))
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XCI_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XCI_FILES))) $(filter /% ./%,$(XCI_FILES))
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IP_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(IP_TCL_FILES))) $(filter /% ./%,$(IP_TCL_FILES))
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CONFIG_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(CONFIG_TCL_FILES))) $(filter /% ./%,$(CONFIG_TCL_FILES))
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ifdef XDC_FILES
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XDC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XDC_FILES))) $(filter /% ./%,$(XDC_FILES))
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else
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XDC_FILES_REL = $(FPGA_TOP).xdc
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endif
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###################################################################
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# Main Targets
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#
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# all: build everything
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# clean: remove output files and project files
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###################################################################
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all: fpga
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fpga: $(FPGA_TOP).bit
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vivado: $(FPGA_TOP).xpr
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vivado $(FPGA_TOP).xpr
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tmpclean::
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-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
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-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
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clean:: tmpclean
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-rm -rf *.bit *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
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distclean:: clean
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-rm -rf rev
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###################################################################
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# Target implementations
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###################################################################
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# Vivado project file
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create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
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rm -rf defines.v
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touch defines.v
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo "create_project -force -part $(FPGA_PART) $(FPGA_TOP)" > $@
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echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@
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echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@
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for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done
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for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done
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for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
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update_config.tcl: $(CONFIG_TCL_FILES_REL)
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echo "open_project -quiet $(FPGA_TOP).xpr" > $@
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for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
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$(FPGA_TOP).xpr: create_project.tcl update_config.tcl
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vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
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# synthesis run
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%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) $(CONFIG_TCL_FILES_REL)
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echo "open_project $*.xpr" > run_synth.tcl
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echo "reset_run synth_1" >> run_synth.tcl
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echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
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echo "wait_on_run synth_1" >> run_synth.tcl
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vivado -nojournal -nolog -mode batch -source run_synth.tcl
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# implementation run
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%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
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echo "open_project $*.xpr" > run_impl.tcl
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echo "reset_run impl_1" >> run_impl.tcl
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echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
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echo "wait_on_run impl_1" >> run_impl.tcl
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vivado -nojournal -nolog -mode batch -source run_impl.tcl
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# bit file
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%.bit: %.runs/impl_1/%_routed.dcp
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echo "open_project $*.xpr" > generate_bit.tcl
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echo "open_run impl_1" >> generate_bit.tcl
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echo "write_bitstream -force $*.runs/impl_1/$*.bit" >> generate_bit.tcl
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echo "write_hw_platform -fixed -force -include_bit $*.xsa" >> generate_bit.tcl
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vivado -nojournal -nolog -mode batch -source generate_bit.tcl
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ln -f -s $*.runs/impl_1/$*.bit .
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mkdir -p rev
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EXT=bit; COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
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do COUNT=$$((COUNT+1)); done; \
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cp $*.bit rev/$*_rev$$COUNT.bit; \
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cp $*.xsa rev/$*_rev$$COUNT.xsa; \
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echo "Output: rev/$*_rev$$COUNT.$$EXT";
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109
fpga/mqnic/ZCU102/fpga/fpga.xdc
Normal file
109
fpga/mqnic/ZCU102/fpga/fpga.xdc
Normal file
@ -0,0 +1,109 @@
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# XDC constraints for the Xilinx ZCU102 board
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# part: xczu9eg-ffvb1156-2-e
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# General configuration
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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# System clocks
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# 125 MHz
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set_property -dict {LOC G21 IOSTANDARD LVDS_25} [get_ports clk_125mhz_p]
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set_property -dict {LOC F21 IOSTANDARD LVDS_25} [get_ports clk_125mhz_n]
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create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
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# LEDs
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set_property -dict {LOC AG14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
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set_property -dict {LOC AF13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[1]}]
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set_property -dict {LOC AE13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[2]}]
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set_property -dict {LOC AJ14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[3]}]
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set_property -dict {LOC AJ15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[4]}]
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set_property -dict {LOC AH13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[5]}]
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set_property -dict {LOC AH14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[6]}]
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set_property -dict {LOC AL12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[7]}]
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set_false_path -to [get_ports {led[*]}]
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set_output_delay 0 [get_ports {led[*]}]
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# Reset button
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#set_property -dict {LOC AM13 IOSTANDARD LVCMOS33} [get_ports reset]
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#set_false_path -from [get_ports {reset}]
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#set_input_delay 0 [get_ports {reset}]
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# Push buttons
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set_property -dict {LOC AG15 IOSTANDARD LVCMOS33} [get_ports btnu]
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set_property -dict {LOC AF15 IOSTANDARD LVCMOS33} [get_ports btnl]
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set_property -dict {LOC AE15 IOSTANDARD LVCMOS33} [get_ports btnd]
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set_property -dict {LOC AE14 IOSTANDARD LVCMOS33} [get_ports btnr]
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set_property -dict {LOC AG13 IOSTANDARD LVCMOS33} [get_ports btnc]
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set_false_path -from [get_ports {btnu btnl btnd btnr btnc}]
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set_input_delay 0 [get_ports {btnu btnl btnd btnr btnc}]
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# DIP switches
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set_property -dict {LOC AN14 IOSTANDARD LVCMOS33} [get_ports {sw[0]}]
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set_property -dict {LOC AP14 IOSTANDARD LVCMOS33} [get_ports {sw[1]}]
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set_property -dict {LOC AM14 IOSTANDARD LVCMOS33} [get_ports {sw[2]}]
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set_property -dict {LOC AN13 IOSTANDARD LVCMOS33} [get_ports {sw[3]}]
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set_property -dict {LOC AN12 IOSTANDARD LVCMOS33} [get_ports {sw[4]}]
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set_property -dict {LOC AP12 IOSTANDARD LVCMOS33} [get_ports {sw[5]}]
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set_property -dict {LOC AL13 IOSTANDARD LVCMOS33} [get_ports {sw[6]}]
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set_property -dict {LOC AK13 IOSTANDARD LVCMOS33} [get_ports {sw[7]}]
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set_false_path -from [get_ports {sw[*]}]
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set_input_delay 0 [get_ports {sw[*]}]
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# UART
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#set_property -dict {LOC F13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_txd]
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#set_property -dict {LOC E13 IOSTANDARD LVCMOS33} [get_ports uart_rxd]
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#set_property -dict {LOC D12 IOSTANDARD LVCMOS33} [get_ports uart_rts]
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#set_property -dict {LOC E12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_cts]
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#set_false_path -to [get_ports {uart_txd uart_cts}]
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#set_output_delay 0 [get_ports {uart_txd uart_cts}]
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#set_false_path -from [get_ports {uart_rxd uart_rts}]
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#set_input_delay 0 [get_ports {uart_rxd uart_rts}]
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# I2C interfaces
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#set_property -dict {LOC J10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c0_scl]
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#set_property -dict {LOC J11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c0_sda]
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#set_property -dict {LOC K20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c1_scl]
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#set_property -dict {LOC L20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c1_sda]
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#set_false_path -to [get_ports {i2c1_sda i2c1_scl}]
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#set_output_delay 0 [get_ports {i2c1_sda i2c1_scl}]
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#set_false_path -from [get_ports {i2c1_sda i2c1_scl}]
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#set_input_delay 0 [get_ports {i2c1_sda i2c1_scl}]
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# SFP+ Interface
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set_property -dict {LOC D2 } [get_ports sfp0_rx_p] ;# MGTHRXP0_230 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC D1 } [get_ports sfp0_rx_n] ;# MGTHRXN0_230 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC E4 } [get_ports sfp0_tx_p] ;# MGTHTXP0_230 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC E3 } [get_ports sfp0_tx_n] ;# MGTHTXN0_230 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC C4 } [get_ports sfp1_rx_p] ;# MGTHRXP1_230 GTHE4_CHANNEL_X1Y13 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC C3 } [get_ports sfp1_rx_n] ;# MGTHRXN1_230 GTHE4_CHANNEL_X1Y13 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC D6 } [get_ports sfp1_tx_p] ;# MGTHTXP1_230 GTHE4_CHANNEL_X1Y13 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC D5 } [get_ports sfp1_tx_n] ;# MGTHTXN1_230 GTHE4_CHANNEL_X1Y13 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC B2 } [get_ports sfp2_rx_p] ;# MGTHRXP2_230 GTHE4_CHANNEL_X1Y14 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC B1 } [get_ports sfp2_rx_n] ;# MGTHRXN2_230 GTHE4_CHANNEL_X1Y14 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC B6 } [get_ports sfp2_tx_p] ;# MGTHTXP2_230 GTHE4_CHANNEL_X1Y14 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC B5 } [get_ports sfp2_tx_n] ;# MGTHTXN2_230 GTHE4_CHANNEL_X1Y14 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC A4 } [get_ports sfp3_rx_p] ;# MGTHRXP3_230 GTHE4_CHANNEL_X1Y15 / GTHE4_COMMON_X1Y3
|
||||
set_property -dict {LOC A3 } [get_ports sfp3_rx_n] ;# MGTHRXN3_230 GTHE4_CHANNEL_X1Y15 / GTHE4_COMMON_X1Y3
|
||||
set_property -dict {LOC A8 } [get_ports sfp3_tx_p] ;# MGTHTXP3_230 GTHE4_CHANNEL_X1Y15 / GTHE4_COMMON_X1Y3
|
||||
set_property -dict {LOC A7 } [get_ports sfp3_tx_n] ;# MGTHTXN3_230 GTHE4_CHANNEL_X1Y15 / GTHE4_COMMON_X1Y3
|
||||
set_property -dict {LOC C8 } [get_ports sfp_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U56 SI570 via U51 SI53340
|
||||
set_property -dict {LOC C7 } [get_ports sfp_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U56 SI570 via U51 SI53340
|
||||
#set_property -dict {LOC B10 } [get_ports sfp_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U20 CKOUT2 SI5328
|
||||
#set_property -dict {LOC B9 } [get_ports sfp_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U20 CKOUT2 SI5328
|
||||
#set_property -dict {LOC R10 IOSTANDARD LVDS} [get_ports sfp_recclk_p] ;# to U20 CKIN1 SI5328
|
||||
#set_property -dict {LOC R9 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to U20 CKIN1 SI5328
|
||||
set_property -dict {LOC A12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports sfp0_tx_disable_b]
|
||||
set_property -dict {LOC A13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports sfp1_tx_disable_b]
|
||||
set_property -dict {LOC B13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports sfp2_tx_disable_b]
|
||||
set_property -dict {LOC C13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports sfp3_tx_disable_b]
|
||||
|
||||
# 156.25 MHz MGT reference clock
|
||||
create_clock -period 6.400 -name sfp_mgt_refclk_0 [get_ports sfp_mgt_refclk_0_p]
|
||||
|
||||
set_false_path -to [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b sfp2_tx_disable_b sfp3_tx_disable_b}]
|
||||
set_output_delay 0 [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b sfp2_tx_disable_b sfp3_tx_disable_b}]
|
||||
3
fpga/mqnic/ZCU102/fpga/fpga/.gitignore
vendored
Normal file
3
fpga/mqnic/ZCU102/fpga/fpga/.gitignore
vendored
Normal file
@ -0,0 +1,3 @@
|
||||
*
|
||||
!/config.tcl
|
||||
!/Makefile
|
||||
136
fpga/mqnic/ZCU102/fpga/fpga/Makefile
Normal file
136
fpga/mqnic/ZCU102/fpga/fpga/Makefile
Normal file
@ -0,0 +1,136 @@
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xczu9eg-ffvb1156-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = zynquplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/debounce_switch.v
|
||||
SYN_FILES += rtl/common/mqnic_core_axi.v
|
||||
SYN_FILES += rtl/common/mqnic_core.v
|
||||
SYN_FILES += rtl/common/mqnic_interface.v
|
||||
SYN_FILES += rtl/common/mqnic_interface_tx.v
|
||||
SYN_FILES += rtl/common/mqnic_interface_rx.v
|
||||
SYN_FILES += rtl/common/mqnic_port.v
|
||||
SYN_FILES += rtl/common/mqnic_port_tx.v
|
||||
SYN_FILES += rtl/common/mqnic_port_rx.v
|
||||
SYN_FILES += rtl/common/mqnic_egress.v
|
||||
SYN_FILES += rtl/common/mqnic_ingress.v
|
||||
SYN_FILES += rtl/common/mqnic_l2_egress.v
|
||||
SYN_FILES += rtl/common/mqnic_l2_ingress.v
|
||||
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp_clock.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp_perout.v
|
||||
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
|
||||
SYN_FILES += rtl/common/cpl_write.v
|
||||
SYN_FILES += rtl/common/cpl_op_mux.v
|
||||
SYN_FILES += rtl/common/desc_fetch.v
|
||||
SYN_FILES += rtl/common/desc_op_mux.v
|
||||
SYN_FILES += rtl/common/event_mux.v
|
||||
SYN_FILES += rtl/common/queue_manager.v
|
||||
SYN_FILES += rtl/common/cpl_queue_manager.v
|
||||
SYN_FILES += rtl/common/tx_fifo.v
|
||||
SYN_FILES += rtl/common/rx_fifo.v
|
||||
SYN_FILES += rtl/common/tx_req_mux.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += rtl/common/rb_drp.v
|
||||
SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_wrapper.v
|
||||
SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_quad_wrapper.v
|
||||
SYN_FILES += rtl/common/stats_counter.v
|
||||
SYN_FILES += rtl/common/stats_collect.v
|
||||
SYN_FILES += rtl/common/stats_dma_if_axi.v
|
||||
SYN_FILES += rtl/common/stats_dma_latency.v
|
||||
SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
|
||||
SYN_FILES += rtl/common/tx_scheduler_rr.v
|
||||
SYN_FILES += rtl/common/tdma_scheduler.v
|
||||
SYN_FILES += rtl/common/tdma_ber.v
|
||||
SYN_FILES += rtl/common/tdma_ber_ch.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
|
||||
SYN_FILES += lib/eth/rtl/lfsr.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_perout.v
|
||||
SYN_FILES += lib/axi/rtl/axil_interconnect.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_register_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_register_wr.v
|
||||
SYN_FILES += lib/axi/rtl/arbiter.v
|
||||
SYN_FILES += lib/axi/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/axis/rtl/axis_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_demux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_register.v
|
||||
SYN_FILES += lib/axis/rtl/sync_reset.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_axi.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_axi_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_axi_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
|
||||
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = ip/zynq_ps.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_gth.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(FPGA_TOP).bit
|
||||
echo "open_hw" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
199
fpga/mqnic/ZCU102/fpga/fpga/config.tcl
Normal file
199
fpga/mqnic/ZCU102/fpga/fpga/config.tcl
Normal file
@ -0,0 +1,199 @@
|
||||
# Copyright 2021, The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
# OF SUCH DAMAGE.
|
||||
#
|
||||
# The views and conclusions contained in the software and documentation are those
|
||||
# of the authors and should not be interpreted as representing official policies,
|
||||
# either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
set params [dict create]
|
||||
|
||||
# collect build information
|
||||
set build_date [clock seconds]
|
||||
set git_hash 00000000
|
||||
set git_tag ""
|
||||
|
||||
if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
|
||||
puts "Error running git or project not under version control"
|
||||
}
|
||||
|
||||
if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
|
||||
puts "Error running git, project not under version control, or no tag found"
|
||||
}
|
||||
|
||||
puts "Build date: ${build_date}"
|
||||
puts "Git hash: ${git_hash}"
|
||||
puts "Git tag: ${git_tag}"
|
||||
|
||||
if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
|
||||
puts "Failed to extract version from git tag"
|
||||
set tag_ver 0.0.1
|
||||
}
|
||||
|
||||
puts "Tag version: ${tag_ver}"
|
||||
|
||||
# FW and board IDs
|
||||
set fpga_id [expr 0x4738093]
|
||||
set fw_id [expr 0x00000000]
|
||||
set fw_ver $tag_ver
|
||||
set board_vendor_id [expr 0x10ee]
|
||||
set board_device_id [expr 0x9066]
|
||||
set board_ver 1.0
|
||||
set release_info [expr 0x00000000]
|
||||
|
||||
# FW ID block
|
||||
dict set params FPGA_ID [format "32'h%08x" $fpga_id]
|
||||
dict set params FW_ID [format "32'h%08x" $fw_id]
|
||||
dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0]
|
||||
dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
|
||||
dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0]
|
||||
dict set params BUILD_DATE "32'd${build_date}"
|
||||
dict set params GIT_HASH "32'h${git_hash}"
|
||||
dict set params RELEASE_INFO [format "32'h%08x" $release_info]
|
||||
|
||||
# Board configuration
|
||||
dict set params TDMA_BER_ENABLE "0"
|
||||
|
||||
# Structural configuration
|
||||
dict set params IF_COUNT "2"
|
||||
dict set params PORTS_PER_IF "1"
|
||||
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
|
||||
dict set params PORT_MASK "0"
|
||||
|
||||
# PTP configuration
|
||||
dict set params PTP_CLOCK_PIPELINE "0"
|
||||
dict set params PTP_CLOCK_CDC_PIPELINE "0"
|
||||
dict set params PTP_PORT_CDC_PIPELINE "0"
|
||||
dict set params PTP_PEROUT_ENABLE "1"
|
||||
dict set params PTP_PEROUT_COUNT "1"
|
||||
|
||||
# Queue manager configuration
|
||||
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
|
||||
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
|
||||
dict set params EVENT_QUEUE_INDEX_WIDTH "2"
|
||||
dict set params TX_QUEUE_INDEX_WIDTH "5"
|
||||
dict set params RX_QUEUE_INDEX_WIDTH "5"
|
||||
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
|
||||
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
|
||||
dict set params EVENT_QUEUE_PIPELINE "3"
|
||||
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
|
||||
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
|
||||
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
|
||||
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
|
||||
dict set params TDMA_INDEX_WIDTH "6"
|
||||
|
||||
# Interface configuration
|
||||
dict set params PTP_TS_ENABLE "1"
|
||||
dict set params TX_CPL_FIFO_DEPTH "32"
|
||||
dict set params TX_CHECKSUM_ENABLE "1"
|
||||
dict set params RX_RSS_ENABLE "1"
|
||||
dict set params RX_HASH_ENABLE "1"
|
||||
dict set params RX_CHECKSUM_ENABLE "1"
|
||||
dict set params TX_FIFO_DEPTH "32768"
|
||||
dict set params RX_FIFO_DEPTH "32768"
|
||||
dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "32768"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
dict set params APP_ENABLE "0"
|
||||
dict set params APP_CTRL_ENABLE "1"
|
||||
dict set params APP_DMA_ENABLE "1"
|
||||
dict set params APP_AXIS_DIRECT_ENABLE "1"
|
||||
dict set params APP_AXIS_SYNC_ENABLE "1"
|
||||
dict set params APP_AXIS_IF_ENABLE "1"
|
||||
dict set params APP_STAT_ENABLE "1"
|
||||
|
||||
# AXI DMA interface configuration
|
||||
open_bd_design [get_files zynq_ps.bd]
|
||||
set s_axi_dma [get_bd_intf_ports s_axi_dma]
|
||||
dict set params AXI_DATA_WIDTH [get_property CONFIG.DATA_WIDTH $s_axi_dma]
|
||||
# dict set params AXI_ADDR_WIDTH [get_property CONFIG.ADDR_WIDTH $s_axi_dma]
|
||||
dict set params AXI_ADDR_WIDTH 64
|
||||
dict set params AXI_ID_WIDTH [get_property CONFIG.ID_WIDTH $s_axi_dma]
|
||||
|
||||
# DMA interface configuration
|
||||
dict set params DMA_IMM_ENABLE "0"
|
||||
dict set params DMA_IMM_WIDTH "32"
|
||||
dict set params DMA_LEN_WIDTH "16"
|
||||
dict set params DMA_TAG_WIDTH "16"
|
||||
dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
|
||||
dict set params RAM_PIPELINE "2"
|
||||
# NOTE: Querying the BD top-level interface port (or even the ZynqMP's interface
|
||||
# pin) yields 256 for the maximum burst length, instead of 16, which is
|
||||
# the actually supported length (due to ZynqMP using AXI3 internally).
|
||||
#dict set params AXI_DMA_MAX_BURST_LEN [get_property CONFIG.MAX_BURST_LENGTH $s_axi_dma]
|
||||
dict set params AXI_DMA_MAX_BURST_LEN "16"
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
set m_axil_ctrl [get_bd_intf_ports m_axil_ctrl]
|
||||
dict set params AXIL_CTRL_DATA_WIDTH [get_property CONFIG.DATA_WIDTH $m_axil_ctrl]
|
||||
dict set params AXIL_CTRL_ADDR_WIDTH 24
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
set m_axil_app_ctrl [get_bd_intf_ports m_axil_app_ctrl]
|
||||
dict set params AXIL_APP_CTRL_DATA_WIDTH [get_property CONFIG.DATA_WIDTH $m_axil_app_ctrl]
|
||||
dict set params AXIL_APP_CTRL_ADDR_WIDTH 24
|
||||
|
||||
# Interrupt configuration
|
||||
set irq [get_bd_ports pl_ps_irq0]
|
||||
dict set params IRQ_COUNT [get_property CONFIG.PortWidth $irq]
|
||||
close_bd_design [get_bd_designs zynq_ps]
|
||||
dict set params IRQ_STRETCH "10"
|
||||
|
||||
# Ethernet interface configuration
|
||||
dict set params AXIS_ETH_TX_PIPELINE "0"
|
||||
dict set params AXIS_ETH_TX_FIFO_PIPELINE "2"
|
||||
dict set params AXIS_ETH_TX_TS_PIPELINE "0"
|
||||
dict set params AXIS_ETH_RX_PIPELINE "0"
|
||||
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
|
||||
|
||||
# Statistics counter subsystem
|
||||
dict set params STAT_ENABLE "1"
|
||||
dict set params STAT_DMA_ENABLE "1"
|
||||
dict set params STAT_AXI_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# apply parameters to top-level
|
||||
set param_list {}
|
||||
dict for {name value} $params {
|
||||
lappend param_list $name=$value
|
||||
}
|
||||
|
||||
# set_property generic $param_list [current_fileset]
|
||||
set_property generic $param_list [get_filesets sources_1]
|
||||
129
fpga/mqnic/ZCU102/fpga/ip/eth_xcvr_gth.tcl
Normal file
129
fpga/mqnic/ZCU102/fpga/ip/eth_xcvr_gth.tcl
Normal file
@ -0,0 +1,129 @@
|
||||
# Copyright 2022, The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
# OF SUCH DAMAGE.
|
||||
#
|
||||
# The views and conclusions contained in the software and documentation are those
|
||||
# of the authors and should not be interpreted as representing official policies,
|
||||
# either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
set base_name {eth_xcvr_gth}
|
||||
|
||||
set preset {GTH-10GBASE-R}
|
||||
|
||||
set freerun_freq {125}
|
||||
set line_rate {10.3125}
|
||||
set sec_line_rate {0}
|
||||
set refclk_freq {156.25}
|
||||
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
|
||||
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
|
||||
set user_data_width {64}
|
||||
set int_data_width {32}
|
||||
set rx_eq_mode {DFE}
|
||||
set extra_ports [list]
|
||||
set extra_pll_ports [list]
|
||||
# DRP connections
|
||||
lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out
|
||||
lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out
|
||||
# PLL reset and power down
|
||||
lappend extra_pll_ports qpll0reset_in qpll1reset_in
|
||||
lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
# PLL clocking
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
|
||||
# channel power down
|
||||
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
|
||||
# channel clock selection
|
||||
lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
|
||||
# channel polarity
|
||||
lappend extra_ports txpolarity_in rxpolarity_in
|
||||
# channel TX driver
|
||||
lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
|
||||
# channel CDR
|
||||
lappend extra_ports rxcdrlock_out rxcdrhold_in
|
||||
# channel EQ
|
||||
lappend extra_ports rxlpmen_in
|
||||
# channel digital monitor
|
||||
lappend extra_ports dmonitorout_out
|
||||
# channel PRBS
|
||||
lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out
|
||||
# channel eye scan
|
||||
lappend extra_ports eyescandataerror_out
|
||||
# channel loopback
|
||||
lappend extra_ports loopback_in
|
||||
|
||||
set config [dict create]
|
||||
|
||||
dict set config TX_LINE_RATE $line_rate
|
||||
dict set config TX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config TX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config TX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_LINE_RATE $line_rate
|
||||
dict set config RX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config RX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config RX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_EQ_MODE $rx_eq_mode
|
||||
if {$sec_line_rate != 0} {
|
||||
dict set config SECONDARY_QPLL_ENABLE true
|
||||
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
|
||||
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
|
||||
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
|
||||
} else {
|
||||
dict set config SECONDARY_QPLL_ENABLE false
|
||||
}
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
|
||||
dict set config LOCATE_TX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_RX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
|
||||
dict set config FREERUN_FREQUENCY $freerun_freq
|
||||
dict set config DISABLE_LOC_XDC {1}
|
||||
|
||||
proc create_gtwizard_ip {name preset config} {
|
||||
create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
|
||||
set ip [get_ips $name]
|
||||
set_property CONFIG.preset $preset $ip
|
||||
set config_list {}
|
||||
dict for {name value} $config {
|
||||
lappend config_list "CONFIG.${name}" $value
|
||||
}
|
||||
set_property -dict $config_list $ip
|
||||
}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_channel" $preset $config
|
||||
215
fpga/mqnic/ZCU102/fpga/ip/zynq_ps.tcl
Normal file
215
fpga/mqnic/ZCU102/fpga/ip/zynq_ps.tcl
Normal file
@ -0,0 +1,215 @@
|
||||
# Copyright 2022, The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
# OF SUCH DAMAGE.
|
||||
#
|
||||
# The views and conclusions contained in the software and documentation are those
|
||||
# of the authors and should not be interpreted as representing official policies,
|
||||
# either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
# create block design
|
||||
create_bd_design "zynq_ps"
|
||||
|
||||
# Create blocks
|
||||
|
||||
# Zynq PS
|
||||
set zynq_ultra_ps [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e zynq_ultra_ps ]
|
||||
set_property -dict [list \
|
||||
CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
|
||||
CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
|
||||
CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
|
||||
CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \
|
||||
CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN 1 \
|
||||
CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \
|
||||
CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
|
||||
CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
|
||||
CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
|
||||
CONFIG.PSU__DDRC__T_RC {46.5} \
|
||||
CONFIG.PSU__DDRC__T_FAW {21.0} \
|
||||
CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
|
||||
CONFIG.PSU__DDRC__FREQ_MHZ {1067} \
|
||||
CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__PMU__GPI0__ENABLE {1} \
|
||||
CONFIG.PSU__PMU__GPI1__ENABLE {0} \
|
||||
CONFIG.PSU__PMU__GPI2__ENABLE {0} \
|
||||
CONFIG.PSU__PMU__GPI3__ENABLE {0} \
|
||||
CONFIG.PSU__PMU__GPI4__ENABLE {0} \
|
||||
CONFIG.PSU__PMU__GPI5__ENABLE {0} \
|
||||
CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \
|
||||
CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
|
||||
CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
|
||||
CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \
|
||||
CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
|
||||
CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
|
||||
CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
|
||||
CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
|
||||
CONFIG.PSU__SD1__GRP_WP__ENABLE {1} \
|
||||
CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
|
||||
CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
|
||||
CONFIG.PSU__USE__M_AXI_GP0 {1} \
|
||||
CONFIG.PSU__MAXIGP0__DATA_WIDTH {32} \
|
||||
CONFIG.PSU__USE__M_AXI_GP1 {0} \
|
||||
CONFIG.PSU__USE__M_AXI_GP2 {0} \
|
||||
CONFIG.PSU__USE__S_AXI_GP0 {1} \
|
||||
CONFIG.PSU__USE__IRQ0 {1} \
|
||||
CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
|
||||
CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
|
||||
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
|
||||
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
|
||||
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
|
||||
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {667} \
|
||||
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
|
||||
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {667} \
|
||||
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
|
||||
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {DPLL} \
|
||||
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
|
||||
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {DPLL} \
|
||||
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {DPLL} \
|
||||
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {DPLL} \
|
||||
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {DPLL} \
|
||||
CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {300} \
|
||||
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
|
||||
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
|
||||
] $zynq_ultra_ps
|
||||
|
||||
# control AXI interconnect
|
||||
set axi_interconnect_ctrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_interconnect_ctrl ]
|
||||
|
||||
# reset
|
||||
set proc_sys_reset [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset proc_sys_reset ]
|
||||
|
||||
# Create connections
|
||||
|
||||
# Clock
|
||||
set pl_clk0 [get_bd_pins $zynq_ultra_ps/pl_clk0]
|
||||
make_bd_pins_external $pl_clk0
|
||||
set_property name pl_clk0 [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_clk0]]
|
||||
set pl_clk0_port [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_clk0]]
|
||||
|
||||
connect_bd_net $pl_clk0 [get_bd_pins $zynq_ultra_ps/maxihpm0_fpd_aclk]
|
||||
connect_bd_net $pl_clk0 [get_bd_pins $zynq_ultra_ps/saxihpc0_fpd_aclk]
|
||||
connect_bd_net $pl_clk0 [get_bd_pins $proc_sys_reset/slowest_sync_clk]
|
||||
connect_bd_net $pl_clk0 [get_bd_pins $axi_interconnect_ctrl/ACLK]
|
||||
connect_bd_net $pl_clk0 [get_bd_pins $axi_interconnect_ctrl/S00_ACLK]
|
||||
connect_bd_net $pl_clk0 [get_bd_pins $axi_interconnect_ctrl/M00_ACLK]
|
||||
connect_bd_net $pl_clk0 [get_bd_pins $axi_interconnect_ctrl/M01_ACLK]
|
||||
|
||||
set pl_clk0_busif [list]
|
||||
|
||||
# Reset
|
||||
set pl_resetn0 [get_bd_pins $zynq_ultra_ps/pl_resetn0]
|
||||
connect_bd_net $pl_resetn0 [get_bd_pins $proc_sys_reset/ext_reset_in]
|
||||
|
||||
set pl_reset [get_bd_pins $proc_sys_reset/peripheral_reset]
|
||||
make_bd_pins_external $pl_reset
|
||||
set_property name pl_reset [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_reset]]
|
||||
|
||||
set interconnect_aresetn [get_bd_pins $proc_sys_reset/interconnect_aresetn]
|
||||
connect_bd_net $interconnect_aresetn [get_bd_pins $axi_interconnect_ctrl/ARESETN]
|
||||
connect_bd_net $interconnect_aresetn [get_bd_pins $axi_interconnect_ctrl/S00_ARESETN]
|
||||
connect_bd_net $interconnect_aresetn [get_bd_pins $axi_interconnect_ctrl/M00_ARESETN]
|
||||
connect_bd_net $interconnect_aresetn [get_bd_pins $axi_interconnect_ctrl/M01_ARESETN]
|
||||
|
||||
# MMIO
|
||||
connect_bd_intf_net [get_bd_intf_pins $zynq_ultra_ps/M_AXI_HPM0_FPD] [get_bd_intf_pins $axi_interconnect_ctrl/S00_AXI]
|
||||
|
||||
# Control interface
|
||||
set m_axil_ctrl_pin [get_bd_intf_pins $axi_interconnect_ctrl/M00_AXI]
|
||||
make_bd_intf_pins_external $m_axil_ctrl_pin
|
||||
set_property name m_axil_ctrl [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $m_axil_ctrl_pin]]
|
||||
set m_axil_ctrl_port [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $m_axil_ctrl_pin]]
|
||||
set_property -dict [list \
|
||||
CONFIG.PROTOCOL AXI4LITE \
|
||||
CONFIG.DATA_WIDTH 32 \
|
||||
CONFIG.ADDR_WIDTH 24 \
|
||||
] $m_axil_ctrl_port
|
||||
lappend pl_clk0_busif $m_axil_ctrl_port
|
||||
|
||||
# Application control interface
|
||||
set m_axil_app_ctrl_pin [get_bd_intf_pins $axi_interconnect_ctrl/M01_AXI]
|
||||
make_bd_intf_pins_external $m_axil_app_ctrl_pin
|
||||
set_property name m_axil_app_ctrl [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $m_axil_app_ctrl_pin]]
|
||||
set m_axil_app_ctrl_port [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $m_axil_app_ctrl_pin]]
|
||||
set_property -dict [list \
|
||||
CONFIG.PROTOCOL AXI4LITE \
|
||||
CONFIG.DATA_WIDTH 32 \
|
||||
CONFIG.ADDR_WIDTH 24 \
|
||||
] $m_axil_app_ctrl_port
|
||||
lappend pl_clk0_busif $m_axil_app_ctrl_port
|
||||
|
||||
# DMA interface
|
||||
set s_axi_dma_pin [get_bd_intf_pins $zynq_ultra_ps/S_AXI_HPC0_FPD]
|
||||
make_bd_intf_pins_external $s_axi_dma_pin
|
||||
set_property name s_axi_dma [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $s_axi_dma_pin]]
|
||||
set s_axi_dma_port [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $s_axi_dma_pin]]
|
||||
lappend pl_clk0_busif $s_axi_dma_port
|
||||
|
||||
# IRQ
|
||||
set pl_ps_irq0 [get_bd_pins $zynq_ultra_ps/pl_ps_irq0]
|
||||
make_bd_pins_external $pl_ps_irq0
|
||||
set_property name pl_ps_irq0 [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_ps_irq0]]
|
||||
set pl_ps_irq0_port [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_ps_irq0]]
|
||||
set_property -dict [list \
|
||||
CONFIG.PortWidth 8 \
|
||||
] $pl_ps_irq0_port
|
||||
|
||||
# Port clock associations
|
||||
set lst [list]
|
||||
foreach port $pl_clk0_busif {
|
||||
lappend lst [get_property name $port]
|
||||
}
|
||||
set_property CONFIG.ASSOCIATED_BUSIF [join $lst ":"] $pl_clk0_port
|
||||
|
||||
# Assign addresses
|
||||
assign_bd_address -target_address_space /s_axi_dma [get_bd_addr_segs $zynq_ultra_ps/SAXIGP0/HPC0_DDR_HIGH] -force
|
||||
assign_bd_address -target_address_space /s_axi_dma [get_bd_addr_segs $zynq_ultra_ps/SAXIGP0/HPC0_QSPI] -force
|
||||
assign_bd_address -target_address_space /s_axi_dma [get_bd_addr_segs $zynq_ultra_ps/SAXIGP0/HPC0_DDR_LOW] -force
|
||||
assign_bd_address -target_address_space /s_axi_dma [get_bd_addr_segs $zynq_ultra_ps/SAXIGP0/HPC0_LPS_OCM] -force
|
||||
|
||||
assign_bd_address -offset 0xA000_0000 -range 16M -target_address_space $zynq_ultra_ps/Data [get_bd_addr_segs $m_axil_ctrl_port/Reg] -force
|
||||
assign_bd_address -offset 0xA800_0000 -range 16M -target_address_space $zynq_ultra_ps/Data [get_bd_addr_segs $m_axil_app_ctrl_port/Reg] -force
|
||||
|
||||
validate_bd_design
|
||||
|
||||
# Save block design
|
||||
save_bd_design [current_bd_design]
|
||||
close_bd_design [current_bd_design]
|
||||
1
fpga/mqnic/ZCU102/fpga/lib
Symbolic link
1
fpga/mqnic/ZCU102/fpga/lib
Symbolic link
@ -0,0 +1 @@
|
||||
../../../lib/
|
||||
25
fpga/mqnic/ZCU102/fpga/ps/petalinux/.gitignore
vendored
Normal file
25
fpga/mqnic/ZCU102/fpga/ps/petalinux/.gitignore
vendored
Normal file
@ -0,0 +1,25 @@
|
||||
*/*/config.old
|
||||
*/*/rootfs_config.old
|
||||
build/
|
||||
images/linux/
|
||||
pre-built/linux/
|
||||
.petalinux/*
|
||||
# NOTE: At least since v2020.2 .petalinux/metadata may contain an absolute path
|
||||
# of the last imported .xsa file! Plus various MD5 sums. Not good for VCS!
|
||||
# Apparently, the file is NOT needed anymore (re-created on each build instead).
|
||||
# However the directory .petalinux/ has to exists.
|
||||
#!.petalinux/metadata
|
||||
!.petalinux/.gitkeep
|
||||
*.o
|
||||
*.jou
|
||||
*.log
|
||||
/components/plnx_workspace
|
||||
/components/yocto
|
||||
|
||||
|
||||
# skip any generated .xsa-related files
|
||||
/project-spec/hw-description/*
|
||||
!/project-spec/hw-description/metadata
|
||||
|
||||
# Xilinx toolchain intermediate files
|
||||
/.Xil/
|
||||
1
fpga/mqnic/ZCU102/fpga/ps/petalinux/Makefile
Symbolic link
1
fpga/mqnic/ZCU102/fpga/ps/petalinux/Makefile
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../../lib/psmake/petalinux.mk
|
||||
11
fpga/mqnic/ZCU102/fpga/ps/petalinux/config.project
Normal file
11
fpga/mqnic/ZCU102/fpga/ps/petalinux/config.project
Normal file
@ -0,0 +1,11 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# PetaLinux SDK Project Configuration
|
||||
#
|
||||
CONFIG_PROJECT_ADDITIONAL_COMPONENTS_SEARCH_PATH=""
|
||||
|
||||
#
|
||||
# Subsystems of the project
|
||||
#
|
||||
CONFIG_PROJECT_SUBSYSTEM_LINUX_INSTANCE_LINUX=y
|
||||
CONFIG_PROJECT_SUBSYSTEMS=y
|
||||
8
fpga/mqnic/ZCU102/fpga/ps/petalinux/local.mk
Normal file
8
fpga/mqnic/ZCU102/fpga/ps/petalinux/local.mk
Normal file
@ -0,0 +1,8 @@
|
||||
HDF ?= ../../fpga/fpga.xsa
|
||||
|
||||
# shortcut to build PetaLinux project including boot files
|
||||
build-boot:
|
||||
$(MAKE) build
|
||||
$(MAKE) package-boot
|
||||
|
||||
.PHONY: build-boot
|
||||
10
fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/attributes
Normal file
10
fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/attributes
Normal file
@ -0,0 +1,10 @@
|
||||
#Virtual Providers
|
||||
|
||||
|
||||
|
||||
#defconfigs
|
||||
|
||||
UBOOT_DEFAULT_DEFCONFIG="xilinx_zynqmp_virt_defconfig"
|
||||
|
||||
#atf
|
||||
CONFIG_SUBSYSTEM_PRELOADED_BL33_BASE="0x8000000"
|
||||
@ -0,0 +1,22 @@
|
||||
#/etc/inetd.conf: see inetd(8) for further informations.
|
||||
#
|
||||
# Internet server configuration database
|
||||
#
|
||||
# If you want to disable an entry so it isn't touched during
|
||||
# package updates just comment it out with a single '#' character.
|
||||
#
|
||||
# <service_name> <sock_type> <proto> <flags> <user> <server_path> <args>
|
||||
#
|
||||
#:INTERNAL: Internal services
|
||||
#echo stream tcp nowait root internal
|
||||
#echo dgram udp wait root internal
|
||||
#chargen stream tcp nowait root internal
|
||||
#chargen dgram udp wait root internal
|
||||
#discard stream tcp nowait root internal
|
||||
#discard dgram udp wait root internal
|
||||
#daytime stream tcp nowait root internal
|
||||
#daytime dgram udp wait root internal
|
||||
#time stream tcp nowait root internal
|
||||
#time dgram udp wait root internal
|
||||
telnet stream tcp nowait root telnetd telnetd -i
|
||||
ftp stream tcp nowait root ftpd ftpd -w
|
||||
301
fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/configs/config
Normal file
301
fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/configs/config
Normal file
@ -0,0 +1,301 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# misc/config System Configuration
|
||||
#
|
||||
CONFIG_SUBSYSTEM_TYPE_LINUX=y
|
||||
CONFIG_SYSTEM_ZYNQMP=y
|
||||
CONFIG_SUBSYSTEM_VARIANT_ZYNQMPEG=y
|
||||
|
||||
#
|
||||
# Linux Components Selection
|
||||
#
|
||||
CONFIG_SUBSYSTEM_COMPONENT_DEVICE__TREE_NAME_DEVICE__TREE__GENERATOR=y
|
||||
# CONFIG_SUBSYSTEM_COMPONENT_IMG_SEL is not set
|
||||
CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_FSBL=y
|
||||
CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_NAME_ZYNQMP_FSBL=y
|
||||
CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_PS_INIT=y
|
||||
CONFIG_SUBSYSTEM_COMPONENT_PMU_FIRMWARE=y
|
||||
CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_U__BOOT__XLNX=y
|
||||
# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_REMOTE is not set
|
||||
# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_EXT__LOCAL__SRC is not set
|
||||
CONFIG_SUBSYSTEM_COMPONENT_ARM__TRUSTED__FIRMWARE_NAME_ARM__TRUSTED__FIRMWARE=y
|
||||
# CONFIG_SUBSYSTEM_COMPONENT_ARM__TRUSTED__FIRMWARE_NAME_REMOTE is not set
|
||||
# CONFIG_SUBSYSTEM_COMPONENT_ARM__TRUSTED__FIRMWARE_NAME_EXT__LOCAL__SRC is not set
|
||||
CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_LINUX__XLNX=y
|
||||
# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_REMOTE is not set
|
||||
# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_EXT__LOCAL__SRC is not set
|
||||
|
||||
#
|
||||
# Auto Config Settings
|
||||
#
|
||||
CONFIG_SUBSYSTEM_AUTOCONFIG_DEVICE__TREE=y
|
||||
# CONFIG_SUBSYSTEM_DEVICE_TREE_MANUAL_INCLUDE is not set
|
||||
CONFIG_SUBSYSTEM_HARDWARE_AUTO=y
|
||||
CONFIG_SUBSYSTEM_PROCESSOR0_IP_NAME="psu_cortexa53_0"
|
||||
CONFIG_SUBSYSTEM_PROCESSOR_psu_cortexa53_0_SELECT=y
|
||||
CONFIG_SUBSYSTEM_ARCH_AARCH64=y
|
||||
|
||||
#
|
||||
# Memory Settings
|
||||
#
|
||||
CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_SELECT=y
|
||||
# CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_1_BANKLESS_SELECT is not set
|
||||
# CONFIG_SUBSYSTEM_MEMORY_MANUAL_SELECT is not set
|
||||
CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_BASEADDR=0x0
|
||||
CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_SIZE=0x80000000
|
||||
CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_KERNEL_BASEADDR=0x0
|
||||
CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_U__BOOT_TEXTBASE_OFFSET=0x100000
|
||||
CONFIG_SUBSYSTEM_MEMORY_IP_NAME="PSU_DDR_0"
|
||||
|
||||
#
|
||||
# Serial Settings
|
||||
#
|
||||
# CONFIG_SUBSYSTEM_PMUFW_SERIAL_PSU_UART_1_SELECT is not set
|
||||
CONFIG_SUBSYSTEM_PMUFW_SERIAL_PSU_UART_0_SELECT=y
|
||||
# CONFIG_SUBSYSTEM_PMUFW_SERIAL_MANUAL_SELECT is not set
|
||||
# CONFIG_SUBSYSTEM_FSBL_SERIAL_PSU_UART_1_SELECT is not set
|
||||
CONFIG_SUBSYSTEM_FSBL_SERIAL_PSU_UART_0_SELECT=y
|
||||
# CONFIG_SUBSYSTEM_FSBL_SERIAL_MANUAL_SELECT is not set
|
||||
# CONFIG_SUBSYSTEM_ATF_SERIAL_PSU_UART_1_SELECT is not set
|
||||
CONFIG_SUBSYSTEM_ATF_SERIAL_PSU_UART_0_SELECT=y
|
||||
# CONFIG_SUBSYSTEM_ATF_SERIAL_MANUAL_SELECT is not set
|
||||
# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_SELECT is not set
|
||||
CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_SELECT=y
|
||||
# CONFIG_SUBSYSTEM_SERIAL_MANUAL_SELECT is not set
|
||||
# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_600 is not set
|
||||
# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_9600 is not set
|
||||
# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_28800 is not set
|
||||
CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_115200=y
|
||||
# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_230400 is not set
|
||||
# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_460800 is not set
|
||||
# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_921600 is not set
|
||||
# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_600 is not set
|
||||
# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_9600 is not set
|
||||
# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_28800 is not set
|
||||
CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_115200=y
|
||||
# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_230400 is not set
|
||||
# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_460800 is not set
|
||||
# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_921600 is not set
|
||||
CONFIG_SUBSYSTEM_SERIAL_PMUFW_IP_NAME="psu_uart_0"
|
||||
CONFIG_SUBSYSTEM_SERIAL_FSBL_IP_NAME="psu_uart_0"
|
||||
CONFIG_SUBSYSTEM_SERIAL_ATF_IP_NAME="cadence"
|
||||
CONFIG_SUBSYSTEM_SERIAL_IP_NAME="psu_uart_0"
|
||||
|
||||
#
|
||||
# Ethernet Settings
|
||||
#
|
||||
CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_SELECT=y
|
||||
# CONFIG_SUBSYSTEM_ETHERNET_MANUAL_SELECT is not set
|
||||
# CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC_AUTO is not set
|
||||
CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC="ff:ff:ff:ff:ff:ff"
|
||||
CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_USE_DHCP=y
|
||||
|
||||
#
|
||||
# Flash Settings
|
||||
#
|
||||
CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_SELECT=y
|
||||
# CONFIG_SUBSYSTEM_FLASH_MANUAL_SELECT is not set
|
||||
# CONFIG_SUBSYSTEM_FLASH__ADVANCED_AUTOCONFIG is not set
|
||||
|
||||
#
|
||||
# partition 0
|
||||
#
|
||||
CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_NAME="boot"
|
||||
CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0x100000
|
||||
|
||||
#
|
||||
# partition 1
|
||||
#
|
||||
CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_NAME="bootenv"
|
||||
CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x40000
|
||||
|
||||
#
|
||||
# partition 2
|
||||
#
|
||||
CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_NAME="kernel"
|
||||
CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x1600000
|
||||
|
||||
#
|
||||
# partition 3
|
||||
#
|
||||
CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME=""
|
||||
CONFIG_SUBSYSTEM_FLASH_IP_NAME="psu_qspi_0"
|
||||
|
||||
#
|
||||
# SD/SDIO Settings
|
||||
#
|
||||
CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
|
||||
# CONFIG_SUBSYSTEM_PRIMARY_SD_MANUAL_SELECT is not set
|
||||
CONFIG_SUBSYSTEM_SD_PSU_SD_1_SELECT=y
|
||||
|
||||
#
|
||||
# RTC Settings
|
||||
#
|
||||
CONFIG_SUBSYSTEM_RTC_PSU_RTC_SELECT=y
|
||||
# CONFIG_SUBSYSTEM_RTC_MANUAL_SELECT is not set
|
||||
CONFIG_SUBSYSTEM_I2C_PSU_I2C_1_SELECT=y
|
||||
CONFIG_SUBSYSTEM_I2C_PSU_I2C_0_SELECT=y
|
||||
CONFIG_SUBSYSTEM_ENDIAN_LITTLE=y
|
||||
|
||||
#
|
||||
# DTG Settings
|
||||
#
|
||||
CONFIG_SUBSYSTEM_MACHINE_NAME="zcu102-rev1.0"
|
||||
CONFIG_SUBSYSTEM_EXTRA_DT_FILES=""
|
||||
|
||||
#
|
||||
# Kernel Bootargs
|
||||
#
|
||||
CONFIG_SUBSYSTEM_BOOTARGS_AUTO=y
|
||||
CONFIG_SUBSYSTEM_BOOTARGS_EARLYPRINTK=y
|
||||
CONFIG_SUBSYSTEM_BOOTARGS_GENERATED=" earlycon console=ttyPS0,115200 clk_ignore_unused init_fatal_sh=1"
|
||||
CONFIG_SUBSYSTEM_DEVICETREE_COMPILER_FLAGS="-@"
|
||||
# CONFIG_SUBSYSTEM_DTB_OVERLAY is not set
|
||||
# CONFIG_SUBSYSTEM_REMOVE_PL_DTB is not set
|
||||
# CONFIG_SUBSYSTEM_ENABLE_NO_ALIAS is not set
|
||||
|
||||
#
|
||||
# PMUFW Configuration
|
||||
#
|
||||
CONFIG_SUBSYSTEM_PMUFW_COMPILER_EXTRA_FLAGS=""
|
||||
|
||||
#
|
||||
# FSBL Configuration
|
||||
#
|
||||
CONFIG_SUBSYSTEM_FSBL_BSPCOMPILER_FLAGS=""
|
||||
CONFIG_SUBSYSTEM_FSBL_COMPILER_EXTRA_FLAGS=""
|
||||
|
||||
#
|
||||
# ARM Trusted Firmware Configuration
|
||||
#
|
||||
# CONFIG_SUBSYSTEM_ATF_MEMORY_SETTINGS is not set
|
||||
CONFIG_SUBSYSTEM_ATF_EXTRA_COMPILER_FLAGS=""
|
||||
CONFIG_SUBSYSTEM_PRELOADED_BL33_BASE=0x8000000
|
||||
# CONFIG_SUBSYSTEM_ATF_DEBUG is not set
|
||||
|
||||
#
|
||||
# FPGA Manager
|
||||
#
|
||||
# CONFIG_SUBSYSTEM_FPGA_MANAGER is not set
|
||||
|
||||
#
|
||||
# u-boot Configuration
|
||||
#
|
||||
CONFIG_SUBSYSTEM_UBOOT_CONFIG_TARGET="xilinx_zynqmp_virt_defconfig"
|
||||
|
||||
#
|
||||
# u-boot script configuration
|
||||
#
|
||||
CONFIG_SUBSYSTEM_UBOOT_APPEND_BASEADDR=y
|
||||
CONFIG_SUBSYSTEM_UBOOT_PRE_BOOTENV=""
|
||||
|
||||
#
|
||||
# JTAG/DDR image offsets
|
||||
#
|
||||
CONFIG_SUBSYSTEM_UBOOT_DEVICETREE_OFFSET=0x100000
|
||||
CONFIG_SUBSYSTEM_UBOOT_KERNEL_OFFSET=0x200000
|
||||
CONFIG_SUBSYSTEM_UBOOT_RAMDISK_IMAGE_OFFSET=0x4000000
|
||||
CONFIG_SUBSYSTEM_UBOOT_FIT_IMAGE_OFFSET=0x10000000
|
||||
|
||||
#
|
||||
# QSPI/OSPI image offsets
|
||||
#
|
||||
CONFIG_SUBSYSTEM_UBOOT_QSPI_KERNEL_OFFSET=0xF00000
|
||||
CONFIG_SUBSYSTEM_UBOOT_QSPI_KERNEL_SIZE=0x1D00000
|
||||
CONFIG_SUBSYSTEM_UBOOT_QSPI_RAMDISK_OFFSET=0x4000000
|
||||
CONFIG_SUBSYSTEM_UBOOT_QSPI_RAMDISK_SIZE=0x4000000
|
||||
CONFIG_SUBSYSTEM_UBOOT_QSPI_FIT_IMAGE_OFFSET=0xF40000
|
||||
CONFIG_SUBSYSTEM_UBOOT_QSPI_FIT_IMAGE_SIZE=0x6400000
|
||||
|
||||
#
|
||||
# NAND image offsets
|
||||
#
|
||||
CONFIG_SUBSYSTEM_UBOOT_NAND_KERNEL_OFFSET=0x4100000
|
||||
CONFIG_SUBSYSTEM_UBOOT_NAND_KERNEL_SIZE=0x3200000
|
||||
CONFIG_SUBSYSTEM_UBOOT_NAND_RAMDISK_OFFSET=0x7800000
|
||||
CONFIG_SUBSYSTEM_UBOOT_NAND_RAMDISK_SIZE=0x3200000
|
||||
CONFIG_SUBSYSTEM_UBOOT_NAND_FIT_IMAGE_OFFSET=0x4180000
|
||||
CONFIG_SUBSYSTEM_UBOOT_NAND_FIT_IMAGE_SIZE=0x6400000
|
||||
CONFIG_SUBSYSTEM_UBOOT_KERNEL_IMAGE="Image"
|
||||
CONFIG_SUBSYSTEM_UBOOT_FIT_IMAGE="image.ub"
|
||||
# CONFIG_SUBSYSTEM_UBOOT_EXT_DTB is not set
|
||||
|
||||
#
|
||||
# Linux Configuration
|
||||
#
|
||||
CONFIG_SUBSYSTEM_LINUX_CONFIG_TARGET=""
|
||||
|
||||
#
|
||||
# Image Packaging Configuration
|
||||
#
|
||||
# CONFIG_SUBSYSTEM_ROOTFS_INITRAMFS is not set
|
||||
CONFIG_SUBSYSTEM_ROOTFS_INITRD=y
|
||||
# CONFIG_SUBSYSTEM_ROOTFS_JFFS2 is not set
|
||||
# CONFIG_SUBSYSTEM_ROOTFS_UBIFS is not set
|
||||
# CONFIG_SUBSYSTEM_ROOTFS_NFS is not set
|
||||
# CONFIG_SUBSYSTEM_ROOTFS_EXT4 is not set
|
||||
# CONFIG_SUBSYSTEM_ROOTFS_OTHER is not set
|
||||
CONFIG_SUBSYSTEM_INITRD_RAMDISK_LOADADDR=0x0
|
||||
CONFIG_SUBSYSTEM_INITRAMFS_IMAGE_NAME="petalinux-initramfs-image"
|
||||
CONFIG_SUBSYSTEM_UIMAGE_NAME="image.ub"
|
||||
CONFIG_SUBSYSTEM_RFS_FORMATS="cpio cpio.gz cpio.gz.u-boot ext4 tar.gz jffs2"
|
||||
CONFIG_SUBSYSTEM_DTB_PADDING_SIZE=0x1000
|
||||
# CONFIG_SUBSYSTEM_COPY_TO_TFTPBOOT is not set
|
||||
|
||||
#
|
||||
# Firmware Version Configuration
|
||||
#
|
||||
CONFIG_SUBSYSTEM_HOSTNAME="petalinux"
|
||||
CONFIG_SUBSYSTEM_PRODUCT="petalinux"
|
||||
CONFIG_SUBSYSTEM_FW_VERSION="1.00"
|
||||
|
||||
#
|
||||
# Yocto Settings
|
||||
#
|
||||
CONFIG_YOCTO_MACHINE_NAME="zynqmp-generic"
|
||||
|
||||
#
|
||||
# Yocto board settings
|
||||
#
|
||||
CONFIG_YOCTO_BOARD_NAME=""
|
||||
CONFIG_YOCTO_BOARD_VARIANT_NAME=""
|
||||
|
||||
#
|
||||
# TMPDIR Location
|
||||
#
|
||||
CONFIG_TMP_DIR_LOCATION="${PROOT}/build/tmp"
|
||||
|
||||
#
|
||||
# Devtool Workspace Location
|
||||
#
|
||||
CONFIG_DEVTOOL_WORKSPACE_LOCATION="${PROOT}/components/yocto/workspace"
|
||||
|
||||
#
|
||||
# Parallel thread execution
|
||||
#
|
||||
CONFIG_YOCTO_BB_NUMBER_THREADS=""
|
||||
CONFIG_YOCTO_PARALLEL_MAKE=""
|
||||
|
||||
#
|
||||
# Add pre-mirror url
|
||||
#
|
||||
CONFIG_PRE_MIRROR_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_VER%%.*}/downloads"
|
||||
|
||||
#
|
||||
# Local sstate feeds settings
|
||||
#
|
||||
CONFIG_YOCTO_LOCAL_SSTATE_FEEDS_URL=""
|
||||
CONFIG_YOCTO_NETWORK_SSTATE_FEEDS=y
|
||||
|
||||
#
|
||||
# Network sstate feeds URL
|
||||
#
|
||||
CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_VER%%.*}/aarch64/sstate-cache"
|
||||
# CONFIG_YOCTO_BB_NO_NETWORK is not set
|
||||
# CONFIG_YOCTO_BUILDTOOLS_EXTENDED is not set
|
||||
|
||||
#
|
||||
# User Layers
|
||||
#
|
||||
CONFIG_USER_LAYER_0="${PROOT}/../../../../../../meta-corundum"
|
||||
CONFIG_USER_LAYER_1=""
|
||||
@ -0,0 +1,31 @@
|
||||
# /etc/network/interfaces -- configuration file for ifup(8), ifdown(8)
|
||||
|
||||
# The loopback interface
|
||||
auto lo
|
||||
iface lo inet loopback
|
||||
|
||||
# Wireless interfaces
|
||||
iface wlan0 inet dhcp
|
||||
wireless_mode managed
|
||||
wireless_essid any
|
||||
wpa-driver wext
|
||||
wpa-conf /etc/wpa_supplicant.conf
|
||||
|
||||
iface atml0 inet dhcp
|
||||
|
||||
# Wired or wireless interfaces
|
||||
auto eth0
|
||||
iface eth0 inet dhcp
|
||||
iface eth1 inet dhcp
|
||||
|
||||
# Ethernet/RNDIS gadget (g_ether)
|
||||
# ... or on host side, usbnet and random hwaddr
|
||||
iface usb0 inet static
|
||||
address 192.168.7.2
|
||||
netmask 255.255.255.0
|
||||
network 192.168.7.0
|
||||
gateway 192.168.7.1
|
||||
|
||||
# Bluetooth networking
|
||||
iface bnep0 inet dhcp
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,17 @@
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
@ -0,0 +1,64 @@
|
||||
This README file contains information on the contents of the
|
||||
meta-user layer.
|
||||
|
||||
Please see the corresponding sections below for details.
|
||||
|
||||
|
||||
Dependencies
|
||||
============
|
||||
|
||||
This layer depends on:
|
||||
|
||||
URI: git://git.openembedded.org/bitbake
|
||||
branch: master
|
||||
|
||||
URI: git://git.openembedded.org/openembedded-core
|
||||
layers: meta
|
||||
branch: master
|
||||
|
||||
URI: git://git.yoctoproject.org/xxxx
|
||||
layers: xxxx
|
||||
branch: master
|
||||
|
||||
|
||||
Patches
|
||||
=======
|
||||
|
||||
Please submit any patches against the meta-user layer to the
|
||||
xxxx mailing list (xxxx@zzzz.org) and cc: the maintainer:
|
||||
|
||||
Maintainer: XXX YYYYYY <xxx.yyyyyy@zzzzz.com>
|
||||
|
||||
|
||||
Table of Contents
|
||||
=================
|
||||
|
||||
I. Adding the meta-user layer to your build
|
||||
II. Misc
|
||||
|
||||
|
||||
I. Adding the meta-user layer to your build
|
||||
=================================================
|
||||
|
||||
--- replace with specific instructions for the meta-user layer ---
|
||||
|
||||
In order to use this layer, you need to make the build system aware of
|
||||
it.
|
||||
|
||||
Assuming the meta-user layer exists at the top-level of your
|
||||
yocto build tree, you can add it to the build system by adding the
|
||||
location of the meta-user layer to bblayers.conf, along with any
|
||||
other layers needed. e.g.:
|
||||
|
||||
BBLAYERS ?= " \
|
||||
/path/to/yocto/meta \
|
||||
/path/to/yocto/meta-poky \
|
||||
/path/to/yocto/meta-yocto-bsp \
|
||||
/path/to/yocto/meta-meta-user \
|
||||
"
|
||||
|
||||
|
||||
II. Misc
|
||||
========
|
||||
|
||||
--- replace with specific information about the meta-user layer ---
|
||||
@ -0,0 +1,11 @@
|
||||
# We have a conf and classes directory, add to BBPATH
|
||||
BBPATH .= ":${LAYERDIR}"
|
||||
|
||||
# We have recipes-* directories, add to BBFILES
|
||||
BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \
|
||||
${LAYERDIR}/recipes-*/*/*.bbappend"
|
||||
|
||||
BBFILE_COLLECTIONS += "meta-user"
|
||||
BBFILE_PATTERN_meta-user = "^${LAYERDIR}/"
|
||||
BBFILE_PRIORITY_meta-user = "7"
|
||||
LAYERSERIES_COMPAT_meta-user = "gatesgarth"
|
||||
@ -0,0 +1,4 @@
|
||||
#User Configuration
|
||||
|
||||
#OE_TERMINAL = "tmux"
|
||||
|
||||
@ -0,0 +1,12 @@
|
||||
#Note: Mention Each package in individual line
|
||||
#These packages will get added into rootfs menu entry
|
||||
|
||||
CONFIG_gpio-demo
|
||||
CONFIG_peekpoke
|
||||
|
||||
CONFIG_iputils-ping
|
||||
CONFIG_iperf2
|
||||
CONFIG_linuxptp
|
||||
|
||||
CONFIG_kernel-module-mqnic
|
||||
CONFIG_mqnic-tools
|
||||
@ -0,0 +1,14 @@
|
||||
APP = gpio-demo
|
||||
|
||||
# Add any other object files to this list below
|
||||
APP_OBJS = gpio-demo.o
|
||||
|
||||
all: $(APP)
|
||||
|
||||
$(APP): $(APP_OBJS)
|
||||
$(CC) $(LDFLAGS) -o $@ $(APP_OBJS) $(LDLIBS)
|
||||
|
||||
clean:
|
||||
-rm -f $(APP) *.elf *.gdb *.o
|
||||
|
||||
|
||||
@ -0,0 +1,355 @@
|
||||
/*
|
||||
*
|
||||
* gpio-demo app
|
||||
*
|
||||
* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without restriction,
|
||||
* including without limitation the rights to use, copy, modify, merge,
|
||||
* publish, distribute, sublicense, and/or sell copies of the Software,
|
||||
* and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in this
|
||||
* Software without prior written authorization from Xilinx.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <unistd.h>
|
||||
#include <string.h>
|
||||
#include <errno.h>
|
||||
#include <fcntl.h>
|
||||
#include <signal.h>
|
||||
|
||||
#define GPIO_ROOT "/sys/class/gpio"
|
||||
#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0]))
|
||||
|
||||
static enum {NONE, IN, OUT, CYLON, KIT} gpio_opt = NONE;
|
||||
|
||||
static const unsigned long cylon[] = {
|
||||
0x00000080, 0x00000040, 0x00000020, 0x00000010,
|
||||
0x00000008, 0x00000004, 0x00000002, 0x00000001,
|
||||
0x00000002, 0x00000004, 0x00000008,
|
||||
0x00000010, 0x00000020, 0x00000040, 0x00000080,
|
||||
};
|
||||
|
||||
static const unsigned long kit[] = {
|
||||
0x000000e0, 0x00000070, 0x00000038, 0x0000001c,
|
||||
0x0000000e, 0x00000007, 0x00000003, 0x00000001,
|
||||
0x00000003, 0x00000007, 0x0000000e,
|
||||
0x0000001c, 0x00000038, 0x00000070, 0x000000e0,
|
||||
};
|
||||
|
||||
static int gl_gpio_base = 0;
|
||||
|
||||
static void usage (char *argv0)
|
||||
{
|
||||
char *basename = strrchr(argv0, '/');
|
||||
if (!basename)
|
||||
basename = argv0;
|
||||
|
||||
fprintf(stderr,
|
||||
"Usage: %s [-g GPIO_BASE] COMMAND\n"
|
||||
"\twhere COMMAND is one of:\n"
|
||||
"\t\t-i\t\tInput value from GPIO and print it\n"
|
||||
"\t\t-o\tVALUE\tOutput value to GPIO\n"
|
||||
"\t\t-c\t\tCylon test pattern\n"
|
||||
"\t\t-k\t\t KIT test pattern\n"
|
||||
"\tGPIO_BASE indicates which GPIO chip to talk to (The number can be \n"
|
||||
"\tfound at /sys/class/gpio/gpiochipN).\n"
|
||||
"\tThe highest gpiochipN is the first gpio listed in the dts file, \n"
|
||||
"\tand the lowest gpiochipN is the last gpio listed in the dts file.\n"
|
||||
"\tE.g.If the gpiochip240 is the LED_8bit gpio, and I want to output '1' \n"
|
||||
"\tto the LED_8bit gpio, the command should be:\n"
|
||||
"\t\tgpio-demo -g 240 -o 1\n"
|
||||
"\n"
|
||||
"\tgpio-demo written by Xilinx Inc.\n"
|
||||
"\n"
|
||||
, basename);
|
||||
exit(-2);
|
||||
}
|
||||
|
||||
static int open_gpio_channel(int gpio_base)
|
||||
{
|
||||
char gpio_nchan_file[128];
|
||||
int gpio_nchan_fd;
|
||||
int gpio_max;
|
||||
int nchannel;
|
||||
char nchannel_str[5];
|
||||
char *cptr;
|
||||
int c;
|
||||
char channel_str[5];
|
||||
|
||||
char *gpio_export_file = "/sys/class/gpio/export";
|
||||
int export_fd=0;
|
||||
|
||||
/* Check how many channels the GPIO chip has */
|
||||
sprintf(gpio_nchan_file, "%s/gpiochip%d/ngpio", GPIO_ROOT, gpio_base);
|
||||
gpio_nchan_fd = open(gpio_nchan_file, O_RDONLY);
|
||||
if (gpio_nchan_fd < 0) {
|
||||
fprintf(stderr, "Failed to open %s: %s\n", gpio_nchan_file, strerror(errno));
|
||||
return -1;
|
||||
}
|
||||
read(gpio_nchan_fd, nchannel_str, sizeof(nchannel_str));
|
||||
close(gpio_nchan_fd);
|
||||
nchannel=(int)strtoul(nchannel_str, &cptr, 0);
|
||||
if (cptr == nchannel_str) {
|
||||
fprintf(stderr, "Failed to change %s into GPIO channel number\n", nchannel_str);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
/* Open files for each GPIO channel */
|
||||
export_fd=open(gpio_export_file, O_WRONLY);
|
||||
if (export_fd < 0) {
|
||||
fprintf(stderr, "Cannot open GPIO to export %d\n", gpio_base);
|
||||
return -1;
|
||||
}
|
||||
|
||||
gpio_max = gpio_base + nchannel;
|
||||
for(c = gpio_base; c < gpio_max; c++) {
|
||||
sprintf(channel_str, "%d", c);
|
||||
write(export_fd, channel_str, (strlen(channel_str)+1));
|
||||
}
|
||||
close(export_fd);
|
||||
return nchannel;
|
||||
}
|
||||
|
||||
static int close_gpio_channel(int gpio_base)
|
||||
{
|
||||
char gpio_nchan_file[128];
|
||||
int gpio_nchan_fd;
|
||||
int gpio_max;
|
||||
int nchannel;
|
||||
char nchannel_str[5];
|
||||
char *cptr;
|
||||
int c;
|
||||
char channel_str[5];
|
||||
|
||||
char *gpio_unexport_file = "/sys/class/gpio/unexport";
|
||||
int unexport_fd=0;
|
||||
|
||||
/* Check how many channels the GPIO chip has */
|
||||
sprintf(gpio_nchan_file, "%s/gpiochip%d/ngpio", GPIO_ROOT, gpio_base);
|
||||
gpio_nchan_fd = open(gpio_nchan_file, O_RDONLY);
|
||||
if (gpio_nchan_fd < 0) {
|
||||
fprintf(stderr, "Failed to open %s: %s\n", gpio_nchan_file, strerror(errno));
|
||||
return -1;
|
||||
}
|
||||
read(gpio_nchan_fd, nchannel_str, sizeof(nchannel_str));
|
||||
close(gpio_nchan_fd);
|
||||
nchannel=(int)strtoul(nchannel_str, &cptr, 0);
|
||||
if (cptr == nchannel_str) {
|
||||
fprintf(stderr, "Failed to change %s into GPIO channel number\n", nchannel_str);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
/* Close opened files for each GPIO channel */
|
||||
unexport_fd=open(gpio_unexport_file, O_WRONLY);
|
||||
if (unexport_fd < 0) {
|
||||
fprintf(stderr, "Cannot close GPIO by writing unexport %d\n", gpio_base);
|
||||
return -1;
|
||||
}
|
||||
|
||||
gpio_max = gpio_base + nchannel;
|
||||
for(c = gpio_base; c < gpio_max; c++) {
|
||||
sprintf(channel_str, "%d", c);
|
||||
write(unexport_fd, channel_str, (strlen(channel_str)+1));
|
||||
}
|
||||
close(unexport_fd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int set_gpio_direction(int gpio_base, int nchannel, char *direction)
|
||||
{
|
||||
char gpio_dir_file[128];
|
||||
int direction_fd=0;
|
||||
int gpio_max;
|
||||
int c;
|
||||
|
||||
gpio_max = gpio_base + nchannel;
|
||||
for(c = gpio_base; c < gpio_max; c++) {
|
||||
sprintf(gpio_dir_file, "/sys/class/gpio/gpio%d/direction",c);
|
||||
direction_fd=open(gpio_dir_file, O_RDWR);
|
||||
if (direction_fd < 0) {
|
||||
fprintf(stderr, "Cannot open the direction file for GPIO %d\n", c);
|
||||
return 1;
|
||||
}
|
||||
write(direction_fd, direction, (strlen(direction)+1));
|
||||
close(direction_fd);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int set_gpio_value(int gpio_base, int nchannel, int value)
|
||||
{
|
||||
char gpio_val_file[128];
|
||||
int val_fd=0;
|
||||
int gpio_max;
|
||||
char val_str[2];
|
||||
int c;
|
||||
|
||||
gpio_max = gpio_base + nchannel;
|
||||
|
||||
for(c = gpio_base; c < gpio_max; c++) {
|
||||
sprintf(gpio_val_file, "/sys/class/gpio/gpio%d/value",c);
|
||||
val_fd=open(gpio_val_file, O_RDWR);
|
||||
if (val_fd < 0) {
|
||||
fprintf(stderr, "Cannot open the value file of GPIO %d\n", c);
|
||||
return -1;
|
||||
}
|
||||
sprintf(val_str,"%d", (value & 1));
|
||||
write(val_fd, val_str, sizeof(val_str));
|
||||
close(val_fd);
|
||||
value >>= 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int get_gpio_value(int gpio_base, int nchannel)
|
||||
{
|
||||
char gpio_val_file[128];
|
||||
int val_fd=0;
|
||||
int gpio_max;
|
||||
char val_str[2];
|
||||
char *cptr;
|
||||
int value = 0;
|
||||
int c;
|
||||
|
||||
gpio_max = gpio_base + nchannel;
|
||||
|
||||
for(c = gpio_max-1; c >= gpio_base; c--) {
|
||||
sprintf(gpio_val_file, "/sys/class/gpio/gpio%d/value",c);
|
||||
val_fd=open(gpio_val_file, O_RDWR);
|
||||
if (val_fd < 0) {
|
||||
fprintf(stderr, "Cannot open GPIO to export %d\n", c);
|
||||
return -1;
|
||||
}
|
||||
read(val_fd, val_str, sizeof(val_str));
|
||||
value <<= 1;
|
||||
value += (int)strtoul(val_str, &cptr, 0);
|
||||
if (cptr == optarg) {
|
||||
fprintf(stderr, "Failed to change %s into integer", val_str);
|
||||
}
|
||||
close(val_fd);
|
||||
}
|
||||
return value;
|
||||
}
|
||||
|
||||
void signal_handler(int sig)
|
||||
{
|
||||
switch (sig) {
|
||||
case SIGTERM:
|
||||
case SIGHUP:
|
||||
case SIGQUIT:
|
||||
case SIGINT:
|
||||
close_gpio_channel(gl_gpio_base);
|
||||
exit(0) ;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
extern char *optarg;
|
||||
char *cptr;
|
||||
int gpio_value = 0;
|
||||
int nchannel = 0;
|
||||
|
||||
int c;
|
||||
int i;
|
||||
|
||||
opterr = 0;
|
||||
|
||||
while ((c = getopt(argc, argv, "g:io:ck")) != -1) {
|
||||
switch (c) {
|
||||
case 'g':
|
||||
gl_gpio_base = (int)strtoul(optarg, &cptr, 0);
|
||||
if (cptr == optarg)
|
||||
usage(argv[0]);
|
||||
break;
|
||||
case 'i':
|
||||
gpio_opt = IN;
|
||||
break;
|
||||
case 'o':
|
||||
gpio_opt = OUT;
|
||||
gpio_value = (int)strtoul(optarg, &cptr, 0);
|
||||
if (cptr == optarg)
|
||||
usage(argv[0]);
|
||||
break;
|
||||
case 'c':
|
||||
gpio_opt = CYLON;
|
||||
break;
|
||||
case 'k':
|
||||
gpio_opt = KIT;
|
||||
break;
|
||||
case '?':
|
||||
usage(argv[0]);
|
||||
default:
|
||||
usage(argv[0]);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
if (gl_gpio_base == 0) {
|
||||
usage(argv[0]);
|
||||
}
|
||||
|
||||
nchannel = open_gpio_channel(gl_gpio_base);
|
||||
signal(SIGTERM, signal_handler); /* catch kill signal */
|
||||
signal(SIGHUP, signal_handler); /* catch hang up signal */
|
||||
signal(SIGQUIT, signal_handler); /* catch quit signal */
|
||||
signal(SIGINT, signal_handler); /* catch a CTRL-c signal */
|
||||
switch (gpio_opt) {
|
||||
case IN:
|
||||
set_gpio_direction(gl_gpio_base, nchannel, "in");
|
||||
gpio_value=get_gpio_value(gl_gpio_base, nchannel);
|
||||
fprintf(stdout,"0x%08X\n", gpio_value);
|
||||
break;
|
||||
case OUT:
|
||||
set_gpio_direction(gl_gpio_base, nchannel, "out");
|
||||
set_gpio_value(gl_gpio_base, nchannel, gpio_value);
|
||||
break;
|
||||
case CYLON:
|
||||
#define CYLON_DELAY_USECS (10000)
|
||||
set_gpio_direction(gl_gpio_base, nchannel, "out");
|
||||
for (;;) {
|
||||
for(i=0; i < ARRAY_SIZE(cylon); i++) {
|
||||
gpio_value=(int)cylon[i];
|
||||
set_gpio_value(gl_gpio_base, nchannel, gpio_value);
|
||||
}
|
||||
usleep(CYLON_DELAY_USECS);
|
||||
}
|
||||
case KIT:
|
||||
#define KIT_DELAY_USECS (10000)
|
||||
set_gpio_direction(gl_gpio_base, nchannel, "out");
|
||||
for (;;) {
|
||||
for (i=0; i<ARRAY_SIZE(kit); i++) {
|
||||
gpio_value=(int)kit[i];
|
||||
set_gpio_value(gl_gpio_base, nchannel, gpio_value);
|
||||
}
|
||||
usleep(KIT_DELAY_USECS);
|
||||
}
|
||||
default:
|
||||
break;
|
||||
}
|
||||
close_gpio_channel(gl_gpio_base);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -0,0 +1,23 @@
|
||||
#
|
||||
# This is the GPIO-DEMO apllication recipe
|
||||
#
|
||||
#
|
||||
|
||||
SUMMARY = "gpio-demo application"
|
||||
SECTION = "PETALINUX/apps"
|
||||
LICENSE = "MIT"
|
||||
LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
|
||||
SRC_URI = "file://gpio-demo.c \
|
||||
file://Makefile \
|
||||
"
|
||||
S = "${WORKDIR}"
|
||||
CFLAGS_prepend = "-I ${S}/include"
|
||||
do_compile() {
|
||||
oe_runmake
|
||||
}
|
||||
do_install() {
|
||||
install -d ${D}${bindir}
|
||||
install -m 0755 ${S}/gpio-demo ${D}${bindir}
|
||||
|
||||
}
|
||||
|
||||
@ -0,0 +1,19 @@
|
||||
PEEK = peek
|
||||
POKE = poke
|
||||
|
||||
# Add any other object files to this list below
|
||||
PEEK_OBJS = peek.o
|
||||
POKE_OBJS = poke.o
|
||||
|
||||
all: $(PEEK) $(POKE)
|
||||
|
||||
$(POKE): $(POKE_OBJS)
|
||||
$(CC) $(LDFLAGS) -o $@ $(POKE_OBJS) $(LDLIBS)
|
||||
|
||||
$(PEEK): $(PEEK_OBJS)
|
||||
$(CC) $(LDFLAGS) -o $@ $(PEEK_OBJS) $(LDLIBS)
|
||||
|
||||
clean:
|
||||
-rm -f $(POKE) $(PEEK) *.elf *.gdb *.o
|
||||
|
||||
|
||||
@ -0,0 +1,77 @@
|
||||
/*
|
||||
* peek utility - for those who remember the good old days!
|
||||
*
|
||||
*
|
||||
* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without restriction,
|
||||
* including without limitation the rights to use, copy, modify, merge,
|
||||
* publish, distribute, sublicense, and/or sell copies of the Software,
|
||||
* and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in this
|
||||
* Software without prior written authorization from Xilinx.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/mman.h>
|
||||
#include <fcntl.h>
|
||||
|
||||
void usage(char *prog)
|
||||
{
|
||||
printf("usage: %s ADDR\n",prog);
|
||||
printf("\n");
|
||||
printf("ADDR may be specified as hex values\n");
|
||||
}
|
||||
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
int fd;
|
||||
void *ptr;
|
||||
unsigned addr, page_addr, page_offset;
|
||||
unsigned page_size=sysconf(_SC_PAGESIZE);
|
||||
|
||||
if(argc!=2) {
|
||||
usage(argv[0]);
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
fd=open("/dev/mem",O_RDONLY);
|
||||
if(fd<1) {
|
||||
perror(argv[0]);
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
addr=strtoul(argv[1],NULL,0);
|
||||
page_addr=(addr & ~(page_size-1));
|
||||
page_offset=addr-page_addr;
|
||||
|
||||
ptr=mmap(NULL,page_size,PROT_READ,MAP_SHARED,fd,(addr & ~(page_size-1)));
|
||||
if((int)ptr==-1) {
|
||||
perror(argv[0]);
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
printf("0x%08x\n",*((unsigned *)(ptr+page_offset)));
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -0,0 +1,77 @@
|
||||
/*
|
||||
* poke utility - for those who remember the good old days!
|
||||
*
|
||||
|
||||
* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without restriction,
|
||||
* including without limitation the rights to use, copy, modify, merge,
|
||||
* publish, distribute, sublicense, and/or sell copies of the Software,
|
||||
* and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in this
|
||||
* Software without prior written authorization from Xilinx.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/mman.h>
|
||||
#include <fcntl.h>
|
||||
|
||||
void usage(char *prog)
|
||||
{
|
||||
printf("usage: %s ADDR VAL\n",prog);
|
||||
printf("\n");
|
||||
printf("ADDR and VAL may be specified as hex values\n");
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
int fd;
|
||||
void *ptr;
|
||||
unsigned val;
|
||||
unsigned addr, page_addr, page_offset;
|
||||
unsigned page_size=sysconf(_SC_PAGESIZE);
|
||||
|
||||
fd=open("/dev/mem",O_RDWR);
|
||||
if(fd<1) {
|
||||
perror(argv[0]);
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
if(argc!=3) {
|
||||
usage(argv[0]);
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
addr=strtoul(argv[1],NULL,0);
|
||||
val=strtoul(argv[2],NULL,0);
|
||||
|
||||
page_addr=(addr & ~(page_size-1));
|
||||
page_offset=addr-page_addr;
|
||||
|
||||
ptr=mmap(NULL,page_size,PROT_READ|PROT_WRITE,MAP_SHARED,fd,(addr & ~(page_size-1)));
|
||||
if((int)ptr==-1) {
|
||||
perror(argv[0]);
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
*((unsigned *)(ptr+page_offset))=val;
|
||||
return 0;
|
||||
}
|
||||
@ -0,0 +1,25 @@
|
||||
#
|
||||
# This is the peekpoke apllication recipe
|
||||
#
|
||||
#
|
||||
|
||||
SUMMARY = "peekpoke application"
|
||||
SECTION = "PETALINUX/apps"
|
||||
LICENSE = "MIT"
|
||||
LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
|
||||
SRC_URI = "file://peek.c \
|
||||
file://poke.c \
|
||||
file://Makefile \
|
||||
"
|
||||
S = "${WORKDIR}"
|
||||
CFLAGS_prepend = "-I ${S}/include"
|
||||
do_compile() {
|
||||
oe_runmake
|
||||
}
|
||||
do_install() {
|
||||
install -d ${D}${bindir}
|
||||
install -m 0755 ${S}/peek ${D}${bindir}
|
||||
install -m 0755 ${S}/poke ${D}${bindir}
|
||||
|
||||
}
|
||||
|
||||
@ -0,0 +1,17 @@
|
||||
FILESEXTRAPATHS_prepend := "${THISDIR}/files:${SYSCONFIG_PATH}:"
|
||||
|
||||
SRC_URI_append = " file://config file://system-user.dtsi"
|
||||
|
||||
python () {
|
||||
if d.getVar("CONFIG_DISABLE"):
|
||||
d.setVarFlag("do_configure", "noexec", "1")
|
||||
}
|
||||
|
||||
export PETALINUX
|
||||
do_configure_append () {
|
||||
script="${PETALINUX}/etc/hsm/scripts/petalinux_hsm_bridge.tcl"
|
||||
data=${PETALINUX}/etc/hsm/data/
|
||||
eval xsct -sdx -nodisp ${script} -c ${WORKDIR}/config \
|
||||
-hdf ${DT_FILES_PATH}/hardware_description.${HDF_EXT} -repo ${S} \
|
||||
-data ${data} -sw ${DT_FILES_PATH} -o ${DT_FILES_PATH} -a "soc_mapping"
|
||||
}
|
||||
@ -0,0 +1,2 @@
|
||||
/ {
|
||||
};
|
||||
@ -0,0 +1,78 @@
|
||||
/include/ "system-conf.dtsi"
|
||||
|
||||
/ {
|
||||
/delete-node/ m_axil_ctrl@a0000000;
|
||||
/delete-node/ m_axil_app_ctrl@a8000000;
|
||||
|
||||
mqnic0: ethernet@a0000000 {
|
||||
compatible = "corundum,mqnic";
|
||||
reg = <0x0 0xa0000000 0x0 0x1000000>,
|
||||
<0x0 0xa8000000 0x0 0x1000000>;
|
||||
reg-names = "csr", "app";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0x0 0x59 0x1>, <0x0 0x5a 0x1>, <0x0 0x5b 0x1>,
|
||||
<0x0 0x5c 0x1>;
|
||||
|
||||
nvmem-cells = <&macaddress>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
|
||||
/* NOTE: The nvmem-cells property provides us with a base MAC
|
||||
* address. We increment its last byte (default) by 0x1. And we
|
||||
* mark the derived address as "locally administrated". The
|
||||
* result is used to derive MAC addresses for mqnic interfaces.
|
||||
*/
|
||||
mac-address-increment = <0x1>;
|
||||
mac-address-local;
|
||||
|
||||
module-eeproms = <&module_eeprom_sfp0>, <&module_eeprom_sfp1>,
|
||||
<&module_eeprom_sfp2>, <&module_eeprom_sfp3>;
|
||||
};
|
||||
};
|
||||
|
||||
&eeprom {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
macaddress: macaddress@20 {
|
||||
/* NOTE: On Xilinx Zynq boards there usually is an
|
||||
* EEPROM with a MAC address for one of the PS GEMs at
|
||||
* offset 0x20. So we take that address as our base
|
||||
* address.
|
||||
*/
|
||||
reg = <0x20 0x06>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
i2c-mux@75 {
|
||||
i2c@4 {
|
||||
module_eeprom_sfp3: eeprom@50 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
i2c@5 {
|
||||
module_eeprom_sfp2: eeprom@50 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
i2c@6 {
|
||||
module_eeprom_sfp1: eeprom@50 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
i2c@7 {
|
||||
module_eeprom_sfp0: eeprom@50 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* USER MGT SI570 (U56) */
|
||||
&si570_2 {
|
||||
clock-frequency = <156250000>;
|
||||
};
|
||||
@ -0,0 +1,4 @@
|
||||
###############################################################################
|
||||
# enable message level FSBL_DEBUG_DETAILED
|
||||
|
||||
YAML_COMPILER_FLAGS_append = " -DFSBL_DEBUG_DETAILED"
|
||||
@ -0,0 +1,28 @@
|
||||
From 357b3eebaa54be1ec8d14b306625eb73732ee5dc Mon Sep 17 00:00:00 2001
|
||||
From: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
|
||||
Date: Wed, 19 Aug 2020 05:29:40 -0600
|
||||
Subject: [UBOOT PATCH] ubifs: distroboot support
|
||||
|
||||
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
|
||||
---
|
||||
include/configs/xilinx_zynqmp.h | 5 ++++-
|
||||
1 file changed, 4 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
|
||||
index d3f465a..dc231b8 100644
|
||||
--- a/include/configs/xilinx_zynqmp.h
|
||||
+++ b/include/configs/xilinx_zynqmp.h
|
||||
@@ -154,7 +154,10 @@
|
||||
|
||||
#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
|
||||
"bootcmd_" #devtypel #instance "=sf probe " #instance " 0 0 && " \
|
||||
- "sf read $scriptaddr $script_offset_f $script_size_f && " \
|
||||
+ "setenv mtdids 'nor0=nor0' && " \
|
||||
+ "setenv mtdparts 'mtdparts=nor0:16m(raw),-(boot)' && " \
|
||||
+ "mtdparts && " \
|
||||
+ "ubi part boot; ubifsmount ubi0:boot; ubifsload $scriptaddr boot.scr; && " \
|
||||
"echo QSPI: Trying to boot script at ${scriptaddr} && " \
|
||||
"source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0"
|
||||
|
||||
--
|
||||
2.7.4
|
||||
@ -0,0 +1,2 @@
|
||||
#include <configs/xilinx_zynqmp.h>
|
||||
#include <configs/platform-auto.h>
|
||||
@ -0,0 +1,17 @@
|
||||
FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
|
||||
|
||||
SRC_URI += "file://platform-top.h"
|
||||
|
||||
do_configure_append () {
|
||||
if [ "${U_BOOT_AUTO_CONFIG}" = "1" ]; then
|
||||
install ${WORKDIR}/platform-auto.h ${S}/include/configs/
|
||||
install ${WORKDIR}/platform-top.h ${S}/include/configs/
|
||||
fi
|
||||
}
|
||||
|
||||
do_configure_append_microblaze () {
|
||||
if [ "${U_BOOT_AUTO_CONFIG}" = "1" ]; then
|
||||
install -d ${B}/source/board/xilinx/microblaze-generic/
|
||||
install ${WORKDIR}/config.mk ${B}/source/board/xilinx/microblaze-generic/
|
||||
fi
|
||||
}
|
||||
@ -0,0 +1,3 @@
|
||||
/include/ "system-conf.dtsi"
|
||||
/ {
|
||||
};
|
||||
@ -0,0 +1,16 @@
|
||||
FILESEXTRAPATHS_prepend := "${THISDIR}/files:${SYSCONFIG_PATH}:"
|
||||
|
||||
SRC_URI_append = " file://config file://system-user.dtsi"
|
||||
|
||||
python () {
|
||||
if d.getVar("CONFIG_DISABLE"):
|
||||
d.setVarFlag("do_configure", "noexec", "1")
|
||||
}
|
||||
export PETALINUX
|
||||
do_configure_append () {
|
||||
script="${PETALINUX}/etc/hsm/scripts/petalinux_hsm_bridge.tcl"
|
||||
data=${PETALINUX}/etc/hsm/data/
|
||||
eval xsct -sdx -nodisp ${script} -c ${WORKDIR}/config \
|
||||
-hdf ${DT_FILES_PATH}/hardware_description.${HDF_EXT} -repo ${S} \
|
||||
-data ${data} -sw ${DT_FILES_PATH} -o ${DT_FILES_PATH} -a "soc_mapping"
|
||||
}
|
||||
@ -0,0 +1,20 @@
|
||||
CONFIG_NET_PTP_CLASSIFY=y
|
||||
CONFIG_MACB_USE_HWSTAMP=y
|
||||
# CONFIG_CAVIUM_PTP is not set
|
||||
CONFIG_PPS=m
|
||||
# CONFIG_PPS_DEBUG is not set
|
||||
|
||||
#
|
||||
# PPS clients support
|
||||
#
|
||||
# CONFIG_PPS_CLIENT_KTIMER is not set
|
||||
# CONFIG_PPS_CLIENT_LDISC is not set
|
||||
# CONFIG_PPS_CLIENT_GPIO is not set
|
||||
|
||||
#
|
||||
# PPS generators support
|
||||
#
|
||||
CONFIG_PTP_1588_CLOCK=m
|
||||
# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
|
||||
# CONFIG_PTP_1588_CLOCK_IDTCM is not set
|
||||
# CONFIG_PTP_1588_CLOCK_XILINX is not set
|
||||
@ -0,0 +1,4 @@
|
||||
SRC_URI += "file://enable_ptp.cfg"
|
||||
|
||||
FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
|
||||
|
||||
1
fpga/mqnic/ZCU102/fpga/rtl/common
Symbolic link
1
fpga/mqnic/ZCU102/fpga/rtl/common
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../common/rtl/
|
||||
93
fpga/mqnic/ZCU102/fpga/rtl/debounce_switch.v
Normal file
93
fpga/mqnic/ZCU102/fpga/rtl/debounce_switch.v
Normal file
@ -0,0 +1,93 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`resetall
|
||||
`timescale 1 ns / 1 ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Synchronizes switch and button inputs with a slow sampled shift register
|
||||
*/
|
||||
module debounce_switch #(
|
||||
parameter WIDTH=1, // width of the input and output signals
|
||||
parameter N=3, // length of shift register
|
||||
parameter RATE=125000 // clock division factor
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire [WIDTH-1:0] in,
|
||||
output wire [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
reg [23:0] cnt_reg = 24'd0;
|
||||
|
||||
reg [N-1:0] debounce_reg[WIDTH-1:0];
|
||||
|
||||
reg [WIDTH-1:0] state;
|
||||
|
||||
/*
|
||||
* The synchronized output is the state register
|
||||
*/
|
||||
assign out = state;
|
||||
|
||||
integer k;
|
||||
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst) begin
|
||||
cnt_reg <= 0;
|
||||
state <= 0;
|
||||
|
||||
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||
debounce_reg[k] <= 0;
|
||||
end
|
||||
end else begin
|
||||
if (cnt_reg < RATE) begin
|
||||
cnt_reg <= cnt_reg + 24'd1;
|
||||
end else begin
|
||||
cnt_reg <= 24'd0;
|
||||
end
|
||||
|
||||
if (cnt_reg == 24'd0) begin
|
||||
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||
debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
|
||||
end
|
||||
end
|
||||
|
||||
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||
if (|debounce_reg[k] == 0) begin
|
||||
state[k] <= 0;
|
||||
end else if (&debounce_reg[k] == 1) begin
|
||||
state[k] <= 1;
|
||||
end else begin
|
||||
state[k] <= state[k];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
1087
fpga/mqnic/ZCU102/fpga/rtl/fpga.v
Normal file
1087
fpga/mqnic/ZCU102/fpga/rtl/fpga.v
Normal file
File diff suppressed because it is too large
Load Diff
1132
fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v
Normal file
1132
fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v
Normal file
File diff suppressed because it is too large
Load Diff
0
fpga/mqnic/ZCU102/fpga/rtl/sync_signal.v
Normal file
0
fpga/mqnic/ZCU102/fpga/rtl/sync_signal.v
Normal file
411
fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile
Normal file
411
fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile
Normal file
@ -0,0 +1,411 @@
|
||||
# Copyright 2020-2021, The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
# OF SUCH DAMAGE.
|
||||
#
|
||||
# The views and conclusions contained in the software and documentation are those
|
||||
# of the authors and should not be interpreted as representing official policies,
|
||||
# either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= icarus
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
DUT = fpga_core
|
||||
TOPLEVEL = $(DUT)
|
||||
MODULE = test_$(DUT)
|
||||
VERILOG_SOURCES += ../../rtl/$(DUT).v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core_axi.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v
|
||||
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
|
||||
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
|
||||
VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/event_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
|
||||
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_hash.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_checksum.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rb_drp.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_counter.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_collect.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_dma_if_axi.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tdma_ber.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# module parameters
|
||||
|
||||
# Structural configuration
|
||||
export PARAM_IF_COUNT ?= 2
|
||||
export PARAM_PORTS_PER_IF ?= 1
|
||||
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
|
||||
export PARAM_PORT_MASK ?= 0
|
||||
|
||||
# PTP configuration
|
||||
export PARAM_PTP_CLK_PERIOD_NS_NUM = 32
|
||||
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5
|
||||
export PARAM_PTP_CLOCK_PIPELINE ?= 0
|
||||
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
|
||||
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
|
||||
export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
|
||||
export PARAM_PTP_PEROUT_ENABLE ?= 1
|
||||
export PARAM_PTP_PEROUT_COUNT ?= 1
|
||||
|
||||
# Queue manager configuration
|
||||
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 2
|
||||
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 5
|
||||
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 5
|
||||
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
export PARAM_EVENT_QUEUE_PIPELINE ?= 3
|
||||
export PARAM_TX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
|
||||
export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
|
||||
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
|
||||
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
|
||||
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE ?= 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE ?= 32
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
|
||||
export PARAM_TDMA_INDEX_WIDTH ?= 6
|
||||
|
||||
# Interface configuration
|
||||
export PARAM_PTP_TS_ENABLE ?= 1
|
||||
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
|
||||
export PARAM_TX_CHECKSUM_ENABLE ?= 1
|
||||
export PARAM_RX_RSS_ENABLE ?= 1
|
||||
export PARAM_RX_HASH_ENABLE ?= 1
|
||||
export PARAM_RX_CHECKSUM_ENABLE ?= 1
|
||||
export PARAM_TX_FIFO_DEPTH ?= 32768
|
||||
export PARAM_RX_FIFO_DEPTH ?= 32768
|
||||
export PARAM_MAX_TX_SIZE ?= 9214
|
||||
export PARAM_MAX_RX_SIZE ?= 9214
|
||||
export PARAM_TX_RAM_SIZE ?= 32768
|
||||
export PARAM_RX_RAM_SIZE ?= 32768
|
||||
|
||||
# Application block configuration
|
||||
export PARAM_APP_ID ?= $(shell echo $$((0x00000000)) )
|
||||
export PARAM_APP_ENABLE ?= 0
|
||||
export PARAM_APP_CTRL_ENABLE ?= 1
|
||||
export PARAM_APP_DMA_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_DIRECT_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_SYNC_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_IF_ENABLE ?= 1
|
||||
export PARAM_APP_STAT_ENABLE ?= 1
|
||||
|
||||
# AXI DMA interface configuration
|
||||
export PARAM_AXI_DATA_WIDTH ?= 128
|
||||
export PARAM_AXI_ADDR_WIDTH ?= 40
|
||||
export PARAM_AXI_ID_WIDTH ?= 4
|
||||
|
||||
# DMA interface configuration
|
||||
export PARAM_DMA_IMM_ENABLE ?= 0
|
||||
export PARAM_DMA_IMM_WIDTH ?= 32
|
||||
export PARAM_DMA_LEN_WIDTH ?= 16
|
||||
export PARAM_DMA_TAG_WIDTH ?= 16
|
||||
export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
|
||||
export PARAM_RAM_PIPELINE ?= 2
|
||||
export PARAM_AXI_DMA_MAX_BURST_LEN ?= 16
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
|
||||
export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
export PARAM_AXIL_APP_CTRL_DATA_WIDTH ?= $(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
export PARAM_AXIL_APP_CTRL_ADDR_WIDTH ?= 24
|
||||
|
||||
# Ethernet interface configuration
|
||||
export PARAM_AXIS_ETH_TX_PIPELINE ?= 0
|
||||
export PARAM_AXIS_ETH_TX_FIFO_PIPELINE ?= 2
|
||||
export PARAM_AXIS_ETH_TX_TS_PIPELINE ?= 0
|
||||
export PARAM_AXIS_ETH_RX_PIPELINE ?= 0
|
||||
export PARAM_AXIS_ETH_RX_FIFO_PIPELINE ?= 2
|
||||
|
||||
# Statistics counter subsystem
|
||||
export PARAM_STAT_ENABLE ?= 1
|
||||
export PARAM_STAT_DMA_ENABLE ?= 1
|
||||
export PARAM_STAT_AXI_ENABLE ?= 1
|
||||
export PARAM_STAT_INC_WIDTH ?= 24
|
||||
export PARAM_STAT_ID_WIDTH ?= 12
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_INDEX_WIDTH=$(PARAM_EVENT_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).MAX_TX_SIZE=$(PARAM_MAX_TX_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_ID=$(PARAM_APP_ID)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_ENABLE=$(PARAM_APP_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXI_DMA_MAX_BURST_LEN=$(PARAM_AXI_DMA_MAX_BURST_LEN)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ENABLE=$(PARAM_STAT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_AXI_ENABLE=$(PARAM_STAT_AXI_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
COMPILE_ARGS += -s iverilog_dump
|
||||
endif
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
|
||||
|
||||
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
|
||||
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
|
||||
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
|
||||
COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK)
|
||||
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
|
||||
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
|
||||
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
|
||||
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
|
||||
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
|
||||
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
|
||||
COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
|
||||
COMPILE_ARGS += -GPTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT)
|
||||
COMPILE_ARGS += -GEVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GEVENT_QUEUE_INDEX_WIDTH=$(PARAM_EVENT_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GTX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GRX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GEVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GRX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
|
||||
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
|
||||
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
|
||||
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
|
||||
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GMAX_TX_SIZE=$(PARAM_MAX_TX_SIZE)
|
||||
COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
|
||||
COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
|
||||
COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
|
||||
COMPILE_ARGS += -GAPP_ID=$(PARAM_APP_ID)
|
||||
COMPILE_ARGS += -GAPP_ENABLE=$(PARAM_APP_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
|
||||
COMPILE_ARGS += -GAXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -GAXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH)
|
||||
COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
|
||||
COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
|
||||
COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
|
||||
COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
|
||||
COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE)
|
||||
COMPILE_ARGS += -GAXI_DMA_MAX_BURST_LEN=$(PARAM_AXI_DMA_MAX_BURST_LEN)
|
||||
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -GSTAT_ENABLE=$(PARAM_STAT_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_AXI_ENABLE=$(PARAM_STAT_AXI_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
|
||||
COMPILE_ARGS += -GSTAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
|
||||
iverilog_dump.v:
|
||||
echo 'module iverilog_dump();' > $@
|
||||
echo 'initial begin' >> $@
|
||||
echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
|
||||
echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
|
||||
echo 'end' >> $@
|
||||
echo 'endmodule' >> $@
|
||||
|
||||
clean::
|
||||
@rm -rf iverilog_dump.v
|
||||
@rm -rf dump.fst $(TOPLEVEL).fst
|
||||
1
fpga/mqnic/ZCU102/fpga/tb/fpga_core/mqnic.py
Symbolic link
1
fpga/mqnic/ZCU102/fpga/tb/fpga_core/mqnic.py
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../../common/tb/mqnic.py
|
||||
586
fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
Normal file
586
fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
Normal file
@ -0,0 +1,586 @@
|
||||
"""
|
||||
|
||||
Copyright 2020-2021, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
|
||||
The views and conclusions contained in the software and documentation are those
|
||||
of the authors and should not be interpreted as representing official policies,
|
||||
either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
"""
|
||||
|
||||
import logging
|
||||
import os
|
||||
import sys
|
||||
|
||||
import scapy.utils
|
||||
from scapy.layers.l2 import Ether
|
||||
from scapy.layers.inet import IP, UDP
|
||||
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.log import SimLog
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
|
||||
from cocotbext.axi import AddressSpace
|
||||
from cocotbext.axi import AxiLiteMaster, AxiLiteBus
|
||||
from cocotbext.axi import AxiSlave, AxiBus
|
||||
from cocotbext.eth import XgmiiSource, XgmiiSink
|
||||
|
||||
try:
|
||||
import mqnic
|
||||
except ImportError:
|
||||
# attempt import from current directory
|
||||
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||
try:
|
||||
import mqnic
|
||||
finally:
|
||||
del sys.path[0]
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = SimLog("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk_300mhz, 3332, units="ps").start())
|
||||
|
||||
# AXI
|
||||
self.address_space = AddressSpace()
|
||||
self.pool = self.address_space.create_pool(0, 0x8000_0000)
|
||||
|
||||
self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil_ctrl"), dut.clk_300mhz, dut.rst_300mhz)
|
||||
self.address_space.register_region(self.axil_master, 0x10_0000_0000)
|
||||
self.hw_regs = self.address_space.create_window(0x10_0000_0000, self.axil_master.size)
|
||||
|
||||
self.axi_slave = AxiSlave(AxiBus.from_prefix(dut, "m_axi"), dut.clk_300mhz, dut.rst_300mhz, self.address_space)
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
cocotb.start_soon(Clock(dut.ptp_clk, 6.4, units="ns").start())
|
||||
dut.ptp_rst.setimmediatevalue(0)
|
||||
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
|
||||
|
||||
# Ethernet
|
||||
cocotb.start_soon(Clock(dut.sfp0_rx_clk, 6.4, units="ns").start())
|
||||
self.sfp0_source = XgmiiSource(dut.sfp0_rxd, dut.sfp0_rxc, dut.sfp0_rx_clk, dut.sfp0_rx_rst)
|
||||
cocotb.start_soon(Clock(dut.sfp0_tx_clk, 6.4, units="ns").start())
|
||||
self.sfp0_sink = XgmiiSink(dut.sfp0_txd, dut.sfp0_txc, dut.sfp0_tx_clk, dut.sfp0_tx_rst)
|
||||
|
||||
cocotb.start_soon(Clock(dut.sfp1_rx_clk, 6.4, units="ns").start())
|
||||
self.sfp1_source = XgmiiSource(dut.sfp1_rxd, dut.sfp1_rxc, dut.sfp1_rx_clk, dut.sfp1_rx_rst)
|
||||
cocotb.start_soon(Clock(dut.sfp1_tx_clk, 6.4, units="ns").start())
|
||||
self.sfp1_sink = XgmiiSink(dut.sfp1_txd, dut.sfp1_txc, dut.sfp1_tx_clk, dut.sfp1_tx_rst)
|
||||
|
||||
cocotb.start_soon(Clock(dut.sfp2_rx_clk, 6.4, units="ns").start())
|
||||
self.sfp2_source = XgmiiSource(dut.sfp2_rxd, dut.sfp2_rxc, dut.sfp2_rx_clk, dut.sfp2_rx_rst)
|
||||
cocotb.start_soon(Clock(dut.sfp2_tx_clk, 6.4, units="ns").start())
|
||||
self.sfp2_sink = XgmiiSink(dut.sfp2_txd, dut.sfp2_txc, dut.sfp2_tx_clk, dut.sfp2_tx_rst)
|
||||
|
||||
cocotb.start_soon(Clock(dut.sfp3_rx_clk, 6.4, units="ns").start())
|
||||
self.sfp3_source = XgmiiSource(dut.sfp3_rxd, dut.sfp3_rxc, dut.sfp3_rx_clk, dut.sfp3_rx_rst)
|
||||
cocotb.start_soon(Clock(dut.sfp3_tx_clk, 6.4, units="ns").start())
|
||||
self.sfp3_sink = XgmiiSink(dut.sfp3_txd, dut.sfp3_txc, dut.sfp3_tx_clk, dut.sfp3_tx_rst)
|
||||
|
||||
dut.sfp0_rx_status.setimmediatevalue(1)
|
||||
dut.sfp1_rx_status.setimmediatevalue(1)
|
||||
dut.sfp2_rx_status.setimmediatevalue(1)
|
||||
dut.sfp3_rx_status.setimmediatevalue(1)
|
||||
|
||||
cocotb.start_soon(Clock(dut.sfp_drp_clk, 8, units="ns").start())
|
||||
dut.sfp_drp_rst.setimmediatevalue(0)
|
||||
dut.sfp_drp_do.setimmediatevalue(0)
|
||||
dut.sfp_drp_rdy.setimmediatevalue(0)
|
||||
|
||||
dut.sfp0_rx_error_count.setimmediatevalue(0)
|
||||
dut.sfp1_rx_error_count.setimmediatevalue(0)
|
||||
dut.sfp2_rx_error_count.setimmediatevalue(0)
|
||||
dut.sfp3_rx_error_count.setimmediatevalue(0)
|
||||
|
||||
dut.btnu.setimmediatevalue(0)
|
||||
dut.btnl.setimmediatevalue(0)
|
||||
dut.btnd.setimmediatevalue(0)
|
||||
dut.btnr.setimmediatevalue(0)
|
||||
dut.btnc.setimmediatevalue(0)
|
||||
dut.sw.setimmediatevalue(0)
|
||||
|
||||
self.loopback_enable = False
|
||||
cocotb.start_soon(self._run_loopback())
|
||||
|
||||
async def init(self):
|
||||
|
||||
self.dut.rst_300mhz.setimmediatevalue(0)
|
||||
self.dut.ptp_rst.setimmediatevalue(0)
|
||||
self.dut.sfp0_rx_rst.setimmediatevalue(0)
|
||||
self.dut.sfp0_tx_rst.setimmediatevalue(0)
|
||||
self.dut.sfp1_rx_rst.setimmediatevalue(0)
|
||||
self.dut.sfp1_tx_rst.setimmediatevalue(0)
|
||||
self.dut.sfp2_rx_rst.setimmediatevalue(0)
|
||||
self.dut.sfp2_tx_rst.setimmediatevalue(0)
|
||||
self.dut.sfp3_rx_rst.setimmediatevalue(0)
|
||||
self.dut.sfp3_tx_rst.setimmediatevalue(0)
|
||||
|
||||
await RisingEdge(self.dut.clk_300mhz)
|
||||
await RisingEdge(self.dut.clk_300mhz)
|
||||
|
||||
self.dut.rst_300mhz.value = 1
|
||||
self.dut.ptp_rst.setimmediatevalue(1)
|
||||
self.dut.sfp0_rx_rst.setimmediatevalue(1)
|
||||
self.dut.sfp0_tx_rst.setimmediatevalue(1)
|
||||
self.dut.sfp1_rx_rst.setimmediatevalue(1)
|
||||
self.dut.sfp1_tx_rst.setimmediatevalue(1)
|
||||
self.dut.sfp2_rx_rst.setimmediatevalue(1)
|
||||
self.dut.sfp2_tx_rst.setimmediatevalue(1)
|
||||
self.dut.sfp3_rx_rst.setimmediatevalue(1)
|
||||
self.dut.sfp3_tx_rst.setimmediatevalue(1)
|
||||
|
||||
await RisingEdge(self.dut.clk_300mhz)
|
||||
await RisingEdge(self.dut.clk_300mhz)
|
||||
|
||||
self.dut.rst_300mhz.value = 0
|
||||
self.dut.ptp_rst.setimmediatevalue(0)
|
||||
self.dut.sfp0_rx_rst.setimmediatevalue(0)
|
||||
self.dut.sfp0_tx_rst.setimmediatevalue(0)
|
||||
self.dut.sfp1_rx_rst.setimmediatevalue(0)
|
||||
self.dut.sfp1_tx_rst.setimmediatevalue(0)
|
||||
self.dut.sfp2_rx_rst.setimmediatevalue(0)
|
||||
self.dut.sfp2_tx_rst.setimmediatevalue(0)
|
||||
self.dut.sfp3_rx_rst.setimmediatevalue(0)
|
||||
self.dut.sfp3_tx_rst.setimmediatevalue(0)
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
await RisingEdge(self.dut.clk_300mhz)
|
||||
|
||||
if self.loopback_enable:
|
||||
if not self.sfp0_sink.empty():
|
||||
await self.sfp0_source.send(await self.sfp0_sink.recv())
|
||||
if not self.sfp1_sink.empty():
|
||||
await self.sfp1_source.send(await self.sfp1_sink.recv())
|
||||
if not self.sfp2_sink.empty():
|
||||
await self.sfp2_source.send(await self.sfp2_sink.recv())
|
||||
if not self.sfp3_sink.empty():
|
||||
await self.sfp3_source.send(await self.sfp3_sink.recv())
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_test_nic(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_axi_dev(tb.pool, tb.hw_regs, irq=dut.irq)
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
# enable queues
|
||||
tb.log.info("Enable queues")
|
||||
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
|
||||
for k in range(tb.driver.interfaces[0].tx_queue_count):
|
||||
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
|
||||
|
||||
# wait for all writes to complete
|
||||
await tb.driver.hw_regs.read_dword(0)
|
||||
tb.log.info("Init complete")
|
||||
|
||||
tb.log.info("Send and receive single packet")
|
||||
|
||||
data = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
pkt = await tb.sfp0_sink.recv()
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
|
||||
await tb.sfp0_source.send(pkt)
|
||||
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
# await tb.driver.interfaces[1].start_xmit(data, 0)
|
||||
|
||||
# pkt = await tb.sfp1_sink.recv()
|
||||
# tb.log.info("Packet: %s", pkt)
|
||||
|
||||
# await tb.sfp1_source.send(pkt)
|
||||
|
||||
# pkt = await tb.driver.interfaces[1].recv()
|
||||
|
||||
# tb.log.info("Packet: %s", pkt)
|
||||
# assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.log.info("RX and TX checksum tests")
|
||||
|
||||
payload = bytes([x % 256 for x in range(256)])
|
||||
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
|
||||
ip = IP(src='192.168.1.100', dst='192.168.1.101')
|
||||
udp = UDP(sport=1, dport=2)
|
||||
test_pkt = eth / ip / udp / payload
|
||||
|
||||
test_pkt2 = test_pkt.copy()
|
||||
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
|
||||
|
||||
pkt = await tb.sfp0_sink.recv()
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
|
||||
await tb.sfp0_source.send(pkt)
|
||||
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
assert Ether(pkt.data).build() == test_pkt.build()
|
||||
|
||||
tb.log.info("Queue mapping offset test")
|
||||
|
||||
data = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
assert pkt.queue == k
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
|
||||
for k in range(64):
|
||||
payload = bytes([x % 256 for x in range(256)])
|
||||
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
|
||||
ip = IP(src='192.168.1.100', dst='192.168.1.101')
|
||||
udp = UDP(sport=1, dport=k+0)
|
||||
test_pkt = eth / ip / udp / payload
|
||||
|
||||
test_pkt2 = test_pkt.copy()
|
||||
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
|
||||
|
||||
for k in range(64):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
queues.add(pkt.queue)
|
||||
|
||||
assert len(queues) == 4
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
|
||||
|
||||
tb.log.info("Multiple small packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for p in pkts:
|
||||
await tb.driver.interfaces[0].start_xmit(p, 0)
|
||||
|
||||
for k in range(count):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.data == pkts[k]
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
tb.log.info("Multiple large packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for p in pkts:
|
||||
await tb.driver.interfaces[0].start_xmit(p, 0)
|
||||
|
||||
for k in range(count):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.data == pkts[k]
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await RisingEdge(dut.clk_300mhz)
|
||||
await RisingEdge(dut.clk_300mhz)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
|
||||
app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app'))
|
||||
axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl'))
|
||||
axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
|
||||
eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl'))
|
||||
pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
|
||||
|
||||
|
||||
def test_fpga_core(request):
|
||||
dut = "fpga_core"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core_axi.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_port.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_write.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "desc_fetch.v"),
|
||||
os.path.join(rtl_dir, "common", "desc_op_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "event_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "queue_manager.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_fifo.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_fifo.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_engine.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_engine.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_checksum.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_hash.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_checksum.v"),
|
||||
os.path.join(rtl_dir, "common", "rb_drp.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_counter.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_collect.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_dma_if_axi.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_dma_latency.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_scheduler.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_ber.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_ber_ch.v"),
|
||||
os.path.join(eth_rtl_dir, "eth_mac_10g.v"),
|
||||
os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"),
|
||||
os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"),
|
||||
os.path.join(eth_rtl_dir, "lfsr.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_clock.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_perout.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_interconnect.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_reg_if.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_register_rd.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_register_wr.v"),
|
||||
os.path.join(axi_rtl_dir, "arbiter.v"),
|
||||
os.path.join(axi_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_demux.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_register.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_axi.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_axi_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_axi_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
|
||||
parameters = {}
|
||||
|
||||
# Structural configuration
|
||||
parameters['IF_COUNT'] = 2
|
||||
parameters['PORTS_PER_IF'] = 1
|
||||
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
|
||||
parameters['PORT_MASK'] = 0
|
||||
|
||||
# PTP configuration
|
||||
parameters['PTP_CLK_PERIOD_NS_NUM'] = 32
|
||||
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5
|
||||
parameters['PTP_CLOCK_PIPELINE'] = 0
|
||||
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
|
||||
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
|
||||
parameters['PTP_PORT_CDC_PIPELINE'] = 0
|
||||
parameters['PTP_PEROUT_ENABLE'] = 1
|
||||
parameters['PTP_PEROUT_COUNT'] = 1
|
||||
|
||||
# Queue manager configuration
|
||||
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
|
||||
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
|
||||
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 2
|
||||
parameters['TX_QUEUE_INDEX_WIDTH'] = 5
|
||||
parameters['RX_QUEUE_INDEX_WIDTH'] = 5
|
||||
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
|
||||
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
|
||||
parameters['EVENT_QUEUE_PIPELINE'] = 3
|
||||
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
|
||||
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
|
||||
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
|
||||
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
|
||||
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
|
||||
parameters['TDMA_INDEX_WIDTH'] = 6
|
||||
|
||||
# Interface configuration
|
||||
parameters['PTP_TS_ENABLE'] = 1
|
||||
parameters['TX_CPL_FIFO_DEPTH'] = 32
|
||||
parameters['TX_CHECKSUM_ENABLE'] = 1
|
||||
parameters['RX_RSS_ENABLE'] = 1
|
||||
parameters['RX_HASH_ENABLE'] = 1
|
||||
parameters['RX_CHECKSUM_ENABLE'] = 1
|
||||
parameters['TX_FIFO_DEPTH'] = 32768
|
||||
parameters['RX_FIFO_DEPTH'] = 32768
|
||||
parameters['MAX_TX_SIZE'] = 9214
|
||||
parameters['MAX_RX_SIZE'] = 9214
|
||||
parameters['TX_RAM_SIZE'] = 32768
|
||||
parameters['RX_RAM_SIZE'] = 32768
|
||||
|
||||
# Application block configuration
|
||||
parameters['APP_ID'] = 0x00000000
|
||||
parameters['APP_ENABLE'] = 0
|
||||
parameters['APP_CTRL_ENABLE'] = 1
|
||||
parameters['APP_DMA_ENABLE'] = 1
|
||||
parameters['APP_AXIS_DIRECT_ENABLE'] = 1
|
||||
parameters['APP_AXIS_SYNC_ENABLE'] = 1
|
||||
parameters['APP_AXIS_IF_ENABLE'] = 1
|
||||
parameters['APP_STAT_ENABLE'] = 1
|
||||
|
||||
# AXI DMA interface configuration
|
||||
parameters['AXI_DATA_WIDTH'] = 128
|
||||
parameters['AXI_ADDR_WIDTH'] = 40
|
||||
parameters['AXI_ID_WIDTH'] = 4
|
||||
|
||||
# DMA interface configuration
|
||||
parameters['DMA_IMM_ENABLE'] = 0
|
||||
parameters['DMA_IMM_WIDTH'] = 32
|
||||
parameters['DMA_LEN_WIDTH'] = 16
|
||||
parameters['DMA_TAG_WIDTH'] = 16
|
||||
parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
|
||||
parameters['RAM_PIPELINE'] = 2
|
||||
parameters['AXI_DMA_MAX_BURST_LEN'] = 16
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
parameters['AXIL_CTRL_DATA_WIDTH'] = 32
|
||||
parameters['AXIL_CTRL_ADDR_WIDTH'] = 24
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH']
|
||||
parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24
|
||||
|
||||
# Ethernet interface configuration
|
||||
parameters['AXIS_ETH_TX_PIPELINE'] = 0
|
||||
parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 2
|
||||
parameters['AXIS_ETH_TX_TS_PIPELINE'] = 0
|
||||
parameters['AXIS_ETH_RX_PIPELINE'] = 0
|
||||
parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 2
|
||||
|
||||
# Statistics counter subsystem
|
||||
parameters['STAT_ENABLE'] = 1
|
||||
parameters['STAT_DMA_ENABLE'] = 1
|
||||
parameters['STAT_AXI_ENABLE'] = 1
|
||||
parameters['STAT_INC_WIDTH'] = 24
|
||||
parameters['STAT_ID_WIDTH'] = 12
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
Loading…
x
Reference in New Issue
Block a user