diff --git a/README.md b/README.md index 1be9f315c..4e9110555 100644 --- a/README.md +++ b/README.md @@ -41,6 +41,7 @@ Corundum currently supports devices from both Xilinx and Intel, on boards from s * Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095) * Xilinx VCU118 (Xilinx Virtex UltraScale+ XCVU9P) * Xilinx VCU1525 (Xilinx Virtex UltraScale+ XCVU9P) +* Xilinx ZCU102 (Xilinx Zynq UltraScale+ XCZU9EG) * Xilinx ZCU106 (Xilinx Zynq UltraScale+ XCZU7EV) For operation at 10G and 25G, Corundum uses the open source 10G/25G MAC and PHY modules from the verilog-ethernet repository, no extra licenses are required. However, it is possible to use other MAC and/or PHY modules. diff --git a/docs/source/devicelist.rst b/docs/source/devicelist.rst index 107c34462..2c0f643cb 100644 --- a/docs/source/devicelist.rst +++ b/docs/source/devicelist.rst @@ -177,6 +177,7 @@ This section details SoC targets, which interface with CPU cores on the same dev ============ ================= ==================== ========== Manufacturer Board FPGA Board ID ============ ================= ==================== ========== + Xilinx ZCU102 XCZU9EG-2FFVB1156E 0x10ee9066 Xilinx ZCU106 XCZU7EV-2FFVC1156E 0x10ee906a ============ ================= ==================== ========== @@ -185,6 +186,7 @@ This section details SoC targets, which interface with CPU cores on the same dev ================= ========= ========== =============================== ===== Board PCIe IF Network IF DDR HBM ================= ========= ========== =============================== ===== + ZCU102 \- 4x SFP+ 2 GB DDR4 2400 (256M x64) \- ZCU106 Gen 3 x4 2x SFP+ 2 GB DDR4 2400 (256M x64) \- ================= ========= ========== =============================== ===== @@ -193,6 +195,7 @@ This section details SoC targets, which interface with CPU cores on the same dev ================= ============ ============ ========== Board I2C :sup:`1` MAC :sup:`2` FW update ================= ============ ============ ========== + ZCU102 Y Y :sup:`3` N ZCU106 Y Y :sup:`3` N ================= ============ ============ ========== @@ -205,5 +208,6 @@ This section details SoC targets, which interface with CPU cores on the same dev ================= ========================= ==== ======= ==== ===== Board Design IFxP RXQ/TXQ MAC Sched ================= ========================= ==== ======= ==== ===== + ZCU102 mqnic/fpga/fpga 2x1 32/32 10G RR ZCU106 mqnic/fpga_zynqmp/fpga 2x1 32/32 10G RR ================= ========================= ==== ======= ==== ===== diff --git a/docs/source/index.rst b/docs/source/index.rst index f61416d85..faba24635 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -33,6 +33,7 @@ Corundum currently supports devices from both Xilinx and Intel, on boards from s * Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095) * Xilinx VCU118 (Xilinx Virtex UltraScale+ XCVU9P) * Xilinx VCU1525 (Xilinx Virtex UltraScale+ XCVU9P) +* Xilinx ZCU102 (Xilinx Zynq UltraScale+ XCZU9EG) * Xilinx ZCU106 (Xilinx Zynq UltraScale+ XCZU7EV) Publications diff --git a/fpga/mqnic/ZCU102/fpga/Makefile b/fpga/mqnic/ZCU102/fpga/Makefile new file mode 100644 index 000000000..f504bd06f --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/Makefile @@ -0,0 +1,25 @@ +# Targets +TARGETS:= + +# Subdirectories +SUBDIRS = fpga +SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) + +# Rules +.PHONY: all +all: $(SUBDIRS) $(TARGETS) + +.PHONY: $(SUBDIRS) +$(SUBDIRS): + cd $@ && $(MAKE) + +.PHONY: $(SUBDIRS_CLEAN) +$(SUBDIRS_CLEAN): + cd $(@:.clean=) && $(MAKE) clean + +.PHONY: clean +clean: $(SUBDIRS_CLEAN) + -rm -rf $(TARGETS) + +program: + #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit diff --git a/fpga/mqnic/ZCU102/fpga/README.md b/fpga/mqnic/ZCU102/fpga/README.md new file mode 100644 index 000000000..32e371f91 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/README.md @@ -0,0 +1,31 @@ +# Corundum mqnic for ZCU102 using ZynqMP PS as host system + +## Introduction + +This design targets the Xilinx ZCU102 FPGA board. The host system of the NIC is +the Zynq US+ MPSoC. + +FPGA: xczu9eg-ffvb1156-2-e +PHY: 10G BASE-R PHY IP core and internal GTH transceiver + +## How to build + +Run make in this directory to build the bitstream and the .xsa +file. Ensure that the Xilinx Vivado toolchain components are in PATH. + +Then change into sub-directory ps/petalinux/ and build the PetaLinux project. +Ensure that the Xilinx PetaLinux toolchain components are in PATH. + + make -C ps/petalinux/ build-boot + +## How to test + +Copy the following, resulting files of building the PetaLinux project onto an +SDcard suitable for then booting the ZCU102 in SDcard boot mode. + + ps/petalinux/images/linux/: + BOOT.BIN + boot.scr + Image + system.dtb + rootfs.cpio.gz.u-boot diff --git a/fpga/mqnic/ZCU102/fpga/app b/fpga/mqnic/ZCU102/fpga/app new file mode 120000 index 000000000..4d46690fb --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/app @@ -0,0 +1 @@ +../../../app/ \ No newline at end of file diff --git a/fpga/mqnic/ZCU102/fpga/common/vivado.mk b/fpga/mqnic/ZCU102/fpga/common/vivado.mk new file mode 100644 index 000000000..5440c7a49 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/common/vivado.mk @@ -0,0 +1,129 @@ +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - space-separated list of source files +# INC_FILES - space-separated list of include files +# XDC_FILES - space-separated list of timing constraint files +# XCI_FILES - space-separated list of IP XCI files +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: fpga vivado tmpclean clean distclean + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include ../$(CONFIG) + +SYN_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(SYN_FILES))) $(filter /% ./%,$(SYN_FILES)) +INC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(INC_FILES))) $(filter /% ./%,$(INC_FILES)) +XCI_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XCI_FILES))) $(filter /% ./%,$(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(IP_TCL_FILES))) $(filter /% ./%,$(IP_TCL_FILES)) +CONFIG_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(CONFIG_TCL_FILES))) $(filter /% ./%,$(CONFIG_TCL_FILES)) + +ifdef XDC_FILES + XDC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XDC_FILES))) $(filter /% ./%,$(XDC_FILES)) +else + XDC_FILES_REL = $(FPGA_TOP).xdc +endif + +################################################################### +# Main Targets +# +# all: build everything +# clean: remove output files and project files +################################################################### + +all: fpga + +fpga: $(FPGA_TOP).bit + +vivado: $(FPGA_TOP).xpr + vivado $(FPGA_TOP).xpr + +tmpclean:: + -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean:: tmpclean + -rm -rf *.bit *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + +distclean:: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file +create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $(FPGA_TOP)" > $@ + echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ + echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ + for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +update_config.tcl: $(CONFIG_TCL_FILES_REL) + echo "open_project -quiet $(FPGA_TOP).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(FPGA_TOP).xpr: create_project.tcl update_config.tcl + vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) + +# synthesis run +%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) $(CONFIG_TCL_FILES_REL) + echo "open_project $*.xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp + echo "open_project $*.xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# bit file +%.bit: %.runs/impl_1/%_routed.dcp + echo "open_project $*.xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force $*.runs/impl_1/$*.bit" >> generate_bit.tcl + echo "write_hw_platform -fixed -force -include_bit $*.xsa" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + ln -f -s $*.runs/impl_1/$*.bit . + mkdir -p rev + EXT=bit; COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.$$EXT ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp $*.bit rev/$*_rev$$COUNT.bit; \ + cp $*.xsa rev/$*_rev$$COUNT.xsa; \ + echo "Output: rev/$*_rev$$COUNT.$$EXT"; diff --git a/fpga/mqnic/ZCU102/fpga/fpga.xdc b/fpga/mqnic/ZCU102/fpga/fpga.xdc new file mode 100644 index 000000000..9c9abf58c --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/fpga.xdc @@ -0,0 +1,109 @@ +# XDC constraints for the Xilinx ZCU102 board +# part: xczu9eg-ffvb1156-2-e + +# General configuration +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] + +# System clocks +# 125 MHz +set_property -dict {LOC G21 IOSTANDARD LVDS_25} [get_ports clk_125mhz_p] +set_property -dict {LOC F21 IOSTANDARD LVDS_25} [get_ports clk_125mhz_n] +create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p] + +# LEDs +set_property -dict {LOC AG14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[0]}] +set_property -dict {LOC AF13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[1]}] +set_property -dict {LOC AE13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[2]}] +set_property -dict {LOC AJ14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[3]}] +set_property -dict {LOC AJ15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[4]}] +set_property -dict {LOC AH13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[5]}] +set_property -dict {LOC AH14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[6]}] +set_property -dict {LOC AL12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[7]}] + +set_false_path -to [get_ports {led[*]}] +set_output_delay 0 [get_ports {led[*]}] + +# Reset button +#set_property -dict {LOC AM13 IOSTANDARD LVCMOS33} [get_ports reset] + +#set_false_path -from [get_ports {reset}] +#set_input_delay 0 [get_ports {reset}] + +# Push buttons +set_property -dict {LOC AG15 IOSTANDARD LVCMOS33} [get_ports btnu] +set_property -dict {LOC AF15 IOSTANDARD LVCMOS33} [get_ports btnl] +set_property -dict {LOC AE15 IOSTANDARD LVCMOS33} [get_ports btnd] +set_property -dict {LOC AE14 IOSTANDARD LVCMOS33} [get_ports btnr] +set_property -dict {LOC AG13 IOSTANDARD LVCMOS33} [get_ports btnc] + +set_false_path -from [get_ports {btnu btnl btnd btnr btnc}] +set_input_delay 0 [get_ports {btnu btnl btnd btnr btnc}] + +# DIP switches +set_property -dict {LOC AN14 IOSTANDARD LVCMOS33} [get_ports {sw[0]}] +set_property -dict {LOC AP14 IOSTANDARD LVCMOS33} [get_ports {sw[1]}] +set_property -dict {LOC AM14 IOSTANDARD LVCMOS33} [get_ports {sw[2]}] +set_property -dict {LOC AN13 IOSTANDARD LVCMOS33} [get_ports {sw[3]}] +set_property -dict {LOC AN12 IOSTANDARD LVCMOS33} [get_ports {sw[4]}] +set_property -dict {LOC AP12 IOSTANDARD LVCMOS33} [get_ports {sw[5]}] +set_property -dict {LOC AL13 IOSTANDARD LVCMOS33} [get_ports {sw[6]}] +set_property -dict {LOC AK13 IOSTANDARD LVCMOS33} [get_ports {sw[7]}] + +set_false_path -from [get_ports {sw[*]}] +set_input_delay 0 [get_ports {sw[*]}] + +# UART +#set_property -dict {LOC F13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_txd] +#set_property -dict {LOC E13 IOSTANDARD LVCMOS33} [get_ports uart_rxd] +#set_property -dict {LOC D12 IOSTANDARD LVCMOS33} [get_ports uart_rts] +#set_property -dict {LOC E12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_cts] + +#set_false_path -to [get_ports {uart_txd uart_cts}] +#set_output_delay 0 [get_ports {uart_txd uart_cts}] +#set_false_path -from [get_ports {uart_rxd uart_rts}] +#set_input_delay 0 [get_ports {uart_rxd uart_rts}] + +# I2C interfaces +#set_property -dict {LOC J10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c0_scl] +#set_property -dict {LOC J11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c0_sda] +#set_property -dict {LOC K20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c1_scl] +#set_property -dict {LOC L20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports i2c1_sda] + +#set_false_path -to [get_ports {i2c1_sda i2c1_scl}] +#set_output_delay 0 [get_ports {i2c1_sda i2c1_scl}] +#set_false_path -from [get_ports {i2c1_sda i2c1_scl}] +#set_input_delay 0 [get_ports {i2c1_sda i2c1_scl}] + +# SFP+ Interface +set_property -dict {LOC D2 } [get_ports sfp0_rx_p] ;# MGTHRXP0_230 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3 +set_property -dict {LOC D1 } [get_ports sfp0_rx_n] ;# MGTHRXN0_230 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3 +set_property -dict {LOC E4 } [get_ports sfp0_tx_p] ;# MGTHTXP0_230 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3 +set_property -dict {LOC E3 } [get_ports sfp0_tx_n] ;# MGTHTXN0_230 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3 +set_property -dict {LOC C4 } [get_ports sfp1_rx_p] ;# MGTHRXP1_230 GTHE4_CHANNEL_X1Y13 / GTHE4_COMMON_X1Y3 +set_property -dict {LOC C3 } [get_ports sfp1_rx_n] ;# MGTHRXN1_230 GTHE4_CHANNEL_X1Y13 / GTHE4_COMMON_X1Y3 +set_property -dict {LOC D6 } [get_ports sfp1_tx_p] ;# MGTHTXP1_230 GTHE4_CHANNEL_X1Y13 / GTHE4_COMMON_X1Y3 +set_property -dict {LOC D5 } [get_ports sfp1_tx_n] ;# MGTHTXN1_230 GTHE4_CHANNEL_X1Y13 / GTHE4_COMMON_X1Y3 +set_property -dict {LOC B2 } [get_ports sfp2_rx_p] ;# MGTHRXP2_230 GTHE4_CHANNEL_X1Y14 / GTHE4_COMMON_X1Y3 +set_property -dict {LOC B1 } [get_ports sfp2_rx_n] ;# MGTHRXN2_230 GTHE4_CHANNEL_X1Y14 / GTHE4_COMMON_X1Y3 +set_property -dict {LOC B6 } [get_ports sfp2_tx_p] ;# MGTHTXP2_230 GTHE4_CHANNEL_X1Y14 / GTHE4_COMMON_X1Y3 +set_property -dict {LOC B5 } [get_ports sfp2_tx_n] ;# MGTHTXN2_230 GTHE4_CHANNEL_X1Y14 / GTHE4_COMMON_X1Y3 +set_property -dict {LOC A4 } [get_ports sfp3_rx_p] ;# MGTHRXP3_230 GTHE4_CHANNEL_X1Y15 / GTHE4_COMMON_X1Y3 +set_property -dict {LOC A3 } [get_ports sfp3_rx_n] ;# MGTHRXN3_230 GTHE4_CHANNEL_X1Y15 / GTHE4_COMMON_X1Y3 +set_property -dict {LOC A8 } [get_ports sfp3_tx_p] ;# MGTHTXP3_230 GTHE4_CHANNEL_X1Y15 / GTHE4_COMMON_X1Y3 +set_property -dict {LOC A7 } [get_ports sfp3_tx_n] ;# MGTHTXN3_230 GTHE4_CHANNEL_X1Y15 / GTHE4_COMMON_X1Y3 +set_property -dict {LOC C8 } [get_ports sfp_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U56 SI570 via U51 SI53340 +set_property -dict {LOC C7 } [get_ports sfp_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U56 SI570 via U51 SI53340 +#set_property -dict {LOC B10 } [get_ports sfp_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U20 CKOUT2 SI5328 +#set_property -dict {LOC B9 } [get_ports sfp_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U20 CKOUT2 SI5328 +#set_property -dict {LOC R10 IOSTANDARD LVDS} [get_ports sfp_recclk_p] ;# to U20 CKIN1 SI5328 +#set_property -dict {LOC R9 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to U20 CKIN1 SI5328 +set_property -dict {LOC A12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports sfp0_tx_disable_b] +set_property -dict {LOC A13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports sfp1_tx_disable_b] +set_property -dict {LOC B13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports sfp2_tx_disable_b] +set_property -dict {LOC C13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports sfp3_tx_disable_b] + +# 156.25 MHz MGT reference clock +create_clock -period 6.400 -name sfp_mgt_refclk_0 [get_ports sfp_mgt_refclk_0_p] + +set_false_path -to [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b sfp2_tx_disable_b sfp3_tx_disable_b}] +set_output_delay 0 [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b sfp2_tx_disable_b sfp3_tx_disable_b}] diff --git a/fpga/mqnic/ZCU102/fpga/fpga/.gitignore b/fpga/mqnic/ZCU102/fpga/fpga/.gitignore new file mode 100644 index 000000000..1d20931e2 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/fpga/.gitignore @@ -0,0 +1,3 @@ +* +!/config.tcl +!/Makefile diff --git a/fpga/mqnic/ZCU102/fpga/fpga/Makefile b/fpga/mqnic/ZCU102/fpga/fpga/Makefile new file mode 100644 index 000000000..fc73e734c --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/fpga/Makefile @@ -0,0 +1,136 @@ + +# FPGA settings +FPGA_PART = xczu9eg-ffvb1156-2-e +FPGA_TOP = fpga +FPGA_ARCH = zynquplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/debounce_switch.v +SYN_FILES += rtl/common/mqnic_core_axi.v +SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_port_tx.v +SYN_FILES += rtl/common/mqnic_port_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v +SYN_FILES += rtl/common/mqnic_l2_egress.v +SYN_FILES += rtl/common/mqnic_l2_ingress.v +SYN_FILES += rtl/common/mqnic_rx_queue_map.v +SYN_FILES += rtl/common/mqnic_ptp.v +SYN_FILES += rtl/common/mqnic_ptp_clock.v +SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v +SYN_FILES += rtl/common/cpl_write.v +SYN_FILES += rtl/common/cpl_op_mux.v +SYN_FILES += rtl/common/desc_fetch.v +SYN_FILES += rtl/common/desc_op_mux.v +SYN_FILES += rtl/common/event_mux.v +SYN_FILES += rtl/common/queue_manager.v +SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v +SYN_FILES += rtl/common/tx_engine.v +SYN_FILES += rtl/common/rx_engine.v +SYN_FILES += rtl/common/tx_checksum.v +SYN_FILES += rtl/common/rx_hash.v +SYN_FILES += rtl/common/rx_checksum.v +SYN_FILES += rtl/common/rb_drp.v +SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_wrapper.v +SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_quad_wrapper.v +SYN_FILES += rtl/common/stats_counter.v +SYN_FILES += rtl/common/stats_collect.v +SYN_FILES += rtl/common/stats_dma_if_axi.v +SYN_FILES += rtl/common/stats_dma_latency.v +SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v +SYN_FILES += rtl/common/tx_scheduler_rr.v +SYN_FILES += rtl/common/tdma_scheduler.v +SYN_FILES += rtl/common/tdma_ber.v +SYN_FILES += rtl/common/tdma_ber_ch.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/ptp_clock.v +SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_perout.v +SYN_FILES += lib/axi/rtl/axil_interconnect.v +SYN_FILES += lib/axi/rtl/axil_crossbar.v +SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v +SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v +SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v +SYN_FILES += lib/axi/rtl/axil_reg_if.v +SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v +SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v +SYN_FILES += lib/axi/rtl/axil_register_rd.v +SYN_FILES += lib/axi/rtl/axil_register_wr.v +SYN_FILES += lib/axi/rtl/arbiter.v +SYN_FILES += lib/axi/rtl/priority_encoder.v +SYN_FILES += lib/axis/rtl/axis_adapter.v +SYN_FILES += lib/axis/rtl/axis_arb_mux.v +SYN_FILES += lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v +SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v +SYN_FILES += lib/axis/rtl/axis_register.v +SYN_FILES += lib/axis/rtl/sync_reset.v +SYN_FILES += lib/pcie/rtl/dma_if_axi.v +SYN_FILES += lib/pcie/rtl/dma_if_axi_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_axi_wr.v +SYN_FILES += lib/pcie/rtl/dma_if_mux.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v +SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v +SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v +SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v +SYN_FILES += lib/pcie/rtl/dma_psdpram.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl +XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl +XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl + +# IP +IP_TCL_FILES = ip/zynq_ps.tcl +IP_TCL_FILES += ip/eth_xcvr_gth.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl diff --git a/fpga/mqnic/ZCU102/fpga/fpga/config.tcl b/fpga/mqnic/ZCU102/fpga/fpga/config.tcl new file mode 100644 index 000000000..543cfeea1 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/fpga/config.tcl @@ -0,0 +1,199 @@ +# Copyright 2021, The Regents of the University of California. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +# OF SUCH DAMAGE. +# +# The views and conclusions contained in the software and documentation are those +# of the authors and should not be interpreted as representing official policies, +# either expressed or implied, of The Regents of the University of California. + +set params [dict create] + +# collect build information +set build_date [clock seconds] +set git_hash 00000000 +set git_tag "" + +if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } { + puts "Error running git or project not under version control" +} + +if { [catch {set git_tag [exec git describe --tags HEAD]}] } { + puts "Error running git, project not under version control, or no tag found" +} + +puts "Build date: ${build_date}" +puts "Git hash: ${git_hash}" +puts "Git tag: ${git_tag}" + +if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } { + puts "Failed to extract version from git tag" + set tag_ver 0.0.1 +} + +puts "Tag version: ${tag_ver}" + +# FW and board IDs +set fpga_id [expr 0x4738093] +set fw_id [expr 0x00000000] +set fw_ver $tag_ver +set board_vendor_id [expr 0x10ee] +set board_device_id [expr 0x9066] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# FW ID block +dict set params FPGA_ID [format "32'h%08x" $fpga_id] +dict set params FW_ID [format "32'h%08x" $fw_id] +dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0] +dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] +dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0] +dict set params BUILD_DATE "32'd${build_date}" +dict set params GIT_HASH "32'h${git_hash}" +dict set params RELEASE_INFO [format "32'h%08x" $release_info] + +# Board configuration +dict set params TDMA_BER_ENABLE "0" + +# Structural configuration +dict set params IF_COUNT "2" +dict set params PORTS_PER_IF "1" +dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] +dict set params PORT_MASK "0" + +# PTP configuration +dict set params PTP_CLOCK_PIPELINE "0" +dict set params PTP_CLOCK_CDC_PIPELINE "0" +dict set params PTP_PORT_CDC_PIPELINE "0" +dict set params PTP_PEROUT_ENABLE "1" +dict set params PTP_PEROUT_COUNT "1" + +# Queue manager configuration +dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" +dict set params TX_QUEUE_OP_TABLE_SIZE "32" +dict set params RX_QUEUE_OP_TABLE_SIZE "32" +dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] +dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] +dict set params EVENT_QUEUE_INDEX_WIDTH "2" +dict set params TX_QUEUE_INDEX_WIDTH "5" +dict set params RX_QUEUE_INDEX_WIDTH "5" +dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] +dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] +dict set params EVENT_QUEUE_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] +dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] +dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] +dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] + +# TX and RX engine configuration +dict set params TX_DESC_TABLE_SIZE "32" +dict set params RX_DESC_TABLE_SIZE "32" + +# Scheduler configuration +dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] +dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE] +dict set params TDMA_INDEX_WIDTH "6" + +# Interface configuration +dict set params PTP_TS_ENABLE "1" +dict set params TX_CPL_FIFO_DEPTH "32" +dict set params TX_CHECKSUM_ENABLE "1" +dict set params RX_RSS_ENABLE "1" +dict set params RX_HASH_ENABLE "1" +dict set params RX_CHECKSUM_ENABLE "1" +dict set params TX_FIFO_DEPTH "32768" +dict set params RX_FIFO_DEPTH "32768" +dict set params MAX_TX_SIZE "9214" +dict set params MAX_RX_SIZE "9214" +dict set params TX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "32768" + +# Application block configuration +dict set params APP_ID "32'h00000000" +dict set params APP_ENABLE "0" +dict set params APP_CTRL_ENABLE "1" +dict set params APP_DMA_ENABLE "1" +dict set params APP_AXIS_DIRECT_ENABLE "1" +dict set params APP_AXIS_SYNC_ENABLE "1" +dict set params APP_AXIS_IF_ENABLE "1" +dict set params APP_STAT_ENABLE "1" + +# AXI DMA interface configuration +open_bd_design [get_files zynq_ps.bd] +set s_axi_dma [get_bd_intf_ports s_axi_dma] +dict set params AXI_DATA_WIDTH [get_property CONFIG.DATA_WIDTH $s_axi_dma] +# dict set params AXI_ADDR_WIDTH [get_property CONFIG.ADDR_WIDTH $s_axi_dma] +dict set params AXI_ADDR_WIDTH 64 +dict set params AXI_ID_WIDTH [get_property CONFIG.ID_WIDTH $s_axi_dma] + +# DMA interface configuration +dict set params DMA_IMM_ENABLE "0" +dict set params DMA_IMM_WIDTH "32" +dict set params DMA_LEN_WIDTH "16" +dict set params DMA_TAG_WIDTH "16" +dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))] +dict set params RAM_PIPELINE "2" +# NOTE: Querying the BD top-level interface port (or even the ZynqMP's interface +# pin) yields 256 for the maximum burst length, instead of 16, which is +# the actually supported length (due to ZynqMP using AXI3 internally). +#dict set params AXI_DMA_MAX_BURST_LEN [get_property CONFIG.MAX_BURST_LENGTH $s_axi_dma] +dict set params AXI_DMA_MAX_BURST_LEN "16" + +# AXI lite interface configuration (control) +set m_axil_ctrl [get_bd_intf_ports m_axil_ctrl] +dict set params AXIL_CTRL_DATA_WIDTH [get_property CONFIG.DATA_WIDTH $m_axil_ctrl] +dict set params AXIL_CTRL_ADDR_WIDTH 24 + +# AXI lite interface configuration (application control) +set m_axil_app_ctrl [get_bd_intf_ports m_axil_app_ctrl] +dict set params AXIL_APP_CTRL_DATA_WIDTH [get_property CONFIG.DATA_WIDTH $m_axil_app_ctrl] +dict set params AXIL_APP_CTRL_ADDR_WIDTH 24 + +# Interrupt configuration +set irq [get_bd_ports pl_ps_irq0] +dict set params IRQ_COUNT [get_property CONFIG.PortWidth $irq] +close_bd_design [get_bd_designs zynq_ps] +dict set params IRQ_STRETCH "10" + +# Ethernet interface configuration +dict set params AXIS_ETH_TX_PIPELINE "0" +dict set params AXIS_ETH_TX_FIFO_PIPELINE "2" +dict set params AXIS_ETH_TX_TS_PIPELINE "0" +dict set params AXIS_ETH_RX_PIPELINE "0" +dict set params AXIS_ETH_RX_FIFO_PIPELINE "2" + +# Statistics counter subsystem +dict set params STAT_ENABLE "1" +dict set params STAT_DMA_ENABLE "1" +dict set params STAT_AXI_ENABLE "1" +dict set params STAT_INC_WIDTH "24" +dict set params STAT_ID_WIDTH "12" + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +# set_property generic $param_list [current_fileset] +set_property generic $param_list [get_filesets sources_1] diff --git a/fpga/mqnic/ZCU102/fpga/ip/eth_xcvr_gth.tcl b/fpga/mqnic/ZCU102/fpga/ip/eth_xcvr_gth.tcl new file mode 100644 index 000000000..3209d5d72 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ip/eth_xcvr_gth.tcl @@ -0,0 +1,129 @@ +# Copyright 2022, The Regents of the University of California. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +# OF SUCH DAMAGE. +# +# The views and conclusions contained in the software and documentation are those +# of the authors and should not be interpreted as representing official policies, +# either expressed or implied, of The Regents of the University of California. + +set base_name {eth_xcvr_gth} + +set preset {GTH-10GBASE-R} + +set freerun_freq {125} +set line_rate {10.3125} +set sec_line_rate {0} +set refclk_freq {156.25} +set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set user_data_width {64} +set int_data_width {32} +set rx_eq_mode {DFE} +set extra_ports [list] +set extra_pll_ports [list] +# DRP connections +lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out +lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out +# PLL reset and power down +lappend extra_pll_ports qpll0reset_in qpll1reset_in +lappend extra_pll_ports qpll0pd_in qpll1pd_in +# PLL clocking +lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out +lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# channel reset +lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out +lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out +# channel power down +lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in +# channel clock selection +lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in +# channel polarity +lappend extra_ports txpolarity_in rxpolarity_in +# channel TX driver +lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in +# channel CDR +lappend extra_ports rxcdrlock_out rxcdrhold_in +# channel EQ +lappend extra_ports rxlpmen_in +# channel digital monitor +lappend extra_ports dmonitorout_out +# channel PRBS +lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out +# channel eye scan +lappend extra_ports eyescandataerror_out +# channel loopback +lappend extra_ports loopback_in + +set config [dict create] + +dict set config TX_LINE_RATE $line_rate +dict set config TX_REFCLK_FREQUENCY $refclk_freq +dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn +dict set config TX_USER_DATA_WIDTH $user_data_width +dict set config TX_INT_DATA_WIDTH $int_data_width +dict set config RX_LINE_RATE $line_rate +dict set config RX_REFCLK_FREQUENCY $refclk_freq +dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn +dict set config RX_USER_DATA_WIDTH $user_data_width +dict set config RX_INT_DATA_WIDTH $int_data_width +dict set config RX_EQ_MODE $rx_eq_mode +if {$sec_line_rate != 0} { + dict set config SECONDARY_QPLL_ENABLE true + dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn + dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq +} else { + dict set config SECONDARY_QPLL_ENABLE false +} +dict set config ENABLE_OPTIONAL_PORTS $extra_ports +dict set config LOCATE_COMMON {CORE} +dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} +dict set config LOCATE_TX_USER_CLOCKING {CORE} +dict set config LOCATE_RX_USER_CLOCKING {CORE} +dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} +dict set config FREERUN_FREQUENCY $freerun_freq +dict set config DISABLE_LOC_XDC {1} + +proc create_gtwizard_ip {name preset config} { + create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name + set ip [get_ips $name] + set_property CONFIG.preset $preset $ip + set config_list {} + dict for {name value} $config { + lappend config_list "CONFIG.${name}" $value + } + set_property -dict $config_list $ip +} + +# variant with channel and common +dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports] +dict set config LOCATE_COMMON {CORE} + +create_gtwizard_ip "${base_name}_full" $preset $config + +# variant with channel only +dict set config ENABLE_OPTIONAL_PORTS $extra_ports +dict set config LOCATE_COMMON {EXAMPLE_DESIGN} + +create_gtwizard_ip "${base_name}_channel" $preset $config diff --git a/fpga/mqnic/ZCU102/fpga/ip/zynq_ps.tcl b/fpga/mqnic/ZCU102/fpga/ip/zynq_ps.tcl new file mode 100644 index 000000000..e63d21431 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ip/zynq_ps.tcl @@ -0,0 +1,215 @@ +# Copyright 2022, The Regents of the University of California. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +# OF SUCH DAMAGE. +# +# The views and conclusions contained in the software and documentation are those +# of the authors and should not be interpreted as representing official policies, +# either expressed or implied, of The Regents of the University of California. + +# create block design +create_bd_design "zynq_ps" + +# Create blocks + +# Zynq PS +set zynq_ultra_ps [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e zynq_ultra_ps ] +set_property -dict [list \ + CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \ + CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN 1 \ + CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \ + CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \ + CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \ + CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \ + CONFIG.PSU__DDRC__T_RC {46.5} \ + CONFIG.PSU__DDRC__T_FAW {21.0} \ + CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ + CONFIG.PSU__DDRC__FREQ_MHZ {1067} \ + CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__PMU__GPI0__ENABLE {1} \ + CONFIG.PSU__PMU__GPI1__ENABLE {0} \ + CONFIG.PSU__PMU__GPI2__ENABLE {0} \ + CONFIG.PSU__PMU__GPI3__ENABLE {0} \ + CONFIG.PSU__PMU__GPI4__ENABLE {0} \ + CONFIG.PSU__PMU__GPI5__ENABLE {0} \ + CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \ + CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \ + CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \ + CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \ + CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \ + CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \ + CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \ + CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \ + CONFIG.PSU__SD1__GRP_WP__ENABLE {1} \ + CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ + CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USE__M_AXI_GP0 {1} \ + CONFIG.PSU__MAXIGP0__DATA_WIDTH {32} \ + CONFIG.PSU__USE__M_AXI_GP1 {0} \ + CONFIG.PSU__USE__M_AXI_GP2 {0} \ + CONFIG.PSU__USE__S_AXI_GP0 {1} \ + CONFIG.PSU__USE__IRQ0 {1} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {300} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ +] $zynq_ultra_ps + +# control AXI interconnect +set axi_interconnect_ctrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_interconnect_ctrl ] + +# reset +set proc_sys_reset [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset proc_sys_reset ] + +# Create connections + +# Clock +set pl_clk0 [get_bd_pins $zynq_ultra_ps/pl_clk0] +make_bd_pins_external $pl_clk0 +set_property name pl_clk0 [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_clk0]] +set pl_clk0_port [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_clk0]] + +connect_bd_net $pl_clk0 [get_bd_pins $zynq_ultra_ps/maxihpm0_fpd_aclk] +connect_bd_net $pl_clk0 [get_bd_pins $zynq_ultra_ps/saxihpc0_fpd_aclk] +connect_bd_net $pl_clk0 [get_bd_pins $proc_sys_reset/slowest_sync_clk] +connect_bd_net $pl_clk0 [get_bd_pins $axi_interconnect_ctrl/ACLK] +connect_bd_net $pl_clk0 [get_bd_pins $axi_interconnect_ctrl/S00_ACLK] +connect_bd_net $pl_clk0 [get_bd_pins $axi_interconnect_ctrl/M00_ACLK] +connect_bd_net $pl_clk0 [get_bd_pins $axi_interconnect_ctrl/M01_ACLK] + +set pl_clk0_busif [list] + +# Reset +set pl_resetn0 [get_bd_pins $zynq_ultra_ps/pl_resetn0] +connect_bd_net $pl_resetn0 [get_bd_pins $proc_sys_reset/ext_reset_in] + +set pl_reset [get_bd_pins $proc_sys_reset/peripheral_reset] +make_bd_pins_external $pl_reset +set_property name pl_reset [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_reset]] + +set interconnect_aresetn [get_bd_pins $proc_sys_reset/interconnect_aresetn] +connect_bd_net $interconnect_aresetn [get_bd_pins $axi_interconnect_ctrl/ARESETN] +connect_bd_net $interconnect_aresetn [get_bd_pins $axi_interconnect_ctrl/S00_ARESETN] +connect_bd_net $interconnect_aresetn [get_bd_pins $axi_interconnect_ctrl/M00_ARESETN] +connect_bd_net $interconnect_aresetn [get_bd_pins $axi_interconnect_ctrl/M01_ARESETN] + +# MMIO +connect_bd_intf_net [get_bd_intf_pins $zynq_ultra_ps/M_AXI_HPM0_FPD] [get_bd_intf_pins $axi_interconnect_ctrl/S00_AXI] + +# Control interface +set m_axil_ctrl_pin [get_bd_intf_pins $axi_interconnect_ctrl/M00_AXI] +make_bd_intf_pins_external $m_axil_ctrl_pin +set_property name m_axil_ctrl [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $m_axil_ctrl_pin]] +set m_axil_ctrl_port [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $m_axil_ctrl_pin]] +set_property -dict [list \ + CONFIG.PROTOCOL AXI4LITE \ + CONFIG.DATA_WIDTH 32 \ + CONFIG.ADDR_WIDTH 24 \ +] $m_axil_ctrl_port +lappend pl_clk0_busif $m_axil_ctrl_port + +# Application control interface +set m_axil_app_ctrl_pin [get_bd_intf_pins $axi_interconnect_ctrl/M01_AXI] +make_bd_intf_pins_external $m_axil_app_ctrl_pin +set_property name m_axil_app_ctrl [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $m_axil_app_ctrl_pin]] +set m_axil_app_ctrl_port [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $m_axil_app_ctrl_pin]] +set_property -dict [list \ + CONFIG.PROTOCOL AXI4LITE \ + CONFIG.DATA_WIDTH 32 \ + CONFIG.ADDR_WIDTH 24 \ +] $m_axil_app_ctrl_port +lappend pl_clk0_busif $m_axil_app_ctrl_port + +# DMA interface +set s_axi_dma_pin [get_bd_intf_pins $zynq_ultra_ps/S_AXI_HPC0_FPD] +make_bd_intf_pins_external $s_axi_dma_pin +set_property name s_axi_dma [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $s_axi_dma_pin]] +set s_axi_dma_port [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $s_axi_dma_pin]] +lappend pl_clk0_busif $s_axi_dma_port + +# IRQ +set pl_ps_irq0 [get_bd_pins $zynq_ultra_ps/pl_ps_irq0] +make_bd_pins_external $pl_ps_irq0 +set_property name pl_ps_irq0 [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_ps_irq0]] +set pl_ps_irq0_port [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_ps_irq0]] +set_property -dict [list \ + CONFIG.PortWidth 8 \ +] $pl_ps_irq0_port + +# Port clock associations +set lst [list] +foreach port $pl_clk0_busif { + lappend lst [get_property name $port] +} +set_property CONFIG.ASSOCIATED_BUSIF [join $lst ":"] $pl_clk0_port + +# Assign addresses +assign_bd_address -target_address_space /s_axi_dma [get_bd_addr_segs $zynq_ultra_ps/SAXIGP0/HPC0_DDR_HIGH] -force +assign_bd_address -target_address_space /s_axi_dma [get_bd_addr_segs $zynq_ultra_ps/SAXIGP0/HPC0_QSPI] -force +assign_bd_address -target_address_space /s_axi_dma [get_bd_addr_segs $zynq_ultra_ps/SAXIGP0/HPC0_DDR_LOW] -force +assign_bd_address -target_address_space /s_axi_dma [get_bd_addr_segs $zynq_ultra_ps/SAXIGP0/HPC0_LPS_OCM] -force + +assign_bd_address -offset 0xA000_0000 -range 16M -target_address_space $zynq_ultra_ps/Data [get_bd_addr_segs $m_axil_ctrl_port/Reg] -force +assign_bd_address -offset 0xA800_0000 -range 16M -target_address_space $zynq_ultra_ps/Data [get_bd_addr_segs $m_axil_app_ctrl_port/Reg] -force + +validate_bd_design + +# Save block design +save_bd_design [current_bd_design] +close_bd_design [current_bd_design] diff --git a/fpga/mqnic/ZCU102/fpga/lib b/fpga/mqnic/ZCU102/fpga/lib new file mode 120000 index 000000000..9512b3d5e --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/lib @@ -0,0 +1 @@ +../../../lib/ \ No newline at end of file diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/.gitignore b/fpga/mqnic/ZCU102/fpga/ps/petalinux/.gitignore new file mode 100644 index 000000000..0b48802db --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/.gitignore @@ -0,0 +1,25 @@ +*/*/config.old +*/*/rootfs_config.old +build/ +images/linux/ +pre-built/linux/ +.petalinux/* +# NOTE: At least since v2020.2 .petalinux/metadata may contain an absolute path +# of the last imported .xsa file! Plus various MD5 sums. Not good for VCS! +# Apparently, the file is NOT needed anymore (re-created on each build instead). +# However the directory .petalinux/ has to exists. +#!.petalinux/metadata +!.petalinux/.gitkeep +*.o +*.jou +*.log +/components/plnx_workspace +/components/yocto + + +# skip any generated .xsa-related files +/project-spec/hw-description/* +!/project-spec/hw-description/metadata + +# Xilinx toolchain intermediate files +/.Xil/ diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/.petalinux/.gitkeep b/fpga/mqnic/ZCU102/fpga/ps/petalinux/.petalinux/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/Makefile b/fpga/mqnic/ZCU102/fpga/ps/petalinux/Makefile new file mode 120000 index 000000000..547316522 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/Makefile @@ -0,0 +1 @@ +../../../../../lib/psmake/petalinux.mk \ No newline at end of file diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/config.project b/fpga/mqnic/ZCU102/fpga/ps/petalinux/config.project new file mode 100644 index 000000000..3d5b67598 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/config.project @@ -0,0 +1,11 @@ +# +# Automatically generated file; DO NOT EDIT. +# PetaLinux SDK Project Configuration +# +CONFIG_PROJECT_ADDITIONAL_COMPONENTS_SEARCH_PATH="" + +# +# Subsystems of the project +# +CONFIG_PROJECT_SUBSYSTEM_LINUX_INSTANCE_LINUX=y +CONFIG_PROJECT_SUBSYSTEMS=y diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/local.mk b/fpga/mqnic/ZCU102/fpga/ps/petalinux/local.mk new file mode 100644 index 000000000..3c36ee770 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/local.mk @@ -0,0 +1,8 @@ +HDF ?= ../../fpga/fpga.xsa + +# shortcut to build PetaLinux project including boot files +build-boot: + $(MAKE) build + $(MAKE) package-boot + +.PHONY: build-boot diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/attributes b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/attributes new file mode 100644 index 000000000..52c333c79 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/attributes @@ -0,0 +1,10 @@ +#Virtual Providers + + + +#defconfigs + +UBOOT_DEFAULT_DEFCONFIG="xilinx_zynqmp_virt_defconfig" + +#atf +CONFIG_SUBSYSTEM_PRELOADED_BL33_BASE="0x8000000" diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/configs/busybox/inetd.conf b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/configs/busybox/inetd.conf new file mode 100644 index 000000000..b7c0bbcd7 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/configs/busybox/inetd.conf @@ -0,0 +1,22 @@ +#/etc/inetd.conf: see inetd(8) for further informations. +# +# Internet server configuration database +# +# If you want to disable an entry so it isn't touched during +# package updates just comment it out with a single '#' character. +# +# +# +#:INTERNAL: Internal services +#echo stream tcp nowait root internal +#echo dgram udp wait root internal +#chargen stream tcp nowait root internal +#chargen dgram udp wait root internal +#discard stream tcp nowait root internal +#discard dgram udp wait root internal +#daytime stream tcp nowait root internal +#daytime dgram udp wait root internal +#time stream tcp nowait root internal +#time dgram udp wait root internal +telnet stream tcp nowait root telnetd telnetd -i +ftp stream tcp nowait root ftpd ftpd -w diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/configs/config b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/configs/config new file mode 100644 index 000000000..3b2ff9b46 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/configs/config @@ -0,0 +1,301 @@ +# +# Automatically generated file; DO NOT EDIT. +# misc/config System Configuration +# +CONFIG_SUBSYSTEM_TYPE_LINUX=y +CONFIG_SYSTEM_ZYNQMP=y +CONFIG_SUBSYSTEM_VARIANT_ZYNQMPEG=y + +# +# Linux Components Selection +# +CONFIG_SUBSYSTEM_COMPONENT_DEVICE__TREE_NAME_DEVICE__TREE__GENERATOR=y +# CONFIG_SUBSYSTEM_COMPONENT_IMG_SEL is not set +CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_FSBL=y +CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_NAME_ZYNQMP_FSBL=y +CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_PS_INIT=y +CONFIG_SUBSYSTEM_COMPONENT_PMU_FIRMWARE=y +CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_U__BOOT__XLNX=y +# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_REMOTE is not set +# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_EXT__LOCAL__SRC is not set +CONFIG_SUBSYSTEM_COMPONENT_ARM__TRUSTED__FIRMWARE_NAME_ARM__TRUSTED__FIRMWARE=y +# CONFIG_SUBSYSTEM_COMPONENT_ARM__TRUSTED__FIRMWARE_NAME_REMOTE is not set +# CONFIG_SUBSYSTEM_COMPONENT_ARM__TRUSTED__FIRMWARE_NAME_EXT__LOCAL__SRC is not set +CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_LINUX__XLNX=y +# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_REMOTE is not set +# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_EXT__LOCAL__SRC is not set + +# +# Auto Config Settings +# +CONFIG_SUBSYSTEM_AUTOCONFIG_DEVICE__TREE=y +# CONFIG_SUBSYSTEM_DEVICE_TREE_MANUAL_INCLUDE is not set +CONFIG_SUBSYSTEM_HARDWARE_AUTO=y +CONFIG_SUBSYSTEM_PROCESSOR0_IP_NAME="psu_cortexa53_0" +CONFIG_SUBSYSTEM_PROCESSOR_psu_cortexa53_0_SELECT=y +CONFIG_SUBSYSTEM_ARCH_AARCH64=y + +# +# Memory Settings +# +CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_SELECT=y +# CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_1_BANKLESS_SELECT is not set +# CONFIG_SUBSYSTEM_MEMORY_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_BASEADDR=0x0 +CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_SIZE=0x80000000 +CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_KERNEL_BASEADDR=0x0 +CONFIG_SUBSYSTEM_MEMORY_PSU_DDR_0_BANKLESS_U__BOOT_TEXTBASE_OFFSET=0x100000 +CONFIG_SUBSYSTEM_MEMORY_IP_NAME="PSU_DDR_0" + +# +# Serial Settings +# +# CONFIG_SUBSYSTEM_PMUFW_SERIAL_PSU_UART_1_SELECT is not set +CONFIG_SUBSYSTEM_PMUFW_SERIAL_PSU_UART_0_SELECT=y +# CONFIG_SUBSYSTEM_PMUFW_SERIAL_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_FSBL_SERIAL_PSU_UART_1_SELECT is not set +CONFIG_SUBSYSTEM_FSBL_SERIAL_PSU_UART_0_SELECT=y +# CONFIG_SUBSYSTEM_FSBL_SERIAL_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_ATF_SERIAL_PSU_UART_1_SELECT is not set +CONFIG_SUBSYSTEM_ATF_SERIAL_PSU_UART_0_SELECT=y +# CONFIG_SUBSYSTEM_ATF_SERIAL_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_SELECT is not set +CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_SELECT=y +# CONFIG_SUBSYSTEM_SERIAL_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_600 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_9600 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_28800 is not set +CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_115200=y +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_230400 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_460800 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_1_BAUDRATE_921600 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_600 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_9600 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_28800 is not set +CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_115200=y +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_230400 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_460800 is not set +# CONFIG_SUBSYSTEM_SERIAL_PSU_UART_0_BAUDRATE_921600 is not set +CONFIG_SUBSYSTEM_SERIAL_PMUFW_IP_NAME="psu_uart_0" +CONFIG_SUBSYSTEM_SERIAL_FSBL_IP_NAME="psu_uart_0" +CONFIG_SUBSYSTEM_SERIAL_ATF_IP_NAME="cadence" +CONFIG_SUBSYSTEM_SERIAL_IP_NAME="psu_uart_0" + +# +# Ethernet Settings +# +CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_SELECT=y +# CONFIG_SUBSYSTEM_ETHERNET_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC_AUTO is not set +CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC="ff:ff:ff:ff:ff:ff" +CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_USE_DHCP=y + +# +# Flash Settings +# +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_SELECT=y +# CONFIG_SUBSYSTEM_FLASH_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_FLASH__ADVANCED_AUTOCONFIG is not set + +# +# partition 0 +# +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_NAME="boot" +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0x100000 + +# +# partition 1 +# +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_NAME="bootenv" +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x40000 + +# +# partition 2 +# +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_NAME="kernel" +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x1600000 + +# +# partition 3 +# +CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="" +CONFIG_SUBSYSTEM_FLASH_IP_NAME="psu_qspi_0" + +# +# SD/SDIO Settings +# +CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y +# CONFIG_SUBSYSTEM_PRIMARY_SD_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_SD_PSU_SD_1_SELECT=y + +# +# RTC Settings +# +CONFIG_SUBSYSTEM_RTC_PSU_RTC_SELECT=y +# CONFIG_SUBSYSTEM_RTC_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_I2C_PSU_I2C_1_SELECT=y +CONFIG_SUBSYSTEM_I2C_PSU_I2C_0_SELECT=y +CONFIG_SUBSYSTEM_ENDIAN_LITTLE=y + +# +# DTG Settings +# +CONFIG_SUBSYSTEM_MACHINE_NAME="zcu102-rev1.0" +CONFIG_SUBSYSTEM_EXTRA_DT_FILES="" + +# +# Kernel Bootargs +# +CONFIG_SUBSYSTEM_BOOTARGS_AUTO=y +CONFIG_SUBSYSTEM_BOOTARGS_EARLYPRINTK=y +CONFIG_SUBSYSTEM_BOOTARGS_GENERATED=" earlycon console=ttyPS0,115200 clk_ignore_unused init_fatal_sh=1" +CONFIG_SUBSYSTEM_DEVICETREE_COMPILER_FLAGS="-@" +# CONFIG_SUBSYSTEM_DTB_OVERLAY is not set +# CONFIG_SUBSYSTEM_REMOVE_PL_DTB is not set +# CONFIG_SUBSYSTEM_ENABLE_NO_ALIAS is not set + +# +# PMUFW Configuration +# +CONFIG_SUBSYSTEM_PMUFW_COMPILER_EXTRA_FLAGS="" + +# +# FSBL Configuration +# +CONFIG_SUBSYSTEM_FSBL_BSPCOMPILER_FLAGS="" +CONFIG_SUBSYSTEM_FSBL_COMPILER_EXTRA_FLAGS="" + +# +# ARM Trusted Firmware Configuration +# +# CONFIG_SUBSYSTEM_ATF_MEMORY_SETTINGS is not set +CONFIG_SUBSYSTEM_ATF_EXTRA_COMPILER_FLAGS="" +CONFIG_SUBSYSTEM_PRELOADED_BL33_BASE=0x8000000 +# CONFIG_SUBSYSTEM_ATF_DEBUG is not set + +# +# FPGA Manager +# +# CONFIG_SUBSYSTEM_FPGA_MANAGER is not set + +# +# u-boot Configuration +# +CONFIG_SUBSYSTEM_UBOOT_CONFIG_TARGET="xilinx_zynqmp_virt_defconfig" + +# +# u-boot script configuration +# +CONFIG_SUBSYSTEM_UBOOT_APPEND_BASEADDR=y +CONFIG_SUBSYSTEM_UBOOT_PRE_BOOTENV="" + +# +# JTAG/DDR image offsets +# +CONFIG_SUBSYSTEM_UBOOT_DEVICETREE_OFFSET=0x100000 +CONFIG_SUBSYSTEM_UBOOT_KERNEL_OFFSET=0x200000 +CONFIG_SUBSYSTEM_UBOOT_RAMDISK_IMAGE_OFFSET=0x4000000 +CONFIG_SUBSYSTEM_UBOOT_FIT_IMAGE_OFFSET=0x10000000 + +# +# QSPI/OSPI image offsets +# +CONFIG_SUBSYSTEM_UBOOT_QSPI_KERNEL_OFFSET=0xF00000 +CONFIG_SUBSYSTEM_UBOOT_QSPI_KERNEL_SIZE=0x1D00000 +CONFIG_SUBSYSTEM_UBOOT_QSPI_RAMDISK_OFFSET=0x4000000 +CONFIG_SUBSYSTEM_UBOOT_QSPI_RAMDISK_SIZE=0x4000000 +CONFIG_SUBSYSTEM_UBOOT_QSPI_FIT_IMAGE_OFFSET=0xF40000 +CONFIG_SUBSYSTEM_UBOOT_QSPI_FIT_IMAGE_SIZE=0x6400000 + +# +# NAND image offsets +# +CONFIG_SUBSYSTEM_UBOOT_NAND_KERNEL_OFFSET=0x4100000 +CONFIG_SUBSYSTEM_UBOOT_NAND_KERNEL_SIZE=0x3200000 +CONFIG_SUBSYSTEM_UBOOT_NAND_RAMDISK_OFFSET=0x7800000 +CONFIG_SUBSYSTEM_UBOOT_NAND_RAMDISK_SIZE=0x3200000 +CONFIG_SUBSYSTEM_UBOOT_NAND_FIT_IMAGE_OFFSET=0x4180000 +CONFIG_SUBSYSTEM_UBOOT_NAND_FIT_IMAGE_SIZE=0x6400000 +CONFIG_SUBSYSTEM_UBOOT_KERNEL_IMAGE="Image" +CONFIG_SUBSYSTEM_UBOOT_FIT_IMAGE="image.ub" +# CONFIG_SUBSYSTEM_UBOOT_EXT_DTB is not set + +# +# Linux Configuration +# +CONFIG_SUBSYSTEM_LINUX_CONFIG_TARGET="" + +# +# Image Packaging Configuration +# +# CONFIG_SUBSYSTEM_ROOTFS_INITRAMFS is not set +CONFIG_SUBSYSTEM_ROOTFS_INITRD=y +# CONFIG_SUBSYSTEM_ROOTFS_JFFS2 is not set +# CONFIG_SUBSYSTEM_ROOTFS_UBIFS is not set +# CONFIG_SUBSYSTEM_ROOTFS_NFS is not set +# CONFIG_SUBSYSTEM_ROOTFS_EXT4 is not set +# CONFIG_SUBSYSTEM_ROOTFS_OTHER is not set +CONFIG_SUBSYSTEM_INITRD_RAMDISK_LOADADDR=0x0 +CONFIG_SUBSYSTEM_INITRAMFS_IMAGE_NAME="petalinux-initramfs-image" +CONFIG_SUBSYSTEM_UIMAGE_NAME="image.ub" +CONFIG_SUBSYSTEM_RFS_FORMATS="cpio cpio.gz cpio.gz.u-boot ext4 tar.gz jffs2" +CONFIG_SUBSYSTEM_DTB_PADDING_SIZE=0x1000 +# CONFIG_SUBSYSTEM_COPY_TO_TFTPBOOT is not set + +# +# Firmware Version Configuration +# +CONFIG_SUBSYSTEM_HOSTNAME="petalinux" +CONFIG_SUBSYSTEM_PRODUCT="petalinux" +CONFIG_SUBSYSTEM_FW_VERSION="1.00" + +# +# Yocto Settings +# +CONFIG_YOCTO_MACHINE_NAME="zynqmp-generic" + +# +# Yocto board settings +# +CONFIG_YOCTO_BOARD_NAME="" +CONFIG_YOCTO_BOARD_VARIANT_NAME="" + +# +# TMPDIR Location +# +CONFIG_TMP_DIR_LOCATION="${PROOT}/build/tmp" + +# +# Devtool Workspace Location +# +CONFIG_DEVTOOL_WORKSPACE_LOCATION="${PROOT}/components/yocto/workspace" + +# +# Parallel thread execution +# +CONFIG_YOCTO_BB_NUMBER_THREADS="" +CONFIG_YOCTO_PARALLEL_MAKE="" + +# +# Add pre-mirror url +# +CONFIG_PRE_MIRROR_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_VER%%.*}/downloads" + +# +# Local sstate feeds settings +# +CONFIG_YOCTO_LOCAL_SSTATE_FEEDS_URL="" +CONFIG_YOCTO_NETWORK_SSTATE_FEEDS=y + +# +# Network sstate feeds URL +# +CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_VER%%.*}/aarch64/sstate-cache" +# CONFIG_YOCTO_BB_NO_NETWORK is not set +# CONFIG_YOCTO_BUILDTOOLS_EXTENDED is not set + +# +# User Layers +# +CONFIG_USER_LAYER_0="${PROOT}/../../../../../../meta-corundum" +CONFIG_USER_LAYER_1="" diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/configs/init-ifupdown/interfaces b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/configs/init-ifupdown/interfaces new file mode 100644 index 000000000..0acf4cf44 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/configs/init-ifupdown/interfaces @@ -0,0 +1,31 @@ +# /etc/network/interfaces -- configuration file for ifup(8), ifdown(8) + +# The loopback interface +auto lo +iface lo inet loopback + +# Wireless interfaces +iface wlan0 inet dhcp + wireless_mode managed + wireless_essid any + wpa-driver wext + wpa-conf /etc/wpa_supplicant.conf + +iface atml0 inet dhcp + +# Wired or wireless interfaces +auto eth0 +iface eth0 inet dhcp +iface eth1 inet dhcp + +# Ethernet/RNDIS gadget (g_ether) +# ... or on host side, usbnet and random hwaddr +iface usb0 inet static + address 192.168.7.2 + netmask 255.255.255.0 + network 192.168.7.0 + gateway 192.168.7.1 + +# Bluetooth networking +iface bnep0 inet dhcp + diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/configs/rootfs_config b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/configs/rootfs_config new file mode 100644 index 000000000..baa68db44 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/configs/rootfs_config @@ -0,0 +1,4188 @@ +# +# Automatically generated file; DO NOT EDIT. +# Configuration +# +CONFIG_system-zynqmp=y + +# +# Filesystem Packages +# + +# +# admin +# + +# +# sudo +# +# CONFIG_sudo is not set +# CONFIG_sudo-dev is not set +# CONFIG_sudo-dbg is not set + +# +# audio +# + +# +# sox +# +# CONFIG_sox is not set +# CONFIG_sox-dbg is not set +# CONFIG_sox-dev is not set + +# +# base +# + +# +# base-files +# +# CONFIG_base-files is not set +# CONFIG_base-files-dbg is not set +# CONFIG_base-files-dev is not set + +# +# base-passwd +# +# CONFIG_base-passwd is not set +# CONFIG_base-passwd-dev is not set +# CONFIG_base-passwd-dbg is not set +# CONFIG_base-passwd-update is not set + +# +# bc +# +# CONFIG_bc is not set +# CONFIG_bc-dev is not set +# CONFIG_bc-dbg is not set + +# +# busybox +# +# CONFIG_busybox is not set +# CONFIG_busybox-inetd is not set +# CONFIG_busybox-dbg is not set +# CONFIG_busybox-syslog is not set +# CONFIG_busybox-hwclock is not set +# CONFIG_busybox-httpd is not set +# CONFIG_busybox-dev is not set +# CONFIG_busybox-udhcpc is not set +# CONFIG_busybox-udhcpd is not set + +# +# cpio +# +# CONFIG_cpio is not set +# CONFIG_cpio-dbg is not set +# CONFIG_cpio-dev is not set +# CONFIG_cpio-rmt is not set + +# +# dbus +# +# CONFIG_dbus is not set +# CONFIG_dbus-dbg is not set +# CONFIG_dbus-lib is not set +# CONFIG_dbus-dev is not set + +# +# dbus-glib +# +# CONFIG_dbus-glib is not set +# CONFIG_dbus-glib-dev is not set +# CONFIG_dbus-glib-bash-completion is not set +# CONFIG_dbus-glib-tests is not set +# CONFIG_dbus-glib-dbg is not set + +# +# dbus-wait +# +# CONFIG_dbus-wait is not set +# CONFIG_dbus-wait-dbg is not set +# CONFIG_dbus-wait-dev is not set + +# +# diffutils +# +# CONFIG_diffutils is not set +# CONFIG_diffutils-dbg is not set +# CONFIG_diffutils-dev is not set + +# +# dnf +# +# CONFIG_dnf is not set + +# +# e2fsprogs +# +# CONFIG_e2fsprogs is not set +# CONFIG_e2fsprogs-dev is not set +CONFIG_e2fsprogs-mke2fs=y +# CONFIG_e2fsprogs-dbg is not set +# CONFIG_e2fsprogs-resize2fs is not set +# CONFIG_e2fsprogs-tune2fs is not set +# CONFIG_libss is not set +# CONFIG_libcomerr is not set +# CONFIG_libext2fs is not set +# CONFIG_libe2p is not set +# CONFIG_e2fsprogs-e2fsck is not set +# CONFIG_e2fsprogs-badblocks is not set + +# +# ed +# +# CONFIG_ed is not set +# CONFIG_ed-dev is not set +# CONFIG_ed-dbg is not set + +# +# elfutils +# +# CONFIG_elfutils is not set +# CONFIG_libdw is not set +# CONFIG_elfutils-dev is not set +# CONFIG_elfutils-binutils is not set +# CONFIG_libelf is not set +# CONFIG_elfutils-dbg is not set +# CONFIG_libasm is not set + +# +# formfactor +# +# CONFIG_formfactor is not set +# CONFIG_formfactor-dbg is not set +# CONFIG_formfactor-dev is not set + +# +# fpga-manager-script +# +CONFIG_fpga-manager-script=y + +# +# haveged +# +CONFIG_haveged=y + +# +# i2c-tools +# +# CONFIG_i2c-tools is not set +# CONFIG_i2c-tools-dev is not set +# CONFIG_i2c-tools-misc is not set +# CONFIG_i2c-tools-dbg is not set + +# +# init-ifupdown +# +# CONFIG_init-ifupdown is not set +# CONFIG_init-ifupdown-dev is not set +# CONFIG_init-ifupdown-dbg is not set + +# +# initscripts +# +# CONFIG_initscripts is not set +# CONFIG_initscripts-functions is not set +# CONFIG_initscripts-dev is not set +# CONFIG_initscripts-dbg is not set + +# +# iproute2 +# +CONFIG_iproute2=y +# CONFIG_iproute2-ss is not set +# CONFIG_iproute2-dev is not set +# CONFIG_iproute2-dbg is not set +# CONFIG_iproute2-ifstat is not set +# CONFIG_iproute2-nstat is not set +# CONFIG_iproute2-tc is not set +# CONFIG_iproute2-bash-completion is not set +# CONFIG_iproute2-genl is not set +# CONFIG_iproute2-rtacct is not set +# CONFIG_iproute2-lnstat is not set + +# +# kmod +# +CONFIG_kmod=y +# CONFIG_kmod-bash-completion is not set +# CONFIG_libkmod is not set +# CONFIG_kmod-dbg is not set +# CONFIG_kmod-dev is not set + +# +# linuxptp +# +CONFIG_linuxptp=y +# CONFIG_linuxptp-dev is not set +# CONFIG_linuxptp-dbg is not set + +# +# modutils-initscripts +# +# CONFIG_modutils-initscripts is not set +# CONFIG_modutils-initscripts-dev is not set +# CONFIG_modutils-initscripts-dbg is not set + +# +# mtd-utils +# +CONFIG_mtd-utils=y +# CONFIG_mtd-utils-jffs2 is not set +# CONFIG_mtd-utils-misc is not set +# CONFIG_mtd-utils-dev is not set +# CONFIG_mtd-utils-ubifs is not set +# CONFIG_mtd-utils-dbg is not set + +# +# netbase +# +# CONFIG_netbase is not set +# CONFIG_netbase-dev is not set +# CONFIG_netbase-dbg is not set + +# +# opkg +# +# CONFIG_opkg is not set +# CONFIG_libopkg is not set +# CONFIG_opkg-dbg is not set +# CONFIG_opkg-dev is not set + +# +# opkg-utils +# +# CONFIG_opkg-utils is not set +# CONFIG_opkg-utils-dbg is not set +# CONFIG_update-alternatives-opkg is not set + +# +# procps +# +# CONFIG_procps is not set +# CONFIG_procps-dev is not set +# CONFIG_procps-dbg is not set + +# +# pseudo +# +# CONFIG_pseudo is not set +# CONFIG_pseudo-dev is not set +# CONFIG_pseudo-dbg is not set + +# +# psplash +# +# CONFIG_psplash is not set +# CONFIG_psplash-dbg is not set +# CONFIG_psplash-default is not set +# CONFIG_psplash-dev is not set + +# +# quota +# +# CONFIG_quota is not set +# CONFIG_quota-dbg is not set +# CONFIG_quota-dev is not set + +# +# shared-mime-info +# +# CONFIG_shared-mime-info is not set +# CONFIG_shared-mime-info-dev is not set +# CONFIG_shared-mime-info-dbg is not set +# CONFIG_shared-mime-info-data is not set + +# +# shell +# + +# +# bash +# +# CONFIG_bash is not set +# CONFIG_bash-dbg is not set +# CONFIG_bash-dev is not set + +# +# sysvinit +# +# CONFIG_sysvinit is not set +# CONFIG_sysvinit-dev is not set +# CONFIG_sysvinit-sulogin is not set +# CONFIG_sysvinit-dbg is not set +# CONFIG_sysvinit-pidof is not set + +# +# tar +# +# CONFIG_tar is not set +# CONFIG_tar-dev is not set +# CONFIG_tar-dbg is not set +# CONFIG_tar-rmt is not set + +# +# tzdata +# +# CONFIG_tzdata is not set +# CONFIG_tzdata-pacific is not set +# CONFIG_tzdata-posix is not set +# CONFIG_tzdata-antarctica is not set +# CONFIG_tzdata-africa is not set +# CONFIG_tzdata-europe is not set +# CONFIG_tzdata-americas is not set +# CONFIG_tzdata-right is not set +# CONFIG_tzdata-atlantic is not set +# CONFIG_tzdata-australia is not set +# CONFIG_tzdata-misc is not set +# CONFIG_tzdata-asia is not set +# CONFIG_tzdata-arctic is not set + +# +# update-rc.d +# +# CONFIG_update-rc.d is not set +# CONFIG_update-rc.d-dbg is not set +# CONFIG_update-rc.d-dev is not set + +# +# usbutils +# +# CONFIG_usbutils is not set +# CONFIG_usbutils-dev is not set +# CONFIG_usbutils-dbg is not set + +# +# util-linux +# +# CONFIG_util-linux is not set +# CONFIG_util-linux-sulogin is not set +# CONFIG_util-linux-losetup is not set +# CONFIG_util-linux-hwclock is not set +# CONFIG_util-linux-fsck is not set +# CONFIG_util-linux-uuidgen is not set +# CONFIG_util-linux-bash-completion is not set +# CONFIG_util-linux-fstrim is not set +# CONFIG_util-linux-cfdisk is not set +# CONFIG_util-linux-umount is not set +# CONFIG_util-linux-findfs is not set +# CONFIG_util-linux-agetty is not set +# CONFIG_util-linux-mount is not set +# CONFIG_util-linux-sfdisk is not set +# CONFIG_util-linux-swaponoff is not set +# CONFIG_util-linux-fsck.cramfs is not set +# CONFIG_util-linux-prlimit is not set +# CONFIG_util-linux-mcookie is not set +# CONFIG_util-linux-getopt is not set +# CONFIG_util-linux-blkid is not set +# CONFIG_util-linux-dev is not set +# CONFIG_util-linux-partx is not set +# CONFIG_util-linux-mkfs is not set +# CONFIG_util-linux-readprofile is not set +# CONFIG_util-linux-mountpoint is not set +# CONFIG_util-linux-fdisk is not set +# CONFIG_util-linux-lscpu is not set +# CONFIG_util-linux-dbg is not set +# CONFIG_util-linux-uuidd is not set +# CONFIG_util-linux-mkfs.cramfs is not set + +# +# utils +# + +# +# shadow +# +# CONFIG_shadow is not set +# CONFIG_shadow-base is not set +# CONFIG_shadow-dev is not set +# CONFIG_shadow-dbg is not set + +# +# xz +# +# CONFIG_xz is not set +# CONFIG_xz-dev is not set +# CONFIG_xz-dbg is not set +# CONFIG_liblzma is not set + +# +# baseutils +# + +# +# shadow-securetty +# +# CONFIG_shadow-securetty is not set +# CONFIG_shadow-securetty-dev is not set +# CONFIG_shadow-securetty-dbg is not set + +# +# benchmark +# + +# +# tests +# + +# +# dhrystone +# +# CONFIG_dhrystone is not set +# CONFIG_dhrystone-dev is not set +# CONFIG_dhrystone-dbg is not set + +# +# linpack +# +# CONFIG_linpack is not set +# CONFIG_linpack-dbg is not set +# CONFIG_linpack-dev is not set + +# +# whetstone +# +# CONFIG_whetstone is not set +# CONFIG_whetstone-dev is not set +# CONFIG_whetstone-dbg is not set + +# +# bootgen +# +# CONFIG_bootgen is not set +# CONFIG_bootgen-dev is not set +# CONFIG_bootgen-dbg is not set + +# +# bootloader +# + +# +# dtc +# +# CONFIG_dtc is not set +# CONFIG_dtc-dbg is not set +# CONFIG_dtc-misc is not set +# CONFIG_dtc-dev is not set + +# +# console +# + +# +# network +# + +# +# canutils +# +# CONFIG_canutils is not set +# CONFIG_canutils-dev is not set +# CONFIG_canutils-dbg is not set + +# +# can-utils +# +CONFIG_can-utils=y +# CONFIG_can-utils-dbg is not set +# CONFIG_can-utils-dev is not set + +# +# curl +# +# CONFIG_curl is not set +# CONFIG_curl-dbg is not set +# CONFIG_libcurl is not set +# CONFIG_curl-dev is not set + +# +# dropbear +# +# CONFIG_dropbear is not set +# CONFIG_dropbear-dev is not set +# CONFIG_dropbear-dbg is not set + +# +# ethtool +# +CONFIG_ethtool=y +# CONFIG_ethtool-dev is not set +# CONFIG_ethtool-dbg is not set + +# +# lrzsz +# +# CONFIG_lrzsz is not set +# CONFIG_lrzsz-dbg is not set +# CONFIG_lrzsz-dev is not set + +# +# mailx +# +# CONFIG_mailx is not set +# CONFIG_mailx-dbg is not set +# CONFIG_mailx-dev is not set + +# +# minicom +# +# CONFIG_minicom is not set +# CONFIG_minicom-dev is not set +# CONFIG_minicom-dbg is not set + +# +# nfs-utils +# +# CONFIG_nfs-utils is not set +# CONFIG_nfs-utils-stats is not set +# CONFIG_nfs-utils-dbg is not set +# CONFIG_nfs-utils-dev is not set +# CONFIG_nfs-utils-client is not set + +# +# openssh +# +# CONFIG_openssh is not set +# CONFIG_openssh-ssh is not set +# CONFIG_openssh-sftp is not set +CONFIG_openssh-sftp-server=y +# CONFIG_openssh-keygen is not set +# CONFIG_openssh-dbg is not set +# CONFIG_openssh-dev is not set +# CONFIG_openssh-misc is not set +# CONFIG_openssh-sshd is not set +# CONFIG_openssh-scp is not set + +# +# ppp +# +# CONFIG_ppp is not set +# CONFIG_ppp-dev is not set +# CONFIG_ppp-l2tp is not set +# CONFIG_ppp-minconn is not set +# CONFIG_ppp-winbind is not set +# CONFIG_ppp-dbg is not set +# CONFIG_ppp-oe is not set +# CONFIG_ppp-oa is not set +# CONFIG_ppp-radius is not set +# CONFIG_ppp-tools is not set +# CONFIG_ppp-password is not set + +# +# rpcbind +# +# CONFIG_rpcbind is not set +# CONFIG_rpcbind-dev is not set +# CONFIG_rpcbind-dbg is not set + +# +# rsync +# +# CONFIG_rsync is not set +# CONFIG_rsync-dev is not set +# CONFIG_rsync-dbg is not set + +# +# socat +# +# CONFIG_socat is not set +# CONFIG_socat-dev is not set +# CONFIG_socat-dbg is not set + +# +# subversion +# +# CONFIG_subversion is not set +# CONFIG_subversion-dev is not set +# CONFIG_subversion-dbg is not set + +# +# tcp-wrappers +# +# CONFIG_tcp-wrappers is not set +# CONFIG_libwrap is not set +# CONFIG_tcp-wrappers-dbg is not set +# CONFIG_libwrap-dev is not set + +# +# wget +# +# CONFIG_wget is not set +# CONFIG_wget-dev is not set +# CONFIG_wget-dbg is not set + +# +# tools +# + +# +# parted +# +# CONFIG_parted is not set +# CONFIG_parted-dev is not set +# CONFIG_parted-dbg is not set + +# +# xen +# +# CONFIG_xen-efi is not set +# CONFIG_xen-dbg is not set +# CONFIG_xen-tools is not set + +# +# utils +# + +# +# alsa-tools +# +# CONFIG_alsa-tools is not set +# CONFIG_alsa-tools-dbg is not set +# CONFIG_alsa-tools-dev is not set + +# +# alsa-utils +# +# CONFIG_alsa-utils is not set +# CONFIG_alsa-utils-alsatplg is not set +# CONFIG_alsa-utils-midi is not set +# CONFIG_alsa-utils-alsactl is not set +# CONFIG_alsa-utils-alsamixer is not set +# CONFIG_alsa-utils-amixer is not set +# CONFIG_alsa-utils-speakertest is not set +# CONFIG_alsa-utils-aplay is not set +# CONFIG_alsa-utils-dev is not set +# CONFIG_alsa-utils-aconnect is not set +# CONFIG_alsa-utils-alsaloop is not set +# CONFIG_alsa-utils-aseqdump is not set +# CONFIG_alsa-utils-iecset is not set +# CONFIG_alsa-utils-alsaucm is not set +# CONFIG_alsa-utils-dbg is not set +# CONFIG_alsa-utils-aseqnet is not set + +# +# bash-completion +# +# CONFIG_bash-completion is not set +# CONFIG_bash-completion-dbg is not set +# CONFIG_bash-completion-dev is not set +# CONFIG_bash-completion-extra is not set + +# +# bzip2 +# +# CONFIG_bzip2 is not set +# CONFIG_libbz2 is not set +# CONFIG_bzip2-dbg is not set +# CONFIG_bzip2-dev is not set + +# +# file +# +# CONFIG_file is not set +# CONFIG_file-dev is not set +# CONFIG_file-dbg is not set + +# +# findutils +# +# CONFIG_findutils is not set +# CONFIG_findutils-dbg is not set +# CONFIG_findutils-dev is not set + +# +# gawk +# +# CONFIG_gawk is not set +# CONFIG_gawk-dbg is not set +# CONFIG_gawk-dev is not set + +# +# git +# +# CONFIG_git is not set +# CONFIG_git-bash-completion is not set +# CONFIG_git-perltools is not set +# CONFIG_gitweb is not set +# CONFIG_git-dev is not set +# CONFIG_git-dbg is not set + +# +# grep +# +# CONFIG_grep is not set +# CONFIG_grep-dbg is not set +# CONFIG_grep-dev is not set + +# +# groff +# +# CONFIG_groff is not set +# CONFIG_groff-dev is not set +# CONFIG_groff-dbg is not set + +# +# gzip +# +# CONFIG_gzip is not set +# CONFIG_gzip-dev is not set +# CONFIG_gzip-dbg is not set + +# +# hdparm +# +# CONFIG_hdparm is not set +# CONFIG_hdparm-dev is not set +# CONFIG_wiper is not set +# CONFIG_hdparm-dbg is not set + +# +# less +# +# CONFIG_less is not set +# CONFIG_less-dbg is not set +# CONFIG_less-dev is not set + +# +# lmbench +# +# CONFIG_lmbench is not set +# CONFIG_lmbench-dbg is not set +# CONFIG_lmbench-dev is not set + +# +# ltp +# +# CONFIG_ltp is not set +# CONFIG_ltp-dev is not set +# CONFIG_ltp-dbg is not set + +# +# man +# +# CONFIG_man is not set + +# +# man-pages +# +# CONFIG_man-pages is not set +# CONFIG_man-pages-dev is not set +# CONFIG_man-pages-dbg is not set + +# +# mc +# +# CONFIG_mc is not set +# CONFIG_mc-fish is not set +# CONFIG_mc-dev is not set +# CONFIG_mc-dbg is not set +# CONFIG_mc-helpers is not set +# CONFIG_mc-helpers-perl is not set + +# +# pciutils +# +CONFIG_pciutils=y +# CONFIG_pciutils-dbg is not set +# CONFIG_libpci is not set +# CONFIG_pciutils-ids is not set +# CONFIG_pciutils-dev is not set + +# +# pkgconfig +# +# CONFIG_pkgconfig is not set +# CONFIG_pkgconfig-dev is not set +# CONFIG_pkgconfig-dbg is not set + +# +# screen +# +# CONFIG_screen is not set +# CONFIG_screen-dev is not set +# CONFIG_screen-dbg is not set + +# +# sed +# +# CONFIG_sed is not set +# CONFIG_sed-dev is not set +# CONFIG_sed-dbg is not set + +# +# setserial +# +# CONFIG_setserial is not set +# CONFIG_setserial-dbg is not set +# CONFIG_setserial-dev is not set + +# +# smartmontools +# +# CONFIG_smartmontools is not set +# CONFIG_smartmontools-dev is not set +# CONFIG_smartmontools-dbg is not set + +# +# strace +# +# CONFIG_strace is not set +# CONFIG_strace-dev is not set +# CONFIG_strace-dbg is not set + +# +# sysstat +# +# CONFIG_sysstat is not set +# CONFIG_sysstat-dbg is not set +# CONFIG_sysstat-dev is not set + +# +# texinfo +# +# CONFIG_texinfo is not set +# CONFIG_texinfo-dbg is not set +# CONFIG_texinfo-dev is not set +# CONFIG_info is not set + +# +# unzip +# +# CONFIG_unzip is not set +# CONFIG_unzip-dbg is not set +# CONFIG_unzip-dev is not set + +# +# vim +# +# CONFIG_vim is not set +# CONFIG_vim-help is not set +# CONFIG_vim-dbg is not set +# CONFIG_vim-vimrc is not set +# CONFIG_vim-dev is not set +# CONFIG_vim-tutor is not set +# CONFIG_vim-tools is not set +# CONFIG_vim-common is not set +# CONFIG_vim-syntax is not set + +# +# zip +# +# CONFIG_zip is not set +# CONFIG_zip-dev is not set +# CONFIG_zip-dbg is not set + +# +# devel +# + +# +# autoconf +# +# CONFIG_autoconf is not set +# CONFIG_autoconf-dbg is not set +# CONFIG_autoconf-dev is not set + +# +# automake +# +# CONFIG_automake is not set +# CONFIG_automake-dev is not set +# CONFIG_automake-dbg is not set + +# +# binutils +# +# CONFIG_binutils is not set +# CONFIG_binutils-dev is not set +# CONFIG_binutils-dbg is not set + +# +# bison +# +# CONFIG_bison is not set +# CONFIG_bison-dbg is not set +# CONFIG_bison-dev is not set + +# +# ccache +# +# CONFIG_ccache is not set +# CONFIG_ccache-dbg is not set +# CONFIG_ccache-dev is not set + +# +# diffstat +# +# CONFIG_diffstat is not set +# CONFIG_diffstat-dev is not set +# CONFIG_diffstat-dbg is not set + +# +# distcc +# +# CONFIG_distcc is not set +# CONFIG_distcc-dbg is not set +# CONFIG_distcc-dev is not set + +# +# expect +# +# CONFIG_expect is not set +# CONFIG_expect-dev is not set +# CONFIG_expect-dbg is not set + +# +# flex +# +# CONFIG_flex is not set +# CONFIG_flex-dbg is not set +# CONFIG_flex-dev is not set + +# +# gmp +# +# CONFIG_gmp is not set +# CONFIG_libgmpxx is not set +# CONFIG_gmp-dbg is not set +# CONFIG_gmp-dev is not set + +# +# gnu-config +# +# CONFIG_gnu-config is not set + +# +# gnu-efi +# +# CONFIG_gnu-efi is not set +# CONFIG_gnu-efi-dbg is not set +# CONFIG_gnu-efi-dev is not set + +# +# intltool +# +# CONFIG_intltool is not set +# CONFIG_intltool-dev is not set +# CONFIG_intltool-dbg is not set + +# +# libarchive +# +# CONFIG_libarchive is not set +# CONFIG_bsdcpio is not set +# CONFIG_libarchive-dbg is not set +# CONFIG_bsdtar is not set +# CONFIG_libarchive-dev is not set + +# +# libcheck +# +# CONFIG_libcheck is not set +# CONFIG_libcheck-dev is not set +# CONFIG_libcheck-dbg is not set + +# +# libpcre +# +# CONFIG_libpcre is not set +# CONFIG_libpcrecpp is not set +# CONFIG_libpcre-dbg is not set +# CONFIG_libpcreposix is not set +# CONFIG_libpcre-dev is not set +# CONFIG_pcregrep is not set +# CONFIG_pcretest is not set + +# +# lsof +# +# CONFIG_lsof is not set +# CONFIG_lsof-dev is not set +# CONFIG_lsof-dbg is not set + +# +# make +# +# CONFIG_make is not set +# CONFIG_make-dev is not set +# CONFIG_make-dbg is not set + +# +# mpfr +# +# CONFIG_mpfr is not set +# CONFIG_mpfr-dbg is not set +# CONFIG_mpfr-dev is not set + +# +# perl +# +# CONFIG_perl is not set +# CONFIG_perl-misc is not set +# CONFIG_perl-modules is not set +# CONFIG_perl-module-unicore is not set +# CONFIG_perl-dbg is not set +# CONFIG_perl-module-cpan is not set +# CONFIG_perl-pod is not set +# CONFIG_perl-dev is not set + +# +# python +# + +# +# python +# +# CONFIG_python is not set +# CONFIG_python-terminal is not set +# CONFIG_python-mailbox is not set +# CONFIG_python-logging is not set +# CONFIG_python-xml is not set +# CONFIG_python-hotshot is not set +# CONFIG_python-multiprocessing is not set +# CONFIG_python-threading is not set +# CONFIG_python-curses is not set +# CONFIG_python-mime is not set +# CONFIG_python-netclient is not set +# CONFIG_python-netserver is not set +# CONFIG_python-image is not set +# CONFIG_python-unixadmin is not set +# CONFIG_python-sqlite3 is not set +# CONFIG_python-pprint is not set +# CONFIG_python-contextlib is not set +# CONFIG_python-idle is not set +# CONFIG_python-pkgutil is not set +# CONFIG_python-crypt is not set +# CONFIG_python-zlib is not set +# CONFIG_python-fcntl is not set +# CONFIG_python-stringold is not set +# CONFIG_python-dev is not set +# CONFIG_libpython2 is not set +# CONFIG_python-smtpd is not set +# CONFIG_python-core is not set +# CONFIG_python-tkinter is not set +# CONFIG_python-codecs is not set +# CONFIG_python-compression is not set +# CONFIG_python-bsddb is not set +# CONFIG_python-subprocess is not set +# CONFIG_python-io is not set +# CONFIG_python-numbers is not set +# CONFIG_python-unittest is not set +# CONFIG_python-json is not set +# CONFIG_python-html is not set +# CONFIG_python-lang is not set +# CONFIG_python-compiler is not set +# CONFIG_python-shell is not set +# CONFIG_python-datetime is not set +# CONFIG_python-email is not set +# CONFIG_python-misc is not set +# CONFIG_python-resource is not set +# CONFIG_python-distutils is not set +# CONFIG_python-syslog is not set +# CONFIG_python-2to3 is not set +# CONFIG_python-pydoc is not set +# CONFIG_python-tests is not set +# CONFIG_python-modules is not set +# CONFIG_python-db is not set +# CONFIG_python-ctypes is not set +# CONFIG_python-re is not set +# CONFIG_python-audio is not set +# CONFIG_python-profile is not set +# CONFIG_python-dbg is not set +# CONFIG_python-mmap is not set +# CONFIG_python-compile is not set +# CONFIG_python-difflib is not set +# CONFIG_python-xmlrpc is not set +# CONFIG_python-argparse is not set +# CONFIG_python-math is not set +# CONFIG_python-robotparser is not set +# CONFIG_python-pickle is not set +# CONFIG_python-debugger is not set +# CONFIG_python-plistlib is not set +# CONFIG_python-gdbm is not set +# CONFIG_python-textutils is not set + +# +# python3-nose +# +# CONFIG_python3-nose is not set +# CONFIG_python3-nose-dbg is not set +# CONFIG_python3-nose-dev is not set + +# +# python3-numpy +# +# CONFIG_python3-numpy is not set +# CONFIG_python3-numpy-dbg is not set +# CONFIG_python3-numpy-dev is not set + +# +# python3-scons +# +# CONFIG_python3-scons is not set +# CONFIG_python3-scons-dev is not set +# CONFIG_python3-scons-dbg is not set + +# +# python3-dbus +# +# CONFIG_python3-dbus is not set +# CONFIG_python3-dbus-dev is not set +# CONFIG_python3-dbus-dbg is not set + +# +# python3-pygobject +# +# CONFIG_python3-pygobject is not set +# CONFIG_python3-pygobject-dbg is not set +# CONFIG_python3-pygobject-dev is not set + +# +# quilt +# +# CONFIG_quilt is not set +# CONFIG_quilt-dev is not set +# CONFIG_quilt-dbg is not set +# CONFIG_guards is not set + +# +# ruby +# + +# +# ruby +# +# CONFIG_ruby is not set +# CONFIG_ruby-dbg is not set +# CONFIG_ruby-dev is not set +# CONFIG_ruby-rdoc is not set + +# +# run-postinsts +# +CONFIG_run-postinsts=y +# CONFIG_run-postinsts-dbg is not set +# CONFIG_run-postinsts-dev is not set + +# +# swig +# +# CONFIG_swig is not set +# CONFIG_swig-dev is not set +# CONFIG_swig-dbg is not set + +# +# tcltk +# + +# +# tcl +# +# CONFIG_tcl is not set +# CONFIG_tcl-dbg is not set +# CONFIG_tcl-lib is not set +# CONFIG_tcl-dev is not set + +# +# vala +# +# CONFIG_vala is not set +# CONFIG_vala-dbg is not set +# CONFIG_vala-dev is not set + +# +# fonts +# + +# +# cantarell-fonts +# +# CONFIG_cantarell-fonts is not set +# CONFIG_cantarell-fonts-dbg is not set +# CONFIG_cantarell-fonts-dev is not set + +# +# kernel +# + +# +# userland +# + +# +# kexec-tools +# +# CONFIG_kexec-tools is not set +# CONFIG_kexec-tools-dbg is not set +# CONFIG_vmcore-dmesg is not set +# CONFIG_kdump is not set +# CONFIG_kexec is not set +# CONFIG_kexec-tools-dev is not set + +# +# libs +# + +# +# acl +# +# CONFIG_acl is not set +# CONFIG_acl-dev is not set +# CONFIG_libacl is not set +# CONFIG_acl-dbg is not set + +# +# apr +# +# CONFIG_apr is not set +# CONFIG_apr-dev is not set +# CONFIG_apr-dbg is not set + +# +# apr-util +# +# CONFIG_apr-util is not set +# CONFIG_apr-util-dev is not set +# CONFIG_apr-util-dbg is not set + +# +# attr +# +# CONFIG_attr is not set +# CONFIG_libattr is not set +# CONFIG_attr-dbg is not set +# CONFIG_attr-dev is not set + +# +# bluez5 +# +# CONFIG_bluez5 is not set +# CONFIG_bluez5-obex is not set +# CONFIG_bluez5-dev is not set +# CONFIG_bluez5-dbg is not set +# CONFIG_bluez5-noinst-tools is not set +# CONFIG_bluez5-testtools is not set + +# +# cairo +# +# CONFIG_cairo is not set +# CONFIG_cairo-dbg is not set +# CONFIG_cairo-dev is not set +# CONFIG_cairo-script-interpreter is not set +# CONFIG_cairo-perf-utils is not set +# CONFIG_cairo-gobject is not set + +# +# db +# +# CONFIG_db is not set +# CONFIG_db-bin is not set +# CONFIG_db-cxx is not set +# CONFIG_db-dbg is not set +# CONFIG_db-dev is not set + +# +# devel +# + +# +# libyaml +# +# CONFIG_libyaml is not set +# CONFIG_libyaml-dev is not set +# CONFIG_libyaml-dbg is not set + +# +# expat +# +# CONFIG_expat is not set +# CONFIG_expat-dev is not set +# CONFIG_expat-dbg is not set +# CONFIG_expat-bin is not set + +# +# faad2 +# +# CONFIG_faad2 is not set +# CONFIG_faad2-dev is not set +# CONFIG_faad2-dbg is not set + +# +# ffmpeg +# +# CONFIG_ffmpeg is not set +# CONFIG_ffmpeg-dbg is not set +# CONFIG_ffmpeg-dev is not set + +# +# flac +# +# CONFIG_flac is not set +# CONFIG_libflac is not set +# CONFIG_flac-dev is not set +# CONFIG_libflacPLUSPLUS is not set +# CONFIG_flac-dbg is not set + +# +# fontconfig +# +# CONFIG_fontconfig is not set +# CONFIG_fontconfig-utils is not set +# CONFIG_fontconfig-dev is not set +# CONFIG_fontconfig-dbg is not set + +# +# freetype +# +# CONFIG_freetype is not set +# CONFIG_freetype-dbg is not set +# CONFIG_freetype-dev is not set + +# +# gdbm +# +# CONFIG_gdbm is not set +# CONFIG_gdbm-dbg is not set +# CONFIG_gdbm-compat is not set +# CONFIG_gdbm-dev is not set +# CONFIG_gdbm-bin is not set + +# +# gdk-pixbuf +# +# CONFIG_gdk-pixbuf is not set +# CONFIG_gdk-pixbuf-xlib is not set +# CONFIG_gdk-pixbuf-dev is not set +# CONFIG_gdk-pixbuf-dbg is not set + +# +# gettext +# +# CONFIG_gettext is not set +# CONFIG_libgettextsrc is not set +# CONFIG_gettext-dbg is not set +# CONFIG_gettext-runtime is not set +# CONFIG_gettext-dev is not set +# CONFIG_libgettextlib is not set + +# +# glib-networking +# +# CONFIG_glib-networking is not set +# CONFIG_glib-networking-dev is not set +# CONFIG_glib-networking-dbg is not set + +# +# gobject-introspection +# +# CONFIG_gobject-introspection is not set +# CONFIG_gobject-introspection-dbg is not set +# CONFIG_gobject-introspection-dev is not set + +# +# gtk+ +# +# CONFIG_gtkPLUS is not set +# CONFIG_gtkPLUS-dev is not set +# CONFIG_libgail is not set +# CONFIG_gtkPLUS-dbg is not set +# CONFIG_gtk-demo is not set + +# +# gtk+3 +# +# CONFIG_gtkPLUS3 is not set +# CONFIG_gtkPLUS3-dev is not set +# CONFIG_gtkPLUS3-dbg is not set +# CONFIG_gtkPLUS3-demo is not set + +# +# harfbuzz +# +# CONFIG_harfbuzz is not set +# CONFIG_harfbuzz-dev is not set +# CONFIG_harfbuzz-bin is not set +# CONFIG_harfbuzz-icu-dev is not set +# CONFIG_harfbuzz-dbg is not set +# CONFIG_harfbuzz-icu is not set + +# +# libaio +# +# CONFIG_libaio is not set +# CONFIG_libaio-dev is not set +# CONFIG_libaio-dbg is not set + +# +# libcap +# +# CONFIG_libcap is not set +# CONFIG_libcap-bin is not set +# CONFIG_libcap-dbg is not set +# CONFIG_libcap-dev is not set + +# +# libcgroup +# +# CONFIG_libcgroup is not set +# CONFIG_libcgroup-dbg is not set +# CONFIG_libcgroup-dev is not set + +# +# libdaemon +# +# CONFIG_libdaemon is not set +# CONFIG_libdaemon-dbg is not set +# CONFIG_libdaemon-dev is not set + +# +# libdmx +# +# CONFIG_libdmx is not set +# CONFIG_libdmx-dbg is not set +# CONFIG_libdmx-dev is not set + +# +# libeigen +# +# CONFIG_libeigen-dev is not set +# CONFIG_libeigen-dbg is not set + +# +# libepoxy +# +# CONFIG_libepoxy is not set +# CONFIG_libepoxy-dev is not set +# CONFIG_libepoxy-dbg is not set + +# +# libevdev +# +# CONFIG_libevdev is not set +# CONFIG_libevdev-dev is not set +# CONFIG_libevdev-dbg is not set + +# +# libevent +# +# CONFIG_libevent is not set +# CONFIG_libevent-dbg is not set +# CONFIG_libevent-dev is not set + +# +# libexif +# +# CONFIG_libexif is not set +# CONFIG_libexif-dbg is not set +# CONFIG_libexif-dev is not set + +# +# libffi +# +# CONFIG_libffi is not set +# CONFIG_libffi-dbg is not set +# CONFIG_libffi-dev is not set + +# +# libfontenc +# +# CONFIG_libfontenc is not set +# CONFIG_libfontenc-dev is not set +# CONFIG_libfontenc-dbg is not set + +# +# libgcrypt +# +# CONFIG_libgcrypt is not set +# CONFIG_dumpsexp-dev is not set +# CONFIG_libgcrypt-dbg is not set +# CONFIG_libgcrypt-dev is not set + +# +# libgcc +# +# CONFIG_libgcc is not set +# CONFIG_libgcc-dbg is not set +# CONFIG_libgcc-dev is not set + +# +# libgpg-error +# +# CONFIG_libgpg-error is not set +# CONFIG_libgpg-error-dbg is not set +# CONFIG_libgpg-error-dev is not set + +# +# libgphoto2 +# +# CONFIG_libgphoto2 is not set +# CONFIG_libgphoto2-dbg is not set +# CONFIG_libgphoto2-camlibs is not set +# CONFIG_libgphoto2-dev is not set +# CONFIG_libgphoto2-bin is not set +# CONFIG_libgphotoport is not set + +# +# libgpiod +# +# CONFIG_libgpiod is not set +# CONFIG_libgpiod-dev is not set +# CONFIG_libgpiod-dbg is not set + +# +# libgudev +# +# CONFIG_libgudev is not set +# CONFIG_libgudev-dev is not set +# CONFIG_libgudev-dbg is not set + +# +# libhugetlbfs +# +# CONFIG_libhugetlbfs is not set +# CONFIG_libhugetlbfs-tests is not set +# CONFIG_libhugetlbfs-dbg is not set +# CONFIG_libhugetlbfs-dev is not set + +# +# libical +# +# CONFIG_libical is not set +# CONFIG_libical-dev is not set +# CONFIG_libical-dbg is not set + +# +# libice +# +# CONFIG_libice is not set +# CONFIG_libice-dbg is not set +# CONFIG_libice-dev is not set + +# +# libid3tag +# +# CONFIG_libid3tag is not set +# CONFIG_libid3tag-dev is not set +# CONFIG_libid3tag-dbg is not set + +# +# libidn +# +# CONFIG_libidn is not set +# CONFIG_libidn-dbg is not set +# CONFIG_idn is not set +# CONFIG_libidn-dev is not set + +# +# libinput +# +# CONFIG_libinput is not set +# CONFIG_libinput-dev is not set +# CONFIG_libinput-dbg is not set + +# +# libjpeg-turbo +# +# CONFIG_libjpeg-turbo is not set +# CONFIG_jpeg-tools is not set +# CONFIG_libturbojpeg is not set +# CONFIG_libjpeg-turbo-dbg is not set +# CONFIG_libjpeg-turbo-dev is not set + +# +# libmali-xlnx +# +# CONFIG_libmali-xlnx is not set +# CONFIG_libmali-xlnx-dbg is not set +# CONFIG_libmali-xlnx-dev is not set + +# +# libmetal +# +# CONFIG_libmetal is not set +# CONFIG_libmetal-dev is not set +# CONFIG_libmetal-dbg is not set +# CONFIG_libmetal-demos is not set + +# +# libmpc +# +# CONFIG_libmpc is not set +# CONFIG_libmpc-dbg is not set +# CONFIG_libmpc-dev is not set + +# +# libnet +# +# CONFIG_libnet is not set +# CONFIG_libnet-dbg is not set +# CONFIG_libnet-dev is not set + +# +# libnewt +# +# CONFIG_libnewt is not set +# CONFIG_libnewt-dev is not set +# CONFIG_libnewt-dbg is not set +# CONFIG_whiptail is not set + +# +# libnotify +# +# CONFIG_libnotify is not set +# CONFIG_libnotify-dev is not set +# CONFIG_libnotify-dbg is not set + +# +# libnss-mdns +# +# CONFIG_libnss-mdns is not set +# CONFIG_libnss-mdns-dbg is not set +# CONFIG_libnss-mdns-dev is not set + +# +# libogg +# +# CONFIG_libogg is not set +# CONFIG_libogg-dev is not set +# CONFIG_libogg-dbg is not set + +# +# libomxil +# +# CONFIG_libomxil is not set +# CONFIG_libomxil-dev is not set +# CONFIG_libomxil-dbg is not set + +# +# libpciaccess +# +# CONFIG_libpciaccess is not set +# CONFIG_libpciaccess-dev is not set +# CONFIG_libpciaccess-dbg is not set + +# +# libpng +# +# CONFIG_libpng is not set +# CONFIG_libpng-dbg is not set +# CONFIG_libpng-dev is not set +# CONFIG_libpng-tools is not set + +# +# libproxy +# +# CONFIG_libproxy is not set +# CONFIG_libproxy-dbg is not set +# CONFIG_libproxy-dev is not set + +# +# libsamplerate0 +# +# CONFIG_libsamplerate0 is not set +# CONFIG_libsamplerate0-dev is not set +# CONFIG_libsamplerate0-dbg is not set + +# +# libsecret +# +# CONFIG_libsecret is not set +# CONFIG_libsecret-dbg is not set +# CONFIG_libsecret-dev is not set + +# +# libsm +# +# CONFIG_libsm is not set +# CONFIG_libsm-dev is not set +# CONFIG_libsm-dbg is not set + +# +# libtasn1 +# +# CONFIG_libtasn1 is not set +# CONFIG_libtasn1-dbg is not set +# CONFIG_libtasn1-dev is not set +# CONFIG_libtasn1-bin is not set + +# +# libtheora +# +# CONFIG_libtheora is not set +# CONFIG_libtheora-dev is not set +# CONFIG_libtheora-dbg is not set + +# +# libtool +# +# CONFIG_libtool is not set +# CONFIG_libtool-dev is not set +# CONFIG_libltdl is not set +# CONFIG_libtool-dbg is not set + +# +# liburcu +# +# CONFIG_liburcu is not set +# CONFIG_liburcu-dbg is not set +# CONFIG_liburcu-dev is not set + +# +# libusb-compat +# +# CONFIG_libusb-compat is not set +# CONFIG_libusb-compat-dbg is not set +# CONFIG_libusb-compat-dev is not set + +# +# libusb1 +# +# CONFIG_libusb1 is not set +# CONFIG_libusb1-dev is not set +# CONFIG_libusb1-dbg is not set + +# +# libvorbis +# +# CONFIG_libvorbis is not set +# CONFIG_libvorbis-dev is not set +# CONFIG_libvorbis-dbg is not set + +# +# libwebp +# +# CONFIG_libwebp is not set +# CONFIG_libwebp-dbg is not set +# CONFIG_libwebp-bin is not set +# CONFIG_libwebp-dev is not set + +# +# libx11 +# +# CONFIG_libx11 is not set +# CONFIG_libx11-xcb is not set +# CONFIG_libx11-dev is not set +# CONFIG_libx11-dbg is not set + +# +# libxau +# +# CONFIG_libxau is not set +# CONFIG_libxau-dbg is not set +# CONFIG_libxau-dev is not set + +# +# libxcomposite +# +# CONFIG_libxcomposite is not set +# CONFIG_libxcomposite-dbg is not set +# CONFIG_libxcomposite-dev is not set + +# +# libxcursor +# +# CONFIG_libxcursor is not set +# CONFIG_libxcursor-dbg is not set +# CONFIG_libxcursor-dev is not set + +# +# libxdamage +# +# CONFIG_libxdamage is not set +# CONFIG_libxdamage-dbg is not set +# CONFIG_libxdamage-dev is not set + +# +# libxdmcp +# +# CONFIG_libxdmcp is not set +# CONFIG_libxdmcp-dbg is not set +# CONFIG_libxdmcp-dev is not set + +# +# libxext +# +# CONFIG_libxext is not set +# CONFIG_libxext-dev is not set +# CONFIG_libxext-dbg is not set + +# +# libxfixes +# +# CONFIG_libxfixes is not set +# CONFIG_libxfixes-dev is not set +# CONFIG_libxfixes-dbg is not set + +# +# libxfont +# +# CONFIG_libxfont is not set +# CONFIG_libxfont-dev is not set +# CONFIG_libxfont-dbg is not set + +# +# libxft +# +# CONFIG_libxft is not set +# CONFIG_libxft-dbg is not set +# CONFIG_libxft-dev is not set + +# +# libxi +# +# CONFIG_libxi is not set +# CONFIG_libxi-dbg is not set +# CONFIG_libxi-dev is not set + +# +# libxinerama +# +# CONFIG_libxinerama is not set +# CONFIG_libxinerama-dbg is not set +# CONFIG_libxinerama-dev is not set + +# +# libxkbcommon +# +# CONFIG_libxkbcommon is not set +# CONFIG_libxkbcommon-dev is not set +# CONFIG_libxkbcommon-dbg is not set + +# +# libxkbfile +# +# CONFIG_libxkbfile is not set +# CONFIG_libxkbfile-dbg is not set +# CONFIG_libxkbfile-dev is not set + +# +# libxml-parser-perl +# +# CONFIG_libxml-parser-perl is not set +# CONFIG_libxml-parser-perl-dev is not set +# CONFIG_libxml-parser-perl-dbg is not set + +# +# libxml2 +# +# CONFIG_libxml2 is not set +# CONFIG_libxml2-python is not set +# CONFIG_libxml2-dbg is not set +# CONFIG_libxml2-dev is not set + +# +# libxmu +# +# CONFIG_libxmu is not set +# CONFIG_libxmu-dbg is not set +# CONFIG_libxmuu is not set +# CONFIG_libxmu-dev is not set + +# +# libxrandr +# +# CONFIG_libxrandr is not set +# CONFIG_libxrandr-dbg is not set +# CONFIG_libxrandr-dev is not set + +# +# libxrender +# +# CONFIG_libxrender is not set +# CONFIG_libxrender-dev is not set +# CONFIG_libxrender-dbg is not set + +# +# libxres +# +# CONFIG_libxres is not set +# CONFIG_libxres-dbg is not set +# CONFIG_libxres-dev is not set + +# +# libxslt +# +# CONFIG_libxslt is not set +# CONFIG_libxslt-dbg is not set +# CONFIG_libxslt-bin is not set +# CONFIG_libxslt-dev is not set + +# +# libxt +# +# CONFIG_libxt is not set +# CONFIG_libxt-dev is not set +# CONFIG_libxt-dbg is not set + +# +# libxtst +# +# CONFIG_libxtst is not set +# CONFIG_libxtst-dbg is not set +# CONFIG_libxtst-dev is not set + +# +# libxv +# +# CONFIG_libxv is not set +# CONFIG_libxv-dbg is not set +# CONFIG_libxv-dev is not set + +# +# libxxf86vm +# +# CONFIG_libxxf86vm is not set +# CONFIG_libxxf86vm-dbg is not set +# CONFIG_libxxf86vm-dev is not set + +# +# lzo +# +# CONFIG_lzo is not set +# CONFIG_lzo-dbg is not set +# CONFIG_lzo-dev is not set + +# +# mtdev +# +# CONFIG_mtdev is not set +# CONFIG_mtdev-dbg is not set +# CONFIG_mtdev-dev is not set + +# +# multimedia +# + +# +# alsa-lib +# +# CONFIG_alsa-lib is not set +# CONFIG_alsa-server is not set +# CONFIG_libasound is not set +# CONFIG_alsa-conf is not set +# CONFIG_alsa-lib-dbg is not set +# CONFIG_alsa-conf-base is not set +# CONFIG_alsa-lib-dev is not set +# CONFIG_alsa-oss is not set + +# +# libsndfile1 +# +# CONFIG_libsndfile1 is not set +# CONFIG_libsndfile1-dev is not set +# CONFIG_libsndfile1-bin is not set +# CONFIG_libsndfile1-dbg is not set + +# +# pulseaudio +# +# CONFIG_pulseaudio is not set +# CONFIG_pulseaudio-module-console-kit is not set +# CONFIG_pulseaudio-bash-completion is not set +# CONFIG_libpulse is not set +# CONFIG_pulseaudio-misc is not set +# CONFIG_pulseaudio-dev is not set +# CONFIG_libpulse-simple is not set +# CONFIG_pulseaudio-dbg is not set +# CONFIG_libpulsecommon is not set +# CONFIG_pulseaudio-server is not set +# CONFIG_libpulsecore is not set +# CONFIG_libpulse-mainloop-glib is not set + +# +# taglib +# +# CONFIG_taglib is not set +# CONFIG_taglib-dev is not set +# CONFIG_taglib-dbg is not set +# CONFIG_taglib-c is not set + +# +# ncurses +# +# CONFIG_ncurses is not set +# CONFIG_ncurses-terminfo is not set +# CONFIG_ncurses-dev is not set +# CONFIG_ncurses-terminfo-base is not set +# CONFIG_ncurses-tools is not set +# CONFIG_ncurses-dbg is not set + +# +# neon +# +# CONFIG_neon is not set +# CONFIG_neon-dbg is not set +# CONFIG_neon-dev is not set + +# +# nettle +# +# CONFIG_nettle is not set +# CONFIG_nettle-dbg is not set +# CONFIG_nettle-dev is not set + +# +# network +# + +# +# libnl +# +# CONFIG_libnl is not set +# CONFIG_libnl-dbg is not set +# CONFIG_libnl-idiag is not set +# CONFIG_libnl-dev is not set +# CONFIG_libnl-cli is not set +# CONFIG_libnl-nf is not set +# CONFIG_libnl-route is not set +# CONFIG_libnl-xfrm is not set +# CONFIG_libnl-genl is not set + +# +# libpcap +# +# CONFIG_libpcap is not set +# CONFIG_libpcap-dev is not set +# CONFIG_libpcap-dbg is not set + +# +# libsocketcan +# +# CONFIG_libsocketcan is not set +# CONFIG_libsocketcan-dev is not set +# CONFIG_libsocketcan-dbg is not set + +# +# libtirpc +# +# CONFIG_libtirpc is not set +# CONFIG_libtirpc-dbg is not set +# CONFIG_libtirpc-dev is not set + +# +# openssl +# +# CONFIG_openssl is not set +# CONFIG_openssl-bin is not set +# CONFIG_openssl-misc is not set +# CONFIG_openssl-conf is not set +# CONFIG_openssl-dbg is not set +# CONFIG_libcrypto is not set +# CONFIG_openssl-dev is not set +# CONFIG_libssl is not set +# CONFIG_openssl-engines is not set + +# +# open-amp +# +# CONFIG_open-amp is not set +# CONFIG_open-amp-dev is not set +# CONFIG_open-amp-dbg is not set +# CONFIG_open-amp-demos is not set + +# +# opencv +# +# CONFIG_opencv is not set +# CONFIG_opencv-dbg is not set +# CONFIG_opencv-apps is not set +# CONFIG_opencv-dev is not set +# CONFIG_opencv-samples is not set + +# +# pango +# +# CONFIG_pango is not set +# CONFIG_pango-dev is not set +# CONFIG_pango-dbg is not set + +# +# popt +# +# CONFIG_popt is not set +# CONFIG_popt-dev is not set +# CONFIG_popt-dbg is not set + +# +# readline +# +# CONFIG_readline is not set +# CONFIG_readline-dev is not set +# CONFIG_readline-dbg is not set + +# +# sbc +# +# CONFIG_sbc is not set +# CONFIG_sbc-dev is not set +# CONFIG_sbc-dbg is not set + +# +# slang +# +# CONFIG_slang is not set +# CONFIG_slang-dev is not set +# CONFIG_slang-dbg is not set + +# +# speex +# +# CONFIG_speex is not set +# CONFIG_speex-dev is not set +# CONFIG_speex-dbg is not set + +# +# speexdsp +# +# CONFIG_speexdsp is not set +# CONFIG_speexdsp-dev is not set +# CONFIG_speexdsp-dbg is not set + +# +# sqlite3 +# +# CONFIG_sqlite3 is not set +# CONFIG_libsqlite3 is not set +# CONFIG_libsqlite3-dev is not set +# CONFIG_sqlite3-dbg is not set + +# +# startup-notification +# +# CONFIG_startup-notification is not set +# CONFIG_startup-notification-dev is not set +# CONFIG_startup-notification-dbg is not set + +# +# tremor +# +# CONFIG_tremor is not set +# CONFIG_tremor-dbg is not set +# CONFIG_tremor-dev is not set + +# +# which +# +# CONFIG_which is not set +# CONFIG_which-dev is not set +# CONFIG_which-dbg is not set + +# +# xrt +# +# CONFIG_xrt is not set +# CONFIG_xrt-dev is not set +# CONFIG_xrt-dbg is not set + +# +# zocl +# +# CONFIG_zocl is not set +# CONFIG_zocl-dev is not set +# CONFIG_zocl-dbg is not set + +# +# opencl-clhpp +# +# CONFIG_opencl-clhpp-dev is not set + +# +# opencl-headers +# +# CONFIG_opencl-headers is not set + +# +# protobuf +# +# CONFIG_protobuf is not set + +# +# zlib +# +# CONFIG_zlib is not set +# CONFIG_zlib-dev is not set +# CONFIG_zlib-dbg is not set + +# +# misc +# + +# +# alsa-state +# +# CONFIG_alsa-state is not set +# CONFIG_alsa-state-dev is not set +# CONFIG_alsa-states is not set +# CONFIG_alsa-state-dbg is not set + +# +# alsa-utils-scripts +# +# CONFIG_alsa-utils-scripts is not set + +# +# apache2 +# +# CONFIG_apache2 is not set +# CONFIG_apache2-dbg is not set +# CONFIG_apache2-dev is not set + +# +# at-spi2-atk +# +# CONFIG_at-spi2-atk is not set +# CONFIG_at-spi2-atk-dbg is not set +# CONFIG_at-spi2-atk-dev is not set +# CONFIG_at-spi2-atk-gtk2 is not set +# CONFIG_at-spi2-atk-gnome is not set + +# +# at-spi2-core +# +# CONFIG_at-spi2-core is not set +# CONFIG_at-spi2-core-dev is not set +# CONFIG_at-spi2-core-dbg is not set + +# +# babeltrace +# +# CONFIG_babeltrace is not set +# CONFIG_babeltrace-dbg is not set +# CONFIG_babeltrace-dev is not set + +# +# blktool +# +# CONFIG_blktool is not set +# CONFIG_blktool-dbg is not set +# CONFIG_blktool-dev is not set + +# +# blktrace +# +# CONFIG_blktrace is not set +# CONFIG_blktrace-dbg is not set +# CONFIG_blktrace-dev is not set + +# +# ca-certificates +# +# CONFIG_ca-certificates is not set +# CONFIG_ca-certificates-dev is not set +# CONFIG_ca-certificates-dbg is not set + +# +# chrpath +# +# CONFIG_chrpath is not set +# CONFIG_chrpath-dev is not set +# CONFIG_chrpath-dbg is not set + +# +# connman +# +# CONFIG_connman is not set +# CONFIG_connman-tests is not set +# CONFIG_connman-dbg is not set +# CONFIG_connman-dev is not set +# CONFIG_connman-wait-online is not set +# CONFIG_connman-client is not set +# CONFIG_connman-tools is not set + +# +# connman-conf +# +# CONFIG_connman-conf-dbg is not set + +# +# consolekit +# +# CONFIG_consolekit is not set +# CONFIG_consolekit-dbg is not set +# CONFIG_consolekit-dev is not set + +# +# coreutils +# +# CONFIG_coreutils is not set +# CONFIG_coreutils-dbg is not set +# CONFIG_coreutils-dev is not set + +# +# cpufrequtils +# +# CONFIG_cpufrequtils is not set +# CONFIG_cpufrequtils-dbg is not set +# CONFIG_cpufrequtils-dev is not set + +# +# cryptodev-linux +# +# CONFIG_cryptodev-linux is not set +# CONFIG_cryptodev-linux-dev is not set +# CONFIG_cryptodev-linux-dbg is not set + +# +# dstat +# +# CONFIG_dstat is not set +# CONFIG_dstat-dev is not set +# CONFIG_dstat-dbg is not set + +# +# encodings +# +# CONFIG_encodings is not set +# CONFIG_encodings-dev is not set +# CONFIG_encodings-dbg is not set + +# +# epiphany +# +# CONFIG_epiphany is not set +# CONFIG_epiphany-dev is not set +# CONFIG_epiphany-dbg is not set + +# +# eudev +# +# CONFIG_eudev is not set +# CONFIG_libudev is not set +# CONFIG_eudev-hwdb is not set +# CONFIG_eudev-dev is not set +# CONFIG_eudev-dbg is not set +CONFIG_udev-extraconf=y + +# +# fbset +# +# CONFIG_fbset is not set +# CONFIG_fbset-dev is not set +# CONFIG_fbset-dbg is not set + +# +# fbset-modes +# +# CONFIG_fbset-modes is not set +# CONFIG_fbset-modes-dbg is not set +# CONFIG_fbset-modes-dev is not set + +# +# font-util +# +# CONFIG_font-util is not set +# CONFIG_font-util-dev is not set +# CONFIG_font-util-dbg is not set + +# +# gcc-runtime +# +# CONFIG_libstdcPLUSPLUS-dev is not set +# CONFIG_libstdcPLUSPLUS is not set + +# +# gcr +# +# CONFIG_gcr is not set +# CONFIG_gcr-dev is not set +# CONFIG_gcr-dbg is not set + +# +# gdb +# +# CONFIG_gdb is not set +# CONFIG_gdb-dev is not set +# CONFIG_gdbserver is not set +# CONFIG_gdb-dbg is not set + +# +# glib-2.0 +# +# CONFIG_glib-2.0 is not set +# CONFIG_glib-2.0-dbg is not set +# CONFIG_glib-2.0-dev is not set +# CONFIG_glib-2.0-codegen is not set +# CONFIG_glib-2.0-bash-completion is not set +# CONFIG_glib-2.0-utils is not set + +# +# glibc +# +# CONFIG_glibc is not set +# CONFIG_glibc-dev is not set +# CONFIG_glibc-dbg is not set +# CONFIG_ldd is not set + +# +# gnome-desktop-testing +# +# CONFIG_gnome-desktop-testing is not set +# CONFIG_gnome-desktop-testing-dbg is not set +# CONFIG_gnome-desktop-testing-dev is not set + +# +# gnutls +# +# CONFIG_gnutls is not set +# CONFIG_gnutls-bin is not set +# CONFIG_gnutls-xx is not set +# CONFIG_gnutls-dbg is not set +# CONFIG_gnutls-openssl is not set +# CONFIG_gnutls-dev is not set + +# +# gsettings-desktop-schemas +# +# CONFIG_gsettings-desktop-schemas is not set +# CONFIG_gsettings-desktop-schemas-dev is not set +# CONFIG_gsettings-desktop-schemas-dbg is not set + +# +# gst-player +# +# CONFIG_gst-player is not set + +# +# gstreamer1.0-meta-base +# +# CONFIG_gstreamer1.0-meta-base is not set +# CONFIG_gstreamer1.0-meta-video is not set +# CONFIG_gstreamer1.0-meta-video-dbg is not set +# CONFIG_gstreamer1.0-meta-debug-dev is not set +# CONFIG_gstreamer1.0-meta-x11-base-dev is not set +# CONFIG_gstreamer1.0-meta-audio-dbg is not set +# CONFIG_gstreamer1.0-meta-audio is not set +# CONFIG_gstreamer1.0-meta-x11-base is not set +# CONFIG_gstreamer1.0-meta-video-dev is not set +# CONFIG_gstreamer1.0-meta-x11-base-dbg is not set +# CONFIG_gstreamer1.0-meta-base-dev is not set +# CONFIG_gstreamer1.0-meta-base-dbg is not set +# CONFIG_gstreamer1.0-meta-debug is not set +# CONFIG_gstreamer1.0-meta-audio-dev is not set +# CONFIG_gstreamer1.0-meta-debug-dbg is not set + +# +# gstreamer1.0-plugins-bad +# +# CONFIG_gstreamer1.0-plugins-bad is not set +# CONFIG_gstreamer1.0-plugins-bad-meta is not set +# CONFIG_gstreamer1.0-plugins-bad-dev is not set +# CONFIG_gstreamer1.0-plugins-bad-dbg is not set + +# +# gstreamer1.0-plugins-base +# +# CONFIG_gstreamer1.0-plugins-base is not set +# CONFIG_gstreamer1.0-plugins-base-apps is not set +# CONFIG_gstreamer1.0-plugins-base-dev is not set +# CONFIG_gstreamer1.0-plugins-base-dbg is not set +# CONFIG_gstreamer1.0-plugins-base-meta is not set + +# +# gstreamer1.0-plugins-good +# +# CONFIG_gstreamer1.0-plugins-good is not set +# CONFIG_gstreamer1.0-plugins-good-dev is not set +# CONFIG_gstreamer1.0-plugins-good-dbg is not set +# CONFIG_gstreamer1.0-plugins-good-meta is not set + +# +# hicolor-icon-theme +# +# CONFIG_hicolor-icon-theme is not set +# CONFIG_hicolor-icon-theme-dev is not set +# CONFIG_hicolor-icon-theme-dbg is not set + +# +# hdmi-module +# +# CONFIG_kernel-module-hdmi is not set + +# +# icu +# +# CONFIG_icu is not set +# CONFIG_icu-dbg is not set +# CONFIG_icu-dev is not set +# CONFIG_libicudata is not set +# CONFIG_libicuio is not set +# CONFIG_libicui18n is not set +# CONFIG_libicuuc is not set +# CONFIG_libicutu is not set + +# +# iotop +# +# CONFIG_iotop is not set +# CONFIG_iotop-dev is not set +# CONFIG_iotop-dbg is not set + +# +# iptables +# +# CONFIG_iptables is not set +# CONFIG_iptables-dev is not set +# CONFIG_iptables-dbg is not set + +# +# iptraf +# +# CONFIG_iptraf is not set + +# +# iso-codes +# +# CONFIG_iso-codes is not set +# CONFIG_iso-codes-dbg is not set +# CONFIG_iso-codes-dev is not set + +# +# json-c +# +# CONFIG_json-c is not set +# CONFIG_json-c-dev is not set +# CONFIG_json-c-dbg is not set + +# +# l3afpad +# +# CONFIG_l3afpad is not set +# CONFIG_l3afpad-dev is not set +# CONFIG_l3afpad-dbg is not set + +# +# lttng-ust +# +# CONFIG_lttng-ust is not set +# CONFIG_lttng-ust-dev is not set +# CONFIG_lttng-ust-dbg is not set +# CONFIG_lttng-ust-bin is not set + +# +# m4 +# +# CONFIG_m4 is not set +# CONFIG_m4-dev is not set +# CONFIG_m4-dbg is not set + +# +# matchbox-config-gtk +# +# CONFIG_matchbox-config-gtk is not set +# CONFIG_matchbox-config-gtk-dbg is not set +# CONFIG_matchbox-config-gtk-dev is not set + +# +# matchbox-panel-2 +# +# CONFIG_matchbox-panel-2 is not set +# CONFIG_matchbox-panel-2-dbg is not set +# CONFIG_matchbox-panel-2-dev is not set + +# +# mdadm +# +# CONFIG_mdadm is not set +# CONFIG_mdadm-dbg is not set +# CONFIG_mdadm-dev is not set + +# +# mesa-gl +# +# CONFIG_mesa-gl-dev is not set +# CONFIG_libgl-mesa is not set +# CONFIG_mesa-megadriver is not set +# CONFIG_libglapi-dev is not set +# CONFIG_libglapi is not set +# CONFIG_libgl-mesa-dev is not set +# CONFIG_mesa-gl-dbg is not set + +# +# mkfontdir +# +# CONFIG_mkfontdir is not set + +# +# mkfontscale +# +# CONFIG_mkfontscale is not set +# CONFIG_mkfontscale-dbg is not set +# CONFIG_mkfontscale-dev is not set + +# +# net-tools +# +CONFIG_net-tools=y +# CONFIG_net-tools-dbg is not set +# CONFIG_net-tools-dev is not set + +# +# nicstat +# +# CONFIG_nicstat is not set +# CONFIG_nicstat-dbg is not set +# CONFIG_nicstat-dev is not set + +# +# ofono +# +# CONFIG_ofono is not set +# CONFIG_ofono-dbg is not set +# CONFIG_ofono-dev is not set +# CONFIG_ofono-tests is not set + +# +# openamp-fw-echo-testd +# +# CONFIG_openamp-fw-echo-testd is not set +# CONFIG_openamp-fw-echo-testd-dev is not set +# CONFIG_openamp-fw-echo-testd-dbg is not set + +# +# openamp-fw-mat-muld +# +# CONFIG_openamp-fw-mat-muld is not set +# CONFIG_openamp-fw-mat-muld-dev is not set +# CONFIG_openamp-fw-mat-muld-dbg is not set + +# +# openamp-fw-rpc-demo +# +# CONFIG_openamp-fw-rpc-demo is not set +# CONFIG_openamp-fw-rpc-demo-dbg is not set +# CONFIG_openamp-fw-rpc-demo-dev is not set + +# +# opkg-arch-config +# +# CONFIG_opkg-arch-config is not set +# CONFIG_opkg-arch-config-dbg is not set +# CONFIG_opkg-arch-config-dev is not set + +# +# orc +# +# CONFIG_orc is not set +# CONFIG_orc-dbg is not set +# CONFIG_orc-dev is not set + +# +# p11-kit +# +# CONFIG_p11-kit is not set +# CONFIG_p11-kit-dbg is not set +# CONFIG_p11-kit-dev is not set + +# +# packagegroup-core-boot +# +CONFIG_packagegroup-core-boot=y +# CONFIG_packagegroup-core-boot-dev is not set +# CONFIG_packagegroup-core-boot-dbg is not set + +# +# packagegroup-core-buildessential +# +# CONFIG_packagegroup-core-buildessential is not set +# CONFIG_packagegroup-core-buildessential-dbg is not set +# CONFIG_packagegroup-core-buildessential-dev is not set + +# +# packagegroup-core-sdk +# +# CONFIG_packagegroup-core-sdk is not set +# CONFIG_packagegroup-core-sdk-dbg is not set +# CONFIG_packagegroup-core-sdk-dev is not set + +# +# packagegroup-core-ssh-dropbear +# +CONFIG_packagegroup-core-ssh-dropbear=y +# CONFIG_packagegroup-core-ssh-dropbear-dev is not set +# CONFIG_packagegroup-core-ssh-dropbear-dbg is not set + +# +# packagegroup-core-standalone-sdk-target +# +# CONFIG_packagegroup-core-standalone-sdk-target is not set +# CONFIG_packagegroup-core-standalone-sdk-target-dbg is not set +# CONFIG_packagegroup-core-standalone-sdk-target-dev is not set + +# +# packagegroup-core-tools-debug +# +# CONFIG_packagegroup-core-tools-debug is not set +# CONFIG_packagegroup-core-tools-debug-dev is not set +# CONFIG_packagegroup-core-tools-debug-dbg is not set + +# +# packagegroup-core-tools-profile +# +# CONFIG_packagegroup-core-tools-profile is not set +# CONFIG_packagegroup-core-tools-profile-dev is not set +# CONFIG_packagegroup-core-tools-profile-dbg is not set + +# +# packagegroup-core-tools-testapps +# +# CONFIG_packagegroup-core-tools-testapps is not set +# CONFIG_packagegroup-core-tools-testapps-dev is not set +# CONFIG_packagegroup-core-tools-testapps-dbg is not set + +# +# packagegroup-core-x11 +# +# CONFIG_packagegroup-core-x11 is not set +# CONFIG_packagegroup-core-x11-utils-dbg is not set +# CONFIG_packagegroup-core-x11-utils is not set +# CONFIG_packagegroup-core-x11-utils-dev is not set +# CONFIG_packagegroup-core-x11-dev is not set +# CONFIG_packagegroup-core-x11-dbg is not set + +# +# packagegroup-core-x11-base +# +# CONFIG_packagegroup-core-x11-base is not set +# CONFIG_packagegroup-core-x11-base-dev is not set +# CONFIG_packagegroup-core-x11-base-dbg is not set + +# +# packagegroup-core-x11-xserver +# +# CONFIG_packagegroup-core-x11-xserver is not set +# CONFIG_packagegroup-core-x11-xserver-dev is not set +# CONFIG_packagegroup-core-x11-xserver-dbg is not set + +# +# packagegroup-self-hosted +# +# CONFIG_packagegroup-self-hosted is not set +# CONFIG_packagegroup-self-hosted-debug-dbg is not set +# CONFIG_packagegroup-self-hosted-dev is not set +# CONFIG_packagegroup-self-hosted-debug is not set +# CONFIG_packagegroup-self-hosted-sdk is not set +# CONFIG_packagegroup-self-hosted-extended-dbg is not set +# CONFIG_packagegroup-self-hosted-graphics-dbg is not set +# CONFIG_packagegroup-self-hosted-extended is not set +# CONFIG_packagegroup-self-hosted-host-tools-dev is not set +# CONFIG_packagegroup-self-hosted-debug-dev is not set +# CONFIG_packagegroup-self-hosted-sdk-dbg is not set +# CONFIG_packagegroup-self-hosted-sdk-dev is not set +# CONFIG_packagegroup-self-hosted-extended-dev is not set +# CONFIG_packagegroup-self-hosted-graphics is not set +# CONFIG_packagegroup-self-hosted-host-tools-dbg is not set +# CONFIG_packagegroup-self-hosted-dbg is not set +# CONFIG_packagegroup-self-hosted-host-tools is not set +# CONFIG_packagegroup-self-hosted-graphics-dev is not set + +# +# perf +# +# CONFIG_perf is not set +# CONFIG_perf-python is not set +# CONFIG_perf-dbg is not set +# CONFIG_perf-dev is not set +# CONFIG_perf-tests is not set + +# +# pixman +# +# CONFIG_pixman is not set +# CONFIG_pixman-dbg is not set +# CONFIG_pixman-dev is not set + +# +# powertop +# +# CONFIG_powertop is not set +# CONFIG_powertop-dbg is not set +# CONFIG_powertop-dev is not set + +# +# ptest-runner +# +# CONFIG_ptest-runner is not set +# CONFIG_ptest-runner-dev is not set +# CONFIG_ptest-runner-dbg is not set + +# +# python3 +# +# CONFIG_python3 is not set +# CONFIG_python3-crypt is not set +# CONFIG_python3-unixadmin is not set +# CONFIG_python3-io is not set +# CONFIG_python3-pydoc is not set +# CONFIG_python3-codecs is not set +# CONFIG_python3-pprint is not set +# CONFIG_python3-datetime is not set +# CONFIG_python3-2to3 is not set +# CONFIG_python3-modules is not set +# CONFIG_python3-xml is not set +# CONFIG_python3-numbers is not set +# CONFIG_python3-pyvenv is not set +# CONFIG_python3-tests is not set +# CONFIG_python3-netclient is not set +# CONFIG_python3-netserver is not set +# CONFIG_python3-math is not set +# CONFIG_python3-asyncio is not set +# CONFIG_python3-tkinter is not set +# CONFIG_python3-compression is not set +# CONFIG_python3-gdbm is not set +# CONFIG_python3-idle is not set +# CONFIG_python3-core is not set +# CONFIG_python3-smtpd is not set +# CONFIG_python3-resource is not set +# CONFIG_python3-terminal is not set +# CONFIG_python3-shell is not set +# CONFIG_python3-db is not set +# CONFIG_python3-threading is not set +# CONFIG_python3-email is not set +# CONFIG_python3-stringold is not set +# CONFIG_python3-unittest is not set +# CONFIG_python3-misc is not set +# CONFIG_python3-mailbox is not set +# CONFIG_python3-pkgutil is not set +# CONFIG_python3-mmap is not set +# CONFIG_python3-json is not set +# CONFIG_python3-audio is not set +# CONFIG_python3-distutils is not set +# CONFIG_python3-mime is not set +# CONFIG_python3-multiprocessing is not set +# CONFIG_python3-html is not set +# CONFIG_python3-image is not set +# CONFIG_python3-difflib is not set +# CONFIG_python3-dev is not set +# CONFIG_python3-syslog is not set +# CONFIG_python3-curses is not set +# CONFIG_libpython3 is not set +# CONFIG_python3-logging is not set +# CONFIG_python3-profile is not set +# CONFIG_python3-xmlrpc is not set +# CONFIG_python3-ctypes is not set +# CONFIG_python3-sqlite3 is not set +# CONFIG_python3-fcntl is not set +# CONFIG_python3-compile is not set +# CONFIG_python3-pickle is not set +# CONFIG_python3-dbg is not set +# CONFIG_python3-debugger is not set + +# +# python3-async +# +# CONFIG_python3-async is not set +# CONFIG_python3-async-dbg is not set +# CONFIG_python3-async-dev is not set + +# +# python3-git +# +# CONFIG_python3-git is not set +# CONFIG_python3-git-dev is not set +# CONFIG_python3-git-dbg is not set + +# +# python3-gitdb +# +# CONFIG_python3-gitdb is not set +# CONFIG_python3-gitdb-dev is not set +# CONFIG_python3-gitdb-dbg is not set + +# +# python3-setuptools +# +# CONFIG_python3-setuptools is not set +# CONFIG_python3-setuptools-dbg is not set +# CONFIG_python3-setuptools-dev is not set + +# +# python3-smmap +# +# CONFIG_python3-smmap is not set +# CONFIG_python3-smmap-dev is not set +# CONFIG_python3-smmap-dbg is not set + +# +# qemu +# +# CONFIG_qemu is not set +# CONFIG_qemu-dev is not set +# CONFIG_qemu-dbg is not set + +# +# qtbase +# +# CONFIG_qtbase is not set +# CONFIG_qtbase-plugins is not set +# CONFIG_qtbase-dev is not set +# CONFIG_qtbase-dbg is not set +# CONFIG_qtbase-tools is not set +# CONFIG_qtbase-examples is not set +# CONFIG_qtbase-mkspecs is not set + +# +# qtcharts +# +# CONFIG_qtcharts is not set +# CONFIG_qtcharts-qmlplugins is not set +# CONFIG_qtcharts-mkspecs is not set +# CONFIG_qtcharts-dbg is not set +# CONFIG_qtcharts-dev is not set +# CONFIG_qtcharts-qmldesigner is not set + +# +# qtconnectivity +# +# CONFIG_qtconnectivity is not set +# CONFIG_qtconnectivity-qmlplugins is not set +# CONFIG_qtconnectivity-tools is not set +# CONFIG_qtconnectivity-mkspecs is not set +# CONFIG_qtconnectivity-dev is not set +# CONFIG_qtconnectivity-dbg is not set + +# +# qtdeclarative +# +# CONFIG_qtdeclarative is not set +# CONFIG_qtdeclarative-tools is not set +# CONFIG_qtdeclarative-mkspecs is not set +# CONFIG_qtdeclarative-dbg is not set +# CONFIG_qtdeclarative-qmlplugins is not set +# CONFIG_qtdeclarative-dev is not set + +# +# qtimageformats +# +# CONFIG_qtimageformats is not set +# CONFIG_qtimageformats-dev is not set +# CONFIG_qtimageformats-dbg is not set +# CONFIG_qtimageformats-plugins is not set + +# +# qtlocation +# +# CONFIG_qtlocation is not set +# CONFIG_qtlocation-qmlplugins is not set +# CONFIG_qtlocation-mkspecs is not set +# CONFIG_qtlocation-dev is not set +# CONFIG_qtlocation-plugins is not set +# CONFIG_qtlocation-dbg is not set + +# +# qtmultimedia +# +# CONFIG_qtmultimedia is not set +# CONFIG_qtmultimedia-dbg is not set +# CONFIG_qtmultimedia-plugins is not set +# CONFIG_qtmultimedia-mkspecs is not set +# CONFIG_qtmultimedia-dev is not set +# CONFIG_qtmultimedia-qmlplugins is not set + +# +# qtquickcontrols +# +# CONFIG_qtquickcontrols is not set +# CONFIG_qtquickcontrols-dev is not set +# CONFIG_qtquickcontrols-qmldesigner is not set +# CONFIG_qtquickcontrols-qmlplugins is not set +# CONFIG_qtquickcontrols-dbg is not set + +# +# qtscript +# +# CONFIG_qtscript is not set +# CONFIG_qtscript-dbg is not set +# CONFIG_qtscript-mkspecs is not set +# CONFIG_qtscript-dev is not set + +# +# qtsensors +# +# CONFIG_qtsensors is not set +# CONFIG_qtsensors-qmlplugins is not set +# CONFIG_qtsensors-mkspecs is not set +# CONFIG_qtsensors-plugins is not set +# CONFIG_qtsensors-dbg is not set +# CONFIG_qtsensors-dev is not set + +# +# qtserialport +# +# CONFIG_qtserialport is not set +# CONFIG_qtserialport-mkspecs is not set +# CONFIG_qtserialport-dev is not set +# CONFIG_qtserialport-dbg is not set + +# +# qtsvg +# +# CONFIG_qtsvg is not set +# CONFIG_qtsvg-dev is not set +# CONFIG_qtsvg-dbg is not set +# CONFIG_qtsvg-mkspecs is not set +# CONFIG_qtsvg-plugins is not set + +# +# qtsystems +# +# CONFIG_qtsystems is not set +# CONFIG_qtsystems-dev is not set +# CONFIG_qtsystems-mkspecs is not set +# CONFIG_qtsystems-qmlplugins is not set +# CONFIG_qtsystems-dbg is not set +# CONFIG_qtsystems-tools is not set + +# +# qttools +# +# CONFIG_qttools is not set +# CONFIG_qttools-dbg is not set +# CONFIG_qttools-dev is not set +# CONFIG_qttools-tools is not set +# CONFIG_qttools-mkspecs is not set +# CONFIG_qttools-plugins is not set + +# +# qttranslations +# +# CONFIG_qttranslations is not set +# CONFIG_qttranslations-qtwebengine is not set +# CONFIG_qttranslations-qthelp is not set +# CONFIG_qttranslations-qtbase is not set +# CONFIG_qttranslations-dbg is not set +# CONFIG_qttranslations-dev is not set +# CONFIG_qttranslations-qtscript is not set +# CONFIG_qttranslations-qtdeclarative is not set +# CONFIG_qttranslations-assistant is not set +# CONFIG_qttranslations-qtwebsockets is not set +# CONFIG_qttranslations-linguist is not set +# CONFIG_qttranslations-qtserialport is not set +# CONFIG_qttranslations-qtmultimedia is not set +# CONFIG_qttranslations-qtconnectivity is not set +# CONFIG_qttranslations-qtlocation is not set +# CONFIG_qttranslations-qtxmlpatterns is not set +# CONFIG_qttranslations-qtquickcontrols is not set +# CONFIG_qttranslations-designer is not set +# CONFIG_qttranslations-qtquickcontrols2 is not set + +# +# qtwebchannel +# +# CONFIG_qtwebchannel is not set +# CONFIG_qtwebchannel-mkspecs is not set +# CONFIG_qtwebchannel-dbg is not set +# CONFIG_qtwebchannel-qmlplugins is not set +# CONFIG_qtwebchannel-dev is not set + +# +# qtwebkit +# +# CONFIG_qtwebkit is not set +# CONFIG_qtwebkit-qmlplugins is not set +# CONFIG_qtwebkit-mkspecs is not set +# CONFIG_qtwebkit-dbg is not set +# CONFIG_qtwebkit-dev is not set + +# +# qtwebsockets +# +# CONFIG_qtwebsockets is not set +# CONFIG_qtwebsockets-qmlplugins is not set +# CONFIG_qtwebsockets-dbg is not set +# CONFIG_qtwebsockets-dev is not set +# CONFIG_qtwebsockets-mkspecs is not set + +# +# qtxmlpatterns +# +# CONFIG_qtxmlpatterns is not set +# CONFIG_qtxmlpatterns-dev is not set +# CONFIG_qtxmlpatterns-mkspecs is not set +# CONFIG_qtxmlpatterns-examples is not set +# CONFIG_qtxmlpatterns-dbg is not set +# CONFIG_qtxmlpatterns-tools is not set + +# +# rgb +# +# CONFIG_rgb is not set +# CONFIG_rgb-dev is not set +# CONFIG_rgb-dbg is not set + +# +# rpm +# +# CONFIG_rpm is not set +# CONFIG_rpm-build is not set +# CONFIG_rpm-dbg is not set +# CONFIG_rpm-dev is not set + +# +# rpmsg-echo-test +# +# CONFIG_rpmsg-echo-test is not set +# CONFIG_rpmsg-echo-test-dbg is not set +# CONFIG_rpmsg-echo-test-dev is not set + +# +# rpmsg-mat-mul +# +# CONFIG_rpmsg-mat-mul is not set +# CONFIG_rpmsg-mat-mul-dev is not set +# CONFIG_rpmsg-mat-mul-dbg is not set + +# +# rpmsg-proxy-app +# +# CONFIG_rpmsg-proxy-app is not set +# CONFIG_rpmsg-proxy-app-dbg is not set +# CONFIG_rpmsg-proxy-app-dev is not set + +# +# serf +# +# CONFIG_serf is not set +# CONFIG_serf-dev is not set +# CONFIG_serf-dbg is not set + +# +# sysfsutils +# +# CONFIG_sysfsutils is not set +# CONFIG_libsysfs is not set +# CONFIG_sysfsutils-dbg is not set +# CONFIG_sysfsutils-dev is not set + +# +# sysvinit-inittab +# +# CONFIG_sysvinit-inittab is not set +# CONFIG_sysvinit-inittab-dev is not set +# CONFIG_sysvinit-inittab-dbg is not set + +# +# tbb +# +# CONFIG_tbb is not set +# CONFIG_tbb-dbg is not set +# CONFIG_tbb-dev is not set + +# +# tcf-agent +# +CONFIG_tcf-agent=y +# CONFIG_tcf-agent-dev is not set +# CONFIG_tcf-agent-dbg is not set + +# +# tiff +# +# CONFIG_tiff is not set +# CONFIG_tiffxx is not set +# CONFIG_tiff-dbg is not set +# CONFIG_tiff-utils is not set +# CONFIG_tiff-dev is not set + +# +# tpm2 +# + +# +# tpm2-abrmd +# +# CONFIG_tpm2-abrmd is not set +# CONFIG_tpm2-abrmd-dev is not set +# CONFIG_tpm2-abrmd-dbg is not set + +# +# tpm2-pkcs11 +# +# CONFIG_tpm2-pkcs11 is not set +# CONFIG_tpm2-pkcs11-dev is not set +# CONFIG_tpm2-pkcs11-dbg is not set + +# +# tpm2-tools +# +# CONFIG_tpm2-tools is not set +# CONFIG_tpm2-tools-dev is not set +# CONFIG_tpm2-tools-dbg is not set + +# +# tpm2-tss +# +# CONFIG_tpm2-tss is not set +# CONFIG_tpm2-tss-dbg is not set + +# +# tpm2-tss-engine +# +# CONFIG_tpm2-tss-engine is not set +# CONFIG_tpm2-tss-engine-dev is not set +# CONFIG_tpm2-tss-engine-dbg is not set + +# +# util-macros +# +# CONFIG_util-macros is not set +# CONFIG_util-macros-dbg is not set +# CONFIG_util-macros-dev is not set + +# +# v4l-utils +# +# CONFIG_v4l-utils is not set +# CONFIG_libv4l is not set +# CONFIG_ir-keytable is not set +# CONFIG_media-ctl is not set +# CONFIG_v4l-utils-dbg is not set +# CONFIG_rc-keymaps is not set +# CONFIG_v4l-utils-dev is not set +# CONFIG_libv4l-dev is not set + +# +# valgrind +# +# CONFIG_valgrind is not set +# CONFIG_valgrind-dbg is not set +# CONFIG_valgrind-dev is not set + +# +# vte +# +# CONFIG_vte is not set +# CONFIG_vte-dbg is not set +# CONFIG_vte-dev is not set +# CONFIG_libvte is not set + +# +# watchdog +# +# CONFIG_watchdog is not set +# CONFIG_watchdog-dbg is not set +# CONFIG_watchdog-dev is not set +# CONFIG_watchdog-keepalive is not set + +# +# watchdog-config +# +# CONFIG_watchdog-config is not set +# CONFIG_watchdog-config-dbg is not set +# CONFIG_watchdog-config-dev is not set + +# +# watchdog-init +# +CONFIG_watchdog-init=y + +# +# webkitgtk +# +# CONFIG_webkitgtk is not set +# CONFIG_webkitgtk-dbg is not set +# CONFIG_webkitgtk-dev is not set + +# +# x11perf +# +# CONFIG_x11perf is not set +# CONFIG_x11perf-dev is not set +# CONFIG_x11perf-dbg is not set + +# +# x264 +# +# CONFIG_x264 is not set +# CONFIG_x264-dev is not set +# CONFIG_x264-dbg is not set +# CONFIG_x264-bin is not set + +# +# xauth +# +# CONFIG_xauth is not set +# CONFIG_xauth-dbg is not set +# CONFIG_xauth-dev is not set + +# +# xcb-util-image +# +# CONFIG_xcb-util-image is not set +# CONFIG_xcb-util-image-dbg is not set +# CONFIG_xcb-util-image-dev is not set + +# +# xcb-util-keysyms +# +# CONFIG_xcb-util-keysyms is not set +# CONFIG_xcb-util-keysyms-dev is not set +# CONFIG_xcb-util-keysyms-dbg is not set + +# +# xcb-util-renderutil +# +# CONFIG_xcb-util-renderutil is not set +# CONFIG_xcb-util-renderutil-dev is not set +# CONFIG_xcb-util-renderutil-dbg is not set + +# +# xcb-util-wm +# +# CONFIG_xcb-util-wm is not set +# CONFIG_xcb-util-wm-dbg is not set +# CONFIG_xcb-util-wm-dev is not set + +# +# xdg-utils +# +# CONFIG_xdg-utils is not set +# CONFIG_xdg-utils-dev is not set +# CONFIG_xdg-utils-dbg is not set + +# +# xdpyinfo +# +# CONFIG_xdpyinfo is not set +# CONFIG_xdpyinfo-dev is not set +# CONFIG_xdpyinfo-dbg is not set + +# +# xf86-input-evdev +# +# CONFIG_xf86-input-evdev is not set +# CONFIG_xf86-input-evdev-dbg is not set +# CONFIG_xf86-input-evdev-dev is not set + +# +# xf86-input-keyboard +# +# CONFIG_xf86-input-keyboard is not set +# CONFIG_xf86-input-keyboard-dev is not set +# CONFIG_xf86-input-keyboard-dbg is not set + +# +# xf86-input-mouse +# +# CONFIG_xf86-input-mouse is not set +# CONFIG_xf86-input-mouse-dbg is not set +# CONFIG_xf86-input-mouse-dev is not set + +# +# xf86-video-armsoc +# +# CONFIG_xf86-video-armsoc is not set +# CONFIG_xf86-video-armsoc-dbg is not set +# CONFIG_xf86-video-armsoc-dev is not set + +# +# xf86-video-fbdev +# +# CONFIG_xf86-video-fbdev is not set +# CONFIG_xf86-video-fbdev-dbg is not set +# CONFIG_xf86-video-fbdev-dev is not set + +# +# xhost +# +# CONFIG_xhost is not set +# CONFIG_xhost-dbg is not set +# CONFIG_xhost-dev is not set + +# +# xinetd +# +# CONFIG_xinetd is not set +# CONFIG_xinetd-dbg is not set +# CONFIG_xinetd-dev is not set + +# +# xinit +# +# CONFIG_xinit is not set +# CONFIG_xinit-dbg is not set + +# +# xinput +# +# CONFIG_xinput is not set +# CONFIG_xinput-dev is not set +# CONFIG_xinput-dbg is not set + +# +# xinput-calibrator +# +# CONFIG_xinput-calibrator is not set +# CONFIG_xinput-calibrator-dev is not set +# CONFIG_xinput-calibrator-dbg is not set + +# +# xkbcomp +# +# CONFIG_xkbcomp is not set +# CONFIG_xkbcomp-dbg is not set +# CONFIG_xkbcomp-dev is not set + +# +# xmodmap +# +# CONFIG_xmodmap is not set +# CONFIG_xmodmap-dbg is not set +# CONFIG_xmodmap-dev is not set + +# +# xprop +# +# CONFIG_xprop is not set +# CONFIG_xprop-dbg is not set +# CONFIG_xprop-dev is not set + +# +# xrandr +# +# CONFIG_xrandr is not set +# CONFIG_xrandr-dbg is not set +# CONFIG_xrandr-dev is not set + +# +# xserver-common +# +# CONFIG_xserver-common is not set +# CONFIG_xserver-common-dbg is not set +# CONFIG_xserver-common-dev is not set + +# +# xset +# +# CONFIG_xset is not set +# CONFIG_xset-dev is not set +# CONFIG_xset-dbg is not set + +# +# xtrans +# +# CONFIG_xtrans-dev is not set +# CONFIG_xtrans-dbg is not set + +# +# xwininfo +# +# CONFIG_xwininfo is not set +# CONFIG_xwininfo-dev is not set +# CONFIG_xwininfo-dbg is not set + +# +# yajl +# +# CONFIG_yajl is not set +# CONFIG_yajl-dev is not set +# CONFIG_yajl-dbg is not set +# CONFIG_yajl-bin is not set + +# +# yavta +# +# CONFIG_yavta is not set +# CONFIG_yavta-dbg is not set +# CONFIG_yavta-dev is not set + +# +# multimedia +# + +# +# alsa-plugins +# +# CONFIG_alsa-plugins is not set +# CONFIG_alsa-plugins-dbg is not set +# CONFIG_alsa-plugins-dev is not set +# CONFIG_alsa-plugins-pulseaudio-conf is not set + +# +# gstreamer1.0 +# +# CONFIG_gstreamer1.0 is not set +# CONFIG_gstreamer1.0-dev is not set +# CONFIG_gstreamer1.0-bash-completion is not set +# CONFIG_gstreamer1.0-dbg is not set + +# +# gstreamer1.0-omx +# +# CONFIG_gstreamer1.0-omx is not set +# CONFIG_gstreamer1.0-omx-dbg is not set +# CONFIG_gstreamer1.0-omx-dev is not set + +# +# gstreamer1.0-rtsp-server +# +# CONFIG_gstreamer1.0-rtsp-server is not set +# CONFIG_gstreamer1.0-rtsp-server-dbg is not set +# CONFIG_gstreamer1.0-rtsp-server-dev is not set +# CONFIG_gstreamer1.0-rtsp-server-meta is not set + +# +# net +# + +# +# bridge-utils +# +CONFIG_bridge-utils=y +# CONFIG_bridge-utils-dbg is not set +# CONFIG_bridge-utils-dev is not set + +# +# net-snmp +# +# CONFIG_net-snmp is not set +# CONFIG_net-snmp-server-snmptrapd is not set +# CONFIG_net-snmp-libs is not set +# CONFIG_net-snmp-dev is not set +# CONFIG_net-snmp-client is not set +# CONFIG_net-snmp-mibs is not set +# CONFIG_net-snmp-dbg is not set +# CONFIG_net-snmp-server-snmpd is not set +# CONFIG_net-snmp-server is not set + +# +# netcat +# +# CONFIG_netcat is not set +# CONFIG_netcat-dbg is not set +# CONFIG_netcat-dev is not set + +# +# tcpdump +# +CONFIG_tcpdump=y +# CONFIG_tcpdump-dev is not set +# CONFIG_tcpdump-dbg is not set + +# +# network +# + +# +# avahi +# +# CONFIG_libavahi-client is not set +# CONFIG_libavahi-glib is not set +# CONFIG_avahi-utils is not set +# CONFIG_libavahi-common is not set +# CONFIG_avahi-dnsconfd is not set +# CONFIG_avahi-daemon is not set +# CONFIG_avahi-autoipd is not set +# CONFIG_libavahi-gobject is not set +# CONFIG_libavahi-core is not set +# CONFIG_avahi-dbg is not set +# CONFIG_avahi-dev is not set + +# +# mobile-broadband-provider-info +# +# CONFIG_mobile-broadband-provider-info is not set +# CONFIG_mobile-broadband-provider-info-dbg is not set +# CONFIG_mobile-broadband-provider-info-dev is not set + +# +# wpa-supplicant +# +# CONFIG_wpa-supplicant is not set +# CONFIG_wpa-supplicant-passphrase is not set +# CONFIG_wpa-supplicant-dev is not set +# CONFIG_wpa-supplicant-dbg is not set +# CONFIG_wpa-supplicant-cli is not set + +# +# optional +# + +# +# libatomic-ops +# +# CONFIG_libatomic-ops is not set +# CONFIG_libatomic-ops-dev is not set +# CONFIG_libatomic-ops-dbg is not set + +# +# mtools +# +# CONFIG_mtools is not set +# CONFIG_mtools-dev is not set +# CONFIG_mtools-dbg is not set + +# +# power management +# +CONFIG_hellopm=y + +# +# utils +# + +# +# dosfstools +# +# CONFIG_dosfstools is not set +# CONFIG_dosfstools-dev is not set +# CONFIG_dosfstools-dbg is not set + +# +# patch +# +# CONFIG_patch is not set +# CONFIG_patch-dbg is not set +# CONFIG_patch-dev is not set + +# +# resize-part +# +# CONFIG_resize-part is not set +# CONFIG_resize-part-dbg is not set +# CONFIG_resize-part-dev is not set + +# +# u-boot-tools +# +CONFIG_u-boot-tools=y +# CONFIG_u-boot-tools-dbg is not set +# CONFIG_u-boot-tools-dev is not set + +# +# x11 +# + +# +# base +# + +# +# libdrm +# +# CONFIG_libdrm is not set +# CONFIG_libdrm-tests is not set +# CONFIG_libdrm-drivers is not set +# CONFIG_libdrm-amdgpu is not set +# CONFIG_libdrm-nouveau is not set +# CONFIG_libdrm-dev is not set +# CONFIG_libdrm-freedreno is not set +# CONFIG_libdrm-radeon is not set +# CONFIG_libdrm-kms is not set +# CONFIG_libdrm-dbg is not set +# CONFIG_libdrm-omap is not set + +# +# xcursor-transparent-theme +# +# CONFIG_xcursor-transparent-theme is not set +# CONFIG_xcursor-transparent-theme-dev is not set +# CONFIG_xcursor-transparent-theme-dbg is not set + +# +# xserver-xf86-config +# +# CONFIG_xserver-xf86-config is not set +# CONFIG_xserver-xf86-config-dev is not set +# CONFIG_xserver-xf86-config-dbg is not set + +# +# xserver-xorg +# +# CONFIG_xserver-xorg is not set +# CONFIG_xserver-xorg-module-exa is not set +# CONFIG_xserver-xorg-module-libint10 is not set +# CONFIG_xserver-xorg-extension-record is not set +# CONFIG_xserver-xorg-dev is not set +# CONFIG_xserver-xorg-extension-dri2 is not set +# CONFIG_xserver-xorg-extension-dri is not set +# CONFIG_xserver-xorg-module-libwfb is not set +# CONFIG_xf86-video-modesetting is not set +# CONFIG_xserver-xorg-extension-dbe is not set +# CONFIG_xserver-xorg-extension-glx is not set +# CONFIG_xserver-xorg-xvfb is not set +# CONFIG_xserver-xorg-utils is not set +# CONFIG_xserver-xorg-dbg is not set +# CONFIG_xserver-xorg-extension-extmod is not set + +# +# builder +# +# CONFIG_builder is not set +# CONFIG_builder-dbg is not set +# CONFIG_builder-dev is not set + +# +# fonts +# + +# +# liberation-fonts +# +# CONFIG_liberation-fonts is not set + +# +# glew +# +# CONFIG_glew is not set +# CONFIG_glew-bin is not set +# CONFIG_glew-dev is not set +# CONFIG_glew-dbg is not set + +# +# gnome +# + +# +# adwaita-icon-theme +# +# CONFIG_adwaita-icon-theme is not set +# CONFIG_adwaita-icon-theme-hires is not set +# CONFIG_adwaita-icon-theme-symbolic is not set +# CONFIG_adwaita-icon-theme-cursors is not set +# CONFIG_adwaita-icon-theme-symbolic-hires is not set + +# +# gconf +# +# CONFIG_gconf is not set +# CONFIG_gconf-dev is not set +# CONFIG_gconf-dbg is not set + +# +# gnome-common +# +# CONFIG_gnome-common is not set +# CONFIG_gnome-common-dev is not set +# CONFIG_gnome-common-dbg is not set + +# +# gnome-desktop3 +# +# CONFIG_gnome-desktop3 is not set +# CONFIG_gnome-desktop3-dbg is not set +# CONFIG_gnome-desktop3-dev is not set +# CONFIG_libgnome-desktop3 is not set + +# +# gnome-themes-standard +# +# CONFIG_gnome-themes-standard-dev is not set +# CONFIG_gnome-themes-standard-dbg is not set +# CONFIG_gnome-theme-adwaita is not set + +# +# libsoup-2.4 +# +# CONFIG_libsoup-2.4 is not set +# CONFIG_libsoup-2.4-dev is not set +# CONFIG_libsoup-2.4-dbg is not set + +# +# libglu +# +# CONFIG_libglu is not set +# CONFIG_libglu-dev is not set +# CONFIG_libglu-dbg is not set + +# +# libs +# + +# +# atk +# +# CONFIG_atk is not set +# CONFIG_atk-dev is not set +# CONFIG_atk-dbg is not set + +# +# libfm +# +# CONFIG_libfm is not set +# CONFIG_libfm-mime is not set +# CONFIG_libfm-dev is not set +# CONFIG_libfm-dbg is not set + +# +# libfm-extra +# +# CONFIG_libfm-extra is not set +# CONFIG_libfm-extra-dev is not set +# CONFIG_libfm-extra-dbg is not set + +# +# libmatchbox +# +# CONFIG_libmatchbox is not set +# CONFIG_libmatchbox-dev is not set +# CONFIG_libmatchbox-dbg is not set + +# +# libpthread-stubs +# +# CONFIG_libpthread-stubs-dbg is not set +# CONFIG_libpthread-stubs-dev is not set + +# +# libwnck3 +# +# CONFIG_libwnck3 is not set +# CONFIG_libwnck3-dev is not set +# CONFIG_libwnck3-dbg is not set + +# +# libxcb +# +# CONFIG_libxcb is not set +# CONFIG_libxcb-dev is not set +# CONFIG_libxcb-dbg is not set + +# +# menu-cache +# +# CONFIG_menu-cache is not set +# CONFIG_menu-cache-dbg is not set +# CONFIG_menu-cache-dev is not set + +# +# xcb-proto +# +# CONFIG_python-xcbgen is not set +# CONFIG_xcb-proto-dev is not set +# CONFIG_xcb-proto-dbg is not set + +# +# xcb-util +# +# CONFIG_xcb-util is not set +# CONFIG_xcb-util-dbg is not set +# CONFIG_xcb-util-dev is not set + +# +# xkeyboard-config +# +# CONFIG_xkeyboard-config is not set +# CONFIG_xkeyboard-config-dev is not set +# CONFIG_xkeyboard-config-dbg is not set + +# +# matchbox-keyboard +# +# CONFIG_matchbox-keyboard is not set +# CONFIG_matchbox-keyboard-im is not set +# CONFIG_matchbox-keyboard-dev is not set +# CONFIG_matchbox-keyboard-applet is not set +# CONFIG_matchbox-keyboard-dbg is not set + +# +# matchbox-session +# +# CONFIG_matchbox-session is not set +# CONFIG_matchbox-session-dev is not set +# CONFIG_matchbox-session-dbg is not set + +# +# matchbox-session-sato +# +# CONFIG_matchbox-session-sato is not set +# CONFIG_matchbox-session-sato-dev is not set +# CONFIG_matchbox-session-sato-dbg is not set + +# +# mesa-demos +# +# CONFIG_mesa-demos is not set +# CONFIG_mesa-demos-dbg is not set +# CONFIG_mesa-demos-dev is not set + +# +# mini-x-session +# +# CONFIG_mini-x-session is not set +# CONFIG_mini-x-session-dev is not set +# CONFIG_mini-x-session-dbg is not set + +# +# pcmanfm +# +# CONFIG_pcmanfm is not set +# CONFIG_pcmanfm-dbg is not set +# CONFIG_pcmanfm-dev is not set + +# +# settings-daemon +# +# CONFIG_settings-daemon is not set +# CONFIG_settings-daemon-dev is not set +# CONFIG_settings-daemon-dbg is not set + +# +# utils +# + +# +# libcroco +# +# CONFIG_libcroco is not set +# CONFIG_libcroco-dbg is not set +# CONFIG_libcroco-dev is not set + +# +# librsvg +# +# CONFIG_librsvg is not set +# CONFIG_librsvg-gtk is not set +# CONFIG_rsvg is not set +# CONFIG_librsvg-dev is not set +# CONFIG_librsvg-dbg is not set + +# +# matchbox-terminal +# +# CONFIG_matchbox-terminal is not set +# CONFIG_matchbox-terminal-dev is not set +# CONFIG_matchbox-terminal-dbg is not set + +# +# xrestop +# +# CONFIG_xrestop is not set +# CONFIG_xrestop-dev is not set +# CONFIG_xrestop-dbg is not set + +# +# wm +# + +# +# libfakekey +# +# CONFIG_libfakekey is not set +# CONFIG_libfakekey-dev is not set +# CONFIG_libfakekey-dbg is not set + +# +# matchbox-desktop +# +# CONFIG_matchbox-desktop is not set +# CONFIG_matchbox-desktop-dbg is not set +# CONFIG_matchbox-desktop-dev is not set + +# +# matchbox-theme-sato +# +# CONFIG_matchbox-theme-sato is not set +# CONFIG_matchbox-theme-sato-dbg is not set +# CONFIG_matchbox-theme-sato-dev is not set + +# +# matchbox-wm +# +# CONFIG_matchbox-wm is not set +# CONFIG_matchbox-wm-dev is not set +# CONFIG_matchbox-wm-dbg is not set + +# +# xserver-nodm-init +# +# CONFIG_xserver-nodm-init is not set +# CONFIG_xserver-nodm-init-dbg is not set +# CONFIG_xserver-nodm-init-dev is not set + +# +# Petalinux Package Groups +# + +# +# packagegroup-petalinux +# +# CONFIG_packagegroup-petalinux is not set +# CONFIG_packagegroup-petalinux-dbg is not set +# CONFIG_packagegroup-petalinux-dev is not set + +# +# packagegroup-petalinux-audio +# +# CONFIG_packagegroup-petalinux-audio is not set +# CONFIG_packagegroup-petalinux-audio-dbg is not set +# CONFIG_packagegroup-petalinux-audio-dev is not set + +# +# packagegroup-petalinux-benchmarks +# +# CONFIG_packagegroup-petalinux-benchmarks is not set +# CONFIG_packagegroup-petalinux-benchmarks-dbg is not set +# CONFIG_packagegroup-petalinux-benchmarks-dev is not set + +# +# packagegroup-petalinux-display-debug +# +# CONFIG_packagegroup-petalinux-display-debug is not set +# CONFIG_packagegroup-petalinux-display-debug-dbg is not set +# CONFIG_packagegroup-petalinux-display-debug-dev is not set + +# +# packagegroup-petalinux-gstreamer +# +# CONFIG_packagegroup-petalinux-gstreamer is not set +# CONFIG_packagegroup-petalinux-gstreamer-dev is not set +# CONFIG_packagegroup-petalinux-gstreamer-dbg is not set + +# +# packagegroup-petalinux-lmsensors +# +# CONFIG_packagegroup-petalinux-lmsensors is not set +# CONFIG_packagegroup-petalinux-lmsensors-dbg is not set +# CONFIG_packagegroup-petalinux-lmsensors-dev is not set + +# +# packagegroup-petalinux-matchbox +# +# CONFIG_packagegroup-petalinux-matchbox is not set +# CONFIG_packagegroup-petalinux-matchbox-dbg is not set +# CONFIG_packagegroup-petalinux-matchbox-dev is not set + +# +# packagegroup-petalinux-mraa +# +# CONFIG_packagegroup-petalinux-mraa is not set +# CONFIG_packagegroup-petalinux-mraa-dbg is not set +# CONFIG_packagegroup-petalinux-mraa-dev is not set + +# +# packagegroup-petalinux-multimedia +# +# CONFIG_packagegroup-petalinux-multimedia is not set +# CONFIG_packagegroup-petalinux-multimedia-dbg is not set +# CONFIG_packagegroup-petalinux-multimedia-dev is not set + +# +# packagegroup-petalinux-networking-debug +# +# CONFIG_packagegroup-petalinux-networking-debug is not set +# CONFIG_packagegroup-petalinux-networking-debug-dbg is not set +# CONFIG_packagegroup-petalinux-networking-debug-dev is not set + +# +# packagegroup-petalinux-networking-stack +# +# CONFIG_packagegroup-petalinux-networking-stack is not set +# CONFIG_packagegroup-petalinux-networking-stack-dbg is not set +# CONFIG_packagegroup-petalinux-networking-stack-dev is not set + +# +# packagegroup-petalinux-ocicontainers +# +# CONFIG_packagegroup-petalinux-ocicontainers is not set +# CONFIG_packagegroup-petalinux-ocicontainers-dev is not set +# CONFIG_packagegroup-petalinux-ocicontainers-dbg is not set + +# +# packagegroup-petalinux-openamp +# +# CONFIG_packagegroup-petalinux-openamp is not set +# CONFIG_packagegroup-petalinux-openamp-dev is not set +# CONFIG_packagegroup-petalinux-openamp-dbg is not set + +# +# packagegroup-petalinux-opencv +# +# CONFIG_packagegroup-petalinux-opencv is not set +# CONFIG_packagegroup-petalinux-opencv-dev is not set +# CONFIG_packagegroup-petalinux-opencv-dbg is not set + +# +# packagegroup-petalinux-python-modules +# +# CONFIG_packagegroup-petalinux-python-modules is not set +# CONFIG_packagegroup-petalinux-python-modules-dbg is not set +# CONFIG_packagegroup-petalinux-python-modules-dev is not set + +# +# packagegroup-petalinux-qt +# +# CONFIG_packagegroup-petalinux-qt is not set +# CONFIG_packagegroup-petalinux-qt-dev is not set +# CONFIG_packagegroup-petalinux-qt-dbg is not set +# CONFIG_imageclass-populate-sdk-qt5 is not set + +# +# packagegroup-petalinux-qt-extended +# +# CONFIG_packagegroup-petalinux-qt-extended is not set +# CONFIG_packagegroup-petalinux-qt-extended-dbg is not set +# CONFIG_packagegroup-petalinux-qt-extended-dev is not set + +# +# packagegroup-petalinux-self-hosted +# +# CONFIG_packagegroup-petalinux-self-hosted is not set +# CONFIG_packagegroup-petalinux-self-hosted-dbg is not set +# CONFIG_packagegroup-petalinux-self-hosted-dev is not set + +# +# packagegroup-petalinux-utils +# +# CONFIG_packagegroup-petalinux-utils is not set +# CONFIG_packagegroup-petalinux-utils-dbg is not set +# CONFIG_packagegroup-petalinux-utils-dev is not set + +# +# packagegroup-petalinux-v4lutils +# +# CONFIG_packagegroup-petalinux-v4lutils is not set +# CONFIG_packagegroup-petalinux-v4lutils-dbg is not set +# CONFIG_packagegroup-petalinux-v4lutils-dev is not set + +# +# packagegroup-petalinux-weston +# +# CONFIG_packagegroup-petalinux-weston is not set +# CONFIG_packagegroup-petalinux-weston-dbg is not set +# CONFIG_packagegroup-petalinux-weston-dev is not set + +# +# packagegroup-petalinux-x11 +# +# CONFIG_packagegroup-petalinux-x11 is not set +# CONFIG_packagegroup-petalinux-x11-dev is not set +# CONFIG_packagegroup-petalinux-x11-dbg is not set + +# +# packagegroup-petalinux-xen +# +# CONFIG_packagegroup-petalinux-xen is not set +# CONFIG_packagegroup-petalinux-xen-dev is not set +# CONFIG_packagegroup-petalinux-xen-dbg is not set + +# +# Image Features +# +CONFIG_imagefeature-ssh-server-dropbear=y +# CONFIG_imagefeature-ssh-server-openssh is not set +CONFIG_imagefeature-hwcodecs=y +# CONFIG_imagefeature-package-management is not set +CONFIG_imagefeature-debug-tweaks=y +CONFIG_auto-login=y + +# +# apps +# +# CONFIG_gpio-demo is not set +# CONFIG_peekpoke is not set + +# +# user packages +# +CONFIG_iperf2=y +CONFIG_iputils-ping=y +CONFIG_kernel-module-mqnic=y +CONFIG_mqnic-tools=y + +# +# PetaLinux RootFS Settings +# +CONFIG_ROOTFS_ROOT_PASSWD="root" +CONFIG_ADD_EXTRA_USERS="petalinux:petalinux;" diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/hw-description/metadata b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/hw-description/metadata new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/COPYING.MIT b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/COPYING.MIT new file mode 100644 index 000000000..89de35479 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/COPYING.MIT @@ -0,0 +1,17 @@ +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/README b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/README new file mode 100644 index 000000000..5a5b9b948 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/README @@ -0,0 +1,64 @@ +This README file contains information on the contents of the +meta-user layer. + +Please see the corresponding sections below for details. + + +Dependencies +============ + +This layer depends on: + + URI: git://git.openembedded.org/bitbake + branch: master + + URI: git://git.openembedded.org/openembedded-core + layers: meta + branch: master + + URI: git://git.yoctoproject.org/xxxx + layers: xxxx + branch: master + + +Patches +======= + +Please submit any patches against the meta-user layer to the +xxxx mailing list (xxxx@zzzz.org) and cc: the maintainer: + +Maintainer: XXX YYYYYY + + +Table of Contents +================= + + I. Adding the meta-user layer to your build + II. Misc + + +I. Adding the meta-user layer to your build +================================================= + +--- replace with specific instructions for the meta-user layer --- + +In order to use this layer, you need to make the build system aware of +it. + +Assuming the meta-user layer exists at the top-level of your +yocto build tree, you can add it to the build system by adding the +location of the meta-user layer to bblayers.conf, along with any +other layers needed. e.g.: + + BBLAYERS ?= " \ + /path/to/yocto/meta \ + /path/to/yocto/meta-poky \ + /path/to/yocto/meta-yocto-bsp \ + /path/to/yocto/meta-meta-user \ + " + + +II. Misc +======== + +--- replace with specific information about the meta-user layer --- diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/conf/layer.conf b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/conf/layer.conf new file mode 100644 index 000000000..2895a8c0c --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/conf/layer.conf @@ -0,0 +1,11 @@ +# We have a conf and classes directory, add to BBPATH +BBPATH .= ":${LAYERDIR}" + +# We have recipes-* directories, add to BBFILES +BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ + ${LAYERDIR}/recipes-*/*/*.bbappend" + +BBFILE_COLLECTIONS += "meta-user" +BBFILE_PATTERN_meta-user = "^${LAYERDIR}/" +BBFILE_PRIORITY_meta-user = "7" +LAYERSERIES_COMPAT_meta-user = "gatesgarth" diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/conf/petalinuxbsp.conf b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/conf/petalinuxbsp.conf new file mode 100644 index 000000000..828a0af1f --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/conf/petalinuxbsp.conf @@ -0,0 +1,4 @@ +#User Configuration + +#OE_TERMINAL = "tmux" + diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/conf/user-rootfsconfig b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/conf/user-rootfsconfig new file mode 100644 index 000000000..fdb8ebb04 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/conf/user-rootfsconfig @@ -0,0 +1,12 @@ +#Note: Mention Each package in individual line +#These packages will get added into rootfs menu entry + +CONFIG_gpio-demo +CONFIG_peekpoke + +CONFIG_iputils-ping +CONFIG_iperf2 +CONFIG_linuxptp + +CONFIG_kernel-module-mqnic +CONFIG_mqnic-tools diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/Makefile b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/Makefile new file mode 100644 index 000000000..9106be1bd --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/Makefile @@ -0,0 +1,14 @@ +APP = gpio-demo + +# Add any other object files to this list below +APP_OBJS = gpio-demo.o + +all: $(APP) + +$(APP): $(APP_OBJS) + $(CC) $(LDFLAGS) -o $@ $(APP_OBJS) $(LDLIBS) + +clean: + -rm -f $(APP) *.elf *.gdb *.o + + diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/gpio-demo.c b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/gpio-demo.c new file mode 100644 index 000000000..4e17779da --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/gpio-demo.c @@ -0,0 +1,355 @@ +/* +* +* gpio-demo app +* +* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person +* obtaining a copy of this software and associated documentation +* files (the "Software"), to deal in the Software without restriction, +* including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, +* and to permit persons to whom the Software is furnished to do so, +* subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in this +* Software without prior written authorization from Xilinx. +* +*/ + +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_ROOT "/sys/class/gpio" +#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0])) + +static enum {NONE, IN, OUT, CYLON, KIT} gpio_opt = NONE; + +static const unsigned long cylon[] = { + 0x00000080, 0x00000040, 0x00000020, 0x00000010, + 0x00000008, 0x00000004, 0x00000002, 0x00000001, + 0x00000002, 0x00000004, 0x00000008, + 0x00000010, 0x00000020, 0x00000040, 0x00000080, +}; + +static const unsigned long kit[] = { + 0x000000e0, 0x00000070, 0x00000038, 0x0000001c, + 0x0000000e, 0x00000007, 0x00000003, 0x00000001, + 0x00000003, 0x00000007, 0x0000000e, + 0x0000001c, 0x00000038, 0x00000070, 0x000000e0, +}; + +static int gl_gpio_base = 0; + +static void usage (char *argv0) +{ + char *basename = strrchr(argv0, '/'); + if (!basename) + basename = argv0; + + fprintf(stderr, + "Usage: %s [-g GPIO_BASE] COMMAND\n" + "\twhere COMMAND is one of:\n" + "\t\t-i\t\tInput value from GPIO and print it\n" + "\t\t-o\tVALUE\tOutput value to GPIO\n" + "\t\t-c\t\tCylon test pattern\n" + "\t\t-k\t\t KIT test pattern\n" + "\tGPIO_BASE indicates which GPIO chip to talk to (The number can be \n" + "\tfound at /sys/class/gpio/gpiochipN).\n" + "\tThe highest gpiochipN is the first gpio listed in the dts file, \n" + "\tand the lowest gpiochipN is the last gpio listed in the dts file.\n" + "\tE.g.If the gpiochip240 is the LED_8bit gpio, and I want to output '1' \n" + "\tto the LED_8bit gpio, the command should be:\n" + "\t\tgpio-demo -g 240 -o 1\n" + "\n" + "\tgpio-demo written by Xilinx Inc.\n" + "\n" + , basename); + exit(-2); +} + +static int open_gpio_channel(int gpio_base) +{ + char gpio_nchan_file[128]; + int gpio_nchan_fd; + int gpio_max; + int nchannel; + char nchannel_str[5]; + char *cptr; + int c; + char channel_str[5]; + + char *gpio_export_file = "/sys/class/gpio/export"; + int export_fd=0; + + /* Check how many channels the GPIO chip has */ + sprintf(gpio_nchan_file, "%s/gpiochip%d/ngpio", GPIO_ROOT, gpio_base); + gpio_nchan_fd = open(gpio_nchan_file, O_RDONLY); + if (gpio_nchan_fd < 0) { + fprintf(stderr, "Failed to open %s: %s\n", gpio_nchan_file, strerror(errno)); + return -1; + } + read(gpio_nchan_fd, nchannel_str, sizeof(nchannel_str)); + close(gpio_nchan_fd); + nchannel=(int)strtoul(nchannel_str, &cptr, 0); + if (cptr == nchannel_str) { + fprintf(stderr, "Failed to change %s into GPIO channel number\n", nchannel_str); + exit(1); + } + + /* Open files for each GPIO channel */ + export_fd=open(gpio_export_file, O_WRONLY); + if (export_fd < 0) { + fprintf(stderr, "Cannot open GPIO to export %d\n", gpio_base); + return -1; + } + + gpio_max = gpio_base + nchannel; + for(c = gpio_base; c < gpio_max; c++) { + sprintf(channel_str, "%d", c); + write(export_fd, channel_str, (strlen(channel_str)+1)); + } + close(export_fd); + return nchannel; +} + +static int close_gpio_channel(int gpio_base) +{ + char gpio_nchan_file[128]; + int gpio_nchan_fd; + int gpio_max; + int nchannel; + char nchannel_str[5]; + char *cptr; + int c; + char channel_str[5]; + + char *gpio_unexport_file = "/sys/class/gpio/unexport"; + int unexport_fd=0; + + /* Check how many channels the GPIO chip has */ + sprintf(gpio_nchan_file, "%s/gpiochip%d/ngpio", GPIO_ROOT, gpio_base); + gpio_nchan_fd = open(gpio_nchan_file, O_RDONLY); + if (gpio_nchan_fd < 0) { + fprintf(stderr, "Failed to open %s: %s\n", gpio_nchan_file, strerror(errno)); + return -1; + } + read(gpio_nchan_fd, nchannel_str, sizeof(nchannel_str)); + close(gpio_nchan_fd); + nchannel=(int)strtoul(nchannel_str, &cptr, 0); + if (cptr == nchannel_str) { + fprintf(stderr, "Failed to change %s into GPIO channel number\n", nchannel_str); + exit(1); + } + + /* Close opened files for each GPIO channel */ + unexport_fd=open(gpio_unexport_file, O_WRONLY); + if (unexport_fd < 0) { + fprintf(stderr, "Cannot close GPIO by writing unexport %d\n", gpio_base); + return -1; + } + + gpio_max = gpio_base + nchannel; + for(c = gpio_base; c < gpio_max; c++) { + sprintf(channel_str, "%d", c); + write(unexport_fd, channel_str, (strlen(channel_str)+1)); + } + close(unexport_fd); + return 0; +} + +static int set_gpio_direction(int gpio_base, int nchannel, char *direction) +{ + char gpio_dir_file[128]; + int direction_fd=0; + int gpio_max; + int c; + + gpio_max = gpio_base + nchannel; + for(c = gpio_base; c < gpio_max; c++) { + sprintf(gpio_dir_file, "/sys/class/gpio/gpio%d/direction",c); + direction_fd=open(gpio_dir_file, O_RDWR); + if (direction_fd < 0) { + fprintf(stderr, "Cannot open the direction file for GPIO %d\n", c); + return 1; + } + write(direction_fd, direction, (strlen(direction)+1)); + close(direction_fd); + } + return 0; +} + +static int set_gpio_value(int gpio_base, int nchannel, int value) +{ + char gpio_val_file[128]; + int val_fd=0; + int gpio_max; + char val_str[2]; + int c; + + gpio_max = gpio_base + nchannel; + + for(c = gpio_base; c < gpio_max; c++) { + sprintf(gpio_val_file, "/sys/class/gpio/gpio%d/value",c); + val_fd=open(gpio_val_file, O_RDWR); + if (val_fd < 0) { + fprintf(stderr, "Cannot open the value file of GPIO %d\n", c); + return -1; + } + sprintf(val_str,"%d", (value & 1)); + write(val_fd, val_str, sizeof(val_str)); + close(val_fd); + value >>= 1; + } + return 0; +} + +static int get_gpio_value(int gpio_base, int nchannel) +{ + char gpio_val_file[128]; + int val_fd=0; + int gpio_max; + char val_str[2]; + char *cptr; + int value = 0; + int c; + + gpio_max = gpio_base + nchannel; + + for(c = gpio_max-1; c >= gpio_base; c--) { + sprintf(gpio_val_file, "/sys/class/gpio/gpio%d/value",c); + val_fd=open(gpio_val_file, O_RDWR); + if (val_fd < 0) { + fprintf(stderr, "Cannot open GPIO to export %d\n", c); + return -1; + } + read(val_fd, val_str, sizeof(val_str)); + value <<= 1; + value += (int)strtoul(val_str, &cptr, 0); + if (cptr == optarg) { + fprintf(stderr, "Failed to change %s into integer", val_str); + } + close(val_fd); + } + return value; +} + +void signal_handler(int sig) +{ + switch (sig) { + case SIGTERM: + case SIGHUP: + case SIGQUIT: + case SIGINT: + close_gpio_channel(gl_gpio_base); + exit(0) ; + default: + break; + } +} + +int main(int argc, char *argv[]) +{ + extern char *optarg; + char *cptr; + int gpio_value = 0; + int nchannel = 0; + + int c; + int i; + + opterr = 0; + + while ((c = getopt(argc, argv, "g:io:ck")) != -1) { + switch (c) { + case 'g': + gl_gpio_base = (int)strtoul(optarg, &cptr, 0); + if (cptr == optarg) + usage(argv[0]); + break; + case 'i': + gpio_opt = IN; + break; + case 'o': + gpio_opt = OUT; + gpio_value = (int)strtoul(optarg, &cptr, 0); + if (cptr == optarg) + usage(argv[0]); + break; + case 'c': + gpio_opt = CYLON; + break; + case 'k': + gpio_opt = KIT; + break; + case '?': + usage(argv[0]); + default: + usage(argv[0]); + + } + } + + if (gl_gpio_base == 0) { + usage(argv[0]); + } + + nchannel = open_gpio_channel(gl_gpio_base); + signal(SIGTERM, signal_handler); /* catch kill signal */ + signal(SIGHUP, signal_handler); /* catch hang up signal */ + signal(SIGQUIT, signal_handler); /* catch quit signal */ + signal(SIGINT, signal_handler); /* catch a CTRL-c signal */ + switch (gpio_opt) { + case IN: + set_gpio_direction(gl_gpio_base, nchannel, "in"); + gpio_value=get_gpio_value(gl_gpio_base, nchannel); + fprintf(stdout,"0x%08X\n", gpio_value); + break; + case OUT: + set_gpio_direction(gl_gpio_base, nchannel, "out"); + set_gpio_value(gl_gpio_base, nchannel, gpio_value); + break; + case CYLON: +#define CYLON_DELAY_USECS (10000) + set_gpio_direction(gl_gpio_base, nchannel, "out"); + for (;;) { + for(i=0; i < ARRAY_SIZE(cylon); i++) { + gpio_value=(int)cylon[i]; + set_gpio_value(gl_gpio_base, nchannel, gpio_value); + } + usleep(CYLON_DELAY_USECS); + } + case KIT: +#define KIT_DELAY_USECS (10000) + set_gpio_direction(gl_gpio_base, nchannel, "out"); + for (;;) { + for (i=0; i +#include +#include +#include +#include + +void usage(char *prog) +{ + printf("usage: %s ADDR\n",prog); + printf("\n"); + printf("ADDR may be specified as hex values\n"); +} + + +int main(int argc, char *argv[]) +{ + int fd; + void *ptr; + unsigned addr, page_addr, page_offset; + unsigned page_size=sysconf(_SC_PAGESIZE); + + if(argc!=2) { + usage(argv[0]); + exit(-1); + } + + fd=open("/dev/mem",O_RDONLY); + if(fd<1) { + perror(argv[0]); + exit(-1); + } + + addr=strtoul(argv[1],NULL,0); + page_addr=(addr & ~(page_size-1)); + page_offset=addr-page_addr; + + ptr=mmap(NULL,page_size,PROT_READ,MAP_SHARED,fd,(addr & ~(page_size-1))); + if((int)ptr==-1) { + perror(argv[0]); + exit(-1); + } + + printf("0x%08x\n",*((unsigned *)(ptr+page_offset))); + return 0; +} + + diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/poke.c b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/poke.c new file mode 100644 index 000000000..bc670c3b0 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/poke.c @@ -0,0 +1,77 @@ +/* +* poke utility - for those who remember the good old days! +* + +* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person +* obtaining a copy of this software and associated documentation +* files (the "Software"), to deal in the Software without restriction, +* including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, +* and to permit persons to whom the Software is furnished to do so, +* subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in this +* Software without prior written authorization from Xilinx. +* +*/ + +#include +#include +#include +#include +#include + +void usage(char *prog) +{ + printf("usage: %s ADDR VAL\n",prog); + printf("\n"); + printf("ADDR and VAL may be specified as hex values\n"); +} + +int main(int argc, char *argv[]) +{ + int fd; + void *ptr; + unsigned val; + unsigned addr, page_addr, page_offset; + unsigned page_size=sysconf(_SC_PAGESIZE); + + fd=open("/dev/mem",O_RDWR); + if(fd<1) { + perror(argv[0]); + exit(-1); + } + + if(argc!=3) { + usage(argv[0]); + exit(-1); + } + + addr=strtoul(argv[1],NULL,0); + val=strtoul(argv[2],NULL,0); + + page_addr=(addr & ~(page_size-1)); + page_offset=addr-page_addr; + + ptr=mmap(NULL,page_size,PROT_READ|PROT_WRITE,MAP_SHARED,fd,(addr & ~(page_size-1))); + if((int)ptr==-1) { + perror(argv[0]); + exit(-1); + } + + *((unsigned *)(ptr+page_offset))=val; + return 0; +} diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-apps/peekpoke/peekpoke.bb b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-apps/peekpoke/peekpoke.bb new file mode 100644 index 000000000..bace3952d --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-apps/peekpoke/peekpoke.bb @@ -0,0 +1,25 @@ +# +# This is the peekpoke apllication recipe +# +# + +SUMMARY = "peekpoke application" +SECTION = "PETALINUX/apps" +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" +SRC_URI = "file://peek.c \ + file://poke.c \ + file://Makefile \ + " +S = "${WORKDIR}" +CFLAGS_prepend = "-I ${S}/include" +do_compile() { + oe_runmake +} +do_install() { + install -d ${D}${bindir} + install -m 0755 ${S}/peek ${D}${bindir} + install -m 0755 ${S}/poke ${D}${bindir} + +} + diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/device-tree.bbappend b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/device-tree.bbappend new file mode 100644 index 000000000..711d9a74b --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/device-tree.bbappend @@ -0,0 +1,17 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/files:${SYSCONFIG_PATH}:" + +SRC_URI_append = " file://config file://system-user.dtsi" + +python () { + if d.getVar("CONFIG_DISABLE"): + d.setVarFlag("do_configure", "noexec", "1") +} + +export PETALINUX +do_configure_append () { + script="${PETALINUX}/etc/hsm/scripts/petalinux_hsm_bridge.tcl" + data=${PETALINUX}/etc/hsm/data/ + eval xsct -sdx -nodisp ${script} -c ${WORKDIR}/config \ + -hdf ${DT_FILES_PATH}/hardware_description.${HDF_EXT} -repo ${S} \ + -data ${data} -sw ${DT_FILES_PATH} -o ${DT_FILES_PATH} -a "soc_mapping" +} diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/pl-custom.dtsi b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/pl-custom.dtsi new file mode 100644 index 000000000..336d7a250 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/pl-custom.dtsi @@ -0,0 +1,2 @@ +/ { +}; diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi new file mode 100644 index 000000000..31cb34c93 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi @@ -0,0 +1,78 @@ +/include/ "system-conf.dtsi" + +/ { + /delete-node/ m_axil_ctrl@a0000000; + /delete-node/ m_axil_app_ctrl@a8000000; + + mqnic0: ethernet@a0000000 { + compatible = "corundum,mqnic"; + reg = <0x0 0xa0000000 0x0 0x1000000>, + <0x0 0xa8000000 0x0 0x1000000>; + reg-names = "csr", "app"; + interrupt-parent = <&gic>; + interrupts = <0x0 0x59 0x1>, <0x0 0x5a 0x1>, <0x0 0x5b 0x1>, + <0x0 0x5c 0x1>; + + nvmem-cells = <&macaddress>; + nvmem-cell-names = "mac-address"; + + /* NOTE: The nvmem-cells property provides us with a base MAC + * address. We increment its last byte (default) by 0x1. And we + * mark the derived address as "locally administrated". The + * result is used to derive MAC addresses for mqnic interfaces. + */ + mac-address-increment = <0x1>; + mac-address-local; + + module-eeproms = <&module_eeprom_sfp0>, <&module_eeprom_sfp1>, + <&module_eeprom_sfp2>, <&module_eeprom_sfp3>; + }; +}; + +&eeprom { + #address-cells = <1>; + #size-cells = <1>; + + macaddress: macaddress@20 { + /* NOTE: On Xilinx Zynq boards there usually is an + * EEPROM with a MAC address for one of the PS GEMs at + * offset 0x20. So we take that address as our base + * address. + */ + reg = <0x20 0x06>; + }; +}; + +&i2c1 { + i2c-mux@75 { + i2c@4 { + module_eeprom_sfp3: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + }; + i2c@5 { + module_eeprom_sfp2: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + }; + i2c@6 { + module_eeprom_sfp1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + }; + i2c@7 { + module_eeprom_sfp0: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + }; + }; +}; + +/* USER MGT SI570 (U56) */ +&si570_2 { + clock-frequency = <156250000>; +}; diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/fsbl-firmware/fsbl-firmware_%.bbappend b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/fsbl-firmware/fsbl-firmware_%.bbappend new file mode 100644 index 000000000..7639d58ae --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/fsbl-firmware/fsbl-firmware_%.bbappend @@ -0,0 +1,4 @@ +############################################################################### +# enable message level FSBL_DEBUG_DETAILED + +YAML_COMPILER_FLAGS_append = " -DFSBL_DEBUG_DETAILED" diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/0001-ubifs-distroboot-support.patch b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/0001-ubifs-distroboot-support.patch new file mode 100644 index 000000000..01cdb6dd7 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/0001-ubifs-distroboot-support.patch @@ -0,0 +1,28 @@ +From 357b3eebaa54be1ec8d14b306625eb73732ee5dc Mon Sep 17 00:00:00 2001 +From: Ashok Reddy Soma +Date: Wed, 19 Aug 2020 05:29:40 -0600 +Subject: [UBOOT PATCH] ubifs: distroboot support + +Signed-off-by: Ashok Reddy Soma +--- + include/configs/xilinx_zynqmp.h | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h +index d3f465a..dc231b8 100644 +--- a/include/configs/xilinx_zynqmp.h ++++ b/include/configs/xilinx_zynqmp.h +@@ -154,7 +154,10 @@ + + #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=sf probe " #instance " 0 0 && " \ +- "sf read $scriptaddr $script_offset_f $script_size_f && " \ ++ "setenv mtdids 'nor0=nor0' && " \ ++ "setenv mtdparts 'mtdparts=nor0:16m(raw),-(boot)' && " \ ++ "mtdparts && " \ ++ "ubi part boot; ubifsmount ubi0:boot; ubifsload $scriptaddr boot.scr; && " \ + "echo QSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0" + +-- +2.7.4 diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h new file mode 100644 index 000000000..6542b604a --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h @@ -0,0 +1,2 @@ +#include +#include diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend new file mode 100644 index 000000000..fbd24d8c1 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend @@ -0,0 +1,17 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/files:" + +SRC_URI += "file://platform-top.h" + +do_configure_append () { + if [ "${U_BOOT_AUTO_CONFIG}" = "1" ]; then + install ${WORKDIR}/platform-auto.h ${S}/include/configs/ + install ${WORKDIR}/platform-top.h ${S}/include/configs/ + fi +} + +do_configure_append_microblaze () { + if [ "${U_BOOT_AUTO_CONFIG}" = "1" ]; then + install -d ${B}/source/board/xilinx/microblaze-generic/ + install ${WORKDIR}/config.mk ${B}/source/board/xilinx/microblaze-generic/ + fi +} diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/uboot-device-tree/files/system-user.dtsi b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/uboot-device-tree/files/system-user.dtsi new file mode 100644 index 000000000..f3270dbb6 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/uboot-device-tree/files/system-user.dtsi @@ -0,0 +1,3 @@ +/include/ "system-conf.dtsi" +/ { +}; diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/uboot-device-tree/uboot-device-tree.bbappend b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/uboot-device-tree/uboot-device-tree.bbappend new file mode 100644 index 000000000..59e084554 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/uboot-device-tree/uboot-device-tree.bbappend @@ -0,0 +1,16 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/files:${SYSCONFIG_PATH}:" + +SRC_URI_append = " file://config file://system-user.dtsi" + +python () { + if d.getVar("CONFIG_DISABLE"): + d.setVarFlag("do_configure", "noexec", "1") +} +export PETALINUX +do_configure_append () { + script="${PETALINUX}/etc/hsm/scripts/petalinux_hsm_bridge.tcl" + data=${PETALINUX}/etc/hsm/data/ + eval xsct -sdx -nodisp ${script} -c ${WORKDIR}/config \ + -hdf ${DT_FILES_PATH}/hardware_description.${HDF_EXT} -repo ${S} \ + -data ${data} -sw ${DT_FILES_PATH} -o ${DT_FILES_PATH} -a "soc_mapping" +} diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/enable_ptp.cfg b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/enable_ptp.cfg new file mode 100644 index 000000000..eed8371c3 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/enable_ptp.cfg @@ -0,0 +1,20 @@ +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_MACB_USE_HWSTAMP=y +# CONFIG_CAVIUM_PTP is not set +CONFIG_PPS=m +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# +CONFIG_PTP_1588_CLOCK=m +# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set +# CONFIG_PTP_1588_CLOCK_IDTCM is not set +# CONFIG_PTP_1588_CLOCK_XILINX is not set diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend new file mode 100644 index 000000000..74e808520 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend @@ -0,0 +1,4 @@ +SRC_URI += "file://enable_ptp.cfg" + +FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" + diff --git a/fpga/mqnic/ZCU102/fpga/rtl/common b/fpga/mqnic/ZCU102/fpga/rtl/common new file mode 120000 index 000000000..449c9409c --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/rtl/common @@ -0,0 +1 @@ +../../../../common/rtl/ \ No newline at end of file diff --git a/fpga/mqnic/ZCU102/fpga/rtl/debounce_switch.v b/fpga/mqnic/ZCU102/fpga/rtl/debounce_switch.v new file mode 100644 index 000000000..8e93a50c4 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/rtl/debounce_switch.v @@ -0,0 +1,93 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog-2001 + +`resetall +`timescale 1 ns / 1 ps +`default_nettype none + +/* + * Synchronizes switch and button inputs with a slow sampled shift register + */ +module debounce_switch #( + parameter WIDTH=1, // width of the input and output signals + parameter N=3, // length of shift register + parameter RATE=125000 // clock division factor +)( + input wire clk, + input wire rst, + input wire [WIDTH-1:0] in, + output wire [WIDTH-1:0] out +); + +reg [23:0] cnt_reg = 24'd0; + +reg [N-1:0] debounce_reg[WIDTH-1:0]; + +reg [WIDTH-1:0] state; + +/* + * The synchronized output is the state register + */ +assign out = state; + +integer k; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cnt_reg <= 0; + state <= 0; + + for (k = 0; k < WIDTH; k = k + 1) begin + debounce_reg[k] <= 0; + end + end else begin + if (cnt_reg < RATE) begin + cnt_reg <= cnt_reg + 24'd1; + end else begin + cnt_reg <= 24'd0; + end + + if (cnt_reg == 24'd0) begin + for (k = 0; k < WIDTH; k = k + 1) begin + debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]}; + end + end + + for (k = 0; k < WIDTH; k = k + 1) begin + if (|debounce_reg[k] == 0) begin + state[k] <= 0; + end else if (&debounce_reg[k] == 1) begin + state[k] <= 1; + end else begin + state[k] <= state[k]; + end + end + end +end + +endmodule + +`resetall diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v new file mode 100644 index 000000000..146fcc660 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v @@ -0,0 +1,1087 @@ +/* + +Copyright 2021-2022, MissingLinkElectronics Inc. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY MISSINGLINKELECTRONICS INC. ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL MISSINGLINKELECTRONICS INC. OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of MissingLinkElectronics Inc. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA top-level module + */ +module fpga # +( + // FW and board IDs + parameter FPGA_ID = 32'h4738093, + parameter FW_ID = 32'h00000000, + parameter FW_VER = 32'h00_00_01_00, + parameter BOARD_ID = 32'h10ee_9066, + parameter BOARD_VER = 32'h01_00_00_00, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'hdce357bf, + parameter RELEASE_INFO = 32'h00000000, + + // Board configuration + parameter TDMA_BER_ENABLE = 0, + + // Structural configuration + parameter IF_COUNT = 2, + parameter PORTS_PER_IF = 1, + parameter SCHED_PER_IF = PORTS_PER_IF, + parameter PORT_MASK = 0, + + // PTP configuration + parameter PTP_CLOCK_PIPELINE = 0, + parameter PTP_CLOCK_CDC_PIPELINE = 0, + parameter PTP_PORT_CDC_PIPELINE = 0, + parameter PTP_PEROUT_ENABLE = 1, + parameter PTP_PEROUT_COUNT = 1, + + // Queue manager configuration + parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, + parameter TX_QUEUE_OP_TABLE_SIZE = 32, + parameter RX_QUEUE_OP_TABLE_SIZE = 32, + parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, + parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, + parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter TX_QUEUE_INDEX_WIDTH = 13, + parameter RX_QUEUE_INDEX_WIDTH = 8, + parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, + parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, + parameter EVENT_QUEUE_PIPELINE = 3, + parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), + parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), + parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, + parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + + // TX and RX engine configuration + parameter TX_DESC_TABLE_SIZE = 32, + parameter RX_DESC_TABLE_SIZE = 32, + + // Scheduler configuration + parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, + parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, + parameter TDMA_INDEX_WIDTH = 6, + + // Timestamping configuration + parameter PTP_TS_ENABLE = 1, + parameter TX_CPL_FIFO_DEPTH = 32, + parameter TX_CHECKSUM_ENABLE = 1, + parameter RX_RSS_ENABLE = 1, + parameter RX_HASH_ENABLE = 1, + parameter RX_CHECKSUM_ENABLE = 1, + parameter TX_FIFO_DEPTH = 32768, + parameter RX_FIFO_DEPTH = 32768, + parameter MAX_TX_SIZE = 9214, + parameter MAX_RX_SIZE = 9214, + parameter TX_RAM_SIZE = 32768, + parameter RX_RAM_SIZE = 32768, + + // Application block configuration + parameter APP_ID = 32'h00000000, + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + + // AXI interface configuration (DMA) + parameter AXI_DATA_WIDTH = 128, + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8), + parameter AXI_ID_WIDTH = 8, + + // DMA interface configuration + parameter DMA_IMM_ENABLE = 0, + parameter DMA_IMM_WIDTH = 32, + parameter DMA_LEN_WIDTH = 16, + parameter DMA_TAG_WIDTH = 16, + parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), + parameter RAM_PIPELINE = 2, + parameter AXI_DMA_MAX_BURST_LEN = 256, + + // Interrupts + parameter IRQ_COUNT = 32, + parameter IRQ_STRETCH = 10, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_WIDTH = 32, + parameter AXIL_CTRL_ADDR_WIDTH = 24, + parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8), + + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + parameter AXIL_APP_CTRL_STRB_WIDTH = (AXIL_APP_CTRL_DATA_WIDTH/8), + + // Ethernet interface configuration + parameter AXIS_ETH_TX_PIPELINE = 0, + parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, + parameter AXIS_ETH_TX_TS_PIPELINE = 0, + parameter AXIS_ETH_RX_PIPELINE = 0, + parameter AXIS_ETH_RX_FIFO_PIPELINE = 2, + + // Statistics counter subsystem + parameter STAT_ENABLE = 1, + parameter STAT_DMA_ENABLE = 1, + parameter STAT_AXI_ENABLE = 1, + parameter STAT_INC_WIDTH = 24, + parameter STAT_ID_WIDTH = 12 +) +( + /* + * Clock: 125MHz LVDS + */ + input wire clk_125mhz_p, + input wire clk_125mhz_n, + + /* + * GPIO + */ + input wire btnu, + input wire btnl, + input wire btnd, + input wire btnr, + input wire btnc, + input wire [7:0] sw, + output wire [7:0] led, + + /* + * Ethernet: SFP+ + */ + input wire sfp0_rx_p, + input wire sfp0_rx_n, + output wire sfp0_tx_p, + output wire sfp0_tx_n, + input wire sfp1_rx_p, + input wire sfp1_rx_n, + output wire sfp1_tx_p, + output wire sfp1_tx_n, + input wire sfp2_rx_p, + input wire sfp2_rx_n, + output wire sfp2_tx_p, + output wire sfp2_tx_n, + input wire sfp3_rx_p, + input wire sfp3_rx_n, + output wire sfp3_tx_p, + output wire sfp3_tx_n, + input wire sfp_mgt_refclk_0_p, + input wire sfp_mgt_refclk_0_n, + output wire sfp0_tx_disable_b, + output wire sfp1_tx_disable_b, + output wire sfp2_tx_disable_b, + output wire sfp3_tx_disable_b +); + +// PTP configuration +parameter PTP_CLK_PERIOD_NS_NUM = 32; +parameter PTP_CLK_PERIOD_NS_DENOM = 5; +parameter PTP_TS_WIDTH = 96; +parameter PTP_USE_SAMPLE_CLOCK = 1; +parameter IF_PTP_PERIOD_NS = 6'h6; +parameter IF_PTP_PERIOD_FNS = 16'h6666; + +// Interface configuration +parameter TX_TAG_WIDTH = 16; + +// Ethernet interface configuration +parameter XGMII_DATA_WIDTH = 64; +parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; +parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH; +parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; +parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH; +parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1; +parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; + +// Clock and reset +wire zynq_pl_clk; +wire zynq_pl_reset; + +wire clk_125mhz_ibufg; +wire clk_125mhz_bufg; +wire clk_125mhz_mmcm_out; + +// Internal 125 MHz clock +wire clk_125mhz_int; +wire rst_125mhz_int; + +wire mmcm_rst = zynq_pl_reset; +wire mmcm_locked; +wire mmcm_clkfb; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_125mhz_ibufg_inst ( + .O (clk_125mhz_ibufg), + .I (clk_125mhz_p), + .IB (clk_125mhz_n) +); + +BUFG +clk_125mhz_bufg_in_inst ( + .I(clk_125mhz_ibufg), + .O(clk_125mhz_bufg) +); + +// MMCM instance +// 125 MHz in, 125 MHz out +// PFD range: 10 MHz to 500 MHz +// VCO range: 800 MHz to 1600 MHz +// M = 8, D = 1 sets Fvco = 1000 MHz +// Divide by 8 to get output frequency of 125 MHz +MMCME4_BASE #( + .BANDWIDTH("OPTIMIZED"), + .CLKOUT0_DIVIDE_F(8), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + .CLKFBOUT_MULT_F(8), + .CLKFBOUT_PHASE(0), + .DIVCLK_DIVIDE(1), + .REF_JITTER1(0.010), + .CLKIN1_PERIOD(8.0), + .STARTUP_WAIT("FALSE"), + .CLKOUT4_CASCADE("FALSE") +) +clk_mmcm_inst ( + .CLKIN1(clk_125mhz_bufg), + .CLKFBIN(mmcm_clkfb), + .RST(mmcm_rst), + .PWRDWN(1'b0), + .CLKOUT0(clk_125mhz_mmcm_out), + .CLKOUT0B(), + .CLKOUT1(), + .CLKOUT1B(), + .CLKOUT2(), + .CLKOUT2B(), + .CLKOUT3(), + .CLKOUT3B(), + .CLKOUT4(), + .CLKOUT5(), + .CLKOUT6(), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + .LOCKED(mmcm_locked) +); + +BUFG +clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int) +); + +sync_reset #( + .N(4) +) +sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .out(rst_125mhz_int) +); + +// GPIO +wire btnu_int; +wire btnl_int; +wire btnd_int; +wire btnr_int; +wire btnc_int; +wire [7:0] sw_int; + +debounce_switch #( + .WIDTH(13), + .N(4), + .RATE(250000) +) +debounce_switch_inst ( + .clk(zynq_pl_clk), + .rst(zynq_pl_reset), + .in({btnu, + btnl, + btnd, + btnr, + btnc, + sw}), + .out({btnu_int, + btnl_int, + btnd_int, + btnr_int, + btnc_int, + sw_int}) +); + +// Zynq AXI MM +wire [IRQ_COUNT-1:0] irq; + +wire [AXI_ID_WIDTH-1:0] axi_awid; +wire [AXI_ADDR_WIDTH-1:0] axi_awaddr; +wire [7:0] axi_awlen; +wire [2:0] axi_awsize; +wire [1:0] axi_awburst; +wire axi_awlock; +wire [3:0] axi_awcache; +wire [2:0] axi_awprot; +wire axi_awvalid; +wire axi_awready; +wire [AXI_DATA_WIDTH-1:0] axi_wdata; +wire [AXI_STRB_WIDTH-1:0] axi_wstrb; +wire axi_wlast; +wire axi_wvalid; +wire axi_wready; +wire [AXI_ID_WIDTH-1:0] axi_bid; +wire [1:0] axi_bresp; +wire axi_bvalid; +wire axi_bready; +wire [AXI_ID_WIDTH-1:0] axi_arid; +wire [AXI_ADDR_WIDTH-1:0] axi_araddr; +wire [7:0] axi_arlen; +wire [2:0] axi_arsize; +wire [1:0] axi_arburst; +wire axi_arlock; +wire [3:0] axi_arcache; +wire [2:0] axi_arprot; +wire axi_arvalid; +wire axi_arready; +wire [AXI_ID_WIDTH-1:0] axi_rid; +wire [AXI_DATA_WIDTH-1:0] axi_rdata; +wire [1:0] axi_rresp; +wire axi_rlast; +wire axi_rvalid; +wire axi_rready; + +// AXI lite connections +wire [AXIL_CTRL_ADDR_WIDTH-1:0] axil_ctrl_awaddr; +wire [2:0] axil_ctrl_awprot; +wire axil_ctrl_awvalid; +wire axil_ctrl_awready; +wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_ctrl_wdata; +wire [AXIL_CTRL_STRB_WIDTH-1:0] axil_ctrl_wstrb; +wire axil_ctrl_wvalid; +wire axil_ctrl_wready; +wire [1:0] axil_ctrl_bresp; +wire axil_ctrl_bvalid; +wire axil_ctrl_bready; +wire [AXIL_CTRL_ADDR_WIDTH-1:0] axil_ctrl_araddr; +wire [2:0] axil_ctrl_arprot; +wire axil_ctrl_arvalid; +wire axil_ctrl_arready; +wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_ctrl_rdata; +wire [1:0] axil_ctrl_rresp; +wire axil_ctrl_rvalid; +wire axil_ctrl_rready; + +wire [AXIL_APP_CTRL_ADDR_WIDTH-1:0] axil_app_ctrl_awaddr; +wire [2:0] axil_app_ctrl_awprot; +wire axil_app_ctrl_awvalid; +wire axil_app_ctrl_awready; +wire [AXIL_APP_CTRL_DATA_WIDTH-1:0] axil_app_ctrl_wdata; +wire [AXIL_APP_CTRL_STRB_WIDTH-1:0] axil_app_ctrl_wstrb; +wire axil_app_ctrl_wvalid; +wire axil_app_ctrl_wready; +wire [1:0] axil_app_ctrl_bresp; +wire axil_app_ctrl_bvalid; +wire axil_app_ctrl_bready; +wire [AXIL_APP_CTRL_ADDR_WIDTH-1:0] axil_app_ctrl_araddr; +wire [2:0] axil_app_ctrl_arprot; +wire axil_app_ctrl_arvalid; +wire axil_app_ctrl_arready; +wire [AXIL_APP_CTRL_DATA_WIDTH-1:0] axil_app_ctrl_rdata; +wire [1:0] axil_app_ctrl_rresp; +wire axil_app_ctrl_rvalid; +wire axil_app_ctrl_rready; + +reg [(IRQ_COUNT*IRQ_STRETCH)-1:0] irq_stretch = {(IRQ_COUNT*IRQ_STRETCH){1'b0}}; +always @(posedge zynq_pl_clk) begin + if (zynq_pl_reset) begin + irq_stretch <= {(IRQ_COUNT*IRQ_STRETCH){1'b0}}; + end else begin + /* IRQ shift vector */ + irq_stretch <= {irq_stretch[0 +: (IRQ_COUNT*IRQ_STRETCH)-IRQ_COUNT], irq}; + end +end + +reg [IRQ_COUNT-1:0] zynq_irq; +integer i, k; +always @* begin + for (k = 0; k < IRQ_COUNT; k = k + 1) begin + zynq_irq[k] = 1'b0; + for (i = 0; i < (IRQ_COUNT*IRQ_STRETCH); i = i + IRQ_COUNT) begin + zynq_irq[k] = zynq_irq[k] | irq_stretch[k + i]; + end + end +end + +zynq_ps zynq_ps_inst ( + .pl_clk0(zynq_pl_clk), + .pl_reset(zynq_pl_reset), + .pl_ps_irq0(zynq_irq), + + .m_axil_ctrl_araddr(axil_ctrl_araddr), + .m_axil_ctrl_arprot(axil_ctrl_arprot), + .m_axil_ctrl_arready(axil_ctrl_arready), + .m_axil_ctrl_arvalid(axil_ctrl_arvalid), + .m_axil_ctrl_awaddr(axil_ctrl_awaddr), + .m_axil_ctrl_awprot(axil_ctrl_awprot), + .m_axil_ctrl_awready(axil_ctrl_awready), + .m_axil_ctrl_awvalid(axil_ctrl_awvalid), + .m_axil_ctrl_bready(axil_ctrl_bready), + .m_axil_ctrl_bresp(axil_ctrl_bresp), + .m_axil_ctrl_bvalid(axil_ctrl_bvalid), + .m_axil_ctrl_rdata(axil_ctrl_rdata), + .m_axil_ctrl_rready(axil_ctrl_rready), + .m_axil_ctrl_rresp(axil_ctrl_rresp), + .m_axil_ctrl_rvalid(axil_ctrl_rvalid), + .m_axil_ctrl_wdata(axil_ctrl_wdata), + .m_axil_ctrl_wready(axil_ctrl_wready), + .m_axil_ctrl_wstrb(axil_ctrl_wstrb), + .m_axil_ctrl_wvalid(axil_ctrl_wvalid), + + .m_axil_app_ctrl_araddr(axil_app_ctrl_araddr), + .m_axil_app_ctrl_arprot(axil_app_ctrl_arprot), + .m_axil_app_ctrl_arready(axil_app_ctrl_arready), + .m_axil_app_ctrl_arvalid(axil_app_ctrl_arvalid), + .m_axil_app_ctrl_awaddr(axil_app_ctrl_awaddr), + .m_axil_app_ctrl_awprot(axil_app_ctrl_awprot), + .m_axil_app_ctrl_awready(axil_app_ctrl_awready), + .m_axil_app_ctrl_awvalid(axil_app_ctrl_awvalid), + .m_axil_app_ctrl_bready(axil_app_ctrl_bready), + .m_axil_app_ctrl_bresp(axil_app_ctrl_bresp), + .m_axil_app_ctrl_bvalid(axil_app_ctrl_bvalid), + .m_axil_app_ctrl_rdata(axil_app_ctrl_rdata), + .m_axil_app_ctrl_rready(axil_app_ctrl_rready), + .m_axil_app_ctrl_rresp(axil_app_ctrl_rresp), + .m_axil_app_ctrl_rvalid(axil_app_ctrl_rvalid), + .m_axil_app_ctrl_wdata(axil_app_ctrl_wdata), + .m_axil_app_ctrl_wready(axil_app_ctrl_wready), + .m_axil_app_ctrl_wstrb(axil_app_ctrl_wstrb), + .m_axil_app_ctrl_wvalid(axil_app_ctrl_wvalid), + + .s_axi_dma_araddr(axi_araddr), + .s_axi_dma_arburst(axi_arburst), + .s_axi_dma_arcache(axi_arcache), + .s_axi_dma_arid(axi_arid), + .s_axi_dma_arlen(axi_arlen), + .s_axi_dma_arlock(axi_arlock), + .s_axi_dma_arprot(axi_arprot), + .s_axi_dma_arqos({4{1'b0}}), + .s_axi_dma_arready(axi_arready), + .s_axi_dma_arsize(axi_arsize), + .s_axi_dma_aruser(1'b0), + .s_axi_dma_arvalid(axi_arvalid), + .s_axi_dma_awaddr(axi_awaddr), + .s_axi_dma_awburst(axi_awburst), + .s_axi_dma_awcache(axi_awcache), + .s_axi_dma_awid(axi_awid), + .s_axi_dma_awlen(axi_awlen), + .s_axi_dma_awlock(axi_awlock), + .s_axi_dma_awprot(axi_awprot), + .s_axi_dma_awqos({4{1'b0}}), + .s_axi_dma_awready(axi_awready), + .s_axi_dma_awsize(axi_awsize), + .s_axi_dma_awuser(1'b0), + .s_axi_dma_awvalid(axi_awvalid), + .s_axi_dma_bid(axi_bid), + .s_axi_dma_bready(axi_bready), + .s_axi_dma_bresp(axi_bresp), + .s_axi_dma_bvalid(axi_bvalid), + .s_axi_dma_rdata(axi_rdata), + .s_axi_dma_rid(axi_rid), + .s_axi_dma_rlast(axi_rlast), + .s_axi_dma_rready(axi_rready), + .s_axi_dma_rresp(axi_rresp), + .s_axi_dma_rvalid(axi_rvalid), + .s_axi_dma_wdata(axi_wdata), + .s_axi_dma_wlast(axi_wlast), + .s_axi_dma_wready(axi_wready), + .s_axi_dma_wstrb(axi_wstrb), + .s_axi_dma_wvalid(axi_wvalid) +); + +// XGMII 10G PHY +wire sfp0_tx_clk_int; +wire sfp0_tx_rst_int; +wire [XGMII_DATA_WIDTH-1:0] sfp0_txd_int; +wire [XGMII_CTRL_WIDTH-1:0] sfp0_txc_int; +wire sfp0_tx_prbs31_enable_int; +wire sfp0_rx_clk_int; +wire sfp0_rx_rst_int; +wire [XGMII_DATA_WIDTH-1:0] sfp0_rxd_int; +wire [XGMII_CTRL_WIDTH-1:0] sfp0_rxc_int; +wire sfp0_rx_prbs31_enable_int; +wire [6:0] sfp0_rx_error_count_int; + +wire sfp1_tx_clk_int; +wire sfp1_tx_rst_int; +wire [XGMII_DATA_WIDTH-1:0] sfp1_txd_int; +wire [XGMII_CTRL_WIDTH-1:0] sfp1_txc_int; +wire sfp1_tx_prbs31_enable_int; +wire sfp1_rx_clk_int; +wire sfp1_rx_rst_int; +wire [XGMII_DATA_WIDTH-1:0] sfp1_rxd_int; +wire [XGMII_CTRL_WIDTH-1:0] sfp1_rxc_int; +wire sfp1_rx_prbs31_enable_int; +wire [6:0] sfp1_rx_error_count_int; + +wire sfp2_tx_clk_int; +wire sfp2_tx_rst_int; +wire [XGMII_DATA_WIDTH-1:0] sfp2_txd_int; +wire [XGMII_CTRL_WIDTH-1:0] sfp2_txc_int; +wire sfp2_tx_prbs31_enable_int; +wire sfp2_rx_clk_int; +wire sfp2_rx_rst_int; +wire [XGMII_DATA_WIDTH-1:0] sfp2_rxd_int; +wire [XGMII_CTRL_WIDTH-1:0] sfp2_rxc_int; +wire sfp2_rx_prbs31_enable_int; +wire [6:0] sfp2_rx_error_count_int; + +wire sfp3_tx_clk_int; +wire sfp3_tx_rst_int; +wire [XGMII_DATA_WIDTH-1:0] sfp3_txd_int; +wire [XGMII_CTRL_WIDTH-1:0] sfp3_txc_int; +wire sfp3_tx_prbs31_enable_int; +wire sfp3_rx_clk_int; +wire sfp3_rx_rst_int; +wire [XGMII_DATA_WIDTH-1:0] sfp3_rxd_int; +wire [XGMII_CTRL_WIDTH-1:0] sfp3_rxc_int; +wire sfp3_rx_prbs31_enable_int; +wire [6:0] sfp3_rx_error_count_int; + +wire sfp_drp_clk = clk_125mhz_int; +wire sfp_drp_rst = rst_125mhz_int; +wire [23:0] sfp_drp_addr; +wire [15:0] sfp_drp_di; +wire sfp_drp_en; +wire sfp_drp_we; +wire [15:0] sfp_drp_do; +wire sfp_drp_rdy; + +wire sfp0_rx_block_lock; +wire sfp0_rx_status; +wire sfp1_rx_block_lock; +wire sfp1_rx_status; +wire sfp2_rx_block_lock; +wire sfp2_rx_status; +wire sfp3_rx_block_lock; +wire sfp3_rx_status; + +wire sfp_gtpowergood; + +wire sfp_mgt_refclk_0; +wire sfp_mgt_refclk_0_int; +wire sfp_mgt_refclk_0_bufg; + +IBUFDS_GTE4 ibufds_gte4_sfp_mgt_refclk_0_inst ( + .I (sfp_mgt_refclk_0_p), + .IB (sfp_mgt_refclk_0_n), + .CEB (1'b0), + .O (sfp_mgt_refclk_0), + .ODIV2 (sfp_mgt_refclk_0_int) +); + +BUFG_GT bufg_gt_sfp_mgt_refclk_0_inst ( + .CE (sfp_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (sfp_mgt_refclk_0_int), + .O (sfp_mgt_refclk_0_bufg) +); + +wire sfp_rst; + +sync_reset #( + .N(4) +) +sfp_sync_reset_inst ( + .clk(sfp_mgt_refclk_0_bufg), + .rst(rst_125mhz_int), + .out(sfp_rst) +); + +eth_xcvr_phy_10g_gty_quad_wrapper #( + .GT_GTH(1), + .PRBS31_ENABLE(1) +) +sfp_phy_quad_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(sfp_rst), + + /* + * Common + */ + .xcvr_gtpowergood_out(sfp_gtpowergood), + .xcvr_ref_clk(sfp_mgt_refclk_0), + + /* + * DRP + */ + .drp_clk(sfp_drp_clk), + .drp_rst(sfp_drp_rst), + .drp_addr(sfp_drp_addr), + .drp_di(sfp_drp_di), + .drp_en(sfp_drp_en), + .drp_we(sfp_drp_we), + .drp_do(sfp_drp_do), + .drp_rdy(sfp_drp_rdy), + + /* + * Serial data + */ + .xcvr_txp({sfp3_tx_p, sfp2_tx_p, sfp1_tx_p, sfp0_tx_p}), + .xcvr_txn({sfp3_tx_n, sfp2_tx_n, sfp1_tx_n, sfp0_tx_n}), + .xcvr_rxp({sfp3_rx_p, sfp2_rx_p, sfp1_rx_p, sfp0_rx_p}), + .xcvr_rxn({sfp3_rx_n, sfp2_rx_n, sfp1_rx_n, sfp0_rx_n}), + + /* + * PHY connections + */ + .phy_1_tx_clk(sfp0_tx_clk_int), + .phy_1_tx_rst(sfp0_tx_rst_int), + .phy_1_xgmii_txd(sfp0_txd_int), + .phy_1_xgmii_txc(sfp0_txc_int), + .phy_1_rx_clk(sfp0_rx_clk_int), + .phy_1_rx_rst(sfp0_rx_rst_int), + .phy_1_xgmii_rxd(sfp0_rxd_int), + .phy_1_xgmii_rxc(sfp0_rxc_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(sfp0_rx_error_count_int), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(sfp0_rx_block_lock), + .phy_1_rx_high_ber(), + .phy_1_rx_status(sfp0_rx_status), + .phy_1_tx_prbs31_enable(sfp0_tx_prbs31_enable_int), + .phy_1_rx_prbs31_enable(sfp0_rx_prbs31_enable_int), + + .phy_2_tx_clk(sfp1_tx_clk_int), + .phy_2_tx_rst(sfp1_tx_rst_int), + .phy_2_xgmii_txd(sfp1_txd_int), + .phy_2_xgmii_txc(sfp1_txc_int), + .phy_2_rx_clk(sfp1_rx_clk_int), + .phy_2_rx_rst(sfp1_rx_rst_int), + .phy_2_xgmii_rxd(sfp1_rxd_int), + .phy_2_xgmii_rxc(sfp1_rxc_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(sfp1_rx_error_count_int), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(sfp1_rx_block_lock), + .phy_2_rx_high_ber(), + .phy_2_rx_status(sfp1_rx_status), + .phy_2_tx_prbs31_enable(sfp1_tx_prbs31_enable_int), + .phy_2_rx_prbs31_enable(sfp1_rx_prbs31_enable_int), + + .phy_3_tx_clk(sfp2_tx_clk_int), + .phy_3_tx_rst(sfp2_tx_rst_int), + .phy_3_xgmii_txd(sfp2_txd_int), + .phy_3_xgmii_txc(sfp2_txc_int), + .phy_3_rx_clk(sfp2_rx_clk_int), + .phy_3_rx_rst(sfp2_rx_rst_int), + .phy_3_xgmii_rxd(sfp2_rxd_int), + .phy_3_xgmii_rxc(sfp2_rxc_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(sfp2_rx_error_count_int), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(sfp2_rx_block_lock), + .phy_3_rx_high_ber(), + .phy_3_rx_status(sfp2_rx_status), + .phy_3_tx_prbs31_enable(sfp2_tx_prbs31_enable_int), + .phy_3_rx_prbs31_enable(sfp2_rx_prbs31_enable_int), + + .phy_4_tx_clk(sfp3_tx_clk_int), + .phy_4_tx_rst(sfp3_tx_rst_int), + .phy_4_xgmii_txd(sfp3_txd_int), + .phy_4_xgmii_txc(sfp3_txc_int), + .phy_4_rx_clk(sfp3_rx_clk_int), + .phy_4_rx_rst(sfp3_rx_rst_int), + .phy_4_xgmii_rxd(sfp3_rxd_int), + .phy_4_xgmii_rxc(sfp3_rxc_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(sfp3_rx_error_count_int), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(sfp3_rx_block_lock), + .phy_4_rx_high_ber(), + .phy_4_rx_status(sfp3_rx_status), + .phy_4_tx_prbs31_enable(sfp3_tx_prbs31_enable_int), + .phy_4_rx_prbs31_enable(sfp3_rx_prbs31_enable_int) +); + +wire ptp_clk; +wire ptp_rst; +wire ptp_sample_clk; + +assign ptp_clk = sfp_mgt_refclk_0_bufg; +assign ptp_rst = sfp_rst; +assign ptp_sample_clk = clk_125mhz_int; + +fpga_core #( + // FW and board IDs + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Board configuration + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + + // Structural configuration + .IF_COUNT(IF_COUNT), + .PORTS_PER_IF(PORTS_PER_IF), + .SCHED_PER_IF(SCHED_PER_IF), + .PORT_MASK(PORT_MASK), + + // PTP configuration + .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), + .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), + .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), + .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), + .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), + .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), + .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), + + // Queue manager configuration + .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), + .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), + .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), + .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), + .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), + .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), + .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), + .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), + .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), + .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), + .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), + .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), + .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + + // TX and RX engine configuration + .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), + .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + + // Scheduler configuration + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), + .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), + .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), + + // Interface configuration + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), + .TX_TAG_WIDTH(TX_TAG_WIDTH), + .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), + .RX_RSS_ENABLE(RX_RSS_ENABLE), + .RX_HASH_ENABLE(RX_HASH_ENABLE), + .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .MAX_TX_SIZE(MAX_TX_SIZE), + .MAX_RX_SIZE(MAX_RX_SIZE), + .TX_RAM_SIZE(TX_RAM_SIZE), + .RX_RAM_SIZE(RX_RAM_SIZE), + + // Application block configuration + .APP_ID(APP_ID), + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + + // AXI interface configuration (DMA) + .AXI_DATA_WIDTH(AXI_DATA_WIDTH), + .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), + .AXI_STRB_WIDTH(AXI_STRB_WIDTH), + .AXI_ID_WIDTH(AXI_ID_WIDTH), + + // DMA interface configuration + .DMA_IMM_ENABLE(DMA_IMM_ENABLE), + .DMA_IMM_WIDTH(DMA_IMM_WIDTH), + .DMA_LEN_WIDTH(DMA_LEN_WIDTH), + .DMA_TAG_WIDTH(DMA_TAG_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_PIPELINE(RAM_PIPELINE), + .AXI_DMA_MAX_BURST_LEN(AXI_DMA_MAX_BURST_LEN), + + // Interrupts + .IRQ_COUNT(IRQ_COUNT), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), + .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + .AXIL_APP_CTRL_STRB_WIDTH(AXIL_APP_CTRL_STRB_WIDTH), + + // Ethernet interface configuration + .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), + .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), + .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), + .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), + .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), + .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), + .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), + + // Statistics counter subsystem + .STAT_ENABLE(STAT_ENABLE), + .STAT_DMA_ENABLE(STAT_DMA_ENABLE), + .STAT_AXI_ENABLE(STAT_AXI_ENABLE), + .STAT_INC_WIDTH(STAT_INC_WIDTH), + .STAT_ID_WIDTH(STAT_ID_WIDTH) +) +core_inst ( + /* + * Clock: 300 MHz + * Synchronous reset + */ + .clk_300mhz(zynq_pl_clk), + .rst_300mhz(zynq_pl_reset), + + /* + * PTP clock + */ + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_sample_clk(ptp_sample_clk), + + /* + * GPIO + */ + .btnu(btnu_int), + .btnl(btnl_int), + .btnd(btnd_int), + .btnr(btnr_int), + .btnc(btnc_int), + .sw(sw_int), + .led(led), + + /* + * Interrupt outputs + */ + .irq(irq), + + /* + * AXI master interface (DMA) + */ + .m_axi_awid(axi_awid), + .m_axi_awaddr(axi_awaddr), + .m_axi_awlen(axi_awlen), + .m_axi_awsize(axi_awsize), + .m_axi_awburst(axi_awburst), + .m_axi_awlock(axi_awlock), + .m_axi_awcache(axi_awcache), + .m_axi_awprot(axi_awprot), + .m_axi_awvalid(axi_awvalid), + .m_axi_awready(axi_awready), + .m_axi_wdata(axi_wdata), + .m_axi_wstrb(axi_wstrb), + .m_axi_wlast(axi_wlast), + .m_axi_wvalid(axi_wvalid), + .m_axi_wready(axi_wready), + .m_axi_bid(axi_bid), + .m_axi_bresp(axi_bresp), + .m_axi_bvalid(axi_bvalid), + .m_axi_bready(axi_bready), + .m_axi_arid(axi_arid), + .m_axi_araddr(axi_araddr), + .m_axi_arlen(axi_arlen), + .m_axi_arsize(axi_arsize), + .m_axi_arburst(axi_arburst), + .m_axi_arlock(axi_arlock), + .m_axi_arcache(axi_arcache), + .m_axi_arprot(axi_arprot), + .m_axi_arvalid(axi_arvalid), + .m_axi_arready(axi_arready), + .m_axi_rid(axi_rid), + .m_axi_rdata(axi_rdata), + .m_axi_rresp(axi_rresp), + .m_axi_rlast(axi_rlast), + .m_axi_rvalid(axi_rvalid), + .m_axi_rready(axi_rready), + + /* + * AXI lite interface configuration (control) + */ + .s_axil_ctrl_awaddr(axil_ctrl_awaddr), + .s_axil_ctrl_awprot(axil_ctrl_awprot), + .s_axil_ctrl_awvalid(axil_ctrl_awvalid), + .s_axil_ctrl_awready(axil_ctrl_awready), + .s_axil_ctrl_wdata(axil_ctrl_wdata), + .s_axil_ctrl_wstrb(axil_ctrl_wstrb), + .s_axil_ctrl_wvalid(axil_ctrl_wvalid), + .s_axil_ctrl_wready(axil_ctrl_wready), + .s_axil_ctrl_bresp(axil_ctrl_bresp), + .s_axil_ctrl_bvalid(axil_ctrl_bvalid), + .s_axil_ctrl_bready(axil_ctrl_bready), + .s_axil_ctrl_araddr(axil_ctrl_araddr), + .s_axil_ctrl_arprot(axil_ctrl_arprot), + .s_axil_ctrl_arvalid(axil_ctrl_arvalid), + .s_axil_ctrl_arready(axil_ctrl_arready), + .s_axil_ctrl_rdata(axil_ctrl_rdata), + .s_axil_ctrl_rresp(axil_ctrl_rresp), + .s_axil_ctrl_rvalid(axil_ctrl_rvalid), + .s_axil_ctrl_rready(axil_ctrl_rready), + + /* + * AXI lite interface configuration (application control) + */ + .s_axil_app_ctrl_awaddr(axil_app_ctrl_awaddr), + .s_axil_app_ctrl_awprot(axil_app_ctrl_awprot), + .s_axil_app_ctrl_awvalid(axil_app_ctrl_awvalid), + .s_axil_app_ctrl_awready(axil_app_ctrl_awready), + .s_axil_app_ctrl_wdata(axil_app_ctrl_wdata), + .s_axil_app_ctrl_wstrb(axil_app_ctrl_wstrb), + .s_axil_app_ctrl_wvalid(axil_app_ctrl_wvalid), + .s_axil_app_ctrl_wready(axil_app_ctrl_wready), + .s_axil_app_ctrl_bresp(axil_app_ctrl_bresp), + .s_axil_app_ctrl_bvalid(axil_app_ctrl_bvalid), + .s_axil_app_ctrl_bready(axil_app_ctrl_bready), + .s_axil_app_ctrl_araddr(axil_app_ctrl_araddr), + .s_axil_app_ctrl_arprot(axil_app_ctrl_arprot), + .s_axil_app_ctrl_arvalid(axil_app_ctrl_arvalid), + .s_axil_app_ctrl_arready(axil_app_ctrl_arready), + .s_axil_app_ctrl_rdata(axil_app_ctrl_rdata), + .s_axil_app_ctrl_rresp(axil_app_ctrl_rresp), + .s_axil_app_ctrl_rvalid(axil_app_ctrl_rvalid), + .s_axil_app_ctrl_rready(axil_app_ctrl_rready), + + /* + * Ethernet: SFP+ + */ + .sfp0_tx_clk(sfp0_tx_clk_int), + .sfp0_tx_rst(sfp0_tx_rst_int), + .sfp0_txd(sfp0_txd_int), + .sfp0_txc(sfp0_txc_int), + .sfp0_tx_prbs31_enable(sfp0_tx_prbs31_enable_int), + .sfp0_rx_clk(sfp0_rx_clk_int), + .sfp0_rx_rst(sfp0_rx_rst_int), + .sfp0_rxd(sfp0_rxd_int), + .sfp0_rxc(sfp0_rxc_int), + .sfp0_rx_prbs31_enable(sfp0_rx_prbs31_enable_int), + .sfp0_rx_error_count(sfp0_rx_error_count_int), + .sfp0_rx_status(sfp0_rx_status), + .sfp0_tx_disable_b(sfp0_tx_disable_b), + + .sfp1_tx_clk(sfp1_tx_clk_int), + .sfp1_tx_rst(sfp1_tx_rst_int), + .sfp1_txd(sfp1_txd_int), + .sfp1_txc(sfp1_txc_int), + .sfp1_tx_prbs31_enable(sfp1_tx_prbs31_enable_int), + .sfp1_rx_clk(sfp1_rx_clk_int), + .sfp1_rx_rst(sfp1_rx_rst_int), + .sfp1_rxd(sfp1_rxd_int), + .sfp1_rxc(sfp1_rxc_int), + .sfp1_rx_prbs31_enable(sfp1_rx_prbs31_enable_int), + .sfp1_rx_error_count(sfp1_rx_error_count_int), + .sfp1_rx_status(sfp1_rx_status), + .sfp1_tx_disable_b(sfp1_tx_disable_b), + + .sfp2_tx_clk(sfp2_tx_clk_int), + .sfp2_tx_rst(sfp2_tx_rst_int), + .sfp2_txd(sfp2_txd_int), + .sfp2_txc(sfp2_txc_int), + .sfp2_tx_prbs31_enable(sfp2_tx_prbs31_enable_int), + .sfp2_rx_clk(sfp2_rx_clk_int), + .sfp2_rx_rst(sfp2_rx_rst_int), + .sfp2_rxd(sfp2_rxd_int), + .sfp2_rxc(sfp2_rxc_int), + .sfp2_rx_prbs31_enable(sfp2_rx_prbs31_enable_int), + .sfp2_rx_error_count(sfp2_rx_error_count_int), + .sfp2_rx_status(sfp2_rx_status), + .sfp2_tx_disable_b(sfp2_tx_disable_b), + + .sfp3_tx_clk(sfp3_tx_clk_int), + .sfp3_tx_rst(sfp3_tx_rst_int), + .sfp3_txd(sfp3_txd_int), + .sfp3_txc(sfp3_txc_int), + .sfp3_tx_prbs31_enable(sfp3_tx_prbs31_enable_int), + .sfp3_rx_clk(sfp3_rx_clk_int), + .sfp3_rx_rst(sfp3_rx_rst_int), + .sfp3_rxd(sfp3_rxd_int), + .sfp3_rxc(sfp3_rxc_int), + .sfp3_rx_prbs31_enable(sfp3_rx_prbs31_enable_int), + .sfp3_rx_error_count(sfp3_rx_error_count_int), + .sfp3_rx_status(sfp3_rx_status), + .sfp3_tx_disable_b(sfp3_tx_disable_b), + + .sfp_drp_clk(sfp_drp_clk), + .sfp_drp_rst(sfp_drp_rst), + .sfp_drp_addr(sfp_drp_addr), + .sfp_drp_di(sfp_drp_di), + .sfp_drp_en(sfp_drp_en), + .sfp_drp_we(sfp_drp_we), + .sfp_drp_do(sfp_drp_do), + .sfp_drp_rdy(sfp_drp_rdy) +); + +endmodule + +`resetall diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v new file mode 100644 index 000000000..72e39ee53 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v @@ -0,0 +1,1132 @@ +/* + +Copyright 2021-2022, MissingLinkElectronics Inc. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY MISSINGLINKELECTRONICS INC. ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL MISSINGLINKELECTRONICS INC. OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of MissingLinkElectronics Inc. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA core logic + */ +module fpga_core # +( + // FW and board IDs + parameter FPGA_ID = 32'h4738093, + parameter FW_ID = 32'h00000000, + parameter FW_VER = 32'h00_00_01_00, + parameter BOARD_ID = 32'h10ee_9066, + parameter BOARD_VER = 32'h01_00_00_00, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'hdce357bf, + parameter RELEASE_INFO = 32'h00000000, + + // Board configuration + parameter TDMA_BER_ENABLE = 0, + + // Structural configuration + parameter IF_COUNT = 2, + parameter PORTS_PER_IF = 1, + parameter SCHED_PER_IF = PORTS_PER_IF, + parameter PORT_MASK = 0, + + // PTP configuration + parameter PTP_CLK_PERIOD_NS_NUM = 32, + parameter PTP_CLK_PERIOD_NS_DENOM = 5, + parameter PTP_TS_WIDTH = 96, + parameter PTP_CLOCK_PIPELINE = 0, + parameter PTP_CLOCK_CDC_PIPELINE = 0, + parameter PTP_USE_SAMPLE_CLOCK = 1, + parameter PTP_PORT_CDC_PIPELINE = 0, + parameter PTP_PEROUT_ENABLE = 1, + parameter PTP_PEROUT_COUNT = 1, + parameter IF_PTP_PERIOD_NS = 6'h6, + parameter IF_PTP_PERIOD_FNS = 16'h6666, + + // Queue manager configuration + parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, + parameter TX_QUEUE_OP_TABLE_SIZE = 32, + parameter RX_QUEUE_OP_TABLE_SIZE = 32, + parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, + parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, + parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter TX_QUEUE_INDEX_WIDTH = 13, + parameter RX_QUEUE_INDEX_WIDTH = 8, + parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, + parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, + parameter EVENT_QUEUE_PIPELINE = 3, + parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), + parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), + parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, + parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + + // TX and RX engine configuration + parameter TX_DESC_TABLE_SIZE = 32, + parameter RX_DESC_TABLE_SIZE = 32, + + // Scheduler configuration + parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, + parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, + parameter TDMA_INDEX_WIDTH = 6, + + // Interface configuration + parameter PTP_TS_ENABLE = 1, + parameter TX_CPL_FIFO_DEPTH = 32, + parameter TX_TAG_WIDTH = 16, + parameter TX_CHECKSUM_ENABLE = 1, + parameter RX_RSS_ENABLE = 1, + parameter RX_HASH_ENABLE = 1, + parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, + parameter TX_FIFO_DEPTH = 32768, + parameter RX_FIFO_DEPTH = 32768, + parameter MAX_TX_SIZE = 9214, + parameter MAX_RX_SIZE = 9214, + parameter TX_RAM_SIZE = 32768, + parameter RX_RAM_SIZE = 32768, + + // Application block configuration + parameter APP_ID = 32'h00000000, + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + + // AXI interface configuration (DMA) + parameter AXI_DATA_WIDTH = 128, + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8), + parameter AXI_ID_WIDTH = 8, + + // DMA interface configuration + parameter DMA_IMM_ENABLE = 0, + parameter DMA_IMM_WIDTH = 32, + parameter DMA_LEN_WIDTH = 16, + parameter DMA_TAG_WIDTH = 16, + parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), + parameter RAM_PIPELINE = 2, + parameter AXI_DMA_MAX_BURST_LEN = 256, + + // Interrupts + parameter IRQ_COUNT = 32, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_WIDTH = 32, + parameter AXIL_CTRL_ADDR_WIDTH = 24, + parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8), + + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + parameter AXIL_APP_CTRL_STRB_WIDTH = (AXIL_APP_CTRL_DATA_WIDTH/8), + + // Ethernet interface configuration + parameter XGMII_DATA_WIDTH = 64, + parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8, + parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH, + parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, + parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH, + parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1, + parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, + parameter AXIS_ETH_TX_PIPELINE = 0, + parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, + parameter AXIS_ETH_TX_TS_PIPELINE = 0, + parameter AXIS_ETH_RX_PIPELINE = 0, + parameter AXIS_ETH_RX_FIFO_PIPELINE = 2, + + // Statistics counter subsystem + parameter STAT_ENABLE = 1, + parameter STAT_DMA_ENABLE = 1, + parameter STAT_AXI_ENABLE = 1, + parameter STAT_INC_WIDTH = 24, + parameter STAT_ID_WIDTH = 12 +) +( + /* + * Clock: 300 MHz + * Synchronous reset + */ + input wire clk_300mhz, + input wire rst_300mhz, + + /* + * PTP clock + */ + input wire ptp_clk, + input wire ptp_rst, + input wire ptp_sample_clk, + + /* + * GPIO + */ + input wire btnu, + input wire btnl, + input wire btnd, + input wire btnr, + input wire btnc, + input wire [7:0] sw, + output wire [7:0] led, + + /* + * Interrupt outputs + */ + output wire [IRQ_COUNT-1:0] irq, + + /* + * AXI master interface (DMA) + */ + output wire [AXI_ID_WIDTH-1:0] m_axi_awid, + output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [7:0] m_axi_awlen, + output wire [2:0] m_axi_awsize, + output wire [1:0] m_axi_awburst, + output wire m_axi_awlock, + output wire [3:0] m_axi_awcache, + output wire [2:0] m_axi_awprot, + output wire m_axi_awvalid, + input wire m_axi_awready, + output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, + output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb, + output wire m_axi_wlast, + output wire m_axi_wvalid, + input wire m_axi_wready, + input wire [AXI_ID_WIDTH-1:0] m_axi_bid, + input wire [1:0] m_axi_bresp, + input wire m_axi_bvalid, + output wire m_axi_bready, + output wire [AXI_ID_WIDTH-1:0] m_axi_arid, + output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output wire [7:0] m_axi_arlen, + output wire [2:0] m_axi_arsize, + output wire [1:0] m_axi_arburst, + output wire m_axi_arlock, + output wire [3:0] m_axi_arcache, + output wire [2:0] m_axi_arprot, + output wire m_axi_arvalid, + input wire m_axi_arready, + input wire [AXI_ID_WIDTH-1:0] m_axi_rid, + input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata, + input wire [1:0] m_axi_rresp, + input wire m_axi_rlast, + input wire m_axi_rvalid, + output wire m_axi_rready, + + /* + * AXI lite interface configuration (control) + */ + input wire [AXIL_CTRL_ADDR_WIDTH-1:0] s_axil_ctrl_awaddr, + input wire [2:0] s_axil_ctrl_awprot, + input wire s_axil_ctrl_awvalid, + output wire s_axil_ctrl_awready, + input wire [AXIL_CTRL_DATA_WIDTH-1:0] s_axil_ctrl_wdata, + input wire [AXIL_CTRL_STRB_WIDTH-1:0] s_axil_ctrl_wstrb, + input wire s_axil_ctrl_wvalid, + output wire s_axil_ctrl_wready, + output wire [1:0] s_axil_ctrl_bresp, + output wire s_axil_ctrl_bvalid, + input wire s_axil_ctrl_bready, + input wire [AXIL_CTRL_ADDR_WIDTH-1:0] s_axil_ctrl_araddr, + input wire [2:0] s_axil_ctrl_arprot, + input wire s_axil_ctrl_arvalid, + output wire s_axil_ctrl_arready, + output wire [AXIL_CTRL_DATA_WIDTH-1:0] s_axil_ctrl_rdata, + output wire [1:0] s_axil_ctrl_rresp, + output wire s_axil_ctrl_rvalid, + input wire s_axil_ctrl_rready, + + /* + * AXI lite interface configuration (application control) + */ + input wire [AXIL_APP_CTRL_ADDR_WIDTH-1:0] s_axil_app_ctrl_awaddr, + input wire [2:0] s_axil_app_ctrl_awprot, + input wire s_axil_app_ctrl_awvalid, + output wire s_axil_app_ctrl_awready, + input wire [AXIL_APP_CTRL_DATA_WIDTH-1:0] s_axil_app_ctrl_wdata, + input wire [AXIL_APP_CTRL_STRB_WIDTH-1:0] s_axil_app_ctrl_wstrb, + input wire s_axil_app_ctrl_wvalid, + output wire s_axil_app_ctrl_wready, + output wire [1:0] s_axil_app_ctrl_bresp, + output wire s_axil_app_ctrl_bvalid, + input wire s_axil_app_ctrl_bready, + input wire [AXIL_APP_CTRL_ADDR_WIDTH-1:0] s_axil_app_ctrl_araddr, + input wire [2:0] s_axil_app_ctrl_arprot, + input wire s_axil_app_ctrl_arvalid, + output wire s_axil_app_ctrl_arready, + output wire [AXIL_APP_CTRL_DATA_WIDTH-1:0] s_axil_app_ctrl_rdata, + output wire [1:0] s_axil_app_ctrl_rresp, + output wire s_axil_app_ctrl_rvalid, + input wire s_axil_app_ctrl_rready, + + /* + * Ethernet: SFP+ + */ + input wire sfp0_tx_clk, + input wire sfp0_tx_rst, + output wire [63:0] sfp0_txd, + output wire [7:0] sfp0_txc, + output wire sfp0_tx_prbs31_enable, + input wire sfp0_rx_clk, + input wire sfp0_rx_rst, + input wire [63:0] sfp0_rxd, + input wire [7:0] sfp0_rxc, + output wire sfp0_rx_prbs31_enable, + input wire [6:0] sfp0_rx_error_count, + input wire sfp0_rx_status, + output wire sfp0_tx_disable_b, + + input wire sfp1_tx_clk, + input wire sfp1_tx_rst, + output wire [63:0] sfp1_txd, + output wire [7:0] sfp1_txc, + output wire sfp1_tx_prbs31_enable, + input wire sfp1_rx_clk, + input wire sfp1_rx_rst, + input wire [63:0] sfp1_rxd, + input wire [7:0] sfp1_rxc, + output wire sfp1_rx_prbs31_enable, + input wire [6:0] sfp1_rx_error_count, + input wire sfp1_rx_status, + output wire sfp1_tx_disable_b, + + input wire sfp2_tx_clk, + input wire sfp2_tx_rst, + output wire [63:0] sfp2_txd, + output wire [7:0] sfp2_txc, + output wire sfp2_tx_prbs31_enable, + input wire sfp2_rx_clk, + input wire sfp2_rx_rst, + input wire [63:0] sfp2_rxd, + input wire [7:0] sfp2_rxc, + output wire sfp2_rx_prbs31_enable, + input wire [6:0] sfp2_rx_error_count, + input wire sfp2_rx_status, + output wire sfp2_tx_disable_b, + + input wire sfp3_tx_clk, + input wire sfp3_tx_rst, + output wire [63:0] sfp3_txd, + output wire [7:0] sfp3_txc, + output wire sfp3_tx_prbs31_enable, + input wire sfp3_rx_clk, + input wire sfp3_rx_rst, + input wire [63:0] sfp3_rxd, + input wire [7:0] sfp3_rxc, + output wire sfp3_rx_prbs31_enable, + input wire [6:0] sfp3_rx_error_count, + input wire sfp3_rx_status, + output wire sfp3_tx_disable_b, + + input wire sfp_drp_clk, + input wire sfp_drp_rst, + output wire [23:0] sfp_drp_addr, + output wire [15:0] sfp_drp_di, + output wire sfp_drp_en, + output wire sfp_drp_we, + input wire [15:0] sfp_drp_do, + input wire sfp_drp_rdy +); + +parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; + +parameter AXIL_IF_CTRL_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT); +parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8); + +localparam RB_BASE_ADDR = 16'h1000; +localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; + +localparam RB_DRP_SFP_BASE = RB_BASE_ADDR + 16'h10; + +initial begin + if (PORT_COUNT > 4) begin + $error("Error: Max port count exceeded (instance %m)"); + $finish; + end +end + +// AXI lite connections +wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_awaddr; +wire [2:0] axil_csr_awprot; +wire axil_csr_awvalid; +wire axil_csr_awready; +wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_wdata; +wire [AXIL_CTRL_STRB_WIDTH-1:0] axil_csr_wstrb; +wire axil_csr_wvalid; +wire axil_csr_wready; +wire [1:0] axil_csr_bresp; +wire axil_csr_bvalid; +wire axil_csr_bready; +wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_araddr; +wire [2:0] axil_csr_arprot; +wire axil_csr_arvalid; +wire axil_csr_arready; +wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_rdata; +wire [1:0] axil_csr_rresp; +wire axil_csr_rvalid; +wire axil_csr_rready; + +// PTP +wire [PTP_TS_WIDTH-1:0] ptp_ts_96; +wire ptp_ts_step; +wire ptp_pps; +wire ptp_pps_str; +wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; +wire ptp_sync_ts_step; +wire ptp_sync_pps; + +wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; +wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; +wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse; + +// control registers +wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_wr_addr; +wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_wr_data; +wire [AXIL_CTRL_STRB_WIDTH-1:0] ctrl_reg_wr_strb; +wire ctrl_reg_wr_en; +wire ctrl_reg_wr_wait; +wire ctrl_reg_wr_ack; +wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_rd_addr; +wire ctrl_reg_rd_en; +wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data; +wire ctrl_reg_rd_wait; +wire ctrl_reg_rd_ack; + +wire sfp_drp_reg_wr_wait; +wire sfp_drp_reg_wr_ack; +wire [AXIL_CTRL_DATA_WIDTH-1:0] sfp_drp_reg_rd_data; +wire sfp_drp_reg_rd_wait; +wire sfp_drp_reg_rd_ack; + +reg ctrl_reg_wr_ack_reg = 1'b0; +reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; +reg ctrl_reg_rd_ack_reg = 1'b0; + +reg sfp0_tx_disable_reg = 1'b0; +reg sfp1_tx_disable_reg = 1'b0; +reg sfp2_tx_disable_reg = 1'b0; +reg sfp3_tx_disable_reg = 1'b0; + +assign ctrl_reg_wr_wait = sfp_drp_reg_wr_wait; +assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | sfp_drp_reg_wr_ack; +assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | sfp_drp_reg_rd_data; +assign ctrl_reg_rd_wait = sfp_drp_reg_rd_wait; +assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | sfp_drp_reg_rd_ack; + +assign sfp0_tx_disable_b = !sfp0_tx_disable_reg; +assign sfp1_tx_disable_b = !sfp1_tx_disable_reg; +assign sfp2_tx_disable_b = !sfp2_tx_disable_reg; +assign sfp3_tx_disable_b = !sfp3_tx_disable_reg; + +always @(posedge clk_300mhz) begin + ctrl_reg_wr_ack_reg <= 1'b0; + ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; + ctrl_reg_rd_ack_reg <= 1'b0; + + if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin + // write operation + ctrl_reg_wr_ack_reg <= 1'b0; + case ({ctrl_reg_wr_addr >> 2, 2'b00}) + // XCVR GPIO + RBB+8'h0C: begin + // XCVR GPIO: control 0123 + if (ctrl_reg_wr_strb[0]) begin + sfp0_tx_disable_reg <= ctrl_reg_wr_data[5]; + end + if (ctrl_reg_wr_strb[1]) begin + sfp1_tx_disable_reg <= ctrl_reg_wr_data[13]; + end + if (ctrl_reg_wr_strb[1]) begin + sfp1_tx_disable_reg <= ctrl_reg_wr_data[21]; + end + if (ctrl_reg_wr_strb[1]) begin + sfp1_tx_disable_reg <= ctrl_reg_wr_data[29]; + end + end + default: ctrl_reg_wr_ack_reg <= 1'b0; + endcase + end + + if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin + // read operation + ctrl_reg_rd_ack_reg <= 1'b1; + case ({ctrl_reg_rd_addr >> 2, 2'b00}) + // XCVR GPIO + RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C101; // XCVR GPIO: Type + RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // XCVR GPIO: Version + RBB+8'h08: ctrl_reg_rd_data_reg <= RB_DRP_SFP_BASE; // XCVR GPIO: Next header + RBB+8'h0C: begin + // XCVR GPIO: control 0123 + ctrl_reg_rd_data_reg[5] <= sfp0_tx_disable_reg; + ctrl_reg_rd_data_reg[13] <= sfp1_tx_disable_reg; + ctrl_reg_rd_data_reg[21] <= sfp2_tx_disable_reg; + ctrl_reg_rd_data_reg[29] <= sfp3_tx_disable_reg; + end + default: ctrl_reg_rd_ack_reg <= 1'b0; + endcase + end + + if (rst_300mhz) begin + ctrl_reg_wr_ack_reg <= 1'b0; + ctrl_reg_rd_ack_reg <= 1'b0; + + sfp0_tx_disable_reg <= 1'b0; + sfp1_tx_disable_reg <= 1'b0; + sfp2_tx_disable_reg <= 1'b0; + sfp3_tx_disable_reg <= 1'b0; + end +end + +rb_drp #( + .DRP_ADDR_WIDTH(24), + .DRP_DATA_WIDTH(16), + .DRP_INFO({8'h09, 8'h02, 8'd0, 8'd4}), + .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), + .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .RB_BASE_ADDR(RB_DRP_SFP_BASE), + .RB_NEXT_PTR(0) +) +sfp_rb_drp_inst ( + .clk(clk_300mhz), + .rst(rst_300mhz), + + /* + * Register interface + */ + .reg_wr_addr(ctrl_reg_wr_addr), + .reg_wr_data(ctrl_reg_wr_data), + .reg_wr_strb(ctrl_reg_wr_strb), + .reg_wr_en(ctrl_reg_wr_en), + .reg_wr_wait(sfp_drp_reg_wr_wait), + .reg_wr_ack(sfp_drp_reg_wr_ack), + .reg_rd_addr(ctrl_reg_rd_addr), + .reg_rd_en(ctrl_reg_rd_en), + .reg_rd_data(sfp_drp_reg_rd_data), + .reg_rd_wait(sfp_drp_reg_rd_wait), + .reg_rd_ack(sfp_drp_reg_rd_ack), + + /* + * DRP + */ + .drp_clk(sfp_drp_clk), + .drp_rst(sfp_drp_rst), + .drp_addr(sfp_drp_addr), + .drp_di(sfp_drp_di), + .drp_en(sfp_drp_en), + .drp_we(sfp_drp_we), + .drp_do(sfp_drp_do), + .drp_rdy(sfp_drp_rdy) +); + +generate + +if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(4), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(4)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000) + ) + tdma_ber_inst ( + .clk(clk_300mhz), + .rst(rst_300mhz), + .phy_tx_clk({sfp3_tx_clk, sfp2_tx_clk, sfp1_tx_clk, sfp0_tx_clk}), + .phy_rx_clk({sfp3_rx_clk, sfp2_rx_clk, sfp1_rx_clk, sfp0_rx_clk}), + .phy_rx_error_count({sfp3_rx_error_count, sfp2_rx_error_count, sfp1_rx_error_count, sfp0_rx_error_count}), + .phy_tx_prbs31_enable({sfp3_tx_prbs31_enable, sfp2_tx_prbs31_enable, sfp1_tx_prbs31_enable, sfp0_tx_prbs31_enable}), + .phy_rx_prbs31_enable({sfp3_rx_prbs31_enable, sfp2_rx_prbs31_enable, sfp1_rx_prbs31_enable, sfp0_rx_prbs31_enable}), + .s_axil_awaddr(axil_csr_awaddr), + .s_axil_awprot(axil_csr_awprot), + .s_axil_awvalid(axil_csr_awvalid), + .s_axil_awready(axil_csr_awready), + .s_axil_wdata(axil_csr_wdata), + .s_axil_wstrb(axil_csr_wstrb), + .s_axil_wvalid(axil_csr_wvalid), + .s_axil_wready(axil_csr_wready), + .s_axil_bresp(axil_csr_bresp), + .s_axil_bvalid(axil_csr_bvalid), + .s_axil_bready(axil_csr_bready), + .s_axil_araddr(axil_csr_araddr), + .s_axil_arprot(axil_csr_arprot), + .s_axil_arvalid(axil_csr_arvalid), + .s_axil_arready(axil_csr_arready), + .s_axil_rdata(axil_csr_rdata), + .s_axil_rresp(axil_csr_rresp), + .s_axil_rvalid(axil_csr_rvalid), + .s_axil_rready(axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_96), + .ptp_ts_step(ptp_sync_ts_step) + ); + +end else begin + + assign sfp0_tx_prbs31_enable = 1'b0; + assign sfp0_rx_prbs31_enable = 1'b0; + assign sfp1_tx_prbs31_enable = 1'b0; + assign sfp1_rx_prbs31_enable = 1'b0; + assign sfp2_tx_prbs31_enable = 1'b0; + assign sfp2_rx_prbs31_enable = 1'b0; + assign sfp3_tx_prbs31_enable = 1'b0; + assign sfp3_rx_prbs31_enable = 1'b0; + +end + +endgenerate + +assign led[6:0] = 0; +assign led[7] = ptp_pps_str; + +wire [PORT_COUNT-1:0] eth_tx_clk; +wire [PORT_COUNT-1:0] eth_tx_rst; + +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; + +wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; +wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; +wire [PORT_COUNT-1:0] axis_eth_tx_tvalid; +wire [PORT_COUNT-1:0] axis_eth_tx_tready; +wire [PORT_COUNT-1:0] axis_eth_tx_tlast; +wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser; + +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts; +wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag; +wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; +wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; + +wire [PORT_COUNT-1:0] eth_tx_status; + +wire [PORT_COUNT-1:0] eth_rx_clk; +wire [PORT_COUNT-1:0] eth_rx_rst; + +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; + +wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; +wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; +wire [PORT_COUNT-1:0] axis_eth_rx_tvalid; +wire [PORT_COUNT-1:0] axis_eth_rx_tready; +wire [PORT_COUNT-1:0] axis_eth_rx_tlast; +wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; + +wire [PORT_COUNT-1:0] eth_rx_status; + +wire [PORT_COUNT-1:0] port_xgmii_tx_clk; +wire [PORT_COUNT-1:0] port_xgmii_tx_rst; +wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_txd; +wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_txc; + +wire [PORT_COUNT-1:0] port_xgmii_rx_clk; +wire [PORT_COUNT-1:0] port_xgmii_rx_rst; +wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_rxd; +wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_rxc; + +mqnic_port_map_phy_xgmii #( + .PHY_COUNT(4), + .PORT_MASK(PORT_MASK), + .PORT_GROUP_SIZE(1), + + .IF_COUNT(IF_COUNT), + .PORTS_PER_IF(PORTS_PER_IF), + + .PORT_COUNT(PORT_COUNT), + + .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), + .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH) +) +mqnic_port_map_phy_xgmii_inst ( + // towards PHY + .phy_xgmii_tx_clk({sfp3_tx_clk, sfp2_tx_clk, sfp1_tx_clk, sfp0_tx_clk}), + .phy_xgmii_tx_rst({sfp3_tx_rst, sfp2_tx_rst, sfp1_tx_rst, sfp0_tx_rst}), + .phy_xgmii_txd({sfp3_txd, sfp2_txd, sfp1_txd, sfp0_txd}), + .phy_xgmii_txc({sfp3_txc, sfp2_txc, sfp1_txc, sfp0_txc}), + .phy_tx_status(4'b1111), + + .phy_xgmii_rx_clk({sfp3_rx_clk, sfp2_rx_clk, sfp1_rx_clk, sfp0_rx_clk}), + .phy_xgmii_rx_rst({sfp3_rx_rst, sfp2_rx_rst, sfp1_rx_rst, sfp0_rx_rst}), + .phy_xgmii_rxd({sfp3_rxd, sfp2_rxd, sfp1_rxd, sfp0_rxd}), + .phy_xgmii_rxc({sfp3_rxc, sfp2_rxc, sfp1_rxc, sfp0_rxc}), + .phy_rx_status({sfp3_rx_status, sfp2_rx_status, sfp1_rx_status, sfp0_rx_status}), + + // towards MAC + .port_xgmii_tx_clk(port_xgmii_tx_clk), + .port_xgmii_tx_rst(port_xgmii_tx_rst), + .port_xgmii_txd(port_xgmii_txd), + .port_xgmii_txc(port_xgmii_txc), + .port_tx_status(eth_tx_status), + + .port_xgmii_rx_clk(port_xgmii_rx_clk), + .port_xgmii_rx_rst(port_xgmii_rx_rst), + .port_xgmii_rxd(port_xgmii_rxd), + .port_xgmii_rxc(port_xgmii_rxc), + .port_rx_status(eth_rx_status) +); + +generate + genvar n; + + for (n = 0; n < PORT_COUNT; n = n + 1) begin : mac + + assign eth_tx_clk[n] = port_xgmii_tx_clk[n]; + assign eth_tx_rst[n] = port_xgmii_tx_rst[n]; + assign eth_rx_clk[n] = port_xgmii_rx_clk[n]; + assign eth_rx_rst[n] = port_xgmii_rx_rst[n]; + + eth_mac_10g #( + .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), + .PTP_PERIOD_NS(IF_PTP_PERIOD_NS), + .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS), + .TX_PTP_TS_ENABLE(PTP_TS_ENABLE), + .TX_PTP_TS_WIDTH(PTP_TS_WIDTH), + .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE), + .TX_PTP_TAG_WIDTH(TX_TAG_WIDTH), + .RX_PTP_TS_ENABLE(PTP_TS_ENABLE), + .RX_PTP_TS_WIDTH(PTP_TS_WIDTH), + .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) + ) + eth_mac_inst ( + .tx_clk(port_xgmii_tx_clk[n]), + .tx_rst(port_xgmii_tx_rst[n]), + .rx_clk(port_xgmii_rx_clk[n]), + .rx_rst(port_xgmii_rx_rst[n]), + + .tx_axis_tdata(axis_eth_tx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .tx_axis_tkeep(axis_eth_tx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .tx_axis_tvalid(axis_eth_tx_tvalid[n +: 1]), + .tx_axis_tready(axis_eth_tx_tready[n +: 1]), + .tx_axis_tlast(axis_eth_tx_tlast[n +: 1]), + .tx_axis_tuser(axis_eth_tx_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]), + + .rx_axis_tdata(axis_eth_rx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .rx_axis_tkeep(axis_eth_rx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .rx_axis_tvalid(axis_eth_rx_tvalid[n +: 1]), + .rx_axis_tlast(axis_eth_rx_tlast[n +: 1]), + .rx_axis_tuser(axis_eth_rx_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]), + + .xgmii_rxd(port_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .xgmii_rxc(port_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + + .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), + .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), + + .tx_error_underflow(), + .rx_error_bad_frame(), + .rx_error_bad_fcs(), + + .ifg_delay(8'd12) + ); + + end + +endgenerate + +mqnic_core_axi #( + // FW and board IDs + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Structural configuration + .IF_COUNT(IF_COUNT), + .PORTS_PER_IF(PORTS_PER_IF), + .SCHED_PER_IF(SCHED_PER_IF), + + .PORT_COUNT(PORT_COUNT), + + // PTP configuration + .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), + .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), + .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), + .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), + .PTP_SEPARATE_TX_CLOCK(0), + .PTP_SEPARATE_RX_CLOCK(0), + .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), + .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), + .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), + + // Queue manager configuration + .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), + .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), + .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), + .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), + .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), + .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), + .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), + .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), + .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), + .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), + .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), + .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), + .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + + // TX and RX engine configuration + .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), + .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + + // Scheduler configuration + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), + .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), + .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), + + // Interface configuration + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .TX_CPL_ENABLE(PTP_TS_ENABLE), + .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), + .TX_TAG_WIDTH(TX_TAG_WIDTH), + .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), + .RX_RSS_ENABLE(RX_RSS_ENABLE), + .RX_HASH_ENABLE(RX_HASH_ENABLE), + .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .MAX_TX_SIZE(MAX_TX_SIZE), + .MAX_RX_SIZE(MAX_RX_SIZE), + .TX_RAM_SIZE(TX_RAM_SIZE), + .RX_RAM_SIZE(RX_RAM_SIZE), + + // Application block configuration + .APP_ID(APP_ID), + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + .APP_GPIO_IN_WIDTH(32), + .APP_GPIO_OUT_WIDTH(32), + + // AXI interface configuration (DMA) + .AXI_DATA_WIDTH(AXI_DATA_WIDTH), + .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), + .AXI_STRB_WIDTH(AXI_STRB_WIDTH), + .AXI_ID_WIDTH(AXI_ID_WIDTH), + + // DMA interface configuration + .DMA_IMM_ENABLE(DMA_IMM_ENABLE), + .DMA_IMM_WIDTH(DMA_IMM_WIDTH), + .DMA_LEN_WIDTH(DMA_LEN_WIDTH), + .DMA_TAG_WIDTH(DMA_TAG_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_PIPELINE(RAM_PIPELINE), + .AXI_DMA_MAX_BURST_LEN(AXI_DMA_MAX_BURST_LEN), + + // Interrupts + .IRQ_COUNT(IRQ_COUNT), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), + .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), + .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), + .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), + .RB_NEXT_PTR(RB_BASE_ADDR), + + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + + // Ethernet interface configuration + .AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .AXIS_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), + .AXIS_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .AXIS_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), + .AXIS_RX_USE_READY(0), + .AXIS_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), + .AXIS_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), + .AXIS_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), + .AXIS_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), + .AXIS_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), + + // Statistics counter subsystem + .STAT_ENABLE(STAT_ENABLE), + .STAT_DMA_ENABLE(STAT_DMA_ENABLE), + .STAT_AXI_ENABLE(STAT_AXI_ENABLE), + .STAT_INC_WIDTH(STAT_INC_WIDTH), + .STAT_ID_WIDTH(STAT_ID_WIDTH) +) +core_inst ( + .clk(clk_300mhz), + .rst(rst_300mhz), + + /* + * Interrupt outputs + */ + .irq(irq), + + /* + * AXI master interface (DMA) + */ + .m_axi_awid(m_axi_awid), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awlen(m_axi_awlen), + .m_axi_awsize(m_axi_awsize), + .m_axi_awburst(m_axi_awburst), + .m_axi_awlock(m_axi_awlock), + .m_axi_awcache(m_axi_awcache), + .m_axi_awprot(m_axi_awprot), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_awready(m_axi_awready), + .m_axi_wdata(m_axi_wdata), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wlast(m_axi_wlast), + .m_axi_wvalid(m_axi_wvalid), + .m_axi_wready(m_axi_wready), + .m_axi_bid(m_axi_bid), + .m_axi_bresp(m_axi_bresp), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_bready(m_axi_bready), + .m_axi_arid(m_axi_arid), + .m_axi_araddr(m_axi_araddr), + .m_axi_arlen(m_axi_arlen), + .m_axi_arsize(m_axi_arsize), + .m_axi_arburst(m_axi_arburst), + .m_axi_arlock(m_axi_arlock), + .m_axi_arcache(m_axi_arcache), + .m_axi_arprot(m_axi_arprot), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_arready(m_axi_arready), + .m_axi_rid(m_axi_rid), + .m_axi_rdata(m_axi_rdata), + .m_axi_rresp(m_axi_rresp), + .m_axi_rlast(m_axi_rlast), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_rready(m_axi_rready), + + /* + * AXI-Lite slave interface (control) + */ + .s_axil_ctrl_awaddr(s_axil_ctrl_awaddr), + .s_axil_ctrl_awprot(s_axil_ctrl_awprot), + .s_axil_ctrl_awvalid(s_axil_ctrl_awvalid), + .s_axil_ctrl_awready(s_axil_ctrl_awready), + .s_axil_ctrl_wdata(s_axil_ctrl_wdata), + .s_axil_ctrl_wstrb(s_axil_ctrl_wstrb), + .s_axil_ctrl_wvalid(s_axil_ctrl_wvalid), + .s_axil_ctrl_wready(s_axil_ctrl_wready), + .s_axil_ctrl_bresp(s_axil_ctrl_bresp), + .s_axil_ctrl_bvalid(s_axil_ctrl_bvalid), + .s_axil_ctrl_bready(s_axil_ctrl_bready), + .s_axil_ctrl_araddr(s_axil_ctrl_araddr), + .s_axil_ctrl_arprot(s_axil_ctrl_arprot), + .s_axil_ctrl_arvalid(s_axil_ctrl_arvalid), + .s_axil_ctrl_arready(s_axil_ctrl_arready), + .s_axil_ctrl_rdata(s_axil_ctrl_rdata), + .s_axil_ctrl_rresp(s_axil_ctrl_rresp), + .s_axil_ctrl_rvalid(s_axil_ctrl_rvalid), + .s_axil_ctrl_rready(s_axil_ctrl_rready), + + /* + * AXI-Lite slave interface (application control) + */ + .s_axil_app_ctrl_awaddr(s_axil_app_ctrl_awaddr), + .s_axil_app_ctrl_awprot(s_axil_app_ctrl_awprot), + .s_axil_app_ctrl_awvalid(s_axil_app_ctrl_awvalid), + .s_axil_app_ctrl_awready(s_axil_app_ctrl_awready), + .s_axil_app_ctrl_wdata(s_axil_app_ctrl_wdata), + .s_axil_app_ctrl_wstrb(s_axil_app_ctrl_wstrb), + .s_axil_app_ctrl_wvalid(s_axil_app_ctrl_wvalid), + .s_axil_app_ctrl_wready(s_axil_app_ctrl_wready), + .s_axil_app_ctrl_bresp(s_axil_app_ctrl_bresp), + .s_axil_app_ctrl_bvalid(s_axil_app_ctrl_bvalid), + .s_axil_app_ctrl_bready(s_axil_app_ctrl_bready), + .s_axil_app_ctrl_araddr(s_axil_app_ctrl_araddr), + .s_axil_app_ctrl_arprot(s_axil_app_ctrl_arprot), + .s_axil_app_ctrl_arvalid(s_axil_app_ctrl_arvalid), + .s_axil_app_ctrl_arready(s_axil_app_ctrl_arready), + .s_axil_app_ctrl_rdata(s_axil_app_ctrl_rdata), + .s_axil_app_ctrl_rresp(s_axil_app_ctrl_rresp), + .s_axil_app_ctrl_rvalid(s_axil_app_ctrl_rvalid), + .s_axil_app_ctrl_rready(s_axil_app_ctrl_rready), + + /* + * AXI-Lite master interface (passthrough for NIC control and status) + */ + .m_axil_csr_awaddr(axil_csr_awaddr), + .m_axil_csr_awprot(axil_csr_awprot), + .m_axil_csr_awvalid(axil_csr_awvalid), + .m_axil_csr_awready(axil_csr_awready), + .m_axil_csr_wdata(axil_csr_wdata), + .m_axil_csr_wstrb(axil_csr_wstrb), + .m_axil_csr_wvalid(axil_csr_wvalid), + .m_axil_csr_wready(axil_csr_wready), + .m_axil_csr_bresp(axil_csr_bresp), + .m_axil_csr_bvalid(axil_csr_bvalid), + .m_axil_csr_bready(axil_csr_bready), + .m_axil_csr_araddr(axil_csr_araddr), + .m_axil_csr_arprot(axil_csr_arprot), + .m_axil_csr_arvalid(axil_csr_arvalid), + .m_axil_csr_arready(axil_csr_arready), + .m_axil_csr_rdata(axil_csr_rdata), + .m_axil_csr_rresp(axil_csr_rresp), + .m_axil_csr_rvalid(axil_csr_rvalid), + .m_axil_csr_rready(axil_csr_rready), + + /* + * Control register interface + */ + .ctrl_reg_wr_addr(ctrl_reg_wr_addr), + .ctrl_reg_wr_data(ctrl_reg_wr_data), + .ctrl_reg_wr_strb(ctrl_reg_wr_strb), + .ctrl_reg_wr_en(ctrl_reg_wr_en), + .ctrl_reg_wr_wait(ctrl_reg_wr_wait), + .ctrl_reg_wr_ack(ctrl_reg_wr_ack), + .ctrl_reg_rd_addr(ctrl_reg_rd_addr), + .ctrl_reg_rd_en(ctrl_reg_rd_en), + .ctrl_reg_rd_data(ctrl_reg_rd_data), + .ctrl_reg_rd_wait(ctrl_reg_rd_wait), + .ctrl_reg_rd_ack(ctrl_reg_rd_ack), + + /* + * PTP clock + */ + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_sample_clk(ptp_sample_clk), + .ptp_pps(ptp_pps), + .ptp_pps_str(ptp_pps_str), + .ptp_ts_96(ptp_ts_96), + .ptp_ts_step(ptp_ts_step), + .ptp_sync_pps(ptp_sync_pps), + .ptp_sync_ts_96(ptp_sync_ts_96), + .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_perout_locked(ptp_perout_locked), + .ptp_perout_error(ptp_perout_error), + .ptp_perout_pulse(ptp_perout_pulse), + + /* + * Ethernet + */ + .tx_clk(eth_tx_clk), + .tx_rst(eth_tx_rst), + + .tx_ptp_clk(0), + .tx_ptp_rst(0), + .tx_ptp_ts_96(eth_tx_ptp_ts_96), + .tx_ptp_ts_step(eth_tx_ptp_ts_step), + + .m_axis_tx_tdata(axis_eth_tx_tdata), + .m_axis_tx_tkeep(axis_eth_tx_tkeep), + .m_axis_tx_tvalid(axis_eth_tx_tvalid), + .m_axis_tx_tready(axis_eth_tx_tready), + .m_axis_tx_tlast(axis_eth_tx_tlast), + .m_axis_tx_tuser(axis_eth_tx_tuser), + + .s_axis_tx_cpl_ts(axis_eth_tx_ptp_ts), + .s_axis_tx_cpl_tag(axis_eth_tx_ptp_ts_tag), + .s_axis_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), + .s_axis_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), + + .tx_status(eth_tx_status), + + .rx_clk(eth_rx_clk), + .rx_rst(eth_rx_rst), + + .rx_ptp_clk(0), + .rx_ptp_rst(0), + .rx_ptp_ts_96(eth_rx_ptp_ts_96), + .rx_ptp_ts_step(eth_rx_ptp_ts_step), + + .s_axis_rx_tdata(axis_eth_rx_tdata), + .s_axis_rx_tkeep(axis_eth_rx_tkeep), + .s_axis_rx_tvalid(axis_eth_rx_tvalid), + .s_axis_rx_tready(axis_eth_rx_tready), + .s_axis_rx_tlast(axis_eth_rx_tlast), + .s_axis_rx_tuser(axis_eth_rx_tuser), + + .rx_status(eth_rx_status), + + /* + * Statistics input + */ + .s_axis_stat_tdata(0), + .s_axis_stat_tid(0), + .s_axis_stat_tvalid(1'b0), + .s_axis_stat_tready(), + + /* + * GPIO + */ + .app_gpio_in(0), + .app_gpio_out(), + + /* + * JTAG + */ + .app_jtag_tdi(1'b0), + .app_jtag_tdo(), + .app_jtag_tms(1'b0), + .app_jtag_tck(1'b0) +); + +endmodule + +`resetall diff --git a/fpga/mqnic/ZCU102/fpga/rtl/sync_signal.v b/fpga/mqnic/ZCU102/fpga/rtl/sync_signal.v new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile new file mode 100644 index 000000000..942393614 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile @@ -0,0 +1,411 @@ +# Copyright 2020-2021, The Regents of the University of California. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +# OF SUCH DAMAGE. +# +# The views and conclusions contained in the software and documentation are those +# of the authors and should not be interpreted as representing official policies, +# either expressed or implied, of The Regents of the University of California. + +TOPLEVEL_LANG = verilog + +SIM ?= icarus +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = fpga_core +TOPLEVEL = $(DUT) +MODULE = test_$(DUT) +VERILOG_SOURCES += ../../rtl/$(DUT).v +VERILOG_SOURCES += ../../rtl/common/mqnic_core_axi.v +VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v +VERILOG_SOURCES += ../../rtl/common/cpl_write.v +VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v +VERILOG_SOURCES += ../../rtl/common/desc_fetch.v +VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v +VERILOG_SOURCES += ../../rtl/common/event_mux.v +VERILOG_SOURCES += ../../rtl/common/queue_manager.v +VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v +VERILOG_SOURCES += ../../rtl/common/tx_engine.v +VERILOG_SOURCES += ../../rtl/common/rx_engine.v +VERILOG_SOURCES += ../../rtl/common/tx_checksum.v +VERILOG_SOURCES += ../../rtl/common/rx_hash.v +VERILOG_SOURCES += ../../rtl/common/rx_checksum.v +VERILOG_SOURCES += ../../rtl/common/rb_drp.v +VERILOG_SOURCES += ../../rtl/common/stats_counter.v +VERILOG_SOURCES += ../../rtl/common/stats_collect.v +VERILOG_SOURCES += ../../rtl/common/stats_dma_if_axi.v +VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v +VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v +VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v +VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v +VERILOG_SOURCES += ../../rtl/common/tdma_ber.v +VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v +VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v +VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v +VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v +VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi_rd.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi_wr.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v + +# module parameters + +# Structural configuration +export PARAM_IF_COUNT ?= 2 +export PARAM_PORTS_PER_IF ?= 1 +export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF) +export PARAM_PORT_MASK ?= 0 + +# PTP configuration +export PARAM_PTP_CLK_PERIOD_NS_NUM = 32 +export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5 +export PARAM_PTP_CLOCK_PIPELINE ?= 0 +export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0 +export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1 +export PARAM_PTP_PORT_CDC_PIPELINE ?= 0 +export PARAM_PTP_PEROUT_ENABLE ?= 1 +export PARAM_PTP_PEROUT_COUNT ?= 1 + +# Queue manager configuration +export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32 +export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32 +export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32 +export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE) +export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE) +export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 2 +export PARAM_TX_QUEUE_INDEX_WIDTH ?= 5 +export PARAM_RX_QUEUE_INDEX_WIDTH ?= 5 +export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH) +export PARAM_RX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_RX_QUEUE_INDEX_WIDTH) +export PARAM_EVENT_QUEUE_PIPELINE ?= 3 +export PARAM_TX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") +export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") +export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE) +export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE) + +# TX and RX engine configuration +export PARAM_TX_DESC_TABLE_SIZE ?= 32 +export PARAM_RX_DESC_TABLE_SIZE ?= 32 + +# Scheduler configuration +export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE) +export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE) +export PARAM_TDMA_INDEX_WIDTH ?= 6 + +# Interface configuration +export PARAM_PTP_TS_ENABLE ?= 1 +export PARAM_TX_CPL_FIFO_DEPTH ?= 32 +export PARAM_TX_CHECKSUM_ENABLE ?= 1 +export PARAM_RX_RSS_ENABLE ?= 1 +export PARAM_RX_HASH_ENABLE ?= 1 +export PARAM_RX_CHECKSUM_ENABLE ?= 1 +export PARAM_TX_FIFO_DEPTH ?= 32768 +export PARAM_RX_FIFO_DEPTH ?= 32768 +export PARAM_MAX_TX_SIZE ?= 9214 +export PARAM_MAX_RX_SIZE ?= 9214 +export PARAM_TX_RAM_SIZE ?= 32768 +export PARAM_RX_RAM_SIZE ?= 32768 + +# Application block configuration +export PARAM_APP_ID ?= $(shell echo $$((0x00000000)) ) +export PARAM_APP_ENABLE ?= 0 +export PARAM_APP_CTRL_ENABLE ?= 1 +export PARAM_APP_DMA_ENABLE ?= 1 +export PARAM_APP_AXIS_DIRECT_ENABLE ?= 1 +export PARAM_APP_AXIS_SYNC_ENABLE ?= 1 +export PARAM_APP_AXIS_IF_ENABLE ?= 1 +export PARAM_APP_STAT_ENABLE ?= 1 + +# AXI DMA interface configuration +export PARAM_AXI_DATA_WIDTH ?= 128 +export PARAM_AXI_ADDR_WIDTH ?= 40 +export PARAM_AXI_ID_WIDTH ?= 4 + +# DMA interface configuration +export PARAM_DMA_IMM_ENABLE ?= 0 +export PARAM_DMA_IMM_WIDTH ?= 32 +export PARAM_DMA_LEN_WIDTH ?= 16 +export PARAM_DMA_TAG_WIDTH ?= 16 +export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())") +export PARAM_RAM_PIPELINE ?= 2 +export PARAM_AXI_DMA_MAX_BURST_LEN ?= 16 + +# AXI lite interface configuration (control) +export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32 +export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24 + +# AXI lite interface configuration (application control) +export PARAM_AXIL_APP_CTRL_DATA_WIDTH ?= $(PARAM_AXIL_CTRL_DATA_WIDTH) +export PARAM_AXIL_APP_CTRL_ADDR_WIDTH ?= 24 + +# Ethernet interface configuration +export PARAM_AXIS_ETH_TX_PIPELINE ?= 0 +export PARAM_AXIS_ETH_TX_FIFO_PIPELINE ?= 2 +export PARAM_AXIS_ETH_TX_TS_PIPELINE ?= 0 +export PARAM_AXIS_ETH_RX_PIPELINE ?= 0 +export PARAM_AXIS_ETH_RX_FIFO_PIPELINE ?= 2 + +# Statistics counter subsystem +export PARAM_STAT_ENABLE ?= 1 +export PARAM_STAT_DMA_ENABLE ?= 1 +export PARAM_STAT_AXI_ENABLE ?= 1 +export PARAM_STAT_INC_WIDTH ?= 24 +export PARAM_STAT_ID_WIDTH ?= 12 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT) + COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF) + COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF) + COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) + COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK) + COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT) + COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_INDEX_WIDTH=$(PARAM_EVENT_QUEUE_INDEX_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).RX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) + COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) + COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) + COMPILE_ARGS += -P $(TOPLEVEL).MAX_TX_SIZE=$(PARAM_MAX_TX_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_ID=$(PARAM_APP_ID) + COMPILE_ARGS += -P $(TOPLEVEL).APP_ENABLE=$(PARAM_APP_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).AXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).AXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).AXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).AXI_DMA_MAX_BURST_LEN=$(PARAM_AXI_DMA_MAX_BURST_LEN) + COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE) + COMPILE_ARGS += -P $(TOPLEVEL).STAT_ENABLE=$(PARAM_STAT_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).STAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).STAT_AXI_ENABLE=$(PARAM_STAT_AXI_ENABLE) + COMPILE_ARGS += -P $(TOPLEVEL).STAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH) + COMPILE_ARGS += -P $(TOPLEVEL).STAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH) + + ifeq ($(WAVES), 1) + VERILOG_SOURCES += iverilog_dump.v + COMPILE_ARGS += -s iverilog_dump + endif +else ifeq ($(SIM), verilator) + COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH + + COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT) + COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF) + COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF) + COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK) + COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM) + COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM) + COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE) + COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE) + COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK) + COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE) + COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE) + COMPILE_ARGS += -GPTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT) + COMPILE_ARGS += -GEVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -GTX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -GRX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -GTX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -GRX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE) + COMPILE_ARGS += -GEVENT_QUEUE_INDEX_WIDTH=$(PARAM_EVENT_QUEUE_INDEX_WIDTH) + COMPILE_ARGS += -GTX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH) + COMPILE_ARGS += -GRX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH) + COMPILE_ARGS += -GTX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH) + COMPILE_ARGS += -GRX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH) + COMPILE_ARGS += -GEVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE) + COMPILE_ARGS += -GTX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE) + COMPILE_ARGS += -GRX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE) + COMPILE_ARGS += -GTX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE) + COMPILE_ARGS += -GRX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE) + COMPILE_ARGS += -GTX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE) + COMPILE_ARGS += -GRX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE) + COMPILE_ARGS += -GTX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE) + COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE) + COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH) + COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE) + COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH) + COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE) + COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE) + COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE) + COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE) + COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) + COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) + COMPILE_ARGS += -GMAX_TX_SIZE=$(PARAM_MAX_TX_SIZE) + COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE) + COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE) + COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE) + COMPILE_ARGS += -GAPP_ID=$(PARAM_APP_ID) + COMPILE_ARGS += -GAPP_ENABLE=$(PARAM_APP_ENABLE) + COMPILE_ARGS += -GAPP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE) + COMPILE_ARGS += -GAPP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE) + COMPILE_ARGS += -GAPP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE) + COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE) + COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE) + COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE) + COMPILE_ARGS += -GAXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH) + COMPILE_ARGS += -GAXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH) + COMPILE_ARGS += -GAXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH) + COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE) + COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH) + COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH) + COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH) + COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH) + COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE) + COMPILE_ARGS += -GAXI_DMA_MAX_BURST_LEN=$(PARAM_AXI_DMA_MAX_BURST_LEN) + COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH) + COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH) + COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH) + COMPILE_ARGS += -GAXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH) + COMPILE_ARGS += -GAXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE) + COMPILE_ARGS += -GAXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE) + COMPILE_ARGS += -GAXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE) + COMPILE_ARGS += -GAXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE) + COMPILE_ARGS += -GAXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE) + COMPILE_ARGS += -GSTAT_ENABLE=$(PARAM_STAT_ENABLE) + COMPILE_ARGS += -GSTAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE) + COMPILE_ARGS += -GSTAT_AXI_ENABLE=$(PARAM_STAT_AXI_ENABLE) + COMPILE_ARGS += -GSTAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH) + COMPILE_ARGS += -GSTAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim + +iverilog_dump.v: + echo 'module iverilog_dump();' > $@ + echo 'initial begin' >> $@ + echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ + echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ + echo 'end' >> $@ + echo 'endmodule' >> $@ + +clean:: + @rm -rf iverilog_dump.v + @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/mqnic.py b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/mqnic.py new file mode 120000 index 000000000..dfa8522e7 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/mqnic.py @@ -0,0 +1 @@ +../../../../../common/tb/mqnic.py \ No newline at end of file diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py new file mode 100644 index 000000000..31aa7dea0 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py @@ -0,0 +1,586 @@ +""" + +Copyright 2020-2021, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +""" + +import logging +import os +import sys + +import scapy.utils +from scapy.layers.l2 import Ether +from scapy.layers.inet import IP, UDP + +import cocotb_test.simulator + +import cocotb +from cocotb.log import SimLog +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge + +from cocotbext.axi import AddressSpace +from cocotbext.axi import AxiLiteMaster, AxiLiteBus +from cocotbext.axi import AxiSlave, AxiBus +from cocotbext.eth import XgmiiSource, XgmiiSink + +try: + import mqnic +except ImportError: + # attempt import from current directory + sys.path.insert(0, os.path.join(os.path.dirname(__file__))) + try: + import mqnic + finally: + del sys.path[0] + + +class TB(object): + def __init__(self, dut): + self.dut = dut + + self.log = SimLog("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk_300mhz, 3332, units="ps").start()) + + # AXI + self.address_space = AddressSpace() + self.pool = self.address_space.create_pool(0, 0x8000_0000) + + self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil_ctrl"), dut.clk_300mhz, dut.rst_300mhz) + self.address_space.register_region(self.axil_master, 0x10_0000_0000) + self.hw_regs = self.address_space.create_window(0x10_0000_0000, self.axil_master.size) + + self.axi_slave = AxiSlave(AxiBus.from_prefix(dut, "m_axi"), dut.clk_300mhz, dut.rst_300mhz, self.address_space) + + self.driver = mqnic.Driver() + + cocotb.start_soon(Clock(dut.ptp_clk, 6.4, units="ns").start()) + dut.ptp_rst.setimmediatevalue(0) + cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start()) + + # Ethernet + cocotb.start_soon(Clock(dut.sfp0_rx_clk, 6.4, units="ns").start()) + self.sfp0_source = XgmiiSource(dut.sfp0_rxd, dut.sfp0_rxc, dut.sfp0_rx_clk, dut.sfp0_rx_rst) + cocotb.start_soon(Clock(dut.sfp0_tx_clk, 6.4, units="ns").start()) + self.sfp0_sink = XgmiiSink(dut.sfp0_txd, dut.sfp0_txc, dut.sfp0_tx_clk, dut.sfp0_tx_rst) + + cocotb.start_soon(Clock(dut.sfp1_rx_clk, 6.4, units="ns").start()) + self.sfp1_source = XgmiiSource(dut.sfp1_rxd, dut.sfp1_rxc, dut.sfp1_rx_clk, dut.sfp1_rx_rst) + cocotb.start_soon(Clock(dut.sfp1_tx_clk, 6.4, units="ns").start()) + self.sfp1_sink = XgmiiSink(dut.sfp1_txd, dut.sfp1_txc, dut.sfp1_tx_clk, dut.sfp1_tx_rst) + + cocotb.start_soon(Clock(dut.sfp2_rx_clk, 6.4, units="ns").start()) + self.sfp2_source = XgmiiSource(dut.sfp2_rxd, dut.sfp2_rxc, dut.sfp2_rx_clk, dut.sfp2_rx_rst) + cocotb.start_soon(Clock(dut.sfp2_tx_clk, 6.4, units="ns").start()) + self.sfp2_sink = XgmiiSink(dut.sfp2_txd, dut.sfp2_txc, dut.sfp2_tx_clk, dut.sfp2_tx_rst) + + cocotb.start_soon(Clock(dut.sfp3_rx_clk, 6.4, units="ns").start()) + self.sfp3_source = XgmiiSource(dut.sfp3_rxd, dut.sfp3_rxc, dut.sfp3_rx_clk, dut.sfp3_rx_rst) + cocotb.start_soon(Clock(dut.sfp3_tx_clk, 6.4, units="ns").start()) + self.sfp3_sink = XgmiiSink(dut.sfp3_txd, dut.sfp3_txc, dut.sfp3_tx_clk, dut.sfp3_tx_rst) + + dut.sfp0_rx_status.setimmediatevalue(1) + dut.sfp1_rx_status.setimmediatevalue(1) + dut.sfp2_rx_status.setimmediatevalue(1) + dut.sfp3_rx_status.setimmediatevalue(1) + + cocotb.start_soon(Clock(dut.sfp_drp_clk, 8, units="ns").start()) + dut.sfp_drp_rst.setimmediatevalue(0) + dut.sfp_drp_do.setimmediatevalue(0) + dut.sfp_drp_rdy.setimmediatevalue(0) + + dut.sfp0_rx_error_count.setimmediatevalue(0) + dut.sfp1_rx_error_count.setimmediatevalue(0) + dut.sfp2_rx_error_count.setimmediatevalue(0) + dut.sfp3_rx_error_count.setimmediatevalue(0) + + dut.btnu.setimmediatevalue(0) + dut.btnl.setimmediatevalue(0) + dut.btnd.setimmediatevalue(0) + dut.btnr.setimmediatevalue(0) + dut.btnc.setimmediatevalue(0) + dut.sw.setimmediatevalue(0) + + self.loopback_enable = False + cocotb.start_soon(self._run_loopback()) + + async def init(self): + + self.dut.rst_300mhz.setimmediatevalue(0) + self.dut.ptp_rst.setimmediatevalue(0) + self.dut.sfp0_rx_rst.setimmediatevalue(0) + self.dut.sfp0_tx_rst.setimmediatevalue(0) + self.dut.sfp1_rx_rst.setimmediatevalue(0) + self.dut.sfp1_tx_rst.setimmediatevalue(0) + self.dut.sfp2_rx_rst.setimmediatevalue(0) + self.dut.sfp2_tx_rst.setimmediatevalue(0) + self.dut.sfp3_rx_rst.setimmediatevalue(0) + self.dut.sfp3_tx_rst.setimmediatevalue(0) + + await RisingEdge(self.dut.clk_300mhz) + await RisingEdge(self.dut.clk_300mhz) + + self.dut.rst_300mhz.value = 1 + self.dut.ptp_rst.setimmediatevalue(1) + self.dut.sfp0_rx_rst.setimmediatevalue(1) + self.dut.sfp0_tx_rst.setimmediatevalue(1) + self.dut.sfp1_rx_rst.setimmediatevalue(1) + self.dut.sfp1_tx_rst.setimmediatevalue(1) + self.dut.sfp2_rx_rst.setimmediatevalue(1) + self.dut.sfp2_tx_rst.setimmediatevalue(1) + self.dut.sfp3_rx_rst.setimmediatevalue(1) + self.dut.sfp3_tx_rst.setimmediatevalue(1) + + await RisingEdge(self.dut.clk_300mhz) + await RisingEdge(self.dut.clk_300mhz) + + self.dut.rst_300mhz.value = 0 + self.dut.ptp_rst.setimmediatevalue(0) + self.dut.sfp0_rx_rst.setimmediatevalue(0) + self.dut.sfp0_tx_rst.setimmediatevalue(0) + self.dut.sfp1_rx_rst.setimmediatevalue(0) + self.dut.sfp1_tx_rst.setimmediatevalue(0) + self.dut.sfp2_rx_rst.setimmediatevalue(0) + self.dut.sfp2_tx_rst.setimmediatevalue(0) + self.dut.sfp3_rx_rst.setimmediatevalue(0) + self.dut.sfp3_tx_rst.setimmediatevalue(0) + + async def _run_loopback(self): + while True: + await RisingEdge(self.dut.clk_300mhz) + + if self.loopback_enable: + if not self.sfp0_sink.empty(): + await self.sfp0_source.send(await self.sfp0_sink.recv()) + if not self.sfp1_sink.empty(): + await self.sfp1_source.send(await self.sfp1_sink.recv()) + if not self.sfp2_sink.empty(): + await self.sfp2_source.send(await self.sfp2_sink.recv()) + if not self.sfp3_sink.empty(): + await self.sfp3_source.send(await self.sfp3_sink.recv()) + + +@cocotb.test() +async def run_test_nic(dut): + + tb = TB(dut) + + await tb.init() + + tb.log.info("Init driver") + await tb.driver.init_axi_dev(tb.pool, tb.hw_regs, irq=dut.irq) + await tb.driver.interfaces[0].open() + # await tb.driver.interfaces[1].open() + + # enable queues + tb.log.info("Enable queues") + await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) + for k in range(tb.driver.interfaces[0].tx_queue_count): + await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003) + + # wait for all writes to complete + await tb.driver.hw_regs.read_dword(0) + tb.log.info("Init complete") + + tb.log.info("Send and receive single packet") + + data = bytearray([x % 256 for x in range(1024)]) + + await tb.driver.interfaces[0].start_xmit(data, 0) + + pkt = await tb.sfp0_sink.recv() + tb.log.info("Packet: %s", pkt) + + await tb.sfp0_source.send(pkt) + + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + # await tb.driver.interfaces[1].start_xmit(data, 0) + + # pkt = await tb.sfp1_sink.recv() + # tb.log.info("Packet: %s", pkt) + + # await tb.sfp1_source.send(pkt) + + # pkt = await tb.driver.interfaces[1].recv() + + # tb.log.info("Packet: %s", pkt) + # assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + tb.log.info("RX and TX checksum tests") + + payload = bytes([x % 256 for x in range(256)]) + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') + ip = IP(src='192.168.1.100', dst='192.168.1.101') + udp = UDP(sport=1, dport=2) + test_pkt = eth / ip / udp / payload + + test_pkt2 = test_pkt.copy() + test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) + + await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) + + pkt = await tb.sfp0_sink.recv() + tb.log.info("Packet: %s", pkt) + + await tb.sfp0_source.send(pkt) + + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + assert Ether(pkt.data).build() == test_pkt.build() + + tb.log.info("Queue mapping offset test") + + data = bytearray([x % 256 for x in range(1024)]) + + tb.loopback_enable = True + + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k) + + await tb.driver.interfaces[0].start_xmit(data, 0) + + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + assert pkt.queue == k + + tb.loopback_enable = False + + await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0) + + tb.log.info("Queue mapping RSS mask test") + + await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + + tb.loopback_enable = True + + queues = set() + + for k in range(64): + payload = bytes([x % 256 for x in range(256)]) + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') + ip = IP(src='192.168.1.100', dst='192.168.1.101') + udp = UDP(sport=1, dport=k+0) + test_pkt = eth / ip / udp / payload + + test_pkt2 = test_pkt.copy() + test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) + + await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) + + for k in range(64): + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + queues.add(pkt.queue) + + assert len(queues) == 4 + + tb.loopback_enable = False + + await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0) + + tb.log.info("Multiple small packets") + + count = 64 + + pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] + + tb.loopback_enable = True + + for p in pkts: + await tb.driver.interfaces[0].start_xmit(p, 0) + + for k in range(count): + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.data == pkts[k] + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + tb.loopback_enable = False + + tb.log.info("Multiple large packets") + + count = 64 + + pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] + + tb.loopback_enable = True + + for p in pkts: + await tb.driver.interfaces[0].start_xmit(p, 0) + + for k in range(count): + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.data == pkts[k] + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + tb.loopback_enable = False + + await RisingEdge(dut.clk_300mhz) + await RisingEdge(dut.clk_300mhz) + + +# cocotb-test + +tests_dir = os.path.dirname(__file__) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app')) +axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl')) +axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) +eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) +pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl')) + + +def test_fpga_core(request): + dut = "fpga_core" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, f"{dut}.v"), + os.path.join(rtl_dir, "common", "mqnic_core_axi.v"), + os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_interface.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_port_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_port_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), + os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), + os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"), + os.path.join(rtl_dir, "common", "mqnic_ptp.v"), + os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), + os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), + os.path.join(rtl_dir, "common", "cpl_write.v"), + os.path.join(rtl_dir, "common", "cpl_op_mux.v"), + os.path.join(rtl_dir, "common", "desc_fetch.v"), + os.path.join(rtl_dir, "common", "desc_op_mux.v"), + os.path.join(rtl_dir, "common", "event_mux.v"), + os.path.join(rtl_dir, "common", "queue_manager.v"), + os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), + os.path.join(rtl_dir, "common", "tx_engine.v"), + os.path.join(rtl_dir, "common", "rx_engine.v"), + os.path.join(rtl_dir, "common", "tx_checksum.v"), + os.path.join(rtl_dir, "common", "rx_hash.v"), + os.path.join(rtl_dir, "common", "rx_checksum.v"), + os.path.join(rtl_dir, "common", "rb_drp.v"), + os.path.join(rtl_dir, "common", "stats_counter.v"), + os.path.join(rtl_dir, "common", "stats_collect.v"), + os.path.join(rtl_dir, "common", "stats_dma_if_axi.v"), + os.path.join(rtl_dir, "common", "stats_dma_latency.v"), + os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), + os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), + os.path.join(rtl_dir, "common", "tdma_scheduler.v"), + os.path.join(rtl_dir, "common", "tdma_ber.v"), + os.path.join(rtl_dir, "common", "tdma_ber_ch.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), + os.path.join(eth_rtl_dir, "lfsr.v"), + os.path.join(eth_rtl_dir, "ptp_clock.v"), + os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_perout.v"), + os.path.join(axi_rtl_dir, "axil_interconnect.v"), + os.path.join(axi_rtl_dir, "axil_crossbar.v"), + os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), + os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"), + os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"), + os.path.join(axi_rtl_dir, "axil_reg_if.v"), + os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"), + os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"), + os.path.join(axi_rtl_dir, "axil_register_rd.v"), + os.path.join(axi_rtl_dir, "axil_register_wr.v"), + os.path.join(axi_rtl_dir, "arbiter.v"), + os.path.join(axi_rtl_dir, "priority_encoder.v"), + os.path.join(axis_rtl_dir, "axis_adapter.v"), + os.path.join(axis_rtl_dir, "axis_arb_mux.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), + os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), + os.path.join(axis_rtl_dir, "axis_register.v"), + os.path.join(pcie_rtl_dir, "dma_if_axi.v"), + os.path.join(pcie_rtl_dir, "dma_if_axi_rd.v"), + os.path.join(pcie_rtl_dir, "dma_if_axi_wr.v"), + os.path.join(pcie_rtl_dir, "dma_if_mux.v"), + os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"), + os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"), + os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"), + os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"), + os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"), + os.path.join(pcie_rtl_dir, "dma_psdpram.v"), + os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"), + os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"), + os.path.join(pcie_rtl_dir, "pulse_merge.v"), + ] + + parameters = {} + + # Structural configuration + parameters['IF_COUNT'] = 2 + parameters['PORTS_PER_IF'] = 1 + parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] + parameters['PORT_MASK'] = 0 + + # PTP configuration + parameters['PTP_CLK_PERIOD_NS_NUM'] = 32 + parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5 + parameters['PTP_CLOCK_PIPELINE'] = 0 + parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 + parameters['PTP_USE_SAMPLE_CLOCK'] = 1 + parameters['PTP_PORT_CDC_PIPELINE'] = 0 + parameters['PTP_PEROUT_ENABLE'] = 1 + parameters['PTP_PEROUT_COUNT'] = 1 + + # Queue manager configuration + parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 + parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 + parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 + parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] + parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] + parameters['EVENT_QUEUE_INDEX_WIDTH'] = 2 + parameters['TX_QUEUE_INDEX_WIDTH'] = 5 + parameters['RX_QUEUE_INDEX_WIDTH'] = 5 + parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] + parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] + parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) + parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) + parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] + parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + + # TX and RX engine configuration + parameters['TX_DESC_TABLE_SIZE'] = 32 + parameters['RX_DESC_TABLE_SIZE'] = 32 + + # Scheduler configuration + parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] + parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] + parameters['TDMA_INDEX_WIDTH'] = 6 + + # Interface configuration + parameters['PTP_TS_ENABLE'] = 1 + parameters['TX_CPL_FIFO_DEPTH'] = 32 + parameters['TX_CHECKSUM_ENABLE'] = 1 + parameters['RX_RSS_ENABLE'] = 1 + parameters['RX_HASH_ENABLE'] = 1 + parameters['RX_CHECKSUM_ENABLE'] = 1 + parameters['TX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 32768 + parameters['MAX_TX_SIZE'] = 9214 + parameters['MAX_RX_SIZE'] = 9214 + parameters['TX_RAM_SIZE'] = 32768 + parameters['RX_RAM_SIZE'] = 32768 + + # Application block configuration + parameters['APP_ID'] = 0x00000000 + parameters['APP_ENABLE'] = 0 + parameters['APP_CTRL_ENABLE'] = 1 + parameters['APP_DMA_ENABLE'] = 1 + parameters['APP_AXIS_DIRECT_ENABLE'] = 1 + parameters['APP_AXIS_SYNC_ENABLE'] = 1 + parameters['APP_AXIS_IF_ENABLE'] = 1 + parameters['APP_STAT_ENABLE'] = 1 + + # AXI DMA interface configuration + parameters['AXI_DATA_WIDTH'] = 128 + parameters['AXI_ADDR_WIDTH'] = 40 + parameters['AXI_ID_WIDTH'] = 4 + + # DMA interface configuration + parameters['DMA_IMM_ENABLE'] = 0 + parameters['DMA_IMM_WIDTH'] = 32 + parameters['DMA_LEN_WIDTH'] = 16 + parameters['DMA_TAG_WIDTH'] = 16 + parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length() + parameters['RAM_PIPELINE'] = 2 + parameters['AXI_DMA_MAX_BURST_LEN'] = 16 + + # AXI lite interface configuration (control) + parameters['AXIL_CTRL_DATA_WIDTH'] = 32 + parameters['AXIL_CTRL_ADDR_WIDTH'] = 24 + + # AXI lite interface configuration (application control) + parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH'] + parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24 + + # Ethernet interface configuration + parameters['AXIS_ETH_TX_PIPELINE'] = 0 + parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 2 + parameters['AXIS_ETH_TX_TS_PIPELINE'] = 0 + parameters['AXIS_ETH_RX_PIPELINE'] = 0 + parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 2 + + # Statistics counter subsystem + parameters['STAT_ENABLE'] = 1 + parameters['STAT_DMA_ENABLE'] = 1 + parameters['STAT_AXI_ENABLE'] = 1 + parameters['STAT_INC_WIDTH'] = 24 + parameters['STAT_ID_WIDTH'] = 12 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + )